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netxen: download firmware in pci probe
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sky2.c
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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
bcc52894 54#define DRV_VERSION "1.21"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
f4331a6d
SH		 79#define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
cd28ab6a 101static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
cd28ab6a
SH		 139 { 0 }
140};
793b883e 141
cd28ab6a
SH		 142MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144/* Avoid conditionals by using array */
145static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 148
92f965e8
SH		 149/* This driver supports yukon2 chipset only */
150static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
93745494 153 "Extreme", /* 0xb5 */
92f965e8
SH		 154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
05745c4a 156 "FE+", /* 0xb8 */
c63eddb2 157 "Supreme", /* 0xb9 */
793b883e
SH		 158};
159
d1b139c0
SH		 160static void sky2_set_multicast(struct net_device *dev);
161
af043aa5 162/* Access to PHY via serial interconnect */
ef743d33 163static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 164{
165 int i;
166
167 gma_write16(hw, port, GM_SMI_DATA, val);
168 gma_write16(hw, port, GM_SMI_CTRL,
169 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
170
171 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 172 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
173 if (ctrl == 0xffff)
174 goto io_error;
175
176 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 177 return 0;
af043aa5
SH		 178
179 udelay(10);
cd28ab6a 180 }
ef743d33 181
af043aa5 182 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 183 return -ETIMEDOUT;
af043aa5
SH		 184
185io_error:
186 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
187 return -EIO;
cd28ab6a
SH		 188}
189
ef743d33 190static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 191{
192 int i;
193
793b883e 194 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 195 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
196
197 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 198 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
199 if (ctrl == 0xffff)
200 goto io_error;
201
202 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 203 *val = gma_read16(hw, port, GM_SMI_DATA);
204 return 0;
205 }
206
af043aa5 207 udelay(10);
cd28ab6a
SH		 208 }
209
af043aa5 210 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 211 return -ETIMEDOUT;
af043aa5
SH		 212io_error:
213 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
214 return -EIO;
ef743d33
SH		 215}
216
af043aa5 217static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 218{
219 u16 v;
af043aa5 220 __gm_phy_read(hw, port, reg, &v);
ef743d33 221 return v;
cd28ab6a
SH		 222}
223
5afa0a9c 224
ae306cca
SH		 225static void sky2_power_on(struct sky2_hw *hw)
226{
227 /* switch power to VCC (WA for VAUX problem) */
228 sky2_write8(hw, B0_POWER_CTRL,
229 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 230
ae306cca
SH		 231 /* disable Core Clock Division, */
232 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 233
ae306cca
SH		 234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240 else
241 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 242
ea76e635 243 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 244 u32 reg;
5afa0a9c 245
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 247
b32f40c4 248 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 249 /* set all bits to 0 except bits 15..12 and 8 */
250 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 251 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 252
b32f40c4 253 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 254 /* set all bits to 0 except bits 28 & 27 */
255 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 256 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 257
b32f40c4 258 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 259
260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 reg = sky2_read32(hw, B2_GP_IO);
262 reg |= GLB_GPIO_STAT_RACE_DIS;
263 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 264
265 sky2_read32(hw, B2_GP_IO);
5afa0a9c 266 }
ae306cca 267}
5afa0a9c 268
ae306cca
SH		 269static void sky2_power_aux(struct sky2_hw *hw)
270{
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
280 /* switch power to VAUX */
281 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 285}
286
d3bcfbeb 287static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 288{
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 293
cd28ab6a
SH		 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302}
303
16ad91e1
SH		 304/* flow control to advertise bits */
305static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310};
311
312/* flow control to advertise bits when using 1000BaseX */
313static const u16 fiber_fc_adv[] = {
df3fe1f3 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 318};
319
320/* flow control to GMA disable bits */
321static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326};
327
328
cd28ab6a
SH		 329static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330{
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 333
ea76e635
SH		 334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 339 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
53419c68 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 343 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 344 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
53419c68
SH		 347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 354 if (sky2_is_copper(hw)) {
05745c4a 355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
cd28ab6a
SH		 368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
53419c68 375 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 376 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 377 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 378 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
cd28ab6a
SH		 383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 388 }
cd28ab6a 389
b89165f2
SH		 390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
ea76e635 393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 395
b89165f2
SH		 396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 411 }
b89165f2
SH		 412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 414 }
415
7800fddc 416 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
2eaba1a2 419 reg = 0;
cd28ab6a
SH		 420
421 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 422 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
709c6e7b 435
16ad91e1 436 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 442
16ad91e1 443 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 444 }
cd28ab6a
SH		 445
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 } else {
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
451
2eaba1a2
SH		 452 /* Disable auto update for duplex flow control and speed */
453 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 454
455 switch (sky2->speed) {
456 case SPEED_1000:
457 ctrl |= PHY_CT_SP1000;
2eaba1a2 458 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 459 break;
460 case SPEED_100:
461 ctrl |= PHY_CT_SP100;
2eaba1a2 462 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 463 break;
464 }
465
2eaba1a2
SH		 466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
2eaba1a2 471
2eaba1a2 472
16ad91e1 473 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 474
475 /* Forward pause packets to GMAC? */
16ad91e1 476 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
478 else
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 480 }
481
2eaba1a2
SH		 482 gma_write16(hw, port, GM_GP_CTRL, reg);
483
05745c4a 484 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 485 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
486
487 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
488 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
489
490 /* Setup Phy LED's */
491 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
492 ledover = 0;
493
494 switch (hw->chip_id) {
495 case CHIP_ID_YUKON_FE:
496 /* on 88E3082 these bits are at 11..9 (shifted left) */
497 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
498
499 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
500
501 /* delete ACT LED control bits */
502 ctrl &= ~PHY_M_FELP_LED1_MSK;
503 /* change ACT LED control to blink mode */
504 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
506 break;
507
05745c4a
SH		 508 case CHIP_ID_YUKON_FE_P:
509 /* Enable Link Partner Next Page */
510 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
511 ctrl |= PHY_M_PC_ENA_LIP_NP;
512
513 /* disable Energy Detect and enable scrambler */
514 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
516
517 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
518 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
519 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
520 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
521
522 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
523 break;
524
cd28ab6a 525 case CHIP_ID_YUKON_XL:
793b883e 526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 527
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
530
531 /* set LED Function Control register */
ed6d32c7
SH		 532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 537
538 /* set Polarity Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 540 (PHY_M_POLC_LS1_P_MIX(4) |
541 PHY_M_POLC_IS0_P_MIX(4) |
542 PHY_M_POLC_LOS_CTRL(2) |
543 PHY_M_POLC_INIT_CTRL(2) |
544 PHY_M_POLC_STA1_CTRL(2) |
545 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 546
547 /* restore page register */
793b883e 548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 549 break;
93745494 550
ed6d32c7 551 case CHIP_ID_YUKON_EC_U:
93745494 552 case CHIP_ID_YUKON_EX:
ed4d4161 553 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 554 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
555
556 /* select page 3 to access LED control register */
557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
558
559 /* set LED Function Control register */
560 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
561 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
562 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
563 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
564 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
565
566 /* set Blink Rate in LED Timer Control Register */
567 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
568 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
569 /* restore page register */
570 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
571 break;
cd28ab6a
SH		 572
573 default:
574 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
575 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 576
cd28ab6a 577 /* turn off the Rx LED (LED_RX) */
a84d0a3d 578 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 579 }
580
9467a8fc
SH		 581 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
582 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 583 /* apply fixes in PHY AFE */
ed6d32c7
SH		 584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
585
977bdf06 586 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 587 gm_phy_write(hw, port, 0x18, 0xaa99);
588 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 589
977bdf06 590 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 591 gm_phy_write(hw, port, 0x18, 0xa204);
592 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 593
594 /* set page register to 0 */
9467a8fc 595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 596 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
597 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
598 /* apply workaround for integrated resistors calibration */
599 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
600 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 601 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 602 /* no effect on Yukon-XL */
977bdf06 603 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 604
977bdf06
SH		 605 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
606 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 607 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 608 }
cd28ab6a 609
977bdf06
SH		 610 if (ledover)
611 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
612
613 }
2eaba1a2 614
d571b694 615 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 616 if (sky2->autoneg == AUTONEG_ENABLE)
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
618 else
619 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
620}
621
d3bcfbeb
SH		 622static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
623{
624 u32 reg1;
ff35164e
SH		 625 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
626 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
d3bcfbeb 627
82637e80 628 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 629 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
ff35164e 630 /* Turn on/off phy power saving */
d3bcfbeb 631 if (onoff)
d3bcfbeb
SH		 632 reg1 &= ~phy_power[port];
633 else
634 reg1 |= phy_power[port];
635
ff35164e
SH		 636 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
637 reg1 |= coma_mode[port];
638
b32f40c4 639 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 640 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
641 sky2_pci_read32(hw, PCI_DEV_REG1);
167f53d0 642
d3bcfbeb
SH		 643 udelay(100);
644}
645
1b537565
SH		 646/* Force a renegotiation */
647static void sky2_phy_reinit(struct sky2_port *sky2)
648{
e07b1aa8 649 spin_lock_bh(&sky2->phy_lock);
1b537565 650 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 651 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 652}
653
e3173832
SH		 654/* Put device in state to listen for Wake On Lan */
655static void sky2_wol_init(struct sky2_port *sky2)
656{
657 struct sky2_hw *hw = sky2->hw;
658 unsigned port = sky2->port;
659 enum flow_control save_mode;
660 u16 ctrl;
661 u32 reg1;
662
663 /* Bring hardware out of reset */
664 sky2_write16(hw, B0_CTST, CS_RST_CLR);
665 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
666
667 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
668 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
669
670 /* Force to 10/100
671 * sky2_reset will re-enable on resume
672 */
673 save_mode = sky2->flow_mode;
674 ctrl = sky2->advertising;
675
676 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
677 sky2->flow_mode = FC_NONE;
678 sky2_phy_power(hw, port, 1);
679 sky2_phy_reinit(sky2);
680
681 sky2->flow_mode = save_mode;
682 sky2->advertising = ctrl;
683
684 /* Set GMAC to no flow control and auto update for speed/duplex */
685 gma_write16(hw, port, GM_GP_CTRL,
686 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
687 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
688
689 /* Set WOL address */
690 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
691 sky2->netdev->dev_addr, ETH_ALEN);
692
693 /* Turn on appropriate WOL control bits */
694 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
695 ctrl = 0;
696 if (sky2->wol & WAKE_PHY)
697 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
698 else
699 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
700
701 if (sky2->wol & WAKE_MAGIC)
702 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
703 else
704 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
705
706 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
707 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
708
709 /* Turn on legacy PCI-Express PME mode */
b32f40c4 710 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 711 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 712 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 713
714 /* block receiver */
715 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
716
717}
718
69161611
SH		 719static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
720{
05745c4a
SH		 721 struct net_device *dev = hw->dev[port];
722
ed4d4161
SH		 723 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
724 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
725 hw->chip_id == CHIP_ID_YUKON_FE_P ||
726 hw->chip_id == CHIP_ID_YUKON_SUPR) {
727 /* Yukon-Extreme B0 and further Extreme devices */
728 /* enable Store & Forward mode for TX */
05745c4a 729
ed4d4161
SH		 730 if (dev->mtu <= ETH_DATA_LEN)
731 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
732 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 733
ed4d4161
SH		 734 else
735 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
736 TX_JUMBO_ENA| TX_STFW_ENA);
737 } else {
738 if (dev->mtu <= ETH_DATA_LEN)
739 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
740 else {
741 /* set Tx GMAC FIFO Almost Empty Threshold */
742 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
743 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 744
ed4d4161
SH		 745 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
746
747 /* Can't do offload because of lack of store/forward */
748 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
749 }
69161611
SH		 750 }
751}
752
cd28ab6a
SH		 753static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
754{
755 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
756 u16 reg;
25cccecc 757 u32 rx_reg;
cd28ab6a
SH		 758 int i;
759 const u8 *addr = hw->dev[port]->dev_addr;
760
f350339c
SH		 761 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
762 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 763
764 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
765
793b883e 766 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 767 /* WA DEV_472 -- looks like crossed wires on port 2 */
768 /* clear GMAC 1 Control reset */
769 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
770 do {
771 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
772 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
773 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
774 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
775 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
776 }
777
793b883e 778 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 779
2eaba1a2
SH		 780 /* Enable Transmit FIFO Underrun */
781 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
782
e07b1aa8 783 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 784 sky2_phy_init(hw, port);
e07b1aa8 785 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 786
787 /* MIB clear */
788 reg = gma_read16(hw, port, GM_PHY_ADDR);
789 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
790
43f2f104
SH		 791 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
792 gma_read16(hw, port, i);
cd28ab6a
SH		 793 gma_write16(hw, port, GM_PHY_ADDR, reg);
794
795 /* transmit control */
796 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
797
798 /* receive control reg: unicast + multicast + no FCS */
799 gma_write16(hw, port, GM_RX_CTRL,
793b883e 800 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 801
802 /* transmit flow control */
803 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
804
805 /* transmit parameter */
806 gma_write16(hw, port, GM_TX_PARAM,
807 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
808 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
809 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
810 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
811
812 /* serial mode register */
813 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 814 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 815
6b1a3aef 816 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 817 reg |= GM_SMOD_JUMBO_ENA;
818
819 gma_write16(hw, port, GM_SERIAL_MODE, reg);
820
cd28ab6a
SH		 821 /* virtual address for data */
822 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
823
793b883e
SH		 824 /* physical address: used for pause frames */
825 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
826
827 /* ignore counter overflows */
cd28ab6a
SH		 828 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
829 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
830 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
831
832 /* Configure Rx MAC FIFO */
833 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 834 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 835 if (hw->chip_id == CHIP_ID_YUKON_EX ||
836 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 837 rx_reg |= GMF_RX_OVER_ON;
69161611 838
25cccecc 839 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 840
798fdd07
SH		 841 if (hw->chip_id == CHIP_ID_YUKON_XL) {
842 /* Hardware errata - clear flush mask */
843 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
844 } else {
845 /* Flush Rx MAC FIFO on any flow control or error */
846 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
847 }
cd28ab6a 848
8df9a876 849 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 850 reg = RX_GMF_FL_THR_DEF + 1;
851 /* Another magic mystery workaround from sk98lin */
852 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
853 hw->chip_rev == CHIP_REV_YU_FE2_A0)
854 reg = 0x178;
855 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 856
857 /* Configure Tx MAC FIFO */
858 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
859 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 860
e0c28116 861 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 862 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 863 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 864 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 865
69161611 866 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 867 }
868
e970d1f8
SH		 869 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
870 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
871 /* disable dynamic watermark */
872 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
873 reg &= ~TX_DYN_WM_ENA;
874 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
875 }
cd28ab6a
SH		 876}
877
67712901
SH		 878/* Assign Ram Buffer allocation to queue */
879static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 880{
67712901
SH		 881 u32 end;
882
883 /* convert from K bytes to qwords used for hw register */
884 start *= 1024/8;
885 space *= 1024/8;
886 end = start + space - 1;
793b883e 887
cd28ab6a
SH		 888 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
889 sky2_write32(hw, RB_ADDR(q, RB_START), start);
890 sky2_write32(hw, RB_ADDR(q, RB_END), end);
891 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
892 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
893
894 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 895 u32 tp = space - space/4;
793b883e 896
1c28f6ba
SH		 897 /* On receive queue's set the thresholds
898 * give receiver priority when > 3/4 full
899 * send pause when down to 2K
900 */
901 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
902 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 903
1c28f6ba
SH		 904 tp = space - 2048/8;
905 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
906 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 907 } else {
908 /* Enable store & forward on Tx queue's because
909 * Tx FIFO is only 1K on Yukon
910 */
911 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
912 }
913
914 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 915 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 916}
917
cd28ab6a 918/* Setup Bus Memory Interface */
af4ed7e6 919static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 920{
921 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
922 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
923 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 924 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 925}
926
cd28ab6a
SH		 927/* Setup prefetch unit registers. This is the interface between
928 * hardware and driver list elements
929 */
8cc048e3 930static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 931 u64 addr, u32 last)
932{
cd28ab6a
SH		 933 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
934 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
935 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
936 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
937 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
938 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 939
940 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 941}
942
793b883e
SH		 943static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
944{
945 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
946
cb5d9547 947 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 948 le->ctrl = 0;
793b883e
SH		 949 return le;
950}
cd28ab6a 951
88f5f0ca
SH		 952static void tx_init(struct sky2_port *sky2)
953{
954 struct sky2_tx_le *le;
955
956 sky2->tx_prod = sky2->tx_cons = 0;
957 sky2->tx_tcpsum = 0;
958 sky2->tx_last_mss = 0;
959
960 le = get_tx_le(sky2);
961 le->addr = 0;
962 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 963}
964
291ea614
SH		 965static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
966 struct sky2_tx_le *le)
967{
968 return sky2->tx_ring + (le - sky2->tx_le);
969}
970
290d4de5
SH		 971/* Update chip's next pointer */
972static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 973{
50432cb5 974 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 975 wmb();
50432cb5
SH		 976 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
977
978 /* Synchronize I/O on since next processor may write to tail */
979 mmiowb();
cd28ab6a
SH		 980}
981
793b883e 982
cd28ab6a
SH		 983static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
984{
985 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 986 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 987 le->ctrl = 0;
cd28ab6a
SH		 988 return le;
989}
990
14d0263f
SH		 991/* Build description to hardware for one receive segment */
992static void sky2_rx_add(struct sky2_port *sky2, u8 op,
993 dma_addr_t map, unsigned len)
cd28ab6a
SH		 994{
995 struct sky2_rx_le *le;
996
86c6887e 997 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 998 le = sky2_next_rx(sky2);
86c6887e 999 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1000 le->opcode = OP_ADDR64 | HW_OWNER;
1001 }
793b883e 1002
cd28ab6a 1003 le = sky2_next_rx(sky2);
734d1868
SH		 1004 le->addr = cpu_to_le32((u32) map);
1005 le->length = cpu_to_le16(len);
14d0263f 1006 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1007}
1008
14d0263f
SH		 1009/* Build description to hardware for one possibly fragmented skb */
1010static void sky2_rx_submit(struct sky2_port *sky2,
1011 const struct rx_ring_info *re)
1012{
1013 int i;
1014
1015 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1016
1017 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1018 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1019}
1020
1021
1022static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1023 unsigned size)
1024{
1025 struct sk_buff *skb = re->skb;
1026 int i;
1027
1028 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1029 pci_unmap_len_set(re, data_size, size);
1030
1031 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1032 re->frag_addr[i] = pci_map_page(pdev,
1033 skb_shinfo(skb)->frags[i].page,
1034 skb_shinfo(skb)->frags[i].page_offset,
1035 skb_shinfo(skb)->frags[i].size,
1036 PCI_DMA_FROMDEVICE);
1037}
1038
1039static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1040{
1041 struct sk_buff *skb = re->skb;
1042 int i;
1043
1044 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1045 PCI_DMA_FROMDEVICE);
1046
1047 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1048 pci_unmap_page(pdev, re->frag_addr[i],
1049 skb_shinfo(skb)->frags[i].size,
1050 PCI_DMA_FROMDEVICE);
1051}
793b883e 1052
cd28ab6a
SH		 1053/* Tell chip where to start receive checksum.
1054 * Actually has two checksums, but set both same to avoid possible byte
1055 * order problems.
1056 */
793b883e 1057static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1058{
ea76e635 1059 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1060
ea76e635
SH		 1061 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1062 le->ctrl = 0;
1063 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1064
ea76e635
SH		 1065 sky2_write32(sky2->hw,
1066 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1067 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1068}
1069
6b1a3aef
SH		 1070/*
1071 * The RX Stop command will not work for Yukon-2 if the BMU does not
1072 * reach the end of packet and since we can't make sure that we have
1073 * incoming data, we must reset the BMU while it is not doing a DMA
1074 * transfer. Since it is possible that the RX path is still active,
1075 * the RX RAM buffer will be stopped first, so any possible incoming
1076 * data will not trigger a DMA. After the RAM buffer is stopped, the
1077 * BMU is polled until any DMA in progress is ended and only then it
1078 * will be reset.
1079 */
1080static void sky2_rx_stop(struct sky2_port *sky2)
1081{
1082 struct sky2_hw *hw = sky2->hw;
1083 unsigned rxq = rxqaddr[sky2->port];
1084 int i;
1085
1086 /* disable the RAM Buffer receive queue */
1087 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1088
1089 for (i = 0; i < 0xffff; i++)
1090 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1091 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1092 goto stopped;
1093
1094 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1095 sky2->netdev->name);
1096stopped:
1097 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1098
1099 /* reset the Rx prefetch unit */
1100 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1101 mmiowb();
6b1a3aef 1102}
793b883e 1103
d571b694 1104/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1105static void sky2_rx_clean(struct sky2_port *sky2)
1106{
1107 unsigned i;
1108
1109 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1110 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1111 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1112
1113 if (re->skb) {
14d0263f 1114 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1115 kfree_skb(re->skb);
1116 re->skb = NULL;
1117 }
1118 }
1119}
1120
ef743d33
SH		 1121/* Basic MII support */
1122static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1123{
1124 struct mii_ioctl_data *data = if_mii(ifr);
1125 struct sky2_port *sky2 = netdev_priv(dev);
1126 struct sky2_hw *hw = sky2->hw;
1127 int err = -EOPNOTSUPP;
1128
1129 if (!netif_running(dev))
1130 return -ENODEV; /* Phy still in reset */
1131
d89e1343 1132 switch (cmd) {
ef743d33
SH		 1133 case SIOCGMIIPHY:
1134 data->phy_id = PHY_ADDR_MARV;
1135
1136 /* fallthru */
1137 case SIOCGMIIREG: {
1138 u16 val = 0;
91c86df5 1139
e07b1aa8 1140 spin_lock_bh(&sky2->phy_lock);
ef743d33 1141 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1142 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1143
ef743d33
SH		 1144 data->val_out = val;
1145 break;
1146 }
1147
1148 case SIOCSMIIREG:
1149 if (!capable(CAP_NET_ADMIN))
1150 return -EPERM;
1151
e07b1aa8 1152 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1153 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1154 data->val_in);
e07b1aa8 1155 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1156 break;
1157 }
1158 return err;
1159}
1160
d1f13708 1161#ifdef SKY2_VLAN_TAG_USED
d494eacd 1162static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1163{
d494eacd 1164 if (onoff) {
3d4e66f5
SH		 1165 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1166 RX_VLAN_STRIP_ON);
1167 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1168 TX_VLAN_TAG_ON);
1169 } else {
1170 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1171 RX_VLAN_STRIP_OFF);
1172 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1173 TX_VLAN_TAG_OFF);
1174 }
d494eacd
SH		 1175}
1176
1177static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1178{
1179 struct sky2_port *sky2 = netdev_priv(dev);
1180 struct sky2_hw *hw = sky2->hw;
1181 u16 port = sky2->port;
1182
1183 netif_tx_lock_bh(dev);
1184 napi_disable(&hw->napi);
1185
1186 sky2->vlgrp = grp;
1187 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1188
d1d08d12 1189 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1190 napi_enable(&hw->napi);
2bb8c262 1191 netif_tx_unlock_bh(dev);
d1f13708
SH		 1192}
1193#endif
1194
82788c7a 1195/*
14d0263f
SH		 1196 * Allocate an skb for receiving. If the MTU is large enough
1197 * make the skb non-linear with a fragment list of pages.
82788c7a 1198 */
14d0263f 1199static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1200{
1201 struct sk_buff *skb;
14d0263f 1202 int i;
82788c7a 1203
39dbd958 1204 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1205 unsigned char *start;
1206 /*
1207 * Workaround for a bug in FIFO that cause hang
1208 * if the FIFO if the receive buffer is not 64 byte aligned.
1209 * The buffer returned from netdev_alloc_skb is
1210 * aligned except if slab debugging is enabled.
1211 */
1212 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1213 if (!skb)
1214 goto nomem;
1215 start = PTR_ALIGN(skb->data, 8);
1216 skb_reserve(skb, start - skb->data);
1217 } else {
1218 skb = netdev_alloc_skb(sky2->netdev,
1219 sky2->rx_data_size + NET_IP_ALIGN);
1220 if (!skb)
1221 goto nomem;
1222 skb_reserve(skb, NET_IP_ALIGN);
1223 }
14d0263f
SH		 1224
1225 for (i = 0; i < sky2->rx_nfrags; i++) {
1226 struct page *page = alloc_page(GFP_ATOMIC);
1227
1228 if (!page)
1229 goto free_partial;
1230 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1231 }
1232
1233 return skb;
14d0263f
SH		 1234free_partial:
1235 kfree_skb(skb);
1236nomem:
1237 return NULL;
82788c7a
SH		 1238}
1239
55c9dd35
SH		 1240static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1241{
1242 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1243}
1244
cd28ab6a
SH		 1245/*
1246 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1247 * Normal case this ends up creating one list element for skb
1248 * in the receive ring. Worst case if using large MTU and each
1249 * allocation falls on a different 64 bit region, that results
1250 * in 6 list elements per ring entry.
1251 * One element is used for checksum enable/disable, and one
1252 * extra to avoid wrap.
cd28ab6a 1253 */
6b1a3aef 1254static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1255{
6b1a3aef 1256 struct sky2_hw *hw = sky2->hw;
14d0263f 1257 struct rx_ring_info *re;
6b1a3aef 1258 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1259 unsigned i, size, thresh;
cd28ab6a 1260
6b1a3aef 1261 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1262 sky2_qset(hw, rxq);
977bdf06 1263
c3905bc4
SH		 1264 /* On PCI express lowering the watermark gives better performance */
1265 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1266 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1267
1268 /* These chips have no ram buffer?
1269 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1270 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1271 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1272 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1273 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1274
6b1a3aef
SH		 1275 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1276
ea76e635
SH		 1277 if (!(hw->flags & SKY2_HW_NEW_LE))
1278 rx_set_checksum(sky2);
14d0263f
SH		 1279
1280 /* Space needed for frame data + headers rounded up */
f957da2a 1281 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1282
1283 /* Stopping point for hardware truncation */
1284 thresh = (size - 8) / sizeof(u32);
1285
5f06eba4 1286 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1287 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1288
5f06eba4
SH		 1289 /* Compute residue after pages */
1290 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1291
5f06eba4
SH		 1292 /* Optimize to handle small packets and headers */
1293 if (size < copybreak)
1294 size = copybreak;
1295 if (size < ETH_HLEN)
1296 size = ETH_HLEN;
14d0263f 1297
14d0263f
SH		 1298 sky2->rx_data_size = size;
1299
1300 /* Fill Rx ring */
793b883e 1301 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1302 re = sky2->rx_ring + i;
cd28ab6a 1303
14d0263f 1304 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1305 if (!re->skb)
1306 goto nomem;
1307
14d0263f
SH		 1308 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1309 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1310 }
1311
a1433ac4
SH		 1312 /*
1313 * The receiver hangs if it receives frames larger than the
1314 * packet buffer. As a workaround, truncate oversize frames, but
1315 * the register is limited to 9 bits, so if you do frames > 2052
1316 * you better get the MTU right!
1317 */
a1433ac4
SH		 1318 if (thresh > 0x1ff)
1319 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1320 else {
1321 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1322 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1323 }
1324
6b1a3aef 1325 /* Tell chip about available buffers */
55c9dd35 1326 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1327 return 0;
1328nomem:
1329 sky2_rx_clean(sky2);
1330 return -ENOMEM;
1331}
1332
1333/* Bring up network interface. */
1334static int sky2_up(struct net_device *dev)
1335{
1336 struct sky2_port *sky2 = netdev_priv(dev);
1337 struct sky2_hw *hw = sky2->hw;
1338 unsigned port = sky2->port;
e0c28116 1339 u32 imask, ramsize;
ee7abb04 1340 int cap, err = -ENOMEM;
843a46f4 1341 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1342
ee7abb04
SH		 1343 /*
1344 * On dual port PCI-X card, there is an problem where status
1345 * can be received out of order due to split transactions
843a46f4 1346 */
ee7abb04
SH		 1347 if (otherdev && netif_running(otherdev) &&
1348 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1349 u16 cmd;
1350
b32f40c4 1351 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1352 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1353 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1354
ee7abb04 1355 }
843a46f4 1356
cd28ab6a
SH		 1357 if (netif_msg_ifup(sky2))
1358 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1359
55d7b4e6
SH		 1360 netif_carrier_off(dev);
1361
cd28ab6a
SH		 1362 /* must be power of 2 */
1363 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1364 TX_RING_SIZE *
1365 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1366 &sky2->tx_le_map);
1367 if (!sky2->tx_le)
1368 goto err_out;
1369
6cdbbdf3 1370 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1371 GFP_KERNEL);
1372 if (!sky2->tx_ring)
1373 goto err_out;
88f5f0ca
SH		 1374
1375 tx_init(sky2);
cd28ab6a
SH		 1376
1377 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1378 &sky2->rx_le_map);
1379 if (!sky2->rx_le)
1380 goto err_out;
1381 memset(sky2->rx_le, 0, RX_LE_BYTES);
1382
291ea614 1383 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1384 GFP_KERNEL);
1385 if (!sky2->rx_ring)
1386 goto err_out;
1387
d3bcfbeb
SH		 1388 sky2_phy_power(hw, port, 1);
1389
cd28ab6a
SH		 1390 sky2_mac_init(hw, port);
1391
e0c28116
SH		 1392 /* Register is number of 4K blocks on internal RAM buffer. */
1393 ramsize = sky2_read8(hw, B2_E_0) * 4;
1394 if (ramsize > 0) {
67712901 1395 u32 rxspace;
cd28ab6a 1396
39dbd958 1397 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1398 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1399 if (ramsize < 16)
1400 rxspace = ramsize / 2;
1401 else
1402 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1403
67712901
SH		 1404 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1405 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1406
1407 /* Make sure SyncQ is disabled */
1408 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1409 RB_RST_SET);
1410 }
793b883e 1411
af4ed7e6 1412 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1413
69161611
SH		 1414 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1415 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1416 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1417
977bdf06 1418 /* Set almost empty threshold */
c2716fb4
SH		 1419 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1420 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1421 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1422
6b1a3aef
SH		 1423 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1424 TX_RING_SIZE - 1);
cd28ab6a 1425
d494eacd
SH		 1426#ifdef SKY2_VLAN_TAG_USED
1427 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1428#endif
1429
6b1a3aef 1430 err = sky2_rx_start(sky2);
6de16237 1431 if (err)
cd28ab6a
SH		 1432 goto err_out;
1433
cd28ab6a 1434 /* Enable interrupts from phy/mac for port */
e07b1aa8 1435 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1436 imask |= portirq_msk[port];
e07b1aa8
SH		 1437 sky2_write32(hw, B0_IMSK, imask);
1438
a7bffe72 1439 sky2_set_multicast(dev);
cd28ab6a
SH		 1440 return 0;
1441
1442err_out:
1b537565 1443 if (sky2->rx_le) {
cd28ab6a
SH		 1444 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1445 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1446 sky2->rx_le = NULL;
1447 }
1448 if (sky2->tx_le) {
cd28ab6a
SH		 1449 pci_free_consistent(hw->pdev,
1450 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1451 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1452 sky2->tx_le = NULL;
1453 }
1454 kfree(sky2->tx_ring);
1455 kfree(sky2->rx_ring);
cd28ab6a 1456
1b537565
SH		 1457 sky2->tx_ring = NULL;
1458 sky2->rx_ring = NULL;
cd28ab6a
SH		 1459 return err;
1460}
1461
793b883e
SH		 1462/* Modular subtraction in ring */
1463static inline int tx_dist(unsigned tail, unsigned head)
1464{
cb5d9547 1465 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1466}
cd28ab6a 1467
793b883e
SH		 1468/* Number of list elements available for next tx */
1469static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1470{
793b883e 1471 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1472}
1473
793b883e 1474/* Estimate of number of transmit list elements required */
28bd181a 1475static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1476{
793b883e
SH		 1477 unsigned count;
1478
1479 count = sizeof(dma_addr_t) / sizeof(u32);
1480 count += skb_shinfo(skb)->nr_frags * count;
1481
89114afd 1482 if (skb_is_gso(skb))
793b883e
SH		 1483 ++count;
1484
84fa7933 1485 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1486 ++count;
1487
1488 return count;
cd28ab6a
SH		 1489}
1490
793b883e
SH		 1491/*
1492 * Put one packet in ring for transmit.
1493 * A single packet can generate multiple list elements, and
1494 * the number of ring elements will probably be less than the number
1495 * of list elements used.
1496 */
cd28ab6a
SH		 1497static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1498{
1499 struct sky2_port *sky2 = netdev_priv(dev);
1500 struct sky2_hw *hw = sky2->hw;
d1f13708 1501 struct sky2_tx_le *le = NULL;
6cdbbdf3 1502 struct tx_ring_info *re;
cd28ab6a
SH		 1503 unsigned i, len;
1504 dma_addr_t mapping;
cd28ab6a
SH		 1505 u16 mss;
1506 u8 ctrl;
1507
2bb8c262
SH		 1508 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1509 return NETDEV_TX_BUSY;
cd28ab6a 1510
793b883e 1511 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1512 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1513 dev->name, sky2->tx_prod, skb->len);
1514
cd28ab6a
SH		 1515 len = skb_headlen(skb);
1516 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1517
86c6887e
SH		 1518 /* Send high bits if needed */
1519 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1520 le = get_tx_le(sky2);
86c6887e 1521 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1522 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1523 }
cd28ab6a
SH		 1524
1525 /* Check for TCP Segmentation Offload */
7967168c 1526 mss = skb_shinfo(skb)->gso_size;
793b883e 1527 if (mss != 0) {
ea76e635
SH		 1528
1529 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1530 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1531
1532 if (mss != sky2->tx_last_mss) {
1533 le = get_tx_le(sky2);
1534 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1535
1536 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1537 le->opcode = OP_MSS | HW_OWNER;
1538 else
1539 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1540 sky2->tx_last_mss = mss;
1541 }
cd28ab6a
SH		 1542 }
1543
cd28ab6a 1544 ctrl = 0;
d1f13708
SH		 1545#ifdef SKY2_VLAN_TAG_USED
1546 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1547 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1548 if (!le) {
1549 le = get_tx_le(sky2);
f65b138c 1550 le->addr = 0;
d1f13708 1551 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1552 } else
1553 le->opcode |= OP_VLAN;
1554 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1555 ctrl |= INS_VLAN;
1556 }
1557#endif
1558
1559 /* Handle TCP checksum offload */
84fa7933 1560 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1561 /* On Yukon EX (some versions) encoding change. */
ea76e635 1562 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1563 ctrl |= CALSUM; /* auto checksum */
1564 else {
1565 const unsigned offset = skb_transport_offset(skb);
1566 u32 tcpsum;
1567
1568 tcpsum = offset << 16; /* sum start */
1569 tcpsum |= offset + skb->csum_offset; /* sum write */
1570
1571 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1572 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1573 ctrl |= UDPTCP;
1574
1575 if (tcpsum != sky2->tx_tcpsum) {
1576 sky2->tx_tcpsum = tcpsum;
1577
1578 le = get_tx_le(sky2);
1579 le->addr = cpu_to_le32(tcpsum);
1580 le->length = 0; /* initial checksum value */
1581 le->ctrl = 1; /* one packet */
1582 le->opcode = OP_TCPLISW | HW_OWNER;
1583 }
1d179332 1584 }
cd28ab6a
SH		 1585 }
1586
1587 le = get_tx_le(sky2);
f65b138c 1588 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1589 le->length = cpu_to_le16(len);
1590 le->ctrl = ctrl;
793b883e 1591 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1592
291ea614 1593 re = tx_le_re(sky2, le);
cd28ab6a 1594 re->skb = skb;
6cdbbdf3 1595 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1596 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1597
1598 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1599 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1600
1601 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1602 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1603
1604 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1605 le = get_tx_le(sky2);
86c6887e 1606 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1607 le->ctrl = 0;
1608 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1609 }
1610
1611 le = get_tx_le(sky2);
f65b138c 1612 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1613 le->length = cpu_to_le16(frag->size);
1614 le->ctrl = ctrl;
793b883e 1615 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1616
291ea614
SH		 1617 re = tx_le_re(sky2, le);
1618 re->skb = skb;
1619 pci_unmap_addr_set(re, mapaddr, mapping);
1620 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1621 }
6cdbbdf3 1622
cd28ab6a
SH		 1623 le->ctrl |= EOP;
1624
97bda706
SH		 1625 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1626 netif_stop_queue(dev);
b19666d9 1627
290d4de5 1628 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1629
cd28ab6a
SH		 1630 dev->trans_start = jiffies;
1631 return NETDEV_TX_OK;
1632}
1633
cd28ab6a 1634/*
793b883e
SH		 1635 * Free ring elements from starting at tx_cons until "done"
1636 *
1637 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1638 * buffers so make sure not to free skb to early.
cd28ab6a 1639 */
d11c13e7 1640static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1641{
d11c13e7 1642 struct net_device *dev = sky2->netdev;
af2a58ac 1643 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1644 unsigned idx;
cd28ab6a 1645
0e3ff6aa 1646 BUG_ON(done >= TX_RING_SIZE);
2224795d 1647
291ea614
SH		 1648 for (idx = sky2->tx_cons; idx != done;
1649 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1650 struct sky2_tx_le *le = sky2->tx_le + idx;
1651 struct tx_ring_info *re = sky2->tx_ring + idx;
1652
1653 switch(le->opcode & ~HW_OWNER) {
1654 case OP_LARGESEND:
1655 case OP_PACKET:
1656 pci_unmap_single(pdev,
1657 pci_unmap_addr(re, mapaddr),
1658 pci_unmap_len(re, maplen),
1659 PCI_DMA_TODEVICE);
af2a58ac 1660 break;
291ea614
SH		 1661 case OP_BUFFER:
1662 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1663 pci_unmap_len(re, maplen),
734d1868 1664 PCI_DMA_TODEVICE);
291ea614
SH		 1665 break;
1666 }
1667
1668 if (le->ctrl & EOP) {
1669 if (unlikely(netif_msg_tx_done(sky2)))
1670 printk(KERN_DEBUG "%s: tx done %u\n",
1671 dev->name, idx);
3cf26753 1672
7138a0f5
SH		 1673 dev->stats.tx_packets++;
1674 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1675
794b2bd2 1676 dev_kfree_skb_any(re->skb);
3cf26753 1677 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1678 }
793b883e 1679 }
793b883e 1680
291ea614 1681 sky2->tx_cons = idx;
50432cb5
SH		 1682 smp_mb();
1683
22e11703 1684 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1685 netif_wake_queue(dev);
cd28ab6a
SH		 1686}
1687
1688/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1689static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1690{
2bb8c262
SH		 1691 struct sky2_port *sky2 = netdev_priv(dev);
1692
1693 netif_tx_lock_bh(dev);
d11c13e7 1694 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1695 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1696}
1697
1698/* Network shutdown */
1699static int sky2_down(struct net_device *dev)
1700{
1701 struct sky2_port *sky2 = netdev_priv(dev);
1702 struct sky2_hw *hw = sky2->hw;
1703 unsigned port = sky2->port;
1704 u16 ctrl;
e07b1aa8 1705 u32 imask;
cd28ab6a 1706
1b537565
SH		 1707 /* Never really got started! */
1708 if (!sky2->tx_le)
1709 return 0;
1710
cd28ab6a
SH		 1711 if (netif_msg_ifdown(sky2))
1712 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1713
018d1c66 1714 /* Stop more packets from being queued */
cd28ab6a
SH		 1715 netif_stop_queue(dev);
1716
ebc646f6
SH		 1717 /* Disable port IRQ */
1718 imask = sky2_read32(hw, B0_IMSK);
1719 imask &= ~portirq_msk[port];
1720 sky2_write32(hw, B0_IMSK, imask);
1721
6de16237
SH		 1722 synchronize_irq(hw->pdev->irq);
1723
d3bcfbeb 1724 sky2_gmac_reset(hw, port);
793b883e 1725
cd28ab6a
SH		 1726 /* Stop transmitter */
1727 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1728 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1729
1730 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1731 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1732
1733 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1734 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1735 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1736
6de16237
SH		 1737 /* Make sure no packets are pending */
1738 napi_synchronize(&hw->napi);
1739
cd28ab6a
SH		 1740 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1741
1742 /* Workaround shared GMAC reset */
793b883e
SH		 1743 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1744 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1745 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1746
1747 /* Disable Force Sync bit and Enable Alloc bit */
1748 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1749 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1750
1751 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1752 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1753 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1754
1755 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1756 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1757 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1758
1759 /* Reset the Tx prefetch units */
1760 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1761 PREF_UNIT_RST_SET);
1762
1763 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1764
6b1a3aef 1765 sky2_rx_stop(sky2);
cd28ab6a
SH		 1766
1767 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1768 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1769
d3bcfbeb
SH		 1770 sky2_phy_power(hw, port, 0);
1771
55d7b4e6
SH		 1772 netif_carrier_off(dev);
1773
d571b694 1774 /* turn off LED's */
cd28ab6a
SH		 1775 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1776
2bb8c262 1777 sky2_tx_clean(dev);
cd28ab6a
SH		 1778 sky2_rx_clean(sky2);
1779
1780 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1781 sky2->rx_le, sky2->rx_le_map);
1782 kfree(sky2->rx_ring);
1783
1784 pci_free_consistent(hw->pdev,
1785 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1786 sky2->tx_le, sky2->tx_le_map);
1787 kfree(sky2->tx_ring);
1788
1b537565
SH		 1789 sky2->tx_le = NULL;
1790 sky2->rx_le = NULL;
1791
1792 sky2->rx_ring = NULL;
1793 sky2->tx_ring = NULL;
1794
cd28ab6a
SH		 1795 return 0;
1796}
1797
1798static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1799{
ea76e635 1800 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1801 return SPEED_1000;
1802
05745c4a
SH		 1803 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1804 if (aux & PHY_M_PS_SPEED_100)
1805 return SPEED_100;
1806 else
1807 return SPEED_10;
1808 }
cd28ab6a
SH		 1809
1810 switch (aux & PHY_M_PS_SPEED_MSK) {
1811 case PHY_M_PS_SPEED_1000:
1812 return SPEED_1000;
1813 case PHY_M_PS_SPEED_100:
1814 return SPEED_100;
1815 default:
1816 return SPEED_10;
1817 }
1818}
1819
1820static void sky2_link_up(struct sky2_port *sky2)
1821{
1822 struct sky2_hw *hw = sky2->hw;
1823 unsigned port = sky2->port;
1824 u16 reg;
16ad91e1
SH		 1825 static const char *fc_name[] = {
1826 [FC_NONE] = "none",
1827 [FC_TX] = "tx",
1828 [FC_RX] = "rx",
1829 [FC_BOTH] = "both",
1830 };
cd28ab6a 1831
cd28ab6a 1832 /* enable Rx/Tx */
2eaba1a2 1833 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1834 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1835 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1836
1837 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1838
1839 netif_carrier_on(sky2->netdev);
cd28ab6a 1840
75e80683 1841 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1842
cd28ab6a 1843 /* Turn on link LED */
793b883e 1844 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1845 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1846
1847 if (netif_msg_link(sky2))
1848 printk(KERN_INFO PFX
d571b694 1849 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1850 sky2->netdev->name, sky2->speed,
1851 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1852 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1853}
1854
1855static void sky2_link_down(struct sky2_port *sky2)
1856{
1857 struct sky2_hw *hw = sky2->hw;
1858 unsigned port = sky2->port;
1859 u16 reg;
1860
1861 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1862
1863 reg = gma_read16(hw, port, GM_GP_CTRL);
1864 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1865 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1866
cd28ab6a 1867 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1868
1869 /* Turn on link LED */
1870 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1871
1872 if (netif_msg_link(sky2))
1873 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1874
cd28ab6a
SH		 1875 sky2_phy_init(hw, port);
1876}
1877
16ad91e1
SH		 1878static enum flow_control sky2_flow(int rx, int tx)
1879{
1880 if (rx)
1881 return tx ? FC_BOTH : FC_RX;
1882 else
1883 return tx ? FC_TX : FC_NONE;
1884}
1885
793b883e
SH		 1886static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1887{
1888 struct sky2_hw *hw = sky2->hw;
1889 unsigned port = sky2->port;
da4c1ff4 1890 u16 advert, lpa;
793b883e 1891
da4c1ff4 1892 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1893 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1894 if (lpa & PHY_M_AN_RF) {
1895 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1896 return -1;
1897 }
1898
793b883e
SH		 1899 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1900 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1901 sky2->netdev->name);
1902 return -1;
1903 }
1904
793b883e 1905 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1906 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1907
da4c1ff4
SH		 1908 /* Since the pause result bits seem to in different positions on
1909 * different chips. look at registers.
1910 */
ea76e635 1911 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1912 /* Shift for bits in fiber PHY */
1913 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1914 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1915
1916 if (advert & ADVERTISE_1000XPAUSE)
1917 advert |= ADVERTISE_PAUSE_CAP;
1918 if (advert & ADVERTISE_1000XPSE_ASYM)
1919 advert |= ADVERTISE_PAUSE_ASYM;
1920 if (lpa & LPA_1000XPAUSE)
1921 lpa |= LPA_PAUSE_CAP;
1922 if (lpa & LPA_1000XPAUSE_ASYM)
1923 lpa |= LPA_PAUSE_ASYM;
1924 }
793b883e 1925
da4c1ff4
SH		 1926 sky2->flow_status = FC_NONE;
1927 if (advert & ADVERTISE_PAUSE_CAP) {
1928 if (lpa & LPA_PAUSE_CAP)
1929 sky2->flow_status = FC_BOTH;
1930 else if (advert & ADVERTISE_PAUSE_ASYM)
1931 sky2->flow_status = FC_RX;
1932 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1933 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1934 sky2->flow_status = FC_TX;
1935 }
793b883e 1936
16ad91e1 1937 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1938 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1939 sky2->flow_status = FC_NONE;
2eaba1a2 1940
da4c1ff4 1941 if (sky2->flow_status & FC_TX)
793b883e
SH		 1942 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1943 else
1944 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1945
1946 return 0;
1947}
cd28ab6a 1948
e07b1aa8
SH		 1949/* Interrupt from PHY */
1950static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1951{
e07b1aa8
SH		 1952 struct net_device *dev = hw->dev[port];
1953 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1954 u16 istatus, phystat;
1955
ebc646f6
SH		 1956 if (!netif_running(dev))
1957 return;
1958
e07b1aa8
SH		 1959 spin_lock(&sky2->phy_lock);
1960 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1961 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1962
cd28ab6a
SH		 1963 if (netif_msg_intr(sky2))
1964 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1965 sky2->netdev->name, istatus, phystat);
1966
2eaba1a2 1967 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1968 if (sky2_autoneg_done(sky2, phystat) == 0)
1969 sky2_link_up(sky2);
1970 goto out;
1971 }
cd28ab6a 1972
793b883e
SH		 1973 if (istatus & PHY_M_IS_LSP_CHANGE)
1974 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1975
793b883e
SH		 1976 if (istatus & PHY_M_IS_DUP_CHANGE)
1977 sky2->duplex =
1978 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1979
793b883e
SH		 1980 if (istatus & PHY_M_IS_LST_CHANGE) {
1981 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1982 sky2_link_up(sky2);
793b883e
SH		 1983 else
1984 sky2_link_down(sky2);
cd28ab6a 1985 }
793b883e 1986out:
e07b1aa8 1987 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1988}
1989
62335ab0 1990/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1991 * and tx queue is full (stopped).
1992 */
cd28ab6a
SH		 1993static void sky2_tx_timeout(struct net_device *dev)
1994{
1995 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1996 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1997
1998 if (netif_msg_timer(sky2))
1999 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2000
8f24664d 2001 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2002 dev->name, sky2->tx_cons, sky2->tx_prod,
2003 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2004 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2005
81906791
SH		 2006 /* can't restart safely under softirq */
2007 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2008}
2009
2010static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2011{
6b1a3aef
SH		 2012 struct sky2_port *sky2 = netdev_priv(dev);
2013 struct sky2_hw *hw = sky2->hw;
b628ed98 2014 unsigned port = sky2->port;
6b1a3aef
SH		 2015 int err;
2016 u16 ctl, mode;
e07b1aa8 2017 u32 imask;
cd28ab6a
SH		 2018
2019 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2020 return -EINVAL;
2021
05745c4a
SH		 2022 if (new_mtu > ETH_DATA_LEN &&
2023 (hw->chip_id == CHIP_ID_YUKON_FE ||
2024 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2025 return -EINVAL;
2026
6b1a3aef
SH		 2027 if (!netif_running(dev)) {
2028 dev->mtu = new_mtu;
2029 return 0;
2030 }
2031
e07b1aa8 2032 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2033 sky2_write32(hw, B0_IMSK, 0);
2034
018d1c66
SH		 2035 dev->trans_start = jiffies; /* prevent tx timeout */
2036 netif_stop_queue(dev);
bea3348e 2037 napi_disable(&hw->napi);
018d1c66 2038
e07b1aa8
SH		 2039 synchronize_irq(hw->pdev->irq);
2040
39dbd958 2041 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2042 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2043
2044 ctl = gma_read16(hw, port, GM_GP_CTRL);
2045 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2046 sky2_rx_stop(sky2);
2047 sky2_rx_clean(sky2);
cd28ab6a
SH		 2048
2049 dev->mtu = new_mtu;
14d0263f 2050
6b1a3aef
SH		 2051 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2052 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2053
2054 if (dev->mtu > ETH_DATA_LEN)
2055 mode |= GM_SMOD_JUMBO_ENA;
2056
b628ed98 2057 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2058
b628ed98 2059 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2060
6b1a3aef 2061 err = sky2_rx_start(sky2);
e07b1aa8 2062 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2063
d1d08d12 2064 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2065 napi_enable(&hw->napi);
2066
1b537565
SH		 2067 if (err)
2068 dev_close(dev);
2069 else {
b628ed98 2070 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2071
1b537565
SH		 2072 netif_wake_queue(dev);
2073 }
2074
cd28ab6a
SH		 2075 return err;
2076}
2077
14d0263f
SH		 2078/* For small just reuse existing skb for next receive */
2079static struct sk_buff *receive_copy(struct sky2_port *sky2,
2080 const struct rx_ring_info *re,
2081 unsigned length)
2082{
2083 struct sk_buff *skb;
2084
2085 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2086 if (likely(skb)) {
2087 skb_reserve(skb, 2);
2088 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2089 length, PCI_DMA_FROMDEVICE);
d626f62b 2090 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2091 skb->ip_summed = re->skb->ip_summed;
2092 skb->csum = re->skb->csum;
2093 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2094 length, PCI_DMA_FROMDEVICE);
2095 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2096 skb_put(skb, length);
14d0263f
SH		 2097 }
2098 return skb;
2099}
2100
2101/* Adjust length of skb with fragments to match received data */
2102static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2103 unsigned int length)
2104{
2105 int i, num_frags;
2106 unsigned int size;
2107
2108 /* put header into skb */
2109 size = min(length, hdr_space);
2110 skb->tail += size;
2111 skb->len += size;
2112 length -= size;
2113
2114 num_frags = skb_shinfo(skb)->nr_frags;
2115 for (i = 0; i < num_frags; i++) {
2116 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2117
2118 if (length == 0) {
2119 /* don't need this page */
2120 __free_page(frag->page);
2121 --skb_shinfo(skb)->nr_frags;
2122 } else {
2123 size = min(length, (unsigned) PAGE_SIZE);
2124
2125 frag->size = size;
2126 skb->data_len += size;
2127 skb->truesize += size;
2128 skb->len += size;
2129 length -= size;
2130 }
2131 }
2132}
2133
2134/* Normal packet - take skb from ring element and put in a new one */
2135static struct sk_buff *receive_new(struct sky2_port *sky2,
2136 struct rx_ring_info *re,
2137 unsigned int length)
2138{
2139 struct sk_buff *skb, *nskb;
2140 unsigned hdr_space = sky2->rx_data_size;
2141
14d0263f
SH		 2142 /* Don't be tricky about reusing pages (yet) */
2143 nskb = sky2_rx_alloc(sky2);
2144 if (unlikely(!nskb))
2145 return NULL;
2146
2147 skb = re->skb;
2148 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2149
2150 prefetch(skb->data);
2151 re->skb = nskb;
2152 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2153
2154 if (skb_shinfo(skb)->nr_frags)
2155 skb_put_frags(skb, hdr_space, length);
2156 else
489b10c1 2157 skb_put(skb, length);
14d0263f
SH		 2158 return skb;
2159}
2160
cd28ab6a
SH		 2161/*
2162 * Receive one packet.
d571b694 2163 * For larger packets, get new buffer.
cd28ab6a 2164 */
497d7c86 2165static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2166 u16 length, u32 status)
2167{
497d7c86 2168 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2169 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2170 struct sk_buff *skb = NULL;
d6532232
SH		 2171 u16 count = (status & GMR_FS_LEN) >> 16;
2172
2173#ifdef SKY2_VLAN_TAG_USED
2174 /* Account for vlan tag */
2175 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2176 count -= VLAN_HLEN;
2177#endif
cd28ab6a
SH		 2178
2179 if (unlikely(netif_msg_rx_status(sky2)))
2180 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2181 dev->name, sky2->rx_next, status, length);
cd28ab6a 2182
793b883e 2183 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2184 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2185
3b12e014
SH		 2186 /* This chip has hardware problems that generates bogus status.
2187 * So do only marginal checking and expect higher level protocols
2188 * to handle crap frames.
2189 */
2190 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2191 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2192 length != count)
2193 goto okay;
2194
42eeea01 2195 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2196 goto error;
2197
42eeea01
SH		 2198 if (!(status & GMR_FS_RX_OK))
2199 goto resubmit;
2200
d6532232
SH		 2201 /* if length reported by DMA does not match PHY, packet was truncated */
2202 if (length != count)
3b12e014 2203 goto len_error;
71749531 2204
3b12e014 2205okay:
14d0263f
SH		 2206 if (length < copybreak)
2207 skb = receive_copy(sky2, re, length);
2208 else
2209 skb = receive_new(sky2, re, length);
793b883e 2210resubmit:
14d0263f 2211 sky2_rx_submit(sky2, re);
79e57d32 2212
cd28ab6a
SH		 2213 return skb;
2214
3b12e014 2215len_error:
71749531
SH		 2216 /* Truncation of overlength packets
2217 causes PHY length to not match MAC length */
7138a0f5 2218 ++dev->stats.rx_length_errors;
d6532232 2219 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2220 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2221 dev->name, status, length);
d6532232 2222 goto resubmit;
71749531 2223
cd28ab6a 2224error:
7138a0f5 2225 ++dev->stats.rx_errors;
b6d77734 2226 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2227 dev->stats.rx_over_errors++;
b6d77734
SH		 2228 goto resubmit;
2229 }
6e15b712 2230
3be92a70 2231 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2232 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2233 dev->name, status, length);
793b883e
SH		 2234
2235 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2236 dev->stats.rx_length_errors++;
cd28ab6a 2237 if (status & GMR_FS_FRAGMENT)
7138a0f5 2238 dev->stats.rx_frame_errors++;
cd28ab6a 2239 if (status & GMR_FS_CRC_ERR)
7138a0f5 2240 dev->stats.rx_crc_errors++;
79e57d32 2241
793b883e 2242 goto resubmit;
cd28ab6a
SH		 2243}
2244
e07b1aa8
SH		 2245/* Transmit complete */
2246static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2247{
e07b1aa8 2248 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2249
e07b1aa8 2250 if (netif_running(dev)) {
2bb8c262 2251 netif_tx_lock(dev);
e07b1aa8 2252 sky2_tx_complete(sky2, last);
2bb8c262 2253 netif_tx_unlock(dev);
2224795d 2254 }
cd28ab6a
SH		 2255}
2256
e07b1aa8 2257/* Process status response ring */
26691830 2258static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2259{
e07b1aa8 2260 int work_done = 0;
55c9dd35 2261 unsigned rx[2] = { 0, 0 };
a8fd6266 2262
af2a58ac 2263 rmb();
26691830 2264 do {
55c9dd35 2265 struct sky2_port *sky2;
13210ce5 2266 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2267 unsigned port;
13210ce5 2268 struct net_device *dev;
cd28ab6a 2269 struct sk_buff *skb;
cd28ab6a
SH		 2270 u32 status;
2271 u16 length;
ab5adecb
SH		 2272 u8 opcode = le->opcode;
2273
2274 if (!(opcode & HW_OWNER))
2275 break;
cd28ab6a 2276
cb5d9547 2277 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2278
ab5adecb 2279 port = le->css & CSS_LINK_BIT;
69161611 2280 dev = hw->dev[port];
13210ce5 2281 sky2 = netdev_priv(dev);
f65b138c
SH		 2282 length = le16_to_cpu(le->length);
2283 status = le32_to_cpu(le->status);
cd28ab6a 2284
ab5adecb
SH		 2285 le->opcode = 0;
2286 switch (opcode & ~HW_OWNER) {
cd28ab6a 2287 case OP_RXSTAT:
55c9dd35 2288 ++rx[port];
497d7c86 2289 skb = sky2_receive(dev, length, status);
3225b919 2290 if (unlikely(!skb)) {
7138a0f5 2291 dev->stats.rx_dropped++;
55c9dd35 2292 break;
3225b919 2293 }
13210ce5 2294
69161611 2295 /* This chip reports checksum status differently */
05745c4a 2296 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2297 if (sky2->rx_csum &&
2298 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2299 (le->css & CSS_TCPUDPCSOK))
2300 skb->ip_summed = CHECKSUM_UNNECESSARY;
2301 else
2302 skb->ip_summed = CHECKSUM_NONE;
2303 }
2304
13210ce5 2305 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2306 dev->stats.rx_packets++;
2307 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2308 dev->last_rx = jiffies;
2309
d1f13708
SH		 2310#ifdef SKY2_VLAN_TAG_USED
2311 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2312 vlan_hwaccel_receive_skb(skb,
2313 sky2->vlgrp,
2314 be16_to_cpu(sky2->rx_tag));
2315 } else
2316#endif
cd28ab6a 2317 netif_receive_skb(skb);
13210ce5 2318
22e11703 2319 /* Stop after net poll weight */
13210ce5
SH		 2320 if (++work_done >= to_do)
2321 goto exit_loop;
cd28ab6a
SH		 2322 break;
2323
d1f13708
SH		 2324#ifdef SKY2_VLAN_TAG_USED
2325 case OP_RXVLAN:
2326 sky2->rx_tag = length;
2327 break;
2328
2329 case OP_RXCHKSVLAN:
2330 sky2->rx_tag = length;
2331 /* fall through */
2332#endif
cd28ab6a 2333 case OP_RXCHKS:
87418307
SH		 2334 if (!sky2->rx_csum)
2335 break;
2336
05745c4a
SH		 2337 /* If this happens then driver assuming wrong format */
2338 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2339 if (net_ratelimit())
2340 printk(KERN_NOTICE "%s: unexpected"
2341 " checksum status\n",
2342 dev->name);
69161611 2343 break;
05745c4a 2344 }
69161611 2345
87418307
SH		 2346 /* Both checksum counters are programmed to start at
2347 * the same offset, so unless there is a problem they
2348 * should match. This failure is an early indication that
2349 * hardware receive checksumming won't work.
2350 */
2351 if (likely(status >> 16 == (status & 0xffff))) {
2352 skb = sky2->rx_ring[sky2->rx_next].skb;
2353 skb->ip_summed = CHECKSUM_COMPLETE;
2354 skb->csum = status & 0xffff;
2355 } else {
2356 printk(KERN_NOTICE PFX "%s: hardware receive "
2357 "checksum problem (status = %#x)\n",
2358 dev->name, status);
2359 sky2->rx_csum = 0;
2360 sky2_write32(sky2->hw,
69161611 2361 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2362 BMU_DIS_RX_CHKSUM);
2363 }
cd28ab6a
SH		 2364 break;
2365
2366 case OP_TXINDEXLE:
13b97b74 2367 /* TX index reports status for both ports */
f55925d7
SH		 2368 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2369 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2370 if (hw->dev[1])
2371 sky2_tx_done(hw->dev[1],
2372 ((status >> 24) & 0xff)
2373 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2374 break;
2375
cd28ab6a
SH		 2376 default:
2377 if (net_ratelimit())
793b883e 2378 printk(KERN_WARNING PFX
ab5adecb 2379 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2380 }
26691830 2381 } while (hw->st_idx != idx);
cd28ab6a 2382
fe2a24df
SH		 2383 /* Fully processed status ring so clear irq */
2384 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2385
13210ce5 2386exit_loop:
55c9dd35
SH		 2387 if (rx[0])
2388 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2389
55c9dd35
SH		 2390 if (rx[1])
2391 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2392
e07b1aa8 2393 return work_done;
cd28ab6a
SH		 2394}
2395
2396static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2397{
2398 struct net_device *dev = hw->dev[port];
2399
3be92a70
SH		 2400 if (net_ratelimit())
2401 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2402 dev->name, status);
cd28ab6a
SH		 2403
2404 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2405 if (net_ratelimit())
2406 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2407 dev->name);
cd28ab6a
SH		 2408 /* Clear IRQ */
2409 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2410 }
2411
2412 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2413 if (net_ratelimit())
2414 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2415 dev->name);
cd28ab6a
SH		 2416
2417 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2418 }
2419
2420 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2421 if (net_ratelimit())
2422 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2423 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2424 }
2425
2426 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2427 if (net_ratelimit())
2428 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2429 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2430 }
2431
2432 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2433 if (net_ratelimit())
2434 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2435 dev->name);
cd28ab6a
SH		 2436 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2437 }
2438}
2439
2440static void sky2_hw_intr(struct sky2_hw *hw)
2441{
555382cb 2442 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2443 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2444 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2445
2446 status &= hwmsk;
cd28ab6a 2447
793b883e 2448 if (status & Y2_IS_TIST_OV)
cd28ab6a 2449 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2450
2451 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2452 u16 pci_err;
2453
82637e80 2454 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2455 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2456 if (net_ratelimit())
555382cb 2457 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2458 pci_err);
cd28ab6a 2459
b32f40c4 2460 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2461 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2462 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2463 }
2464
2465 if (status & Y2_IS_PCI_EXP) {
d571b694 2466 /* PCI-Express uncorrectable Error occurred */
555382cb 2467 u32 err;
cd28ab6a 2468
82637e80 2469 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2470 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2471 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2472 0xfffffffful);
3be92a70 2473 if (net_ratelimit())
555382cb 2474 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2475
7782c8c4 2476 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2477 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2478 }
2479
2480 if (status & Y2_HWE_L1_MASK)
2481 sky2_hw_error(hw, 0, status);
2482 status >>= 8;
2483 if (status & Y2_HWE_L1_MASK)
2484 sky2_hw_error(hw, 1, status);
2485}
2486
2487static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2488{
2489 struct net_device *dev = hw->dev[port];
2490 struct sky2_port *sky2 = netdev_priv(dev);
2491 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2492
2493 if (netif_msg_intr(sky2))
2494 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2495 dev->name, status);
2496
a3caeada
SH		 2497 if (status & GM_IS_RX_CO_OV)
2498 gma_read16(hw, port, GM_RX_IRQ_SRC);
2499
2500 if (status & GM_IS_TX_CO_OV)
2501 gma_read16(hw, port, GM_TX_IRQ_SRC);
2502
cd28ab6a 2503 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2504 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2505 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2506 }
2507
2508 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2509 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2510 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2511 }
cd28ab6a
SH		 2512}
2513
40b01727
SH		 2514/* This should never happen it is a bug. */
2515static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2516 u16 q, unsigned ring_size)
d257924e
SH		 2517{
2518 struct net_device *dev = hw->dev[port];
2519 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2520 unsigned idx;
2521 const u64 *le = (q == Q_R1 || q == Q_R2)
2522 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2523
40b01727
SH		 2524 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2525 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2526 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2527 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2528
40b01727 2529 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2530}
cd28ab6a 2531
75e80683
SH		 2532static int sky2_rx_hung(struct net_device *dev)
2533{
2534 struct sky2_port *sky2 = netdev_priv(dev);
2535 struct sky2_hw *hw = sky2->hw;
2536 unsigned port = sky2->port;
2537 unsigned rxq = rxqaddr[port];
2538 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2539 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2540 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2541 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2542
2543 /* If idle and MAC or PCI is stuck */
2544 if (sky2->check.last == dev->last_rx &&
2545 ((mac_rp == sky2->check.mac_rp &&
2546 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2547 /* Check if the PCI RX hang */
2548 (fifo_rp == sky2->check.fifo_rp &&
2549 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2550 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2551 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2552 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2553 return 1;
2554 } else {
2555 sky2->check.last = dev->last_rx;
2556 sky2->check.mac_rp = mac_rp;
2557 sky2->check.mac_lev = mac_lev;
2558 sky2->check.fifo_rp = fifo_rp;
2559 sky2->check.fifo_lev = fifo_lev;
2560 return 0;
2561 }
2562}
2563
32c2c300 2564static void sky2_watchdog(unsigned long arg)
d27ed387 2565{
01bd7564 2566 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2567
75e80683 2568 /* Check for lost IRQ once a second */
32c2c300 2569 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2570 napi_schedule(&hw->napi);
75e80683
SH		 2571 } else {
2572 int i, active = 0;
2573
2574 for (i = 0; i < hw->ports; i++) {
bea3348e 2575 struct net_device *dev = hw->dev[i];
75e80683
SH		 2576 if (!netif_running(dev))
2577 continue;
2578 ++active;
2579
2580 /* For chips with Rx FIFO, check if stuck */
39dbd958 2581 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2582 sky2_rx_hung(dev)) {
2583 pr_info(PFX "%s: receiver hang detected\n",
2584 dev->name);
2585 schedule_work(&hw->restart_work);
2586 return;
2587 }
2588 }
2589
2590 if (active == 0)
2591 return;
32c2c300 2592 }
01bd7564 2593
75e80683 2594 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2595}
2596
40b01727
SH		 2597/* Hardware/software error handling */
2598static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2599{
40b01727
SH		 2600 if (net_ratelimit())
2601 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2602
1e5f1283
SH		 2603 if (status & Y2_IS_HW_ERR)
2604 sky2_hw_intr(hw);
d257924e 2605
1e5f1283
SH		 2606 if (status & Y2_IS_IRQ_MAC1)
2607 sky2_mac_intr(hw, 0);
cd28ab6a 2608
1e5f1283
SH		 2609 if (status & Y2_IS_IRQ_MAC2)
2610 sky2_mac_intr(hw, 1);
cd28ab6a 2611
1e5f1283 2612 if (status & Y2_IS_CHK_RX1)
40b01727 2613 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2614
1e5f1283 2615 if (status & Y2_IS_CHK_RX2)
40b01727 2616 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2617
1e5f1283 2618 if (status & Y2_IS_CHK_TXA1)
40b01727 2619 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2620
1e5f1283 2621 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2622 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2623}
2624
bea3348e 2625static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2626{
bea3348e 2627 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2628 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2629 int work_done = 0;
26691830 2630 u16 idx;
40b01727
SH		 2631
2632 if (unlikely(status & Y2_IS_ERROR))
2633 sky2_err_intr(hw, status);
2634
2635 if (status & Y2_IS_IRQ_PHY1)
2636 sky2_phy_intr(hw, 0);
2637
2638 if (status & Y2_IS_IRQ_PHY2)
2639 sky2_phy_intr(hw, 1);
cd28ab6a 2640
26691830
SH		 2641 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2642 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2643
2644 if (work_done >= work_limit)
26691830
SH		 2645 goto done;
2646 }
6f535763 2647
26691830
SH		 2648 /* Bug/Errata workaround?
2649 * Need to kick the TX irq moderation timer.
2650 */
2651 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2652 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2653 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2654 }
26691830
SH		 2655 napi_complete(napi);
2656 sky2_read32(hw, B0_Y2_SP_LISR);
2657done:
6f535763 2658
bea3348e 2659 return work_done;
e07b1aa8
SH		 2660}
2661
7d12e780 2662static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2663{
2664 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2665 u32 status;
2666
2667 /* Reading this mask interrupts as side effect */
2668 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2669 if (status == 0 || status == ~0)
2670 return IRQ_NONE;
793b883e 2671
e07b1aa8 2672 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2673
2674 napi_schedule(&hw->napi);
793b883e 2675
cd28ab6a
SH		 2676 return IRQ_HANDLED;
2677}
2678
2679#ifdef CONFIG_NET_POLL_CONTROLLER
2680static void sky2_netpoll(struct net_device *dev)
2681{
2682 struct sky2_port *sky2 = netdev_priv(dev);
2683
bea3348e 2684 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2685}
2686#endif
2687
2688/* Chip internal frequency for clock calculations */
05745c4a 2689static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2690{
793b883e 2691 switch (hw->chip_id) {
cd28ab6a 2692 case CHIP_ID_YUKON_EC:
5a5b1ea0 2693 case CHIP_ID_YUKON_EC_U:
93745494 2694 case CHIP_ID_YUKON_EX:
ed4d4161 2695 case CHIP_ID_YUKON_SUPR:
05745c4a
SH		 2696 return 125;
2697
cd28ab6a 2698 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2699 return 100;
2700
2701 case CHIP_ID_YUKON_FE_P:
2702 return 50;
2703
2704 case CHIP_ID_YUKON_XL:
2705 return 156;
2706
2707 default:
2708 BUG();
cd28ab6a
SH		 2709 }
2710}
2711
fb17358f 2712static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2713{
fb17358f 2714 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2715}
2716
fb17358f 2717static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2718{
fb17358f 2719 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2720}
2721
fb17358f 2722
e3173832 2723static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2724{
b89165f2 2725 u8 t8;
cd28ab6a 2726
167f53d0 2727 /* Enable all clocks and check for bad PCI access */
b32f40c4 2728 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2729
cd28ab6a 2730 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2731
cd28ab6a 2732 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2733 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2734
2735 switch(hw->chip_id) {
2736 case CHIP_ID_YUKON_XL:
39dbd958 2737 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2738 break;
2739
2740 case CHIP_ID_YUKON_EC_U:
2741 hw->flags = SKY2_HW_GIGABIT
2742 | SKY2_HW_NEWER_PHY
2743 | SKY2_HW_ADV_POWER_CTL;
2744 break;
2745
2746 case CHIP_ID_YUKON_EX:
2747 hw->flags = SKY2_HW_GIGABIT
2748 | SKY2_HW_NEWER_PHY
2749 | SKY2_HW_NEW_LE
2750 | SKY2_HW_ADV_POWER_CTL;
2751
2752 /* New transmit checksum */
2753 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2754 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2755 break;
2756
2757 case CHIP_ID_YUKON_EC:
2758 /* This rev is really old, and requires untested workarounds */
2759 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2760 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2761 return -EOPNOTSUPP;
2762 }
39dbd958 2763 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2764 break;
2765
2766 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2767 break;
2768
05745c4a
SH		 2769 case CHIP_ID_YUKON_FE_P:
2770 hw->flags = SKY2_HW_NEWER_PHY
2771 | SKY2_HW_NEW_LE
2772 | SKY2_HW_AUTO_TX_SUM
2773 | SKY2_HW_ADV_POWER_CTL;
2774 break;
ed4d4161
SH		 2775
2776 case CHIP_ID_YUKON_SUPR:
2777 hw->flags = SKY2_HW_GIGABIT
2778 | SKY2_HW_NEWER_PHY
2779 | SKY2_HW_NEW_LE
2780 | SKY2_HW_AUTO_TX_SUM
2781 | SKY2_HW_ADV_POWER_CTL;
2782 break;
2783
ea76e635 2784 default:
b02a9258
SH		 2785 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2786 hw->chip_id);
cd28ab6a
SH		 2787 return -EOPNOTSUPP;
2788 }
2789
ea76e635
SH		 2790 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2791 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2792 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2793
290d4de5 2794
e3173832
SH		 2795 hw->ports = 1;
2796 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2797 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2798 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2799 ++hw->ports;
2800 }
2801
2802 return 0;
2803}
2804
2805static void sky2_reset(struct sky2_hw *hw)
2806{
555382cb 2807 struct pci_dev *pdev = hw->pdev;
e3173832 2808 u16 status;
555382cb
SH		 2809 int i, cap;
2810 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2811
cd28ab6a 2812 /* disable ASF */
4f44d8ba
SH		 2813 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2814 status = sky2_read16(hw, HCU_CCSR);
2815 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2816 HCU_CCSR_UC_STATE_MSK);
2817 sky2_write16(hw, HCU_CCSR, status);
2818 } else
2819 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2820 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2821
2822 /* do a SW reset */
2823 sky2_write8(hw, B0_CTST, CS_RST_SET);
2824 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2825
ac93a394
SH		 2826 /* allow writes to PCI config */
2827 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2828
cd28ab6a 2829 /* clear PCI errors, if any */
b32f40c4 2830 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2831 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2832 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2833
2834 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2835
555382cb
SH		 2836 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2837 if (cap) {
7782c8c4
SH		 2838 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2839 0xfffffffful);
555382cb
SH		 2840
2841 /* If error bit is stuck on ignore it */
2842 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2843 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2844 else
555382cb
SH		 2845 hwe_mask |= Y2_IS_PCI_EXP;
2846 }
cd28ab6a 2847
ae306cca 2848 sky2_power_on(hw);
82637e80 2849 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2850
2851 for (i = 0; i < hw->ports; i++) {
2852 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2853 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2854
ed4d4161
SH		 2855 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2856 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2857 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2858 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2859 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2860 }
2861
793b883e
SH		 2862 /* Clear I2C IRQ noise */
2863 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2864
2865 /* turn off hardware timer (unused) */
2866 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2867 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2868
cd28ab6a
SH		 2869 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2870
69634ee7
SH		 2871 /* Turn off descriptor polling */
2872 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2873
2874 /* Turn off receive timestamp */
2875 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2876 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2877
2878 /* enable the Tx Arbiters */
2879 for (i = 0; i < hw->ports; i++)
2880 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2881
2882 /* Initialize ram interface */
2883 for (i = 0; i < hw->ports; i++) {
793b883e 2884 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2885
2886 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2887 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2888 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2889 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2890 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2891 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2892 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2893 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2894 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2895 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2896 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2897 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2898 }
2899
555382cb 2900 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2901
cd28ab6a 2902 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2903 sky2_gmac_reset(hw, i);
cd28ab6a 2904
cd28ab6a
SH		 2905 memset(hw->st_le, 0, STATUS_LE_BYTES);
2906 hw->st_idx = 0;
2907
2908 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2909 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2910
2911 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2912 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2913
2914 /* Set the list last index */
793b883e 2915 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2916
290d4de5
SH		 2917 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2918 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2919
290d4de5
SH		 2920 /* set Status-FIFO ISR watermark */
2921 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2922 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2923 else
2924 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2925
290d4de5 2926 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2927 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2928 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2929
793b883e 2930 /* enable status unit */
cd28ab6a
SH		 2931 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2932
2933 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2934 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2935 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2936}
2937
81906791
SH		 2938static void sky2_restart(struct work_struct *work)
2939{
2940 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2941 struct net_device *dev;
2942 int i, err;
2943
81906791 2944 rtnl_lock();
81906791
SH		 2945 for (i = 0; i < hw->ports; i++) {
2946 dev = hw->dev[i];
2947 if (netif_running(dev))
2948 sky2_down(dev);
2949 }
2950
8cfcbe99
SH		 2951 napi_disable(&hw->napi);
2952 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 2953 sky2_reset(hw);
2954 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2955 napi_enable(&hw->napi);
81906791
SH		 2956
2957 for (i = 0; i < hw->ports; i++) {
2958 dev = hw->dev[i];
2959 if (netif_running(dev)) {
2960 err = sky2_up(dev);
2961 if (err) {
2962 printk(KERN_INFO PFX "%s: could not restart %d\n",
2963 dev->name, err);
2964 dev_close(dev);
2965 }
2966 }
2967 }
2968
81906791
SH		 2969 rtnl_unlock();
2970}
2971
e3173832
SH		 2972static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2973{
2974 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2975}
2976
2977static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2978{
2979 const struct sky2_port *sky2 = netdev_priv(dev);
2980
2981 wol->supported = sky2_wol_supported(sky2->hw);
2982 wol->wolopts = sky2->wol;
2983}
2984
2985static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2986{
2987 struct sky2_port *sky2 = netdev_priv(dev);
2988 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2989
e3173832
SH		 2990 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2991 return -EOPNOTSUPP;
2992
2993 sky2->wol = wol->wolopts;
2994
05745c4a
SH		 2995 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2996 hw->chip_id == CHIP_ID_YUKON_EX ||
2997 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2998 sky2_write32(hw, B0_CTST, sky2->wol
2999 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3000
3001 if (!netif_running(dev))
3002 sky2_wol_init(sky2);
cd28ab6a
SH		 3003 return 0;
3004}
3005
28bd181a 3006static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3007{
b89165f2
SH		 3008 if (sky2_is_copper(hw)) {
3009 u32 modes = SUPPORTED_10baseT_Half
3010 | SUPPORTED_10baseT_Full
3011 | SUPPORTED_100baseT_Half
3012 | SUPPORTED_100baseT_Full
3013 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3014
ea76e635 3015 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3016 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3017 | SUPPORTED_1000baseT_Full;
3018 return modes;
cd28ab6a 3019 } else
b89165f2
SH		 3020 return SUPPORTED_1000baseT_Half
3021 | SUPPORTED_1000baseT_Full
3022 | SUPPORTED_Autoneg
3023 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3024}
3025
793b883e 3026static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3027{
3028 struct sky2_port *sky2 = netdev_priv(dev);
3029 struct sky2_hw *hw = sky2->hw;
3030
3031 ecmd->transceiver = XCVR_INTERNAL;
3032 ecmd->supported = sky2_supported_modes(hw);
3033 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3034 if (sky2_is_copper(hw)) {
cd28ab6a 3035 ecmd->port = PORT_TP;
b89165f2
SH		 3036 ecmd->speed = sky2->speed;
3037 } else {
3038 ecmd->speed = SPEED_1000;
cd28ab6a 3039 ecmd->port = PORT_FIBRE;
b89165f2 3040 }
cd28ab6a
SH		 3041
3042 ecmd->advertising = sky2->advertising;
3043 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3044 ecmd->duplex = sky2->duplex;
3045 return 0;
3046}
3047
3048static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3049{
3050 struct sky2_port *sky2 = netdev_priv(dev);
3051 const struct sky2_hw *hw = sky2->hw;
3052 u32 supported = sky2_supported_modes(hw);
3053
3054 if (ecmd->autoneg == AUTONEG_ENABLE) {
3055 ecmd->advertising = supported;
3056 sky2->duplex = -1;
3057 sky2->speed = -1;
3058 } else {
3059 u32 setting;
3060
793b883e 3061 switch (ecmd->speed) {
cd28ab6a
SH		 3062 case SPEED_1000:
3063 if (ecmd->duplex == DUPLEX_FULL)
3064 setting = SUPPORTED_1000baseT_Full;
3065 else if (ecmd->duplex == DUPLEX_HALF)
3066 setting = SUPPORTED_1000baseT_Half;
3067 else
3068 return -EINVAL;
3069 break;
3070 case SPEED_100:
3071 if (ecmd->duplex == DUPLEX_FULL)
3072 setting = SUPPORTED_100baseT_Full;
3073 else if (ecmd->duplex == DUPLEX_HALF)
3074 setting = SUPPORTED_100baseT_Half;
3075 else
3076 return -EINVAL;
3077 break;
3078
3079 case SPEED_10:
3080 if (ecmd->duplex == DUPLEX_FULL)
3081 setting = SUPPORTED_10baseT_Full;
3082 else if (ecmd->duplex == DUPLEX_HALF)
3083 setting = SUPPORTED_10baseT_Half;
3084 else
3085 return -EINVAL;
3086 break;
3087 default:
3088 return -EINVAL;
3089 }
3090
3091 if ((setting & supported) == 0)
3092 return -EINVAL;
3093
3094 sky2->speed = ecmd->speed;
3095 sky2->duplex = ecmd->duplex;
3096 }
3097
3098 sky2->autoneg = ecmd->autoneg;
3099 sky2->advertising = ecmd->advertising;
3100
d1b139c0 3101 if (netif_running(dev)) {
1b537565 3102 sky2_phy_reinit(sky2);
d1b139c0
SH		 3103 sky2_set_multicast(dev);
3104 }
cd28ab6a
SH		 3105
3106 return 0;
3107}
3108
3109static void sky2_get_drvinfo(struct net_device *dev,
3110 struct ethtool_drvinfo *info)
3111{
3112 struct sky2_port *sky2 = netdev_priv(dev);
3113
3114 strcpy(info->driver, DRV_NAME);
3115 strcpy(info->version, DRV_VERSION);
3116 strcpy(info->fw_version, "N/A");
3117 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3118}
3119
3120static const struct sky2_stat {
793b883e
SH		 3121 char name[ETH_GSTRING_LEN];
3122 u16 offset;
cd28ab6a
SH		 3123} sky2_stats[] = {
3124 { "tx_bytes", GM_TXO_OK_HI },
3125 { "rx_bytes", GM_RXO_OK_HI },
3126 { "tx_broadcast", GM_TXF_BC_OK },
3127 { "rx_broadcast", GM_RXF_BC_OK },
3128 { "tx_multicast", GM_TXF_MC_OK },
3129 { "rx_multicast", GM_RXF_MC_OK },
3130 { "tx_unicast", GM_TXF_UC_OK },
3131 { "rx_unicast", GM_RXF_UC_OK },
3132 { "tx_mac_pause", GM_TXF_MPAUSE },
3133 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3134 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3135 { "late_collision",GM_TXF_LAT_COL },
3136 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3137 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3138 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3139
d2604540 3140 { "rx_short", GM_RXF_SHT },
cd28ab6a 3141 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3142 { "rx_64_byte_packets", GM_RXF_64B },
3143 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3144 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3145 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3146 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3147 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3148 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3149 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3150 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3151 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3152 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3153
3154 { "tx_64_byte_packets", GM_TXF_64B },
3155 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3156 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3157 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3158 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3159 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3160 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3161 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3162};
3163
cd28ab6a
SH		 3164static u32 sky2_get_rx_csum(struct net_device *dev)
3165{
3166 struct sky2_port *sky2 = netdev_priv(dev);
3167
3168 return sky2->rx_csum;
3169}
3170
3171static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3172{
3173 struct sky2_port *sky2 = netdev_priv(dev);
3174
3175 sky2->rx_csum = data;
793b883e 3176
cd28ab6a
SH		 3177 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3178 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3179
3180 return 0;
3181}
3182
3183static u32 sky2_get_msglevel(struct net_device *netdev)
3184{
3185 struct sky2_port *sky2 = netdev_priv(netdev);
3186 return sky2->msg_enable;
3187}
3188
9a7ae0a9
SH		 3189static int sky2_nway_reset(struct net_device *dev)
3190{
3191 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3192
16ad91e1 3193 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3194 return -EINVAL;
3195
1b537565 3196 sky2_phy_reinit(sky2);
d1b139c0 3197 sky2_set_multicast(dev);
9a7ae0a9
SH		 3198
3199 return 0;
3200}
3201
793b883e 3202static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3203{
3204 struct sky2_hw *hw = sky2->hw;
3205 unsigned port = sky2->port;
3206 int i;
3207
3208 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3209 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3210 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3211 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3212
793b883e 3213 for (i = 2; i < count; i++)
cd28ab6a
SH		 3214 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3215}
3216
cd28ab6a
SH		 3217static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3218{
3219 struct sky2_port *sky2 = netdev_priv(netdev);
3220 sky2->msg_enable = value;
3221}
3222
b9f2c044 3223static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3224{
b9f2c044
JG		 3225 switch (sset) {
3226 case ETH_SS_STATS:
3227 return ARRAY_SIZE(sky2_stats);
3228 default:
3229 return -EOPNOTSUPP;
3230 }
cd28ab6a
SH		 3231}
3232
3233static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3234 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3235{
3236 struct sky2_port *sky2 = netdev_priv(dev);
3237
793b883e 3238 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3239}
3240
793b883e 3241static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3242{
3243 int i;
3244
3245 switch (stringset) {
3246 case ETH_SS_STATS:
3247 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3248 memcpy(data + i * ETH_GSTRING_LEN,
3249 sky2_stats[i].name, ETH_GSTRING_LEN);
3250 break;
3251 }
3252}
3253
cd28ab6a
SH		 3254static int sky2_set_mac_address(struct net_device *dev, void *p)
3255{
3256 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3257 struct sky2_hw *hw = sky2->hw;
3258 unsigned port = sky2->port;
3259 const struct sockaddr *addr = p;
cd28ab6a
SH		 3260
3261 if (!is_valid_ether_addr(addr->sa_data))
3262 return -EADDRNOTAVAIL;
3263
cd28ab6a 3264 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3265 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3266 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3267 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3268 dev->dev_addr, ETH_ALEN);
1b537565 3269
a8ab1ec0
SH		 3270 /* virtual address for data */
3271 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3272
3273 /* physical address: used for pause frames */
3274 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3275
3276 return 0;
cd28ab6a
SH		 3277}
3278
a052b52f
SH		 3279static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3280{
3281 u32 bit;
3282
3283 bit = ether_crc(ETH_ALEN, addr) & 63;
3284 filter[bit >> 3] |= 1 << (bit & 7);
3285}
3286
cd28ab6a
SH		 3287static void sky2_set_multicast(struct net_device *dev)
3288{
3289 struct sky2_port *sky2 = netdev_priv(dev);
3290 struct sky2_hw *hw = sky2->hw;
3291 unsigned port = sky2->port;
3292 struct dev_mc_list *list = dev->mc_list;
3293 u16 reg;
3294 u8 filter[8];
a052b52f
SH		 3295 int rx_pause;
3296 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3297
a052b52f 3298 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3299 memset(filter, 0, sizeof(filter));
3300
3301 reg = gma_read16(hw, port, GM_RX_CTRL);
3302 reg |= GM_RXCR_UCF_ENA;
3303
d571b694 3304 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3305 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3306 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3307 memset(filter, 0xff, sizeof(filter));
a052b52f 3308 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3309 reg &= ~GM_RXCR_MCF_ENA;
3310 else {
3311 int i;
3312 reg |= GM_RXCR_MCF_ENA;
3313
a052b52f
SH		 3314 if (rx_pause)
3315 sky2_add_filter(filter, pause_mc_addr);
3316
3317 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3318 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3319 }
3320
cd28ab6a 3321 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3322 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3323 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3324 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3325 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3326 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3327 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3328 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3329
3330 gma_write16(hw, port, GM_RX_CTRL, reg);
3331}
3332
3333/* Can have one global because blinking is controlled by
3334 * ethtool and that is always under RTNL mutex
3335 */
a84d0a3d 3336static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3337{
a84d0a3d
SH		 3338 struct sky2_hw *hw = sky2->hw;
3339 unsigned port = sky2->port;
793b883e 3340
a84d0a3d
SH		 3341 spin_lock_bh(&sky2->phy_lock);
3342 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3343 hw->chip_id == CHIP_ID_YUKON_EX ||
3344 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3345 u16 pg;
793b883e
SH		 3346 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3347 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3348
a84d0a3d
SH		 3349 switch (mode) {
3350 case MO_LED_OFF:
3351 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3352 PHY_M_LEDC_LOS_CTRL(8) |
3353 PHY_M_LEDC_INIT_CTRL(8) |
3354 PHY_M_LEDC_STA1_CTRL(8) |
3355 PHY_M_LEDC_STA0_CTRL(8));
3356 break;
3357 case MO_LED_ON:
3358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3359 PHY_M_LEDC_LOS_CTRL(9) |
3360 PHY_M_LEDC_INIT_CTRL(9) |
3361 PHY_M_LEDC_STA1_CTRL(9) |
3362 PHY_M_LEDC_STA0_CTRL(9));
3363 break;
3364 case MO_LED_BLINK:
3365 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3366 PHY_M_LEDC_LOS_CTRL(0xa) |
3367 PHY_M_LEDC_INIT_CTRL(0xa) |
3368 PHY_M_LEDC_STA1_CTRL(0xa) |
3369 PHY_M_LEDC_STA0_CTRL(0xa));
3370 break;
3371 case MO_LED_NORM:
3372 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3373 PHY_M_LEDC_LOS_CTRL(1) |
3374 PHY_M_LEDC_INIT_CTRL(8) |
3375 PHY_M_LEDC_STA1_CTRL(7) |
3376 PHY_M_LEDC_STA0_CTRL(7));
3377 }
793b883e 3378
a84d0a3d
SH		 3379 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3380 } else
0efdf262 3381 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3382 PHY_M_LED_MO_DUP(mode) |
3383 PHY_M_LED_MO_10(mode) |
3384 PHY_M_LED_MO_100(mode) |
3385 PHY_M_LED_MO_1000(mode) |
3386 PHY_M_LED_MO_RX(mode) |
3387 PHY_M_LED_MO_TX(mode));
3388
3389 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3390}
3391
3392/* blink LED's for finding board */
3393static int sky2_phys_id(struct net_device *dev, u32 data)
3394{
3395 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3396 unsigned int i;
cd28ab6a 3397
a84d0a3d
SH		 3398 if (data == 0)
3399 data = UINT_MAX;
cd28ab6a 3400
a84d0a3d
SH		 3401 for (i = 0; i < data; i++) {
3402 sky2_led(sky2, MO_LED_ON);
3403 if (msleep_interruptible(500))
3404 break;
3405 sky2_led(sky2, MO_LED_OFF);
3406 if (msleep_interruptible(500))
3407 break;
793b883e 3408 }
a84d0a3d 3409 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3410
3411 return 0;
3412}
3413
3414static void sky2_get_pauseparam(struct net_device *dev,
3415 struct ethtool_pauseparam *ecmd)
3416{
3417 struct sky2_port *sky2 = netdev_priv(dev);
3418
16ad91e1
SH		 3419 switch (sky2->flow_mode) {
3420 case FC_NONE:
3421 ecmd->tx_pause = ecmd->rx_pause = 0;
3422 break;
3423 case FC_TX:
3424 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3425 break;
3426 case FC_RX:
3427 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3428 break;
3429 case FC_BOTH:
3430 ecmd->tx_pause = ecmd->rx_pause = 1;
3431 }
3432
cd28ab6a
SH		 3433 ecmd->autoneg = sky2->autoneg;
3434}
3435
3436static int sky2_set_pauseparam(struct net_device *dev,
3437 struct ethtool_pauseparam *ecmd)
3438{
3439 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3440
3441 sky2->autoneg = ecmd->autoneg;
16ad91e1 3442 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3443
16ad91e1
SH		 3444 if (netif_running(dev))
3445 sky2_phy_reinit(sky2);
cd28ab6a 3446
2eaba1a2 3447 return 0;
cd28ab6a
SH		 3448}
3449
fb17358f
SH		 3450static int sky2_get_coalesce(struct net_device *dev,
3451 struct ethtool_coalesce *ecmd)
3452{
3453 struct sky2_port *sky2 = netdev_priv(dev);
3454 struct sky2_hw *hw = sky2->hw;
3455
3456 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3457 ecmd->tx_coalesce_usecs = 0;
3458 else {
3459 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3460 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3461 }
3462 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3463
3464 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3465 ecmd->rx_coalesce_usecs = 0;
3466 else {
3467 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3468 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3469 }
3470 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3471
3472 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3473 ecmd->rx_coalesce_usecs_irq = 0;
3474 else {
3475 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3476 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3477 }
3478
3479 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3480
3481 return 0;
3482}
3483
3484/* Note: this affect both ports */
3485static int sky2_set_coalesce(struct net_device *dev,
3486 struct ethtool_coalesce *ecmd)
3487{
3488 struct sky2_port *sky2 = netdev_priv(dev);
3489 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3490 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3491
77b3d6a2
SH		 3492 if (ecmd->tx_coalesce_usecs > tmax ||
3493 ecmd->rx_coalesce_usecs > tmax ||
3494 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3495 return -EINVAL;
3496
ff81fbbe 3497 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3498 return -EINVAL;
ff81fbbe 3499 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3500 return -EINVAL;
ff81fbbe 3501 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3502 return -EINVAL;
3503
3504 if (ecmd->tx_coalesce_usecs == 0)
3505 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3506 else {
3507 sky2_write32(hw, STAT_TX_TIMER_INI,
3508 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3509 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3510 }
3511 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3512
3513 if (ecmd->rx_coalesce_usecs == 0)
3514 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3515 else {
3516 sky2_write32(hw, STAT_LEV_TIMER_INI,
3517 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3518 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3519 }
3520 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3521
3522 if (ecmd->rx_coalesce_usecs_irq == 0)
3523 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3524 else {
d28d4870 3525 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3526 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3527 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3528 }
3529 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3530 return 0;
3531}
3532
793b883e
SH		 3533static void sky2_get_ringparam(struct net_device *dev,
3534 struct ethtool_ringparam *ering)
3535{
3536 struct sky2_port *sky2 = netdev_priv(dev);
3537
3538 ering->rx_max_pending = RX_MAX_PENDING;
3539 ering->rx_mini_max_pending = 0;
3540 ering->rx_jumbo_max_pending = 0;
3541 ering->tx_max_pending = TX_RING_SIZE - 1;
3542
3543 ering->rx_pending = sky2->rx_pending;
3544 ering->rx_mini_pending = 0;
3545 ering->rx_jumbo_pending = 0;
3546 ering->tx_pending = sky2->tx_pending;
3547}
3548
3549static int sky2_set_ringparam(struct net_device *dev,
3550 struct ethtool_ringparam *ering)
3551{
3552 struct sky2_port *sky2 = netdev_priv(dev);
3553 int err = 0;
3554
3555 if (ering->rx_pending > RX_MAX_PENDING ||
3556 ering->rx_pending < 8 ||
3557 ering->tx_pending < MAX_SKB_TX_LE ||
3558 ering->tx_pending > TX_RING_SIZE - 1)
3559 return -EINVAL;
3560
3561 if (netif_running(dev))
3562 sky2_down(dev);
3563
3564 sky2->rx_pending = ering->rx_pending;
3565 sky2->tx_pending = ering->tx_pending;
3566
1b537565 3567 if (netif_running(dev)) {
793b883e 3568 err = sky2_up(dev);
1b537565
SH		 3569 if (err)
3570 dev_close(dev);
3571 }
793b883e
SH		 3572
3573 return err;
3574}
3575
793b883e
SH		 3576static int sky2_get_regs_len(struct net_device *dev)
3577{
6e4cbb34 3578 return 0x4000;
793b883e
SH		 3579}
3580
3581/*
3582 * Returns copy of control register region
3ead5db7 3583 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3584 */
3585static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3586 void *p)
3587{
3588 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3589 const void __iomem *io = sky2->hw->regs;
295b54c4 3590 unsigned int b;
793b883e
SH		 3591
3592 regs->version = 1;
793b883e 3593
295b54c4
SH		 3594 for (b = 0; b < 128; b++) {
3595 /* This complicated switch statement is to make sure and
3596 * only access regions that are unreserved.
3597 * Some blocks are only valid on dual port cards.
3598 * and block 3 has some special diagnostic registers that
3599 * are poison.
3600 */
3601 switch (b) {
3602 case 3:
3603 /* skip diagnostic ram region */
3604 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3605 break;
3ead5db7 3606
295b54c4
SH		 3607 /* dual port cards only */
3608 case 5: /* Tx Arbiter 2 */
3609 case 9: /* RX2 */
3610 case 14 ... 15: /* TX2 */
3611 case 17: case 19: /* Ram Buffer 2 */
3612 case 22 ... 23: /* Tx Ram Buffer 2 */
3613 case 25: /* Rx MAC Fifo 1 */
3614 case 27: /* Tx MAC Fifo 2 */
3615 case 31: /* GPHY 2 */
3616 case 40 ... 47: /* Pattern Ram 2 */
3617 case 52: case 54: /* TCP Segmentation 2 */
3618 case 112 ... 116: /* GMAC 2 */
3619 if (sky2->hw->ports == 1)
3620 goto reserved;
3621 /* fall through */
3622 case 0: /* Control */
3623 case 2: /* Mac address */
3624 case 4: /* Tx Arbiter 1 */
3625 case 7: /* PCI express reg */
3626 case 8: /* RX1 */
3627 case 12 ... 13: /* TX1 */
3628 case 16: case 18:/* Rx Ram Buffer 1 */
3629 case 20 ... 21: /* Tx Ram Buffer 1 */
3630 case 24: /* Rx MAC Fifo 1 */
3631 case 26: /* Tx MAC Fifo 1 */
3632 case 28 ... 29: /* Descriptor and status unit */
3633 case 30: /* GPHY 1*/
3634 case 32 ... 39: /* Pattern Ram 1 */
3635 case 48: case 50: /* TCP Segmentation 1 */
3636 case 56 ... 60: /* PCI space */
3637 case 80 ... 84: /* GMAC 1 */
3638 memcpy_fromio(p, io, 128);
3639 break;
3640 default:
3641reserved:
3642 memset(p, 0, 128);
3643 }
3ead5db7 3644
295b54c4
SH		 3645 p += 128;
3646 io += 128;
3647 }
793b883e 3648}
cd28ab6a 3649
b628ed98
SH		 3650/* In order to do Jumbo packets on these chips, need to turn off the
3651 * transmit store/forward. Therefore checksum offload won't work.
3652 */
3653static int no_tx_offload(struct net_device *dev)
3654{
3655 const struct sky2_port *sky2 = netdev_priv(dev);
3656 const struct sky2_hw *hw = sky2->hw;
3657
69161611 3658 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3659}
3660
3661static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3662{
3663 if (data && no_tx_offload(dev))
3664 return -EINVAL;
3665
3666 return ethtool_op_set_tx_csum(dev, data);
3667}
3668
3669
3670static int sky2_set_tso(struct net_device *dev, u32 data)
3671{
3672 if (data && no_tx_offload(dev))
3673 return -EINVAL;
3674
3675 return ethtool_op_set_tso(dev, data);
3676}
3677
f4331a6d
SH		 3678static int sky2_get_eeprom_len(struct net_device *dev)
3679{
3680 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3681 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3682 u16 reg2;
3683
b32f40c4 3684 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3685 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3686}
3687
b32f40c4 3688static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3689{
167f53d0 3690 u32 val;
f4331a6d 3691
b32f40c4 3692 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3693
3694 do {
b32f40c4 3695 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3696 } while (!(offset & PCI_VPD_ADDR_F));
3697
b32f40c4 3698 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3699 return val;
f4331a6d
SH		 3700}
3701
b32f40c4 3702static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3703{
b32f40c4
SH		 3704 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3705 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3706 do {
b32f40c4 3707 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3708 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3709}
3710
3711static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3712 u8 *data)
3713{
3714 struct sky2_port *sky2 = netdev_priv(dev);
3715 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3716 int length = eeprom->len;
3717 u16 offset = eeprom->offset;
3718
3719 if (!cap)
3720 return -EINVAL;
3721
3722 eeprom->magic = SKY2_EEPROM_MAGIC;
3723
3724 while (length > 0) {
b32f40c4 3725 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3726 int n = min_t(int, length, sizeof(val));
3727
3728 memcpy(data, &val, n);
3729 length -= n;
3730 data += n;
3731 offset += n;
3732 }
3733 return 0;
3734}
3735
3736static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3737 u8 *data)
3738{
3739 struct sky2_port *sky2 = netdev_priv(dev);
3740 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3741 int length = eeprom->len;
3742 u16 offset = eeprom->offset;
3743
3744 if (!cap)
3745 return -EINVAL;
3746
3747 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3748 return -EINVAL;
3749
3750 while (length > 0) {
3751 u32 val;
3752 int n = min_t(int, length, sizeof(val));
3753
3754 if (n < sizeof(val))
b32f40c4 3755 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3756 memcpy(&val, data, n);
3757
b32f40c4 3758 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3759
3760 length -= n;
3761 data += n;
3762 offset += n;
3763 }
3764 return 0;
3765}
3766
3767
7282d491 3768static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3769 .get_settings = sky2_get_settings,
3770 .set_settings = sky2_set_settings,
3771 .get_drvinfo = sky2_get_drvinfo,
3772 .get_wol = sky2_get_wol,
3773 .set_wol = sky2_set_wol,
3774 .get_msglevel = sky2_get_msglevel,
3775 .set_msglevel = sky2_set_msglevel,
3776 .nway_reset = sky2_nway_reset,
3777 .get_regs_len = sky2_get_regs_len,
3778 .get_regs = sky2_get_regs,
3779 .get_link = ethtool_op_get_link,
3780 .get_eeprom_len = sky2_get_eeprom_len,
3781 .get_eeprom = sky2_get_eeprom,
3782 .set_eeprom = sky2_set_eeprom,
f4331a6d 3783 .set_sg = ethtool_op_set_sg,
f4331a6d 3784 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3785 .set_tso = sky2_set_tso,
3786 .get_rx_csum = sky2_get_rx_csum,
3787 .set_rx_csum = sky2_set_rx_csum,
3788 .get_strings = sky2_get_strings,
3789 .get_coalesce = sky2_get_coalesce,
3790 .set_coalesce = sky2_set_coalesce,
3791 .get_ringparam = sky2_get_ringparam,
3792 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3793 .get_pauseparam = sky2_get_pauseparam,
3794 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3795 .phys_id = sky2_phys_id,
b9f2c044 3796 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3797 .get_ethtool_stats = sky2_get_ethtool_stats,
3798};
3799
3cf26753
SH		 3800#ifdef CONFIG_SKY2_DEBUG
3801
3802static struct dentry *sky2_debug;
3803
3804static int sky2_debug_show(struct seq_file *seq, void *v)
3805{
3806 struct net_device *dev = seq->private;
3807 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3808 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3809 unsigned port = sky2->port;
3810 unsigned idx, last;
3811 int sop;
3812
3813 if (!netif_running(dev))
3814 return -ENETDOWN;
3815
3816 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3817 sky2_read32(hw, B0_ISRC),
3818 sky2_read32(hw, B0_IMSK),
3819 sky2_read32(hw, B0_Y2_SP_ICR));
3820
bea3348e 3821 napi_disable(&hw->napi);
3cf26753
SH		 3822 last = sky2_read16(hw, STAT_PUT_IDX);
3823
3824 if (hw->st_idx == last)
3825 seq_puts(seq, "Status ring (empty)\n");
3826 else {
3827 seq_puts(seq, "Status ring\n");
3828 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3829 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3830 const struct sky2_status_le *le = hw->st_le + idx;
3831 seq_printf(seq, "[%d] %#x %d %#x\n",
3832 idx, le->opcode, le->length, le->status);
3833 }
3834 seq_puts(seq, "\n");
3835 }
3836
3837 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3838 sky2->tx_cons, sky2->tx_prod,
3839 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3840 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3841
3842 /* Dump contents of tx ring */
3843 sop = 1;
3844 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3845 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3846 const struct sky2_tx_le *le = sky2->tx_le + idx;
3847 u32 a = le32_to_cpu(le->addr);
3848
3849 if (sop)
3850 seq_printf(seq, "%u:", idx);
3851 sop = 0;
3852
3853 switch(le->opcode & ~HW_OWNER) {
3854 case OP_ADDR64:
3855 seq_printf(seq, " %#x:", a);
3856 break;
3857 case OP_LRGLEN:
3858 seq_printf(seq, " mtu=%d", a);
3859 break;
3860 case OP_VLAN:
3861 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3862 break;
3863 case OP_TCPLISW:
3864 seq_printf(seq, " csum=%#x", a);
3865 break;
3866 case OP_LARGESEND:
3867 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3868 break;
3869 case OP_PACKET:
3870 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3871 break;
3872 case OP_BUFFER:
3873 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3874 break;
3875 default:
3876 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3877 a, le16_to_cpu(le->length));
3878 }
3879
3880 if (le->ctrl & EOP) {
3881 seq_putc(seq, '\n');
3882 sop = 1;
3883 }
3884 }
3885
3886 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3887 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3888 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3889 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3890
d1d08d12 3891 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 3892 napi_enable(&hw->napi);
3cf26753
SH		 3893 return 0;
3894}
3895
3896static int sky2_debug_open(struct inode *inode, struct file *file)
3897{
3898 return single_open(file, sky2_debug_show, inode->i_private);
3899}
3900
3901static const struct file_operations sky2_debug_fops = {
3902 .owner = THIS_MODULE,
3903 .open = sky2_debug_open,
3904 .read = seq_read,
3905 .llseek = seq_lseek,
3906 .release = single_release,
3907};
3908
3909/*
3910 * Use network device events to create/remove/rename
3911 * debugfs file entries
3912 */
3913static int sky2_device_event(struct notifier_block *unused,
3914 unsigned long event, void *ptr)
3915{
3916 struct net_device *dev = ptr;
5b296bc9 3917 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3918
5b296bc9
SH		 3919 if (dev->open != sky2_up || !sky2_debug)
3920 return NOTIFY_DONE;
3cf26753 3921
5b296bc9
SH		 3922 switch(event) {
3923 case NETDEV_CHANGENAME:
3924 if (sky2->debugfs) {
3925 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3926 sky2_debug, dev->name);
3927 }
3928 break;
3cf26753 3929
5b296bc9
SH		 3930 case NETDEV_GOING_DOWN:
3931 if (sky2->debugfs) {
3932 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3933 dev->name);
3934 debugfs_remove(sky2->debugfs);
3935 sky2->debugfs = NULL;
3cf26753 3936 }
5b296bc9
SH		 3937 break;
3938
3939 case NETDEV_UP:
3940 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3941 sky2_debug, dev,
3942 &sky2_debug_fops);
3943 if (IS_ERR(sky2->debugfs))
3944 sky2->debugfs = NULL;
3cf26753
SH		 3945 }
3946
3947 return NOTIFY_DONE;
3948}
3949
3950static struct notifier_block sky2_notifier = {
3951 .notifier_call = sky2_device_event,
3952};
3953
3954
3955static __init void sky2_debug_init(void)
3956{
3957 struct dentry *ent;
3958
3959 ent = debugfs_create_dir("sky2", NULL);
3960 if (!ent || IS_ERR(ent))
3961 return;
3962
3963 sky2_debug = ent;
3964 register_netdevice_notifier(&sky2_notifier);
3965}
3966
3967static __exit void sky2_debug_cleanup(void)
3968{
3969 if (sky2_debug) {
3970 unregister_netdevice_notifier(&sky2_notifier);
3971 debugfs_remove(sky2_debug);
3972 sky2_debug = NULL;
3973 }
3974}
3975
3976#else
3977#define sky2_debug_init()
3978#define sky2_debug_cleanup()
3979#endif
3980
3981
cd28ab6a
SH		 3982/* Initialize network device */
3983static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 3984 unsigned port,
be63a21c 3985 int highmem, int wol)
cd28ab6a
SH		 3986{
3987 struct sky2_port *sky2;
3988 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3989
3990 if (!dev) {
898eb71c 3991 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 3992 return NULL;
3993 }
3994
cd28ab6a 3995 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3996 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3997 dev->open = sky2_up;
3998 dev->stop = sky2_down;
ef743d33 3999 dev->do_ioctl = sky2_ioctl;
cd28ab6a 4000 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 4001 dev->set_multicast_list = sky2_set_multicast;
4002 dev->set_mac_address = sky2_set_mac_address;
4003 dev->change_mtu = sky2_change_mtu;
4004 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4005 dev->tx_timeout = sky2_tx_timeout;
4006 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 4007#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 4008 if (port == 0)
4009 dev->poll_controller = sky2_netpoll;
cd28ab6a 4010#endif
cd28ab6a
SH		 4011
4012 sky2 = netdev_priv(dev);
4013 sky2->netdev = dev;
4014 sky2->hw = hw;
4015 sky2->msg_enable = netif_msg_init(debug, default_msg);
4016
cd28ab6a
SH		 4017 /* Auto speed and flow control */
4018 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4019 sky2->flow_mode = FC_BOTH;
4020
cd28ab6a
SH		 4021 sky2->duplex = -1;
4022 sky2->speed = -1;
4023 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4024 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4025 sky2->wol = wol;
75d070c5 4026
e07b1aa8 4027 spin_lock_init(&sky2->phy_lock);
793b883e 4028 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4029 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4030
4031 hw->dev[port] = dev;
4032
4033 sky2->port = port;
4034
4a50a876 4035 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4036 if (highmem)
4037 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4038
d1f13708 4039#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4040 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4041 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4042 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4043 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4044 dev->vlan_rx_register = sky2_vlan_rx_register;
4045 }
d1f13708
SH		 4046#endif
4047
cd28ab6a 4048 /* read the mac address */
793b883e 4049 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4050 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4051
cd28ab6a
SH		 4052 return dev;
4053}
4054
28bd181a 4055static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4056{
4057 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4058 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4059
4060 if (netif_msg_probe(sky2))
0795af57
JP		 4061 printk(KERN_INFO PFX "%s: addr %s\n",
4062 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4063}
4064
fb2690a9 4065/* Handle software interrupt used during MSI test */
7d12e780 4066static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4067{
4068 struct sky2_hw *hw = dev_id;
4069 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4070
4071 if (status == 0)
4072 return IRQ_NONE;
4073
4074 if (status & Y2_IS_IRQ_SW) {
ea76e635 4075 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4076 wake_up(&hw->msi_wait);
4077 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4078 }
4079 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4080
4081 return IRQ_HANDLED;
4082}
4083
4084/* Test interrupt path by forcing a a software IRQ */
4085static int __devinit sky2_test_msi(struct sky2_hw *hw)
4086{
4087 struct pci_dev *pdev = hw->pdev;
4088 int err;
4089
bb507fe1
SH		 4090 init_waitqueue_head (&hw->msi_wait);
4091
fb2690a9
SH		 4092 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4093
b0a20ded 4094 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4095 if (err) {
b02a9258 4096 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4097 return err;
4098 }
4099
fb2690a9 4100 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4101 sky2_read8(hw, B0_CTST);
fb2690a9 4102
ea76e635 4103 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4104
ea76e635 4105 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4106 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4107 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4108 "switching to INTx mode.\n");
fb2690a9
SH		 4109
4110 err = -EOPNOTSUPP;
4111 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4112 }
4113
4114 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4115 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4116
4117 free_irq(pdev->irq, hw);
4118
4119 return err;
4120}
4121
be63a21c
SH		 4122static int __devinit pci_wake_enabled(struct pci_dev *dev)
4123{
4124 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4125 u16 value;
4126
4127 if (!pm)
4128 return 0;
4129 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4130 return 0;
4131 return value & PCI_PM_CTRL_PME_ENABLE;
4132}
4133
cd28ab6a
SH		 4134static int __devinit sky2_probe(struct pci_dev *pdev,
4135 const struct pci_device_id *ent)
4136{
7f60c64b 4137 struct net_device *dev;
cd28ab6a 4138 struct sky2_hw *hw;
be63a21c 4139 int err, using_dac = 0, wol_default;
cd28ab6a 4140
793b883e
SH		 4141 err = pci_enable_device(pdev);
4142 if (err) {
b02a9258 4143 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4144 goto err_out;
4145 }
4146
793b883e
SH		 4147 err = pci_request_regions(pdev, DRV_NAME);
4148 if (err) {
b02a9258 4149 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4150 goto err_out_disable;
cd28ab6a
SH		 4151 }
4152
4153 pci_set_master(pdev);
4154
d1f3d4dd
SH		 4155 if (sizeof(dma_addr_t) > sizeof(u32) &&
4156 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4157 using_dac = 1;
4158 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4159 if (err < 0) {
b02a9258
SH		 4160 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4161 "for consistent allocations\n");
d1f3d4dd
SH		 4162 goto err_out_free_regions;
4163 }
d1f3d4dd 4164 } else {
cd28ab6a
SH		 4165 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4166 if (err) {
b02a9258 4167 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4168 goto err_out_free_regions;
4169 }
4170 }
d1f3d4dd 4171
be63a21c
SH		 4172 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4173
cd28ab6a 4174 err = -ENOMEM;
6aad85d6 4175 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4176 if (!hw) {
b02a9258 4177 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4178 goto err_out_free_regions;
4179 }
4180
cd28ab6a 4181 hw->pdev = pdev;
cd28ab6a
SH		 4182
4183 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4184 if (!hw->regs) {
b02a9258 4185 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4186 goto err_out_free_hw;
4187 }
4188
56a645cc 4189#ifdef __BIG_ENDIAN
f65b138c
SH		 4190 /* The sk98lin vendor driver uses hardware byte swapping but
4191 * this driver uses software swapping.
4192 */
56a645cc
SH		 4193 {
4194 u32 reg;
b32f40c4 4195 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4196 reg &= ~PCI_REV_DESC;
b32f40c4 4197 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4198 }
4199#endif
4200
08c06d8a 4201 /* ring for status responses */
167f53d0 4202 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4203 if (!hw->st_le)
4204 goto err_out_iounmap;
4205
e3173832 4206 err = sky2_init(hw);
cd28ab6a 4207 if (err)
793b883e 4208 goto err_out_iounmap;
cd28ab6a 4209
b02a9258 4210 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4211 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4212 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4213 hw->chip_id, hw->chip_rev);
cd28ab6a 4214
e3173832
SH		 4215 sky2_reset(hw);
4216
be63a21c 4217 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4218 if (!dev) {
4219 err = -ENOMEM;
cd28ab6a 4220 goto err_out_free_pci;
7f60c64b 4221 }
cd28ab6a 4222
9fa1b1f3
SH		 4223 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4224 err = sky2_test_msi(hw);
4225 if (err == -EOPNOTSUPP)
4226 pci_disable_msi(pdev);
4227 else if (err)
4228 goto err_out_free_netdev;
4229 }
4230
793b883e
SH		 4231 err = register_netdev(dev);
4232 if (err) {
b02a9258 4233 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4234 goto err_out_free_netdev;
4235 }
4236
6de16237
SH		 4237 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4238
ea76e635
SH		 4239 err = request_irq(pdev->irq, sky2_intr,
4240 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4241 dev->name, hw);
9fa1b1f3 4242 if (err) {
b02a9258 4243 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4244 goto err_out_unregister;
4245 }
4246 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4247 napi_enable(&hw->napi);
9fa1b1f3 4248
cd28ab6a
SH		 4249 sky2_show_addr(dev);
4250
7f60c64b 4251 if (hw->ports > 1) {
4252 struct net_device *dev1;
4253
be63a21c 4254 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4255 if (!dev1)
4256 dev_warn(&pdev->dev, "allocation for second device failed\n");
4257 else if ((err = register_netdev(dev1))) {
4258 dev_warn(&pdev->dev,
4259 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4260 hw->dev[1] = NULL;
4261 free_netdev(dev1);
b02a9258
SH		 4262 } else
4263 sky2_show_addr(dev1);
cd28ab6a
SH		 4264 }
4265
32c2c300 4266 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4267 INIT_WORK(&hw->restart_work, sky2_restart);
4268
793b883e
SH		 4269 pci_set_drvdata(pdev, hw);
4270
cd28ab6a
SH		 4271 return 0;
4272
793b883e 4273err_out_unregister:
ea76e635 4274 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4275 pci_disable_msi(pdev);
793b883e 4276 unregister_netdev(dev);
cd28ab6a
SH		 4277err_out_free_netdev:
4278 free_netdev(dev);
cd28ab6a 4279err_out_free_pci:
793b883e 4280 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4281 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4282err_out_iounmap:
4283 iounmap(hw->regs);
4284err_out_free_hw:
4285 kfree(hw);
4286err_out_free_regions:
4287 pci_release_regions(pdev);
44a1d2e5 4288err_out_disable:
cd28ab6a 4289 pci_disable_device(pdev);
cd28ab6a 4290err_out:
549a68c3 4291 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4292 return err;
4293}
4294
4295static void __devexit sky2_remove(struct pci_dev *pdev)
4296{
793b883e 4297 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4298 int i;
cd28ab6a 4299
793b883e 4300 if (!hw)
cd28ab6a
SH		 4301 return;
4302
32c2c300 4303 del_timer_sync(&hw->watchdog_timer);
6de16237 4304 cancel_work_sync(&hw->restart_work);
d27ed387 4305
b877fe28 4306 for (i = hw->ports-1; i >= 0; --i)
6de16237 4307 unregister_netdev(hw->dev[i]);
81906791 4308
d27ed387 4309 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4310
ae306cca
SH		 4311 sky2_power_aux(hw);
4312
cd28ab6a 4313 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4314 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4315 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4316
4317 free_irq(pdev->irq, hw);
ea76e635 4318 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4319 pci_disable_msi(pdev);
793b883e 4320 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4321 pci_release_regions(pdev);
4322 pci_disable_device(pdev);
793b883e 4323
b877fe28 4324 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4325 free_netdev(hw->dev[i]);
4326
cd28ab6a
SH		 4327 iounmap(hw->regs);
4328 kfree(hw);
5afa0a9c 4329
cd28ab6a
SH		 4330 pci_set_drvdata(pdev, NULL);
4331}
4332
4333#ifdef CONFIG_PM
4334static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4335{
793b883e 4336 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4337 int i, wol = 0;
cd28ab6a 4338
549a68c3
SH		 4339 if (!hw)
4340 return 0;
4341
063a0b38
SH		 4342 del_timer_sync(&hw->watchdog_timer);
4343 cancel_work_sync(&hw->restart_work);
4344
f05267e7 4345 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4346 struct net_device *dev = hw->dev[i];
e3173832 4347 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4348
063a0b38 4349 netif_device_detach(dev);
e3173832 4350 if (netif_running(dev))
5afa0a9c 4351 sky2_down(dev);
e3173832
SH		 4352
4353 if (sky2->wol)
4354 sky2_wol_init(sky2);
4355
4356 wol |= sky2->wol;
cd28ab6a
SH		 4357 }
4358
8ab8fca2 4359 sky2_write32(hw, B0_IMSK, 0);
6de16237 4360 napi_disable(&hw->napi);
ae306cca 4361 sky2_power_aux(hw);
e3173832 4362
d374c1c1 4363 pci_save_state(pdev);
e3173832 4364 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4365 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4366
2ccc99b7 4367 return 0;
cd28ab6a
SH		 4368}
4369
4370static int sky2_resume(struct pci_dev *pdev)
4371{
793b883e 4372 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4373 int i, err;
cd28ab6a 4374
549a68c3
SH		 4375 if (!hw)
4376 return 0;
4377
ae306cca
SH		 4378 err = pci_set_power_state(pdev, PCI_D0);
4379 if (err)
4380 goto out;
4381
4382 err = pci_restore_state(pdev);
4383 if (err)
4384 goto out;
4385
cd28ab6a 4386 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4387
4388 /* Re-enable all clocks */
05745c4a
SH		 4389 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4390 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4391 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4392 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4393
e3173832 4394 sky2_reset(hw);
8ab8fca2 4395 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4396 napi_enable(&hw->napi);
8ab8fca2 4397
f05267e7 4398 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4399 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4400
4401 netif_device_attach(dev);
6a5706b9 4402 if (netif_running(dev)) {
08c06d8a
SH		 4403 err = sky2_up(dev);
4404 if (err) {
4405 printk(KERN_ERR PFX "%s: could not up: %d\n",
4406 dev->name, err);
68c28898 4407 rtnl_lock();
08c06d8a 4408 dev_close(dev);
68c28898 4409 rtnl_unlock();
eb35cf60 4410 goto out;
5afa0a9c 4411 }
cd28ab6a
SH		 4412 }
4413 }
eb35cf60 4414
ae306cca 4415 return 0;
08c06d8a 4416out:
b02a9258 4417 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4418 pci_disable_device(pdev);
08c06d8a 4419 return err;
cd28ab6a
SH		 4420}
4421#endif
4422
e3173832
SH		 4423static void sky2_shutdown(struct pci_dev *pdev)
4424{
4425 struct sky2_hw *hw = pci_get_drvdata(pdev);
4426 int i, wol = 0;
4427
549a68c3
SH		 4428 if (!hw)
4429 return;
4430
5c0d6b34 4431 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4432
4433 for (i = 0; i < hw->ports; i++) {
4434 struct net_device *dev = hw->dev[i];
4435 struct sky2_port *sky2 = netdev_priv(dev);
4436
4437 if (sky2->wol) {
4438 wol = 1;
4439 sky2_wol_init(sky2);
4440 }
4441 }
4442
4443 if (wol)
4444 sky2_power_aux(hw);
4445
4446 pci_enable_wake(pdev, PCI_D3hot, wol);
4447 pci_enable_wake(pdev, PCI_D3cold, wol);
4448
4449 pci_disable_device(pdev);
4450 pci_set_power_state(pdev, PCI_D3hot);
4451
4452}
4453
cd28ab6a 4454static struct pci_driver sky2_driver = {
793b883e
SH		 4455 .name = DRV_NAME,
4456 .id_table = sky2_id_table,
4457 .probe = sky2_probe,
4458 .remove = __devexit_p(sky2_remove),
cd28ab6a 4459#ifdef CONFIG_PM
793b883e
SH		 4460 .suspend = sky2_suspend,
4461 .resume = sky2_resume,
cd28ab6a 4462#endif
e3173832 4463 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4464};
4465
4466static int __init sky2_init_module(void)
4467{
3cf26753 4468 sky2_debug_init();
50241c4c 4469 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4470}
4471
4472static void __exit sky2_cleanup_module(void)
4473{
4474 pci_unregister_driver(&sky2_driver);
3cf26753 4475 sky2_debug_cleanup();
cd28ab6a
SH		 4476}
4477
4478module_init(sky2_init_module);
4479module_exit(sky2_cleanup_module);
4480
4481MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4482MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4483MODULE_LICENSE("GPL");
5f4f9dc1 4484MODULE_VERSION(DRV_VERSION);
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