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sky2: enable clocks before probe
[mirror_ubuntu-jammy-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
93cd791e 53#define DRV_VERSION "1.14"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
78f0b62d 133// { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 134 { 0 }
135};
793b883e 136
cd28ab6a
SH		 137MODULE_DEVICE_TABLE(pci, sky2_id_table);
138
139/* Avoid conditionals by using array */
140static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
141static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 142static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 143
92f965e8
SH		 144/* This driver supports yukon2 chipset only */
145static const char *yukon2_name[] = {
146 "XL", /* 0xb3 */
147 "EC Ultra", /* 0xb4 */
93745494 148 "Extreme", /* 0xb5 */
92f965e8
SH		 149 "EC", /* 0xb6 */
150 "FE", /* 0xb7 */
793b883e
SH		 151};
152
793b883e 153/* Access to external PHY */
ef743d33 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 155{
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 164 return 0;
793b883e 165 udelay(1);
cd28ab6a 166 }
ef743d33 167
793b883e 168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 169 return -ETIMEDOUT;
cd28ab6a
SH		 170}
171
ef743d33 172static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 173{
174 int i;
175
793b883e 176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 177 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
178
179 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
181 *val = gma_read16(hw, port, GM_SMI_DATA);
182 return 0;
183 }
184
793b883e 185 udelay(1);
cd28ab6a
SH		 186 }
187
ef743d33
SH		 188 return -ETIMEDOUT;
189}
190
191static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
192{
193 u16 v;
194
195 if (__gm_phy_read(hw, port, reg, &v) != 0)
196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
197 return v;
cd28ab6a
SH		 198}
199
5afa0a9c 200
ae306cca
SH		 201static void sky2_power_on(struct sky2_hw *hw)
202{
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 206
ae306cca
SH		 207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 209
ae306cca
SH		 210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 218
93745494 219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 220 u32 reg;
5afa0a9c 221
fc99fe06
SH		 222 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
223 /* set all bits to 0 except bits 15..12 and 8 */
224 reg &= P_ASPM_CONTROL_MSK;
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
226
227 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
228 /* set all bits to 0 except bits 28 & 27 */
229 reg &= P_CTL_TIM_VMAIN_AV_MSK;
230 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
231
232 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
5afa0a9c 233 }
ae306cca 234}
5afa0a9c 235
ae306cca
SH		 236static void sky2_power_aux(struct sky2_hw *hw)
237{
238 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
239 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
240 else
241 /* enable bits are inverted */
242 sky2_write8(hw, B2_Y2_CLK_GATE,
243 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
244 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
245 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
246
247 /* switch power to VAUX */
248 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
249 sky2_write8(hw, B0_POWER_CTRL,
250 (PC_VAUX_ENA | PC_VCC_ENA |
251 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 252}
253
d3bcfbeb 254static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 255{
256 u16 reg;
257
258 /* disable all GMAC IRQ's */
259 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
260 /* disable PHY IRQs */
261 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 262
cd28ab6a
SH		 263 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
264 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
265 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
266 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
267
268 reg = gma_read16(hw, port, GM_RX_CTRL);
269 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
270 gma_write16(hw, port, GM_RX_CTRL, reg);
271}
272
16ad91e1
SH		 273/* flow control to advertise bits */
274static const u16 copper_fc_adv[] = {
275 [FC_NONE] = 0,
276 [FC_TX] = PHY_M_AN_ASP,
277 [FC_RX] = PHY_M_AN_PC,
278 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
279};
280
281/* flow control to advertise bits when using 1000BaseX */
282static const u16 fiber_fc_adv[] = {
283 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
284 [FC_TX] = PHY_M_P_ASYM_MD_X,
285 [FC_RX] = PHY_M_P_SYM_MD_X,
286 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
287};
288
289/* flow control to GMA disable bits */
290static const u16 gm_fc_disable[] = {
291 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
292 [FC_TX] = GM_GPCR_FC_RX_DIS,
293 [FC_RX] = GM_GPCR_FC_TX_DIS,
294 [FC_BOTH] = 0,
295};
296
297
cd28ab6a
SH		 298static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
299{
300 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 301 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 302
93745494
SH		 303 if (sky2->autoneg == AUTONEG_ENABLE
304 && !(hw->chip_id == CHIP_ID_YUKON_XL
305 || hw->chip_id == CHIP_ID_YUKON_EC_U
306 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 307 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
308
309 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 310 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 311 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
312
53419c68 313 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 314 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 315 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 316 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
317 else
53419c68
SH		 318 /* set master & slave downshift counter to 1x */
319 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 320
321 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
322 }
323
324 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 325 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 326 if (hw->chip_id == CHIP_ID_YUKON_FE) {
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
329 } else {
330 /* disable energy detect */
331 ctrl &= ~PHY_M_PC_EN_DET_MSK;
332
333 /* enable automatic crossover */
334 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
335
53419c68 336 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 337 if (sky2->autoneg == AUTONEG_ENABLE
338 && (hw->chip_id == CHIP_ID_YUKON_XL
339 || hw->chip_id == CHIP_ID_YUKON_EC_U
340 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 341 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 342 ctrl &= ~PHY_M_PC_DSC_MSK;
343 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
344 }
345 }
cd28ab6a
SH		 346 } else {
347 /* workaround for deviation #4.88 (CRC errors) */
348 /* disable Automatic Crossover */
349
350 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 351 }
cd28ab6a 352
b89165f2
SH		 353 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
354
355 /* special setup for PHY 88E1112 Fiber */
356 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
357 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 358
b89165f2
SH		 359 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
360 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
361 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
362 ctrl &= ~PHY_M_MAC_MD_MSK;
363 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
364 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
365
366 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 367 /* select page 1 to access Fiber registers */
368 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 369
370 /* for SFP-module set SIGDET polarity to low */
371 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
372 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 373 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 374 }
b89165f2
SH		 375
376 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 377 }
378
7800fddc 379 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 380 ct1000 = 0;
381 adv = PHY_AN_CSMA;
2eaba1a2 382 reg = 0;
cd28ab6a
SH		 383
384 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 385 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 386 if (sky2->advertising & ADVERTISED_1000baseT_Full)
387 ct1000 |= PHY_M_1000C_AFD;
388 if (sky2->advertising & ADVERTISED_1000baseT_Half)
389 ct1000 |= PHY_M_1000C_AHD;
390 if (sky2->advertising & ADVERTISED_100baseT_Full)
391 adv |= PHY_M_AN_100_FD;
392 if (sky2->advertising & ADVERTISED_100baseT_Half)
393 adv |= PHY_M_AN_100_HD;
394 if (sky2->advertising & ADVERTISED_10baseT_Full)
395 adv |= PHY_M_AN_10_FD;
396 if (sky2->advertising & ADVERTISED_10baseT_Half)
397 adv |= PHY_M_AN_10_HD;
709c6e7b 398
16ad91e1 399 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 400 } else { /* special defines for FIBER (88E1040S only) */
401 if (sky2->advertising & ADVERTISED_1000baseT_Full)
402 adv |= PHY_M_AN_1000X_AFD;
403 if (sky2->advertising & ADVERTISED_1000baseT_Half)
404 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 405
16ad91e1 406 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 407 }
cd28ab6a
SH		 408
409 /* Restart Auto-negotiation */
410 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
411 } else {
412 /* forced speed/duplex settings */
413 ct1000 = PHY_M_1000C_MSE;
414
2eaba1a2
SH		 415 /* Disable auto update for duplex flow control and speed */
416 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 417
418 switch (sky2->speed) {
419 case SPEED_1000:
420 ctrl |= PHY_CT_SP1000;
2eaba1a2 421 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 422 break;
423 case SPEED_100:
424 ctrl |= PHY_CT_SP100;
2eaba1a2 425 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 426 break;
427 }
428
2eaba1a2
SH		 429 if (sky2->duplex == DUPLEX_FULL) {
430 reg |= GM_GPCR_DUP_FULL;
431 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 432 } else if (sky2->speed < SPEED_1000)
433 sky2->flow_mode = FC_NONE;
2eaba1a2 434
2eaba1a2 435
16ad91e1 436 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 437
438 /* Forward pause packets to GMAC? */
16ad91e1 439 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 440 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
441 else
442 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 443 }
444
2eaba1a2
SH		 445 gma_write16(hw, port, GM_GP_CTRL, reg);
446
cd28ab6a
SH		 447 if (hw->chip_id != CHIP_ID_YUKON_FE)
448 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
449
450 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
451 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
452
453 /* Setup Phy LED's */
454 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
455 ledover = 0;
456
457 switch (hw->chip_id) {
458 case CHIP_ID_YUKON_FE:
459 /* on 88E3082 these bits are at 11..9 (shifted left) */
460 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
461
462 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
463
464 /* delete ACT LED control bits */
465 ctrl &= ~PHY_M_FELP_LED1_MSK;
466 /* change ACT LED control to blink mode */
467 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
468 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
469 break;
470
471 case CHIP_ID_YUKON_XL:
793b883e 472 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 473
474 /* select page 3 to access LED control register */
475 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
476
477 /* set LED Function Control register */
ed6d32c7
SH		 478 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
479 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
480 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
481 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
482 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 483
484 /* set Polarity Control register */
485 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 486 (PHY_M_POLC_LS1_P_MIX(4) |
487 PHY_M_POLC_IS0_P_MIX(4) |
488 PHY_M_POLC_LOS_CTRL(2) |
489 PHY_M_POLC_INIT_CTRL(2) |
490 PHY_M_POLC_STA1_CTRL(2) |
491 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 492
493 /* restore page register */
793b883e 494 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 495 break;
93745494 496
ed6d32c7 497 case CHIP_ID_YUKON_EC_U:
93745494 498 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 499 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
500
501 /* select page 3 to access LED control register */
502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
503
504 /* set LED Function Control register */
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
506 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
507 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
508 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
509 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
510
511 /* set Blink Rate in LED Timer Control Register */
512 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
513 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
514 /* restore page register */
515 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
516 break;
cd28ab6a
SH		 517
518 default:
519 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
520 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
521 /* turn off the Rx LED (LED_RX) */
0efdf262 522 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 523 }
524
9467a8fc
SH		 525 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
526 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 527 /* apply fixes in PHY AFE */
ed6d32c7
SH		 528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
529
977bdf06 530 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 531 gm_phy_write(hw, port, 0x18, 0xaa99);
532 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 533
977bdf06 534 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 535 gm_phy_write(hw, port, 0x18, 0xa204);
536 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 537
538 /* set page register to 0 */
9467a8fc 539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 540 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 541 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 542
977bdf06
SH		 543 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
544 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 545 ledover |= PHY_M_LED_MO_100;
977bdf06 546 }
cd28ab6a 547
977bdf06
SH		 548 if (ledover)
549 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
550
551 }
2eaba1a2 552
d571b694 553 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 554 if (sky2->autoneg == AUTONEG_ENABLE)
555 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
556 else
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
558}
559
d3bcfbeb
SH		 560static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
561{
562 u32 reg1;
563 static const u32 phy_power[]
564 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
565
566 /* looks like this XL is back asswards .. */
567 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
568 onoff = !onoff;
569
aed2cec4 570 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 571 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 572 if (onoff)
573 /* Turn off phy power saving */
574 reg1 &= ~phy_power[port];
575 else
576 reg1 |= phy_power[port];
577
578 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 579 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 580 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 581 udelay(100);
582}
583
1b537565
SH		 584/* Force a renegotiation */
585static void sky2_phy_reinit(struct sky2_port *sky2)
586{
e07b1aa8 587 spin_lock_bh(&sky2->phy_lock);
1b537565 588 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 589 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 590}
591
e3173832
SH		 592/* Put device in state to listen for Wake On Lan */
593static void sky2_wol_init(struct sky2_port *sky2)
594{
595 struct sky2_hw *hw = sky2->hw;
596 unsigned port = sky2->port;
597 enum flow_control save_mode;
598 u16 ctrl;
599 u32 reg1;
600
601 /* Bring hardware out of reset */
602 sky2_write16(hw, B0_CTST, CS_RST_CLR);
603 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
604
605 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
606 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
607
608 /* Force to 10/100
609 * sky2_reset will re-enable on resume
610 */
611 save_mode = sky2->flow_mode;
612 ctrl = sky2->advertising;
613
614 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
615 sky2->flow_mode = FC_NONE;
616 sky2_phy_power(hw, port, 1);
617 sky2_phy_reinit(sky2);
618
619 sky2->flow_mode = save_mode;
620 sky2->advertising = ctrl;
621
622 /* Set GMAC to no flow control and auto update for speed/duplex */
623 gma_write16(hw, port, GM_GP_CTRL,
624 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
625 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
626
627 /* Set WOL address */
628 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
629 sky2->netdev->dev_addr, ETH_ALEN);
630
631 /* Turn on appropriate WOL control bits */
632 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
633 ctrl = 0;
634 if (sky2->wol & WAKE_PHY)
635 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
636 else
637 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
638
639 if (sky2->wol & WAKE_MAGIC)
640 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
641 else
642 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
643
644 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
645 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
646
647 /* Turn on legacy PCI-Express PME mode */
648 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
649 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
650 reg1 |= PCI_Y2_PME_LEGACY;
651 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
652 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
653
654 /* block receiver */
655 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
656
657}
658
cd28ab6a
SH		 659static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
660{
661 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
662 u16 reg;
663 int i;
664 const u8 *addr = hw->dev[port]->dev_addr;
665
42eeea01 666 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
b4ed372b 667 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 668
669 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
670
793b883e 671 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 672 /* WA DEV_472 -- looks like crossed wires on port 2 */
673 /* clear GMAC 1 Control reset */
674 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
675 do {
676 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
677 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
678 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
679 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
680 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
681 }
682
793b883e 683 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 684
2eaba1a2
SH		 685 /* Enable Transmit FIFO Underrun */
686 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
687
e07b1aa8 688 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 689 sky2_phy_init(hw, port);
e07b1aa8 690 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 691
692 /* MIB clear */
693 reg = gma_read16(hw, port, GM_PHY_ADDR);
694 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
695
43f2f104
SH		 696 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
697 gma_read16(hw, port, i);
cd28ab6a
SH		 698 gma_write16(hw, port, GM_PHY_ADDR, reg);
699
700 /* transmit control */
701 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
702
703 /* receive control reg: unicast + multicast + no FCS */
704 gma_write16(hw, port, GM_RX_CTRL,
793b883e 705 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 706
707 /* transmit flow control */
708 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
709
710 /* transmit parameter */
711 gma_write16(hw, port, GM_TX_PARAM,
712 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
713 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
714 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
715 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
716
717 /* serial mode register */
718 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 719 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 720
6b1a3aef 721 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 722 reg |= GM_SMOD_JUMBO_ENA;
723
724 gma_write16(hw, port, GM_SERIAL_MODE, reg);
725
cd28ab6a
SH		 726 /* virtual address for data */
727 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
728
793b883e
SH		 729 /* physical address: used for pause frames */
730 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
731
732 /* ignore counter overflows */
cd28ab6a
SH		 733 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
734 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
735 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
736
737 /* Configure Rx MAC FIFO */
738 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 739 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
740 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 741
d571b694 742 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 743 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 744
8df9a876
SH		 745 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
746 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 747
748 /* Configure Tx MAC FIFO */
749 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
750 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 751
93745494 752 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 753 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 754 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98
SH		 755
756 /* set Tx GMAC FIFO Almost Empty Threshold */
757 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
758 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
759
760 if (hw->dev[port]->mtu > ETH_DATA_LEN)
761 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
762 TX_JUMBO_ENA | TX_STFW_DIS);
763 else
764 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
765 TX_JUMBO_DIS | TX_STFW_ENA);
5a5b1ea0
SH		 766 }
767
cd28ab6a
SH		 768}
769
67712901
SH		 770/* Assign Ram Buffer allocation to queue */
771static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 772{
67712901
SH		 773 u32 end;
774
775 /* convert from K bytes to qwords used for hw register */
776 start *= 1024/8;
777 space *= 1024/8;
778 end = start + space - 1;
793b883e 779
cd28ab6a
SH		 780 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
781 sky2_write32(hw, RB_ADDR(q, RB_START), start);
782 sky2_write32(hw, RB_ADDR(q, RB_END), end);
783 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
784 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
785
786 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 787 u32 tp = space - space/4;
793b883e 788
1c28f6ba
SH		 789 /* On receive queue's set the thresholds
790 * give receiver priority when > 3/4 full
791 * send pause when down to 2K
792 */
793 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
794 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 795
1c28f6ba
SH		 796 tp = space - 2048/8;
797 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
798 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 799 } else {
800 /* Enable store & forward on Tx queue's because
801 * Tx FIFO is only 1K on Yukon
802 */
803 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
804 }
805
806 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 807 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 808}
809
cd28ab6a 810/* Setup Bus Memory Interface */
af4ed7e6 811static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 812{
813 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
814 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
815 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 816 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 817}
818
cd28ab6a
SH		 819/* Setup prefetch unit registers. This is the interface between
820 * hardware and driver list elements
821 */
8cc048e3 822static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 823 u64 addr, u32 last)
824{
cd28ab6a
SH		 825 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
826 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
827 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
828 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
829 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
830 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 831
832 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 833}
834
793b883e
SH		 835static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
836{
837 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
838
cb5d9547 839 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 840 le->ctrl = 0;
793b883e
SH		 841 return le;
842}
cd28ab6a 843
291ea614
SH		 844static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
845 struct sky2_tx_le *le)
846{
847 return sky2->tx_ring + (le - sky2->tx_le);
848}
849
290d4de5
SH		 850/* Update chip's next pointer */
851static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 852{
50432cb5 853 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 854 wmb();
50432cb5
SH		 855 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
856
857 /* Synchronize I/O on since next processor may write to tail */
858 mmiowb();
cd28ab6a
SH		 859}
860
793b883e 861
cd28ab6a
SH		 862static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
863{
864 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 865 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 866 le->ctrl = 0;
cd28ab6a
SH		 867 return le;
868}
869
a018e330
SH		 870/* Return high part of DMA address (could be 32 or 64 bit) */
871static inline u32 high32(dma_addr_t a)
872{
a036119f 873 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 874}
875
14d0263f
SH		 876/* Build description to hardware for one receive segment */
877static void sky2_rx_add(struct sky2_port *sky2, u8 op,
878 dma_addr_t map, unsigned len)
cd28ab6a
SH		 879{
880 struct sky2_rx_le *le;
734d1868 881 u32 hi = high32(map);
cd28ab6a 882
793b883e 883 if (sky2->rx_addr64 != hi) {
cd28ab6a 884 le = sky2_next_rx(sky2);
793b883e 885 le->addr = cpu_to_le32(hi);
cd28ab6a 886 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 887 sky2->rx_addr64 = high32(map + len);
cd28ab6a 888 }
793b883e 889
cd28ab6a 890 le = sky2_next_rx(sky2);
734d1868
SH		 891 le->addr = cpu_to_le32((u32) map);
892 le->length = cpu_to_le16(len);
14d0263f 893 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 894}
895
14d0263f
SH		 896/* Build description to hardware for one possibly fragmented skb */
897static void sky2_rx_submit(struct sky2_port *sky2,
898 const struct rx_ring_info *re)
899{
900 int i;
901
902 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
903
904 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
905 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
906}
907
908
909static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
910 unsigned size)
911{
912 struct sk_buff *skb = re->skb;
913 int i;
914
915 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
916 pci_unmap_len_set(re, data_size, size);
917
918 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
919 re->frag_addr[i] = pci_map_page(pdev,
920 skb_shinfo(skb)->frags[i].page,
921 skb_shinfo(skb)->frags[i].page_offset,
922 skb_shinfo(skb)->frags[i].size,
923 PCI_DMA_FROMDEVICE);
924}
925
926static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
927{
928 struct sk_buff *skb = re->skb;
929 int i;
930
931 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
932 PCI_DMA_FROMDEVICE);
933
934 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
935 pci_unmap_page(pdev, re->frag_addr[i],
936 skb_shinfo(skb)->frags[i].size,
937 PCI_DMA_FROMDEVICE);
938}
793b883e 939
cd28ab6a
SH		 940/* Tell chip where to start receive checksum.
941 * Actually has two checksums, but set both same to avoid possible byte
942 * order problems.
943 */
793b883e 944static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 945{
946 struct sky2_rx_le *le;
947
cd28ab6a 948 le = sky2_next_rx(sky2);
f65b138c 949 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 950 le->ctrl = 0;
951 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 952
793b883e
SH		 953 sky2_write32(sky2->hw,
954 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
955 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 956
957}
958
6b1a3aef
SH		 959/*
960 * The RX Stop command will not work for Yukon-2 if the BMU does not
961 * reach the end of packet and since we can't make sure that we have
962 * incoming data, we must reset the BMU while it is not doing a DMA
963 * transfer. Since it is possible that the RX path is still active,
964 * the RX RAM buffer will be stopped first, so any possible incoming
965 * data will not trigger a DMA. After the RAM buffer is stopped, the
966 * BMU is polled until any DMA in progress is ended and only then it
967 * will be reset.
968 */
969static void sky2_rx_stop(struct sky2_port *sky2)
970{
971 struct sky2_hw *hw = sky2->hw;
972 unsigned rxq = rxqaddr[sky2->port];
973 int i;
974
975 /* disable the RAM Buffer receive queue */
976 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
977
978 for (i = 0; i < 0xffff; i++)
979 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
980 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
981 goto stopped;
982
983 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
984 sky2->netdev->name);
985stopped:
986 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
987
988 /* reset the Rx prefetch unit */
989 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 990 mmiowb();
6b1a3aef 991}
793b883e 992
d571b694 993/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 994static void sky2_rx_clean(struct sky2_port *sky2)
995{
996 unsigned i;
997
998 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 999 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1000 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1001
1002 if (re->skb) {
14d0263f 1003 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1004 kfree_skb(re->skb);
1005 re->skb = NULL;
1006 }
1007 }
1008}
1009
ef743d33
SH		 1010/* Basic MII support */
1011static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1012{
1013 struct mii_ioctl_data *data = if_mii(ifr);
1014 struct sky2_port *sky2 = netdev_priv(dev);
1015 struct sky2_hw *hw = sky2->hw;
1016 int err = -EOPNOTSUPP;
1017
1018 if (!netif_running(dev))
1019 return -ENODEV; /* Phy still in reset */
1020
d89e1343 1021 switch (cmd) {
ef743d33
SH		 1022 case SIOCGMIIPHY:
1023 data->phy_id = PHY_ADDR_MARV;
1024
1025 /* fallthru */
1026 case SIOCGMIIREG: {
1027 u16 val = 0;
91c86df5 1028
e07b1aa8 1029 spin_lock_bh(&sky2->phy_lock);
ef743d33 1030 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1031 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1032
ef743d33
SH		 1033 data->val_out = val;
1034 break;
1035 }
1036
1037 case SIOCSMIIREG:
1038 if (!capable(CAP_NET_ADMIN))
1039 return -EPERM;
1040
e07b1aa8 1041 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1042 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1043 data->val_in);
e07b1aa8 1044 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1045 break;
1046 }
1047 return err;
1048}
1049
d1f13708
SH		 1050#ifdef SKY2_VLAN_TAG_USED
1051static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1052{
1053 struct sky2_port *sky2 = netdev_priv(dev);
1054 struct sky2_hw *hw = sky2->hw;
1055 u16 port = sky2->port;
d1f13708 1056
2bb8c262 1057 netif_tx_lock_bh(dev);
3d4e66f5 1058 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1059
d1f13708 1060 sky2->vlgrp = grp;
3d4e66f5
SH		 1061 if (grp) {
1062 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1063 RX_VLAN_STRIP_ON);
1064 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1065 TX_VLAN_TAG_ON);
1066 } else {
1067 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1068 RX_VLAN_STRIP_OFF);
1069 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1070 TX_VLAN_TAG_OFF);
1071 }
d1f13708 1072
3d4e66f5 1073 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1074 netif_tx_unlock_bh(dev);
d1f13708
SH		 1075}
1076#endif
1077
82788c7a 1078/*
14d0263f
SH		 1079 * Allocate an skb for receiving. If the MTU is large enough
1080 * make the skb non-linear with a fragment list of pages.
1081 *
82788c7a
SH		 1082 * It appears the hardware has a bug in the FIFO logic that
1083 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1084 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1085 * aligned except if slab debugging is enabled.
82788c7a 1086 */
14d0263f 1087static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1088{
1089 struct sk_buff *skb;
14d0263f
SH		 1090 unsigned long p;
1091 int i;
82788c7a 1092
14d0263f
SH		 1093 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1094 if (!skb)
1095 goto nomem;
1096
1097 p = (unsigned long) skb->data;
1098 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1099
1100 for (i = 0; i < sky2->rx_nfrags; i++) {
1101 struct page *page = alloc_page(GFP_ATOMIC);
1102
1103 if (!page)
1104 goto free_partial;
1105 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1106 }
1107
1108 return skb;
14d0263f
SH		 1109free_partial:
1110 kfree_skb(skb);
1111nomem:
1112 return NULL;
82788c7a
SH		 1113}
1114
cd28ab6a
SH		 1115/*
1116 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1117 * Normal case this ends up creating one list element for skb
1118 * in the receive ring. Worst case if using large MTU and each
1119 * allocation falls on a different 64 bit region, that results
1120 * in 6 list elements per ring entry.
1121 * One element is used for checksum enable/disable, and one
1122 * extra to avoid wrap.
cd28ab6a 1123 */
6b1a3aef 1124static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1125{
6b1a3aef 1126 struct sky2_hw *hw = sky2->hw;
14d0263f 1127 struct rx_ring_info *re;
6b1a3aef 1128 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1129 unsigned i, size, space, thresh;
cd28ab6a 1130
6b1a3aef 1131 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1132 sky2_qset(hw, rxq);
977bdf06 1133
c3905bc4
SH		 1134 /* On PCI express lowering the watermark gives better performance */
1135 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1136 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1137
1138 /* These chips have no ram buffer?
1139 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1140 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1141 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1142 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1143 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1144
6b1a3aef
SH		 1145 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1146
1147 rx_set_checksum(sky2);
14d0263f
SH		 1148
1149 /* Space needed for frame data + headers rounded up */
1150 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1151 + 8;
1152
1153 /* Stopping point for hardware truncation */
1154 thresh = (size - 8) / sizeof(u32);
1155
1156 /* Account for overhead of skb - to avoid order > 0 allocation */
1157 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1158 + sizeof(struct skb_shared_info);
1159
1160 sky2->rx_nfrags = space >> PAGE_SHIFT;
1161 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1162
1163 if (sky2->rx_nfrags != 0) {
1164 /* Compute residue after pages */
1165 space = sky2->rx_nfrags << PAGE_SHIFT;
1166
1167 if (space < size)
1168 size -= space;
1169 else
1170 size = 0;
1171
1172 /* Optimize to handle small packets and headers */
1173 if (size < copybreak)
1174 size = copybreak;
1175 if (size < ETH_HLEN)
1176 size = ETH_HLEN;
1177 }
1178 sky2->rx_data_size = size;
1179
1180 /* Fill Rx ring */
793b883e 1181 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1182 re = sky2->rx_ring + i;
cd28ab6a 1183
14d0263f 1184 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1185 if (!re->skb)
1186 goto nomem;
1187
14d0263f
SH		 1188 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1189 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1190 }
1191
a1433ac4
SH		 1192 /*
1193 * The receiver hangs if it receives frames larger than the
1194 * packet buffer. As a workaround, truncate oversize frames, but
1195 * the register is limited to 9 bits, so if you do frames > 2052
1196 * you better get the MTU right!
1197 */
a1433ac4
SH		 1198 if (thresh > 0x1ff)
1199 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1200 else {
1201 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1202 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1203 }
1204
6b1a3aef 1205 /* Tell chip about available buffers */
50432cb5 1206 sky2_put_idx(hw, rxq, sky2->rx_put);
cd28ab6a
SH		 1207 return 0;
1208nomem:
1209 sky2_rx_clean(sky2);
1210 return -ENOMEM;
1211}
1212
1213/* Bring up network interface. */
1214static int sky2_up(struct net_device *dev)
1215{
1216 struct sky2_port *sky2 = netdev_priv(dev);
1217 struct sky2_hw *hw = sky2->hw;
1218 unsigned port = sky2->port;
67712901 1219 u32 ramsize, imask;
ee7abb04 1220 int cap, err = -ENOMEM;
843a46f4 1221 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1222
ee7abb04
SH		 1223 /*
1224 * On dual port PCI-X card, there is an problem where status
1225 * can be received out of order due to split transactions
843a46f4 1226 */
ee7abb04
SH		 1227 if (otherdev && netif_running(otherdev) &&
1228 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1229 struct sky2_port *osky2 = netdev_priv(otherdev);
1230 u16 cmd;
1231
1232 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1233 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1234 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1235
1236 sky2->rx_csum = 0;
1237 osky2->rx_csum = 0;
1238 }
843a46f4 1239
cd28ab6a
SH		 1240 if (netif_msg_ifup(sky2))
1241 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1242
1243 /* must be power of 2 */
1244 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1245 TX_RING_SIZE *
1246 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1247 &sky2->tx_le_map);
1248 if (!sky2->tx_le)
1249 goto err_out;
1250
6cdbbdf3 1251 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1252 GFP_KERNEL);
1253 if (!sky2->tx_ring)
1254 goto err_out;
1255 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1256
1257 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1258 &sky2->rx_le_map);
1259 if (!sky2->rx_le)
1260 goto err_out;
1261 memset(sky2->rx_le, 0, RX_LE_BYTES);
1262
291ea614 1263 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1264 GFP_KERNEL);
1265 if (!sky2->rx_ring)
1266 goto err_out;
1267
d3bcfbeb
SH		 1268 sky2_phy_power(hw, port, 1);
1269
cd28ab6a
SH		 1270 sky2_mac_init(hw, port);
1271
67712901
SH		 1272 /* Register is number of 4K blocks on internal RAM buffer. */
1273 ramsize = sky2_read8(hw, B2_E_0) * 4;
1274 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1275
67712901
SH		 1276 if (ramsize > 0) {
1277 u32 rxspace;
cd28ab6a 1278
67712901
SH		 1279 if (ramsize < 16)
1280 rxspace = ramsize / 2;
1281 else
1282 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1283
67712901
SH		 1284 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1285 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1286
1287 /* Make sure SyncQ is disabled */
1288 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1289 RB_RST_SET);
1290 }
793b883e 1291
af4ed7e6 1292 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1293
977bdf06 1294 /* Set almost empty threshold */
c2716fb4
SH		 1295 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1296 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1297 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1298
6b1a3aef
SH		 1299 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1300 TX_RING_SIZE - 1);
cd28ab6a 1301
6b1a3aef 1302 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1303 if (err)
1304 goto err_out;
1305
cd28ab6a 1306 /* Enable interrupts from phy/mac for port */
e07b1aa8 1307 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1308 imask |= portirq_msk[port];
e07b1aa8
SH		 1309 sky2_write32(hw, B0_IMSK, imask);
1310
cd28ab6a
SH		 1311 return 0;
1312
1313err_out:
1b537565 1314 if (sky2->rx_le) {
cd28ab6a
SH		 1315 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1316 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1317 sky2->rx_le = NULL;
1318 }
1319 if (sky2->tx_le) {
cd28ab6a
SH		 1320 pci_free_consistent(hw->pdev,
1321 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1322 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1323 sky2->tx_le = NULL;
1324 }
1325 kfree(sky2->tx_ring);
1326 kfree(sky2->rx_ring);
cd28ab6a 1327
1b537565
SH		 1328 sky2->tx_ring = NULL;
1329 sky2->rx_ring = NULL;
cd28ab6a
SH		 1330 return err;
1331}
1332
793b883e
SH		 1333/* Modular subtraction in ring */
1334static inline int tx_dist(unsigned tail, unsigned head)
1335{
cb5d9547 1336 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1337}
cd28ab6a 1338
793b883e
SH		 1339/* Number of list elements available for next tx */
1340static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1341{
793b883e 1342 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1343}
1344
793b883e 1345/* Estimate of number of transmit list elements required */
28bd181a 1346static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1347{
793b883e
SH		 1348 unsigned count;
1349
1350 count = sizeof(dma_addr_t) / sizeof(u32);
1351 count += skb_shinfo(skb)->nr_frags * count;
1352
89114afd 1353 if (skb_is_gso(skb))
793b883e
SH		 1354 ++count;
1355
84fa7933 1356 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1357 ++count;
1358
1359 return count;
cd28ab6a
SH		 1360}
1361
793b883e
SH		 1362/*
1363 * Put one packet in ring for transmit.
1364 * A single packet can generate multiple list elements, and
1365 * the number of ring elements will probably be less than the number
1366 * of list elements used.
1367 */
cd28ab6a
SH		 1368static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1369{
1370 struct sky2_port *sky2 = netdev_priv(dev);
1371 struct sky2_hw *hw = sky2->hw;
d1f13708 1372 struct sky2_tx_le *le = NULL;
6cdbbdf3 1373 struct tx_ring_info *re;
cd28ab6a
SH		 1374 unsigned i, len;
1375 dma_addr_t mapping;
1376 u32 addr64;
1377 u16 mss;
1378 u8 ctrl;
1379
2bb8c262
SH		 1380 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1381 return NETDEV_TX_BUSY;
cd28ab6a 1382
793b883e 1383 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1384 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1385 dev->name, sky2->tx_prod, skb->len);
1386
cd28ab6a
SH		 1387 len = skb_headlen(skb);
1388 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1389 addr64 = high32(mapping);
793b883e 1390
a018e330
SH		 1391 /* Send high bits if changed or crosses boundary */
1392 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1393 le = get_tx_le(sky2);
f65b138c 1394 le->addr = cpu_to_le32(addr64);
793b883e 1395 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1396 sky2->tx_addr64 = high32(mapping + len);
793b883e 1397 }
cd28ab6a
SH		 1398
1399 /* Check for TCP Segmentation Offload */
7967168c 1400 mss = skb_shinfo(skb)->gso_size;
793b883e 1401 if (mss != 0) {
ab6a5bb6 1402 mss += tcp_optlen(skb); /* TCP options */
c9bdd4b5 1403 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
cd28ab6a
SH		 1404 mss += ETH_HLEN;
1405
e07560cd
SH		 1406 if (mss != sky2->tx_last_mss) {
1407 le = get_tx_le(sky2);
f65b138c 1408 le->addr = cpu_to_le32(mss);
e07560cd 1409 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1410 sky2->tx_last_mss = mss;
1411 }
cd28ab6a
SH		 1412 }
1413
cd28ab6a 1414 ctrl = 0;
d1f13708
SH		 1415#ifdef SKY2_VLAN_TAG_USED
1416 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1417 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1418 if (!le) {
1419 le = get_tx_le(sky2);
f65b138c 1420 le->addr = 0;
d1f13708 1421 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1422 } else
1423 le->opcode |= OP_VLAN;
1424 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1425 ctrl |= INS_VLAN;
1426 }
1427#endif
1428
1429 /* Handle TCP checksum offload */
84fa7933 1430 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 1431 const unsigned offset = skb_transport_offset(skb);
f65b138c
SH		 1432 u32 tcpsum;
1433
1434 tcpsum = offset << 16; /* sum start */
ff1dcadb 1435 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a 1436
56069c0f 1437 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
eddc9ec5 1438 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
cd28ab6a
SH		 1439 ctrl |= UDPTCP;
1440
f65b138c
SH		 1441 if (tcpsum != sky2->tx_tcpsum) {
1442 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1443
1444 le = get_tx_le(sky2);
f65b138c 1445 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1446 le->length = 0; /* initial checksum value */
1447 le->ctrl = 1; /* one packet */
1448 le->opcode = OP_TCPLISW | HW_OWNER;
1449 }
cd28ab6a
SH		 1450 }
1451
1452 le = get_tx_le(sky2);
f65b138c 1453 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1454 le->length = cpu_to_le16(len);
1455 le->ctrl = ctrl;
793b883e 1456 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1457
291ea614 1458 re = tx_le_re(sky2, le);
cd28ab6a 1459 re->skb = skb;
6cdbbdf3 1460 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1461 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1462
1463 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1464 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1465
1466 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1467 frag->size, PCI_DMA_TODEVICE);
a036119f 1468 addr64 = high32(mapping);
793b883e
SH		 1469 if (addr64 != sky2->tx_addr64) {
1470 le = get_tx_le(sky2);
f65b138c 1471 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1472 le->ctrl = 0;
1473 le->opcode = OP_ADDR64 | HW_OWNER;
1474 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1475 }
1476
1477 le = get_tx_le(sky2);
f65b138c 1478 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1479 le->length = cpu_to_le16(frag->size);
1480 le->ctrl = ctrl;
793b883e 1481 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1482
291ea614
SH		 1483 re = tx_le_re(sky2, le);
1484 re->skb = skb;
1485 pci_unmap_addr_set(re, mapaddr, mapping);
1486 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1487 }
6cdbbdf3 1488
cd28ab6a
SH		 1489 le->ctrl |= EOP;
1490
97bda706
SH		 1491 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1492 netif_stop_queue(dev);
b19666d9 1493
290d4de5 1494 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1495
cd28ab6a
SH		 1496 dev->trans_start = jiffies;
1497 return NETDEV_TX_OK;
1498}
1499
cd28ab6a 1500/*
793b883e
SH		 1501 * Free ring elements from starting at tx_cons until "done"
1502 *
1503 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1504 * buffers so make sure not to free skb to early.
cd28ab6a 1505 */
d11c13e7 1506static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1507{
d11c13e7 1508 struct net_device *dev = sky2->netdev;
af2a58ac 1509 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1510 unsigned idx;
cd28ab6a 1511
0e3ff6aa 1512 BUG_ON(done >= TX_RING_SIZE);
2224795d 1513
291ea614
SH		 1514 for (idx = sky2->tx_cons; idx != done;
1515 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1516 struct sky2_tx_le *le = sky2->tx_le + idx;
1517 struct tx_ring_info *re = sky2->tx_ring + idx;
1518
1519 switch(le->opcode & ~HW_OWNER) {
1520 case OP_LARGESEND:
1521 case OP_PACKET:
1522 pci_unmap_single(pdev,
1523 pci_unmap_addr(re, mapaddr),
1524 pci_unmap_len(re, maplen),
1525 PCI_DMA_TODEVICE);
af2a58ac 1526 break;
291ea614
SH		 1527 case OP_BUFFER:
1528 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1529 pci_unmap_len(re, maplen),
734d1868 1530 PCI_DMA_TODEVICE);
291ea614
SH		 1531 break;
1532 }
1533
1534 if (le->ctrl & EOP) {
1535 if (unlikely(netif_msg_tx_done(sky2)))
1536 printk(KERN_DEBUG "%s: tx done %u\n",
1537 dev->name, idx);
2bf56fe2 1538 sky2->net_stats.tx_packets++;
1539 sky2->net_stats.tx_bytes += re->skb->len;
1540
794b2bd2 1541 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1542 }
1543
291ea614 1544 le->opcode = 0; /* paranoia */
793b883e 1545 }
793b883e 1546
291ea614 1547 sky2->tx_cons = idx;
50432cb5
SH		 1548 smp_mb();
1549
22e11703 1550 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1551 netif_wake_queue(dev);
cd28ab6a
SH		 1552}
1553
1554/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1555static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1556{
2bb8c262
SH		 1557 struct sky2_port *sky2 = netdev_priv(dev);
1558
1559 netif_tx_lock_bh(dev);
d11c13e7 1560 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1561 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1562}
1563
1564/* Network shutdown */
1565static int sky2_down(struct net_device *dev)
1566{
1567 struct sky2_port *sky2 = netdev_priv(dev);
1568 struct sky2_hw *hw = sky2->hw;
1569 unsigned port = sky2->port;
1570 u16 ctrl;
e07b1aa8 1571 u32 imask;
cd28ab6a 1572
1b537565
SH		 1573 /* Never really got started! */
1574 if (!sky2->tx_le)
1575 return 0;
1576
cd28ab6a
SH		 1577 if (netif_msg_ifdown(sky2))
1578 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1579
018d1c66 1580 /* Stop more packets from being queued */
cd28ab6a 1581 netif_stop_queue(dev);
9a87240c 1582 netif_carrier_off(dev);
cd28ab6a 1583
ebc646f6
SH		 1584 /* Disable port IRQ */
1585 imask = sky2_read32(hw, B0_IMSK);
1586 imask &= ~portirq_msk[port];
1587 sky2_write32(hw, B0_IMSK, imask);
1588
d3bcfbeb 1589 sky2_gmac_reset(hw, port);
793b883e 1590
cd28ab6a
SH		 1591 /* Stop transmitter */
1592 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1593 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1594
1595 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1596 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1597
1598 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1599 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1600 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1601
1602 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1603
1604 /* Workaround shared GMAC reset */
793b883e
SH		 1605 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1606 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1607 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1608
1609 /* Disable Force Sync bit and Enable Alloc bit */
1610 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1611 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1612
1613 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1614 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1615 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1616
1617 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1618 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1619 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1620
1621 /* Reset the Tx prefetch units */
1622 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1623 PREF_UNIT_RST_SET);
1624
1625 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1626
6b1a3aef 1627 sky2_rx_stop(sky2);
cd28ab6a
SH		 1628
1629 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1630 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1631
d3bcfbeb
SH		 1632 sky2_phy_power(hw, port, 0);
1633
d571b694 1634 /* turn off LED's */
cd28ab6a
SH		 1635 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1636
018d1c66
SH		 1637 synchronize_irq(hw->pdev->irq);
1638
2bb8c262 1639 sky2_tx_clean(dev);
cd28ab6a
SH		 1640 sky2_rx_clean(sky2);
1641
1642 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1643 sky2->rx_le, sky2->rx_le_map);
1644 kfree(sky2->rx_ring);
1645
1646 pci_free_consistent(hw->pdev,
1647 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1648 sky2->tx_le, sky2->tx_le_map);
1649 kfree(sky2->tx_ring);
1650
1b537565
SH		 1651 sky2->tx_le = NULL;
1652 sky2->rx_le = NULL;
1653
1654 sky2->rx_ring = NULL;
1655 sky2->tx_ring = NULL;
1656
cd28ab6a
SH		 1657 return 0;
1658}
1659
1660static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1661{
b89165f2 1662 if (!sky2_is_copper(hw))
793b883e
SH		 1663 return SPEED_1000;
1664
cd28ab6a
SH		 1665 if (hw->chip_id == CHIP_ID_YUKON_FE)
1666 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1667
1668 switch (aux & PHY_M_PS_SPEED_MSK) {
1669 case PHY_M_PS_SPEED_1000:
1670 return SPEED_1000;
1671 case PHY_M_PS_SPEED_100:
1672 return SPEED_100;
1673 default:
1674 return SPEED_10;
1675 }
1676}
1677
1678static void sky2_link_up(struct sky2_port *sky2)
1679{
1680 struct sky2_hw *hw = sky2->hw;
1681 unsigned port = sky2->port;
1682 u16 reg;
16ad91e1
SH		 1683 static const char *fc_name[] = {
1684 [FC_NONE] = "none",
1685 [FC_TX] = "tx",
1686 [FC_RX] = "rx",
1687 [FC_BOTH] = "both",
1688 };
cd28ab6a 1689
cd28ab6a 1690 /* enable Rx/Tx */
2eaba1a2 1691 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1692 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1693 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1694
1695 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1696
1697 netif_carrier_on(sky2->netdev);
1698 netif_wake_queue(sky2->netdev);
1699
1700 /* Turn on link LED */
793b883e 1701 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1702 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1703
93745494
SH		 1704 if (hw->chip_id == CHIP_ID_YUKON_XL
1705 || hw->chip_id == CHIP_ID_YUKON_EC_U
1706 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1707 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1708 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1709
1710 switch(sky2->speed) {
1711 case SPEED_10:
1712 led |= PHY_M_LEDC_INIT_CTRL(7);
1713 break;
1714
1715 case SPEED_100:
1716 led |= PHY_M_LEDC_STA1_CTRL(7);
1717 break;
1718
1719 case SPEED_1000:
1720 led |= PHY_M_LEDC_STA0_CTRL(7);
1721 break;
1722 }
793b883e
SH		 1723
1724 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1725 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1726 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1727 }
1728
cd28ab6a
SH		 1729 if (netif_msg_link(sky2))
1730 printk(KERN_INFO PFX
d571b694 1731 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1732 sky2->netdev->name, sky2->speed,
1733 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1734 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1735}
1736
1737static void sky2_link_down(struct sky2_port *sky2)
1738{
1739 struct sky2_hw *hw = sky2->hw;
1740 unsigned port = sky2->port;
1741 u16 reg;
1742
1743 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1744
1745 reg = gma_read16(hw, port, GM_GP_CTRL);
1746 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1747 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1748
cd28ab6a
SH		 1749 netif_carrier_off(sky2->netdev);
1750 netif_stop_queue(sky2->netdev);
1751
1752 /* Turn on link LED */
1753 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1754
1755 if (netif_msg_link(sky2))
1756 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1757
cd28ab6a
SH		 1758 sky2_phy_init(hw, port);
1759}
1760
16ad91e1
SH		 1761static enum flow_control sky2_flow(int rx, int tx)
1762{
1763 if (rx)
1764 return tx ? FC_BOTH : FC_RX;
1765 else
1766 return tx ? FC_TX : FC_NONE;
1767}
1768
793b883e
SH		 1769static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1770{
1771 struct sky2_hw *hw = sky2->hw;
1772 unsigned port = sky2->port;
da4c1ff4 1773 u16 advert, lpa;
793b883e 1774
da4c1ff4 1775 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1776 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1777 if (lpa & PHY_M_AN_RF) {
1778 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1779 return -1;
1780 }
1781
793b883e
SH		 1782 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1783 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1784 sky2->netdev->name);
1785 return -1;
1786 }
1787
793b883e 1788 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1789 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1790
da4c1ff4
SH		 1791 /* Since the pause result bits seem to in different positions on
1792 * different chips. look at registers.
1793 */
1794 if (!sky2_is_copper(hw)) {
1795 /* Shift for bits in fiber PHY */
1796 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1797 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1798
1799 if (advert & ADVERTISE_1000XPAUSE)
1800 advert |= ADVERTISE_PAUSE_CAP;
1801 if (advert & ADVERTISE_1000XPSE_ASYM)
1802 advert |= ADVERTISE_PAUSE_ASYM;
1803 if (lpa & LPA_1000XPAUSE)
1804 lpa |= LPA_PAUSE_CAP;
1805 if (lpa & LPA_1000XPAUSE_ASYM)
1806 lpa |= LPA_PAUSE_ASYM;
1807 }
793b883e 1808
da4c1ff4
SH		 1809 sky2->flow_status = FC_NONE;
1810 if (advert & ADVERTISE_PAUSE_CAP) {
1811 if (lpa & LPA_PAUSE_CAP)
1812 sky2->flow_status = FC_BOTH;
1813 else if (advert & ADVERTISE_PAUSE_ASYM)
1814 sky2->flow_status = FC_RX;
1815 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1816 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1817 sky2->flow_status = FC_TX;
1818 }
793b883e 1819
16ad91e1 1820 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1821 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1822 sky2->flow_status = FC_NONE;
2eaba1a2 1823
da4c1ff4 1824 if (sky2->flow_status & FC_TX)
793b883e
SH		 1825 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1826 else
1827 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1828
1829 return 0;
1830}
cd28ab6a 1831
e07b1aa8
SH		 1832/* Interrupt from PHY */
1833static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1834{
e07b1aa8
SH		 1835 struct net_device *dev = hw->dev[port];
1836 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1837 u16 istatus, phystat;
1838
ebc646f6
SH		 1839 if (!netif_running(dev))
1840 return;
1841
e07b1aa8
SH		 1842 spin_lock(&sky2->phy_lock);
1843 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1844 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1845
cd28ab6a
SH		 1846 if (netif_msg_intr(sky2))
1847 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1848 sky2->netdev->name, istatus, phystat);
1849
2eaba1a2 1850 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1851 if (sky2_autoneg_done(sky2, phystat) == 0)
1852 sky2_link_up(sky2);
1853 goto out;
1854 }
cd28ab6a 1855
793b883e
SH		 1856 if (istatus & PHY_M_IS_LSP_CHANGE)
1857 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1858
793b883e
SH		 1859 if (istatus & PHY_M_IS_DUP_CHANGE)
1860 sky2->duplex =
1861 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1862
793b883e
SH		 1863 if (istatus & PHY_M_IS_LST_CHANGE) {
1864 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1865 sky2_link_up(sky2);
793b883e
SH		 1866 else
1867 sky2_link_down(sky2);
cd28ab6a 1868 }
793b883e 1869out:
e07b1aa8 1870 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1871}
1872
62335ab0 1873/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1874 * and tx queue is full (stopped).
1875 */
cd28ab6a
SH		 1876static void sky2_tx_timeout(struct net_device *dev)
1877{
1878 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1879 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1880
1881 if (netif_msg_timer(sky2))
1882 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1883
8f24664d 1884 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1885 dev->name, sky2->tx_cons, sky2->tx_prod,
1886 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1887 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1888
81906791
SH		 1889 /* can't restart safely under softirq */
1890 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1891}
1892
1893static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1894{
6b1a3aef
SH		 1895 struct sky2_port *sky2 = netdev_priv(dev);
1896 struct sky2_hw *hw = sky2->hw;
b628ed98 1897 unsigned port = sky2->port;
6b1a3aef
SH		 1898 int err;
1899 u16 ctl, mode;
e07b1aa8 1900 u32 imask;
cd28ab6a
SH		 1901
1902 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1903 return -EINVAL;
1904
d2adf4f6
SH		 1905 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1906 return -EINVAL;
1907
6b1a3aef
SH		 1908 if (!netif_running(dev)) {
1909 dev->mtu = new_mtu;
1910 return 0;
1911 }
1912
e07b1aa8 1913 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1914 sky2_write32(hw, B0_IMSK, 0);
1915
018d1c66
SH		 1916 dev->trans_start = jiffies; /* prevent tx timeout */
1917 netif_stop_queue(dev);
1918 netif_poll_disable(hw->dev[0]);
1919
e07b1aa8
SH		 1920 synchronize_irq(hw->pdev->irq);
1921
b628ed98
SH		 1922 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1923 if (new_mtu > ETH_DATA_LEN) {
1924 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1925 TX_JUMBO_ENA | TX_STFW_DIS);
1926 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1927 } else
1928 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1929 TX_JUMBO_DIS | TX_STFW_ENA);
1930 }
1931
1932 ctl = gma_read16(hw, port, GM_GP_CTRL);
1933 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 1934 sky2_rx_stop(sky2);
1935 sky2_rx_clean(sky2);
cd28ab6a
SH		 1936
1937 dev->mtu = new_mtu;
14d0263f 1938
6b1a3aef
SH		 1939 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1940 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1941
1942 if (dev->mtu > ETH_DATA_LEN)
1943 mode |= GM_SMOD_JUMBO_ENA;
1944
b628ed98 1945 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1946
b628ed98 1947 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1948
6b1a3aef 1949 err = sky2_rx_start(sky2);
e07b1aa8 1950 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1951
1b537565
SH		 1952 if (err)
1953 dev_close(dev);
1954 else {
b628ed98 1955 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1956
1957 netif_poll_enable(hw->dev[0]);
1958 netif_wake_queue(dev);
1959 }
1960
cd28ab6a
SH		 1961 return err;
1962}
1963
14d0263f
SH		 1964/* For small just reuse existing skb for next receive */
1965static struct sk_buff *receive_copy(struct sky2_port *sky2,
1966 const struct rx_ring_info *re,
1967 unsigned length)
1968{
1969 struct sk_buff *skb;
1970
1971 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1972 if (likely(skb)) {
1973 skb_reserve(skb, 2);
1974 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1975 length, PCI_DMA_FROMDEVICE);
d626f62b 1976 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 1977 skb->ip_summed = re->skb->ip_summed;
1978 skb->csum = re->skb->csum;
1979 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1980 length, PCI_DMA_FROMDEVICE);
1981 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1982 skb_put(skb, length);
14d0263f
SH		 1983 }
1984 return skb;
1985}
1986
1987/* Adjust length of skb with fragments to match received data */
1988static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1989 unsigned int length)
1990{
1991 int i, num_frags;
1992 unsigned int size;
1993
1994 /* put header into skb */
1995 size = min(length, hdr_space);
1996 skb->tail += size;
1997 skb->len += size;
1998 length -= size;
1999
2000 num_frags = skb_shinfo(skb)->nr_frags;
2001 for (i = 0; i < num_frags; i++) {
2002 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2003
2004 if (length == 0) {
2005 /* don't need this page */
2006 __free_page(frag->page);
2007 --skb_shinfo(skb)->nr_frags;
2008 } else {
2009 size = min(length, (unsigned) PAGE_SIZE);
2010
2011 frag->size = size;
2012 skb->data_len += size;
2013 skb->truesize += size;
2014 skb->len += size;
2015 length -= size;
2016 }
2017 }
2018}
2019
2020/* Normal packet - take skb from ring element and put in a new one */
2021static struct sk_buff *receive_new(struct sky2_port *sky2,
2022 struct rx_ring_info *re,
2023 unsigned int length)
2024{
2025 struct sk_buff *skb, *nskb;
2026 unsigned hdr_space = sky2->rx_data_size;
2027
2028 pr_debug(PFX "receive new length=%d\n", length);
2029
2030 /* Don't be tricky about reusing pages (yet) */
2031 nskb = sky2_rx_alloc(sky2);
2032 if (unlikely(!nskb))
2033 return NULL;
2034
2035 skb = re->skb;
2036 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2037
2038 prefetch(skb->data);
2039 re->skb = nskb;
2040 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2041
2042 if (skb_shinfo(skb)->nr_frags)
2043 skb_put_frags(skb, hdr_space, length);
2044 else
489b10c1 2045 skb_put(skb, length);
14d0263f
SH		 2046 return skb;
2047}
2048
cd28ab6a
SH		 2049/*
2050 * Receive one packet.
d571b694 2051 * For larger packets, get new buffer.
cd28ab6a 2052 */
497d7c86 2053static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2054 u16 length, u32 status)
2055{
497d7c86 2056 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2057 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2058 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2059
2060 if (unlikely(netif_msg_rx_status(sky2)))
2061 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2062 dev->name, sky2->rx_next, status, length);
cd28ab6a 2063
793b883e 2064 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2065 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2066
42eeea01 2067 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2068 goto error;
2069
42eeea01
SH		 2070 if (!(status & GMR_FS_RX_OK))
2071 goto resubmit;
2072
14d0263f
SH		 2073 if (length < copybreak)
2074 skb = receive_copy(sky2, re, length);
2075 else
2076 skb = receive_new(sky2, re, length);
793b883e 2077resubmit:
14d0263f 2078 sky2_rx_submit(sky2, re);
79e57d32 2079
cd28ab6a
SH		 2080 return skb;
2081
2082error:
6e15b712 2083 ++sky2->net_stats.rx_errors;
b6d77734 2084 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2085 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2086 goto resubmit;
2087 }
6e15b712 2088
3be92a70 2089 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2090 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2091 dev->name, status, length);
793b883e
SH		 2092
2093 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2094 sky2->net_stats.rx_length_errors++;
2095 if (status & GMR_FS_FRAGMENT)
2096 sky2->net_stats.rx_frame_errors++;
2097 if (status & GMR_FS_CRC_ERR)
2098 sky2->net_stats.rx_crc_errors++;
79e57d32 2099
793b883e 2100 goto resubmit;
cd28ab6a
SH		 2101}
2102
e07b1aa8
SH		 2103/* Transmit complete */
2104static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2105{
e07b1aa8 2106 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2107
e07b1aa8 2108 if (netif_running(dev)) {
2bb8c262 2109 netif_tx_lock(dev);
e07b1aa8 2110 sky2_tx_complete(sky2, last);
2bb8c262 2111 netif_tx_unlock(dev);
2224795d 2112 }
cd28ab6a
SH		 2113}
2114
e07b1aa8
SH		 2115/* Process status response ring */
2116static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2117{
22e11703 2118 struct sky2_port *sky2;
e07b1aa8 2119 int work_done = 0;
22e11703 2120 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2121 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2122
af2a58ac 2123 rmb();
bea86103 2124
e71ebd73 2125 while (hw->st_idx != hwidx) {
13210ce5
SH		 2126 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2127 struct net_device *dev;
cd28ab6a 2128 struct sk_buff *skb;
cd28ab6a
SH		 2129 u32 status;
2130 u16 length;
2131
cb5d9547 2132 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2133
e71ebd73
SH		 2134 BUG_ON(le->link >= 2);
2135 dev = hw->dev[le->link];
13210ce5
SH		 2136
2137 sky2 = netdev_priv(dev);
f65b138c
SH		 2138 length = le16_to_cpu(le->length);
2139 status = le32_to_cpu(le->status);
cd28ab6a 2140
e71ebd73 2141 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2142 case OP_RXSTAT:
497d7c86 2143 skb = sky2_receive(dev, length, status);
3225b919
SH		 2144 if (unlikely(!skb)) {
2145 sky2->net_stats.rx_dropped++;
5df79111 2146 goto force_update;
3225b919 2147 }
13210ce5 2148
13210ce5 2149 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2150 sky2->net_stats.rx_packets++;
2151 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2152 dev->last_rx = jiffies;
2153
d1f13708
SH		 2154#ifdef SKY2_VLAN_TAG_USED
2155 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2156 vlan_hwaccel_receive_skb(skb,
2157 sky2->vlgrp,
2158 be16_to_cpu(sky2->rx_tag));
2159 } else
2160#endif
cd28ab6a 2161 netif_receive_skb(skb);
13210ce5 2162
22e11703
SH		 2163 /* Update receiver after 16 frames */
2164 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2165force_update:
2166 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2167 buf_write[le->link] = 0;
2168 }
2169
2170 /* Stop after net poll weight */
13210ce5
SH		 2171 if (++work_done >= to_do)
2172 goto exit_loop;
cd28ab6a
SH		 2173 break;
2174
d1f13708
SH		 2175#ifdef SKY2_VLAN_TAG_USED
2176 case OP_RXVLAN:
2177 sky2->rx_tag = length;
2178 break;
2179
2180 case OP_RXCHKSVLAN:
2181 sky2->rx_tag = length;
2182 /* fall through */
2183#endif
cd28ab6a 2184 case OP_RXCHKS:
87418307
SH		 2185 if (!sky2->rx_csum)
2186 break;
2187
2188 /* Both checksum counters are programmed to start at
2189 * the same offset, so unless there is a problem they
2190 * should match. This failure is an early indication that
2191 * hardware receive checksumming won't work.
2192 */
2193 if (likely(status >> 16 == (status & 0xffff))) {
2194 skb = sky2->rx_ring[sky2->rx_next].skb;
2195 skb->ip_summed = CHECKSUM_COMPLETE;
2196 skb->csum = status & 0xffff;
2197 } else {
2198 printk(KERN_NOTICE PFX "%s: hardware receive "
2199 "checksum problem (status = %#x)\n",
2200 dev->name, status);
2201 sky2->rx_csum = 0;
2202 sky2_write32(sky2->hw,
2203 Q_ADDR(rxqaddr[le->link], Q_CSR),
2204 BMU_DIS_RX_CHKSUM);
2205 }
cd28ab6a
SH		 2206 break;
2207
2208 case OP_TXINDEXLE:
13b97b74 2209 /* TX index reports status for both ports */
f55925d7
SH		 2210 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2211 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2212 if (hw->dev[1])
2213 sky2_tx_done(hw->dev[1],
2214 ((status >> 24) & 0xff)
2215 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2216 break;
2217
cd28ab6a
SH		 2218 default:
2219 if (net_ratelimit())
793b883e 2220 printk(KERN_WARNING PFX
e71ebd73
SH		 2221 "unknown status opcode 0x%x\n", le->opcode);
2222 goto exit_loop;
cd28ab6a 2223 }
13210ce5 2224 }
cd28ab6a 2225
fe2a24df
SH		 2226 /* Fully processed status ring so clear irq */
2227 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
50432cb5 2228 mmiowb();
fe2a24df 2229
13210ce5 2230exit_loop:
22e11703
SH		 2231 if (buf_write[0]) {
2232 sky2 = netdev_priv(hw->dev[0]);
2233 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2234 }
2235
2236 if (buf_write[1]) {
2237 sky2 = netdev_priv(hw->dev[1]);
2238 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2239 }
2240
e07b1aa8 2241 return work_done;
cd28ab6a
SH		 2242}
2243
2244static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2245{
2246 struct net_device *dev = hw->dev[port];
2247
3be92a70
SH		 2248 if (net_ratelimit())
2249 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2250 dev->name, status);
cd28ab6a
SH		 2251
2252 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2253 if (net_ratelimit())
2254 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2255 dev->name);
cd28ab6a
SH		 2256 /* Clear IRQ */
2257 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2258 }
2259
2260 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2261 if (net_ratelimit())
2262 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2263 dev->name);
cd28ab6a
SH		 2264
2265 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2266 }
2267
2268 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2269 if (net_ratelimit())
2270 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2271 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2272 }
2273
2274 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2275 if (net_ratelimit())
2276 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2277 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2278 }
2279
2280 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2281 if (net_ratelimit())
2282 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2283 dev->name);
cd28ab6a
SH		 2284 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2285 }
2286}
2287
2288static void sky2_hw_intr(struct sky2_hw *hw)
2289{
2290 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2291
793b883e 2292 if (status & Y2_IS_TIST_OV)
cd28ab6a 2293 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2294
2295 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2296 u16 pci_err;
2297
56a645cc 2298 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2299 if (net_ratelimit())
b02a9258
SH		 2300 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2301 pci_err);
cd28ab6a
SH		 2302
2303 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2304 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2305 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2306 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2307 }
2308
2309 if (status & Y2_IS_PCI_EXP) {
d571b694 2310 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2311 u32 pex_err;
2312
7bd656d1 2313 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2314
3be92a70 2315 if (net_ratelimit())
b02a9258
SH		 2316 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2317 pex_err);
cd28ab6a
SH		 2318
2319 /* clear the interrupt */
2320 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2321 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2322 0xffffffffUL);
cd28ab6a
SH		 2323 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2324
7bd656d1 2325 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2326 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2327 hwmsk &= ~Y2_IS_PCI_EXP;
2328 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2329 }
2330 }
2331
2332 if (status & Y2_HWE_L1_MASK)
2333 sky2_hw_error(hw, 0, status);
2334 status >>= 8;
2335 if (status & Y2_HWE_L1_MASK)
2336 sky2_hw_error(hw, 1, status);
2337}
2338
2339static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2340{
2341 struct net_device *dev = hw->dev[port];
2342 struct sky2_port *sky2 = netdev_priv(dev);
2343 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2344
2345 if (netif_msg_intr(sky2))
2346 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2347 dev->name, status);
2348
a3caeada
SH		 2349 if (status & GM_IS_RX_CO_OV)
2350 gma_read16(hw, port, GM_RX_IRQ_SRC);
2351
2352 if (status & GM_IS_TX_CO_OV)
2353 gma_read16(hw, port, GM_TX_IRQ_SRC);
2354
cd28ab6a
SH		 2355 if (status & GM_IS_RX_FF_OR) {
2356 ++sky2->net_stats.rx_fifo_errors;
2357 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2358 }
2359
2360 if (status & GM_IS_TX_FF_UR) {
2361 ++sky2->net_stats.tx_fifo_errors;
2362 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2363 }
cd28ab6a
SH		 2364}
2365
40b01727
SH		 2366/* This should never happen it is a bug. */
2367static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2368 u16 q, unsigned ring_size)
d257924e
SH		 2369{
2370 struct net_device *dev = hw->dev[port];
2371 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2372 unsigned idx;
2373 const u64 *le = (q == Q_R1 || q == Q_R2)
2374 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2375
40b01727
SH		 2376 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2377 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2378 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2379 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2380
40b01727 2381 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2382}
cd28ab6a 2383
d27ed387
SH		 2384/* If idle then force a fake soft NAPI poll once a second
2385 * to work around cases where sharing an edge triggered interrupt.
2386 */
eb35cf60
SH		 2387static inline void sky2_idle_start(struct sky2_hw *hw)
2388{
2389 if (idle_timeout > 0)
2390 mod_timer(&hw->idle_timer,
2391 jiffies + msecs_to_jiffies(idle_timeout));
2392}
2393
d27ed387
SH		 2394static void sky2_idle(unsigned long arg)
2395{
01bd7564
SH		 2396 struct sky2_hw *hw = (struct sky2_hw *) arg;
2397 struct net_device *dev = hw->dev[0];
d27ed387 2398
d27ed387
SH		 2399 if (__netif_rx_schedule_prep(dev))
2400 __netif_rx_schedule(dev);
01bd7564
SH		 2401
2402 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2403}
2404
40b01727
SH		 2405/* Hardware/software error handling */
2406static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2407{
40b01727
SH		 2408 if (net_ratelimit())
2409 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2410
1e5f1283
SH		 2411 if (status & Y2_IS_HW_ERR)
2412 sky2_hw_intr(hw);
d257924e 2413
1e5f1283
SH		 2414 if (status & Y2_IS_IRQ_MAC1)
2415 sky2_mac_intr(hw, 0);
cd28ab6a 2416
1e5f1283
SH		 2417 if (status & Y2_IS_IRQ_MAC2)
2418 sky2_mac_intr(hw, 1);
cd28ab6a 2419
1e5f1283 2420 if (status & Y2_IS_CHK_RX1)
40b01727 2421 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2422
1e5f1283 2423 if (status & Y2_IS_CHK_RX2)
40b01727 2424 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2425
1e5f1283 2426 if (status & Y2_IS_CHK_TXA1)
40b01727 2427 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2428
1e5f1283 2429 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2430 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2431}
2432
2433static int sky2_poll(struct net_device *dev0, int *budget)
2434{
2435 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2436 int work_limit = min(dev0->quota, *budget);
2437 int work_done = 0;
2438 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2439
2440 if (unlikely(status & Y2_IS_ERROR))
2441 sky2_err_intr(hw, status);
2442
2443 if (status & Y2_IS_IRQ_PHY1)
2444 sky2_phy_intr(hw, 0);
2445
2446 if (status & Y2_IS_IRQ_PHY2)
2447 sky2_phy_intr(hw, 1);
cd28ab6a 2448
1e5f1283 2449 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2450 if (work_done < work_limit) {
2451 netif_rx_complete(dev0);
86fba634 2452
50432cb5 2453 /* end of interrupt, re-enables also acts as I/O synchronization */
fe2a24df
SH		 2454 sky2_read32(hw, B0_Y2_SP_LISR);
2455 return 0;
2456 } else {
2457 *budget -= work_done;
2458 dev0->quota -= work_done;
1e5f1283 2459 return 1;
fe2a24df 2460 }
e07b1aa8
SH		 2461}
2462
7d12e780 2463static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2464{
2465 struct sky2_hw *hw = dev_id;
2466 struct net_device *dev0 = hw->dev[0];
2467 u32 status;
2468
2469 /* Reading this mask interrupts as side effect */
2470 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2471 if (status == 0 || status == ~0)
2472 return IRQ_NONE;
793b883e 2473
e07b1aa8
SH		 2474 prefetch(&hw->st_le[hw->st_idx]);
2475 if (likely(__netif_rx_schedule_prep(dev0)))
2476 __netif_rx_schedule(dev0);
793b883e 2477
cd28ab6a
SH		 2478 return IRQ_HANDLED;
2479}
2480
2481#ifdef CONFIG_NET_POLL_CONTROLLER
2482static void sky2_netpoll(struct net_device *dev)
2483{
2484 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2485 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2486
88d11360
SH		 2487 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2488 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2489}
2490#endif
2491
2492/* Chip internal frequency for clock calculations */
fb17358f 2493static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2494{
793b883e 2495 switch (hw->chip_id) {
cd28ab6a 2496 case CHIP_ID_YUKON_EC:
5a5b1ea0 2497 case CHIP_ID_YUKON_EC_U:
93745494 2498 case CHIP_ID_YUKON_EX:
fb17358f 2499 return 125; /* 125 Mhz */
cd28ab6a 2500 case CHIP_ID_YUKON_FE:
fb17358f 2501 return 100; /* 100 Mhz */
793b883e 2502 default: /* YUKON_XL */
fb17358f 2503 return 156; /* 156 Mhz */
cd28ab6a
SH		 2504 }
2505}
2506
fb17358f 2507static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2508{
fb17358f 2509 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2510}
2511
fb17358f 2512static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2513{
fb17358f 2514 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2515}
2516
fb17358f 2517
e3173832 2518static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2519{
b89165f2 2520 u8 t8;
cd28ab6a 2521
451af335
SH		 2522 /* Enable all clocks */
2523 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2524
cd28ab6a 2525 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2526
cd28ab6a
SH		 2527 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2528 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2529 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2530 hw->chip_id);
cd28ab6a
SH		 2531 return -EOPNOTSUPP;
2532 }
2533
93745494
SH		 2534 if (hw->chip_id == CHIP_ID_YUKON_EX)
2535 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2536 "Please report success or failure to <netdev@vger.kernel.org>\n");
2537
290d4de5
SH		 2538 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2539
2540 /* This rev is really old, and requires untested workarounds */
2541 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2542 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2543 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2544 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2545 return -EOPNOTSUPP;
2546 }
2547
e3173832
SH		 2548 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2549 hw->ports = 1;
2550 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2551 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2552 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2553 ++hw->ports;
2554 }
2555
2556 return 0;
2557}
2558
2559static void sky2_reset(struct sky2_hw *hw)
2560{
2561 u16 status;
2562 int i;
2563
cd28ab6a 2564 /* disable ASF */
4f44d8ba
SH		 2565 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2566 status = sky2_read16(hw, HCU_CCSR);
2567 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2568 HCU_CCSR_UC_STATE_MSK);
2569 sky2_write16(hw, HCU_CCSR, status);
2570 } else
2571 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2572 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2573
2574 /* do a SW reset */
2575 sky2_write8(hw, B0_CTST, CS_RST_SET);
2576 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2577
2578 /* clear PCI errors, if any */
56a645cc 2579 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2580
cd28ab6a 2581 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2582 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2583
cd28ab6a
SH		 2584
2585 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2586
2587 /* clear any PEX errors */
7bd656d1
SH		 2588 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2589 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2590
cd28ab6a 2591
ae306cca 2592 sky2_power_on(hw);
cd28ab6a
SH		 2593
2594 for (i = 0; i < hw->ports; i++) {
2595 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2596 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2597 }
2598
2599 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2600
793b883e
SH		 2601 /* Clear I2C IRQ noise */
2602 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2603
2604 /* turn off hardware timer (unused) */
2605 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2606 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2607
cd28ab6a
SH		 2608 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2609
69634ee7
SH		 2610 /* Turn off descriptor polling */
2611 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2612
2613 /* Turn off receive timestamp */
2614 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2615 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2616
2617 /* enable the Tx Arbiters */
2618 for (i = 0; i < hw->ports; i++)
2619 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2620
2621 /* Initialize ram interface */
2622 for (i = 0; i < hw->ports; i++) {
793b883e 2623 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2624
2625 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2626 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2627 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2628 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2629 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2630 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2631 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2632 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2633 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2634 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2635 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2636 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2637 }
2638
7bd656d1 2639 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2640
cd28ab6a 2641 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2642 sky2_gmac_reset(hw, i);
cd28ab6a 2643
cd28ab6a
SH		 2644 memset(hw->st_le, 0, STATUS_LE_BYTES);
2645 hw->st_idx = 0;
2646
2647 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2648 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2649
2650 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2651 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2652
2653 /* Set the list last index */
793b883e 2654 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2655
290d4de5
SH		 2656 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2657 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2658
290d4de5
SH		 2659 /* set Status-FIFO ISR watermark */
2660 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2661 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2662 else
2663 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2664
290d4de5 2665 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2666 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2667 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2668
793b883e 2669 /* enable status unit */
cd28ab6a
SH		 2670 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2671
2672 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2673 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2674 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2675}
2676
81906791
SH		 2677static void sky2_restart(struct work_struct *work)
2678{
2679 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2680 struct net_device *dev;
2681 int i, err;
2682
2683 dev_dbg(&hw->pdev->dev, "restarting\n");
2684
2685 del_timer_sync(&hw->idle_timer);
2686
2687 rtnl_lock();
2688 sky2_write32(hw, B0_IMSK, 0);
2689 sky2_read32(hw, B0_IMSK);
2690
2691 netif_poll_disable(hw->dev[0]);
2692
2693 for (i = 0; i < hw->ports; i++) {
2694 dev = hw->dev[i];
2695 if (netif_running(dev))
2696 sky2_down(dev);
2697 }
2698
2699 sky2_reset(hw);
2700 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2701 netif_poll_enable(hw->dev[0]);
2702
2703 for (i = 0; i < hw->ports; i++) {
2704 dev = hw->dev[i];
2705 if (netif_running(dev)) {
2706 err = sky2_up(dev);
2707 if (err) {
2708 printk(KERN_INFO PFX "%s: could not restart %d\n",
2709 dev->name, err);
2710 dev_close(dev);
2711 }
2712 }
2713 }
2714
2715 sky2_idle_start(hw);
2716
2717 rtnl_unlock();
2718}
2719
e3173832
SH		 2720static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2721{
2722 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2723}
2724
2725static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2726{
2727 const struct sky2_port *sky2 = netdev_priv(dev);
2728
2729 wol->supported = sky2_wol_supported(sky2->hw);
2730 wol->wolopts = sky2->wol;
2731}
2732
2733static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2734{
2735 struct sky2_port *sky2 = netdev_priv(dev);
2736 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2737
e3173832
SH		 2738 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2739 return -EOPNOTSUPP;
2740
2741 sky2->wol = wol->wolopts;
2742
2743 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2744 sky2_write32(hw, B0_CTST, sky2->wol
2745 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2746
2747 if (!netif_running(dev))
2748 sky2_wol_init(sky2);
cd28ab6a
SH		 2749 return 0;
2750}
2751
28bd181a 2752static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2753{
b89165f2
SH		 2754 if (sky2_is_copper(hw)) {
2755 u32 modes = SUPPORTED_10baseT_Half
2756 | SUPPORTED_10baseT_Full
2757 | SUPPORTED_100baseT_Half
2758 | SUPPORTED_100baseT_Full
2759 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2760
2761 if (hw->chip_id != CHIP_ID_YUKON_FE)
2762 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2763 | SUPPORTED_1000baseT_Full;
2764 return modes;
cd28ab6a 2765 } else
b89165f2
SH		 2766 return SUPPORTED_1000baseT_Half
2767 | SUPPORTED_1000baseT_Full
2768 | SUPPORTED_Autoneg
2769 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2770}
2771
793b883e 2772static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2773{
2774 struct sky2_port *sky2 = netdev_priv(dev);
2775 struct sky2_hw *hw = sky2->hw;
2776
2777 ecmd->transceiver = XCVR_INTERNAL;
2778 ecmd->supported = sky2_supported_modes(hw);
2779 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2780 if (sky2_is_copper(hw)) {
cd28ab6a 2781 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2782 | SUPPORTED_10baseT_Full
2783 | SUPPORTED_100baseT_Half
2784 | SUPPORTED_100baseT_Full
2785 | SUPPORTED_1000baseT_Half
2786 | SUPPORTED_1000baseT_Full
2787 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2788 ecmd->port = PORT_TP;
b89165f2
SH		 2789 ecmd->speed = sky2->speed;
2790 } else {
2791 ecmd->speed = SPEED_1000;
cd28ab6a 2792 ecmd->port = PORT_FIBRE;
b89165f2 2793 }
cd28ab6a
SH		 2794
2795 ecmd->advertising = sky2->advertising;
2796 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2797 ecmd->duplex = sky2->duplex;
2798 return 0;
2799}
2800
2801static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2802{
2803 struct sky2_port *sky2 = netdev_priv(dev);
2804 const struct sky2_hw *hw = sky2->hw;
2805 u32 supported = sky2_supported_modes(hw);
2806
2807 if (ecmd->autoneg == AUTONEG_ENABLE) {
2808 ecmd->advertising = supported;
2809 sky2->duplex = -1;
2810 sky2->speed = -1;
2811 } else {
2812 u32 setting;
2813
793b883e 2814 switch (ecmd->speed) {
cd28ab6a
SH		 2815 case SPEED_1000:
2816 if (ecmd->duplex == DUPLEX_FULL)
2817 setting = SUPPORTED_1000baseT_Full;
2818 else if (ecmd->duplex == DUPLEX_HALF)
2819 setting = SUPPORTED_1000baseT_Half;
2820 else
2821 return -EINVAL;
2822 break;
2823 case SPEED_100:
2824 if (ecmd->duplex == DUPLEX_FULL)
2825 setting = SUPPORTED_100baseT_Full;
2826 else if (ecmd->duplex == DUPLEX_HALF)
2827 setting = SUPPORTED_100baseT_Half;
2828 else
2829 return -EINVAL;
2830 break;
2831
2832 case SPEED_10:
2833 if (ecmd->duplex == DUPLEX_FULL)
2834 setting = SUPPORTED_10baseT_Full;
2835 else if (ecmd->duplex == DUPLEX_HALF)
2836 setting = SUPPORTED_10baseT_Half;
2837 else
2838 return -EINVAL;
2839 break;
2840 default:
2841 return -EINVAL;
2842 }
2843
2844 if ((setting & supported) == 0)
2845 return -EINVAL;
2846
2847 sky2->speed = ecmd->speed;
2848 sky2->duplex = ecmd->duplex;
2849 }
2850
2851 sky2->autoneg = ecmd->autoneg;
2852 sky2->advertising = ecmd->advertising;
2853
1b537565
SH		 2854 if (netif_running(dev))
2855 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2856
2857 return 0;
2858}
2859
2860static void sky2_get_drvinfo(struct net_device *dev,
2861 struct ethtool_drvinfo *info)
2862{
2863 struct sky2_port *sky2 = netdev_priv(dev);
2864
2865 strcpy(info->driver, DRV_NAME);
2866 strcpy(info->version, DRV_VERSION);
2867 strcpy(info->fw_version, "N/A");
2868 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2869}
2870
2871static const struct sky2_stat {
793b883e
SH		 2872 char name[ETH_GSTRING_LEN];
2873 u16 offset;
cd28ab6a
SH		 2874} sky2_stats[] = {
2875 { "tx_bytes", GM_TXO_OK_HI },
2876 { "rx_bytes", GM_RXO_OK_HI },
2877 { "tx_broadcast", GM_TXF_BC_OK },
2878 { "rx_broadcast", GM_RXF_BC_OK },
2879 { "tx_multicast", GM_TXF_MC_OK },
2880 { "rx_multicast", GM_RXF_MC_OK },
2881 { "tx_unicast", GM_TXF_UC_OK },
2882 { "rx_unicast", GM_RXF_UC_OK },
2883 { "tx_mac_pause", GM_TXF_MPAUSE },
2884 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2885 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2886 { "late_collision",GM_TXF_LAT_COL },
2887 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2888 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2889 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2890
d2604540 2891 { "rx_short", GM_RXF_SHT },
cd28ab6a 2892 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2893 { "rx_64_byte_packets", GM_RXF_64B },
2894 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2895 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2896 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2897 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2898 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2899 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2900 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2901 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2902 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2903 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2904
2905 { "tx_64_byte_packets", GM_TXF_64B },
2906 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2907 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2908 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2909 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2910 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2911 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2912 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2913};
2914
cd28ab6a
SH		 2915static u32 sky2_get_rx_csum(struct net_device *dev)
2916{
2917 struct sky2_port *sky2 = netdev_priv(dev);
2918
2919 return sky2->rx_csum;
2920}
2921
2922static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2923{
2924 struct sky2_port *sky2 = netdev_priv(dev);
2925
2926 sky2->rx_csum = data;
793b883e 2927
cd28ab6a
SH		 2928 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2929 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2930
2931 return 0;
2932}
2933
2934static u32 sky2_get_msglevel(struct net_device *netdev)
2935{
2936 struct sky2_port *sky2 = netdev_priv(netdev);
2937 return sky2->msg_enable;
2938}
2939
9a7ae0a9
SH		 2940static int sky2_nway_reset(struct net_device *dev)
2941{
2942 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2943
16ad91e1 2944 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2945 return -EINVAL;
2946
1b537565 2947 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2948
2949 return 0;
2950}
2951
793b883e 2952static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2953{
2954 struct sky2_hw *hw = sky2->hw;
2955 unsigned port = sky2->port;
2956 int i;
2957
2958 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2959 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2960 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2961 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2962
793b883e 2963 for (i = 2; i < count; i++)
cd28ab6a
SH		 2964 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2965}
2966
cd28ab6a
SH		 2967static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2968{
2969 struct sky2_port *sky2 = netdev_priv(netdev);
2970 sky2->msg_enable = value;
2971}
2972
2973static int sky2_get_stats_count(struct net_device *dev)
2974{
2975 return ARRAY_SIZE(sky2_stats);
2976}
2977
2978static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2979 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2980{
2981 struct sky2_port *sky2 = netdev_priv(dev);
2982
793b883e 2983 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2984}
2985
793b883e 2986static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2987{
2988 int i;
2989
2990 switch (stringset) {
2991 case ETH_SS_STATS:
2992 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2993 memcpy(data + i * ETH_GSTRING_LEN,
2994 sky2_stats[i].name, ETH_GSTRING_LEN);
2995 break;
2996 }
2997}
2998
cd28ab6a
SH		 2999static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3000{
3001 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3002 return &sky2->net_stats;
3003}
3004
3005static int sky2_set_mac_address(struct net_device *dev, void *p)
3006{
3007 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3008 struct sky2_hw *hw = sky2->hw;
3009 unsigned port = sky2->port;
3010 const struct sockaddr *addr = p;
cd28ab6a
SH		 3011
3012 if (!is_valid_ether_addr(addr->sa_data))
3013 return -EADDRNOTAVAIL;
3014
cd28ab6a 3015 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3016 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3017 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3018 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3019 dev->dev_addr, ETH_ALEN);
1b537565 3020
a8ab1ec0
SH		 3021 /* virtual address for data */
3022 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3023
3024 /* physical address: used for pause frames */
3025 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3026
3027 return 0;
cd28ab6a
SH		 3028}
3029
a052b52f
SH		 3030static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3031{
3032 u32 bit;
3033
3034 bit = ether_crc(ETH_ALEN, addr) & 63;
3035 filter[bit >> 3] |= 1 << (bit & 7);
3036}
3037
cd28ab6a
SH		 3038static void sky2_set_multicast(struct net_device *dev)
3039{
3040 struct sky2_port *sky2 = netdev_priv(dev);
3041 struct sky2_hw *hw = sky2->hw;
3042 unsigned port = sky2->port;
3043 struct dev_mc_list *list = dev->mc_list;
3044 u16 reg;
3045 u8 filter[8];
a052b52f
SH		 3046 int rx_pause;
3047 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3048
a052b52f 3049 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3050 memset(filter, 0, sizeof(filter));
3051
3052 reg = gma_read16(hw, port, GM_RX_CTRL);
3053 reg |= GM_RXCR_UCF_ENA;
3054
d571b694 3055 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3056 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3057 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3058 memset(filter, 0xff, sizeof(filter));
a052b52f 3059 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3060 reg &= ~GM_RXCR_MCF_ENA;
3061 else {
3062 int i;
3063 reg |= GM_RXCR_MCF_ENA;
3064
a052b52f
SH		 3065 if (rx_pause)
3066 sky2_add_filter(filter, pause_mc_addr);
3067
3068 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3069 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3070 }
3071
cd28ab6a 3072 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3073 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3074 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3075 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3076 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3077 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3078 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3079 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3080
3081 gma_write16(hw, port, GM_RX_CTRL, reg);
3082}
3083
3084/* Can have one global because blinking is controlled by
3085 * ethtool and that is always under RTNL mutex
3086 */
91c86df5 3087static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3088{
793b883e
SH		 3089 u16 pg;
3090
793b883e
SH		 3091 switch (hw->chip_id) {
3092 case CHIP_ID_YUKON_XL:
3093 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3094 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3095 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3096 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3097 PHY_M_LEDC_INIT_CTRL(7) |
3098 PHY_M_LEDC_STA1_CTRL(7) |
3099 PHY_M_LEDC_STA0_CTRL(7))
3100 : 0);
3101
3102 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3103 break;
3104
3105 default:
3106 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3107 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3108 on ? PHY_M_LED_ALL : 0);
793b883e 3109 }
cd28ab6a
SH		 3110}
3111
3112/* blink LED's for finding board */
3113static int sky2_phys_id(struct net_device *dev, u32 data)
3114{
3115 struct sky2_port *sky2 = netdev_priv(dev);
3116 struct sky2_hw *hw = sky2->hw;
3117 unsigned port = sky2->port;
793b883e 3118 u16 ledctrl, ledover = 0;
cd28ab6a 3119 long ms;
91c86df5 3120 int interrupted;
cd28ab6a
SH		 3121 int onoff = 1;
3122
793b883e 3123 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3124 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3125 else
3126 ms = data * 1000;
3127
3128 /* save initial values */
e07b1aa8 3129 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3130 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3131 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3132 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3133 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3134 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3135 } else {
3136 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3137 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3138 }
cd28ab6a 3139
91c86df5
SH		 3140 interrupted = 0;
3141 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3142 sky2_led(hw, port, onoff);
3143 onoff = !onoff;
3144
e07b1aa8 3145 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3146 interrupted = msleep_interruptible(250);
e07b1aa8 3147 spin_lock_bh(&sky2->phy_lock);
91c86df5 3148
cd28ab6a
SH		 3149 ms -= 250;
3150 }
3151
3152 /* resume regularly scheduled programming */
793b883e
SH		 3153 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3154 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3155 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3156 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3157 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3158 } else {
3159 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3160 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3161 }
e07b1aa8 3162 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3163
3164 return 0;
3165}
3166
3167static void sky2_get_pauseparam(struct net_device *dev,
3168 struct ethtool_pauseparam *ecmd)
3169{
3170 struct sky2_port *sky2 = netdev_priv(dev);
3171
16ad91e1
SH		 3172 switch (sky2->flow_mode) {
3173 case FC_NONE:
3174 ecmd->tx_pause = ecmd->rx_pause = 0;
3175 break;
3176 case FC_TX:
3177 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3178 break;
3179 case FC_RX:
3180 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3181 break;
3182 case FC_BOTH:
3183 ecmd->tx_pause = ecmd->rx_pause = 1;
3184 }
3185
cd28ab6a
SH		 3186 ecmd->autoneg = sky2->autoneg;
3187}
3188
3189static int sky2_set_pauseparam(struct net_device *dev,
3190 struct ethtool_pauseparam *ecmd)
3191{
3192 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3193
3194 sky2->autoneg = ecmd->autoneg;
16ad91e1 3195 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3196
16ad91e1
SH		 3197 if (netif_running(dev))
3198 sky2_phy_reinit(sky2);
cd28ab6a 3199
2eaba1a2 3200 return 0;
cd28ab6a
SH		 3201}
3202
fb17358f
SH		 3203static int sky2_get_coalesce(struct net_device *dev,
3204 struct ethtool_coalesce *ecmd)
3205{
3206 struct sky2_port *sky2 = netdev_priv(dev);
3207 struct sky2_hw *hw = sky2->hw;
3208
3209 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3210 ecmd->tx_coalesce_usecs = 0;
3211 else {
3212 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3213 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3214 }
3215 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3216
3217 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3218 ecmd->rx_coalesce_usecs = 0;
3219 else {
3220 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3221 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3222 }
3223 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3224
3225 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3226 ecmd->rx_coalesce_usecs_irq = 0;
3227 else {
3228 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3229 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3230 }
3231
3232 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3233
3234 return 0;
3235}
3236
3237/* Note: this affect both ports */
3238static int sky2_set_coalesce(struct net_device *dev,
3239 struct ethtool_coalesce *ecmd)
3240{
3241 struct sky2_port *sky2 = netdev_priv(dev);
3242 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3243 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3244
77b3d6a2
SH		 3245 if (ecmd->tx_coalesce_usecs > tmax ||
3246 ecmd->rx_coalesce_usecs > tmax ||
3247 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3248 return -EINVAL;
3249
ff81fbbe 3250 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3251 return -EINVAL;
ff81fbbe 3252 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3253 return -EINVAL;
ff81fbbe 3254 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3255 return -EINVAL;
3256
3257 if (ecmd->tx_coalesce_usecs == 0)
3258 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3259 else {
3260 sky2_write32(hw, STAT_TX_TIMER_INI,
3261 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3262 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3263 }
3264 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3265
3266 if (ecmd->rx_coalesce_usecs == 0)
3267 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3268 else {
3269 sky2_write32(hw, STAT_LEV_TIMER_INI,
3270 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3271 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3272 }
3273 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3274
3275 if (ecmd->rx_coalesce_usecs_irq == 0)
3276 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3277 else {
d28d4870 3278 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3279 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3280 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3281 }
3282 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3283 return 0;
3284}
3285
793b883e
SH		 3286static void sky2_get_ringparam(struct net_device *dev,
3287 struct ethtool_ringparam *ering)
3288{
3289 struct sky2_port *sky2 = netdev_priv(dev);
3290
3291 ering->rx_max_pending = RX_MAX_PENDING;
3292 ering->rx_mini_max_pending = 0;
3293 ering->rx_jumbo_max_pending = 0;
3294 ering->tx_max_pending = TX_RING_SIZE - 1;
3295
3296 ering->rx_pending = sky2->rx_pending;
3297 ering->rx_mini_pending = 0;
3298 ering->rx_jumbo_pending = 0;
3299 ering->tx_pending = sky2->tx_pending;
3300}
3301
3302static int sky2_set_ringparam(struct net_device *dev,
3303 struct ethtool_ringparam *ering)
3304{
3305 struct sky2_port *sky2 = netdev_priv(dev);
3306 int err = 0;
3307
3308 if (ering->rx_pending > RX_MAX_PENDING ||
3309 ering->rx_pending < 8 ||
3310 ering->tx_pending < MAX_SKB_TX_LE ||
3311 ering->tx_pending > TX_RING_SIZE - 1)
3312 return -EINVAL;
3313
3314 if (netif_running(dev))
3315 sky2_down(dev);
3316
3317 sky2->rx_pending = ering->rx_pending;
3318 sky2->tx_pending = ering->tx_pending;
3319
1b537565 3320 if (netif_running(dev)) {
793b883e 3321 err = sky2_up(dev);
1b537565
SH		 3322 if (err)
3323 dev_close(dev);
6ed995bb
SH		 3324 else
3325 sky2_set_multicast(dev);
1b537565 3326 }
793b883e
SH		 3327
3328 return err;
3329}
3330
793b883e
SH		 3331static int sky2_get_regs_len(struct net_device *dev)
3332{
6e4cbb34 3333 return 0x4000;
793b883e
SH		 3334}
3335
3336/*
3337 * Returns copy of control register region
3ead5db7 3338 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3339 */
3340static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3341 void *p)
3342{
3343 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3344 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3345
3346 regs->version = 1;
6e4cbb34 3347 memset(p, 0, regs->len);
793b883e 3348
6e4cbb34
SH		 3349 memcpy_fromio(p, io, B3_RAM_ADDR);
3350
3ead5db7
SH		 3351 /* skip diagnostic ram region */
3352 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3353
3354 /* copy GMAC registers */
3355 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3356 if (sky2->hw->ports > 1)
3357 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3358
793b883e 3359}
cd28ab6a 3360
b628ed98
SH		 3361/* In order to do Jumbo packets on these chips, need to turn off the
3362 * transmit store/forward. Therefore checksum offload won't work.
3363 */
3364static int no_tx_offload(struct net_device *dev)
3365{
3366 const struct sky2_port *sky2 = netdev_priv(dev);
3367 const struct sky2_hw *hw = sky2->hw;
3368
3369 return dev->mtu > ETH_DATA_LEN &&
3370 (hw->chip_id == CHIP_ID_YUKON_EX
3371 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3372}
3373
3374static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3375{
3376 if (data && no_tx_offload(dev))
3377 return -EINVAL;
3378
3379 return ethtool_op_set_tx_csum(dev, data);
3380}
3381
3382
3383static int sky2_set_tso(struct net_device *dev, u32 data)
3384{
3385 if (data && no_tx_offload(dev))
3386 return -EINVAL;
3387
3388 return ethtool_op_set_tso(dev, data);
3389}
3390
7282d491 3391static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3392 .get_settings = sky2_get_settings,
3393 .set_settings = sky2_set_settings,
e3173832
SH		 3394 .get_drvinfo = sky2_get_drvinfo,
3395 .get_wol = sky2_get_wol,
3396 .set_wol = sky2_set_wol,
793b883e
SH		 3397 .get_msglevel = sky2_get_msglevel,
3398 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3399 .nway_reset = sky2_nway_reset,
793b883e
SH		 3400 .get_regs_len = sky2_get_regs_len,
3401 .get_regs = sky2_get_regs,
3402 .get_link = ethtool_op_get_link,
3403 .get_sg = ethtool_op_get_sg,
3404 .set_sg = ethtool_op_set_sg,
3405 .get_tx_csum = ethtool_op_get_tx_csum,
b628ed98 3406 .set_tx_csum = sky2_set_tx_csum,
793b883e 3407 .get_tso = ethtool_op_get_tso,
b628ed98 3408 .set_tso = sky2_set_tso,
793b883e
SH		 3409 .get_rx_csum = sky2_get_rx_csum,
3410 .set_rx_csum = sky2_set_rx_csum,
3411 .get_strings = sky2_get_strings,
fb17358f
SH		 3412 .get_coalesce = sky2_get_coalesce,
3413 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3414 .get_ringparam = sky2_get_ringparam,
3415 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3416 .get_pauseparam = sky2_get_pauseparam,
3417 .set_pauseparam = sky2_set_pauseparam,
793b883e 3418 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3419 .get_stats_count = sky2_get_stats_count,
3420 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3421 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3422};
3423
3424/* Initialize network device */
3425static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3426 unsigned port,
3427 int highmem, int wol)
cd28ab6a
SH		 3428{
3429 struct sky2_port *sky2;
3430 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3431
3432 if (!dev) {
b02a9258 3433 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3434 return NULL;
3435 }
3436
3437 SET_MODULE_OWNER(dev);
3438 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3439 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3440 dev->open = sky2_up;
3441 dev->stop = sky2_down;
ef743d33 3442 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3443 dev->hard_start_xmit = sky2_xmit_frame;
3444 dev->get_stats = sky2_get_stats;
3445 dev->set_multicast_list = sky2_set_multicast;
3446 dev->set_mac_address = sky2_set_mac_address;
3447 dev->change_mtu = sky2_change_mtu;
3448 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3449 dev->tx_timeout = sky2_tx_timeout;
3450 dev->watchdog_timeo = TX_WATCHDOG;
3451 if (port == 0)
3452 dev->poll = sky2_poll;
3453 dev->weight = NAPI_WEIGHT;
3454#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3455 /* Network console (only works on port 0)
3456 * because netpoll makes assumptions about NAPI
3457 */
3458 if (port == 0)
3459 dev->poll_controller = sky2_netpoll;
cd28ab6a 3460#endif
cd28ab6a
SH		 3461
3462 sky2 = netdev_priv(dev);
3463 sky2->netdev = dev;
3464 sky2->hw = hw;
3465 sky2->msg_enable = netif_msg_init(debug, default_msg);
3466
cd28ab6a
SH		 3467 /* Auto speed and flow control */
3468 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3469 sky2->flow_mode = FC_BOTH;
3470
cd28ab6a
SH		 3471 sky2->duplex = -1;
3472 sky2->speed = -1;
3473 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3474 sky2->rx_csum = 1;
e3173832 3475 sky2->wol = wol;
75d070c5 3476
e07b1aa8 3477 spin_lock_init(&sky2->phy_lock);
793b883e 3478 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3479 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3480
3481 hw->dev[port] = dev;
3482
3483 sky2->port = port;
3484
4a50a876 3485 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3486 if (highmem)
3487 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3488
d1f13708
SH		 3489#ifdef SKY2_VLAN_TAG_USED
3490 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3491 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708
SH		 3492#endif
3493
cd28ab6a 3494 /* read the mac address */
793b883e 3495 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3496 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3497
3498 /* device is off until link detection */
3499 netif_carrier_off(dev);
3500 netif_stop_queue(dev);
3501
3502 return dev;
3503}
3504
28bd181a 3505static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3506{
3507 const struct sky2_port *sky2 = netdev_priv(dev);
3508
3509 if (netif_msg_probe(sky2))
3510 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3511 dev->name,
3512 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3513 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3514}
3515
fb2690a9 3516/* Handle software interrupt used during MSI test */
7d12e780 3517static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3518{
3519 struct sky2_hw *hw = dev_id;
3520 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3521
3522 if (status == 0)
3523 return IRQ_NONE;
3524
3525 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3526 hw->msi = 1;
fb2690a9
SH		 3527 wake_up(&hw->msi_wait);
3528 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3529 }
3530 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3531
3532 return IRQ_HANDLED;
3533}
3534
3535/* Test interrupt path by forcing a a software IRQ */
3536static int __devinit sky2_test_msi(struct sky2_hw *hw)
3537{
3538 struct pci_dev *pdev = hw->pdev;
3539 int err;
3540
bb507fe1
SH		 3541 init_waitqueue_head (&hw->msi_wait);
3542
fb2690a9
SH		 3543 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3544
b0a20ded 3545 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3546 if (err) {
b02a9258 3547 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3548 return err;
3549 }
3550
fb2690a9 3551 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3552 sky2_read8(hw, B0_CTST);
fb2690a9 3553
b0a20ded 3554 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3555
b0a20ded 3556 if (!hw->msi) {
fb2690a9 3557 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3558 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3559 "switching to INTx mode.\n");
fb2690a9
SH		 3560
3561 err = -EOPNOTSUPP;
3562 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3563 }
3564
3565 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3566 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3567
3568 free_irq(pdev->irq, hw);
3569
3570 return err;
3571}
3572
e3173832
SH		 3573static int __devinit pci_wake_enabled(struct pci_dev *dev)
3574{
3575 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3576 u16 value;
3577
3578 if (!pm)
3579 return 0;
3580 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3581 return 0;
3582 return value & PCI_PM_CTRL_PME_ENABLE;
3583}
3584
cd28ab6a
SH		 3585static int __devinit sky2_probe(struct pci_dev *pdev,
3586 const struct pci_device_id *ent)
3587{
7f60c64b 3588 struct net_device *dev;
cd28ab6a 3589 struct sky2_hw *hw;
e3173832 3590 int err, using_dac = 0, wol_default;
cd28ab6a 3591
793b883e
SH		 3592 err = pci_enable_device(pdev);
3593 if (err) {
b02a9258 3594 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3595 goto err_out;
3596 }
3597
793b883e
SH		 3598 err = pci_request_regions(pdev, DRV_NAME);
3599 if (err) {
b02a9258 3600 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3601 goto err_out_disable;
cd28ab6a
SH		 3602 }
3603
3604 pci_set_master(pdev);
3605
d1f3d4dd
SH		 3606 if (sizeof(dma_addr_t) > sizeof(u32) &&
3607 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3608 using_dac = 1;
3609 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3610 if (err < 0) {
b02a9258
SH		 3611 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3612 "for consistent allocations\n");
d1f3d4dd
SH		 3613 goto err_out_free_regions;
3614 }
d1f3d4dd 3615 } else {
cd28ab6a
SH		 3616 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3617 if (err) {
b02a9258 3618 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3619 goto err_out_free_regions;
3620 }
3621 }
d1f3d4dd 3622
e3173832
SH		 3623 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3624
cd28ab6a 3625 err = -ENOMEM;
6aad85d6 3626 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3627 if (!hw) {
b02a9258 3628 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3629 goto err_out_free_regions;
3630 }
3631
cd28ab6a 3632 hw->pdev = pdev;
cd28ab6a
SH		 3633
3634 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3635 if (!hw->regs) {
b02a9258 3636 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3637 goto err_out_free_hw;
3638 }
3639
56a645cc 3640#ifdef __BIG_ENDIAN
f65b138c
SH		 3641 /* The sk98lin vendor driver uses hardware byte swapping but
3642 * this driver uses software swapping.
3643 */
56a645cc
SH		 3644 {
3645 u32 reg;
56a645cc 3646 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3647 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3648 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3649 }
3650#endif
3651
08c06d8a
SH		 3652 /* ring for status responses */
3653 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3654 &hw->st_dma);
3655 if (!hw->st_le)
3656 goto err_out_iounmap;
3657
e3173832 3658 err = sky2_init(hw);
cd28ab6a 3659 if (err)
793b883e 3660 goto err_out_iounmap;
cd28ab6a 3661
b02a9258 3662 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3663 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3664 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3665 hw->chip_id, hw->chip_rev);
cd28ab6a 3666
e3173832
SH		 3667 sky2_reset(hw);
3668
3669 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3670 if (!dev) {
3671 err = -ENOMEM;
cd28ab6a 3672 goto err_out_free_pci;
7f60c64b 3673 }
cd28ab6a 3674
9fa1b1f3
SH		 3675 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3676 err = sky2_test_msi(hw);
3677 if (err == -EOPNOTSUPP)
3678 pci_disable_msi(pdev);
3679 else if (err)
3680 goto err_out_free_netdev;
3681 }
3682
793b883e
SH		 3683 err = register_netdev(dev);
3684 if (err) {
b02a9258 3685 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3686 goto err_out_free_netdev;
3687 }
3688
b0a20ded
SH		 3689 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3690 dev->name, hw);
9fa1b1f3 3691 if (err) {
b02a9258 3692 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3693 goto err_out_unregister;
3694 }
3695 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3696
cd28ab6a
SH		 3697 sky2_show_addr(dev);
3698
7f60c64b 3699 if (hw->ports > 1) {
3700 struct net_device *dev1;
3701
e3173832 3702 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3703 if (!dev1)
3704 dev_warn(&pdev->dev, "allocation for second device failed\n");
3705 else if ((err = register_netdev(dev1))) {
3706 dev_warn(&pdev->dev,
3707 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3708 hw->dev[1] = NULL;
3709 free_netdev(dev1);
b02a9258
SH		 3710 } else
3711 sky2_show_addr(dev1);
cd28ab6a
SH		 3712 }
3713
01bd7564 3714 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3715 INIT_WORK(&hw->restart_work, sky2_restart);
3716
eb35cf60 3717 sky2_idle_start(hw);
d27ed387 3718
793b883e
SH		 3719 pci_set_drvdata(pdev, hw);
3720
cd28ab6a
SH		 3721 return 0;
3722
793b883e 3723err_out_unregister:
b0a20ded
SH		 3724 if (hw->msi)
3725 pci_disable_msi(pdev);
793b883e 3726 unregister_netdev(dev);
cd28ab6a
SH		 3727err_out_free_netdev:
3728 free_netdev(dev);
cd28ab6a 3729err_out_free_pci:
793b883e 3730 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3731 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3732err_out_iounmap:
3733 iounmap(hw->regs);
3734err_out_free_hw:
3735 kfree(hw);
3736err_out_free_regions:
3737 pci_release_regions(pdev);
44a1d2e5 3738err_out_disable:
cd28ab6a 3739 pci_disable_device(pdev);
cd28ab6a 3740err_out:
549a68c3 3741 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 3742 return err;
3743}
3744
3745static void __devexit sky2_remove(struct pci_dev *pdev)
3746{
793b883e 3747 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3748 struct net_device *dev0, *dev1;
3749
793b883e 3750 if (!hw)
cd28ab6a
SH		 3751 return;
3752
d27ed387
SH		 3753 del_timer_sync(&hw->idle_timer);
3754
81906791
SH		 3755 flush_scheduled_work();
3756
d27ed387 3757 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3758 synchronize_irq(hw->pdev->irq);
3759
cd28ab6a 3760 dev0 = hw->dev[0];
793b883e
SH		 3761 dev1 = hw->dev[1];
3762 if (dev1)
3763 unregister_netdev(dev1);
cd28ab6a
SH		 3764 unregister_netdev(dev0);
3765
ae306cca
SH		 3766 sky2_power_aux(hw);
3767
cd28ab6a 3768 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3769 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3770 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3771
3772 free_irq(pdev->irq, hw);
b0a20ded
SH		 3773 if (hw->msi)
3774 pci_disable_msi(pdev);
793b883e 3775 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3776 pci_release_regions(pdev);
3777 pci_disable_device(pdev);
793b883e 3778
cd28ab6a
SH		 3779 if (dev1)
3780 free_netdev(dev1);
3781 free_netdev(dev0);
3782 iounmap(hw->regs);
3783 kfree(hw);
5afa0a9c 3784
cd28ab6a
SH		 3785 pci_set_drvdata(pdev, NULL);
3786}
3787
3788#ifdef CONFIG_PM
3789static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3790{
793b883e 3791 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3792 int i, wol = 0;
cd28ab6a 3793
549a68c3
SH		 3794 if (!hw)
3795 return 0;
3796
eb35cf60 3797 del_timer_sync(&hw->idle_timer);
6a5706b9 3798 netif_poll_disable(hw->dev[0]);
eb35cf60 3799
f05267e7 3800 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3801 struct net_device *dev = hw->dev[i];
e3173832 3802 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3803
e3173832 3804 if (netif_running(dev))
5afa0a9c 3805 sky2_down(dev);
e3173832
SH		 3806
3807 if (sky2->wol)
3808 sky2_wol_init(sky2);
3809
3810 wol |= sky2->wol;
cd28ab6a
SH		 3811 }
3812
8ab8fca2 3813 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3814 sky2_power_aux(hw);
e3173832 3815
d374c1c1 3816 pci_save_state(pdev);
e3173832 3817 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3818 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3819
2ccc99b7 3820 return 0;
cd28ab6a
SH		 3821}
3822
3823static int sky2_resume(struct pci_dev *pdev)
3824{
793b883e 3825 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3826 int i, err;
cd28ab6a 3827
549a68c3
SH		 3828 if (!hw)
3829 return 0;
3830
ae306cca
SH		 3831 err = pci_set_power_state(pdev, PCI_D0);
3832 if (err)
3833 goto out;
3834
3835 err = pci_restore_state(pdev);
3836 if (err)
3837 goto out;
3838
cd28ab6a 3839 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 3840
3841 /* Re-enable all clocks */
3842 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3843 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3844
e3173832 3845 sky2_reset(hw);
cd28ab6a 3846
8ab8fca2
SH		 3847 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3848
f05267e7 3849 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3850 struct net_device *dev = hw->dev[i];
6a5706b9 3851 if (netif_running(dev)) {
08c06d8a
SH		 3852 err = sky2_up(dev);
3853 if (err) {
3854 printk(KERN_ERR PFX "%s: could not up: %d\n",
3855 dev->name, err);
3856 dev_close(dev);
eb35cf60 3857 goto out;
5afa0a9c 3858 }
cd28ab6a
SH		 3859 }
3860 }
eb35cf60 3861
6a5706b9 3862 netif_poll_enable(hw->dev[0]);
eb35cf60 3863 sky2_idle_start(hw);
ae306cca 3864 return 0;
08c06d8a 3865out:
b02a9258 3866 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3867 pci_disable_device(pdev);
08c06d8a 3868 return err;
cd28ab6a
SH		 3869}
3870#endif
3871
e3173832
SH		 3872static void sky2_shutdown(struct pci_dev *pdev)
3873{
3874 struct sky2_hw *hw = pci_get_drvdata(pdev);
3875 int i, wol = 0;
3876
549a68c3
SH		 3877 if (!hw)
3878 return;
3879
e3173832
SH		 3880 del_timer_sync(&hw->idle_timer);
3881 netif_poll_disable(hw->dev[0]);
3882
3883 for (i = 0; i < hw->ports; i++) {
3884 struct net_device *dev = hw->dev[i];
3885 struct sky2_port *sky2 = netdev_priv(dev);
3886
3887 if (sky2->wol) {
3888 wol = 1;
3889 sky2_wol_init(sky2);
3890 }
3891 }
3892
3893 if (wol)
3894 sky2_power_aux(hw);
3895
3896 pci_enable_wake(pdev, PCI_D3hot, wol);
3897 pci_enable_wake(pdev, PCI_D3cold, wol);
3898
3899 pci_disable_device(pdev);
3900 pci_set_power_state(pdev, PCI_D3hot);
3901
3902}
3903
cd28ab6a 3904static struct pci_driver sky2_driver = {
793b883e
SH		 3905 .name = DRV_NAME,
3906 .id_table = sky2_id_table,
3907 .probe = sky2_probe,
3908 .remove = __devexit_p(sky2_remove),
cd28ab6a 3909#ifdef CONFIG_PM
793b883e
SH		 3910 .suspend = sky2_suspend,
3911 .resume = sky2_resume,
cd28ab6a 3912#endif
e3173832 3913 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3914};
3915
3916static int __init sky2_init_module(void)
3917{
50241c4c 3918 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3919}
3920
3921static void __exit sky2_cleanup_module(void)
3922{
3923 pci_unregister_driver(&sky2_driver);
3924}
3925
3926module_init(sky2_init_module);
3927module_exit(sky2_cleanup_module);
3928
3929MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3930MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3931MODULE_LICENSE("GPL");
5f4f9dc1 3932MODULE_VERSION(DRV_VERSION);
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