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[PATCH] sky2: beter ram buffer partitioning
[mirror_ubuntu-zesty-kernel.git] / drivers / net / sky2.c
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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708
SH		 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
52c89cac 52#define DRV_VERSION "1.10"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33
SH		 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
2ccc99b7 195static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c
SH		 196{
197 u16 power_control;
5afa0a9c 198 int vaux;
5afa0a9c
SH		 199
200 pr_debug("sky2_set_power_state %d\n", state);
201 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
202
56a645cc 203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 204 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 205 (power_control & PCI_PM_CAP_PME_D3cold);
206
56a645cc 207 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 208
209 power_control |= PCI_PM_CTRL_PME_STATUS;
210 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
211
212 switch (state) {
213 case PCI_D0:
214 /* switch power to VCC (WA for VAUX problem) */
215 sky2_write8(hw, B0_POWER_CTRL,
216 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
217
218 /* disable Core Clock Division, */
219 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
220
221 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
222 /* enable bits are inverted */
223 sky2_write8(hw, B2_Y2_CLK_GATE,
224 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
225 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
226 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
227 else
228 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
229
977bdf06 230 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb
SH		 231 u32 reg1;
232
56a645cc
SH		 233 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
234 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 235 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 236 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
237 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 238 }
239
5afa0a9c
SH		 240 break;
241
242 case PCI_D3hot:
243 case PCI_D3cold:
5afa0a9c
SH		 244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
246 else
247 /* enable bits are inverted */
248 sky2_write8(hw, B2_Y2_CLK_GATE,
249 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
250 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
251 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
252
253 /* switch power to VAUX */
254 if (vaux && state != PCI_D3cold)
255 sky2_write8(hw, B0_POWER_CTRL,
256 (PC_VAUX_ENA | PC_VCC_ENA |
257 PC_VAUX_ON | PC_VCC_OFF));
258 break;
259 default:
260 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c
SH		 261 }
262
56a645cc 263 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 264 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c
SH		 265}
266
d3bcfbeb 267static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 268{
269 u16 reg;
270
271 /* disable all GMAC IRQ's */
272 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
273 /* disable PHY IRQs */
274 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 275
cd28ab6a
SH		 276 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
277 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
278 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
280
281 reg = gma_read16(hw, port, GM_RX_CTRL);
282 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
283 gma_write16(hw, port, GM_RX_CTRL, reg);
284}
285
16ad91e1
SH		 286/* flow control to advertise bits */
287static const u16 copper_fc_adv[] = {
288 [FC_NONE] = 0,
289 [FC_TX] = PHY_M_AN_ASP,
290 [FC_RX] = PHY_M_AN_PC,
291 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
292};
293
294/* flow control to advertise bits when using 1000BaseX */
295static const u16 fiber_fc_adv[] = {
296 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
297 [FC_TX] = PHY_M_P_ASYM_MD_X,
298 [FC_RX] = PHY_M_P_SYM_MD_X,
299 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
300};
301
302/* flow control to GMA disable bits */
303static const u16 gm_fc_disable[] = {
304 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
305 [FC_TX] = GM_GPCR_FC_RX_DIS,
306 [FC_RX] = GM_GPCR_FC_TX_DIS,
307 [FC_BOTH] = 0,
308};
309
310
cd28ab6a
SH		 311static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
312{
313 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 314 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 315
ed6d32c7 316 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 317 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 318 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
319
320 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 321 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 322 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
323
324 if (hw->chip_id == CHIP_ID_YUKON_EC)
325 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
326 else
327 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
328
329 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
330 }
331
332 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 333 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 334 if (hw->chip_id == CHIP_ID_YUKON_FE) {
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
337 } else {
338 /* disable energy detect */
339 ctrl &= ~PHY_M_PC_EN_DET_MSK;
340
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
343
344 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 345 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 346 ctrl &= ~PHY_M_PC_DSC_MSK;
347 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
348 }
349 }
cd28ab6a
SH		 350 } else {
351 /* workaround for deviation #4.88 (CRC errors) */
352 /* disable Automatic Crossover */
353
354 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 355 }
cd28ab6a 356
b89165f2
SH		 357 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
358
359 /* special setup for PHY 88E1112 Fiber */
360 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
361 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 362
b89165f2
SH		 363 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
366 ctrl &= ~PHY_M_MAC_MD_MSK;
367 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
368 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
369
370 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 371 /* select page 1 to access Fiber registers */
372 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 373
374 /* for SFP-module set SIGDET polarity to low */
375 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
376 ctrl |= PHY_M_FIB_SIGD_POL;
377 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 378 }
b89165f2
SH		 379
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 381 }
382
7800fddc 383 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 384 ct1000 = 0;
385 adv = PHY_AN_CSMA;
2eaba1a2 386 reg = 0;
cd28ab6a
SH		 387
388 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 389 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 390 if (sky2->advertising & ADVERTISED_1000baseT_Full)
391 ct1000 |= PHY_M_1000C_AFD;
392 if (sky2->advertising & ADVERTISED_1000baseT_Half)
393 ct1000 |= PHY_M_1000C_AHD;
394 if (sky2->advertising & ADVERTISED_100baseT_Full)
395 adv |= PHY_M_AN_100_FD;
396 if (sky2->advertising & ADVERTISED_100baseT_Half)
397 adv |= PHY_M_AN_100_HD;
398 if (sky2->advertising & ADVERTISED_10baseT_Full)
399 adv |= PHY_M_AN_10_FD;
400 if (sky2->advertising & ADVERTISED_10baseT_Half)
401 adv |= PHY_M_AN_10_HD;
709c6e7b 402
16ad91e1 403 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 404 } else { /* special defines for FIBER (88E1040S only) */
405 if (sky2->advertising & ADVERTISED_1000baseT_Full)
406 adv |= PHY_M_AN_1000X_AFD;
407 if (sky2->advertising & ADVERTISED_1000baseT_Half)
408 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 409
16ad91e1 410 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 411 }
cd28ab6a
SH		 412
413 /* Restart Auto-negotiation */
414 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
415 } else {
416 /* forced speed/duplex settings */
417 ct1000 = PHY_M_1000C_MSE;
418
2eaba1a2
SH		 419 /* Disable auto update for duplex flow control and speed */
420 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 421
422 switch (sky2->speed) {
423 case SPEED_1000:
424 ctrl |= PHY_CT_SP1000;
2eaba1a2 425 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 426 break;
427 case SPEED_100:
428 ctrl |= PHY_CT_SP100;
2eaba1a2 429 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 430 break;
431 }
432
2eaba1a2
SH		 433 if (sky2->duplex == DUPLEX_FULL) {
434 reg |= GM_GPCR_DUP_FULL;
435 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 436 } else if (sky2->speed < SPEED_1000)
437 sky2->flow_mode = FC_NONE;
2eaba1a2 438
2eaba1a2 439
16ad91e1 440 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 441
442 /* Forward pause packets to GMAC? */
16ad91e1 443 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 444 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
445 else
446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 447 }
448
2eaba1a2
SH		 449 gma_write16(hw, port, GM_GP_CTRL, reg);
450
cd28ab6a
SH		 451 if (hw->chip_id != CHIP_ID_YUKON_FE)
452 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
453
454 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
455 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
456
457 /* Setup Phy LED's */
458 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
459 ledover = 0;
460
461 switch (hw->chip_id) {
462 case CHIP_ID_YUKON_FE:
463 /* on 88E3082 these bits are at 11..9 (shifted left) */
464 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
465
466 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
467
468 /* delete ACT LED control bits */
469 ctrl &= ~PHY_M_FELP_LED1_MSK;
470 /* change ACT LED control to blink mode */
471 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
472 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
473 break;
474
475 case CHIP_ID_YUKON_XL:
793b883e 476 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 477
478 /* select page 3 to access LED control register */
479 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
480
481 /* set LED Function Control register */
ed6d32c7
SH		 482 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
483 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
484 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
485 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
486 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 487
488 /* set Polarity Control register */
489 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 490 (PHY_M_POLC_LS1_P_MIX(4) |
491 PHY_M_POLC_IS0_P_MIX(4) |
492 PHY_M_POLC_LOS_CTRL(2) |
493 PHY_M_POLC_INIT_CTRL(2) |
494 PHY_M_POLC_STA1_CTRL(2) |
495 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 496
497 /* restore page register */
793b883e 498 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 499 break;
ed6d32c7
SH		 500 case CHIP_ID_YUKON_EC_U:
501 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
502
503 /* select page 3 to access LED control register */
504 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
505
506 /* set LED Function Control register */
507 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
508 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
509 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
510 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
511 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
512
513 /* set Blink Rate in LED Timer Control Register */
514 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
515 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
516 /* restore page register */
517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
518 break;
cd28ab6a
SH		 519
520 default:
521 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
522 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
523 /* turn off the Rx LED (LED_RX) */
524 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
525 }
526
ed6d32c7 527 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 528 /* apply fixes in PHY AFE */
ed6d32c7
SH		 529 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
531
977bdf06 532 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 533 gm_phy_write(hw, port, 0x18, 0xaa99);
534 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 535
977bdf06 536 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 537 gm_phy_write(hw, port, 0x18, 0xa204);
538 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 539
540 /* set page register to 0 */
ed6d32c7 541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 542 } else {
543 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 544
977bdf06
SH		 545 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
546 /* turn on 100 Mbps LED (LED_LINK100) */
547 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
548 }
cd28ab6a 549
977bdf06
SH		 550 if (ledover)
551 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
552
553 }
2eaba1a2 554
d571b694 555 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 556 if (sky2->autoneg == AUTONEG_ENABLE)
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
558 else
559 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
560}
561
d3bcfbeb
SH		 562static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
563{
564 u32 reg1;
565 static const u32 phy_power[]
566 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
567
568 /* looks like this XL is back asswards .. */
569 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
570 onoff = !onoff;
571
572 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
573
574 if (onoff)
575 /* Turn off phy power saving */
576 reg1 &= ~phy_power[port];
577 else
578 reg1 |= phy_power[port];
579
580 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 581 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 582 udelay(100);
583}
584
1b537565
SH		 585/* Force a renegotiation */
586static void sky2_phy_reinit(struct sky2_port *sky2)
587{
e07b1aa8 588 spin_lock_bh(&sky2->phy_lock);
1b537565 589 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 590 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 591}
592
cd28ab6a
SH		 593static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
594{
595 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
596 u16 reg;
597 int i;
598 const u8 *addr = hw->dev[port]->dev_addr;
599
42eeea01
SH		 600 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
601 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 602
603 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
604
793b883e 605 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 606 /* WA DEV_472 -- looks like crossed wires on port 2 */
607 /* clear GMAC 1 Control reset */
608 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
609 do {
610 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
611 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
612 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
613 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
614 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
615 }
616
793b883e 617 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 618
2eaba1a2
SH		 619 /* Enable Transmit FIFO Underrun */
620 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
621
e07b1aa8 622 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 623 sky2_phy_init(hw, port);
e07b1aa8 624 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 625
626 /* MIB clear */
627 reg = gma_read16(hw, port, GM_PHY_ADDR);
628 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
629
43f2f104
SH		 630 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
631 gma_read16(hw, port, i);
cd28ab6a
SH		 632 gma_write16(hw, port, GM_PHY_ADDR, reg);
633
634 /* transmit control */
635 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
636
637 /* receive control reg: unicast + multicast + no FCS */
638 gma_write16(hw, port, GM_RX_CTRL,
793b883e 639 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 640
641 /* transmit flow control */
642 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
643
644 /* transmit parameter */
645 gma_write16(hw, port, GM_TX_PARAM,
646 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
647 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
648 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
649 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
650
651 /* serial mode register */
652 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 653 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 654
6b1a3aef 655 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 656 reg |= GM_SMOD_JUMBO_ENA;
657
658 gma_write16(hw, port, GM_SERIAL_MODE, reg);
659
cd28ab6a
SH		 660 /* virtual address for data */
661 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
662
793b883e
SH		 663 /* physical address: used for pause frames */
664 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
665
666 /* ignore counter overflows */
cd28ab6a
SH		 667 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
668 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
669 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
670
671 /* Configure Rx MAC FIFO */
672 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 673 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
674 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 675
d571b694 676 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 677 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 678
8df9a876
SH		 679 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
680 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 681
682 /* Configure Tx MAC FIFO */
683 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
684 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 685
686 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
8df9a876 687 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0
SH		 688 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
689 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
690 /* set Tx GMAC FIFO Almost Empty Threshold */
691 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
692 /* Disable Store & Forward mode for TX */
693 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
694 }
695 }
696
cd28ab6a
SH		 697}
698
67712901
SH		 699/* Assign Ram Buffer allocation to queue */
700static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 701{
67712901
SH		 702 u32 end;
703
704 /* convert from K bytes to qwords used for hw register */
705 start *= 1024/8;
706 space *= 1024/8;
707 end = start + space - 1;
793b883e 708
cd28ab6a
SH		 709 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
710 sky2_write32(hw, RB_ADDR(q, RB_START), start);
711 sky2_write32(hw, RB_ADDR(q, RB_END), end);
712 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
713 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
714
715 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 716 u32 tp = space - space/4;
793b883e 717
1c28f6ba
SH		 718 /* On receive queue's set the thresholds
719 * give receiver priority when > 3/4 full
720 * send pause when down to 2K
721 */
722 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
723 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 724
1c28f6ba
SH		 725 tp = space - 2048/8;
726 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
727 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 728 } else {
729 /* Enable store & forward on Tx queue's because
730 * Tx FIFO is only 1K on Yukon
731 */
732 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
733 }
734
735 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 736 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 737}
738
cd28ab6a 739/* Setup Bus Memory Interface */
af4ed7e6 740static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 741{
742 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
743 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
744 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 745 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 746}
747
cd28ab6a
SH		 748/* Setup prefetch unit registers. This is the interface between
749 * hardware and driver list elements
750 */
8cc048e3 751static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 752 u64 addr, u32 last)
753{
cd28ab6a
SH		 754 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
756 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
758 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
759 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 760
761 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 762}
763
793b883e
SH		 764static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
765{
766 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
767
cb5d9547 768 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 769 le->ctrl = 0;
793b883e
SH		 770 return le;
771}
cd28ab6a 772
291ea614
SH		 773static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
774 struct sky2_tx_le *le)
775{
776 return sky2->tx_ring + (le - sky2->tx_le);
777}
778
290d4de5
SH		 779/* Update chip's next pointer */
780static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 781{
98232f85 782 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 783 wmb();
98232f85
SH		 784 sky2_write16(hw, q, idx);
785 sky2_read16(hw, q);
cd28ab6a
SH		 786}
787
793b883e 788
cd28ab6a
SH		 789static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
790{
791 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 792 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 793 le->ctrl = 0;
cd28ab6a
SH		 794 return le;
795}
796
a018e330
SH		 797/* Return high part of DMA address (could be 32 or 64 bit) */
798static inline u32 high32(dma_addr_t a)
799{
a036119f 800 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 801}
802
14d0263f
SH		 803/* Build description to hardware for one receive segment */
804static void sky2_rx_add(struct sky2_port *sky2, u8 op,
805 dma_addr_t map, unsigned len)
cd28ab6a
SH		 806{
807 struct sky2_rx_le *le;
734d1868 808 u32 hi = high32(map);
cd28ab6a 809
793b883e 810 if (sky2->rx_addr64 != hi) {
cd28ab6a 811 le = sky2_next_rx(sky2);
793b883e 812 le->addr = cpu_to_le32(hi);
cd28ab6a 813 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 814 sky2->rx_addr64 = high32(map + len);
cd28ab6a 815 }
793b883e 816
cd28ab6a 817 le = sky2_next_rx(sky2);
734d1868
SH		 818 le->addr = cpu_to_le32((u32) map);
819 le->length = cpu_to_le16(len);
14d0263f 820 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 821}
822
14d0263f
SH		 823/* Build description to hardware for one possibly fragmented skb */
824static void sky2_rx_submit(struct sky2_port *sky2,
825 const struct rx_ring_info *re)
826{
827 int i;
828
829 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
830
831 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
832 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
833}
834
835
836static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
837 unsigned size)
838{
839 struct sk_buff *skb = re->skb;
840 int i;
841
842 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
843 pci_unmap_len_set(re, data_size, size);
844
845 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
846 re->frag_addr[i] = pci_map_page(pdev,
847 skb_shinfo(skb)->frags[i].page,
848 skb_shinfo(skb)->frags[i].page_offset,
849 skb_shinfo(skb)->frags[i].size,
850 PCI_DMA_FROMDEVICE);
851}
852
853static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
854{
855 struct sk_buff *skb = re->skb;
856 int i;
857
858 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
859 PCI_DMA_FROMDEVICE);
860
861 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
862 pci_unmap_page(pdev, re->frag_addr[i],
863 skb_shinfo(skb)->frags[i].size,
864 PCI_DMA_FROMDEVICE);
865}
793b883e 866
cd28ab6a
SH		 867/* Tell chip where to start receive checksum.
868 * Actually has two checksums, but set both same to avoid possible byte
869 * order problems.
870 */
793b883e 871static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 872{
873 struct sky2_rx_le *le;
874
cd28ab6a 875 le = sky2_next_rx(sky2);
f65b138c 876 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 877 le->ctrl = 0;
878 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 879
793b883e
SH		 880 sky2_write32(sky2->hw,
881 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
882 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 883
884}
885
6b1a3aef
SH		 886/*
887 * The RX Stop command will not work for Yukon-2 if the BMU does not
888 * reach the end of packet and since we can't make sure that we have
889 * incoming data, we must reset the BMU while it is not doing a DMA
890 * transfer. Since it is possible that the RX path is still active,
891 * the RX RAM buffer will be stopped first, so any possible incoming
892 * data will not trigger a DMA. After the RAM buffer is stopped, the
893 * BMU is polled until any DMA in progress is ended and only then it
894 * will be reset.
895 */
896static void sky2_rx_stop(struct sky2_port *sky2)
897{
898 struct sky2_hw *hw = sky2->hw;
899 unsigned rxq = rxqaddr[sky2->port];
900 int i;
901
902 /* disable the RAM Buffer receive queue */
903 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
904
905 for (i = 0; i < 0xffff; i++)
906 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
907 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
908 goto stopped;
909
910 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
911 sky2->netdev->name);
912stopped:
913 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
914
915 /* reset the Rx prefetch unit */
916 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
917}
793b883e 918
d571b694 919/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 920static void sky2_rx_clean(struct sky2_port *sky2)
921{
922 unsigned i;
923
924 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 925 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 926 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 927
928 if (re->skb) {
14d0263f 929 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 930 kfree_skb(re->skb);
931 re->skb = NULL;
932 }
933 }
934}
935
ef743d33
SH		 936/* Basic MII support */
937static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
938{
939 struct mii_ioctl_data *data = if_mii(ifr);
940 struct sky2_port *sky2 = netdev_priv(dev);
941 struct sky2_hw *hw = sky2->hw;
942 int err = -EOPNOTSUPP;
943
944 if (!netif_running(dev))
945 return -ENODEV; /* Phy still in reset */
946
d89e1343 947 switch (cmd) {
ef743d33
SH		 948 case SIOCGMIIPHY:
949 data->phy_id = PHY_ADDR_MARV;
950
951 /* fallthru */
952 case SIOCGMIIREG: {
953 u16 val = 0;
91c86df5 954
e07b1aa8 955 spin_lock_bh(&sky2->phy_lock);
ef743d33 956 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 957 spin_unlock_bh(&sky2->phy_lock);
91c86df5 958
ef743d33
SH		 959 data->val_out = val;
960 break;
961 }
962
963 case SIOCSMIIREG:
964 if (!capable(CAP_NET_ADMIN))
965 return -EPERM;
966
e07b1aa8 967 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 968 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
969 data->val_in);
e07b1aa8 970 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 971 break;
972 }
973 return err;
974}
975
d1f13708
SH		 976#ifdef SKY2_VLAN_TAG_USED
977static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
978{
979 struct sky2_port *sky2 = netdev_priv(dev);
980 struct sky2_hw *hw = sky2->hw;
981 u16 port = sky2->port;
d1f13708 982
2bb8c262 983 netif_tx_lock_bh(dev);
d1f13708
SH		 984
985 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
986 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
987 sky2->vlgrp = grp;
988
2bb8c262 989 netif_tx_unlock_bh(dev);
d1f13708
SH		 990}
991
992static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
993{
994 struct sky2_port *sky2 = netdev_priv(dev);
995 struct sky2_hw *hw = sky2->hw;
996 u16 port = sky2->port;
d1f13708 997
2bb8c262 998 netif_tx_lock_bh(dev);
d1f13708
SH		 999
1000 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1001 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1002 if (sky2->vlgrp)
1003 sky2->vlgrp->vlan_devices[vid] = NULL;
1004
2bb8c262 1005 netif_tx_unlock_bh(dev);
d1f13708
SH		 1006}
1007#endif
1008
82788c7a 1009/*
14d0263f
SH		 1010 * Allocate an skb for receiving. If the MTU is large enough
1011 * make the skb non-linear with a fragment list of pages.
1012 *
82788c7a
SH		 1013 * It appears the hardware has a bug in the FIFO logic that
1014 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1015 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1016 * aligned except if slab debugging is enabled.
82788c7a 1017 */
14d0263f 1018static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1019{
1020 struct sk_buff *skb;
14d0263f
SH		 1021 unsigned long p;
1022 int i;
82788c7a 1023
14d0263f
SH		 1024 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1025 if (!skb)
1026 goto nomem;
1027
1028 p = (unsigned long) skb->data;
1029 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1030
1031 for (i = 0; i < sky2->rx_nfrags; i++) {
1032 struct page *page = alloc_page(GFP_ATOMIC);
1033
1034 if (!page)
1035 goto free_partial;
1036 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1037 }
1038
1039 return skb;
14d0263f
SH		 1040free_partial:
1041 kfree_skb(skb);
1042nomem:
1043 return NULL;
82788c7a
SH		 1044}
1045
cd28ab6a
SH		 1046/*
1047 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1048 * Normal case this ends up creating one list element for skb
1049 * in the receive ring. Worst case if using large MTU and each
1050 * allocation falls on a different 64 bit region, that results
1051 * in 6 list elements per ring entry.
1052 * One element is used for checksum enable/disable, and one
1053 * extra to avoid wrap.
cd28ab6a 1054 */
6b1a3aef 1055static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1056{
6b1a3aef 1057 struct sky2_hw *hw = sky2->hw;
14d0263f 1058 struct rx_ring_info *re;
6b1a3aef 1059 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1060 unsigned i, size, space, thresh;
cd28ab6a 1061
6b1a3aef 1062 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1063 sky2_qset(hw, rxq);
977bdf06 1064
8df9a876
SH		 1065 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1066 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
977bdf06
SH		 1067 /* MAC Rx RAM Read is controlled by hardware */
1068 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1069 }
1070
6b1a3aef
SH		 1071 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1072
1073 rx_set_checksum(sky2);
14d0263f
SH		 1074
1075 /* Space needed for frame data + headers rounded up */
1076 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1077 + 8;
1078
1079 /* Stopping point for hardware truncation */
1080 thresh = (size - 8) / sizeof(u32);
1081
1082 /* Account for overhead of skb - to avoid order > 0 allocation */
1083 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1084 + sizeof(struct skb_shared_info);
1085
1086 sky2->rx_nfrags = space >> PAGE_SHIFT;
1087 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1088
1089 if (sky2->rx_nfrags != 0) {
1090 /* Compute residue after pages */
1091 space = sky2->rx_nfrags << PAGE_SHIFT;
1092
1093 if (space < size)
1094 size -= space;
1095 else
1096 size = 0;
1097
1098 /* Optimize to handle small packets and headers */
1099 if (size < copybreak)
1100 size = copybreak;
1101 if (size < ETH_HLEN)
1102 size = ETH_HLEN;
1103 }
1104 sky2->rx_data_size = size;
1105
1106 /* Fill Rx ring */
793b883e 1107 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1108 re = sky2->rx_ring + i;
cd28ab6a 1109
14d0263f 1110 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1111 if (!re->skb)
1112 goto nomem;
1113
14d0263f
SH		 1114 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1115 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1116 }
1117
a1433ac4
SH		 1118 /*
1119 * The receiver hangs if it receives frames larger than the
1120 * packet buffer. As a workaround, truncate oversize frames, but
1121 * the register is limited to 9 bits, so if you do frames > 2052
1122 * you better get the MTU right!
1123 */
a1433ac4
SH		 1124 if (thresh > 0x1ff)
1125 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1126 else {
1127 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1128 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1129 }
1130
6b1a3aef
SH		 1131 /* Tell chip about available buffers */
1132 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1133 return 0;
1134nomem:
1135 sky2_rx_clean(sky2);
1136 return -ENOMEM;
1137}
1138
1139/* Bring up network interface. */
1140static int sky2_up(struct net_device *dev)
1141{
1142 struct sky2_port *sky2 = netdev_priv(dev);
1143 struct sky2_hw *hw = sky2->hw;
1144 unsigned port = sky2->port;
67712901 1145 u32 ramsize, imask;
ee7abb04 1146 int cap, err = -ENOMEM;
843a46f4 1147 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1148
ee7abb04
SH		 1149 /*
1150 * On dual port PCI-X card, there is an problem where status
1151 * can be received out of order due to split transactions
843a46f4 1152 */
ee7abb04
SH		 1153 if (otherdev && netif_running(otherdev) &&
1154 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1155 struct sky2_port *osky2 = netdev_priv(otherdev);
1156 u16 cmd;
1157
1158 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1159 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1160 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1161
1162 sky2->rx_csum = 0;
1163 osky2->rx_csum = 0;
1164 }
843a46f4 1165
cd28ab6a
SH		 1166 if (netif_msg_ifup(sky2))
1167 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1168
1169 /* must be power of 2 */
1170 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1171 TX_RING_SIZE *
1172 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1173 &sky2->tx_le_map);
1174 if (!sky2->tx_le)
1175 goto err_out;
1176
6cdbbdf3 1177 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1178 GFP_KERNEL);
1179 if (!sky2->tx_ring)
1180 goto err_out;
1181 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1182
1183 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1184 &sky2->rx_le_map);
1185 if (!sky2->rx_le)
1186 goto err_out;
1187 memset(sky2->rx_le, 0, RX_LE_BYTES);
1188
291ea614 1189 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1190 GFP_KERNEL);
1191 if (!sky2->rx_ring)
1192 goto err_out;
1193
d3bcfbeb
SH		 1194 sky2_phy_power(hw, port, 1);
1195
cd28ab6a
SH		 1196 sky2_mac_init(hw, port);
1197
67712901
SH		 1198 /* Register is number of 4K blocks on internal RAM buffer. */
1199 ramsize = sky2_read8(hw, B2_E_0) * 4;
1200 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1201
67712901
SH		 1202 if (ramsize > 0) {
1203 u32 rxspace;
cd28ab6a 1204
67712901
SH		 1205 if (ramsize < 16)
1206 rxspace = ramsize / 2;
1207 else
1208 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1209
67712901
SH		 1210 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1211 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1212
1213 /* Make sure SyncQ is disabled */
1214 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1215 RB_RST_SET);
1216 }
793b883e 1217
af4ed7e6 1218 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1219
977bdf06 1220 /* Set almost empty threshold */
c2716fb4
SH		 1221 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1222 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1223 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1224
6b1a3aef
SH		 1225 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1226 TX_RING_SIZE - 1);
cd28ab6a 1227
6b1a3aef 1228 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1229 if (err)
1230 goto err_out;
1231
cd28ab6a 1232 /* Enable interrupts from phy/mac for port */
e07b1aa8 1233 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1234 imask |= portirq_msk[port];
e07b1aa8
SH		 1235 sky2_write32(hw, B0_IMSK, imask);
1236
cd28ab6a
SH		 1237 return 0;
1238
1239err_out:
1b537565 1240 if (sky2->rx_le) {
cd28ab6a
SH		 1241 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1242 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1243 sky2->rx_le = NULL;
1244 }
1245 if (sky2->tx_le) {
cd28ab6a
SH		 1246 pci_free_consistent(hw->pdev,
1247 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1248 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1249 sky2->tx_le = NULL;
1250 }
1251 kfree(sky2->tx_ring);
1252 kfree(sky2->rx_ring);
cd28ab6a 1253
1b537565
SH		 1254 sky2->tx_ring = NULL;
1255 sky2->rx_ring = NULL;
cd28ab6a
SH		 1256 return err;
1257}
1258
793b883e
SH		 1259/* Modular subtraction in ring */
1260static inline int tx_dist(unsigned tail, unsigned head)
1261{
cb5d9547 1262 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1263}
cd28ab6a 1264
793b883e
SH		 1265/* Number of list elements available for next tx */
1266static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1267{
793b883e 1268 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1269}
1270
793b883e 1271/* Estimate of number of transmit list elements required */
28bd181a 1272static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1273{
793b883e
SH		 1274 unsigned count;
1275
1276 count = sizeof(dma_addr_t) / sizeof(u32);
1277 count += skb_shinfo(skb)->nr_frags * count;
1278
89114afd 1279 if (skb_is_gso(skb))
793b883e
SH		 1280 ++count;
1281
84fa7933 1282 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1283 ++count;
1284
1285 return count;
cd28ab6a
SH		 1286}
1287
793b883e
SH		 1288/*
1289 * Put one packet in ring for transmit.
1290 * A single packet can generate multiple list elements, and
1291 * the number of ring elements will probably be less than the number
1292 * of list elements used.
1293 */
cd28ab6a
SH		 1294static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1295{
1296 struct sky2_port *sky2 = netdev_priv(dev);
1297 struct sky2_hw *hw = sky2->hw;
d1f13708 1298 struct sky2_tx_le *le = NULL;
6cdbbdf3 1299 struct tx_ring_info *re;
cd28ab6a
SH		 1300 unsigned i, len;
1301 dma_addr_t mapping;
1302 u32 addr64;
1303 u16 mss;
1304 u8 ctrl;
1305
2bb8c262
SH		 1306 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1307 return NETDEV_TX_BUSY;
cd28ab6a 1308
793b883e 1309 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1310 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1311 dev->name, sky2->tx_prod, skb->len);
1312
cd28ab6a
SH		 1313 len = skb_headlen(skb);
1314 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1315 addr64 = high32(mapping);
793b883e 1316
a018e330
SH		 1317 /* Send high bits if changed or crosses boundary */
1318 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1319 le = get_tx_le(sky2);
f65b138c 1320 le->addr = cpu_to_le32(addr64);
793b883e 1321 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1322 sky2->tx_addr64 = high32(mapping + len);
793b883e 1323 }
cd28ab6a
SH		 1324
1325 /* Check for TCP Segmentation Offload */
7967168c 1326 mss = skb_shinfo(skb)->gso_size;
793b883e 1327 if (mss != 0) {
cd28ab6a
SH		 1328 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1329 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1330 mss += ETH_HLEN;
1331
e07560cd
SH		 1332 if (mss != sky2->tx_last_mss) {
1333 le = get_tx_le(sky2);
f65b138c 1334 le->addr = cpu_to_le32(mss);
e07560cd 1335 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1336 sky2->tx_last_mss = mss;
1337 }
cd28ab6a
SH		 1338 }
1339
cd28ab6a 1340 ctrl = 0;
d1f13708
SH		 1341#ifdef SKY2_VLAN_TAG_USED
1342 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1343 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1344 if (!le) {
1345 le = get_tx_le(sky2);
f65b138c 1346 le->addr = 0;
d1f13708 1347 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1348 } else
1349 le->opcode |= OP_VLAN;
1350 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1351 ctrl |= INS_VLAN;
1352 }
1353#endif
1354
1355 /* Handle TCP checksum offload */
84fa7933 1356 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1357 unsigned offset = skb->h.raw - skb->data;
1358 u32 tcpsum;
1359
1360 tcpsum = offset << 16; /* sum start */
ff1dcadb 1361 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1362
1363 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1364 if (skb->nh.iph->protocol == IPPROTO_UDP)
1365 ctrl |= UDPTCP;
1366
f65b138c
SH		 1367 if (tcpsum != sky2->tx_tcpsum) {
1368 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1369
1370 le = get_tx_le(sky2);
f65b138c 1371 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1372 le->length = 0; /* initial checksum value */
1373 le->ctrl = 1; /* one packet */
1374 le->opcode = OP_TCPLISW | HW_OWNER;
1375 }
cd28ab6a
SH		 1376 }
1377
1378 le = get_tx_le(sky2);
f65b138c 1379 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1380 le->length = cpu_to_le16(len);
1381 le->ctrl = ctrl;
793b883e 1382 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1383
291ea614 1384 re = tx_le_re(sky2, le);
cd28ab6a 1385 re->skb = skb;
6cdbbdf3 1386 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1387 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1388
1389 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1390 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1391
1392 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1393 frag->size, PCI_DMA_TODEVICE);
a036119f 1394 addr64 = high32(mapping);
793b883e
SH		 1395 if (addr64 != sky2->tx_addr64) {
1396 le = get_tx_le(sky2);
f65b138c 1397 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1398 le->ctrl = 0;
1399 le->opcode = OP_ADDR64 | HW_OWNER;
1400 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1401 }
1402
1403 le = get_tx_le(sky2);
f65b138c 1404 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1405 le->length = cpu_to_le16(frag->size);
1406 le->ctrl = ctrl;
793b883e 1407 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1408
291ea614
SH		 1409 re = tx_le_re(sky2, le);
1410 re->skb = skb;
1411 pci_unmap_addr_set(re, mapaddr, mapping);
1412 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1413 }
6cdbbdf3 1414
cd28ab6a
SH		 1415 le->ctrl |= EOP;
1416
97bda706
SH		 1417 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1418 netif_stop_queue(dev);
b19666d9 1419
290d4de5 1420 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1421
cd28ab6a
SH		 1422 dev->trans_start = jiffies;
1423 return NETDEV_TX_OK;
1424}
1425
cd28ab6a 1426/*
793b883e
SH		 1427 * Free ring elements from starting at tx_cons until "done"
1428 *
1429 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1430 * buffers so make sure not to free skb to early.
cd28ab6a 1431 */
d11c13e7 1432static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1433{
d11c13e7 1434 struct net_device *dev = sky2->netdev;
af2a58ac 1435 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1436 unsigned idx;
cd28ab6a 1437
0e3ff6aa 1438 BUG_ON(done >= TX_RING_SIZE);
2224795d 1439
291ea614
SH		 1440 for (idx = sky2->tx_cons; idx != done;
1441 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1442 struct sky2_tx_le *le = sky2->tx_le + idx;
1443 struct tx_ring_info *re = sky2->tx_ring + idx;
1444
1445 switch(le->opcode & ~HW_OWNER) {
1446 case OP_LARGESEND:
1447 case OP_PACKET:
1448 pci_unmap_single(pdev,
1449 pci_unmap_addr(re, mapaddr),
1450 pci_unmap_len(re, maplen),
1451 PCI_DMA_TODEVICE);
af2a58ac 1452 break;
291ea614
SH		 1453 case OP_BUFFER:
1454 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1455 pci_unmap_len(re, maplen),
734d1868 1456 PCI_DMA_TODEVICE);
291ea614
SH		 1457 break;
1458 }
1459
1460 if (le->ctrl & EOP) {
1461 if (unlikely(netif_msg_tx_done(sky2)))
1462 printk(KERN_DEBUG "%s: tx done %u\n",
1463 dev->name, idx);
794b2bd2 1464 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1465 }
1466
291ea614 1467 le->opcode = 0; /* paranoia */
793b883e 1468 }
793b883e 1469
291ea614 1470 sky2->tx_cons = idx;
22e11703 1471 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1472 netif_wake_queue(dev);
cd28ab6a
SH		 1473}
1474
1475/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1476static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1477{
2bb8c262
SH		 1478 struct sky2_port *sky2 = netdev_priv(dev);
1479
1480 netif_tx_lock_bh(dev);
d11c13e7 1481 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1482 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1483}
1484
1485/* Network shutdown */
1486static int sky2_down(struct net_device *dev)
1487{
1488 struct sky2_port *sky2 = netdev_priv(dev);
1489 struct sky2_hw *hw = sky2->hw;
1490 unsigned port = sky2->port;
1491 u16 ctrl;
e07b1aa8 1492 u32 imask;
cd28ab6a 1493
1b537565
SH		 1494 /* Never really got started! */
1495 if (!sky2->tx_le)
1496 return 0;
1497
cd28ab6a
SH		 1498 if (netif_msg_ifdown(sky2))
1499 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1500
018d1c66 1501 /* Stop more packets from being queued */
cd28ab6a
SH		 1502 netif_stop_queue(dev);
1503
ebc646f6
SH		 1504 /* Disable port IRQ */
1505 imask = sky2_read32(hw, B0_IMSK);
1506 imask &= ~portirq_msk[port];
1507 sky2_write32(hw, B0_IMSK, imask);
1508
d3bcfbeb 1509 sky2_gmac_reset(hw, port);
793b883e 1510
cd28ab6a
SH		 1511 /* Stop transmitter */
1512 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1513 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1514
1515 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1516 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1517
c2716fb4
SH		 1518 /* WA for dev. #4.209 */
1519 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1520 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1521 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1522 sky2->speed != SPEED_1000 ?
1523 TX_STFW_ENA : TX_STFW_DIS);
1524
cd28ab6a 1525 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1526 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1527 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1528
1529 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1530
1531 /* Workaround shared GMAC reset */
793b883e
SH		 1532 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1533 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1534 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1535
1536 /* Disable Force Sync bit and Enable Alloc bit */
1537 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1538 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1539
1540 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1541 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1542 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1543
1544 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1545 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1546 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1547
1548 /* Reset the Tx prefetch units */
1549 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1550 PREF_UNIT_RST_SET);
1551
1552 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1553
6b1a3aef 1554 sky2_rx_stop(sky2);
cd28ab6a
SH		 1555
1556 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1557 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1558
d3bcfbeb
SH		 1559 sky2_phy_power(hw, port, 0);
1560
d571b694 1561 /* turn off LED's */
cd28ab6a
SH		 1562 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1563
018d1c66
SH		 1564 synchronize_irq(hw->pdev->irq);
1565
2bb8c262 1566 sky2_tx_clean(dev);
cd28ab6a
SH		 1567 sky2_rx_clean(sky2);
1568
1569 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1570 sky2->rx_le, sky2->rx_le_map);
1571 kfree(sky2->rx_ring);
1572
1573 pci_free_consistent(hw->pdev,
1574 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1575 sky2->tx_le, sky2->tx_le_map);
1576 kfree(sky2->tx_ring);
1577
1b537565
SH		 1578 sky2->tx_le = NULL;
1579 sky2->rx_le = NULL;
1580
1581 sky2->rx_ring = NULL;
1582 sky2->tx_ring = NULL;
1583
cd28ab6a
SH		 1584 return 0;
1585}
1586
1587static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1588{
b89165f2 1589 if (!sky2_is_copper(hw))
793b883e
SH		 1590 return SPEED_1000;
1591
cd28ab6a
SH		 1592 if (hw->chip_id == CHIP_ID_YUKON_FE)
1593 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1594
1595 switch (aux & PHY_M_PS_SPEED_MSK) {
1596 case PHY_M_PS_SPEED_1000:
1597 return SPEED_1000;
1598 case PHY_M_PS_SPEED_100:
1599 return SPEED_100;
1600 default:
1601 return SPEED_10;
1602 }
1603}
1604
1605static void sky2_link_up(struct sky2_port *sky2)
1606{
1607 struct sky2_hw *hw = sky2->hw;
1608 unsigned port = sky2->port;
1609 u16 reg;
16ad91e1
SH		 1610 static const char *fc_name[] = {
1611 [FC_NONE] = "none",
1612 [FC_TX] = "tx",
1613 [FC_RX] = "rx",
1614 [FC_BOTH] = "both",
1615 };
cd28ab6a 1616
cd28ab6a 1617 /* enable Rx/Tx */
2eaba1a2 1618 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1619 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1620 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1621
1622 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1623
1624 netif_carrier_on(sky2->netdev);
1625 netif_wake_queue(sky2->netdev);
1626
1627 /* Turn on link LED */
793b883e 1628 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1629 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1630
ed6d32c7 1631 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1632 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1633 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1634
1635 switch(sky2->speed) {
1636 case SPEED_10:
1637 led |= PHY_M_LEDC_INIT_CTRL(7);
1638 break;
1639
1640 case SPEED_100:
1641 led |= PHY_M_LEDC_STA1_CTRL(7);
1642 break;
1643
1644 case SPEED_1000:
1645 led |= PHY_M_LEDC_STA0_CTRL(7);
1646 break;
1647 }
793b883e
SH		 1648
1649 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1650 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1652 }
1653
cd28ab6a
SH		 1654 if (netif_msg_link(sky2))
1655 printk(KERN_INFO PFX
d571b694 1656 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1657 sky2->netdev->name, sky2->speed,
1658 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1659 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1660}
1661
1662static void sky2_link_down(struct sky2_port *sky2)
1663{
1664 struct sky2_hw *hw = sky2->hw;
1665 unsigned port = sky2->port;
1666 u16 reg;
1667
1668 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1669
1670 reg = gma_read16(hw, port, GM_GP_CTRL);
1671 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1672 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1673
16ad91e1 1674 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1675 /* restore Asymmetric Pause bit */
1676 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1677 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1678 | PHY_M_AN_ASP);
cd28ab6a
SH		 1679 }
1680
cd28ab6a
SH		 1681 netif_carrier_off(sky2->netdev);
1682 netif_stop_queue(sky2->netdev);
1683
1684 /* Turn on link LED */
1685 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1686
1687 if (netif_msg_link(sky2))
1688 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1689
cd28ab6a
SH		 1690 sky2_phy_init(hw, port);
1691}
1692
16ad91e1
SH		 1693static enum flow_control sky2_flow(int rx, int tx)
1694{
1695 if (rx)
1696 return tx ? FC_BOTH : FC_RX;
1697 else
1698 return tx ? FC_TX : FC_NONE;
1699}
1700
793b883e
SH		 1701static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1702{
1703 struct sky2_hw *hw = sky2->hw;
1704 unsigned port = sky2->port;
1705 u16 lpa;
1706
1707 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1708
1709 if (lpa & PHY_M_AN_RF) {
1710 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1711 return -1;
1712 }
1713
793b883e
SH		 1714 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1715 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1716 sky2->netdev->name);
1717 return -1;
1718 }
1719
793b883e 1720 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1721 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1722
1723 /* Pause bits are offset (9..8) */
ed6d32c7 1724 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1725 aux >>= 6;
1726
16ad91e1
SH		 1727 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1728 aux & PHY_M_PS_TX_P_EN);
793b883e 1729
16ad91e1 1730 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2eaba1a2 1731 && hw->chip_id != CHIP_ID_YUKON_EC_U)
16ad91e1 1732 sky2->flow_status = FC_NONE;
2eaba1a2 1733
16ad91e1 1734 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1735 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1736 else
1737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1738
1739 return 0;
1740}
cd28ab6a 1741
e07b1aa8
SH		 1742/* Interrupt from PHY */
1743static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1744{
e07b1aa8
SH		 1745 struct net_device *dev = hw->dev[port];
1746 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1747 u16 istatus, phystat;
1748
ebc646f6
SH		 1749 if (!netif_running(dev))
1750 return;
1751
e07b1aa8
SH		 1752 spin_lock(&sky2->phy_lock);
1753 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1754 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1755
cd28ab6a
SH		 1756 if (netif_msg_intr(sky2))
1757 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1758 sky2->netdev->name, istatus, phystat);
1759
2eaba1a2 1760 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1761 if (sky2_autoneg_done(sky2, phystat) == 0)
1762 sky2_link_up(sky2);
1763 goto out;
1764 }
cd28ab6a 1765
793b883e
SH		 1766 if (istatus & PHY_M_IS_LSP_CHANGE)
1767 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1768
793b883e
SH		 1769 if (istatus & PHY_M_IS_DUP_CHANGE)
1770 sky2->duplex =
1771 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1772
793b883e
SH		 1773 if (istatus & PHY_M_IS_LST_CHANGE) {
1774 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1775 sky2_link_up(sky2);
793b883e
SH		 1776 else
1777 sky2_link_down(sky2);
cd28ab6a 1778 }
793b883e 1779out:
e07b1aa8 1780 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1781}
1782
302d1252
SH		 1783
1784/* Transmit timeout is only called if we are running, carries is up
1785 * and tx queue is full (stopped).
1786 */
cd28ab6a
SH		 1787static void sky2_tx_timeout(struct net_device *dev)
1788{
1789 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1790 struct sky2_hw *hw = sky2->hw;
1791 unsigned txq = txqaddr[sky2->port];
8f24664d 1792 u16 report, done;
cd28ab6a
SH		 1793
1794 if (netif_msg_timer(sky2))
1795 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1796
8f24664d
SH		 1797 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1798 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1799
8f24664d
SH		 1800 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1801 dev->name,
1802 sky2->tx_cons, sky2->tx_prod, report, done);
1803
1804 if (report != done) {
1805 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1806
1807 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1808 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1809 } else if (report != sky2->tx_cons) {
1810 printk(KERN_INFO PFX "status report lost?\n");
1811
2bb8c262 1812 netif_tx_lock_bh(dev);
8f24664d 1813 sky2_tx_complete(sky2, report);
2bb8c262 1814 netif_tx_unlock_bh(dev);
8f24664d
SH		 1815 } else {
1816 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1817
8f24664d
SH		 1818 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1819 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1820
2bb8c262 1821 sky2_tx_clean(dev);
8f24664d
SH		 1822
1823 sky2_qset(hw, txq);
1824 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1825 }
cd28ab6a
SH		 1826}
1827
1828static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1829{
6b1a3aef
SH		 1830 struct sky2_port *sky2 = netdev_priv(dev);
1831 struct sky2_hw *hw = sky2->hw;
1832 int err;
1833 u16 ctl, mode;
e07b1aa8 1834 u32 imask;
cd28ab6a
SH		 1835
1836 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1837 return -EINVAL;
1838
5a5b1ea0
SH		 1839 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1840 return -EINVAL;
1841
6b1a3aef
SH		 1842 if (!netif_running(dev)) {
1843 dev->mtu = new_mtu;
1844 return 0;
1845 }
1846
e07b1aa8 1847 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1848 sky2_write32(hw, B0_IMSK, 0);
1849
018d1c66
SH		 1850 dev->trans_start = jiffies; /* prevent tx timeout */
1851 netif_stop_queue(dev);
1852 netif_poll_disable(hw->dev[0]);
1853
e07b1aa8
SH		 1854 synchronize_irq(hw->pdev->irq);
1855
6b1a3aef
SH		 1856 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1857 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1858 sky2_rx_stop(sky2);
1859 sky2_rx_clean(sky2);
cd28ab6a
SH		 1860
1861 dev->mtu = new_mtu;
14d0263f 1862
6b1a3aef
SH		 1863 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1864 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1865
1866 if (dev->mtu > ETH_DATA_LEN)
1867 mode |= GM_SMOD_JUMBO_ENA;
1868
1869 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1870
6b1a3aef 1871 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1872
6b1a3aef 1873 err = sky2_rx_start(sky2);
e07b1aa8 1874 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1875
1b537565
SH		 1876 if (err)
1877 dev_close(dev);
1878 else {
1879 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1880
1881 netif_poll_enable(hw->dev[0]);
1882 netif_wake_queue(dev);
1883 }
1884
cd28ab6a
SH		 1885 return err;
1886}
1887
14d0263f
SH		 1888/* For small just reuse existing skb for next receive */
1889static struct sk_buff *receive_copy(struct sky2_port *sky2,
1890 const struct rx_ring_info *re,
1891 unsigned length)
1892{
1893 struct sk_buff *skb;
1894
1895 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1896 if (likely(skb)) {
1897 skb_reserve(skb, 2);
1898 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1899 length, PCI_DMA_FROMDEVICE);
1900 memcpy(skb->data, re->skb->data, length);
1901 skb->ip_summed = re->skb->ip_summed;
1902 skb->csum = re->skb->csum;
1903 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1904 length, PCI_DMA_FROMDEVICE);
1905 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1906 skb_put(skb, length);
14d0263f
SH		 1907 }
1908 return skb;
1909}
1910
1911/* Adjust length of skb with fragments to match received data */
1912static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1913 unsigned int length)
1914{
1915 int i, num_frags;
1916 unsigned int size;
1917
1918 /* put header into skb */
1919 size = min(length, hdr_space);
1920 skb->tail += size;
1921 skb->len += size;
1922 length -= size;
1923
1924 num_frags = skb_shinfo(skb)->nr_frags;
1925 for (i = 0; i < num_frags; i++) {
1926 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1927
1928 if (length == 0) {
1929 /* don't need this page */
1930 __free_page(frag->page);
1931 --skb_shinfo(skb)->nr_frags;
1932 } else {
1933 size = min(length, (unsigned) PAGE_SIZE);
1934
1935 frag->size = size;
1936 skb->data_len += size;
1937 skb->truesize += size;
1938 skb->len += size;
1939 length -= size;
1940 }
1941 }
1942}
1943
1944/* Normal packet - take skb from ring element and put in a new one */
1945static struct sk_buff *receive_new(struct sky2_port *sky2,
1946 struct rx_ring_info *re,
1947 unsigned int length)
1948{
1949 struct sk_buff *skb, *nskb;
1950 unsigned hdr_space = sky2->rx_data_size;
1951
1952 pr_debug(PFX "receive new length=%d\n", length);
1953
1954 /* Don't be tricky about reusing pages (yet) */
1955 nskb = sky2_rx_alloc(sky2);
1956 if (unlikely(!nskb))
1957 return NULL;
1958
1959 skb = re->skb;
1960 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1961
1962 prefetch(skb->data);
1963 re->skb = nskb;
1964 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1965
1966 if (skb_shinfo(skb)->nr_frags)
1967 skb_put_frags(skb, hdr_space, length);
1968 else
489b10c1 1969 skb_put(skb, length);
14d0263f
SH		 1970 return skb;
1971}
1972
cd28ab6a
SH		 1973/*
1974 * Receive one packet.
d571b694 1975 * For larger packets, get new buffer.
cd28ab6a 1976 */
497d7c86 1977static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1978 u16 length, u32 status)
1979{
497d7c86 1980 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1981 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1982 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1983
1984 if (unlikely(netif_msg_rx_status(sky2)))
1985 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1986 dev->name, sky2->rx_next, status, length);
cd28ab6a 1987
793b883e 1988 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1989 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1990
42eeea01 1991 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1992 goto error;
1993
42eeea01
SH		 1994 if (!(status & GMR_FS_RX_OK))
1995 goto resubmit;
1996
497d7c86 1997 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1998 goto oversize;
1999
14d0263f
SH		 2000 if (length < copybreak)
2001 skb = receive_copy(sky2, re, length);
2002 else
2003 skb = receive_new(sky2, re, length);
793b883e 2004resubmit:
14d0263f 2005 sky2_rx_submit(sky2, re);
79e57d32 2006
cd28ab6a
SH		 2007 return skb;
2008
6e15b712
SH		 2009oversize:
2010 ++sky2->net_stats.rx_over_errors;
2011 goto resubmit;
2012
cd28ab6a 2013error:
6e15b712 2014 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2015 if (status & GMR_FS_RX_FF_OV) {
2016 sky2->net_stats.rx_fifo_errors++;
2017 goto resubmit;
2018 }
6e15b712 2019
3be92a70 2020 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2021 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2022 dev->name, status, length);
793b883e
SH		 2023
2024 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2025 sky2->net_stats.rx_length_errors++;
2026 if (status & GMR_FS_FRAGMENT)
2027 sky2->net_stats.rx_frame_errors++;
2028 if (status & GMR_FS_CRC_ERR)
2029 sky2->net_stats.rx_crc_errors++;
79e57d32 2030
793b883e 2031 goto resubmit;
cd28ab6a
SH		 2032}
2033
e07b1aa8
SH		 2034/* Transmit complete */
2035static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2036{
e07b1aa8 2037 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2038
e07b1aa8 2039 if (netif_running(dev)) {
2bb8c262 2040 netif_tx_lock(dev);
e07b1aa8 2041 sky2_tx_complete(sky2, last);
2bb8c262 2042 netif_tx_unlock(dev);
2224795d 2043 }
cd28ab6a
SH		 2044}
2045
e07b1aa8
SH		 2046/* Process status response ring */
2047static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2048{
22e11703 2049 struct sky2_port *sky2;
e07b1aa8 2050 int work_done = 0;
22e11703 2051 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2052 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2053
af2a58ac 2054 rmb();
bea86103 2055
e71ebd73 2056 while (hw->st_idx != hwidx) {
13210ce5
SH		 2057 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2058 struct net_device *dev;
cd28ab6a 2059 struct sk_buff *skb;
cd28ab6a
SH		 2060 u32 status;
2061 u16 length;
2062
cb5d9547 2063 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2064
e71ebd73
SH		 2065 BUG_ON(le->link >= 2);
2066 dev = hw->dev[le->link];
13210ce5
SH		 2067
2068 sky2 = netdev_priv(dev);
f65b138c
SH		 2069 length = le16_to_cpu(le->length);
2070 status = le32_to_cpu(le->status);
cd28ab6a 2071
e71ebd73 2072 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2073 case OP_RXSTAT:
497d7c86 2074 skb = sky2_receive(dev, length, status);
d1f13708 2075 if (!skb)
5df79111 2076 goto force_update;
13210ce5 2077
13210ce5
SH		 2078 skb->protocol = eth_type_trans(skb, dev);
2079 dev->last_rx = jiffies;
2080
d1f13708
SH		 2081#ifdef SKY2_VLAN_TAG_USED
2082 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2083 vlan_hwaccel_receive_skb(skb,
2084 sky2->vlgrp,
2085 be16_to_cpu(sky2->rx_tag));
2086 } else
2087#endif
cd28ab6a 2088 netif_receive_skb(skb);
13210ce5 2089
22e11703
SH		 2090 /* Update receiver after 16 frames */
2091 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2092force_update:
2093 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2094 buf_write[le->link] = 0;
2095 }
2096
2097 /* Stop after net poll weight */
13210ce5
SH		 2098 if (++work_done >= to_do)
2099 goto exit_loop;
cd28ab6a
SH		 2100 break;
2101
d1f13708
SH		 2102#ifdef SKY2_VLAN_TAG_USED
2103 case OP_RXVLAN:
2104 sky2->rx_tag = length;
2105 break;
2106
2107 case OP_RXCHKSVLAN:
2108 sky2->rx_tag = length;
2109 /* fall through */
2110#endif
cd28ab6a 2111 case OP_RXCHKS:
d11c13e7 2112 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2113 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2114 skb->csum = status & 0xffff;
cd28ab6a
SH		 2115 break;
2116
2117 case OP_TXINDEXLE:
13b97b74 2118 /* TX index reports status for both ports */
f55925d7
SH		 2119 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2120 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2121 if (hw->dev[1])
2122 sky2_tx_done(hw->dev[1],
2123 ((status >> 24) & 0xff)
2124 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2125 break;
2126
cd28ab6a
SH		 2127 default:
2128 if (net_ratelimit())
793b883e 2129 printk(KERN_WARNING PFX
e71ebd73
SH		 2130 "unknown status opcode 0x%x\n", le->opcode);
2131 goto exit_loop;
cd28ab6a 2132 }
13210ce5 2133 }
cd28ab6a 2134
fe2a24df
SH		 2135 /* Fully processed status ring so clear irq */
2136 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2137
13210ce5 2138exit_loop:
22e11703
SH		 2139 if (buf_write[0]) {
2140 sky2 = netdev_priv(hw->dev[0]);
2141 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2142 }
2143
2144 if (buf_write[1]) {
2145 sky2 = netdev_priv(hw->dev[1]);
2146 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2147 }
2148
e07b1aa8 2149 return work_done;
cd28ab6a
SH		 2150}
2151
2152static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2153{
2154 struct net_device *dev = hw->dev[port];
2155
3be92a70
SH		 2156 if (net_ratelimit())
2157 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2158 dev->name, status);
cd28ab6a
SH		 2159
2160 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2161 if (net_ratelimit())
2162 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2163 dev->name);
cd28ab6a
SH		 2164 /* Clear IRQ */
2165 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2166 }
2167
2168 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2169 if (net_ratelimit())
2170 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2171 dev->name);
cd28ab6a
SH		 2172
2173 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2174 }
2175
2176 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2177 if (net_ratelimit())
2178 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2179 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2180 }
2181
2182 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2183 if (net_ratelimit())
2184 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2185 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2186 }
2187
2188 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2189 if (net_ratelimit())
2190 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2191 dev->name);
cd28ab6a
SH		 2192 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2193 }
2194}
2195
2196static void sky2_hw_intr(struct sky2_hw *hw)
2197{
2198 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2199
793b883e 2200 if (status & Y2_IS_TIST_OV)
cd28ab6a 2201 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2202
2203 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2204 u16 pci_err;
2205
56a645cc 2206 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2207 if (net_ratelimit())
2208 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2209 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2210
2211 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2212 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2213 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2214 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2215 }
2216
2217 if (status & Y2_IS_PCI_EXP) {
d571b694 2218 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2219 u32 pex_err;
2220
7bd656d1 2221 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2222
3be92a70
SH		 2223 if (net_ratelimit())
2224 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2225 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2226
2227 /* clear the interrupt */
2228 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2229 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2230 0xffffffffUL);
cd28ab6a
SH		 2231 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2232
7bd656d1 2233 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2234 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2235 hwmsk &= ~Y2_IS_PCI_EXP;
2236 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2237 }
2238 }
2239
2240 if (status & Y2_HWE_L1_MASK)
2241 sky2_hw_error(hw, 0, status);
2242 status >>= 8;
2243 if (status & Y2_HWE_L1_MASK)
2244 sky2_hw_error(hw, 1, status);
2245}
2246
2247static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2248{
2249 struct net_device *dev = hw->dev[port];
2250 struct sky2_port *sky2 = netdev_priv(dev);
2251 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2252
2253 if (netif_msg_intr(sky2))
2254 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2255 dev->name, status);
2256
2257 if (status & GM_IS_RX_FF_OR) {
2258 ++sky2->net_stats.rx_fifo_errors;
2259 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2260 }
2261
2262 if (status & GM_IS_TX_FF_UR) {
2263 ++sky2->net_stats.tx_fifo_errors;
2264 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2265 }
cd28ab6a
SH		 2266}
2267
d257924e
SH		 2268/* This should never happen it is a fatal situation */
2269static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2270 const char *rxtx, u32 mask)
2271{
2272 struct net_device *dev = hw->dev[port];
2273 struct sky2_port *sky2 = netdev_priv(dev);
2274 u32 imask;
2275
2276 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2277 dev ? dev->name : "<not registered>", rxtx);
2278
2279 imask = sky2_read32(hw, B0_IMSK);
2280 imask &= ~mask;
2281 sky2_write32(hw, B0_IMSK, imask);
2282
2283 if (dev) {
2284 spin_lock(&sky2->phy_lock);
2285 sky2_link_down(sky2);
2286 spin_unlock(&sky2->phy_lock);
2287 }
2288}
cd28ab6a 2289
d27ed387
SH		 2290/* If idle then force a fake soft NAPI poll once a second
2291 * to work around cases where sharing an edge triggered interrupt.
2292 */
eb35cf60
SH		 2293static inline void sky2_idle_start(struct sky2_hw *hw)
2294{
2295 if (idle_timeout > 0)
2296 mod_timer(&hw->idle_timer,
2297 jiffies + msecs_to_jiffies(idle_timeout));
2298}
2299
d27ed387
SH		 2300static void sky2_idle(unsigned long arg)
2301{
01bd7564
SH		 2302 struct sky2_hw *hw = (struct sky2_hw *) arg;
2303 struct net_device *dev = hw->dev[0];
d27ed387 2304
d27ed387
SH		 2305 if (__netif_rx_schedule_prep(dev))
2306 __netif_rx_schedule(dev);
01bd7564
SH		 2307
2308 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2309}
2310
2311
e07b1aa8 2312static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2313{
e07b1aa8
SH		 2314 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2315 int work_limit = min(dev0->quota, *budget);
2316 int work_done = 0;
fb2690a9 2317 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2318
1e5f1283
SH		 2319 if (status & Y2_IS_HW_ERR)
2320 sky2_hw_intr(hw);
d257924e 2321
1e5f1283
SH		 2322 if (status & Y2_IS_IRQ_PHY1)
2323 sky2_phy_intr(hw, 0);
cd28ab6a 2324
1e5f1283
SH		 2325 if (status & Y2_IS_IRQ_PHY2)
2326 sky2_phy_intr(hw, 1);
cd28ab6a 2327
1e5f1283
SH		 2328 if (status & Y2_IS_IRQ_MAC1)
2329 sky2_mac_intr(hw, 0);
cd28ab6a 2330
1e5f1283
SH		 2331 if (status & Y2_IS_IRQ_MAC2)
2332 sky2_mac_intr(hw, 1);
cd28ab6a 2333
1e5f1283
SH		 2334 if (status & Y2_IS_CHK_RX1)
2335 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2336
1e5f1283
SH		 2337 if (status & Y2_IS_CHK_RX2)
2338 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2339
1e5f1283
SH		 2340 if (status & Y2_IS_CHK_TXA1)
2341 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2342
1e5f1283
SH		 2343 if (status & Y2_IS_CHK_TXA2)
2344 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2345
1e5f1283 2346 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2347 if (work_done < work_limit) {
2348 netif_rx_complete(dev0);
86fba634 2349
fe2a24df
SH		 2350 sky2_read32(hw, B0_Y2_SP_LISR);
2351 return 0;
2352 } else {
2353 *budget -= work_done;
2354 dev0->quota -= work_done;
1e5f1283 2355 return 1;
fe2a24df 2356 }
e07b1aa8
SH		 2357}
2358
7d12e780 2359static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2360{
2361 struct sky2_hw *hw = dev_id;
2362 struct net_device *dev0 = hw->dev[0];
2363 u32 status;
2364
2365 /* Reading this mask interrupts as side effect */
2366 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2367 if (status == 0 || status == ~0)
2368 return IRQ_NONE;
793b883e 2369
e07b1aa8
SH		 2370 prefetch(&hw->st_le[hw->st_idx]);
2371 if (likely(__netif_rx_schedule_prep(dev0)))
2372 __netif_rx_schedule(dev0);
793b883e 2373
cd28ab6a
SH		 2374 return IRQ_HANDLED;
2375}
2376
2377#ifdef CONFIG_NET_POLL_CONTROLLER
2378static void sky2_netpoll(struct net_device *dev)
2379{
2380 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2381 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2382
88d11360
SH		 2383 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2384 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2385}
2386#endif
2387
2388/* Chip internal frequency for clock calculations */
fb17358f 2389static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2390{
793b883e 2391 switch (hw->chip_id) {
cd28ab6a 2392 case CHIP_ID_YUKON_EC:
5a5b1ea0 2393 case CHIP_ID_YUKON_EC_U:
fb17358f 2394 return 125; /* 125 Mhz */
cd28ab6a 2395 case CHIP_ID_YUKON_FE:
fb17358f 2396 return 100; /* 100 Mhz */
793b883e 2397 default: /* YUKON_XL */
fb17358f 2398 return 156; /* 156 Mhz */
cd28ab6a
SH		 2399 }
2400}
2401
fb17358f 2402static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2403{
fb17358f 2404 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2405}
2406
fb17358f 2407static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2408{
fb17358f 2409 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2410}
2411
fb17358f 2412
59139528 2413static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2414{
cd28ab6a 2415 u16 status;
b89165f2 2416 u8 t8;
56a645cc 2417 int i;
cd28ab6a 2418
cd28ab6a 2419 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2420
cd28ab6a
SH		 2421 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2422 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2423 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2424 pci_name(hw->pdev), hw->chip_id);
2425 return -EOPNOTSUPP;
2426 }
2427
290d4de5
SH		 2428 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2429
2430 /* This rev is really old, and requires untested workarounds */
2431 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2432 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2433 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2434 hw->chip_id, hw->chip_rev);
2435 return -EOPNOTSUPP;
2436 }
2437
cd28ab6a
SH		 2438 /* disable ASF */
2439 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2440 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2441 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2442 }
2443
2444 /* do a SW reset */
2445 sky2_write8(hw, B0_CTST, CS_RST_SET);
2446 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2447
2448 /* clear PCI errors, if any */
56a645cc 2449 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2450
cd28ab6a 2451 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2452 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2453
cd28ab6a
SH		 2454
2455 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2456
2457 /* clear any PEX errors */
7bd656d1
SH		 2458 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2459 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2460
cd28ab6a 2461
b89165f2 2462 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2463 hw->ports = 1;
2464 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2465 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2466 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2467 ++hw->ports;
2468 }
cd28ab6a 2469
5afa0a9c 2470 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2471
2472 for (i = 0; i < hw->ports; i++) {
2473 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2474 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2475 }
2476
2477 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2478
793b883e
SH		 2479 /* Clear I2C IRQ noise */
2480 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2481
2482 /* turn off hardware timer (unused) */
2483 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2484 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2485
cd28ab6a
SH		 2486 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2487
69634ee7
SH		 2488 /* Turn off descriptor polling */
2489 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2490
2491 /* Turn off receive timestamp */
2492 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2493 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2494
2495 /* enable the Tx Arbiters */
2496 for (i = 0; i < hw->ports; i++)
2497 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2498
2499 /* Initialize ram interface */
2500 for (i = 0; i < hw->ports; i++) {
793b883e 2501 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2502
2503 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2504 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2505 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2506 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2507 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2508 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2509 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2510 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2511 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2512 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2513 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2514 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2515 }
2516
7bd656d1 2517 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2518
cd28ab6a 2519 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2520 sky2_gmac_reset(hw, i);
cd28ab6a 2521
cd28ab6a
SH		 2522 memset(hw->st_le, 0, STATUS_LE_BYTES);
2523 hw->st_idx = 0;
2524
2525 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2526 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2527
2528 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2529 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2530
2531 /* Set the list last index */
793b883e 2532 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2533
290d4de5
SH		 2534 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2535 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2536
290d4de5
SH		 2537 /* set Status-FIFO ISR watermark */
2538 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2539 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2540 else
2541 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2542
290d4de5 2543 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2544 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2545 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2546
793b883e 2547 /* enable status unit */
cd28ab6a
SH		 2548 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2549
2550 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2551 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2552 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2553
2554 return 0;
2555}
2556
28bd181a 2557static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2558{
b89165f2
SH		 2559 if (sky2_is_copper(hw)) {
2560 u32 modes = SUPPORTED_10baseT_Half
2561 | SUPPORTED_10baseT_Full
2562 | SUPPORTED_100baseT_Half
2563 | SUPPORTED_100baseT_Full
2564 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2565
2566 if (hw->chip_id != CHIP_ID_YUKON_FE)
2567 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2568 | SUPPORTED_1000baseT_Full;
2569 return modes;
cd28ab6a 2570 } else
b89165f2
SH		 2571 return SUPPORTED_1000baseT_Half
2572 | SUPPORTED_1000baseT_Full
2573 | SUPPORTED_Autoneg
2574 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2575}
2576
793b883e 2577static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2578{
2579 struct sky2_port *sky2 = netdev_priv(dev);
2580 struct sky2_hw *hw = sky2->hw;
2581
2582 ecmd->transceiver = XCVR_INTERNAL;
2583 ecmd->supported = sky2_supported_modes(hw);
2584 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2585 if (sky2_is_copper(hw)) {
cd28ab6a 2586 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2587 | SUPPORTED_10baseT_Full
2588 | SUPPORTED_100baseT_Half
2589 | SUPPORTED_100baseT_Full
2590 | SUPPORTED_1000baseT_Half
2591 | SUPPORTED_1000baseT_Full
2592 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2593 ecmd->port = PORT_TP;
b89165f2
SH		 2594 ecmd->speed = sky2->speed;
2595 } else {
2596 ecmd->speed = SPEED_1000;
cd28ab6a 2597 ecmd->port = PORT_FIBRE;
b89165f2 2598 }
cd28ab6a
SH		 2599
2600 ecmd->advertising = sky2->advertising;
2601 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2602 ecmd->duplex = sky2->duplex;
2603 return 0;
2604}
2605
2606static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2607{
2608 struct sky2_port *sky2 = netdev_priv(dev);
2609 const struct sky2_hw *hw = sky2->hw;
2610 u32 supported = sky2_supported_modes(hw);
2611
2612 if (ecmd->autoneg == AUTONEG_ENABLE) {
2613 ecmd->advertising = supported;
2614 sky2->duplex = -1;
2615 sky2->speed = -1;
2616 } else {
2617 u32 setting;
2618
793b883e 2619 switch (ecmd->speed) {
cd28ab6a
SH		 2620 case SPEED_1000:
2621 if (ecmd->duplex == DUPLEX_FULL)
2622 setting = SUPPORTED_1000baseT_Full;
2623 else if (ecmd->duplex == DUPLEX_HALF)
2624 setting = SUPPORTED_1000baseT_Half;
2625 else
2626 return -EINVAL;
2627 break;
2628 case SPEED_100:
2629 if (ecmd->duplex == DUPLEX_FULL)
2630 setting = SUPPORTED_100baseT_Full;
2631 else if (ecmd->duplex == DUPLEX_HALF)
2632 setting = SUPPORTED_100baseT_Half;
2633 else
2634 return -EINVAL;
2635 break;
2636
2637 case SPEED_10:
2638 if (ecmd->duplex == DUPLEX_FULL)
2639 setting = SUPPORTED_10baseT_Full;
2640 else if (ecmd->duplex == DUPLEX_HALF)
2641 setting = SUPPORTED_10baseT_Half;
2642 else
2643 return -EINVAL;
2644 break;
2645 default:
2646 return -EINVAL;
2647 }
2648
2649 if ((setting & supported) == 0)
2650 return -EINVAL;
2651
2652 sky2->speed = ecmd->speed;
2653 sky2->duplex = ecmd->duplex;
2654 }
2655
2656 sky2->autoneg = ecmd->autoneg;
2657 sky2->advertising = ecmd->advertising;
2658
1b537565
SH		 2659 if (netif_running(dev))
2660 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2661
2662 return 0;
2663}
2664
2665static void sky2_get_drvinfo(struct net_device *dev,
2666 struct ethtool_drvinfo *info)
2667{
2668 struct sky2_port *sky2 = netdev_priv(dev);
2669
2670 strcpy(info->driver, DRV_NAME);
2671 strcpy(info->version, DRV_VERSION);
2672 strcpy(info->fw_version, "N/A");
2673 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2674}
2675
2676static const struct sky2_stat {
793b883e
SH		 2677 char name[ETH_GSTRING_LEN];
2678 u16 offset;
cd28ab6a
SH		 2679} sky2_stats[] = {
2680 { "tx_bytes", GM_TXO_OK_HI },
2681 { "rx_bytes", GM_RXO_OK_HI },
2682 { "tx_broadcast", GM_TXF_BC_OK },
2683 { "rx_broadcast", GM_RXF_BC_OK },
2684 { "tx_multicast", GM_TXF_MC_OK },
2685 { "rx_multicast", GM_RXF_MC_OK },
2686 { "tx_unicast", GM_TXF_UC_OK },
2687 { "rx_unicast", GM_RXF_UC_OK },
2688 { "tx_mac_pause", GM_TXF_MPAUSE },
2689 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2690 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2691 { "late_collision",GM_TXF_LAT_COL },
2692 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2693 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2694 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2695
d2604540 2696 { "rx_short", GM_RXF_SHT },
cd28ab6a 2697 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2698 { "rx_64_byte_packets", GM_RXF_64B },
2699 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2700 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2701 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2702 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2703 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2704 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2705 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2706 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2707 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2708 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2709
2710 { "tx_64_byte_packets", GM_TXF_64B },
2711 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2712 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2713 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2714 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2715 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2716 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2717 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2718};
2719
cd28ab6a
SH		 2720static u32 sky2_get_rx_csum(struct net_device *dev)
2721{
2722 struct sky2_port *sky2 = netdev_priv(dev);
2723
2724 return sky2->rx_csum;
2725}
2726
2727static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2728{
2729 struct sky2_port *sky2 = netdev_priv(dev);
2730
2731 sky2->rx_csum = data;
793b883e 2732
cd28ab6a
SH		 2733 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2734 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2735
2736 return 0;
2737}
2738
2739static u32 sky2_get_msglevel(struct net_device *netdev)
2740{
2741 struct sky2_port *sky2 = netdev_priv(netdev);
2742 return sky2->msg_enable;
2743}
2744
9a7ae0a9
SH		 2745static int sky2_nway_reset(struct net_device *dev)
2746{
2747 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2748
16ad91e1 2749 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2750 return -EINVAL;
2751
1b537565 2752 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2753
2754 return 0;
2755}
2756
793b883e 2757static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2758{
2759 struct sky2_hw *hw = sky2->hw;
2760 unsigned port = sky2->port;
2761 int i;
2762
2763 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2764 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2765 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2766 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2767
793b883e 2768 for (i = 2; i < count; i++)
cd28ab6a
SH		 2769 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2770}
2771
cd28ab6a
SH		 2772static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2773{
2774 struct sky2_port *sky2 = netdev_priv(netdev);
2775 sky2->msg_enable = value;
2776}
2777
2778static int sky2_get_stats_count(struct net_device *dev)
2779{
2780 return ARRAY_SIZE(sky2_stats);
2781}
2782
2783static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2784 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2785{
2786 struct sky2_port *sky2 = netdev_priv(dev);
2787
793b883e 2788 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2789}
2790
793b883e 2791static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2792{
2793 int i;
2794
2795 switch (stringset) {
2796 case ETH_SS_STATS:
2797 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2798 memcpy(data + i * ETH_GSTRING_LEN,
2799 sky2_stats[i].name, ETH_GSTRING_LEN);
2800 break;
2801 }
2802}
2803
2804/* Use hardware MIB variables for critical path statistics and
2805 * transmit feedback not reported at interrupt.
2806 * Other errors are accounted for in interrupt handler.
2807 */
2808static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2809{
2810 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2811 u64 data[13];
cd28ab6a 2812
793b883e 2813 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2814
2815 sky2->net_stats.tx_bytes = data[0];
2816 sky2->net_stats.rx_bytes = data[1];
2817 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2818 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2819 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2820 sky2->net_stats.collisions = data[10];
2821 sky2->net_stats.tx_aborted_errors = data[12];
2822
2823 return &sky2->net_stats;
2824}
2825
2826static int sky2_set_mac_address(struct net_device *dev, void *p)
2827{
2828 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2829 struct sky2_hw *hw = sky2->hw;
2830 unsigned port = sky2->port;
2831 const struct sockaddr *addr = p;
cd28ab6a
SH		 2832
2833 if (!is_valid_ether_addr(addr->sa_data))
2834 return -EADDRNOTAVAIL;
2835
cd28ab6a 2836 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2837 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2838 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2839 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2840 dev->dev_addr, ETH_ALEN);
1b537565 2841
a8ab1ec0
SH		 2842 /* virtual address for data */
2843 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2844
2845 /* physical address: used for pause frames */
2846 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2847
2848 return 0;
cd28ab6a
SH		 2849}
2850
a052b52f
SH		 2851static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2852{
2853 u32 bit;
2854
2855 bit = ether_crc(ETH_ALEN, addr) & 63;
2856 filter[bit >> 3] |= 1 << (bit & 7);
2857}
2858
cd28ab6a
SH		 2859static void sky2_set_multicast(struct net_device *dev)
2860{
2861 struct sky2_port *sky2 = netdev_priv(dev);
2862 struct sky2_hw *hw = sky2->hw;
2863 unsigned port = sky2->port;
2864 struct dev_mc_list *list = dev->mc_list;
2865 u16 reg;
2866 u8 filter[8];
a052b52f
SH		 2867 int rx_pause;
2868 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2869
a052b52f 2870 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2871 memset(filter, 0, sizeof(filter));
2872
2873 reg = gma_read16(hw, port, GM_RX_CTRL);
2874 reg |= GM_RXCR_UCF_ENA;
2875
d571b694 2876 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2877 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2878 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2879 memset(filter, 0xff, sizeof(filter));
a052b52f 2880 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2881 reg &= ~GM_RXCR_MCF_ENA;
2882 else {
2883 int i;
2884 reg |= GM_RXCR_MCF_ENA;
2885
a052b52f
SH		 2886 if (rx_pause)
2887 sky2_add_filter(filter, pause_mc_addr);
2888
2889 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2890 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 2891 }
2892
cd28ab6a 2893 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2894 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2895 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2896 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2897 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2898 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2899 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2900 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2901
2902 gma_write16(hw, port, GM_RX_CTRL, reg);
2903}
2904
2905/* Can have one global because blinking is controlled by
2906 * ethtool and that is always under RTNL mutex
2907 */
91c86df5 2908static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2909{
793b883e
SH		 2910 u16 pg;
2911
793b883e
SH		 2912 switch (hw->chip_id) {
2913 case CHIP_ID_YUKON_XL:
2914 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2915 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2916 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2917 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2918 PHY_M_LEDC_INIT_CTRL(7) |
2919 PHY_M_LEDC_STA1_CTRL(7) |
2920 PHY_M_LEDC_STA0_CTRL(7))
2921 : 0);
2922
2923 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2924 break;
2925
2926 default:
2927 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2928 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2929 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2930 PHY_M_LED_MO_10(MO_LED_ON) |
2931 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2932 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2933 PHY_M_LED_MO_RX(MO_LED_ON)
2934 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2935 PHY_M_LED_MO_10(MO_LED_OFF) |
2936 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2937 PHY_M_LED_MO_1000(MO_LED_OFF) |
2938 PHY_M_LED_MO_RX(MO_LED_OFF));
2939
793b883e 2940 }
cd28ab6a
SH		 2941}
2942
2943/* blink LED's for finding board */
2944static int sky2_phys_id(struct net_device *dev, u32 data)
2945{
2946 struct sky2_port *sky2 = netdev_priv(dev);
2947 struct sky2_hw *hw = sky2->hw;
2948 unsigned port = sky2->port;
793b883e 2949 u16 ledctrl, ledover = 0;
cd28ab6a 2950 long ms;
91c86df5 2951 int interrupted;
cd28ab6a
SH		 2952 int onoff = 1;
2953
793b883e 2954 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2955 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2956 else
2957 ms = data * 1000;
2958
2959 /* save initial values */
e07b1aa8 2960 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2961 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2962 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2963 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2964 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2965 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2966 } else {
2967 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2968 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2969 }
cd28ab6a 2970
91c86df5
SH		 2971 interrupted = 0;
2972 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2973 sky2_led(hw, port, onoff);
2974 onoff = !onoff;
2975
e07b1aa8 2976 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2977 interrupted = msleep_interruptible(250);
e07b1aa8 2978 spin_lock_bh(&sky2->phy_lock);
91c86df5 2979
cd28ab6a
SH		 2980 ms -= 250;
2981 }
2982
2983 /* resume regularly scheduled programming */
793b883e
SH		 2984 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2985 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2986 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2987 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2988 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2989 } else {
2990 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2991 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2992 }
e07b1aa8 2993 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2994
2995 return 0;
2996}
2997
2998static void sky2_get_pauseparam(struct net_device *dev,
2999 struct ethtool_pauseparam *ecmd)
3000{
3001 struct sky2_port *sky2 = netdev_priv(dev);
3002
16ad91e1
SH		 3003 switch (sky2->flow_mode) {
3004 case FC_NONE:
3005 ecmd->tx_pause = ecmd->rx_pause = 0;
3006 break;
3007 case FC_TX:
3008 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3009 break;
3010 case FC_RX:
3011 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3012 break;
3013 case FC_BOTH:
3014 ecmd->tx_pause = ecmd->rx_pause = 1;
3015 }
3016
cd28ab6a
SH		 3017 ecmd->autoneg = sky2->autoneg;
3018}
3019
3020static int sky2_set_pauseparam(struct net_device *dev,
3021 struct ethtool_pauseparam *ecmd)
3022{
3023 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3024
3025 sky2->autoneg = ecmd->autoneg;
16ad91e1 3026 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3027
16ad91e1
SH		 3028 if (netif_running(dev))
3029 sky2_phy_reinit(sky2);
cd28ab6a 3030
2eaba1a2 3031 return 0;
cd28ab6a
SH		 3032}
3033
fb17358f
SH		 3034static int sky2_get_coalesce(struct net_device *dev,
3035 struct ethtool_coalesce *ecmd)
3036{
3037 struct sky2_port *sky2 = netdev_priv(dev);
3038 struct sky2_hw *hw = sky2->hw;
3039
3040 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3041 ecmd->tx_coalesce_usecs = 0;
3042 else {
3043 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3044 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3045 }
3046 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3047
3048 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3049 ecmd->rx_coalesce_usecs = 0;
3050 else {
3051 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3052 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3053 }
3054 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3055
3056 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3057 ecmd->rx_coalesce_usecs_irq = 0;
3058 else {
3059 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3060 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3061 }
3062
3063 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3064
3065 return 0;
3066}
3067
3068/* Note: this affect both ports */
3069static int sky2_set_coalesce(struct net_device *dev,
3070 struct ethtool_coalesce *ecmd)
3071{
3072 struct sky2_port *sky2 = netdev_priv(dev);
3073 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3074 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3075
77b3d6a2
SH		 3076 if (ecmd->tx_coalesce_usecs > tmax ||
3077 ecmd->rx_coalesce_usecs > tmax ||
3078 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3079 return -EINVAL;
3080
ff81fbbe 3081 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3082 return -EINVAL;
ff81fbbe 3083 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3084 return -EINVAL;
ff81fbbe 3085 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3086 return -EINVAL;
3087
3088 if (ecmd->tx_coalesce_usecs == 0)
3089 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3090 else {
3091 sky2_write32(hw, STAT_TX_TIMER_INI,
3092 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3093 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3094 }
3095 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3096
3097 if (ecmd->rx_coalesce_usecs == 0)
3098 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3099 else {
3100 sky2_write32(hw, STAT_LEV_TIMER_INI,
3101 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3102 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3103 }
3104 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3105
3106 if (ecmd->rx_coalesce_usecs_irq == 0)
3107 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3108 else {
d28d4870 3109 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3110 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3111 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3112 }
3113 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3114 return 0;
3115}
3116
793b883e
SH		 3117static void sky2_get_ringparam(struct net_device *dev,
3118 struct ethtool_ringparam *ering)
3119{
3120 struct sky2_port *sky2 = netdev_priv(dev);
3121
3122 ering->rx_max_pending = RX_MAX_PENDING;
3123 ering->rx_mini_max_pending = 0;
3124 ering->rx_jumbo_max_pending = 0;
3125 ering->tx_max_pending = TX_RING_SIZE - 1;
3126
3127 ering->rx_pending = sky2->rx_pending;
3128 ering->rx_mini_pending = 0;
3129 ering->rx_jumbo_pending = 0;
3130 ering->tx_pending = sky2->tx_pending;
3131}
3132
3133static int sky2_set_ringparam(struct net_device *dev,
3134 struct ethtool_ringparam *ering)
3135{
3136 struct sky2_port *sky2 = netdev_priv(dev);
3137 int err = 0;
3138
3139 if (ering->rx_pending > RX_MAX_PENDING ||
3140 ering->rx_pending < 8 ||
3141 ering->tx_pending < MAX_SKB_TX_LE ||
3142 ering->tx_pending > TX_RING_SIZE - 1)
3143 return -EINVAL;
3144
3145 if (netif_running(dev))
3146 sky2_down(dev);
3147
3148 sky2->rx_pending = ering->rx_pending;
3149 sky2->tx_pending = ering->tx_pending;
3150
1b537565 3151 if (netif_running(dev)) {
793b883e 3152 err = sky2_up(dev);
1b537565
SH		 3153 if (err)
3154 dev_close(dev);
6ed995bb
SH		 3155 else
3156 sky2_set_multicast(dev);
1b537565 3157 }
793b883e
SH		 3158
3159 return err;
3160}
3161
793b883e
SH		 3162static int sky2_get_regs_len(struct net_device *dev)
3163{
6e4cbb34 3164 return 0x4000;
793b883e
SH		 3165}
3166
3167/*
3168 * Returns copy of control register region
6e4cbb34 3169 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3170 */
3171static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3172 void *p)
3173{
3174 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3175 const void __iomem *io = sky2->hw->regs;
793b883e 3176
6e4cbb34 3177 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3178 regs->version = 1;
6e4cbb34 3179 memset(p, 0, regs->len);
793b883e 3180
6e4cbb34
SH		 3181 memcpy_fromio(p, io, B3_RAM_ADDR);
3182
3183 memcpy_fromio(p + B3_RI_WTO_R1,
3184 io + B3_RI_WTO_R1,
3185 regs->len - B3_RI_WTO_R1);
793b883e 3186}
cd28ab6a 3187
7282d491 3188static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3189 .get_settings = sky2_get_settings,
3190 .set_settings = sky2_set_settings,
3191 .get_drvinfo = sky2_get_drvinfo,
3192 .get_msglevel = sky2_get_msglevel,
3193 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3194 .nway_reset = sky2_nway_reset,
793b883e
SH		 3195 .get_regs_len = sky2_get_regs_len,
3196 .get_regs = sky2_get_regs,
3197 .get_link = ethtool_op_get_link,
3198 .get_sg = ethtool_op_get_sg,
3199 .set_sg = ethtool_op_set_sg,
3200 .get_tx_csum = ethtool_op_get_tx_csum,
3201 .set_tx_csum = ethtool_op_set_tx_csum,
3202 .get_tso = ethtool_op_get_tso,
3203 .set_tso = ethtool_op_set_tso,
3204 .get_rx_csum = sky2_get_rx_csum,
3205 .set_rx_csum = sky2_set_rx_csum,
3206 .get_strings = sky2_get_strings,
fb17358f
SH		 3207 .get_coalesce = sky2_get_coalesce,
3208 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3209 .get_ringparam = sky2_get_ringparam,
3210 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3211 .get_pauseparam = sky2_get_pauseparam,
3212 .set_pauseparam = sky2_set_pauseparam,
793b883e 3213 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3214 .get_stats_count = sky2_get_stats_count,
3215 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3216 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3217};
3218
3219/* Initialize network device */
3220static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3221 unsigned port, int highmem)
3222{
3223 struct sky2_port *sky2;
3224 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3225
3226 if (!dev) {
3227 printk(KERN_ERR "sky2 etherdev alloc failed");
3228 return NULL;
3229 }
3230
3231 SET_MODULE_OWNER(dev);
3232 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3233 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3234 dev->open = sky2_up;
3235 dev->stop = sky2_down;
ef743d33 3236 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3237 dev->hard_start_xmit = sky2_xmit_frame;
3238 dev->get_stats = sky2_get_stats;
3239 dev->set_multicast_list = sky2_set_multicast;
3240 dev->set_mac_address = sky2_set_mac_address;
3241 dev->change_mtu = sky2_change_mtu;
3242 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3243 dev->tx_timeout = sky2_tx_timeout;
3244 dev->watchdog_timeo = TX_WATCHDOG;
3245 if (port == 0)
3246 dev->poll = sky2_poll;
3247 dev->weight = NAPI_WEIGHT;
3248#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3249 /* Network console (only works on port 0)
3250 * because netpoll makes assumptions about NAPI
3251 */
3252 if (port == 0)
3253 dev->poll_controller = sky2_netpoll;
cd28ab6a 3254#endif
cd28ab6a
SH		 3255
3256 sky2 = netdev_priv(dev);
3257 sky2->netdev = dev;
3258 sky2->hw = hw;
3259 sky2->msg_enable = netif_msg_init(debug, default_msg);
3260
cd28ab6a
SH		 3261 /* Auto speed and flow control */
3262 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3263 sky2->flow_mode = FC_BOTH;
3264
cd28ab6a
SH		 3265 sky2->duplex = -1;
3266 sky2->speed = -1;
3267 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3268 sky2->rx_csum = 1;
75d070c5 3269
e07b1aa8 3270 spin_lock_init(&sky2->phy_lock);
793b883e 3271 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3272 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3273
3274 hw->dev[port] = dev;
3275
3276 sky2->port = port;
3277
5a5b1ea0
SH		 3278 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3279 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3280 if (highmem)
3281 dev->features |= NETIF_F_HIGHDMA;
793b883e 3282 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3283
d1f13708
SH		 3284#ifdef SKY2_VLAN_TAG_USED
3285 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3286 dev->vlan_rx_register = sky2_vlan_rx_register;
3287 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3288#endif
3289
cd28ab6a 3290 /* read the mac address */
793b883e 3291 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3292 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3293
3294 /* device is off until link detection */
3295 netif_carrier_off(dev);
3296 netif_stop_queue(dev);
3297
3298 return dev;
3299}
3300
28bd181a 3301static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3302{
3303 const struct sky2_port *sky2 = netdev_priv(dev);
3304
3305 if (netif_msg_probe(sky2))
3306 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3307 dev->name,
3308 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3309 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3310}
3311
fb2690a9 3312/* Handle software interrupt used during MSI test */
7d12e780 3313static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3314{
3315 struct sky2_hw *hw = dev_id;
3316 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3317
3318 if (status == 0)
3319 return IRQ_NONE;
3320
3321 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3322 hw->msi = 1;
fb2690a9
SH		 3323 wake_up(&hw->msi_wait);
3324 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3325 }
3326 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3327
3328 return IRQ_HANDLED;
3329}
3330
3331/* Test interrupt path by forcing a a software IRQ */
3332static int __devinit sky2_test_msi(struct sky2_hw *hw)
3333{
3334 struct pci_dev *pdev = hw->pdev;
3335 int err;
3336
bb507fe1
SH		 3337 init_waitqueue_head (&hw->msi_wait);
3338
fb2690a9
SH		 3339 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3340
b0a20ded 3341 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9
SH		 3342 if (err) {
3343 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3344 pci_name(pdev), pdev->irq);
3345 return err;
3346 }
3347
fb2690a9 3348 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3349 sky2_read8(hw, B0_CTST);
fb2690a9 3350
b0a20ded 3351 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3352
b0a20ded 3353 if (!hw->msi) {
fb2690a9 3354 /* MSI test failed, go back to INTx mode */
2bffc23a
SH		 3355 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3356 "switching to INTx mode.\n",
fb2690a9
SH		 3357 pci_name(pdev));
3358
3359 err = -EOPNOTSUPP;
3360 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3361 }
3362
3363 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3364 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3365
3366 free_irq(pdev->irq, hw);
3367
3368 return err;
3369}
3370
cd28ab6a
SH		 3371static int __devinit sky2_probe(struct pci_dev *pdev,
3372 const struct pci_device_id *ent)
3373{
793b883e 3374 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3375 struct sky2_hw *hw;
5afa0a9c 3376 int err, pm_cap, using_dac = 0;
cd28ab6a 3377
793b883e
SH		 3378 err = pci_enable_device(pdev);
3379 if (err) {
cd28ab6a
SH		 3380 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3381 pci_name(pdev));
3382 goto err_out;
3383 }
3384
793b883e
SH		 3385 err = pci_request_regions(pdev, DRV_NAME);
3386 if (err) {
cd28ab6a
SH		 3387 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3388 pci_name(pdev));
793b883e 3389 goto err_out;
cd28ab6a
SH		 3390 }
3391
3392 pci_set_master(pdev);
3393
5afa0a9c
SH		 3394 /* Find power-management capability. */
3395 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3396 if (pm_cap == 0) {
3397 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3398 "aborting.\n");
3399 err = -EIO;
3400 goto err_out_free_regions;
3401 }
3402
d1f3d4dd
SH		 3403 if (sizeof(dma_addr_t) > sizeof(u32) &&
3404 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3405 using_dac = 1;
3406 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3407 if (err < 0) {
3408 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3409 "for consistent allocations\n", pci_name(pdev));
3410 goto err_out_free_regions;
3411 }
cd28ab6a 3412
d1f3d4dd 3413 } else {
cd28ab6a
SH		 3414 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3415 if (err) {
3416 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3417 pci_name(pdev));
3418 goto err_out_free_regions;
3419 }
3420 }
d1f3d4dd 3421
cd28ab6a 3422 err = -ENOMEM;
6aad85d6 3423 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3424 if (!hw) {
3425 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3426 pci_name(pdev));
3427 goto err_out_free_regions;
3428 }
3429
cd28ab6a 3430 hw->pdev = pdev;
cd28ab6a
SH		 3431
3432 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3433 if (!hw->regs) {
3434 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3435 pci_name(pdev));
3436 goto err_out_free_hw;
3437 }
5afa0a9c 3438 hw->pm_cap = pm_cap;
cd28ab6a 3439
56a645cc 3440#ifdef __BIG_ENDIAN
f65b138c
SH		 3441 /* The sk98lin vendor driver uses hardware byte swapping but
3442 * this driver uses software swapping.
3443 */
56a645cc
SH		 3444 {
3445 u32 reg;
56a645cc 3446 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3447 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3448 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3449 }
3450#endif
3451
08c06d8a
SH		 3452 /* ring for status responses */
3453 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3454 &hw->st_dma);
3455 if (!hw->st_le)
3456 goto err_out_iounmap;
3457
cd28ab6a
SH		 3458 err = sky2_reset(hw);
3459 if (err)
793b883e 3460 goto err_out_iounmap;
cd28ab6a 3461
7c7459d1
GKH		 3462 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3463 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3464 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3465 hw->chip_id, hw->chip_rev);
cd28ab6a 3466
793b883e
SH		 3467 dev = sky2_init_netdev(hw, 0, using_dac);
3468 if (!dev)
cd28ab6a
SH		 3469 goto err_out_free_pci;
3470
9fa1b1f3
SH		 3471 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3472 err = sky2_test_msi(hw);
3473 if (err == -EOPNOTSUPP)
3474 pci_disable_msi(pdev);
3475 else if (err)
3476 goto err_out_free_netdev;
3477 }
3478
793b883e
SH		 3479 err = register_netdev(dev);
3480 if (err) {
cd28ab6a
SH		 3481 printk(KERN_ERR PFX "%s: cannot register net device\n",
3482 pci_name(pdev));
3483 goto err_out_free_netdev;
3484 }
3485
b0a20ded
SH		 3486 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3487 dev->name, hw);
9fa1b1f3
SH		 3488 if (err) {
3489 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3490 pci_name(pdev), pdev->irq);
3491 goto err_out_unregister;
3492 }
3493 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3494
cd28ab6a
SH		 3495 sky2_show_addr(dev);
3496
3497 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3498 if (register_netdev(dev1) == 0)
3499 sky2_show_addr(dev1);
3500 else {
3501 /* Failure to register second port need not be fatal */
793b883e
SH		 3502 printk(KERN_WARNING PFX
3503 "register of second port failed\n");
cd28ab6a
SH		 3504 hw->dev[1] = NULL;
3505 free_netdev(dev1);
3506 }
3507 }
3508
01bd7564 3509 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3510 sky2_idle_start(hw);
d27ed387 3511
793b883e
SH		 3512 pci_set_drvdata(pdev, hw);
3513
cd28ab6a
SH		 3514 return 0;
3515
793b883e 3516err_out_unregister:
b0a20ded
SH		 3517 if (hw->msi)
3518 pci_disable_msi(pdev);
793b883e 3519 unregister_netdev(dev);
cd28ab6a
SH		 3520err_out_free_netdev:
3521 free_netdev(dev);
cd28ab6a 3522err_out_free_pci:
793b883e 3523 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3524 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3525err_out_iounmap:
3526 iounmap(hw->regs);
3527err_out_free_hw:
3528 kfree(hw);
3529err_out_free_regions:
3530 pci_release_regions(pdev);
cd28ab6a 3531 pci_disable_device(pdev);
cd28ab6a
SH		 3532err_out:
3533 return err;
3534}
3535
3536static void __devexit sky2_remove(struct pci_dev *pdev)
3537{
793b883e 3538 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3539 struct net_device *dev0, *dev1;
3540
793b883e 3541 if (!hw)
cd28ab6a
SH		 3542 return;
3543
d27ed387
SH		 3544 del_timer_sync(&hw->idle_timer);
3545
3546 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3547 synchronize_irq(hw->pdev->irq);
3548
cd28ab6a 3549 dev0 = hw->dev[0];
793b883e
SH		 3550 dev1 = hw->dev[1];
3551 if (dev1)
3552 unregister_netdev(dev1);
cd28ab6a
SH		 3553 unregister_netdev(dev0);
3554
5afa0a9c 3555 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3556 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3557 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3558 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3559
3560 free_irq(pdev->irq, hw);
b0a20ded
SH		 3561 if (hw->msi)
3562 pci_disable_msi(pdev);
793b883e 3563 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3564 pci_release_regions(pdev);
3565 pci_disable_device(pdev);
793b883e 3566
cd28ab6a
SH		 3567 if (dev1)
3568 free_netdev(dev1);
3569 free_netdev(dev0);
3570 iounmap(hw->regs);
3571 kfree(hw);
5afa0a9c 3572
cd28ab6a
SH		 3573 pci_set_drvdata(pdev, NULL);
3574}
3575
3576#ifdef CONFIG_PM
3577static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3578{
793b883e 3579 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3580 int i;
2ccc99b7
SH		 3581 pci_power_t pstate = pci_choose_state(pdev, state);
3582
3583 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3584 return -EINVAL;
cd28ab6a 3585
eb35cf60 3586 del_timer_sync(&hw->idle_timer);
6a5706b9 3587 netif_poll_disable(hw->dev[0]);
eb35cf60 3588
f05267e7 3589 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3590 struct net_device *dev = hw->dev[i];
3591
6a5706b9 3592 if (netif_running(dev)) {
5afa0a9c 3593 sky2_down(dev);
cd28ab6a 3594 netif_device_detach(dev);
cd28ab6a
SH		 3595 }
3596 }
3597
8ab8fca2 3598 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3599 pci_save_state(pdev);
2ccc99b7
SH		 3600 sky2_set_power_state(hw, pstate);
3601 return 0;
cd28ab6a
SH		 3602}
3603
3604static int sky2_resume(struct pci_dev *pdev)
3605{
793b883e 3606 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3607 int i, err;
cd28ab6a 3608
cd28ab6a
SH		 3609 pci_restore_state(pdev);
3610 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3611 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3612
08c06d8a
SH		 3613 err = sky2_reset(hw);
3614 if (err)
3615 goto out;
cd28ab6a 3616
8ab8fca2
SH		 3617 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3618
f05267e7 3619 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3620 struct net_device *dev = hw->dev[i];
6a5706b9 3621 if (netif_running(dev)) {
08c06d8a 3622 netif_device_attach(dev);
88d11360 3623
08c06d8a
SH		 3624 err = sky2_up(dev);
3625 if (err) {
3626 printk(KERN_ERR PFX "%s: could not up: %d\n",
3627 dev->name, err);
3628 dev_close(dev);
eb35cf60 3629 goto out;
5afa0a9c 3630 }
cd28ab6a
SH		 3631 }
3632 }
eb35cf60 3633
6a5706b9 3634 netif_poll_enable(hw->dev[0]);
eb35cf60 3635 sky2_idle_start(hw);
08c06d8a
SH		 3636out:
3637 return err;
cd28ab6a
SH		 3638}
3639#endif
3640
3641static struct pci_driver sky2_driver = {
793b883e
SH		 3642 .name = DRV_NAME,
3643 .id_table = sky2_id_table,
3644 .probe = sky2_probe,
3645 .remove = __devexit_p(sky2_remove),
cd28ab6a 3646#ifdef CONFIG_PM
793b883e
SH		 3647 .suspend = sky2_suspend,
3648 .resume = sky2_resume,
cd28ab6a
SH		 3649#endif
3650};
3651
3652static int __init sky2_init_module(void)
3653{
50241c4c 3654 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3655}
3656
3657static void __exit sky2_cleanup_module(void)
3658{
3659 pci_unregister_driver(&sky2_driver);
3660}
3661
3662module_init(sky2_init_module);
3663module_exit(sky2_cleanup_module);
3664
3665MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3666MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3667MODULE_LICENSE("GPL");
5f4f9dc1 3668MODULE_VERSION(DRV_VERSION);
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