]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/sky2.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PCI: Check the node argument passed to cpumask_of_node
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
ac958154 53#define DRV_VERSION "1.26"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe 67/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 144 { 0 }
145};
793b883e 146
cd28ab6a
SH		 147MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149/* Avoid conditionals by using array */
150static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 152static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 153
d1b139c0
SH		 154static void sky2_set_multicast(struct net_device *dev);
155
af043aa5 156/* Access to PHY via serial interconnect */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 171 return 0;
af043aa5
SH		 172
173 udelay(10);
cd28ab6a 174 }
ef743d33 175
af043aa5 176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 177 return -ETIMEDOUT;
af043aa5
SH		 178
179io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
cd28ab6a
SH		 182}
183
ef743d33 184static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 185{
186 int i;
187
793b883e 188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
af043aa5 201 udelay(10);
cd28ab6a
SH		 202 }
203
af043aa5 204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 205 return -ETIMEDOUT;
af043aa5
SH		 206io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
ef743d33
SH		 209}
210
af043aa5 211static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 212{
213 u16 v;
af043aa5 214 __gm_phy_read(hw, port, reg, &v);
ef743d33 215 return v;
cd28ab6a
SH		 216}
217
5afa0a9c 218
ae306cca
SH		 219static void sky2_power_on(struct sky2_hw *hw)
220{
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 224
ae306cca
SH		 225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 227
ae306cca
SH		 228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 236
ea76e635 237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 238 u32 reg;
5afa0a9c 239
b32f40c4 240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 241
b32f40c4 242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 246
b32f40c4 247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 251
b32f40c4 252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 253
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg = sky2_read32(hw, B2_GP_IO);
256 reg |= GLB_GPIO_STAT_RACE_DIS;
257 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 258
259 sky2_read32(hw, B2_GP_IO);
5afa0a9c 260 }
10547ae2
SH		 261
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 264}
5afa0a9c 265
ae306cca
SH		 266static void sky2_power_aux(struct sky2_hw *hw)
267{
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
270 else
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
276
c23ddf8f
SH		 277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
279 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 283
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 286}
287
d3bcfbeb 288static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 289{
290 u16 reg;
291
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 294
cd28ab6a
SH		 295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
303}
304
16ad91e1
SH		 305/* flow control to advertise bits */
306static const u16 copper_fc_adv[] = {
307 [FC_NONE] = 0,
308 [FC_TX] = PHY_M_AN_ASP,
309 [FC_RX] = PHY_M_AN_PC,
310 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
311};
312
313/* flow control to advertise bits when using 1000BaseX */
314static const u16 fiber_fc_adv[] = {
df3fe1f3 315 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 316 [FC_TX] = PHY_M_P_ASYM_MD_X,
317 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 318 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 319};
320
321/* flow control to GMA disable bits */
322static const u16 gm_fc_disable[] = {
323 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
324 [FC_TX] = GM_GPCR_FC_RX_DIS,
325 [FC_RX] = GM_GPCR_FC_TX_DIS,
326 [FC_BOTH] = 0,
327};
328
329
cd28ab6a
SH		 330static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331{
332 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 333 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 334
0ea065e5 335 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 336 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 337 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
338
339 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 340 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 341 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
342
53419c68 343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 344 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 345 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 346 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
347 else
53419c68
SH		 348 /* set master & slave downshift counter to 1x */
349 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 350
351 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
352 }
353
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 355 if (sky2_is_copper(hw)) {
05745c4a 356 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 359
360 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
361 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
362 u16 spec;
363
364 /* Enable Class A driver for FE+ A0 */
365 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
366 spec |= PHY_M_FESC_SEL_CL_A;
367 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
368 }
cd28ab6a
SH		 369 } else {
370 /* disable energy detect */
371 ctrl &= ~PHY_M_PC_EN_DET_MSK;
372
373 /* enable automatic crossover */
374 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375
53419c68 376 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 377 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
378 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 379 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 380 ctrl &= ~PHY_M_PC_DSC_MSK;
381 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
382 }
383 }
cd28ab6a
SH		 384 } else {
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
387
388 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 389 }
cd28ab6a 390
b89165f2
SH		 391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 /* special setup for PHY 88E1112 Fiber */
ea76e635 394 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 395 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 396
b89165f2
SH		 397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl &= ~PHY_M_MAC_MD_MSK;
401 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403
404 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 407
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 412 }
b89165f2
SH		 413
414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 415 }
416
7800fddc 417 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 418 ct1000 = 0;
419 adv = PHY_AN_CSMA;
2eaba1a2 420 reg = 0;
cd28ab6a 421
0ea065e5 422 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 423 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 424 if (sky2->advertising & ADVERTISED_1000baseT_Full)
425 ct1000 |= PHY_M_1000C_AFD;
426 if (sky2->advertising & ADVERTISED_1000baseT_Half)
427 ct1000 |= PHY_M_1000C_AHD;
428 if (sky2->advertising & ADVERTISED_100baseT_Full)
429 adv |= PHY_M_AN_100_FD;
430 if (sky2->advertising & ADVERTISED_100baseT_Half)
431 adv |= PHY_M_AN_100_HD;
432 if (sky2->advertising & ADVERTISED_10baseT_Full)
433 adv |= PHY_M_AN_10_FD;
434 if (sky2->advertising & ADVERTISED_10baseT_Half)
435 adv |= PHY_M_AN_10_HD;
709c6e7b 436
b89165f2
SH		 437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 442 }
cd28ab6a
SH		 443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
0ea065e5
SH		 450 /* Disable auto update for duplex flow control and duplex */
451 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
2eaba1a2 456 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
2eaba1a2 460 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 461 break;
462 }
463
2eaba1a2
SH		 464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
0ea065e5 469 }
2eaba1a2 470
0ea065e5
SH		 471 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
472 if (sky2_is_copper(hw))
473 adv |= copper_fc_adv[sky2->flow_mode];
474 else
475 adv |= fiber_fc_adv[sky2->flow_mode];
476 } else {
477 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 478 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 479
480 /* Forward pause packets to GMAC? */
16ad91e1 481 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
483 else
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 485 }
486
2eaba1a2
SH		 487 gma_write16(hw, port, GM_GP_CTRL, reg);
488
05745c4a 489 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 490 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
491
492 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
493 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
494
495 /* Setup Phy LED's */
496 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
497 ledover = 0;
498
499 switch (hw->chip_id) {
500 case CHIP_ID_YUKON_FE:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
503
504 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
505
506 /* delete ACT LED control bits */
507 ctrl &= ~PHY_M_FELP_LED1_MSK;
508 /* change ACT LED control to blink mode */
509 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
510 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
511 break;
512
05745c4a
SH		 513 case CHIP_ID_YUKON_FE_P:
514 /* Enable Link Partner Next Page */
515 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
516 ctrl |= PHY_M_PC_ENA_LIP_NP;
517
518 /* disable Energy Detect and enable scrambler */
519 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
521
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
526
527 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
528 break;
529
cd28ab6a 530 case CHIP_ID_YUKON_XL:
793b883e 531 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 532
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
535
536 /* set LED Function Control register */
ed6d32c7
SH		 537 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 542
543 /* set Polarity Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 551
552 /* restore page register */
793b883e 553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 554 break;
93745494 555
ed6d32c7 556 case CHIP_ID_YUKON_EC_U:
93745494 557 case CHIP_ID_YUKON_EX:
ed4d4161 558 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 559 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
560
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
563
564 /* set LED Function Control register */
565 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
570
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
573 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
574 /* restore page register */
575 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
576 break;
cd28ab6a
SH		 577
578 default:
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 581
cd28ab6a 582 /* turn off the Rx LED (LED_RX) */
a84d0a3d 583 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 584 }
585
0ce8b98d 586 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 587 /* apply fixes in PHY AFE */
ed6d32c7
SH		 588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
589
977bdf06 590 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 591 gm_phy_write(hw, port, 0x18, 0xaa99);
592 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 593
0ce8b98d
SH		 594 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw, port, 0x18, 0xa204);
597 gm_phy_write(hw, port, 0x17, 0x2002);
598 }
977bdf06
SH		 599
600 /* set page register to 0 */
9467a8fc 601 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 602 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
603 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
606 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 607 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
610
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw, port, 24, 0x2800);
613 gm_phy_write(hw, port, 23, 0x2001);
614
615 /* set page register back to 0 */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 617 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
618 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 619 /* no effect on Yukon-XL */
977bdf06 620 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 621
8e95a202
JP		 622 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
623 sky2->speed == SPEED_100) {
977bdf06 624 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 625 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 626 }
cd28ab6a 627
977bdf06
SH		 628 if (ledover)
629 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
630
631 }
2eaba1a2 632
d571b694 633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 634 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
636 else
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
638}
639
b96936da
SH		 640static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
641static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
642
643static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 644{
645 u32 reg1;
d3bcfbeb 646
b32f40c4 647 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 648 reg1 &= ~phy_power[port];
d3bcfbeb 649
b96936da 650 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 651 reg1 |= coma_mode[port];
652
b32f40c4 653 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80 654 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 655
656 if (hw->chip_id == CHIP_ID_YUKON_FE)
657 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
658 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
659 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 660}
167f53d0 661
b96936da
SH		 662static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
663{
664 u32 reg1;
db99b988
SH		 665 u16 ctrl;
666
667 /* release GPHY Control reset */
668 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
669
670 /* release GMAC reset */
671 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
672
673 if (hw->flags & SKY2_HW_NEWER_PHY) {
674 /* select page 2 to access MAC control register */
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
676
677 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
678 /* allow GMII Power Down */
679 ctrl &= ~PHY_M_MAC_GMIF_PUP;
680 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
681
682 /* set page register back to 0 */
683 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
684 }
685
686 /* setup General Purpose Control Register */
687 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 688 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
689 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
690 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 691
692 if (hw->chip_id != CHIP_ID_YUKON_EC) {
693 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 694 /* select page 2 to access MAC control register */
695 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 696
e484d5f5 697 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 698 /* enable Power Down */
699 ctrl |= PHY_M_PC_POW_D_ENA;
700 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 701
702 /* set page register back to 0 */
703 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 704 }
705
706 /* set IEEE compatible Power Down Mode (dev. #4.99) */
707 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
708 }
b96936da 709
b96936da 710 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 711 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 712 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
d3bcfbeb
SH		 713}
714
1b537565
SH		 715/* Force a renegotiation */
716static void sky2_phy_reinit(struct sky2_port *sky2)
717{
e07b1aa8 718 spin_lock_bh(&sky2->phy_lock);
1b537565 719 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 720 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 721}
722
e3173832
SH		 723/* Put device in state to listen for Wake On Lan */
724static void sky2_wol_init(struct sky2_port *sky2)
725{
726 struct sky2_hw *hw = sky2->hw;
727 unsigned port = sky2->port;
728 enum flow_control save_mode;
729 u16 ctrl;
730 u32 reg1;
731
732 /* Bring hardware out of reset */
733 sky2_write16(hw, B0_CTST, CS_RST_CLR);
734 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
735
736 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
738
739 /* Force to 10/100
740 * sky2_reset will re-enable on resume
741 */
742 save_mode = sky2->flow_mode;
743 ctrl = sky2->advertising;
744
745 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
746 sky2->flow_mode = FC_NONE;
b96936da
SH		 747
748 spin_lock_bh(&sky2->phy_lock);
749 sky2_phy_power_up(hw, port);
750 sky2_phy_init(hw, port);
751 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 752
753 sky2->flow_mode = save_mode;
754 sky2->advertising = ctrl;
755
756 /* Set GMAC to no flow control and auto update for speed/duplex */
757 gma_write16(hw, port, GM_GP_CTRL,
758 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
759 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
760
761 /* Set WOL address */
762 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
763 sky2->netdev->dev_addr, ETH_ALEN);
764
765 /* Turn on appropriate WOL control bits */
766 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
767 ctrl = 0;
768 if (sky2->wol & WAKE_PHY)
769 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
770 else
771 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
772
773 if (sky2->wol & WAKE_MAGIC)
774 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
775 else
a419aef8 776 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 777
778 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
779 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
780
781 /* Turn on legacy PCI-Express PME mode */
b32f40c4 782 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 783 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 784 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 785
786 /* block receiver */
787 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
788
789}
790
69161611
SH		 791static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
792{
05745c4a
SH		 793 struct net_device *dev = hw->dev[port];
794
ed4d4161
SH		 795 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
796 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 797 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161
SH		 798 /* Yukon-Extreme B0 and further Extreme devices */
799 /* enable Store & Forward mode for TX */
05745c4a 800
ed4d4161
SH		 801 if (dev->mtu <= ETH_DATA_LEN)
802 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
803 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 804
ed4d4161
SH		 805 else
806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
807 TX_JUMBO_ENA| TX_STFW_ENA);
808 } else {
809 if (dev->mtu <= ETH_DATA_LEN)
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
811 else {
812 /* set Tx GMAC FIFO Almost Empty Threshold */
813 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
814 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 815
ed4d4161
SH		 816 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
817
818 /* Can't do offload because of lack of store/forward */
819 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
820 }
69161611
SH		 821 }
822}
823
cd28ab6a
SH		 824static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
825{
826 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
827 u16 reg;
25cccecc 828 u32 rx_reg;
cd28ab6a
SH		 829 int i;
830 const u8 *addr = hw->dev[port]->dev_addr;
831
f350339c
SH		 832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
833 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 834
835 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
836
793b883e 837 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 838 /* WA DEV_472 -- looks like crossed wires on port 2 */
839 /* clear GMAC 1 Control reset */
840 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
841 do {
842 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
843 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
844 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
845 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
846 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
847 }
848
793b883e 849 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 850
2eaba1a2
SH		 851 /* Enable Transmit FIFO Underrun */
852 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
853
e07b1aa8 854 spin_lock_bh(&sky2->phy_lock);
b96936da 855 sky2_phy_power_up(hw, port);
cd28ab6a 856 sky2_phy_init(hw, port);
e07b1aa8 857 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 858
859 /* MIB clear */
860 reg = gma_read16(hw, port, GM_PHY_ADDR);
861 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
862
43f2f104
SH		 863 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
864 gma_read16(hw, port, i);
cd28ab6a
SH		 865 gma_write16(hw, port, GM_PHY_ADDR, reg);
866
867 /* transmit control */
868 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
869
870 /* receive control reg: unicast + multicast + no FCS */
871 gma_write16(hw, port, GM_RX_CTRL,
793b883e 872 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 873
874 /* transmit flow control */
875 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
876
877 /* transmit parameter */
878 gma_write16(hw, port, GM_TX_PARAM,
879 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
880 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
881 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
882 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
883
884 /* serial mode register */
885 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 886 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 887
6b1a3aef 888 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 889 reg |= GM_SMOD_JUMBO_ENA;
890
891 gma_write16(hw, port, GM_SERIAL_MODE, reg);
892
cd28ab6a
SH		 893 /* virtual address for data */
894 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
895
793b883e
SH		 896 /* physical address: used for pause frames */
897 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
898
899 /* ignore counter overflows */
cd28ab6a
SH		 900 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
901 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
902 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
903
904 /* Configure Rx MAC FIFO */
905 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 906 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 907 if (hw->chip_id == CHIP_ID_YUKON_EX ||
908 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 909 rx_reg |= GMF_RX_OVER_ON;
69161611 910
25cccecc 911 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 912
798fdd07
SH		 913 if (hw->chip_id == CHIP_ID_YUKON_XL) {
914 /* Hardware errata - clear flush mask */
915 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
916 } else {
917 /* Flush Rx MAC FIFO on any flow control or error */
918 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
919 }
cd28ab6a 920
8df9a876 921 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 922 reg = RX_GMF_FL_THR_DEF + 1;
923 /* Another magic mystery workaround from sk98lin */
924 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
925 hw->chip_rev == CHIP_REV_YU_FE2_A0)
926 reg = 0x178;
927 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 928
929 /* Configure Tx MAC FIFO */
930 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
931 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 932
e0c28116 933 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 934 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 935 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 936 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
937 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 938 reg = 1568 / 8;
939 else
940 reg = 1024 / 8;
941 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
942 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 943
69161611 944 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 945 }
946
e970d1f8
SH		 947 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
948 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
949 /* disable dynamic watermark */
950 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
951 reg &= ~TX_DYN_WM_ENA;
952 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
953 }
cd28ab6a
SH		 954}
955
67712901
SH		 956/* Assign Ram Buffer allocation to queue */
957static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 958{
67712901
SH		 959 u32 end;
960
961 /* convert from K bytes to qwords used for hw register */
962 start *= 1024/8;
963 space *= 1024/8;
964 end = start + space - 1;
793b883e 965
cd28ab6a
SH		 966 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
967 sky2_write32(hw, RB_ADDR(q, RB_START), start);
968 sky2_write32(hw, RB_ADDR(q, RB_END), end);
969 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
970 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
971
972 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 973 u32 tp = space - space/4;
793b883e 974
1c28f6ba
SH		 975 /* On receive queue's set the thresholds
976 * give receiver priority when > 3/4 full
977 * send pause when down to 2K
978 */
979 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
980 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 981
1c28f6ba
SH		 982 tp = space - 2048/8;
983 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
984 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 985 } else {
986 /* Enable store & forward on Tx queue's because
987 * Tx FIFO is only 1K on Yukon
988 */
989 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
990 }
991
992 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 993 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 994}
995
cd28ab6a 996/* Setup Bus Memory Interface */
af4ed7e6 997static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 998{
999 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1000 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1001 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1002 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1003}
1004
cd28ab6a
SH		 1005/* Setup prefetch unit registers. This is the interface between
1006 * hardware and driver list elements
1007 */
8cc048e3 1008static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1009 dma_addr_t addr, u32 last)
cd28ab6a 1010{
cd28ab6a
SH		 1011 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1012 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1013 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1014 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1015 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1017
1018 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1019}
1020
9b289c33 1021static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1022{
9b289c33 1023 struct sky2_tx_le *le = sky2->tx_le + *slot;
6b84daca 1024 struct tx_ring_info *re = sky2->tx_ring + *slot;
793b883e 1025
ee5f68fe 1026 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
6b84daca
SH		 1027 re->flags = 0;
1028 re->skb = NULL;
291ea614 1029 le->ctrl = 0;
793b883e
SH		 1030 return le;
1031}
cd28ab6a 1032
88f5f0ca
SH		 1033static void tx_init(struct sky2_port *sky2)
1034{
1035 struct sky2_tx_le *le;
1036
1037 sky2->tx_prod = sky2->tx_cons = 0;
1038 sky2->tx_tcpsum = 0;
1039 sky2->tx_last_mss = 0;
1040
9b289c33 1041 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1042 le->addr = 0;
1043 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1044 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1045}
1046
290d4de5
SH		 1047/* Update chip's next pointer */
1048static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1049{
50432cb5 1050 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1051 wmb();
50432cb5
SH		 1052 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1053
1054 /* Synchronize I/O on since next processor may write to tail */
1055 mmiowb();
cd28ab6a
SH		 1056}
1057
793b883e 1058
cd28ab6a
SH		 1059static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1060{
1061 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1062 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1063 le->ctrl = 0;
cd28ab6a
SH		 1064 return le;
1065}
1066
14d0263f
SH		 1067/* Build description to hardware for one receive segment */
1068static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1069 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1070{
1071 struct sky2_rx_le *le;
1072
86c6887e 1073 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1074 le = sky2_next_rx(sky2);
86c6887e 1075 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1076 le->opcode = OP_ADDR64 | HW_OWNER;
1077 }
793b883e 1078
cd28ab6a 1079 le = sky2_next_rx(sky2);
d6e74b6b 1080 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1081 le->length = cpu_to_le16(len);
14d0263f 1082 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1083}
1084
14d0263f
SH		 1085/* Build description to hardware for one possibly fragmented skb */
1086static void sky2_rx_submit(struct sky2_port *sky2,
1087 const struct rx_ring_info *re)
1088{
1089 int i;
1090
1091 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1092
1093 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1094 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1095}
1096
1097
454e6cb6 1098static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1099 unsigned size)
1100{
1101 struct sk_buff *skb = re->skb;
1102 int i;
1103
1104 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1105 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1106 return -EIO;
1107
14d0263f
SH		 1108 pci_unmap_len_set(re, data_size, size);
1109
1110 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1111 re->frag_addr[i] = pci_map_page(pdev,
1112 skb_shinfo(skb)->frags[i].page,
1113 skb_shinfo(skb)->frags[i].page_offset,
1114 skb_shinfo(skb)->frags[i].size,
1115 PCI_DMA_FROMDEVICE);
454e6cb6 1116 return 0;
14d0263f
SH		 1117}
1118
1119static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1120{
1121 struct sk_buff *skb = re->skb;
1122 int i;
1123
1124 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1125 PCI_DMA_FROMDEVICE);
1126
1127 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1128 pci_unmap_page(pdev, re->frag_addr[i],
1129 skb_shinfo(skb)->frags[i].size,
1130 PCI_DMA_FROMDEVICE);
1131}
793b883e 1132
cd28ab6a
SH		 1133/* Tell chip where to start receive checksum.
1134 * Actually has two checksums, but set both same to avoid possible byte
1135 * order problems.
1136 */
793b883e 1137static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1138{
ea76e635 1139 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1140
ea76e635
SH		 1141 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1142 le->ctrl = 0;
1143 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1144
ea76e635
SH		 1145 sky2_write32(sky2->hw,
1146 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1147 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1148 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1149}
1150
6b1a3aef
SH		 1151/*
1152 * The RX Stop command will not work for Yukon-2 if the BMU does not
1153 * reach the end of packet and since we can't make sure that we have
1154 * incoming data, we must reset the BMU while it is not doing a DMA
1155 * transfer. Since it is possible that the RX path is still active,
1156 * the RX RAM buffer will be stopped first, so any possible incoming
1157 * data will not trigger a DMA. After the RAM buffer is stopped, the
1158 * BMU is polled until any DMA in progress is ended and only then it
1159 * will be reset.
1160 */
1161static void sky2_rx_stop(struct sky2_port *sky2)
1162{
1163 struct sky2_hw *hw = sky2->hw;
1164 unsigned rxq = rxqaddr[sky2->port];
1165 int i;
1166
1167 /* disable the RAM Buffer receive queue */
1168 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1169
1170 for (i = 0; i < 0xffff; i++)
1171 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1172 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1173 goto stopped;
1174
1175 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1176 sky2->netdev->name);
1177stopped:
1178 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1179
1180 /* reset the Rx prefetch unit */
1181 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1182 mmiowb();
6b1a3aef 1183}
793b883e 1184
d571b694 1185/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1186static void sky2_rx_clean(struct sky2_port *sky2)
1187{
1188 unsigned i;
1189
1190 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1191 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1192 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1193
1194 if (re->skb) {
14d0263f 1195 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1196 kfree_skb(re->skb);
1197 re->skb = NULL;
1198 }
1199 }
1200}
1201
ef743d33
SH		 1202/* Basic MII support */
1203static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1204{
1205 struct mii_ioctl_data *data = if_mii(ifr);
1206 struct sky2_port *sky2 = netdev_priv(dev);
1207 struct sky2_hw *hw = sky2->hw;
1208 int err = -EOPNOTSUPP;
1209
1210 if (!netif_running(dev))
1211 return -ENODEV; /* Phy still in reset */
1212
d89e1343 1213 switch (cmd) {
ef743d33
SH		 1214 case SIOCGMIIPHY:
1215 data->phy_id = PHY_ADDR_MARV;
1216
1217 /* fallthru */
1218 case SIOCGMIIREG: {
1219 u16 val = 0;
91c86df5 1220
e07b1aa8 1221 spin_lock_bh(&sky2->phy_lock);
ef743d33 1222 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1223 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1224
ef743d33
SH		 1225 data->val_out = val;
1226 break;
1227 }
1228
1229 case SIOCSMIIREG:
e07b1aa8 1230 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1231 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1232 data->val_in);
e07b1aa8 1233 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1234 break;
1235 }
1236 return err;
1237}
1238
d1f13708 1239#ifdef SKY2_VLAN_TAG_USED
d494eacd 1240static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1241{
d494eacd 1242 if (onoff) {
3d4e66f5
SH		 1243 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1244 RX_VLAN_STRIP_ON);
1245 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1246 TX_VLAN_TAG_ON);
1247 } else {
1248 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1249 RX_VLAN_STRIP_OFF);
1250 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1251 TX_VLAN_TAG_OFF);
1252 }
d494eacd
SH		 1253}
1254
1255static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1256{
1257 struct sky2_port *sky2 = netdev_priv(dev);
1258 struct sky2_hw *hw = sky2->hw;
1259 u16 port = sky2->port;
1260
1261 netif_tx_lock_bh(dev);
1262 napi_disable(&hw->napi);
1263
1264 sky2->vlgrp = grp;
1265 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1266
d1d08d12 1267 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1268 napi_enable(&hw->napi);
2bb8c262 1269 netif_tx_unlock_bh(dev);
d1f13708
SH		 1270}
1271#endif
1272
bd1c6869
SH		 1273/* Amount of required worst case padding in rx buffer */
1274static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1275{
1276 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1277}
1278
82788c7a 1279/*
14d0263f
SH		 1280 * Allocate an skb for receiving. If the MTU is large enough
1281 * make the skb non-linear with a fragment list of pages.
82788c7a 1282 */
14d0263f 1283static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1284{
1285 struct sk_buff *skb;
14d0263f 1286 int i;
82788c7a 1287
724b6942
SH		 1288 skb = netdev_alloc_skb(sky2->netdev,
1289 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1290 if (!skb)
1291 goto nomem;
1292
39dbd958 1293 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1294 unsigned char *start;
1295 /*
1296 * Workaround for a bug in FIFO that cause hang
1297 * if the FIFO if the receive buffer is not 64 byte aligned.
1298 * The buffer returned from netdev_alloc_skb is
1299 * aligned except if slab debugging is enabled.
1300 */
f03b8654
SH		 1301 start = PTR_ALIGN(skb->data, 8);
1302 skb_reserve(skb, start - skb->data);
bd1c6869 1303 } else
f03b8654 1304 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1305
1306 for (i = 0; i < sky2->rx_nfrags; i++) {
1307 struct page *page = alloc_page(GFP_ATOMIC);
1308
1309 if (!page)
1310 goto free_partial;
1311 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1312 }
1313
1314 return skb;
14d0263f
SH		 1315free_partial:
1316 kfree_skb(skb);
1317nomem:
1318 return NULL;
82788c7a
SH		 1319}
1320
55c9dd35
SH		 1321static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1322{
1323 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1324}
1325
cd28ab6a
SH		 1326/*
1327 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1328 * Normal case this ends up creating one list element for skb
1329 * in the receive ring. Worst case if using large MTU and each
1330 * allocation falls on a different 64 bit region, that results
1331 * in 6 list elements per ring entry.
1332 * One element is used for checksum enable/disable, and one
1333 * extra to avoid wrap.
cd28ab6a 1334 */
6b1a3aef 1335static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1336{
6b1a3aef 1337 struct sky2_hw *hw = sky2->hw;
14d0263f 1338 struct rx_ring_info *re;
6b1a3aef 1339 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1340 unsigned i, size, thresh;
cd28ab6a 1341
6b1a3aef 1342 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1343 sky2_qset(hw, rxq);
977bdf06 1344
c3905bc4
SH		 1345 /* On PCI express lowering the watermark gives better performance */
1346 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1347 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1348
1349 /* These chips have no ram buffer?
1350 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1351 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
8e95a202
JP		 1352 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1353 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1354 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1355
6b1a3aef
SH		 1356 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1357
ea76e635
SH		 1358 if (!(hw->flags & SKY2_HW_NEW_LE))
1359 rx_set_checksum(sky2);
14d0263f
SH		 1360
1361 /* Space needed for frame data + headers rounded up */
f957da2a 1362 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1363
1364 /* Stopping point for hardware truncation */
1365 thresh = (size - 8) / sizeof(u32);
1366
5f06eba4 1367 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1368 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1369
5f06eba4
SH		 1370 /* Compute residue after pages */
1371 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1372
5f06eba4
SH		 1373 /* Optimize to handle small packets and headers */
1374 if (size < copybreak)
1375 size = copybreak;
1376 if (size < ETH_HLEN)
1377 size = ETH_HLEN;
14d0263f 1378
14d0263f
SH		 1379 sky2->rx_data_size = size;
1380
1381 /* Fill Rx ring */
793b883e 1382 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1383 re = sky2->rx_ring + i;
cd28ab6a 1384
14d0263f 1385 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1386 if (!re->skb)
1387 goto nomem;
1388
454e6cb6
SH		 1389 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1390 dev_kfree_skb(re->skb);
1391 re->skb = NULL;
1392 goto nomem;
1393 }
1394
14d0263f 1395 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1396 }
1397
a1433ac4
SH		 1398 /*
1399 * The receiver hangs if it receives frames larger than the
1400 * packet buffer. As a workaround, truncate oversize frames, but
1401 * the register is limited to 9 bits, so if you do frames > 2052
1402 * you better get the MTU right!
1403 */
a1433ac4
SH		 1404 if (thresh > 0x1ff)
1405 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1406 else {
1407 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1408 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1409 }
1410
6b1a3aef 1411 /* Tell chip about available buffers */
55c9dd35 1412 sky2_rx_update(sky2, rxq);
877c8570
SH		 1413
1414 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1415 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1416 /*
1417 * Disable flushing of non ASF packets;
1418 * must be done after initializing the BMUs;
1419 * drivers without ASF support should do this too, otherwise
1420 * it may happen that they cannot run on ASF devices;
1421 * remember that the MAC FIFO isn't reset during initialization.
1422 */
1423 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1424 }
1425
1426 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1427 /* Enable RX Home Address & Routing Header checksum fix */
1428 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1429 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1430
1431 /* Enable TX Home Address & Routing Header checksum fix */
1432 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1433 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1434 }
1435
1436
1437
cd28ab6a
SH		 1438 return 0;
1439nomem:
1440 sky2_rx_clean(sky2);
1441 return -ENOMEM;
1442}
1443
90bbebb4
MM		 1444static int sky2_alloc_buffers(struct sky2_port *sky2)
1445{
1446 struct sky2_hw *hw = sky2->hw;
1447
1448 /* must be power of 2 */
1449 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1450 sky2->tx_ring_size *
1451 sizeof(struct sky2_tx_le),
1452 &sky2->tx_le_map);
1453 if (!sky2->tx_le)
1454 goto nomem;
1455
1456 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1457 GFP_KERNEL);
1458 if (!sky2->tx_ring)
1459 goto nomem;
1460
1461 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1462 &sky2->rx_le_map);
1463 if (!sky2->rx_le)
1464 goto nomem;
1465 memset(sky2->rx_le, 0, RX_LE_BYTES);
1466
1467 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1468 GFP_KERNEL);
1469 if (!sky2->rx_ring)
1470 goto nomem;
1471
1472 return 0;
1473nomem:
1474 return -ENOMEM;
1475}
1476
1477static void sky2_free_buffers(struct sky2_port *sky2)
1478{
1479 struct sky2_hw *hw = sky2->hw;
1480
1481 if (sky2->rx_le) {
1482 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1483 sky2->rx_le, sky2->rx_le_map);
1484 sky2->rx_le = NULL;
1485 }
1486 if (sky2->tx_le) {
1487 pci_free_consistent(hw->pdev,
1488 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1489 sky2->tx_le, sky2->tx_le_map);
1490 sky2->tx_le = NULL;
1491 }
1492 kfree(sky2->tx_ring);
1493 kfree(sky2->rx_ring);
1494
1495 sky2->tx_ring = NULL;
1496 sky2->rx_ring = NULL;
1497}
1498
cd28ab6a
SH		 1499/* Bring up network interface. */
1500static int sky2_up(struct net_device *dev)
1501{
1502 struct sky2_port *sky2 = netdev_priv(dev);
1503 struct sky2_hw *hw = sky2->hw;
1504 unsigned port = sky2->port;
e0c28116 1505 u32 imask, ramsize;
90bbebb4 1506 int cap, err;
843a46f4 1507 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1508
ee7abb04
SH		 1509 /*
1510 * On dual port PCI-X card, there is an problem where status
1511 * can be received out of order due to split transactions
843a46f4 1512 */
ee7abb04
SH		 1513 if (otherdev && netif_running(otherdev) &&
1514 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1515 u16 cmd;
1516
b32f40c4 1517 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1518 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1519 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1520
ee7abb04 1521 }
843a46f4 1522
55d7b4e6
SH		 1523 netif_carrier_off(dev);
1524
90bbebb4
MM		 1525 err = sky2_alloc_buffers(sky2);
1526 if (err)
cd28ab6a 1527 goto err_out;
88f5f0ca
SH		 1528
1529 tx_init(sky2);
cd28ab6a 1530
cd28ab6a
SH		 1531 sky2_mac_init(hw, port);
1532
e0c28116
SH		 1533 /* Register is number of 4K blocks on internal RAM buffer. */
1534 ramsize = sky2_read8(hw, B2_E_0) * 4;
1535 if (ramsize > 0) {
67712901 1536 u32 rxspace;
cd28ab6a 1537
e0c28116 1538 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1539 if (ramsize < 16)
1540 rxspace = ramsize / 2;
1541 else
1542 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1543
67712901
SH		 1544 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1545 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1546
1547 /* Make sure SyncQ is disabled */
1548 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1549 RB_RST_SET);
1550 }
793b883e 1551
af4ed7e6 1552 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1553
69161611
SH		 1554 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1555 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1556 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1557
977bdf06 1558 /* Set almost empty threshold */
8e95a202
JP		 1559 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1560 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1561 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1562
6b1a3aef 1563 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1564 sky2->tx_ring_size - 1);
cd28ab6a 1565
d494eacd
SH		 1566#ifdef SKY2_VLAN_TAG_USED
1567 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1568#endif
1569
6b1a3aef 1570 err = sky2_rx_start(sky2);
6de16237 1571 if (err)
cd28ab6a
SH		 1572 goto err_out;
1573
cd28ab6a 1574 /* Enable interrupts from phy/mac for port */
e07b1aa8 1575 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1576 imask |= portirq_msk[port];
e07b1aa8 1577 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1578 sky2_read32(hw, B0_IMSK);
e07b1aa8 1579
a11da890
AD		 1580 if (netif_msg_ifup(sky2))
1581 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1582
cd28ab6a
SH		 1583 return 0;
1584
1585err_out:
90bbebb4 1586 sky2_free_buffers(sky2);
cd28ab6a
SH		 1587 return err;
1588}
1589
793b883e 1590/* Modular subtraction in ring */
ee5f68fe 1591static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1592{
ee5f68fe 1593 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1594}
cd28ab6a 1595
793b883e
SH		 1596/* Number of list elements available for next tx */
1597static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1598{
ee5f68fe 1599 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1600}
1601
793b883e 1602/* Estimate of number of transmit list elements required */
28bd181a 1603static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1604{
793b883e
SH		 1605 unsigned count;
1606
07e31637
SH		 1607 count = (skb_shinfo(skb)->nr_frags + 1)
1608 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1609
89114afd 1610 if (skb_is_gso(skb))
793b883e 1611 ++count;
07e31637
SH		 1612 else if (sizeof(dma_addr_t) == sizeof(u32))
1613 ++count; /* possible vlan */
793b883e 1614
84fa7933 1615 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1616 ++count;
1617
1618 return count;
cd28ab6a
SH		 1619}
1620
6b84daca
SH		 1621static void sky2_tx_unmap(struct pci_dev *pdev,
1622 const struct tx_ring_info *re)
1623{
1624 if (re->flags & TX_MAP_SINGLE)
1625 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1626 pci_unmap_len(re, maplen),
1627 PCI_DMA_TODEVICE);
1628 else if (re->flags & TX_MAP_PAGE)
1629 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1630 pci_unmap_len(re, maplen),
1631 PCI_DMA_TODEVICE);
1632}
1633
793b883e
SH		 1634/*
1635 * Put one packet in ring for transmit.
1636 * A single packet can generate multiple list elements, and
1637 * the number of ring elements will probably be less than the number
1638 * of list elements used.
1639 */
61357325
SH		 1640static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1641 struct net_device *dev)
cd28ab6a
SH		 1642{
1643 struct sky2_port *sky2 = netdev_priv(dev);
1644 struct sky2_hw *hw = sky2->hw;
d1f13708 1645 struct sky2_tx_le *le = NULL;
6cdbbdf3 1646 struct tx_ring_info *re;
9b289c33 1647 unsigned i, len;
cd28ab6a 1648 dma_addr_t mapping;
5dce95e5
SH		 1649 u32 upper;
1650 u16 slot;
cd28ab6a
SH		 1651 u16 mss;
1652 u8 ctrl;
1653
2bb8c262
SH		 1654 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1655 return NETDEV_TX_BUSY;
cd28ab6a 1656
cd28ab6a
SH		 1657 len = skb_headlen(skb);
1658 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1659
454e6cb6
SH		 1660 if (pci_dma_mapping_error(hw->pdev, mapping))
1661 goto mapping_error;
1662
9b289c33 1663 slot = sky2->tx_prod;
454e6cb6
SH		 1664 if (unlikely(netif_msg_tx_queued(sky2)))
1665 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1666 dev->name, slot, skb->len);
454e6cb6 1667
86c6887e 1668 /* Send high bits if needed */
5dce95e5
SH		 1669 upper = upper_32_bits(mapping);
1670 if (upper != sky2->tx_last_upper) {
9b289c33 1671 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1672 le->addr = cpu_to_le32(upper);
1673 sky2->tx_last_upper = upper;
793b883e 1674 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1675 }
cd28ab6a
SH		 1676
1677 /* Check for TCP Segmentation Offload */
7967168c 1678 mss = skb_shinfo(skb)->gso_size;
793b883e 1679 if (mss != 0) {
ea76e635
SH		 1680
1681 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1682 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1683
1684 if (mss != sky2->tx_last_mss) {
9b289c33 1685 le = get_tx_le(sky2, &slot);
69161611 1686 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1687
1688 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1689 le->opcode = OP_MSS | HW_OWNER;
1690 else
1691 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1692 sky2->tx_last_mss = mss;
1693 }
cd28ab6a
SH		 1694 }
1695
cd28ab6a 1696 ctrl = 0;
d1f13708
SH		 1697#ifdef SKY2_VLAN_TAG_USED
1698 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1699 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1700 if (!le) {
9b289c33 1701 le = get_tx_le(sky2, &slot);
f65b138c 1702 le->addr = 0;
d1f13708 1703 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1704 } else
1705 le->opcode |= OP_VLAN;
1706 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1707 ctrl |= INS_VLAN;
1708 }
1709#endif
1710
1711 /* Handle TCP checksum offload */
84fa7933 1712 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1713 /* On Yukon EX (some versions) encoding change. */
ea76e635 1714 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1715 ctrl |= CALSUM; /* auto checksum */
1716 else {
1717 const unsigned offset = skb_transport_offset(skb);
1718 u32 tcpsum;
1719
1720 tcpsum = offset << 16; /* sum start */
1721 tcpsum |= offset + skb->csum_offset; /* sum write */
1722
1723 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1724 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1725 ctrl |= UDPTCP;
1726
1727 if (tcpsum != sky2->tx_tcpsum) {
1728 sky2->tx_tcpsum = tcpsum;
1729
9b289c33 1730 le = get_tx_le(sky2, &slot);
69161611
SH		 1731 le->addr = cpu_to_le32(tcpsum);
1732 le->length = 0; /* initial checksum value */
1733 le->ctrl = 1; /* one packet */
1734 le->opcode = OP_TCPLISW | HW_OWNER;
1735 }
1d179332 1736 }
cd28ab6a
SH		 1737 }
1738
6b84daca
SH		 1739 re = sky2->tx_ring + slot;
1740 re->flags = TX_MAP_SINGLE;
1741 pci_unmap_addr_set(re, mapaddr, mapping);
1742 pci_unmap_len_set(re, maplen, len);
1743
9b289c33 1744 le = get_tx_le(sky2, &slot);
d6e74b6b 1745 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1746 le->length = cpu_to_le16(len);
1747 le->ctrl = ctrl;
793b883e 1748 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1749
cd28ab6a
SH		 1750
1751 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1752 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1753
1754 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1755 frag->size, PCI_DMA_TODEVICE);
86c6887e 1756
454e6cb6
SH		 1757 if (pci_dma_mapping_error(hw->pdev, mapping))
1758 goto mapping_unwind;
1759
5dce95e5
SH		 1760 upper = upper_32_bits(mapping);
1761 if (upper != sky2->tx_last_upper) {
9b289c33 1762 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1763 le->addr = cpu_to_le32(upper);
1764 sky2->tx_last_upper = upper;
793b883e 1765 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1766 }
1767
6b84daca
SH		 1768 re = sky2->tx_ring + slot;
1769 re->flags = TX_MAP_PAGE;
1770 pci_unmap_addr_set(re, mapaddr, mapping);
1771 pci_unmap_len_set(re, maplen, frag->size);
1772
9b289c33 1773 le = get_tx_le(sky2, &slot);
d6e74b6b 1774 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1775 le->length = cpu_to_le16(frag->size);
1776 le->ctrl = ctrl;
793b883e 1777 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1778 }
6cdbbdf3 1779
6b84daca 1780 re->skb = skb;
cd28ab6a
SH		 1781 le->ctrl |= EOP;
1782
9b289c33
MM		 1783 sky2->tx_prod = slot;
1784
97bda706
SH		 1785 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1786 netif_stop_queue(dev);
b19666d9 1787
290d4de5 1788 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1789
cd28ab6a 1790 return NETDEV_TX_OK;
454e6cb6
SH		 1791
1792mapping_unwind:
ee5f68fe 1793 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1794 re = sky2->tx_ring + i;
1795
6b84daca 1796 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1797 }
1798
454e6cb6
SH		 1799mapping_error:
1800 if (net_ratelimit())
1801 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1802 dev_kfree_skb(skb);
1803 return NETDEV_TX_OK;
cd28ab6a
SH		 1804}
1805
cd28ab6a 1806/*
793b883e
SH		 1807 * Free ring elements from starting at tx_cons until "done"
1808 *
481cea4a
SH		 1809 * NB:
1810 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1811 * buffers so make sure not to free skb to early.
481cea4a
SH		 1812 * 2. This may run in parallel start_xmit because the it only
1813 * looks at the tail of the queue of FIFO (tx_cons), not
1814 * the head (tx_prod)
cd28ab6a 1815 */
d11c13e7 1816static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1817{
d11c13e7 1818 struct net_device *dev = sky2->netdev;
291ea614 1819 unsigned idx;
cd28ab6a 1820
ee5f68fe 1821 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1822
291ea614 1823 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1824 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1825 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1826 struct sk_buff *skb = re->skb;
291ea614 1827
6b84daca 1828 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1829
6b84daca 1830 if (skb) {
291ea614
SH		 1831 if (unlikely(netif_msg_tx_done(sky2)))
1832 printk(KERN_DEBUG "%s: tx done %u\n",
1833 dev->name, idx);
3cf26753 1834
7138a0f5 1835 dev->stats.tx_packets++;
bd1c6869
SH		 1836 dev->stats.tx_bytes += skb->len;
1837
724b6942 1838 dev_kfree_skb_any(skb);
2bf56fe2 1839
ee5f68fe 1840 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1841 }
793b883e 1842 }
793b883e 1843
291ea614 1844 sky2->tx_cons = idx;
50432cb5
SH		 1845 smp_mb();
1846
22e11703 1847 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1848 netif_wake_queue(dev);
cd28ab6a
SH		 1849}
1850
264bb4fa 1851static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1852{
a510996b
MM		 1853 /* Disable Force Sync bit and Enable Alloc bit */
1854 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1855 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1856
1857 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1858 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1859 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1860
1861 /* Reset the PCI FIFO of the async Tx queue */
1862 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1863 BMU_RST_SET | BMU_FIFO_RST);
1864
1865 /* Reset the Tx prefetch units */
1866 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1867 PREF_UNIT_RST_SET);
1868
1869 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1870 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1871}
1872
cd28ab6a
SH		 1873/* Network shutdown */
1874static int sky2_down(struct net_device *dev)
1875{
1876 struct sky2_port *sky2 = netdev_priv(dev);
1877 struct sky2_hw *hw = sky2->hw;
1878 unsigned port = sky2->port;
1879 u16 ctrl;
e07b1aa8 1880 u32 imask;
cd28ab6a 1881
1b537565
SH		 1882 /* Never really got started! */
1883 if (!sky2->tx_le)
1884 return 0;
1885
cd28ab6a
SH		 1886 if (netif_msg_ifdown(sky2))
1887 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1888
d104acaf
SH		 1889 /* Force flow control off */
1890 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1891
cd28ab6a
SH		 1892 /* Stop transmitter */
1893 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1894 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1895
1896 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1897 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1898
1899 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1900 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1901 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1902
1903 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1904
1905 /* Workaround shared GMAC reset */
8e95a202
JP		 1906 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1907 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1908 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1909
cd28ab6a 1910 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1911
6c83504f
SH		 1912 /* Force any delayed status interrrupt and NAPI */
1913 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1914 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1915 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1916 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1917
a947a39d
MM		 1918 sky2_rx_stop(sky2);
1919
1920 /* Disable port IRQ */
1921 imask = sky2_read32(hw, B0_IMSK);
1922 imask &= ~portirq_msk[port];
1923 sky2_write32(hw, B0_IMSK, imask);
1924 sky2_read32(hw, B0_IMSK);
1925
6c83504f
SH		 1926 synchronize_irq(hw->pdev->irq);
1927 napi_synchronize(&hw->napi);
1928
0da6d7b3 1929 spin_lock_bh(&sky2->phy_lock);
b96936da 1930 sky2_phy_power_down(hw, port);
0da6d7b3 1931 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1932
264bb4fa
MM		 1933 sky2_tx_reset(hw, port);
1934
481cea4a
SH		 1935 /* Free any pending frames stuck in HW queue */
1936 sky2_tx_complete(sky2, sky2->tx_prod);
1937
cd28ab6a
SH		 1938 sky2_rx_clean(sky2);
1939
90bbebb4 1940 sky2_free_buffers(sky2);
1b537565 1941
cd28ab6a
SH		 1942 return 0;
1943}
1944
1945static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1946{
ea76e635 1947 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1948 return SPEED_1000;
1949
05745c4a
SH		 1950 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1951 if (aux & PHY_M_PS_SPEED_100)
1952 return SPEED_100;
1953 else
1954 return SPEED_10;
1955 }
cd28ab6a
SH		 1956
1957 switch (aux & PHY_M_PS_SPEED_MSK) {
1958 case PHY_M_PS_SPEED_1000:
1959 return SPEED_1000;
1960 case PHY_M_PS_SPEED_100:
1961 return SPEED_100;
1962 default:
1963 return SPEED_10;
1964 }
1965}
1966
1967static void sky2_link_up(struct sky2_port *sky2)
1968{
1969 struct sky2_hw *hw = sky2->hw;
1970 unsigned port = sky2->port;
1971 u16 reg;
16ad91e1
SH		 1972 static const char *fc_name[] = {
1973 [FC_NONE] = "none",
1974 [FC_TX] = "tx",
1975 [FC_RX] = "rx",
1976 [FC_BOTH] = "both",
1977 };
cd28ab6a 1978
cd28ab6a 1979 /* enable Rx/Tx */
2eaba1a2 1980 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1981 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1982 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1983
1984 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1985
1986 netif_carrier_on(sky2->netdev);
cd28ab6a 1987
75e80683 1988 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1989
cd28ab6a 1990 /* Turn on link LED */
793b883e 1991 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1992 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1993
1994 if (netif_msg_link(sky2))
1995 printk(KERN_INFO PFX
d571b694 1996 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1997 sky2->netdev->name, sky2->speed,
1998 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1999 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2000}
2001
2002static void sky2_link_down(struct sky2_port *sky2)
2003{
2004 struct sky2_hw *hw = sky2->hw;
2005 unsigned port = sky2->port;
2006 u16 reg;
2007
2008 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2009
2010 reg = gma_read16(hw, port, GM_GP_CTRL);
2011 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2012 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2013
cd28ab6a 2014 netif_carrier_off(sky2->netdev);
cd28ab6a 2015
809aaaae 2016 /* Turn off link LED */
cd28ab6a
SH		 2017 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2018
2019 if (netif_msg_link(sky2))
2020 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 2021
cd28ab6a
SH		 2022 sky2_phy_init(hw, port);
2023}
2024
16ad91e1
SH		 2025static enum flow_control sky2_flow(int rx, int tx)
2026{
2027 if (rx)
2028 return tx ? FC_BOTH : FC_RX;
2029 else
2030 return tx ? FC_TX : FC_NONE;
2031}
2032
793b883e
SH		 2033static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2034{
2035 struct sky2_hw *hw = sky2->hw;
2036 unsigned port = sky2->port;
da4c1ff4 2037 u16 advert, lpa;
793b883e 2038
da4c1ff4 2039 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2040 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2041 if (lpa & PHY_M_AN_RF) {
2042 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2043 return -1;
2044 }
2045
793b883e
SH		 2046 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2047 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2048 sky2->netdev->name);
2049 return -1;
2050 }
2051
793b883e 2052 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2053 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2054
da4c1ff4
SH		 2055 /* Since the pause result bits seem to in different positions on
2056 * different chips. look at registers.
2057 */
ea76e635 2058 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2059 /* Shift for bits in fiber PHY */
2060 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2061 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2062
2063 if (advert & ADVERTISE_1000XPAUSE)
2064 advert |= ADVERTISE_PAUSE_CAP;
2065 if (advert & ADVERTISE_1000XPSE_ASYM)
2066 advert |= ADVERTISE_PAUSE_ASYM;
2067 if (lpa & LPA_1000XPAUSE)
2068 lpa |= LPA_PAUSE_CAP;
2069 if (lpa & LPA_1000XPAUSE_ASYM)
2070 lpa |= LPA_PAUSE_ASYM;
2071 }
793b883e 2072
da4c1ff4
SH		 2073 sky2->flow_status = FC_NONE;
2074 if (advert & ADVERTISE_PAUSE_CAP) {
2075 if (lpa & LPA_PAUSE_CAP)
2076 sky2->flow_status = FC_BOTH;
2077 else if (advert & ADVERTISE_PAUSE_ASYM)
2078 sky2->flow_status = FC_RX;
2079 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2080 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2081 sky2->flow_status = FC_TX;
2082 }
793b883e 2083
8e95a202
JP		 2084 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2085 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2086 sky2->flow_status = FC_NONE;
2eaba1a2 2087
da4c1ff4 2088 if (sky2->flow_status & FC_TX)
793b883e
SH		 2089 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2090 else
2091 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2092
2093 return 0;
2094}
cd28ab6a 2095
e07b1aa8
SH		 2096/* Interrupt from PHY */
2097static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2098{
e07b1aa8
SH		 2099 struct net_device *dev = hw->dev[port];
2100 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2101 u16 istatus, phystat;
2102
ebc646f6
SH		 2103 if (!netif_running(dev))
2104 return;
2105
e07b1aa8
SH		 2106 spin_lock(&sky2->phy_lock);
2107 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2108 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2109
cd28ab6a
SH		 2110 if (netif_msg_intr(sky2))
2111 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2112 sky2->netdev->name, istatus, phystat);
2113
0ea065e5 2114 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2115 if (sky2_autoneg_done(sky2, phystat) == 0)
2116 sky2_link_up(sky2);
2117 goto out;
2118 }
cd28ab6a 2119
793b883e
SH		 2120 if (istatus & PHY_M_IS_LSP_CHANGE)
2121 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2122
793b883e
SH		 2123 if (istatus & PHY_M_IS_DUP_CHANGE)
2124 sky2->duplex =
2125 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2126
793b883e
SH		 2127 if (istatus & PHY_M_IS_LST_CHANGE) {
2128 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2129 sky2_link_up(sky2);
793b883e
SH		 2130 else
2131 sky2_link_down(sky2);
cd28ab6a 2132 }
793b883e 2133out:
e07b1aa8 2134 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2135}
2136
0f5aac70
SH		 2137/* Special quick link interrupt (Yukon-2 Optima only) */
2138static void sky2_qlink_intr(struct sky2_hw *hw)
2139{
2140 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2141 u32 imask;
2142 u16 phy;
2143
2144 /* disable irq */
2145 imask = sky2_read32(hw, B0_IMSK);
2146 imask &= ~Y2_IS_PHY_QLNK;
2147 sky2_write32(hw, B0_IMSK, imask);
2148
2149 /* reset PHY Link Detect */
2150 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2151 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2152
2153 sky2_link_up(sky2);
2154}
2155
62335ab0 2156/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2157 * and tx queue is full (stopped).
2158 */
cd28ab6a
SH		 2159static void sky2_tx_timeout(struct net_device *dev)
2160{
2161 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2162 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2163
2164 if (netif_msg_timer(sky2))
2165 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2166
8f24664d 2167 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2168 dev->name, sky2->tx_cons, sky2->tx_prod,
2169 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2170 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2171
81906791
SH		 2172 /* can't restart safely under softirq */
2173 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2174}
2175
2176static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2177{
6b1a3aef
SH		 2178 struct sky2_port *sky2 = netdev_priv(dev);
2179 struct sky2_hw *hw = sky2->hw;
b628ed98 2180 unsigned port = sky2->port;
6b1a3aef
SH		 2181 int err;
2182 u16 ctl, mode;
e07b1aa8 2183 u32 imask;
cd28ab6a
SH		 2184
2185 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2186 return -EINVAL;
2187
05745c4a
SH		 2188 if (new_mtu > ETH_DATA_LEN &&
2189 (hw->chip_id == CHIP_ID_YUKON_FE ||
2190 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2191 return -EINVAL;
2192
6b1a3aef
SH		 2193 if (!netif_running(dev)) {
2194 dev->mtu = new_mtu;
2195 return 0;
2196 }
2197
e07b1aa8 2198 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2199 sky2_write32(hw, B0_IMSK, 0);
2200
018d1c66
SH		 2201 dev->trans_start = jiffies; /* prevent tx timeout */
2202 netif_stop_queue(dev);
bea3348e 2203 napi_disable(&hw->napi);
018d1c66 2204
e07b1aa8
SH		 2205 synchronize_irq(hw->pdev->irq);
2206
39dbd958 2207 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2208 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2209
2210 ctl = gma_read16(hw, port, GM_GP_CTRL);
2211 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2212 sky2_rx_stop(sky2);
2213 sky2_rx_clean(sky2);
cd28ab6a
SH		 2214
2215 dev->mtu = new_mtu;
14d0263f 2216
6b1a3aef
SH		 2217 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2218 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2219
2220 if (dev->mtu > ETH_DATA_LEN)
2221 mode |= GM_SMOD_JUMBO_ENA;
2222
b628ed98 2223 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2224
b628ed98 2225 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2226
6b1a3aef 2227 err = sky2_rx_start(sky2);
e07b1aa8 2228 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2229
d1d08d12 2230 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2231 napi_enable(&hw->napi);
2232
1b537565
SH		 2233 if (err)
2234 dev_close(dev);
2235 else {
b628ed98 2236 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2237
1b537565
SH		 2238 netif_wake_queue(dev);
2239 }
2240
cd28ab6a
SH		 2241 return err;
2242}
2243
14d0263f
SH		 2244/* For small just reuse existing skb for next receive */
2245static struct sk_buff *receive_copy(struct sky2_port *sky2,
2246 const struct rx_ring_info *re,
2247 unsigned length)
2248{
2249 struct sk_buff *skb;
2250
89d71a66 2251 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2252 if (likely(skb)) {
14d0263f
SH		 2253 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2254 length, PCI_DMA_FROMDEVICE);
d626f62b 2255 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2256 skb->ip_summed = re->skb->ip_summed;
2257 skb->csum = re->skb->csum;
2258 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2259 length, PCI_DMA_FROMDEVICE);
2260 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2261 skb_put(skb, length);
14d0263f
SH		 2262 }
2263 return skb;
2264}
2265
2266/* Adjust length of skb with fragments to match received data */
2267static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2268 unsigned int length)
2269{
2270 int i, num_frags;
2271 unsigned int size;
2272
2273 /* put header into skb */
2274 size = min(length, hdr_space);
2275 skb->tail += size;
2276 skb->len += size;
2277 length -= size;
2278
2279 num_frags = skb_shinfo(skb)->nr_frags;
2280 for (i = 0; i < num_frags; i++) {
2281 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2282
2283 if (length == 0) {
2284 /* don't need this page */
2285 __free_page(frag->page);
2286 --skb_shinfo(skb)->nr_frags;
2287 } else {
2288 size = min(length, (unsigned) PAGE_SIZE);
2289
2290 frag->size = size;
2291 skb->data_len += size;
2292 skb->truesize += size;
2293 skb->len += size;
2294 length -= size;
2295 }
2296 }
2297}
2298
2299/* Normal packet - take skb from ring element and put in a new one */
2300static struct sk_buff *receive_new(struct sky2_port *sky2,
2301 struct rx_ring_info *re,
2302 unsigned int length)
2303{
2304 struct sk_buff *skb, *nskb;
2305 unsigned hdr_space = sky2->rx_data_size;
2306
14d0263f
SH		 2307 /* Don't be tricky about reusing pages (yet) */
2308 nskb = sky2_rx_alloc(sky2);
2309 if (unlikely(!nskb))
2310 return NULL;
2311
2312 skb = re->skb;
2313 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2314
2315 prefetch(skb->data);
2316 re->skb = nskb;
454e6cb6
SH		 2317 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2318 dev_kfree_skb(nskb);
2319 re->skb = skb;
2320 return NULL;
2321 }
14d0263f
SH		 2322
2323 if (skb_shinfo(skb)->nr_frags)
2324 skb_put_frags(skb, hdr_space, length);
2325 else
489b10c1 2326 skb_put(skb, length);
14d0263f
SH		 2327 return skb;
2328}
2329
cd28ab6a
SH		 2330/*
2331 * Receive one packet.
d571b694 2332 * For larger packets, get new buffer.
cd28ab6a 2333 */
497d7c86 2334static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2335 u16 length, u32 status)
2336{
497d7c86 2337 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2338 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2339 struct sk_buff *skb = NULL;
d6532232
SH		 2340 u16 count = (status & GMR_FS_LEN) >> 16;
2341
2342#ifdef SKY2_VLAN_TAG_USED
2343 /* Account for vlan tag */
2344 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2345 count -= VLAN_HLEN;
2346#endif
cd28ab6a
SH		 2347
2348 if (unlikely(netif_msg_rx_status(sky2)))
2349 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2350 dev->name, sky2->rx_next, status, length);
cd28ab6a 2351
793b883e 2352 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2353 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2354
3b12e014
SH		 2355 /* This chip has hardware problems that generates bogus status.
2356 * So do only marginal checking and expect higher level protocols
2357 * to handle crap frames.
2358 */
2359 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2360 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2361 length != count)
2362 goto okay;
2363
42eeea01 2364 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2365 goto error;
2366
42eeea01
SH		 2367 if (!(status & GMR_FS_RX_OK))
2368 goto resubmit;
2369
d6532232
SH		 2370 /* if length reported by DMA does not match PHY, packet was truncated */
2371 if (length != count)
3b12e014 2372 goto len_error;
71749531 2373
3b12e014 2374okay:
14d0263f
SH		 2375 if (length < copybreak)
2376 skb = receive_copy(sky2, re, length);
2377 else
2378 skb = receive_new(sky2, re, length);
793b883e 2379resubmit:
14d0263f 2380 sky2_rx_submit(sky2, re);
79e57d32 2381
cd28ab6a
SH		 2382 return skb;
2383
3b12e014 2384len_error:
71749531
SH		 2385 /* Truncation of overlength packets
2386 causes PHY length to not match MAC length */
7138a0f5 2387 ++dev->stats.rx_length_errors;
d6532232 2388 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2389 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2390 dev->name, status, length);
d6532232 2391 goto resubmit;
71749531 2392
cd28ab6a 2393error:
7138a0f5 2394 ++dev->stats.rx_errors;
b6d77734 2395 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2396 dev->stats.rx_over_errors++;
b6d77734
SH		 2397 goto resubmit;
2398 }
6e15b712 2399
3be92a70 2400 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2401 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2402 dev->name, status, length);
793b883e
SH		 2403
2404 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2405 dev->stats.rx_length_errors++;
cd28ab6a 2406 if (status & GMR_FS_FRAGMENT)
7138a0f5 2407 dev->stats.rx_frame_errors++;
cd28ab6a 2408 if (status & GMR_FS_CRC_ERR)
7138a0f5 2409 dev->stats.rx_crc_errors++;
79e57d32 2410
793b883e 2411 goto resubmit;
cd28ab6a
SH		 2412}
2413
e07b1aa8
SH		 2414/* Transmit complete */
2415static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2416{
e07b1aa8 2417 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2418
49d4b8ba 2419 if (netif_running(dev))
e07b1aa8 2420 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2421}
2422
37e5a243
SH		 2423static inline void sky2_skb_rx(const struct sky2_port *sky2,
2424 u32 status, struct sk_buff *skb)
2425{
2426#ifdef SKY2_VLAN_TAG_USED
2427 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2428 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2429 if (skb->ip_summed == CHECKSUM_NONE)
2430 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2431 else
2432 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2433 vlan_tag, skb);
2434 return;
2435 }
2436#endif
2437 if (skb->ip_summed == CHECKSUM_NONE)
2438 netif_receive_skb(skb);
2439 else
2440 napi_gro_receive(&sky2->hw->napi, skb);
2441}
2442
bf15fe99
SH		 2443static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2444 unsigned packets, unsigned bytes)
2445{
2446 if (packets) {
2447 struct net_device *dev = hw->dev[port];
2448
2449 dev->stats.rx_packets += packets;
2450 dev->stats.rx_bytes += bytes;
2451 dev->last_rx = jiffies;
2452 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2453 }
2454}
2455
e07b1aa8 2456/* Process status response ring */
26691830 2457static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2458{
e07b1aa8 2459 int work_done = 0;
bf15fe99
SH		 2460 unsigned int total_bytes[2] = { 0 };
2461 unsigned int total_packets[2] = { 0 };
a8fd6266 2462
af2a58ac 2463 rmb();
26691830 2464 do {
55c9dd35 2465 struct sky2_port *sky2;
13210ce5 2466 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2467 unsigned port;
13210ce5 2468 struct net_device *dev;
cd28ab6a 2469 struct sk_buff *skb;
cd28ab6a
SH		 2470 u32 status;
2471 u16 length;
ab5adecb
SH		 2472 u8 opcode = le->opcode;
2473
2474 if (!(opcode & HW_OWNER))
2475 break;
cd28ab6a 2476
cb5d9547 2477 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2478
ab5adecb 2479 port = le->css & CSS_LINK_BIT;
69161611 2480 dev = hw->dev[port];
13210ce5 2481 sky2 = netdev_priv(dev);
f65b138c
SH		 2482 length = le16_to_cpu(le->length);
2483 status = le32_to_cpu(le->status);
cd28ab6a 2484
ab5adecb
SH		 2485 le->opcode = 0;
2486 switch (opcode & ~HW_OWNER) {
cd28ab6a 2487 case OP_RXSTAT:
bf15fe99
SH		 2488 total_packets[port]++;
2489 total_bytes[port] += length;
497d7c86 2490 skb = sky2_receive(dev, length, status);
3225b919 2491 if (unlikely(!skb)) {
7138a0f5 2492 dev->stats.rx_dropped++;
55c9dd35 2493 break;
3225b919 2494 }
13210ce5 2495
69161611 2496 /* This chip reports checksum status differently */
05745c4a 2497 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2498 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2499 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2500 (le->css & CSS_TCPUDPCSOK))
2501 skb->ip_summed = CHECKSUM_UNNECESSARY;
2502 else
2503 skb->ip_summed = CHECKSUM_NONE;
2504 }
2505
13210ce5 2506 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2507
37e5a243 2508 sky2_skb_rx(sky2, status, skb);
13210ce5 2509
22e11703 2510 /* Stop after net poll weight */
13210ce5
SH		 2511 if (++work_done >= to_do)
2512 goto exit_loop;
cd28ab6a
SH		 2513 break;
2514
d1f13708
SH		 2515#ifdef SKY2_VLAN_TAG_USED
2516 case OP_RXVLAN:
2517 sky2->rx_tag = length;
2518 break;
2519
2520 case OP_RXCHKSVLAN:
2521 sky2->rx_tag = length;
2522 /* fall through */
2523#endif
cd28ab6a 2524 case OP_RXCHKS:
0ea065e5 2525 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
87418307
SH		 2526 break;
2527
05745c4a
SH		 2528 /* If this happens then driver assuming wrong format */
2529 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2530 if (net_ratelimit())
2531 printk(KERN_NOTICE "%s: unexpected"
2532 " checksum status\n",
2533 dev->name);
69161611 2534 break;
05745c4a 2535 }
69161611 2536
87418307
SH		 2537 /* Both checksum counters are programmed to start at
2538 * the same offset, so unless there is a problem they
2539 * should match. This failure is an early indication that
2540 * hardware receive checksumming won't work.
2541 */
2542 if (likely(status >> 16 == (status & 0xffff))) {
2543 skb = sky2->rx_ring[sky2->rx_next].skb;
2544 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2545 skb->csum = le16_to_cpu(status);
87418307
SH		 2546 } else {
2547 printk(KERN_NOTICE PFX "%s: hardware receive "
2548 "checksum problem (status = %#x)\n",
2549 dev->name, status);
0ea065e5
SH		 2550 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2551
87418307 2552 sky2_write32(sky2->hw,
69161611 2553 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2554 BMU_DIS_RX_CHKSUM);
2555 }
cd28ab6a
SH		 2556 break;
2557
2558 case OP_TXINDEXLE:
13b97b74 2559 /* TX index reports status for both ports */
f55925d7 2560 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2561 if (hw->dev[1])
2562 sky2_tx_done(hw->dev[1],
2563 ((status >> 24) & 0xff)
2564 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2565 break;
2566
cd28ab6a
SH		 2567 default:
2568 if (net_ratelimit())
793b883e 2569 printk(KERN_WARNING PFX
ab5adecb 2570 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2571 }
26691830 2572 } while (hw->st_idx != idx);
cd28ab6a 2573
fe2a24df
SH		 2574 /* Fully processed status ring so clear irq */
2575 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2576
13210ce5 2577exit_loop:
bf15fe99
SH		 2578 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2579 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2580
e07b1aa8 2581 return work_done;
cd28ab6a
SH		 2582}
2583
2584static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2585{
2586 struct net_device *dev = hw->dev[port];
2587
3be92a70
SH		 2588 if (net_ratelimit())
2589 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2590 dev->name, status);
cd28ab6a
SH		 2591
2592 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2593 if (net_ratelimit())
2594 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2595 dev->name);
cd28ab6a
SH		 2596 /* Clear IRQ */
2597 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2598 }
2599
2600 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2601 if (net_ratelimit())
2602 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2603 dev->name);
cd28ab6a
SH		 2604
2605 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2606 }
2607
2608 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2609 if (net_ratelimit())
2610 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2611 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2612 }
2613
2614 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2615 if (net_ratelimit())
2616 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2617 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2618 }
2619
2620 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2621 if (net_ratelimit())
2622 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2623 dev->name);
cd28ab6a
SH		 2624 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2625 }
2626}
2627
2628static void sky2_hw_intr(struct sky2_hw *hw)
2629{
555382cb 2630 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2631 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2632 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2633
2634 status &= hwmsk;
cd28ab6a 2635
793b883e 2636 if (status & Y2_IS_TIST_OV)
cd28ab6a 2637 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2638
2639 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2640 u16 pci_err;
2641
b32f40c4 2642 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2643 if (net_ratelimit())
555382cb 2644 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2645 pci_err);
cd28ab6a 2646
b32f40c4 2647 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2648 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2649 }
2650
2651 if (status & Y2_IS_PCI_EXP) {
d571b694 2652 /* PCI-Express uncorrectable Error occurred */
555382cb 2653 u32 err;
cd28ab6a 2654
7782c8c4
SH		 2655 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2656 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2657 0xfffffffful);
3be92a70 2658 if (net_ratelimit())
555382cb 2659 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2660
7782c8c4 2661 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
cd28ab6a
SH		 2662 }
2663
2664 if (status & Y2_HWE_L1_MASK)
2665 sky2_hw_error(hw, 0, status);
2666 status >>= 8;
2667 if (status & Y2_HWE_L1_MASK)
2668 sky2_hw_error(hw, 1, status);
2669}
2670
2671static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2672{
2673 struct net_device *dev = hw->dev[port];
2674 struct sky2_port *sky2 = netdev_priv(dev);
2675 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2676
2677 if (netif_msg_intr(sky2))
2678 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2679 dev->name, status);
2680
a3caeada
SH		 2681 if (status & GM_IS_RX_CO_OV)
2682 gma_read16(hw, port, GM_RX_IRQ_SRC);
2683
2684 if (status & GM_IS_TX_CO_OV)
2685 gma_read16(hw, port, GM_TX_IRQ_SRC);
2686
cd28ab6a 2687 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2688 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2689 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2690 }
2691
2692 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2693 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2694 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2695 }
cd28ab6a
SH		 2696}
2697
40b01727 2698/* This should never happen it is a bug. */
c119731d 2699static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2700{
2701 struct net_device *dev = hw->dev[port];
c119731d 2702 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2703
c119731d
SH		 2704 dev_err(&hw->pdev->dev, PFX
2705 "%s: descriptor error q=%#x get=%u put=%u\n",
2706 dev->name, (unsigned) q, (unsigned) idx,
2707 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2708
40b01727 2709 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2710}
cd28ab6a 2711
75e80683
SH		 2712static int sky2_rx_hung(struct net_device *dev)
2713{
2714 struct sky2_port *sky2 = netdev_priv(dev);
2715 struct sky2_hw *hw = sky2->hw;
2716 unsigned port = sky2->port;
2717 unsigned rxq = rxqaddr[port];
2718 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2719 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2720 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2721 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2722
2723 /* If idle and MAC or PCI is stuck */
2724 if (sky2->check.last == dev->last_rx &&
2725 ((mac_rp == sky2->check.mac_rp &&
2726 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2727 /* Check if the PCI RX hang */
2728 (fifo_rp == sky2->check.fifo_rp &&
2729 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2730 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2731 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2732 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2733 return 1;
2734 } else {
2735 sky2->check.last = dev->last_rx;
2736 sky2->check.mac_rp = mac_rp;
2737 sky2->check.mac_lev = mac_lev;
2738 sky2->check.fifo_rp = fifo_rp;
2739 sky2->check.fifo_lev = fifo_lev;
2740 return 0;
2741 }
2742}
2743
32c2c300 2744static void sky2_watchdog(unsigned long arg)
d27ed387 2745{
01bd7564 2746 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2747
75e80683 2748 /* Check for lost IRQ once a second */
32c2c300 2749 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2750 napi_schedule(&hw->napi);
75e80683
SH		 2751 } else {
2752 int i, active = 0;
2753
2754 for (i = 0; i < hw->ports; i++) {
bea3348e 2755 struct net_device *dev = hw->dev[i];
75e80683
SH		 2756 if (!netif_running(dev))
2757 continue;
2758 ++active;
2759
2760 /* For chips with Rx FIFO, check if stuck */
39dbd958 2761 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2762 sky2_rx_hung(dev)) {
2763 pr_info(PFX "%s: receiver hang detected\n",
2764 dev->name);
2765 schedule_work(&hw->restart_work);
2766 return;
2767 }
2768 }
2769
2770 if (active == 0)
2771 return;
32c2c300 2772 }
01bd7564 2773
75e80683 2774 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2775}
2776
40b01727
SH		 2777/* Hardware/software error handling */
2778static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2779{
40b01727
SH		 2780 if (net_ratelimit())
2781 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2782
1e5f1283
SH		 2783 if (status & Y2_IS_HW_ERR)
2784 sky2_hw_intr(hw);
d257924e 2785
1e5f1283
SH		 2786 if (status & Y2_IS_IRQ_MAC1)
2787 sky2_mac_intr(hw, 0);
cd28ab6a 2788
1e5f1283
SH		 2789 if (status & Y2_IS_IRQ_MAC2)
2790 sky2_mac_intr(hw, 1);
cd28ab6a 2791
1e5f1283 2792 if (status & Y2_IS_CHK_RX1)
c119731d 2793 sky2_le_error(hw, 0, Q_R1);
d257924e 2794
1e5f1283 2795 if (status & Y2_IS_CHK_RX2)
c119731d 2796 sky2_le_error(hw, 1, Q_R2);
d257924e 2797
1e5f1283 2798 if (status & Y2_IS_CHK_TXA1)
c119731d 2799 sky2_le_error(hw, 0, Q_XA1);
d257924e 2800
1e5f1283 2801 if (status & Y2_IS_CHK_TXA2)
c119731d 2802 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2803}
2804
bea3348e 2805static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2806{
bea3348e 2807 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2808 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2809 int work_done = 0;
26691830 2810 u16 idx;
40b01727
SH		 2811
2812 if (unlikely(status & Y2_IS_ERROR))
2813 sky2_err_intr(hw, status);
2814
2815 if (status & Y2_IS_IRQ_PHY1)
2816 sky2_phy_intr(hw, 0);
2817
2818 if (status & Y2_IS_IRQ_PHY2)
2819 sky2_phy_intr(hw, 1);
cd28ab6a 2820
0f5aac70
SH		 2821 if (status & Y2_IS_PHY_QLNK)
2822 sky2_qlink_intr(hw);
2823
26691830
SH		 2824 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2825 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2826
2827 if (work_done >= work_limit)
26691830
SH		 2828 goto done;
2829 }
6f535763 2830
26691830
SH		 2831 napi_complete(napi);
2832 sky2_read32(hw, B0_Y2_SP_LISR);
2833done:
6f535763 2834
bea3348e 2835 return work_done;
e07b1aa8
SH		 2836}
2837
7d12e780 2838static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2839{
2840 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2841 u32 status;
2842
2843 /* Reading this mask interrupts as side effect */
2844 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2845 if (status == 0 || status == ~0)
2846 return IRQ_NONE;
793b883e 2847
e07b1aa8 2848 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2849
2850 napi_schedule(&hw->napi);
793b883e 2851
cd28ab6a
SH		 2852 return IRQ_HANDLED;
2853}
2854
2855#ifdef CONFIG_NET_POLL_CONTROLLER
2856static void sky2_netpoll(struct net_device *dev)
2857{
2858 struct sky2_port *sky2 = netdev_priv(dev);
2859
bea3348e 2860 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2861}
2862#endif
2863
2864/* Chip internal frequency for clock calculations */
05745c4a 2865static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2866{
793b883e 2867 switch (hw->chip_id) {
cd28ab6a 2868 case CHIP_ID_YUKON_EC:
5a5b1ea0 2869 case CHIP_ID_YUKON_EC_U:
93745494 2870 case CHIP_ID_YUKON_EX:
ed4d4161 2871 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2872 case CHIP_ID_YUKON_UL_2:
0f5aac70 2873 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2874 return 125;
2875
cd28ab6a 2876 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2877 return 100;
2878
2879 case CHIP_ID_YUKON_FE_P:
2880 return 50;
2881
2882 case CHIP_ID_YUKON_XL:
2883 return 156;
2884
2885 default:
2886 BUG();
cd28ab6a
SH		 2887 }
2888}
2889
fb17358f 2890static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2891{
fb17358f 2892 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2893}
2894
fb17358f 2895static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2896{
fb17358f 2897 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2898}
2899
fb17358f 2900
e3173832 2901static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2902{
b89165f2 2903 u8 t8;
cd28ab6a 2904
167f53d0 2905 /* Enable all clocks and check for bad PCI access */
b32f40c4 2906 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2907
cd28ab6a 2908 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2909
cd28ab6a 2910 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2911 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2912
2913 switch(hw->chip_id) {
2914 case CHIP_ID_YUKON_XL:
39dbd958 2915 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2916 break;
2917
2918 case CHIP_ID_YUKON_EC_U:
2919 hw->flags = SKY2_HW_GIGABIT
2920 | SKY2_HW_NEWER_PHY
2921 | SKY2_HW_ADV_POWER_CTL;
2922 break;
2923
2924 case CHIP_ID_YUKON_EX:
2925 hw->flags = SKY2_HW_GIGABIT
2926 | SKY2_HW_NEWER_PHY
2927 | SKY2_HW_NEW_LE
2928 | SKY2_HW_ADV_POWER_CTL;
2929
2930 /* New transmit checksum */
2931 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2932 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2933 break;
2934
2935 case CHIP_ID_YUKON_EC:
2936 /* This rev is really old, and requires untested workarounds */
2937 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2938 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2939 return -EOPNOTSUPP;
2940 }
39dbd958 2941 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2942 break;
2943
2944 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2945 break;
2946
05745c4a
SH		 2947 case CHIP_ID_YUKON_FE_P:
2948 hw->flags = SKY2_HW_NEWER_PHY
2949 | SKY2_HW_NEW_LE
2950 | SKY2_HW_AUTO_TX_SUM
2951 | SKY2_HW_ADV_POWER_CTL;
2952 break;
ed4d4161
SH		 2953
2954 case CHIP_ID_YUKON_SUPR:
2955 hw->flags = SKY2_HW_GIGABIT
2956 | SKY2_HW_NEWER_PHY
2957 | SKY2_HW_NEW_LE
2958 | SKY2_HW_AUTO_TX_SUM
2959 | SKY2_HW_ADV_POWER_CTL;
2960 break;
2961
0ce8b98d 2962 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 2963 hw->flags = SKY2_HW_GIGABIT
2964 | SKY2_HW_ADV_POWER_CTL;
2965 break;
2966
0f5aac70 2967 case CHIP_ID_YUKON_OPT:
0ce8b98d 2968 hw->flags = SKY2_HW_GIGABIT
b338682d 2969 | SKY2_HW_NEW_LE
0ce8b98d
SH		 2970 | SKY2_HW_ADV_POWER_CTL;
2971 break;
2972
ea76e635 2973 default:
b02a9258
SH		 2974 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2975 hw->chip_id);
cd28ab6a
SH		 2976 return -EOPNOTSUPP;
2977 }
2978
ea76e635
SH		 2979 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2980 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2981 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2982
e3173832
SH		 2983 hw->ports = 1;
2984 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2985 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2986 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2987 ++hw->ports;
2988 }
2989
74a61ebf
MM		 2990 if (sky2_read8(hw, B2_E_0))
2991 hw->flags |= SKY2_HW_RAM_BUFFER;
2992
e3173832
SH		 2993 return 0;
2994}
2995
2996static void sky2_reset(struct sky2_hw *hw)
2997{
555382cb 2998 struct pci_dev *pdev = hw->pdev;
e3173832 2999 u16 status;
555382cb
SH		 3000 int i, cap;
3001 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3002
cd28ab6a 3003 /* disable ASF */
4f44d8ba
SH		 3004 if (hw->chip_id == CHIP_ID_YUKON_EX) {
3005 status = sky2_read16(hw, HCU_CCSR);
3006 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3007 HCU_CCSR_UC_STATE_MSK);
3008 sky2_write16(hw, HCU_CCSR, status);
3009 } else
3010 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3011 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3012
3013 /* do a SW reset */
3014 sky2_write8(hw, B0_CTST, CS_RST_SET);
3015 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3016
ac93a394
SH		 3017 /* allow writes to PCI config */
3018 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3019
cd28ab6a 3020 /* clear PCI errors, if any */
b32f40c4 3021 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3022 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3023 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3024
3025 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3026
555382cb
SH		 3027 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3028 if (cap) {
7782c8c4
SH		 3029 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3030 0xfffffffful);
555382cb
SH		 3031
3032 /* If error bit is stuck on ignore it */
3033 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3034 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3035 else
555382cb
SH		 3036 hwe_mask |= Y2_IS_PCI_EXP;
3037 }
cd28ab6a 3038
ae306cca 3039 sky2_power_on(hw);
cd28ab6a
SH		 3040
3041 for (i = 0; i < hw->ports; i++) {
3042 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3043 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3044
ed4d4161
SH		 3045 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3046 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3047 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3048 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3049 | GMC_BYP_RETR_ON);
877c8570
SH		 3050
3051 }
3052
3053 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3054 /* enable MACSec clock gating */
3055 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3056 }
3057
0f5aac70
SH		 3058 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3059 u16 reg;
3060 u32 msk;
3061
3062 if (hw->chip_rev == 0) {
3063 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3064 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3065
3066 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3067 reg = 10;
3068 } else {
3069 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3070 reg = 3;
3071 }
3072
3073 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3074
3075 /* reset PHY Link Detect */
3076 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3077 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3078 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3079
3080
3081 /* enable PHY Quick Link */
3082 msk = sky2_read32(hw, B0_IMSK);
3083 msk |= Y2_IS_PHY_QLNK;
3084 sky2_write32(hw, B0_IMSK, msk);
3085
3086 /* check if PSMv2 was running before */
3087 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3088 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3089 int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3090 /* restore the PCIe Link Control register */
3091 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3092 }
3093
3094 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3095 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3096 }
3097
793b883e
SH		 3098 /* Clear I2C IRQ noise */
3099 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3100
3101 /* turn off hardware timer (unused) */
3102 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3103 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3104
69634ee7
SH		 3105 /* Turn off descriptor polling */
3106 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3107
3108 /* Turn off receive timestamp */
3109 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3110 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3111
3112 /* enable the Tx Arbiters */
3113 for (i = 0; i < hw->ports; i++)
3114 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3115
3116 /* Initialize ram interface */
3117 for (i = 0; i < hw->ports; i++) {
793b883e 3118 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3119
3120 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3121 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3122 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3123 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3124 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3125 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3126 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3127 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3128 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3129 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3130 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3131 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3132 }
3133
555382cb 3134 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3135
cd28ab6a 3136 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3137 sky2_gmac_reset(hw, i);
cd28ab6a 3138
cd28ab6a
SH		 3139 memset(hw->st_le, 0, STATUS_LE_BYTES);
3140 hw->st_idx = 0;
3141
3142 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3143 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3144
3145 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3146 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3147
3148 /* Set the list last index */
793b883e 3149 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3150
290d4de5
SH		 3151 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3152 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3153
290d4de5
SH		 3154 /* set Status-FIFO ISR watermark */
3155 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3156 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3157 else
3158 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3159
290d4de5 3160 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3161 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3162 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3163
793b883e 3164 /* enable status unit */
cd28ab6a
SH		 3165 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3166
3167 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3168 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3169 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3170}
3171
af18d8b8
SH		 3172/* Take device down (offline).
3173 * Equivalent to doing dev_stop() but this does not
3174 * inform upper layers of the transistion.
3175 */
3176static void sky2_detach(struct net_device *dev)
3177{
3178 if (netif_running(dev)) {
3179 netif_device_detach(dev); /* stop txq */
3180 sky2_down(dev);
3181 }
3182}
3183
3184/* Bring device back after doing sky2_detach */
3185static int sky2_reattach(struct net_device *dev)
3186{
3187 int err = 0;
3188
3189 if (netif_running(dev)) {
3190 err = sky2_up(dev);
3191 if (err) {
3192 printk(KERN_INFO PFX "%s: could not restart %d\n",
3193 dev->name, err);
3194 dev_close(dev);
3195 } else {
3196 netif_device_attach(dev);
3197 sky2_set_multicast(dev);
3198 }
3199 }
3200
3201 return err;
3202}
3203
81906791
SH		 3204static void sky2_restart(struct work_struct *work)
3205{
3206 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3207 int i;
81906791 3208
81906791 3209 rtnl_lock();
af18d8b8
SH		 3210 for (i = 0; i < hw->ports; i++)
3211 sky2_detach(hw->dev[i]);
81906791 3212
8cfcbe99
SH		 3213 napi_disable(&hw->napi);
3214 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3215 sky2_reset(hw);
3216 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3217 napi_enable(&hw->napi);
81906791 3218
af18d8b8
SH		 3219 for (i = 0; i < hw->ports; i++)
3220 sky2_reattach(hw->dev[i]);
81906791 3221
81906791
SH		 3222 rtnl_unlock();
3223}
3224
e3173832
SH		 3225static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3226{
3227 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3228}
3229
3230static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3231{
3232 const struct sky2_port *sky2 = netdev_priv(dev);
3233
3234 wol->supported = sky2_wol_supported(sky2->hw);
3235 wol->wolopts = sky2->wol;
3236}
3237
3238static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3239{
3240 struct sky2_port *sky2 = netdev_priv(dev);
3241 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3242
8e95a202
JP		 3243 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3244 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3245 return -EOPNOTSUPP;
3246
3247 sky2->wol = wol->wolopts;
3248
05745c4a
SH		 3249 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3250 hw->chip_id == CHIP_ID_YUKON_EX ||
3251 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3252 sky2_write32(hw, B0_CTST, sky2->wol
3253 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3254
9d731d77
RW		 3255 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3256
e3173832
SH		 3257 if (!netif_running(dev))
3258 sky2_wol_init(sky2);
cd28ab6a
SH		 3259 return 0;
3260}
3261
28bd181a 3262static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3263{
b89165f2
SH		 3264 if (sky2_is_copper(hw)) {
3265 u32 modes = SUPPORTED_10baseT_Half
3266 | SUPPORTED_10baseT_Full
3267 | SUPPORTED_100baseT_Half
3268 | SUPPORTED_100baseT_Full
3269 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3270
ea76e635 3271 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3272 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3273 | SUPPORTED_1000baseT_Full;
3274 return modes;
cd28ab6a 3275 } else
b89165f2
SH		 3276 return SUPPORTED_1000baseT_Half
3277 | SUPPORTED_1000baseT_Full
3278 | SUPPORTED_Autoneg
3279 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3280}
3281
793b883e 3282static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3283{
3284 struct sky2_port *sky2 = netdev_priv(dev);
3285 struct sky2_hw *hw = sky2->hw;
3286
3287 ecmd->transceiver = XCVR_INTERNAL;
3288 ecmd->supported = sky2_supported_modes(hw);
3289 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3290 if (sky2_is_copper(hw)) {
cd28ab6a 3291 ecmd->port = PORT_TP;
b89165f2
SH		 3292 ecmd->speed = sky2->speed;
3293 } else {
3294 ecmd->speed = SPEED_1000;
cd28ab6a 3295 ecmd->port = PORT_FIBRE;
b89165f2 3296 }
cd28ab6a
SH		 3297
3298 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3299 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3300 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3301 ecmd->duplex = sky2->duplex;
3302 return 0;
3303}
3304
3305static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3306{
3307 struct sky2_port *sky2 = netdev_priv(dev);
3308 const struct sky2_hw *hw = sky2->hw;
3309 u32 supported = sky2_supported_modes(hw);
3310
3311 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3312 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3313 ecmd->advertising = supported;
3314 sky2->duplex = -1;
3315 sky2->speed = -1;
3316 } else {
3317 u32 setting;
3318
793b883e 3319 switch (ecmd->speed) {
cd28ab6a
SH		 3320 case SPEED_1000:
3321 if (ecmd->duplex == DUPLEX_FULL)
3322 setting = SUPPORTED_1000baseT_Full;
3323 else if (ecmd->duplex == DUPLEX_HALF)
3324 setting = SUPPORTED_1000baseT_Half;
3325 else
3326 return -EINVAL;
3327 break;
3328 case SPEED_100:
3329 if (ecmd->duplex == DUPLEX_FULL)
3330 setting = SUPPORTED_100baseT_Full;
3331 else if (ecmd->duplex == DUPLEX_HALF)
3332 setting = SUPPORTED_100baseT_Half;
3333 else
3334 return -EINVAL;
3335 break;
3336
3337 case SPEED_10:
3338 if (ecmd->duplex == DUPLEX_FULL)
3339 setting = SUPPORTED_10baseT_Full;
3340 else if (ecmd->duplex == DUPLEX_HALF)
3341 setting = SUPPORTED_10baseT_Half;
3342 else
3343 return -EINVAL;
3344 break;
3345 default:
3346 return -EINVAL;
3347 }
3348
3349 if ((setting & supported) == 0)
3350 return -EINVAL;
3351
3352 sky2->speed = ecmd->speed;
3353 sky2->duplex = ecmd->duplex;
0ea065e5 3354 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3355 }
3356
cd28ab6a
SH		 3357 sky2->advertising = ecmd->advertising;
3358
d1b139c0 3359 if (netif_running(dev)) {
1b537565 3360 sky2_phy_reinit(sky2);
d1b139c0
SH		 3361 sky2_set_multicast(dev);
3362 }
cd28ab6a
SH		 3363
3364 return 0;
3365}
3366
3367static void sky2_get_drvinfo(struct net_device *dev,
3368 struct ethtool_drvinfo *info)
3369{
3370 struct sky2_port *sky2 = netdev_priv(dev);
3371
3372 strcpy(info->driver, DRV_NAME);
3373 strcpy(info->version, DRV_VERSION);
3374 strcpy(info->fw_version, "N/A");
3375 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3376}
3377
3378static const struct sky2_stat {
793b883e
SH		 3379 char name[ETH_GSTRING_LEN];
3380 u16 offset;
cd28ab6a
SH		 3381} sky2_stats[] = {
3382 { "tx_bytes", GM_TXO_OK_HI },
3383 { "rx_bytes", GM_RXO_OK_HI },
3384 { "tx_broadcast", GM_TXF_BC_OK },
3385 { "rx_broadcast", GM_RXF_BC_OK },
3386 { "tx_multicast", GM_TXF_MC_OK },
3387 { "rx_multicast", GM_RXF_MC_OK },
3388 { "tx_unicast", GM_TXF_UC_OK },
3389 { "rx_unicast", GM_RXF_UC_OK },
3390 { "tx_mac_pause", GM_TXF_MPAUSE },
3391 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3392 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3393 { "late_collision",GM_TXF_LAT_COL },
3394 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3395 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3396 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3397
d2604540 3398 { "rx_short", GM_RXF_SHT },
cd28ab6a 3399 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3400 { "rx_64_byte_packets", GM_RXF_64B },
3401 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3402 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3403 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3404 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3405 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3406 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3407 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3408 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3409 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3410 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3411
3412 { "tx_64_byte_packets", GM_TXF_64B },
3413 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3414 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3415 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3416 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3417 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3418 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3419 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3420};
3421
cd28ab6a
SH		 3422static u32 sky2_get_rx_csum(struct net_device *dev)
3423{
3424 struct sky2_port *sky2 = netdev_priv(dev);
3425
0ea065e5 3426 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3427}
3428
3429static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3430{
3431 struct sky2_port *sky2 = netdev_priv(dev);
3432
0ea065e5
SH		 3433 if (data)
3434 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3435 else
3436 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3437
cd28ab6a
SH		 3438 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3439 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3440
3441 return 0;
3442}
3443
3444static u32 sky2_get_msglevel(struct net_device *netdev)
3445{
3446 struct sky2_port *sky2 = netdev_priv(netdev);
3447 return sky2->msg_enable;
3448}
3449
9a7ae0a9
SH		 3450static int sky2_nway_reset(struct net_device *dev)
3451{
3452 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3453
0ea065e5 3454 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3455 return -EINVAL;
3456
1b537565 3457 sky2_phy_reinit(sky2);
d1b139c0 3458 sky2_set_multicast(dev);
9a7ae0a9
SH		 3459
3460 return 0;
3461}
3462
793b883e 3463static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3464{
3465 struct sky2_hw *hw = sky2->hw;
3466 unsigned port = sky2->port;
3467 int i;
3468
3469 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3470 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3471 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3472 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3473
793b883e 3474 for (i = 2; i < count; i++)
cd28ab6a
SH		 3475 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3476}
3477
cd28ab6a
SH		 3478static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3479{
3480 struct sky2_port *sky2 = netdev_priv(netdev);
3481 sky2->msg_enable = value;
3482}
3483
b9f2c044 3484static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3485{
b9f2c044
JG		 3486 switch (sset) {
3487 case ETH_SS_STATS:
3488 return ARRAY_SIZE(sky2_stats);
3489 default:
3490 return -EOPNOTSUPP;
3491 }
cd28ab6a
SH		 3492}
3493
3494static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3495 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3496{
3497 struct sky2_port *sky2 = netdev_priv(dev);
3498
793b883e 3499 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3500}
3501
793b883e 3502static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3503{
3504 int i;
3505
3506 switch (stringset) {
3507 case ETH_SS_STATS:
3508 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3509 memcpy(data + i * ETH_GSTRING_LEN,
3510 sky2_stats[i].name, ETH_GSTRING_LEN);
3511 break;
3512 }
3513}
3514
cd28ab6a
SH		 3515static int sky2_set_mac_address(struct net_device *dev, void *p)
3516{
3517 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3518 struct sky2_hw *hw = sky2->hw;
3519 unsigned port = sky2->port;
3520 const struct sockaddr *addr = p;
cd28ab6a
SH		 3521
3522 if (!is_valid_ether_addr(addr->sa_data))
3523 return -EADDRNOTAVAIL;
3524
cd28ab6a 3525 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3526 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3527 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3528 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3529 dev->dev_addr, ETH_ALEN);
1b537565 3530
a8ab1ec0
SH		 3531 /* virtual address for data */
3532 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3533
3534 /* physical address: used for pause frames */
3535 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3536
3537 return 0;
cd28ab6a
SH		 3538}
3539
a052b52f
SH		 3540static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3541{
3542 u32 bit;
3543
3544 bit = ether_crc(ETH_ALEN, addr) & 63;
3545 filter[bit >> 3] |= 1 << (bit & 7);
3546}
3547
cd28ab6a
SH		 3548static void sky2_set_multicast(struct net_device *dev)
3549{
3550 struct sky2_port *sky2 = netdev_priv(dev);
3551 struct sky2_hw *hw = sky2->hw;
3552 unsigned port = sky2->port;
3553 struct dev_mc_list *list = dev->mc_list;
3554 u16 reg;
3555 u8 filter[8];
a052b52f
SH		 3556 int rx_pause;
3557 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3558
a052b52f 3559 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3560 memset(filter, 0, sizeof(filter));
3561
3562 reg = gma_read16(hw, port, GM_RX_CTRL);
3563 reg |= GM_RXCR_UCF_ENA;
3564
d571b694 3565 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3566 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3567 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3568 memset(filter, 0xff, sizeof(filter));
a052b52f 3569 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3570 reg &= ~GM_RXCR_MCF_ENA;
3571 else {
3572 int i;
3573 reg |= GM_RXCR_MCF_ENA;
3574
a052b52f
SH		 3575 if (rx_pause)
3576 sky2_add_filter(filter, pause_mc_addr);
3577
3578 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3579 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3580 }
3581
cd28ab6a 3582 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3583 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3584 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3585 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3586 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3587 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3588 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3589 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3590
3591 gma_write16(hw, port, GM_RX_CTRL, reg);
3592}
3593
3594/* Can have one global because blinking is controlled by
3595 * ethtool and that is always under RTNL mutex
3596 */
a84d0a3d 3597static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3598{
a84d0a3d
SH		 3599 struct sky2_hw *hw = sky2->hw;
3600 unsigned port = sky2->port;
793b883e 3601
a84d0a3d
SH		 3602 spin_lock_bh(&sky2->phy_lock);
3603 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3604 hw->chip_id == CHIP_ID_YUKON_EX ||
3605 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3606 u16 pg;
793b883e
SH		 3607 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3609
a84d0a3d
SH		 3610 switch (mode) {
3611 case MO_LED_OFF:
3612 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3613 PHY_M_LEDC_LOS_CTRL(8) |
3614 PHY_M_LEDC_INIT_CTRL(8) |
3615 PHY_M_LEDC_STA1_CTRL(8) |
3616 PHY_M_LEDC_STA0_CTRL(8));
3617 break;
3618 case MO_LED_ON:
3619 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3620 PHY_M_LEDC_LOS_CTRL(9) |
3621 PHY_M_LEDC_INIT_CTRL(9) |
3622 PHY_M_LEDC_STA1_CTRL(9) |
3623 PHY_M_LEDC_STA0_CTRL(9));
3624 break;
3625 case MO_LED_BLINK:
3626 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3627 PHY_M_LEDC_LOS_CTRL(0xa) |
3628 PHY_M_LEDC_INIT_CTRL(0xa) |
3629 PHY_M_LEDC_STA1_CTRL(0xa) |
3630 PHY_M_LEDC_STA0_CTRL(0xa));
3631 break;
3632 case MO_LED_NORM:
3633 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3634 PHY_M_LEDC_LOS_CTRL(1) |
3635 PHY_M_LEDC_INIT_CTRL(8) |
3636 PHY_M_LEDC_STA1_CTRL(7) |
3637 PHY_M_LEDC_STA0_CTRL(7));
3638 }
793b883e 3639
a84d0a3d
SH		 3640 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3641 } else
7d2e3cb7 3642 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3643 PHY_M_LED_MO_DUP(mode) |
3644 PHY_M_LED_MO_10(mode) |
3645 PHY_M_LED_MO_100(mode) |
3646 PHY_M_LED_MO_1000(mode) |
3647 PHY_M_LED_MO_RX(mode) |
3648 PHY_M_LED_MO_TX(mode));
3649
3650 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3651}
3652
3653/* blink LED's for finding board */
3654static int sky2_phys_id(struct net_device *dev, u32 data)
3655{
3656 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3657 unsigned int i;
cd28ab6a 3658
a84d0a3d
SH		 3659 if (data == 0)
3660 data = UINT_MAX;
cd28ab6a 3661
a84d0a3d
SH		 3662 for (i = 0; i < data; i++) {
3663 sky2_led(sky2, MO_LED_ON);
3664 if (msleep_interruptible(500))
3665 break;
3666 sky2_led(sky2, MO_LED_OFF);
3667 if (msleep_interruptible(500))
3668 break;
793b883e 3669 }
a84d0a3d 3670 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3671
3672 return 0;
3673}
3674
3675static void sky2_get_pauseparam(struct net_device *dev,
3676 struct ethtool_pauseparam *ecmd)
3677{
3678 struct sky2_port *sky2 = netdev_priv(dev);
3679
16ad91e1
SH		 3680 switch (sky2->flow_mode) {
3681 case FC_NONE:
3682 ecmd->tx_pause = ecmd->rx_pause = 0;
3683 break;
3684 case FC_TX:
3685 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3686 break;
3687 case FC_RX:
3688 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3689 break;
3690 case FC_BOTH:
3691 ecmd->tx_pause = ecmd->rx_pause = 1;
3692 }
3693
0ea065e5
SH		 3694 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3695 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3696}
3697
3698static int sky2_set_pauseparam(struct net_device *dev,
3699 struct ethtool_pauseparam *ecmd)
3700{
3701 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3702
0ea065e5
SH		 3703 if (ecmd->autoneg == AUTONEG_ENABLE)
3704 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3705 else
3706 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3707
16ad91e1 3708 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3709
16ad91e1
SH		 3710 if (netif_running(dev))
3711 sky2_phy_reinit(sky2);
cd28ab6a 3712
2eaba1a2 3713 return 0;
cd28ab6a
SH		 3714}
3715
fb17358f
SH		 3716static int sky2_get_coalesce(struct net_device *dev,
3717 struct ethtool_coalesce *ecmd)
3718{
3719 struct sky2_port *sky2 = netdev_priv(dev);
3720 struct sky2_hw *hw = sky2->hw;
3721
3722 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3723 ecmd->tx_coalesce_usecs = 0;
3724 else {
3725 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3726 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3727 }
3728 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3729
3730 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3731 ecmd->rx_coalesce_usecs = 0;
3732 else {
3733 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3734 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3735 }
3736 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3737
3738 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3739 ecmd->rx_coalesce_usecs_irq = 0;
3740 else {
3741 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3742 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3743 }
3744
3745 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3746
3747 return 0;
3748}
3749
3750/* Note: this affect both ports */
3751static int sky2_set_coalesce(struct net_device *dev,
3752 struct ethtool_coalesce *ecmd)
3753{
3754 struct sky2_port *sky2 = netdev_priv(dev);
3755 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3756 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3757
77b3d6a2
SH		 3758 if (ecmd->tx_coalesce_usecs > tmax ||
3759 ecmd->rx_coalesce_usecs > tmax ||
3760 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3761 return -EINVAL;
3762
ee5f68fe 3763 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3764 return -EINVAL;
ff81fbbe 3765 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3766 return -EINVAL;
ff81fbbe 3767 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3768 return -EINVAL;
3769
3770 if (ecmd->tx_coalesce_usecs == 0)
3771 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3772 else {
3773 sky2_write32(hw, STAT_TX_TIMER_INI,
3774 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3775 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3776 }
3777 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3778
3779 if (ecmd->rx_coalesce_usecs == 0)
3780 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3781 else {
3782 sky2_write32(hw, STAT_LEV_TIMER_INI,
3783 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3784 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3785 }
3786 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3787
3788 if (ecmd->rx_coalesce_usecs_irq == 0)
3789 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3790 else {
d28d4870 3791 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3792 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3793 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3794 }
3795 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3796 return 0;
3797}
3798
793b883e
SH		 3799static void sky2_get_ringparam(struct net_device *dev,
3800 struct ethtool_ringparam *ering)
3801{
3802 struct sky2_port *sky2 = netdev_priv(dev);
3803
3804 ering->rx_max_pending = RX_MAX_PENDING;
3805 ering->rx_mini_max_pending = 0;
3806 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3807 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3808
3809 ering->rx_pending = sky2->rx_pending;
3810 ering->rx_mini_pending = 0;
3811 ering->rx_jumbo_pending = 0;
3812 ering->tx_pending = sky2->tx_pending;
3813}
3814
3815static int sky2_set_ringparam(struct net_device *dev,
3816 struct ethtool_ringparam *ering)
3817{
3818 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3819
3820 if (ering->rx_pending > RX_MAX_PENDING ||
3821 ering->rx_pending < 8 ||
ee5f68fe
SH		 3822 ering->tx_pending < TX_MIN_PENDING ||
3823 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3824 return -EINVAL;
3825
af18d8b8 3826 sky2_detach(dev);
793b883e
SH		 3827
3828 sky2->rx_pending = ering->rx_pending;
3829 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3830 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3831
af18d8b8 3832 return sky2_reattach(dev);
793b883e
SH		 3833}
3834
793b883e
SH		 3835static int sky2_get_regs_len(struct net_device *dev)
3836{
6e4cbb34 3837 return 0x4000;
793b883e
SH		 3838}
3839
3840/*
3841 * Returns copy of control register region
3ead5db7 3842 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3843 */
3844static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3845 void *p)
3846{
3847 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3848 const void __iomem *io = sky2->hw->regs;
295b54c4 3849 unsigned int b;
793b883e
SH		 3850
3851 regs->version = 1;
793b883e 3852
295b54c4
SH		 3853 for (b = 0; b < 128; b++) {
3854 /* This complicated switch statement is to make sure and
3855 * only access regions that are unreserved.
3856 * Some blocks are only valid on dual port cards.
3857 * and block 3 has some special diagnostic registers that
3858 * are poison.
3859 */
3860 switch (b) {
3861 case 3:
3862 /* skip diagnostic ram region */
3863 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3864 break;
3ead5db7 3865
295b54c4
SH		 3866 /* dual port cards only */
3867 case 5: /* Tx Arbiter 2 */
3868 case 9: /* RX2 */
3869 case 14 ... 15: /* TX2 */
3870 case 17: case 19: /* Ram Buffer 2 */
3871 case 22 ... 23: /* Tx Ram Buffer 2 */
3872 case 25: /* Rx MAC Fifo 1 */
3873 case 27: /* Tx MAC Fifo 2 */
3874 case 31: /* GPHY 2 */
3875 case 40 ... 47: /* Pattern Ram 2 */
3876 case 52: case 54: /* TCP Segmentation 2 */
3877 case 112 ... 116: /* GMAC 2 */
3878 if (sky2->hw->ports == 1)
3879 goto reserved;
3880 /* fall through */
3881 case 0: /* Control */
3882 case 2: /* Mac address */
3883 case 4: /* Tx Arbiter 1 */
3884 case 7: /* PCI express reg */
3885 case 8: /* RX1 */
3886 case 12 ... 13: /* TX1 */
3887 case 16: case 18:/* Rx Ram Buffer 1 */
3888 case 20 ... 21: /* Tx Ram Buffer 1 */
3889 case 24: /* Rx MAC Fifo 1 */
3890 case 26: /* Tx MAC Fifo 1 */
3891 case 28 ... 29: /* Descriptor and status unit */
3892 case 30: /* GPHY 1*/
3893 case 32 ... 39: /* Pattern Ram 1 */
3894 case 48: case 50: /* TCP Segmentation 1 */
3895 case 56 ... 60: /* PCI space */
3896 case 80 ... 84: /* GMAC 1 */
3897 memcpy_fromio(p, io, 128);
3898 break;
3899 default:
3900reserved:
3901 memset(p, 0, 128);
3902 }
3ead5db7 3903
295b54c4
SH		 3904 p += 128;
3905 io += 128;
3906 }
793b883e 3907}
cd28ab6a 3908
b628ed98
SH		 3909/* In order to do Jumbo packets on these chips, need to turn off the
3910 * transmit store/forward. Therefore checksum offload won't work.
3911 */
3912static int no_tx_offload(struct net_device *dev)
3913{
3914 const struct sky2_port *sky2 = netdev_priv(dev);
3915 const struct sky2_hw *hw = sky2->hw;
3916
69161611 3917 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3918}
3919
3920static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3921{
3922 if (data && no_tx_offload(dev))
3923 return -EINVAL;
3924
3925 return ethtool_op_set_tx_csum(dev, data);
3926}
3927
3928
3929static int sky2_set_tso(struct net_device *dev, u32 data)
3930{
3931 if (data && no_tx_offload(dev))
3932 return -EINVAL;
3933
3934 return ethtool_op_set_tso(dev, data);
3935}
3936
f4331a6d
SH		 3937static int sky2_get_eeprom_len(struct net_device *dev)
3938{
3939 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3940 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3941 u16 reg2;
3942
b32f40c4 3943 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3944 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3945}
3946
1413235c 3947static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3948{
1413235c 3949 unsigned long start = jiffies;
f4331a6d 3950
1413235c
SH		 3951 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3952 /* Can take up to 10.6 ms for write */
3953 if (time_after(jiffies, start + HZ/4)) {
3954 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3955 return -ETIMEDOUT;
3956 }
3957 mdelay(1);
3958 }
167f53d0 3959
1413235c
SH		 3960 return 0;
3961}
167f53d0 3962
1413235c
SH		 3963static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3964 u16 offset, size_t length)
3965{
3966 int rc = 0;
3967
3968 while (length > 0) {
3969 u32 val;
3970
3971 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3972 rc = sky2_vpd_wait(hw, cap, 0);
3973 if (rc)
3974 break;
3975
3976 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3977
3978 memcpy(data, &val, min(sizeof(val), length));
3979 offset += sizeof(u32);
3980 data += sizeof(u32);
3981 length -= sizeof(u32);
3982 }
3983
3984 return rc;
f4331a6d
SH		 3985}
3986
1413235c
SH		 3987static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3988 u16 offset, unsigned int length)
f4331a6d 3989{
1413235c
SH		 3990 unsigned int i;
3991 int rc = 0;
3992
3993 for (i = 0; i < length; i += sizeof(u32)) {
3994 u32 val = *(u32 *)(data + i);
3995
3996 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3997 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3998
3999 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4000 if (rc)
4001 break;
4002 }
4003 return rc;
f4331a6d
SH		 4004}
4005
4006static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4007 u8 *data)
4008{
4009 struct sky2_port *sky2 = netdev_priv(dev);
4010 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4011
4012 if (!cap)
4013 return -EINVAL;
4014
4015 eeprom->magic = SKY2_EEPROM_MAGIC;
4016
1413235c 4017 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4018}
4019
4020static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4021 u8 *data)
4022{
4023 struct sky2_port *sky2 = netdev_priv(dev);
4024 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4025
4026 if (!cap)
4027 return -EINVAL;
4028
4029 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4030 return -EINVAL;
4031
1413235c
SH		 4032 /* Partial writes not supported */
4033 if ((eeprom->offset & 3) || (eeprom->len & 3))
4034 return -EINVAL;
f4331a6d 4035
1413235c 4036 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4037}
4038
4039
7282d491 4040static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4041 .get_settings = sky2_get_settings,
4042 .set_settings = sky2_set_settings,
4043 .get_drvinfo = sky2_get_drvinfo,
4044 .get_wol = sky2_get_wol,
4045 .set_wol = sky2_set_wol,
4046 .get_msglevel = sky2_get_msglevel,
4047 .set_msglevel = sky2_set_msglevel,
4048 .nway_reset = sky2_nway_reset,
4049 .get_regs_len = sky2_get_regs_len,
4050 .get_regs = sky2_get_regs,
4051 .get_link = ethtool_op_get_link,
4052 .get_eeprom_len = sky2_get_eeprom_len,
4053 .get_eeprom = sky2_get_eeprom,
4054 .set_eeprom = sky2_set_eeprom,
f4331a6d 4055 .set_sg = ethtool_op_set_sg,
f4331a6d 4056 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4057 .set_tso = sky2_set_tso,
4058 .get_rx_csum = sky2_get_rx_csum,
4059 .set_rx_csum = sky2_set_rx_csum,
4060 .get_strings = sky2_get_strings,
4061 .get_coalesce = sky2_get_coalesce,
4062 .set_coalesce = sky2_set_coalesce,
4063 .get_ringparam = sky2_get_ringparam,
4064 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4065 .get_pauseparam = sky2_get_pauseparam,
4066 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4067 .phys_id = sky2_phys_id,
b9f2c044 4068 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4069 .get_ethtool_stats = sky2_get_ethtool_stats,
4070};
4071
3cf26753
SH		 4072#ifdef CONFIG_SKY2_DEBUG
4073
4074static struct dentry *sky2_debug;
4075
e4c2abe2
SH		 4076
4077/*
4078 * Read and parse the first part of Vital Product Data
4079 */
4080#define VPD_SIZE 128
4081#define VPD_MAGIC 0x82
4082
4083static const struct vpd_tag {
4084 char tag[2];
4085 char *label;
4086} vpd_tags[] = {
4087 { "PN", "Part Number" },
4088 { "EC", "Engineering Level" },
4089 { "MN", "Manufacturer" },
4090 { "SN", "Serial Number" },
4091 { "YA", "Asset Tag" },
4092 { "VL", "First Error Log Message" },
4093 { "VF", "Second Error Log Message" },
4094 { "VB", "Boot Agent ROM Configuration" },
4095 { "VE", "EFI UNDI Configuration" },
4096};
4097
4098static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4099{
4100 size_t vpd_size;
4101 loff_t offs;
4102 u8 len;
4103 unsigned char *buf;
4104 u16 reg2;
4105
4106 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4107 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4108
4109 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4110 buf = kmalloc(vpd_size, GFP_KERNEL);
4111 if (!buf) {
4112 seq_puts(seq, "no memory!\n");
4113 return;
4114 }
4115
4116 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4117 seq_puts(seq, "VPD read failed\n");
4118 goto out;
4119 }
4120
4121 if (buf[0] != VPD_MAGIC) {
4122 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4123 goto out;
4124 }
4125 len = buf[1];
4126 if (len == 0 || len > vpd_size - 4) {
4127 seq_printf(seq, "Invalid id length: %d\n", len);
4128 goto out;
4129 }
4130
4131 seq_printf(seq, "%.*s\n", len, buf + 3);
4132 offs = len + 3;
4133
4134 while (offs < vpd_size - 4) {
4135 int i;
4136
4137 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4138 break;
4139 len = buf[offs + 2];
4140 if (offs + len + 3 >= vpd_size)
4141 break;
4142
4143 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4144 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4145 seq_printf(seq, " %s: %.*s\n",
4146 vpd_tags[i].label, len, buf + offs + 3);
4147 break;
4148 }
4149 }
4150 offs += len + 3;
4151 }
4152out:
4153 kfree(buf);
4154}
4155
3cf26753
SH		 4156static int sky2_debug_show(struct seq_file *seq, void *v)
4157{
4158 struct net_device *dev = seq->private;
4159 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4160 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4161 unsigned port = sky2->port;
4162 unsigned idx, last;
4163 int sop;
4164
e4c2abe2 4165 sky2_show_vpd(seq, hw);
3cf26753 4166
e4c2abe2 4167 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4168 sky2_read32(hw, B0_ISRC),
4169 sky2_read32(hw, B0_IMSK),
4170 sky2_read32(hw, B0_Y2_SP_ICR));
4171
e4c2abe2
SH		 4172 if (!netif_running(dev)) {
4173 seq_printf(seq, "network not running\n");
4174 return 0;
4175 }
4176
bea3348e 4177 napi_disable(&hw->napi);
3cf26753
SH		 4178 last = sky2_read16(hw, STAT_PUT_IDX);
4179
4180 if (hw->st_idx == last)
4181 seq_puts(seq, "Status ring (empty)\n");
4182 else {
4183 seq_puts(seq, "Status ring\n");
4184 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4185 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4186 const struct sky2_status_le *le = hw->st_le + idx;
4187 seq_printf(seq, "[%d] %#x %d %#x\n",
4188 idx, le->opcode, le->length, le->status);
4189 }
4190 seq_puts(seq, "\n");
4191 }
4192
4193 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4194 sky2->tx_cons, sky2->tx_prod,
4195 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4196 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4197
4198 /* Dump contents of tx ring */
4199 sop = 1;
ee5f68fe
SH		 4200 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4201 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4202 const struct sky2_tx_le *le = sky2->tx_le + idx;
4203 u32 a = le32_to_cpu(le->addr);
4204
4205 if (sop)
4206 seq_printf(seq, "%u:", idx);
4207 sop = 0;
4208
4209 switch(le->opcode & ~HW_OWNER) {
4210 case OP_ADDR64:
4211 seq_printf(seq, " %#x:", a);
4212 break;
4213 case OP_LRGLEN:
4214 seq_printf(seq, " mtu=%d", a);
4215 break;
4216 case OP_VLAN:
4217 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4218 break;
4219 case OP_TCPLISW:
4220 seq_printf(seq, " csum=%#x", a);
4221 break;
4222 case OP_LARGESEND:
4223 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4224 break;
4225 case OP_PACKET:
4226 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4227 break;
4228 case OP_BUFFER:
4229 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4230 break;
4231 default:
4232 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4233 a, le16_to_cpu(le->length));
4234 }
4235
4236 if (le->ctrl & EOP) {
4237 seq_putc(seq, '\n');
4238 sop = 1;
4239 }
4240 }
4241
4242 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4243 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4244 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4245 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4246
d1d08d12 4247 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4248 napi_enable(&hw->napi);
3cf26753
SH		 4249 return 0;
4250}
4251
4252static int sky2_debug_open(struct inode *inode, struct file *file)
4253{
4254 return single_open(file, sky2_debug_show, inode->i_private);
4255}
4256
4257static const struct file_operations sky2_debug_fops = {
4258 .owner = THIS_MODULE,
4259 .open = sky2_debug_open,
4260 .read = seq_read,
4261 .llseek = seq_lseek,
4262 .release = single_release,
4263};
4264
4265/*
4266 * Use network device events to create/remove/rename
4267 * debugfs file entries
4268 */
4269static int sky2_device_event(struct notifier_block *unused,
4270 unsigned long event, void *ptr)
4271{
4272 struct net_device *dev = ptr;
5b296bc9 4273 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4274
1436b301 4275 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4276 return NOTIFY_DONE;
3cf26753 4277
5b296bc9
SH		 4278 switch(event) {
4279 case NETDEV_CHANGENAME:
4280 if (sky2->debugfs) {
4281 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4282 sky2_debug, dev->name);
4283 }
4284 break;
3cf26753 4285
5b296bc9
SH		 4286 case NETDEV_GOING_DOWN:
4287 if (sky2->debugfs) {
4288 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4289 dev->name);
4290 debugfs_remove(sky2->debugfs);
4291 sky2->debugfs = NULL;
3cf26753 4292 }
5b296bc9
SH		 4293 break;
4294
4295 case NETDEV_UP:
4296 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4297 sky2_debug, dev,
4298 &sky2_debug_fops);
4299 if (IS_ERR(sky2->debugfs))
4300 sky2->debugfs = NULL;
3cf26753
SH		 4301 }
4302
4303 return NOTIFY_DONE;
4304}
4305
4306static struct notifier_block sky2_notifier = {
4307 .notifier_call = sky2_device_event,
4308};
4309
4310
4311static __init void sky2_debug_init(void)
4312{
4313 struct dentry *ent;
4314
4315 ent = debugfs_create_dir("sky2", NULL);
4316 if (!ent || IS_ERR(ent))
4317 return;
4318
4319 sky2_debug = ent;
4320 register_netdevice_notifier(&sky2_notifier);
4321}
4322
4323static __exit void sky2_debug_cleanup(void)
4324{
4325 if (sky2_debug) {
4326 unregister_netdevice_notifier(&sky2_notifier);
4327 debugfs_remove(sky2_debug);
4328 sky2_debug = NULL;
4329 }
4330}
4331
4332#else
4333#define sky2_debug_init()
4334#define sky2_debug_cleanup()
4335#endif
4336
1436b301
SH		 4337/* Two copies of network device operations to handle special case of
4338 not allowing netpoll on second port */
4339static const struct net_device_ops sky2_netdev_ops[2] = {
4340 {
4341 .ndo_open = sky2_up,
4342 .ndo_stop = sky2_down,
00829823 4343 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4344 .ndo_do_ioctl = sky2_ioctl,
4345 .ndo_validate_addr = eth_validate_addr,
4346 .ndo_set_mac_address = sky2_set_mac_address,
4347 .ndo_set_multicast_list = sky2_set_multicast,
4348 .ndo_change_mtu = sky2_change_mtu,
4349 .ndo_tx_timeout = sky2_tx_timeout,
4350#ifdef SKY2_VLAN_TAG_USED
4351 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4352#endif
4353#ifdef CONFIG_NET_POLL_CONTROLLER
4354 .ndo_poll_controller = sky2_netpoll,
4355#endif
4356 },
4357 {
4358 .ndo_open = sky2_up,
4359 .ndo_stop = sky2_down,
00829823 4360 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4361 .ndo_do_ioctl = sky2_ioctl,
4362 .ndo_validate_addr = eth_validate_addr,
4363 .ndo_set_mac_address = sky2_set_mac_address,
4364 .ndo_set_multicast_list = sky2_set_multicast,
4365 .ndo_change_mtu = sky2_change_mtu,
4366 .ndo_tx_timeout = sky2_tx_timeout,
4367#ifdef SKY2_VLAN_TAG_USED
4368 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4369#endif
4370 },
4371};
3cf26753 4372
cd28ab6a
SH		 4373/* Initialize network device */
4374static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4375 unsigned port,
be63a21c 4376 int highmem, int wol)
cd28ab6a
SH		 4377{
4378 struct sky2_port *sky2;
4379 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4380
4381 if (!dev) {
898eb71c 4382 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4383 return NULL;
4384 }
4385
cd28ab6a 4386 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4387 dev->irq = hw->pdev->irq;
cd28ab6a 4388 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4389 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4390 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4391
4392 sky2 = netdev_priv(dev);
4393 sky2->netdev = dev;
4394 sky2->hw = hw;
4395 sky2->msg_enable = netif_msg_init(debug, default_msg);
4396
cd28ab6a 4397 /* Auto speed and flow control */
0ea065e5
SH		 4398 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4399 if (hw->chip_id != CHIP_ID_YUKON_XL)
4400 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4401
16ad91e1
SH		 4402 sky2->flow_mode = FC_BOTH;
4403
cd28ab6a
SH		 4404 sky2->duplex = -1;
4405 sky2->speed = -1;
4406 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4407 sky2->wol = wol;
75d070c5 4408
e07b1aa8 4409 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4410
793b883e 4411 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4412 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4413 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4414
4415 hw->dev[port] = dev;
4416
4417 sky2->port = port;
4418
4a50a876 4419 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4420 if (highmem)
4421 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4422
d1f13708 4423#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4424 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4425 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4426 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4427 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4428 }
d1f13708
SH		 4429#endif
4430
cd28ab6a 4431 /* read the mac address */
793b883e 4432 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4433 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4434
cd28ab6a
SH		 4435 return dev;
4436}
4437
28bd181a 4438static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4439{
4440 const struct sky2_port *sky2 = netdev_priv(dev);
4441
4442 if (netif_msg_probe(sky2))
e174961c
JB		 4443 printk(KERN_INFO PFX "%s: addr %pM\n",
4444 dev->name, dev->dev_addr);
cd28ab6a
SH		 4445}
4446
fb2690a9 4447/* Handle software interrupt used during MSI test */
7d12e780 4448static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4449{
4450 struct sky2_hw *hw = dev_id;
4451 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4452
4453 if (status == 0)
4454 return IRQ_NONE;
4455
4456 if (status & Y2_IS_IRQ_SW) {
ea76e635 4457 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4458 wake_up(&hw->msi_wait);
4459 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4460 }
4461 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4462
4463 return IRQ_HANDLED;
4464}
4465
4466/* Test interrupt path by forcing a a software IRQ */
4467static int __devinit sky2_test_msi(struct sky2_hw *hw)
4468{
4469 struct pci_dev *pdev = hw->pdev;
4470 int err;
4471
bb507fe1
SH		 4472 init_waitqueue_head (&hw->msi_wait);
4473
fb2690a9
SH		 4474 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4475
b0a20ded 4476 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4477 if (err) {
b02a9258 4478 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4479 return err;
4480 }
4481
fb2690a9 4482 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4483 sky2_read8(hw, B0_CTST);
fb2690a9 4484
ea76e635 4485 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4486
ea76e635 4487 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4488 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4489 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4490 "switching to INTx mode.\n");
fb2690a9
SH		 4491
4492 err = -EOPNOTSUPP;
4493 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4494 }
4495
4496 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4497 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4498
4499 free_irq(pdev->irq, hw);
4500
4501 return err;
4502}
4503
c7127a34
SH		 4504/* This driver supports yukon2 chipset only */
4505static const char *sky2_name(u8 chipid, char *buf, int sz)
4506{
4507 const char *name[] = {
4508 "XL", /* 0xb3 */
4509 "EC Ultra", /* 0xb4 */
4510 "Extreme", /* 0xb5 */
4511 "EC", /* 0xb6 */
4512 "FE", /* 0xb7 */
4513 "FE+", /* 0xb8 */
4514 "Supreme", /* 0xb9 */
0ce8b98d 4515 "UL 2", /* 0xba */
0f5aac70
SH		 4516 "Unknown", /* 0xbb */
4517 "Optima", /* 0xbc */
c7127a34
SH		 4518 };
4519
dae3a511 4520 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4521 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4522 else
4523 snprintf(buf, sz, "(chip %#x)", chipid);
4524 return buf;
4525}
4526
cd28ab6a
SH		 4527static int __devinit sky2_probe(struct pci_dev *pdev,
4528 const struct pci_device_id *ent)
4529{
7f60c64b 4530 struct net_device *dev;
cd28ab6a 4531 struct sky2_hw *hw;
be63a21c 4532 int err, using_dac = 0, wol_default;
3834507d 4533 u32 reg;
c7127a34 4534 char buf1[16];
cd28ab6a 4535
793b883e
SH		 4536 err = pci_enable_device(pdev);
4537 if (err) {
b02a9258 4538 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4539 goto err_out;
4540 }
4541
6cc90a5a
SH		 4542 /* Get configuration information
4543 * Note: only regular PCI config access once to test for HW issues
4544 * other PCI access through shared memory for speed and to
4545 * avoid MMCONFIG problems.
4546 */
4547 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4548 if (err) {
4549 dev_err(&pdev->dev, "PCI read config failed\n");
4550 goto err_out;
4551 }
4552
4553 if (~reg == 0) {
4554 dev_err(&pdev->dev, "PCI configuration read error\n");
4555 goto err_out;
4556 }
4557
793b883e
SH		 4558 err = pci_request_regions(pdev, DRV_NAME);
4559 if (err) {
b02a9258 4560 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4561 goto err_out_disable;
cd28ab6a
SH		 4562 }
4563
4564 pci_set_master(pdev);
4565
d1f3d4dd 4566 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4567 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4568 using_dac = 1;
6a35528a 4569 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4570 if (err < 0) {
b02a9258
SH		 4571 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4572 "for consistent allocations\n");
d1f3d4dd
SH		 4573 goto err_out_free_regions;
4574 }
d1f3d4dd 4575 } else {
284901a9 4576 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4577 if (err) {
b02a9258 4578 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4579 goto err_out_free_regions;
4580 }
4581 }
d1f3d4dd 4582
3834507d
SH		 4583
4584#ifdef __BIG_ENDIAN
4585 /* The sk98lin vendor driver uses hardware byte swapping but
4586 * this driver uses software swapping.
4587 */
4588 reg &= ~PCI_REV_DESC;
4589 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4590 if (err) {
4591 dev_err(&pdev->dev, "PCI write config failed\n");
4592 goto err_out_free_regions;
4593 }
4594#endif
4595
9d731d77 4596 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4597
cd28ab6a 4598 err = -ENOMEM;
66466797
SH		 4599
4600 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4601 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4602 if (!hw) {
b02a9258 4603 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4604 goto err_out_free_regions;
4605 }
4606
cd28ab6a 4607 hw->pdev = pdev;
66466797 4608 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4609
4610 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4611 if (!hw->regs) {
b02a9258 4612 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4613 goto err_out_free_hw;
4614 }
4615
08c06d8a 4616 /* ring for status responses */
167f53d0 4617 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4618 if (!hw->st_le)
4619 goto err_out_iounmap;
4620
e3173832 4621 err = sky2_init(hw);
cd28ab6a 4622 if (err)
793b883e 4623 goto err_out_iounmap;
cd28ab6a 4624
c844d483
SH		 4625 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4626 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4627
e3173832
SH		 4628 sky2_reset(hw);
4629
be63a21c 4630 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4631 if (!dev) {
4632 err = -ENOMEM;
cd28ab6a 4633 goto err_out_free_pci;
7f60c64b 4634 }
cd28ab6a 4635
9fa1b1f3
SH		 4636 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4637 err = sky2_test_msi(hw);
4638 if (err == -EOPNOTSUPP)
4639 pci_disable_msi(pdev);
4640 else if (err)
4641 goto err_out_free_netdev;
4642 }
4643
793b883e
SH		 4644 err = register_netdev(dev);
4645 if (err) {
b02a9258 4646 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4647 goto err_out_free_netdev;
4648 }
4649
33cb7d33
BP		 4650 netif_carrier_off(dev);
4651
6de16237
SH		 4652 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4653
ea76e635
SH		 4654 err = request_irq(pdev->irq, sky2_intr,
4655 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4656 hw->irq_name, hw);
9fa1b1f3 4657 if (err) {
b02a9258 4658 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4659 goto err_out_unregister;
4660 }
4661 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4662 napi_enable(&hw->napi);
9fa1b1f3 4663
cd28ab6a
SH		 4664 sky2_show_addr(dev);
4665
7f60c64b 4666 if (hw->ports > 1) {
4667 struct net_device *dev1;
4668
ca519274 4669 err = -ENOMEM;
be63a21c 4670 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4671 if (dev1 && (err = register_netdev(dev1)) == 0)
4672 sky2_show_addr(dev1);
4673 else {
b02a9258
SH		 4674 dev_warn(&pdev->dev,
4675 "register of second port failed (%d)\n", err);
cd28ab6a 4676 hw->dev[1] = NULL;
ca519274
SH		 4677 hw->ports = 1;
4678 if (dev1)
4679 free_netdev(dev1);
4680 }
cd28ab6a
SH		 4681 }
4682
32c2c300 4683 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4684 INIT_WORK(&hw->restart_work, sky2_restart);
4685
793b883e
SH		 4686 pci_set_drvdata(pdev, hw);
4687
cd28ab6a
SH		 4688 return 0;
4689
793b883e 4690err_out_unregister:
ea76e635 4691 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4692 pci_disable_msi(pdev);
793b883e 4693 unregister_netdev(dev);
cd28ab6a
SH		 4694err_out_free_netdev:
4695 free_netdev(dev);
cd28ab6a 4696err_out_free_pci:
793b883e 4697 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4698 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4699err_out_iounmap:
4700 iounmap(hw->regs);
4701err_out_free_hw:
4702 kfree(hw);
4703err_out_free_regions:
4704 pci_release_regions(pdev);
44a1d2e5 4705err_out_disable:
cd28ab6a 4706 pci_disable_device(pdev);
cd28ab6a 4707err_out:
549a68c3 4708 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4709 return err;
4710}
4711
4712static void __devexit sky2_remove(struct pci_dev *pdev)
4713{
793b883e 4714 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4715 int i;
cd28ab6a 4716
793b883e 4717 if (!hw)
cd28ab6a
SH		 4718 return;
4719
32c2c300 4720 del_timer_sync(&hw->watchdog_timer);
6de16237 4721 cancel_work_sync(&hw->restart_work);
d27ed387 4722
b877fe28 4723 for (i = hw->ports-1; i >= 0; --i)
6de16237 4724 unregister_netdev(hw->dev[i]);
81906791 4725
d27ed387 4726 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4727
ae306cca
SH		 4728 sky2_power_aux(hw);
4729
793b883e 4730 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4731 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4732
4733 free_irq(pdev->irq, hw);
ea76e635 4734 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4735 pci_disable_msi(pdev);
793b883e 4736 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4737 pci_release_regions(pdev);
4738 pci_disable_device(pdev);
793b883e 4739
b877fe28 4740 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4741 free_netdev(hw->dev[i]);
4742
cd28ab6a
SH		 4743 iounmap(hw->regs);
4744 kfree(hw);
5afa0a9c 4745
cd28ab6a
SH		 4746 pci_set_drvdata(pdev, NULL);
4747}
4748
4749#ifdef CONFIG_PM
4750static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4751{
793b883e 4752 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4753 int i, wol = 0;
cd28ab6a 4754
549a68c3
SH		 4755 if (!hw)
4756 return 0;
4757
063a0b38
SH		 4758 del_timer_sync(&hw->watchdog_timer);
4759 cancel_work_sync(&hw->restart_work);
4760
19720737 4761 rtnl_lock();
f05267e7 4762 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4763 struct net_device *dev = hw->dev[i];
e3173832 4764 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4765
af18d8b8 4766 sky2_detach(dev);
e3173832
SH		 4767
4768 if (sky2->wol)
4769 sky2_wol_init(sky2);
4770
4771 wol |= sky2->wol;
cd28ab6a
SH		 4772 }
4773
8ab8fca2 4774 sky2_write32(hw, B0_IMSK, 0);
6de16237 4775 napi_disable(&hw->napi);
ae306cca 4776 sky2_power_aux(hw);
19720737 4777 rtnl_unlock();
e3173832 4778
d374c1c1 4779 pci_save_state(pdev);
e3173832 4780 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4781 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4782
2ccc99b7 4783 return 0;
cd28ab6a
SH		 4784}
4785
4786static int sky2_resume(struct pci_dev *pdev)
4787{
793b883e 4788 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4789 int i, err;
cd28ab6a 4790
549a68c3
SH		 4791 if (!hw)
4792 return 0;
4793
f71eb1a2
SH		 4794 err = pci_set_power_state(pdev, PCI_D0);
4795 if (err)
4796 goto out;
ae306cca
SH		 4797
4798 err = pci_restore_state(pdev);
4799 if (err)
4800 goto out;
4801
cd28ab6a 4802 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4803
4804 /* Re-enable all clocks */
05745c4a
SH		 4805 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4806 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4807 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4808 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4809
e3173832 4810 sky2_reset(hw);
8ab8fca2 4811 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4812 napi_enable(&hw->napi);
8ab8fca2 4813
af18d8b8 4814 rtnl_lock();
f05267e7 4815 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4816 err = sky2_reattach(hw->dev[i]);
4817 if (err)
4818 goto out;
cd28ab6a 4819 }
af18d8b8 4820 rtnl_unlock();
eb35cf60 4821
ae306cca 4822 return 0;
08c06d8a 4823out:
af18d8b8
SH		 4824 rtnl_unlock();
4825
b02a9258 4826 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4827 pci_disable_device(pdev);
08c06d8a 4828 return err;
cd28ab6a
SH		 4829}
4830#endif
4831
e3173832
SH		 4832static void sky2_shutdown(struct pci_dev *pdev)
4833{
4834 struct sky2_hw *hw = pci_get_drvdata(pdev);
4835 int i, wol = 0;
4836
549a68c3
SH		 4837 if (!hw)
4838 return;
4839
19720737 4840 rtnl_lock();
5c0d6b34 4841 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4842
4843 for (i = 0; i < hw->ports; i++) {
4844 struct net_device *dev = hw->dev[i];
4845 struct sky2_port *sky2 = netdev_priv(dev);
4846
4847 if (sky2->wol) {
4848 wol = 1;
4849 sky2_wol_init(sky2);
4850 }
4851 }
4852
4853 if (wol)
4854 sky2_power_aux(hw);
19720737 4855 rtnl_unlock();
e3173832
SH		 4856
4857 pci_enable_wake(pdev, PCI_D3hot, wol);
4858 pci_enable_wake(pdev, PCI_D3cold, wol);
4859
4860 pci_disable_device(pdev);
f71eb1a2 4861 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4862}
4863
cd28ab6a 4864static struct pci_driver sky2_driver = {
793b883e
SH		 4865 .name = DRV_NAME,
4866 .id_table = sky2_id_table,
4867 .probe = sky2_probe,
4868 .remove = __devexit_p(sky2_remove),
cd28ab6a 4869#ifdef CONFIG_PM
793b883e
SH		 4870 .suspend = sky2_suspend,
4871 .resume = sky2_resume,
cd28ab6a 4872#endif
e3173832 4873 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4874};
4875
4876static int __init sky2_init_module(void)
4877{
c844d483
SH		 4878 pr_info(PFX "driver version " DRV_VERSION "\n");
4879
3cf26753 4880 sky2_debug_init();
50241c4c 4881 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4882}
4883
4884static void __exit sky2_cleanup_module(void)
4885{
4886 pci_unregister_driver(&sky2_driver);
3cf26753 4887 sky2_debug_cleanup();
cd28ab6a
SH		 4888}
4889
4890module_init(sky2_init_module);
4891module_exit(sky2_cleanup_module);
4892
4893MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4894MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4895MODULE_LICENSE("GPL");
5f4f9dc1 4896MODULE_VERSION(DRV_VERSION);
ubuntu-bionic-kernel mirror