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[PATCH] sky2: device structure alignment
[mirror_ubuntu-zesty-kernel.git] / drivers / net / sky2.c
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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * TODO
28 * - coalescing setting?
cd28ab6a
SH		 29 *
30 * TOTEST
31 * - speed setting
724bca3c 32 * - suspend/resume
cd28ab6a
SH		 33 */
34
35#include <linux/config.h>
793b883e 36#include <linux/crc32.h>
cd28ab6a
SH		 37#include <linux/kernel.h>
38#include <linux/version.h>
39#include <linux/module.h>
40#include <linux/netdevice.h>
d0bbccfa 41#include <linux/dma-mapping.h>
cd28ab6a
SH		 42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/pci.h>
45#include <linux/ip.h>
46#include <linux/tcp.h>
47#include <linux/in.h>
48#include <linux/delay.h>
d1f13708 49#include <linux/if_vlan.h>
ef743d33 50#include <linux/mii.h>
cd28ab6a
SH		 51
52#include <asm/irq.h>
53
d1f13708
SH		 54#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
55#define SKY2_VLAN_TAG_USED 1
56#endif
57
cd28ab6a
SH		 58#include "sky2.h"
59
60#define DRV_NAME "sky2"
5f4f9dc1 61#define DRV_VERSION "0.9"
cd28ab6a
SH		 62#define PFX DRV_NAME " "
63
64/*
65 * The Yukon II chipset takes 64 bit command blocks (called list elements)
66 * that are organized into three (receive, transmit, status) different rings
67 * similar to Tigon3. A transmit can require several elements;
68 * a receive requires one (or two if using 64 bit dma).
69 */
70
cd28ab6a 71#define is_ec_a1(hw) \
21437643
SH		 72 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
73 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
cd28ab6a 74
13210ce5 75#define RX_LE_SIZE 512
cd28ab6a 76#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 77#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 78#define RX_DEF_PENDING RX_MAX_PENDING
79e57d32 79#define RX_COPY_THRESHOLD 256
793b883e
SH		 80
81#define TX_RING_SIZE 512
82#define TX_DEF_PENDING (TX_RING_SIZE - 1)
83#define TX_MIN_PENDING 64
84#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 85
793b883e 86#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 87#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
88#define ETH_JUMBO_MTU 9000
89#define TX_WATCHDOG (5 * HZ)
90#define NAPI_WEIGHT 64
91#define PHY_RETRIES 1000
92
93static const u32 default_msg =
793b883e
SH		 94 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
95 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
96 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
cd28ab6a 97
793b883e 98static int debug = -1; /* defaults above */
cd28ab6a
SH		 99module_param(debug, int, 0);
100MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
101
102static const struct pci_device_id sky2_id_table[] = {
793b883e 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 122 { 0 }
123};
793b883e 124
cd28ab6a
SH		 125MODULE_DEVICE_TABLE(pci, sky2_id_table);
126
127/* Avoid conditionals by using array */
128static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
129static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
130
92f965e8
SH		 131/* This driver supports yukon2 chipset only */
132static const char *yukon2_name[] = {
133 "XL", /* 0xb3 */
134 "EC Ultra", /* 0xb4 */
135 "UNKNOWN", /* 0xb5 */
136 "EC", /* 0xb6 */
137 "FE", /* 0xb7 */
793b883e
SH		 138};
139
793b883e 140/* Access to external PHY */
ef743d33 141static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 142{
143 int i;
144
145 gma_write16(hw, port, GM_SMI_DATA, val);
146 gma_write16(hw, port, GM_SMI_CTRL,
147 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
148
149 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 150 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 151 return 0;
793b883e 152 udelay(1);
cd28ab6a 153 }
ef743d33 154
793b883e 155 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 156 return -ETIMEDOUT;
cd28ab6a
SH		 157}
158
ef743d33 159static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 160{
161 int i;
162
793b883e 163 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 164 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
165
166 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 167 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
168 *val = gma_read16(hw, port, GM_SMI_DATA);
169 return 0;
170 }
171
793b883e 172 udelay(1);
cd28ab6a
SH		 173 }
174
ef743d33
SH		 175 return -ETIMEDOUT;
176}
177
178static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
179{
180 u16 v;
181
182 if (__gm_phy_read(hw, port, reg, &v) != 0)
183 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
184 return v;
cd28ab6a
SH		 185}
186
5afa0a9c
SH		 187static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
188{
189 u16 power_control;
190 u32 reg1;
191 int vaux;
192 int ret = 0;
193
194 pr_debug("sky2_set_power_state %d\n", state);
195 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
196
197 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
198 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
199 (power_control & PCI_PM_CAP_PME_D3cold);
200
201 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
202
203 power_control |= PCI_PM_CTRL_PME_STATUS;
204 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
205
206 switch (state) {
207 case PCI_D0:
208 /* switch power to VCC (WA for VAUX problem) */
209 sky2_write8(hw, B0_POWER_CTRL,
210 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
211
212 /* disable Core Clock Division, */
213 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
214
215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
216 /* enable bits are inverted */
217 sky2_write8(hw, B2_Y2_CLK_GATE,
218 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
219 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
220 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
221 else
222 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
223
224 /* Turn off phy power saving */
225 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
226 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
227
d571b694 228 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 229 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
230 reg1 |= PCI_Y2_PHY1_COMA;
231 if (hw->ports > 1)
232 reg1 |= PCI_Y2_PHY2_COMA;
233 }
234 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
235 break;
236
237 case PCI_D3hot:
238 case PCI_D3cold:
239 /* Turn on phy power saving */
240 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
241 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
242 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
243 else
244 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
245 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
246
247 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
248 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
249 else
250 /* enable bits are inverted */
251 sky2_write8(hw, B2_Y2_CLK_GATE,
252 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
253 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
254 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
255
256 /* switch power to VAUX */
257 if (vaux && state != PCI_D3cold)
258 sky2_write8(hw, B0_POWER_CTRL,
259 (PC_VAUX_ENA | PC_VCC_ENA |
260 PC_VAUX_ON | PC_VCC_OFF));
261 break;
262 default:
263 printk(KERN_ERR PFX "Unknown power state %d\n", state);
264 ret = -1;
265 }
266
267 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
268 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
269 return ret;
270}
271
cd28ab6a
SH		 272static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
273{
274 u16 reg;
275
276 /* disable all GMAC IRQ's */
277 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
278 /* disable PHY IRQs */
279 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 280
cd28ab6a
SH		 281 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
282 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
283 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
284 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
285
286 reg = gma_read16(hw, port, GM_RX_CTRL);
287 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
288 gma_write16(hw, port, GM_RX_CTRL, reg);
289}
290
291static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
292{
293 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 294 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 295
793b883e 296 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 297 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
298
299 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 300 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 301 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
302
303 if (hw->chip_id == CHIP_ID_YUKON_EC)
304 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
305 else
306 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
307
308 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
309 }
310
311 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
312 if (hw->copper) {
313 if (hw->chip_id == CHIP_ID_YUKON_FE) {
314 /* enable automatic crossover */
315 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
316 } else {
317 /* disable energy detect */
318 ctrl &= ~PHY_M_PC_EN_DET_MSK;
319
320 /* enable automatic crossover */
321 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
322
323 if (sky2->autoneg == AUTONEG_ENABLE &&
324 hw->chip_id == CHIP_ID_YUKON_XL) {
325 ctrl &= ~PHY_M_PC_DSC_MSK;
326 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
327 }
328 }
329 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
330 } else {
331 /* workaround for deviation #4.88 (CRC errors) */
332 /* disable Automatic Crossover */
333
334 ctrl &= ~PHY_M_PC_MDIX_MSK;
335 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
336
337 if (hw->chip_id == CHIP_ID_YUKON_XL) {
338 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
339 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
340 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
341 ctrl &= ~PHY_M_MAC_MD_MSK;
342 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
343 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
344
345 /* select page 1 to access Fiber registers */
346 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
347 }
cd28ab6a
SH		 348 }
349
350 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
351 if (sky2->autoneg == AUTONEG_DISABLE)
352 ctrl &= ~PHY_CT_ANE;
353 else
354 ctrl |= PHY_CT_ANE;
355
356 ctrl |= PHY_CT_RESET;
357 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
358
359 ctrl = 0;
360 ct1000 = 0;
361 adv = PHY_AN_CSMA;
362
363 if (sky2->autoneg == AUTONEG_ENABLE) {
364 if (hw->copper) {
365 if (sky2->advertising & ADVERTISED_1000baseT_Full)
366 ct1000 |= PHY_M_1000C_AFD;
367 if (sky2->advertising & ADVERTISED_1000baseT_Half)
368 ct1000 |= PHY_M_1000C_AHD;
369 if (sky2->advertising & ADVERTISED_100baseT_Full)
370 adv |= PHY_M_AN_100_FD;
371 if (sky2->advertising & ADVERTISED_100baseT_Half)
372 adv |= PHY_M_AN_100_HD;
373 if (sky2->advertising & ADVERTISED_10baseT_Full)
374 adv |= PHY_M_AN_10_FD;
375 if (sky2->advertising & ADVERTISED_10baseT_Half)
376 adv |= PHY_M_AN_10_HD;
793b883e 377 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 378 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
379
380 /* Set Flow-control capabilities */
381 if (sky2->tx_pause && sky2->rx_pause)
793b883e 382 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 383 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 384 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 385 else if (!sky2->rx_pause && sky2->tx_pause)
386 adv |= PHY_AN_PAUSE_ASYM; /* local */
387
388 /* Restart Auto-negotiation */
389 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
390 } else {
391 /* forced speed/duplex settings */
392 ct1000 = PHY_M_1000C_MSE;
393
394 if (sky2->duplex == DUPLEX_FULL)
395 ctrl |= PHY_CT_DUP_MD;
396
397 switch (sky2->speed) {
398 case SPEED_1000:
399 ctrl |= PHY_CT_SP1000;
400 break;
401 case SPEED_100:
402 ctrl |= PHY_CT_SP100;
403 break;
404 }
405
406 ctrl |= PHY_CT_RESET;
407 }
408
409 if (hw->chip_id != CHIP_ID_YUKON_FE)
410 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
411
412 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
413 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
414
415 /* Setup Phy LED's */
416 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
417 ledover = 0;
418
419 switch (hw->chip_id) {
420 case CHIP_ID_YUKON_FE:
421 /* on 88E3082 these bits are at 11..9 (shifted left) */
422 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
423
424 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
425
426 /* delete ACT LED control bits */
427 ctrl &= ~PHY_M_FELP_LED1_MSK;
428 /* change ACT LED control to blink mode */
429 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
430 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
431 break;
432
433 case CHIP_ID_YUKON_XL:
793b883e 434 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 435
436 /* select page 3 to access LED control register */
437 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
438
439 /* set LED Function Control register */
793b883e
SH		 440 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
441 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
442 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
443 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 444
445 /* set Polarity Control register */
446 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 447 (PHY_M_POLC_LS1_P_MIX(4) |
448 PHY_M_POLC_IS0_P_MIX(4) |
449 PHY_M_POLC_LOS_CTRL(2) |
450 PHY_M_POLC_INIT_CTRL(2) |
451 PHY_M_POLC_STA1_CTRL(2) |
452 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 453
454 /* restore page register */
793b883e 455 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 456 break;
457
458 default:
459 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
460 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
461 /* turn off the Rx LED (LED_RX) */
462 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
463 }
464
465 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
466
467 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
468 /* turn on 100 Mbps LED (LED_LINK100) */
469 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
470 }
471
472 if (ledover)
473 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
474
d571b694 475 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 476 if (sky2->autoneg == AUTONEG_ENABLE)
477 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
478 else
479 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
480}
481
482static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
483{
484 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
485 u16 reg;
486 int i;
487 const u8 *addr = hw->dev[port]->dev_addr;
488
42eeea01
SH		 489 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
490 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 491
492 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
493
793b883e 494 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 495 /* WA DEV_472 -- looks like crossed wires on port 2 */
496 /* clear GMAC 1 Control reset */
497 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
498 do {
499 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
500 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
501 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
502 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
503 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
504 }
505
cd28ab6a
SH		 506 if (sky2->autoneg == AUTONEG_DISABLE) {
507 reg = gma_read16(hw, port, GM_GP_CTRL);
508 reg |= GM_GPCR_AU_ALL_DIS;
509 gma_write16(hw, port, GM_GP_CTRL, reg);
510 gma_read16(hw, port, GM_GP_CTRL);
511
cd28ab6a
SH		 512 switch (sky2->speed) {
513 case SPEED_1000:
514 reg |= GM_GPCR_SPEED_1000;
515 /* fallthru */
516 case SPEED_100:
517 reg |= GM_GPCR_SPEED_100;
518 }
519
520 if (sky2->duplex == DUPLEX_FULL)
521 reg |= GM_GPCR_DUP_FULL;
522 } else
523 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
524
525 if (!sky2->tx_pause && !sky2->rx_pause) {
526 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 527 reg |=
528 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
529 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 530 /* disable Rx flow-control */
531 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
532 }
533
534 gma_write16(hw, port, GM_GP_CTRL, reg);
535
793b883e 536 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a
SH		 537
538 spin_lock_bh(&hw->phy_lock);
539 sky2_phy_init(hw, port);
540 spin_unlock_bh(&hw->phy_lock);
541
542 /* MIB clear */
543 reg = gma_read16(hw, port, GM_PHY_ADDR);
544 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
545
546 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 547 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 548 gma_write16(hw, port, GM_PHY_ADDR, reg);
549
550 /* transmit control */
551 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
552
553 /* receive control reg: unicast + multicast + no FCS */
554 gma_write16(hw, port, GM_RX_CTRL,
793b883e 555 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 556
557 /* transmit flow control */
558 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
559
560 /* transmit parameter */
561 gma_write16(hw, port, GM_TX_PARAM,
562 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
563 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
564 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
565 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
566
567 /* serial mode register */
568 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 569 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 570
6b1a3aef 571 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 572 reg |= GM_SMOD_JUMBO_ENA;
573
574 gma_write16(hw, port, GM_SERIAL_MODE, reg);
575
cd28ab6a
SH		 576 /* virtual address for data */
577 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
578
793b883e
SH		 579 /* physical address: used for pause frames */
580 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
581
582 /* ignore counter overflows */
cd28ab6a
SH		 583 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
584 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
585 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
586
587 /* Configure Rx MAC FIFO */
588 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 589 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 590 GMF_RX_CTRL_DEF);
cd28ab6a 591
d571b694 592 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 593 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 594
793b883e
SH		 595 /* Set threshold to 0xa (64 bytes)
596 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 597 */
598 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
599
600 /* Configure Tx MAC FIFO */
601 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
602 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 603
604 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
605 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
606 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
607 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
608 /* set Tx GMAC FIFO Almost Empty Threshold */
609 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
610 /* Disable Store & Forward mode for TX */
611 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
612 }
613 }
614
cd28ab6a
SH		 615}
616
617static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
618{
619 u32 end;
620
621 start /= 8;
622 len /= 8;
623 end = start + len - 1;
793b883e 624
cd28ab6a
SH		 625 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
626 sky2_write32(hw, RB_ADDR(q, RB_START), start);
627 sky2_write32(hw, RB_ADDR(q, RB_END), end);
628 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
629 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
630
631 if (q == Q_R1 || q == Q_R2) {
793b883e
SH		 632 u32 rxup, rxlo;
633
634 rxlo = len/2;
635 rxup = rxlo + len/4;
793b883e 636
cd28ab6a 637 /* Set thresholds on receive queue's */
793b883e
SH		 638 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
639 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
cd28ab6a
SH		 640 } else {
641 /* Enable store & forward on Tx queue's because
642 * Tx FIFO is only 1K on Yukon
643 */
644 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
645 }
646
647 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 648 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 649}
650
cd28ab6a 651/* Setup Bus Memory Interface */
af4ed7e6 652static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 653{
654 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
655 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
656 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 657 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 658}
659
cd28ab6a
SH		 660/* Setup prefetch unit registers. This is the interface between
661 * hardware and driver list elements
662 */
663static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
664 u64 addr, u32 last)
665{
cd28ab6a
SH		 666 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
667 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
668 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
669 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
670 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
671 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 672
673 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 674}
675
793b883e
SH		 676static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
677{
678 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
679
680 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
681 return le;
682}
cd28ab6a
SH		 683
684/*
d571b694 685 * This is a workaround code taken from SysKonnect sk98lin driver
793b883e 686 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a
SH		 687 */
688static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
689 u16 idx, u16 *last, u16 size)
cd28ab6a 690{
cd28ab6a
SH		 691 if (is_ec_a1(hw) && idx < *last) {
692 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
693
694 if (hwget == 0) {
695 /* Start prefetching again */
793b883e 696 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 697 goto setnew;
698 }
699
793b883e 700 if (hwget == size - 1) {
cd28ab6a
SH		 701 /* set watermark to one list element */
702 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
703
704 /* set put index to first list element */
705 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 706 } else /* have hardware go to end of list */
707 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
708 size - 1);
cd28ab6a 709 } else {
793b883e 710setnew:
cd28ab6a 711 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 712 }
bea86103 713 *last = idx;
cd28ab6a
SH		 714}
715
793b883e 716
cd28ab6a
SH		 717static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
718{
719 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
720 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
721 return le;
722}
723
a018e330
SH		 724/* Return high part of DMA address (could be 32 or 64 bit) */
725static inline u32 high32(dma_addr_t a)
726{
727 return (a >> 16) >> 16;
728}
729
793b883e
SH		 730/* Build description to hardware about buffer */
731static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
cd28ab6a
SH		 732{
733 struct sky2_rx_le *le;
a018e330 734 u32 hi = high32(re->mapaddr);
cd28ab6a 735
793b883e
SH		 736 re->idx = sky2->rx_put;
737 if (sky2->rx_addr64 != hi) {
cd28ab6a 738 le = sky2_next_rx(sky2);
793b883e 739 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 740 le->ctrl = 0;
741 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 742 sky2->rx_addr64 = high32(re->mapaddr + re->maplen);
cd28ab6a 743 }
793b883e 744
cd28ab6a 745 le = sky2_next_rx(sky2);
793b883e
SH		 746 le->addr = cpu_to_le32((u32) re->mapaddr);
747 le->length = cpu_to_le16(re->maplen);
cd28ab6a
SH		 748 le->ctrl = 0;
749 le->opcode = OP_PACKET | HW_OWNER;
750}
751
793b883e 752
cd28ab6a
SH		 753/* Tell chip where to start receive checksum.
754 * Actually has two checksums, but set both same to avoid possible byte
755 * order problems.
756 */
793b883e 757static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 758{
759 struct sky2_rx_le *le;
760
cd28ab6a 761 le = sky2_next_rx(sky2);
793b883e 762 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 763 le->ctrl = 0;
764 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 765
793b883e
SH		 766 sky2_write32(sky2->hw,
767 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
768 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 769
770}
771
6b1a3aef
SH		 772/*
773 * The RX Stop command will not work for Yukon-2 if the BMU does not
774 * reach the end of packet and since we can't make sure that we have
775 * incoming data, we must reset the BMU while it is not doing a DMA
776 * transfer. Since it is possible that the RX path is still active,
777 * the RX RAM buffer will be stopped first, so any possible incoming
778 * data will not trigger a DMA. After the RAM buffer is stopped, the
779 * BMU is polled until any DMA in progress is ended and only then it
780 * will be reset.
781 */
782static void sky2_rx_stop(struct sky2_port *sky2)
783{
784 struct sky2_hw *hw = sky2->hw;
785 unsigned rxq = rxqaddr[sky2->port];
786 int i;
787
788 /* disable the RAM Buffer receive queue */
789 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
790
791 for (i = 0; i < 0xffff; i++)
792 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
793 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
794 goto stopped;
795
796 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
797 sky2->netdev->name);
798stopped:
799 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
800
801 /* reset the Rx prefetch unit */
802 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
803}
793b883e 804
d571b694 805/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 806static void sky2_rx_clean(struct sky2_port *sky2)
807{
808 unsigned i;
809
810 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 811 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 812 struct ring_info *re = sky2->rx_ring + i;
813
814 if (re->skb) {
793b883e
SH		 815 pci_unmap_single(sky2->hw->pdev,
816 re->mapaddr, re->maplen,
cd28ab6a
SH		 817 PCI_DMA_FROMDEVICE);
818 kfree_skb(re->skb);
819 re->skb = NULL;
820 }
821 }
822}
823
ef743d33
SH		 824/* Basic MII support */
825static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
826{
827 struct mii_ioctl_data *data = if_mii(ifr);
828 struct sky2_port *sky2 = netdev_priv(dev);
829 struct sky2_hw *hw = sky2->hw;
830 int err = -EOPNOTSUPP;
831
832 if (!netif_running(dev))
833 return -ENODEV; /* Phy still in reset */
834
835 switch(cmd) {
836 case SIOCGMIIPHY:
837 data->phy_id = PHY_ADDR_MARV;
838
839 /* fallthru */
840 case SIOCGMIIREG: {
841 u16 val = 0;
842 spin_lock_bh(&hw->phy_lock);
843 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
844 spin_unlock_bh(&hw->phy_lock);
845 data->val_out = val;
846 break;
847 }
848
849 case SIOCSMIIREG:
850 if (!capable(CAP_NET_ADMIN))
851 return -EPERM;
852
853 spin_lock_bh(&hw->phy_lock);
854 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
855 data->val_in);
856 spin_unlock_bh(&hw->phy_lock);
857 break;
858 }
859 return err;
860}
861
d1f13708
SH		 862#ifdef SKY2_VLAN_TAG_USED
863static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
864{
865 struct sky2_port *sky2 = netdev_priv(dev);
866 struct sky2_hw *hw = sky2->hw;
867 u16 port = sky2->port;
868 unsigned long flags;
869
870 spin_lock_irqsave(&sky2->tx_lock, flags);
871
872 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
873 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
874 sky2->vlgrp = grp;
875
876 spin_unlock_irqrestore(&sky2->tx_lock, flags);
877}
878
879static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
880{
881 struct sky2_port *sky2 = netdev_priv(dev);
882 struct sky2_hw *hw = sky2->hw;
883 u16 port = sky2->port;
884 unsigned long flags;
885
886 spin_lock_irqsave(&sky2->tx_lock, flags);
887
888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
889 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
890 if (sky2->vlgrp)
891 sky2->vlgrp->vlan_devices[vid] = NULL;
892
893 spin_unlock_irqrestore(&sky2->tx_lock, flags);
894}
895#endif
896
79e57d32 897#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
6b1a3aef 898static inline unsigned rx_size(const struct sky2_port *sky2)
cd28ab6a 899{
79e57d32 900 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
cd28ab6a
SH		 901}
902
903/*
904 * Allocate and setup receiver buffer pool.
905 * In case of 64 bit dma, there are 2X as many list elements
906 * available as ring entries
907 * and need to reserve one list element so we don't wrap around.
79e57d32
SH		 908 *
909 * It appears the hardware has a bug in the FIFO logic that
910 * cause it to hang if the FIFO gets overrun and the receive buffer
911 * is not aligned. This means we can't use skb_reserve to align
912 * the IP header.
cd28ab6a 913 */
6b1a3aef 914static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 915{
6b1a3aef
SH		 916 struct sky2_hw *hw = sky2->hw;
917 unsigned size = rx_size(sky2);
918 unsigned rxq = rxqaddr[sky2->port];
919 int i;
cd28ab6a 920
6b1a3aef 921 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 922 sky2_qset(hw, rxq);
6b1a3aef
SH		 923 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
924
925 rx_set_checksum(sky2);
793b883e 926 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 927 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 928
79e57d32 929 re->skb = dev_alloc_skb(size);
cd28ab6a
SH		 930 if (!re->skb)
931 goto nomem;
932
6b1a3aef 933 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
79e57d32
SH		 934 size, PCI_DMA_FROMDEVICE);
935 re->maplen = size;
793b883e 936 sky2_rx_add(sky2, re);
cd28ab6a
SH		 937 }
938
6b1a3aef
SH		 939 /* Tell chip about available buffers */
940 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
941 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 942 return 0;
943nomem:
944 sky2_rx_clean(sky2);
945 return -ENOMEM;
946}
947
948/* Bring up network interface. */
949static int sky2_up(struct net_device *dev)
950{
951 struct sky2_port *sky2 = netdev_priv(dev);
952 struct sky2_hw *hw = sky2->hw;
953 unsigned port = sky2->port;
954 u32 ramsize, rxspace;
955 int err = -ENOMEM;
956
957 if (netif_msg_ifup(sky2))
958 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
959
960 /* must be power of 2 */
961 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 962 TX_RING_SIZE *
963 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 964 &sky2->tx_le_map);
965 if (!sky2->tx_le)
966 goto err_out;
967
b2f5ad4f 968 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
cd28ab6a
SH		 969 GFP_KERNEL);
970 if (!sky2->tx_ring)
971 goto err_out;
972 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 973
974 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
975 &sky2->rx_le_map);
976 if (!sky2->rx_le)
977 goto err_out;
978 memset(sky2->rx_le, 0, RX_LE_BYTES);
979
b2f5ad4f 980 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
cd28ab6a
SH		 981 GFP_KERNEL);
982 if (!sky2->rx_ring)
983 goto err_out;
984
985 sky2_mac_init(hw, port);
986
987 /* Configure RAM buffers */
988 if (hw->chip_id == CHIP_ID_YUKON_FE ||
989 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
990 ramsize = 4096;
991 else {
793b883e
SH		 992 u8 e0 = sky2_read8(hw, B2_E_0);
993 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
cd28ab6a
SH		 994 }
995
996 /* 2/3 for Rx */
997 rxspace = (2 * ramsize) / 3;
998 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
999 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1000
793b883e
SH		 1001 /* Make sure SyncQ is disabled */
1002 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1003 RB_RST_SET);
1004
af4ed7e6 1005 sky2_qset(hw, txqaddr[port]);
5a5b1ea0
SH		 1006 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1007 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1008
1009
6b1a3aef
SH		 1010 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1011 TX_RING_SIZE - 1);
cd28ab6a 1012
6b1a3aef 1013 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1014 if (err)
1015 goto err_out;
1016
cd28ab6a
SH		 1017 /* Enable interrupts from phy/mac for port */
1018 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1019 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1020 return 0;
1021
1022err_out:
1023 if (sky2->rx_le)
1024 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1025 sky2->rx_le, sky2->rx_le_map);
1026 if (sky2->tx_le)
1027 pci_free_consistent(hw->pdev,
1028 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1029 sky2->tx_le, sky2->tx_le_map);
1030 if (sky2->tx_ring)
1031 kfree(sky2->tx_ring);
1032 if (sky2->rx_ring)
1033 kfree(sky2->rx_ring);
1034
1035 return err;
1036}
1037
793b883e
SH		 1038/* Modular subtraction in ring */
1039static inline int tx_dist(unsigned tail, unsigned head)
1040{
1041 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
1042}
cd28ab6a 1043
793b883e
SH		 1044/* Number of list elements available for next tx */
1045static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1046{
793b883e 1047 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1048}
1049
793b883e
SH		 1050/* Estimate of number of transmit list elements required */
1051static inline unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1052{
793b883e
SH		 1053 unsigned count;
1054
1055 count = sizeof(dma_addr_t) / sizeof(u32);
1056 count += skb_shinfo(skb)->nr_frags * count;
1057
1058 if (skb_shinfo(skb)->tso_size)
1059 ++count;
1060
1061 if (skb->ip_summed)
1062 ++count;
1063
1064 return count;
cd28ab6a
SH		 1065}
1066
793b883e
SH		 1067/*
1068 * Put one packet in ring for transmit.
1069 * A single packet can generate multiple list elements, and
1070 * the number of ring elements will probably be less than the number
1071 * of list elements used.
1072 */
cd28ab6a
SH		 1073static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1074{
1075 struct sky2_port *sky2 = netdev_priv(dev);
1076 struct sky2_hw *hw = sky2->hw;
d1f13708 1077 struct sky2_tx_le *le = NULL;
cd28ab6a 1078 struct ring_info *re;
793b883e 1079 unsigned long flags;
cd28ab6a
SH		 1080 unsigned i, len;
1081 dma_addr_t mapping;
1082 u32 addr64;
1083 u16 mss;
1084 u8 ctrl;
1085
793b883e
SH		 1086 local_irq_save(flags);
1087 if (!spin_trylock(&sky2->tx_lock)) {
1088 local_irq_restore(flags);
cd28ab6a 1089 return NETDEV_TX_LOCKED;
793b883e 1090 }
cd28ab6a 1091
793b883e 1092 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
cd28ab6a 1093 netif_stop_queue(dev);
793b883e 1094 spin_unlock_irqrestore(&sky2->tx_lock, flags);
cd28ab6a
SH		 1095
1096 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1097 dev->name);
1098 return NETDEV_TX_BUSY;
1099 }
1100
793b883e 1101 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1102 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1103 dev->name, sky2->tx_prod, skb->len);
1104
cd28ab6a
SH		 1105 len = skb_headlen(skb);
1106 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1107 addr64 = high32(mapping);
793b883e
SH		 1108
1109 re = sky2->tx_ring + sky2->tx_prod;
1110
a018e330
SH		 1111 /* Send high bits if changed or crosses boundary */
1112 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1113 le = get_tx_le(sky2);
1114 le->tx.addr = cpu_to_le32(addr64);
1115 le->ctrl = 0;
1116 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1117 sky2->tx_addr64 = high32(mapping + len);
793b883e 1118 }
cd28ab6a
SH		 1119
1120 /* Check for TCP Segmentation Offload */
1121 mss = skb_shinfo(skb)->tso_size;
793b883e 1122 if (mss != 0) {
cd28ab6a
SH		 1123 /* just drop the packet if non-linear expansion fails */
1124 if (skb_header_cloned(skb) &&
1125 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1126 dev_kfree_skb_any(skb);
1127 goto out_unlock;
cd28ab6a
SH		 1128 }
1129
1130 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1131 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1132 mss += ETH_HLEN;
793b883e 1133 }
cd28ab6a 1134
793b883e 1135 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1136 le = get_tx_le(sky2);
1137 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1138 le->tx.tso.rsvd = 0;
cd28ab6a 1139 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1140 le->ctrl = 0;
793b883e 1141 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1142 }
1143
cd28ab6a 1144 ctrl = 0;
d1f13708
SH		 1145#ifdef SKY2_VLAN_TAG_USED
1146 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1147 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1148 if (!le) {
1149 le = get_tx_le(sky2);
1150 le->tx.addr = 0;
1151 le->opcode = OP_VLAN|HW_OWNER;
1152 le->ctrl = 0;
1153 } else
1154 le->opcode |= OP_VLAN;
1155 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1156 ctrl |= INS_VLAN;
1157 }
1158#endif
1159
1160 /* Handle TCP checksum offload */
cd28ab6a 1161 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1162 u16 hdr = skb->h.raw - skb->data;
1163 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1164
1165 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1166 if (skb->nh.iph->protocol == IPPROTO_UDP)
1167 ctrl |= UDPTCP;
1168
1169 le = get_tx_le(sky2);
1170 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1171 le->tx.csum.offset = cpu_to_le16(offset);
1172 le->length = 0; /* initial checksum value */
cd28ab6a 1173 le->ctrl = 1; /* one packet */
793b883e 1174 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1175 }
1176
1177 le = get_tx_le(sky2);
1178 le->tx.addr = cpu_to_le32((u32) mapping);
1179 le->length = cpu_to_le16(len);
1180 le->ctrl = ctrl;
793b883e 1181 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1182
793b883e 1183 /* Record the transmit mapping info */
cd28ab6a 1184 re->skb = skb;
793b883e
SH		 1185 re->mapaddr = mapping;
1186 re->maplen = len;
cd28ab6a
SH		 1187
1188 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1189 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
793b883e 1190 struct ring_info *fre;
cd28ab6a
SH		 1191
1192 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1193 frag->size, PCI_DMA_TODEVICE);
793b883e
SH		 1194 addr64 = (mapping >> 16) >> 16;
1195 if (addr64 != sky2->tx_addr64) {
1196 le = get_tx_le(sky2);
1197 le->tx.addr = cpu_to_le32(addr64);
1198 le->ctrl = 0;
1199 le->opcode = OP_ADDR64 | HW_OWNER;
1200 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1201 }
1202
1203 le = get_tx_le(sky2);
1204 le->tx.addr = cpu_to_le32((u32) mapping);
1205 le->length = cpu_to_le16(frag->size);
1206 le->ctrl = ctrl;
793b883e 1207 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1208
793b883e
SH		 1209 fre = sky2->tx_ring
1210 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1211 fre->skb = NULL;
1212 fre->mapaddr = mapping;
1213 fre->maplen = frag->size;
cd28ab6a 1214 }
793b883e 1215 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1216 le->ctrl |= EOP;
1217
724bca3c 1218 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
cd28ab6a
SH		 1219 &sky2->tx_last_put, TX_RING_SIZE);
1220
793b883e 1221 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
cd28ab6a 1222 netif_stop_queue(dev);
793b883e
SH		 1223
1224out_unlock:
1225 mmiowb();
1226 spin_unlock_irqrestore(&sky2->tx_lock, flags);
cd28ab6a
SH		 1227
1228 dev->trans_start = jiffies;
1229 return NETDEV_TX_OK;
1230}
1231
cd28ab6a 1232/*
793b883e
SH		 1233 * Free ring elements from starting at tx_cons until "done"
1234 *
1235 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1236 * buffers; these are deferred until completion.
cd28ab6a 1237 */
d11c13e7 1238static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1239{
d11c13e7 1240 struct net_device *dev = sky2->netdev;
793b883e 1241 unsigned i;
cd28ab6a 1242
2224795d
SH		 1243 if (done == sky2->tx_cons)
1244 return;
1245
d11c13e7 1246 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1247 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1248 dev->name, done);
cd28ab6a
SH		 1249
1250 spin_lock(&sky2->tx_lock);
cd28ab6a 1251
793b883e
SH		 1252 while (sky2->tx_cons != done) {
1253 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1254 struct sk_buff *skb;
cd28ab6a 1255
793b883e
SH		 1256 /* Check for partial status */
1257 if (tx_dist(sky2->tx_cons, done)
1258 < tx_dist(sky2->tx_cons, re->idx))
1259 goto out;
1260
1261 skb = re->skb;
1262 pci_unmap_single(sky2->hw->pdev,
1263 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1264
1265 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1266 struct ring_info *fre;
1267 fre =
1268 sky2->tx_ring + (sky2->tx_cons + i +
1269 1) % TX_RING_SIZE;
1270 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1271 fre->maplen, PCI_DMA_TODEVICE);
cd28ab6a
SH		 1272 }
1273
cd28ab6a 1274 dev_kfree_skb_any(skb);
cd28ab6a 1275
793b883e
SH		 1276 sky2->tx_cons = re->idx;
1277 }
1278out:
1279
1280 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1281 netif_wake_queue(dev);
1282 spin_unlock(&sky2->tx_lock);
1283}
1284
1285/* Cleanup all untransmitted buffers, assume transmitter not running */
1286static inline void sky2_tx_clean(struct sky2_port *sky2)
1287{
d11c13e7 1288 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1289}
1290
1291/* Network shutdown */
1292static int sky2_down(struct net_device *dev)
1293{
1294 struct sky2_port *sky2 = netdev_priv(dev);
1295 struct sky2_hw *hw = sky2->hw;
1296 unsigned port = sky2->port;
1297 u16 ctrl;
cd28ab6a
SH		 1298
1299 if (netif_msg_ifdown(sky2))
1300 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1301
018d1c66 1302 /* Stop more packets from being queued */
cd28ab6a
SH		 1303 netif_stop_queue(dev);
1304
018d1c66
SH		 1305 /* Disable port IRQ */
1306 local_irq_disable();
1307 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1308 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1309 local_irq_enable();
1310
1311
793b883e
SH		 1312 sky2_phy_reset(hw, port);
1313
cd28ab6a
SH		 1314 /* Stop transmitter */
1315 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1316 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1317
1318 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1319 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1320
1321 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1322 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1323 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1324
1325 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1326
1327 /* Workaround shared GMAC reset */
793b883e
SH		 1328 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1329 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1330 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1331
1332 /* Disable Force Sync bit and Enable Alloc bit */
1333 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1334 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1335
1336 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1337 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1338 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1339
1340 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1341 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1342 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1343
1344 /* Reset the Tx prefetch units */
1345 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1346 PREF_UNIT_RST_SET);
1347
1348 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1349
6b1a3aef 1350 sky2_rx_stop(sky2);
cd28ab6a
SH		 1351
1352 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1353 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1354
d571b694 1355 /* turn off LED's */
cd28ab6a
SH		 1356 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1357
018d1c66
SH		 1358 synchronize_irq(hw->pdev->irq);
1359
cd28ab6a
SH		 1360 sky2_tx_clean(sky2);
1361 sky2_rx_clean(sky2);
1362
1363 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1364 sky2->rx_le, sky2->rx_le_map);
1365 kfree(sky2->rx_ring);
1366
1367 pci_free_consistent(hw->pdev,
1368 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1369 sky2->tx_le, sky2->tx_le_map);
1370 kfree(sky2->tx_ring);
1371
1372 return 0;
1373}
1374
1375static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1376{
793b883e
SH		 1377 if (!hw->copper)
1378 return SPEED_1000;
1379
cd28ab6a
SH		 1380 if (hw->chip_id == CHIP_ID_YUKON_FE)
1381 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1382
1383 switch (aux & PHY_M_PS_SPEED_MSK) {
1384 case PHY_M_PS_SPEED_1000:
1385 return SPEED_1000;
1386 case PHY_M_PS_SPEED_100:
1387 return SPEED_100;
1388 default:
1389 return SPEED_10;
1390 }
1391}
1392
1393static void sky2_link_up(struct sky2_port *sky2)
1394{
1395 struct sky2_hw *hw = sky2->hw;
1396 unsigned port = sky2->port;
1397 u16 reg;
1398
1399 /* Enable Transmit FIFO Underrun */
793b883e 1400 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1401
1402 reg = gma_read16(hw, port, GM_GP_CTRL);
1403 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1404 reg |= GM_GPCR_DUP_FULL;
1405
cd28ab6a
SH		 1406 /* enable Rx/Tx */
1407 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1408 gma_write16(hw, port, GM_GP_CTRL, reg);
1409 gma_read16(hw, port, GM_GP_CTRL);
1410
1411 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1412
1413 netif_carrier_on(sky2->netdev);
1414 netif_wake_queue(sky2->netdev);
1415
1416 /* Turn on link LED */
793b883e 1417 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1418 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1419
793b883e
SH		 1420 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1421 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1422
1423 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1424 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1425 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1426 SPEED_10 ? 7 : 0) |
1427 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1428 SPEED_100 ? 7 : 0) |
1429 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1430 SPEED_1000 ? 7 : 0));
1431 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1432 }
1433
cd28ab6a
SH		 1434 if (netif_msg_link(sky2))
1435 printk(KERN_INFO PFX
d571b694 1436 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1437 sky2->netdev->name, sky2->speed,
1438 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1439 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1440 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1441}
1442
1443static void sky2_link_down(struct sky2_port *sky2)
1444{
1445 struct sky2_hw *hw = sky2->hw;
1446 unsigned port = sky2->port;
1447 u16 reg;
1448
1449 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1450
1451 reg = gma_read16(hw, port, GM_GP_CTRL);
1452 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1453 gma_write16(hw, port, GM_GP_CTRL, reg);
1454 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1455
1456 if (sky2->rx_pause && !sky2->tx_pause) {
1457 /* restore Asymmetric Pause bit */
1458 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1459 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1460 | PHY_M_AN_ASP);
cd28ab6a
SH		 1461 }
1462
1463 sky2_phy_reset(hw, port);
1464
1465 netif_carrier_off(sky2->netdev);
1466 netif_stop_queue(sky2->netdev);
1467
1468 /* Turn on link LED */
1469 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1470
1471 if (netif_msg_link(sky2))
1472 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1473 sky2_phy_init(hw, port);
1474}
1475
793b883e
SH		 1476static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1477{
1478 struct sky2_hw *hw = sky2->hw;
1479 unsigned port = sky2->port;
1480 u16 lpa;
1481
1482 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1483
1484 if (lpa & PHY_M_AN_RF) {
1485 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1486 return -1;
1487 }
1488
1489 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1490 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1491 printk(KERN_ERR PFX "%s: master/slave fault",
1492 sky2->netdev->name);
1493 return -1;
1494 }
1495
1496 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1497 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1498 sky2->netdev->name);
1499 return -1;
1500 }
1501
1502 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1503
1504 sky2->speed = sky2_phy_speed(hw, aux);
1505
1506 /* Pause bits are offset (9..8) */
1507 if (hw->chip_id == CHIP_ID_YUKON_XL)
1508 aux >>= 6;
1509
1510 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1511 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1512
1513 if ((sky2->tx_pause || sky2->rx_pause)
1514 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1515 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1516 else
1517 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1518
1519 return 0;
1520}
cd28ab6a
SH		 1521
1522/*
d571b694 1523 * Interrupt from PHY are handled in tasklet (soft irq)
cd28ab6a
SH		 1524 * because accessing phy registers requires spin wait which might
1525 * cause excess interrupt latency.
1526 */
1527static void sky2_phy_task(unsigned long data)
1528{
793b883e 1529 struct sky2_port *sky2 = (struct sky2_port *)data;
cd28ab6a 1530 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1531 u16 istatus, phystat;
1532
793b883e
SH		 1533 spin_lock(&hw->phy_lock);
1534 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1535 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1536
1537 if (netif_msg_intr(sky2))
1538 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1539 sky2->netdev->name, istatus, phystat);
1540
1541 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1542 if (sky2_autoneg_done(sky2, phystat) == 0)
1543 sky2_link_up(sky2);
1544 goto out;
1545 }
cd28ab6a 1546
793b883e
SH		 1547 if (istatus & PHY_M_IS_LSP_CHANGE)
1548 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1549
793b883e
SH		 1550 if (istatus & PHY_M_IS_DUP_CHANGE)
1551 sky2->duplex =
1552 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1553
793b883e
SH		 1554 if (istatus & PHY_M_IS_LST_CHANGE) {
1555 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1556 sky2_link_up(sky2);
793b883e
SH		 1557 else
1558 sky2_link_down(sky2);
cd28ab6a 1559 }
793b883e
SH		 1560out:
1561 spin_unlock(&hw->phy_lock);
cd28ab6a
SH		 1562
1563 local_irq_disable();
793b883e 1564 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1565 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1566 local_irq_enable();
1567}
1568
1569static void sky2_tx_timeout(struct net_device *dev)
1570{
1571 struct sky2_port *sky2 = netdev_priv(dev);
1572
1573 if (netif_msg_timer(sky2))
1574 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1575
1576 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1577 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1578
1579 sky2_tx_clean(sky2);
1580}
1581
1582static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1583{
6b1a3aef
SH		 1584 struct sky2_port *sky2 = netdev_priv(dev);
1585 struct sky2_hw *hw = sky2->hw;
1586 int err;
1587 u16 ctl, mode;
cd28ab6a
SH		 1588
1589 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1590 return -EINVAL;
1591
5a5b1ea0
SH		 1592 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1593 return -EINVAL;
1594
6b1a3aef
SH		 1595 if (!netif_running(dev)) {
1596 dev->mtu = new_mtu;
1597 return 0;
1598 }
1599
6b1a3aef
SH		 1600 sky2_write32(hw, B0_IMSK, 0);
1601
018d1c66
SH		 1602 dev->trans_start = jiffies; /* prevent tx timeout */
1603 netif_stop_queue(dev);
1604 netif_poll_disable(hw->dev[0]);
1605
6b1a3aef
SH		 1606 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1607 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1608 sky2_rx_stop(sky2);
1609 sky2_rx_clean(sky2);
cd28ab6a
SH		 1610
1611 dev->mtu = new_mtu;
6b1a3aef
SH		 1612 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1613 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1614
1615 if (dev->mtu > ETH_DATA_LEN)
1616 mode |= GM_SMOD_JUMBO_ENA;
1617
1618 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1619
6b1a3aef 1620 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1621
6b1a3aef
SH		 1622 err = sky2_rx_start(sky2);
1623 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1624
018d1c66
SH		 1625 netif_poll_disable(hw->dev[0]);
1626 netif_wake_queue(dev);
6b1a3aef 1627 sky2_write32(hw, B0_IMSK, hw->intr_mask);
018d1c66 1628
cd28ab6a
SH		 1629 return err;
1630}
1631
1632/*
1633 * Receive one packet.
1634 * For small packets or errors, just reuse existing skb.
d571b694 1635 * For larger packets, get new buffer.
cd28ab6a 1636 */
d11c13e7 1637static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1638 u16 length, u32 status)
1639{
cd28ab6a 1640 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1641 struct sk_buff *skb = NULL;
6b1a3aef 1642 const unsigned int bufsize = rx_size(sky2);
cd28ab6a
SH		 1643
1644 if (unlikely(netif_msg_rx_status(sky2)))
1645 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1646 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1647
793b883e 1648 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
cd28ab6a 1649
42eeea01 1650 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1651 goto error;
1652
42eeea01
SH		 1653 if (!(status & GMR_FS_RX_OK))
1654 goto resubmit;
1655
793b883e 1656 if (length < RX_COPY_THRESHOLD) {
79e57d32
SH		 1657 skb = alloc_skb(length + 2, GFP_ATOMIC);
1658 if (!skb)
793b883e
SH		 1659 goto resubmit;
1660
79e57d32 1661 skb_reserve(skb, 2);
793b883e
SH		 1662 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1663 length, PCI_DMA_FROMDEVICE);
79e57d32 1664 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1665 skb->ip_summed = re->skb->ip_summed;
1666 skb->csum = re->skb->csum;
793b883e
SH		 1667 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1668 length, PCI_DMA_FROMDEVICE);
793b883e 1669 } else {
79e57d32
SH		 1670 struct sk_buff *nskb;
1671
1672 nskb = dev_alloc_skb(bufsize);
793b883e
SH		 1673 if (!nskb)
1674 goto resubmit;
cd28ab6a 1675
793b883e 1676 skb = re->skb;
79e57d32 1677 re->skb = nskb;
793b883e
SH		 1678 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1679 re->maplen, PCI_DMA_FROMDEVICE);
1680 prefetch(skb->data);
cd28ab6a 1681
793b883e 1682 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
79e57d32
SH		 1683 bufsize, PCI_DMA_FROMDEVICE);
1684 re->maplen = bufsize;
793b883e 1685 }
cd28ab6a 1686
79e57d32 1687 skb_put(skb, length);
793b883e 1688resubmit:
d11c13e7 1689 re->skb->ip_summed = CHECKSUM_NONE;
793b883e 1690 sky2_rx_add(sky2, re);
79e57d32 1691
bea86103
SH		 1692 /* Tell receiver about new buffers. */
1693 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1694 &sky2->rx_last_put, RX_LE_SIZE);
1695
cd28ab6a
SH		 1696 return skb;
1697
1698error:
1699 if (netif_msg_rx_err(sky2))
1700 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1701 sky2->netdev->name, status, length);
793b883e
SH		 1702
1703 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1704 sky2->net_stats.rx_length_errors++;
1705 if (status & GMR_FS_FRAGMENT)
1706 sky2->net_stats.rx_frame_errors++;
1707 if (status & GMR_FS_CRC_ERR)
1708 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1709 if (status & GMR_FS_RX_FF_OV)
1710 sky2->net_stats.rx_fifo_errors++;
79e57d32 1711
793b883e 1712 goto resubmit;
cd28ab6a
SH		 1713}
1714
2224795d
SH		 1715/*
1716 * Check for transmit complete
793b883e 1717 */
2224795d 1718static inline void sky2_tx_check(struct sky2_hw *hw, int port)
cd28ab6a 1719{
2224795d
SH		 1720 struct net_device *dev = hw->dev[port];
1721
1722 if (dev && netif_running(dev)) {
1723 sky2_tx_complete(netdev_priv(dev),
1724 sky2_read16(hw, port == 0
1725 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX));
1726 }
cd28ab6a
SH		 1727}
1728
1729/*
cd28ab6a
SH		 1730 * Both ports share the same status interrupt, therefore there is only
1731 * one poll routine.
cd28ab6a 1732 */
d11c13e7 1733static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1734{
d11c13e7
SH		 1735 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1736 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1737 unsigned int work_done = 0;
793b883e 1738 u16 hwidx;
cd28ab6a 1739
f89c2b46 1740 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
793b883e 1741 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1742 BUG_ON(hwidx >= STATUS_RING_SIZE);
793b883e 1743 rmb();
bea86103 1744
13210ce5
SH		 1745 while (hwidx != hw->st_idx) {
1746 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1747 struct net_device *dev;
d11c13e7 1748 struct sky2_port *sky2;
cd28ab6a 1749 struct sk_buff *skb;
cd28ab6a
SH		 1750 u32 status;
1751 u16 length;
13210ce5 1752 u8 op;
cd28ab6a 1753
13210ce5 1754 le = hw->st_le + hw->st_idx;
bea86103 1755 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
13210ce5 1756 prefetch(hw->st_le + hw->st_idx);
bea86103
SH		 1757
1758 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
d1f13708 1759
13210ce5
SH		 1760 BUG_ON(le->link >= 2);
1761 dev = hw->dev[le->link];
1762 if (dev == NULL || !netif_running(dev))
1763 continue;
1764
1765 sky2 = netdev_priv(dev);
cd28ab6a
SH		 1766 status = le32_to_cpu(le->status);
1767 length = le16_to_cpu(le->length);
13210ce5
SH		 1768 op = le->opcode & ~HW_OWNER;
1769 le->opcode = 0;
cd28ab6a 1770
13210ce5 1771 switch (op) {
cd28ab6a 1772 case OP_RXSTAT:
d11c13e7 1773 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1774 if (!skb)
1775 break;
13210ce5
SH		 1776
1777 skb->dev = dev;
1778 skb->protocol = eth_type_trans(skb, dev);
1779 dev->last_rx = jiffies;
1780
d1f13708
SH		 1781#ifdef SKY2_VLAN_TAG_USED
1782 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1783 vlan_hwaccel_receive_skb(skb,
1784 sky2->vlgrp,
1785 be16_to_cpu(sky2->rx_tag));
1786 } else
1787#endif
cd28ab6a 1788 netif_receive_skb(skb);
13210ce5
SH		 1789
1790 if (++work_done >= to_do)
1791 goto exit_loop;
cd28ab6a
SH		 1792 break;
1793
d1f13708
SH		 1794#ifdef SKY2_VLAN_TAG_USED
1795 case OP_RXVLAN:
1796 sky2->rx_tag = length;
1797 break;
1798
1799 case OP_RXCHKSVLAN:
1800 sky2->rx_tag = length;
1801 /* fall through */
1802#endif
cd28ab6a 1803 case OP_RXCHKS:
d11c13e7
SH		 1804 skb = sky2->rx_ring[sky2->rx_next].skb;
1805 skb->ip_summed = CHECKSUM_HW;
1806 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1807 break;
1808
1809 case OP_TXINDEXLE:
2224795d 1810 /* pick up transmit status later */
cd28ab6a
SH		 1811 break;
1812
cd28ab6a
SH		 1813 default:
1814 if (net_ratelimit())
793b883e 1815 printk(KERN_WARNING PFX
13210ce5 1816 "unknown status opcode 0x%x\n", op);
cd28ab6a
SH		 1817 break;
1818 }
13210ce5 1819 }
cd28ab6a 1820
13210ce5 1821exit_loop:
2224795d
SH		 1822 sky2_tx_check(hw, 0);
1823 sky2_tx_check(hw, 1);
cd28ab6a 1824
793b883e
SH		 1825 mmiowb();
1826
cd28ab6a
SH		 1827 if (work_done < to_do) {
1828 /*
1829 * Another chip workaround, need to restart TX timer if status
1830 * LE was handled. WA_DEV_43_418
1831 */
1832 if (is_ec_a1(hw)) {
1833 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1834 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1835 }
1836
bea86103 1837 netif_rx_complete(dev0);
cd28ab6a
SH		 1838 hw->intr_mask |= Y2_IS_STAT_BMU;
1839 sky2_write32(hw, B0_IMSK, hw->intr_mask);
13210ce5
SH		 1840 mmiowb();
1841 return 0;
1842 } else {
1843 *budget -= work_done;
1844 dev0->quota -= work_done;
1845 return 1;
cd28ab6a 1846 }
cd28ab6a
SH		 1847}
1848
1849static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1850{
1851 struct net_device *dev = hw->dev[port];
1852
1853 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1854 dev->name, status);
1855
1856 if (status & Y2_IS_PAR_RD1) {
1857 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1858 dev->name);
1859 /* Clear IRQ */
1860 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1861 }
1862
1863 if (status & Y2_IS_PAR_WR1) {
1864 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1865 dev->name);
1866
1867 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1868 }
1869
1870 if (status & Y2_IS_PAR_MAC1) {
1871 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1872 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1873 }
1874
1875 if (status & Y2_IS_PAR_RX1) {
1876 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1877 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1878 }
1879
1880 if (status & Y2_IS_TCP_TXA1) {
1881 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1882 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1883 }
1884}
1885
1886static void sky2_hw_intr(struct sky2_hw *hw)
1887{
1888 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1889
793b883e 1890 if (status & Y2_IS_TIST_OV)
cd28ab6a 1891 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1892
1893 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1894 u16 pci_err;
1895
1896 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
cd28ab6a
SH		 1897 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1898 pci_name(hw->pdev), pci_err);
1899
1900 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1901 pci_write_config_word(hw->pdev, PCI_STATUS,
1902 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1903 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1904 }
1905
1906 if (status & Y2_IS_PCI_EXP) {
d571b694 1907 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 1908 u32 pex_err;
1909
1910 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1911
cd28ab6a
SH		 1912 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1913 pci_name(hw->pdev), pex_err);
1914
1915 /* clear the interrupt */
1916 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1917 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1918 0xffffffffUL);
cd28ab6a
SH		 1919 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1920
1921 if (pex_err & PEX_FATAL_ERRORS) {
1922 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1923 hwmsk &= ~Y2_IS_PCI_EXP;
1924 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1925 }
1926 }
1927
1928 if (status & Y2_HWE_L1_MASK)
1929 sky2_hw_error(hw, 0, status);
1930 status >>= 8;
1931 if (status & Y2_HWE_L1_MASK)
1932 sky2_hw_error(hw, 1, status);
1933}
1934
1935static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1936{
1937 struct net_device *dev = hw->dev[port];
1938 struct sky2_port *sky2 = netdev_priv(dev);
1939 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1940
1941 if (netif_msg_intr(sky2))
1942 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1943 dev->name, status);
1944
1945 if (status & GM_IS_RX_FF_OR) {
1946 ++sky2->net_stats.rx_fifo_errors;
1947 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1948 }
1949
1950 if (status & GM_IS_TX_FF_UR) {
1951 ++sky2->net_stats.tx_fifo_errors;
1952 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1953 }
cd28ab6a
SH		 1954}
1955
1956static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1957{
1958 struct net_device *dev = hw->dev[port];
1959 struct sky2_port *sky2 = netdev_priv(dev);
1960
1961 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1962 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1963 tasklet_schedule(&sky2->phy_task);
1964}
1965
1966static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1967{
1968 struct sky2_hw *hw = dev_id;
bea86103 1969 struct net_device *dev0 = hw->dev[0];
cd28ab6a
SH		 1970 u32 status;
1971
1972 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 1973 if (status == 0 || status == ~0)
cd28ab6a
SH		 1974 return IRQ_NONE;
1975
1976 if (status & Y2_IS_HW_ERR)
1977 sky2_hw_intr(hw);
1978
793b883e 1979 /* Do NAPI for Rx and Tx status */
bea86103 1980 if (status & Y2_IS_STAT_BMU) {
cd28ab6a
SH		 1981 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1982 sky2_write32(hw, B0_IMSK, hw->intr_mask);
bea86103 1983
0a122576
SH		 1984 if (likely(__netif_rx_schedule_prep(dev0))) {
1985 prefetch(&hw->st_le[hw->st_idx]);
bea86103 1986 __netif_rx_schedule(dev0);
0a122576 1987 }
cd28ab6a
SH		 1988 }
1989
793b883e 1990 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 1991 sky2_phy_intr(hw, 0);
1992
1993 if (status & Y2_IS_IRQ_PHY2)
1994 sky2_phy_intr(hw, 1);
1995
1996 if (status & Y2_IS_IRQ_MAC1)
1997 sky2_mac_intr(hw, 0);
1998
1999 if (status & Y2_IS_IRQ_MAC2)
2000 sky2_mac_intr(hw, 1);
2001
cd28ab6a 2002 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 2003
2004 sky2_read32(hw, B0_IMSK);
2005
cd28ab6a
SH		 2006 return IRQ_HANDLED;
2007}
2008
2009#ifdef CONFIG_NET_POLL_CONTROLLER
2010static void sky2_netpoll(struct net_device *dev)
2011{
2012 struct sky2_port *sky2 = netdev_priv(dev);
2013
793b883e 2014 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2015}
2016#endif
2017
2018/* Chip internal frequency for clock calculations */
2019static inline u32 sky2_khz(const struct sky2_hw *hw)
2020{
793b883e 2021 switch (hw->chip_id) {
cd28ab6a 2022 case CHIP_ID_YUKON_EC:
5a5b1ea0 2023 case CHIP_ID_YUKON_EC_U:
cd28ab6a
SH		 2024 return 125000; /* 125 Mhz */
2025 case CHIP_ID_YUKON_FE:
2026 return 100000; /* 100 Mhz */
793b883e 2027 default: /* YUKON_XL */
cd28ab6a
SH		 2028 return 156000; /* 156 Mhz */
2029 }
2030}
2031
2032static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
2033{
2034 return sky2_khz(hw) * ms;
2035}
2036
2037static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2038{
793b883e 2039 return (sky2_khz(hw) * us) / 1000;
cd28ab6a
SH		 2040}
2041
2042static int sky2_reset(struct sky2_hw *hw)
2043{
5afa0a9c 2044 u32 ctst;
cd28ab6a
SH		 2045 u16 status;
2046 u8 t8, pmd_type;
2047 int i;
2048
2049 ctst = sky2_read32(hw, B0_CTST);
2050
2051 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2052 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2053 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2054 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2055 pci_name(hw->pdev), hw->chip_id);
2056 return -EOPNOTSUPP;
2057 }
2058
793b883e
SH		 2059 /* ring for status responses */
2060 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2061 &hw->st_dma);
2062 if (!hw->st_le)
2063 return -ENOMEM;
2064
cd28ab6a
SH		 2065 /* disable ASF */
2066 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2067 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2068 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2069 }
2070
2071 /* do a SW reset */
2072 sky2_write8(hw, B0_CTST, CS_RST_SET);
2073 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2074
2075 /* clear PCI errors, if any */
793b883e 2076 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 2077 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 2078 pci_write_config_word(hw->pdev, PCI_STATUS,
2079 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2080
2081 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2082
2083 /* clear any PEX errors */
2084 if (is_pciex(hw)) {
793b883e
SH		 2085 u16 lstat;
2086 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2087 0xffffffffUL);
2088 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 2089 }
2090
2091 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2092 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2093
2094 hw->ports = 1;
2095 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2096 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2097 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2098 ++hw->ports;
2099 }
2100 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2101
5afa0a9c 2102 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2103
2104 for (i = 0; i < hw->ports; i++) {
2105 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2106 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2107 }
2108
2109 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2110
793b883e
SH		 2111 /* Clear I2C IRQ noise */
2112 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2113
2114 /* turn off hardware timer (unused) */
2115 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2116 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2117
cd28ab6a
SH		 2118 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2119
793b883e 2120 /* Turn on descriptor polling (every 75us) */
cd28ab6a
SH		 2121 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2122 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2123
2124 /* Turn off receive timestamp */
2125 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2126 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2127
2128 /* enable the Tx Arbiters */
2129 for (i = 0; i < hw->ports; i++)
2130 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2131
2132 /* Initialize ram interface */
2133 for (i = 0; i < hw->ports; i++) {
793b883e 2134 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2135
2136 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2137 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2138 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2140 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2144 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2145 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2146 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2147 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2148 }
2149
cd28ab6a
SH		 2150 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2151
cd28ab6a
SH		 2152 spin_lock_bh(&hw->phy_lock);
2153 for (i = 0; i < hw->ports; i++)
2154 sky2_phy_reset(hw, i);
2155 spin_unlock_bh(&hw->phy_lock);
2156
cd28ab6a
SH		 2157 memset(hw->st_le, 0, STATUS_LE_BYTES);
2158 hw->st_idx = 0;
2159
2160 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2161 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2162
2163 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2164 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2165
2166 /* Set the list last index */
793b883e 2167 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2168
793b883e
SH		 2169 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
2170
2171 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2172 if (is_ec_a1(hw)) {
2173 /* WA for dev. #4.3 */
793b883e 2174 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2175
2176 /* set Status-FIFO watermark */
2177 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2178
2179 /* set Status-FIFO ISR watermark */
793b883e 2180 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
cd28ab6a 2181
cd28ab6a 2182 } else {
cd28ab6a
SH		 2183 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2184
2185 /* set Status-FIFO watermark */
2186 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2187
2188 /* set Status-FIFO ISR watermark */
2189 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2190 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2191
d571b694 2192 else /* WA dev 4.109 */
cd28ab6a
SH		 2193 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2194
2195 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2196 }
2197
793b883e 2198 /* enable status unit */
cd28ab6a
SH		 2199 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2200
2201 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2202 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2203 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2204
2205 return 0;
2206}
2207
2208static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2209{
2210 u32 modes;
2211 if (hw->copper) {
793b883e
SH		 2212 modes = SUPPORTED_10baseT_Half
2213 | SUPPORTED_10baseT_Full
2214 | SUPPORTED_100baseT_Half
2215 | SUPPORTED_100baseT_Full
2216 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2217
2218 if (hw->chip_id != CHIP_ID_YUKON_FE)
2219 modes |= SUPPORTED_1000baseT_Half
793b883e 2220 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2221 } else
2222 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2223 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2224 return modes;
2225}
2226
793b883e 2227static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2228{
2229 struct sky2_port *sky2 = netdev_priv(dev);
2230 struct sky2_hw *hw = sky2->hw;
2231
2232 ecmd->transceiver = XCVR_INTERNAL;
2233 ecmd->supported = sky2_supported_modes(hw);
2234 ecmd->phy_address = PHY_ADDR_MARV;
2235 if (hw->copper) {
2236 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2237 | SUPPORTED_10baseT_Full
2238 | SUPPORTED_100baseT_Half
2239 | SUPPORTED_100baseT_Full
2240 | SUPPORTED_1000baseT_Half
2241 | SUPPORTED_1000baseT_Full
2242 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2243 ecmd->port = PORT_TP;
2244 } else
2245 ecmd->port = PORT_FIBRE;
2246
2247 ecmd->advertising = sky2->advertising;
2248 ecmd->autoneg = sky2->autoneg;
2249 ecmd->speed = sky2->speed;
2250 ecmd->duplex = sky2->duplex;
2251 return 0;
2252}
2253
2254static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2255{
2256 struct sky2_port *sky2 = netdev_priv(dev);
2257 const struct sky2_hw *hw = sky2->hw;
2258 u32 supported = sky2_supported_modes(hw);
2259
2260 if (ecmd->autoneg == AUTONEG_ENABLE) {
2261 ecmd->advertising = supported;
2262 sky2->duplex = -1;
2263 sky2->speed = -1;
2264 } else {
2265 u32 setting;
2266
793b883e 2267 switch (ecmd->speed) {
cd28ab6a
SH		 2268 case SPEED_1000:
2269 if (ecmd->duplex == DUPLEX_FULL)
2270 setting = SUPPORTED_1000baseT_Full;
2271 else if (ecmd->duplex == DUPLEX_HALF)
2272 setting = SUPPORTED_1000baseT_Half;
2273 else
2274 return -EINVAL;
2275 break;
2276 case SPEED_100:
2277 if (ecmd->duplex == DUPLEX_FULL)
2278 setting = SUPPORTED_100baseT_Full;
2279 else if (ecmd->duplex == DUPLEX_HALF)
2280 setting = SUPPORTED_100baseT_Half;
2281 else
2282 return -EINVAL;
2283 break;
2284
2285 case SPEED_10:
2286 if (ecmd->duplex == DUPLEX_FULL)
2287 setting = SUPPORTED_10baseT_Full;
2288 else if (ecmd->duplex == DUPLEX_HALF)
2289 setting = SUPPORTED_10baseT_Half;
2290 else
2291 return -EINVAL;
2292 break;
2293 default:
2294 return -EINVAL;
2295 }
2296
2297 if ((setting & supported) == 0)
2298 return -EINVAL;
2299
2300 sky2->speed = ecmd->speed;
2301 sky2->duplex = ecmd->duplex;
2302 }
2303
2304 sky2->autoneg = ecmd->autoneg;
2305 sky2->advertising = ecmd->advertising;
2306
2307 if (netif_running(dev)) {
2308 sky2_down(dev);
2309 sky2_up(dev);
2310 }
2311
2312 return 0;
2313}
2314
2315static void sky2_get_drvinfo(struct net_device *dev,
2316 struct ethtool_drvinfo *info)
2317{
2318 struct sky2_port *sky2 = netdev_priv(dev);
2319
2320 strcpy(info->driver, DRV_NAME);
2321 strcpy(info->version, DRV_VERSION);
2322 strcpy(info->fw_version, "N/A");
2323 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2324}
2325
2326static const struct sky2_stat {
793b883e
SH		 2327 char name[ETH_GSTRING_LEN];
2328 u16 offset;
cd28ab6a
SH		 2329} sky2_stats[] = {
2330 { "tx_bytes", GM_TXO_OK_HI },
2331 { "rx_bytes", GM_RXO_OK_HI },
2332 { "tx_broadcast", GM_TXF_BC_OK },
2333 { "rx_broadcast", GM_RXF_BC_OK },
2334 { "tx_multicast", GM_TXF_MC_OK },
2335 { "rx_multicast", GM_RXF_MC_OK },
2336 { "tx_unicast", GM_TXF_UC_OK },
2337 { "rx_unicast", GM_RXF_UC_OK },
2338 { "tx_mac_pause", GM_TXF_MPAUSE },
2339 { "rx_mac_pause", GM_RXF_MPAUSE },
2340 { "collisions", GM_TXF_SNG_COL },
2341 { "late_collision",GM_TXF_LAT_COL },
2342 { "aborted", GM_TXF_ABO_COL },
2343 { "multi_collisions", GM_TXF_MUL_COL },
2344 { "fifo_underrun", GM_TXE_FIFO_UR },
2345 { "fifo_overflow", GM_RXE_FIFO_OV },
2346 { "rx_toolong", GM_RXF_LNG_ERR },
2347 { "rx_jabber", GM_RXF_JAB_PKT },
2348 { "rx_runt", GM_RXE_FRAG },
2349 { "rx_too_long", GM_RXF_LNG_ERR },
2350 { "rx_fcs_error", GM_RXF_FCS_ERR },
2351};
2352
cd28ab6a
SH		 2353static u32 sky2_get_rx_csum(struct net_device *dev)
2354{
2355 struct sky2_port *sky2 = netdev_priv(dev);
2356
2357 return sky2->rx_csum;
2358}
2359
2360static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2361{
2362 struct sky2_port *sky2 = netdev_priv(dev);
2363
2364 sky2->rx_csum = data;
793b883e 2365
cd28ab6a
SH		 2366 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2367 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2368
2369 return 0;
2370}
2371
2372static u32 sky2_get_msglevel(struct net_device *netdev)
2373{
2374 struct sky2_port *sky2 = netdev_priv(netdev);
2375 return sky2->msg_enable;
2376}
2377
9a7ae0a9
SH		 2378static int sky2_nway_reset(struct net_device *dev)
2379{
2380 struct sky2_port *sky2 = netdev_priv(dev);
2381 struct sky2_hw *hw = sky2->hw;
2382
2383 if (sky2->autoneg != AUTONEG_ENABLE)
2384 return -EINVAL;
2385
2386 netif_stop_queue(dev);
2387
2388 spin_lock_irq(&hw->phy_lock);
2389 sky2_phy_reset(hw, sky2->port);
2390 sky2_phy_init(hw, sky2->port);
2391 spin_unlock_irq(&hw->phy_lock);
2392
2393 return 0;
2394}
2395
793b883e 2396static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2397{
2398 struct sky2_hw *hw = sky2->hw;
2399 unsigned port = sky2->port;
2400 int i;
2401
2402 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2403 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2404 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2405 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2406
793b883e 2407 for (i = 2; i < count; i++)
cd28ab6a
SH		 2408 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2409}
2410
cd28ab6a
SH		 2411static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2412{
2413 struct sky2_port *sky2 = netdev_priv(netdev);
2414 sky2->msg_enable = value;
2415}
2416
2417static int sky2_get_stats_count(struct net_device *dev)
2418{
2419 return ARRAY_SIZE(sky2_stats);
2420}
2421
2422static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2423 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2424{
2425 struct sky2_port *sky2 = netdev_priv(dev);
2426
793b883e 2427 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2428}
2429
793b883e 2430static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2431{
2432 int i;
2433
2434 switch (stringset) {
2435 case ETH_SS_STATS:
2436 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2437 memcpy(data + i * ETH_GSTRING_LEN,
2438 sky2_stats[i].name, ETH_GSTRING_LEN);
2439 break;
2440 }
2441}
2442
2443/* Use hardware MIB variables for critical path statistics and
2444 * transmit feedback not reported at interrupt.
2445 * Other errors are accounted for in interrupt handler.
2446 */
2447static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2448{
2449 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2450 u64 data[13];
cd28ab6a 2451
793b883e 2452 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2453
2454 sky2->net_stats.tx_bytes = data[0];
2455 sky2->net_stats.rx_bytes = data[1];
2456 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2457 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2458 sky2->net_stats.multicast = data[5] + data[7];
2459 sky2->net_stats.collisions = data[10];
2460 sky2->net_stats.tx_aborted_errors = data[12];
2461
2462 return &sky2->net_stats;
2463}
2464
2465static int sky2_set_mac_address(struct net_device *dev, void *p)
2466{
2467 struct sky2_port *sky2 = netdev_priv(dev);
2468 struct sockaddr *addr = p;
2469 int err = 0;
2470
2471 if (!is_valid_ether_addr(addr->sa_data))
2472 return -EADDRNOTAVAIL;
2473
2474 sky2_down(dev);
2475 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2476 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2477 dev->dev_addr, ETH_ALEN);
793b883e 2478 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a
SH		 2479 dev->dev_addr, ETH_ALEN);
2480 if (dev->flags & IFF_UP)
2481 err = sky2_up(dev);
2482 return err;
2483}
2484
2485static void sky2_set_multicast(struct net_device *dev)
2486{
2487 struct sky2_port *sky2 = netdev_priv(dev);
2488 struct sky2_hw *hw = sky2->hw;
2489 unsigned port = sky2->port;
2490 struct dev_mc_list *list = dev->mc_list;
2491 u16 reg;
2492 u8 filter[8];
2493
2494 memset(filter, 0, sizeof(filter));
2495
2496 reg = gma_read16(hw, port, GM_RX_CTRL);
2497 reg |= GM_RXCR_UCF_ENA;
2498
d571b694 2499 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2500 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2501 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2502 memset(filter, 0xff, sizeof(filter));
793b883e 2503 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2504 reg &= ~GM_RXCR_MCF_ENA;
2505 else {
2506 int i;
2507 reg |= GM_RXCR_MCF_ENA;
2508
2509 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2510 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2511 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2512 }
2513 }
2514
cd28ab6a 2515 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2516 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2517 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2518 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2519 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2520 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2521 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2522 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2523
2524 gma_write16(hw, port, GM_RX_CTRL, reg);
2525}
2526
2527/* Can have one global because blinking is controlled by
2528 * ethtool and that is always under RTNL mutex
2529 */
2530static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2531{
793b883e
SH		 2532 u16 pg;
2533
cd28ab6a 2534 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2535 switch (hw->chip_id) {
2536 case CHIP_ID_YUKON_XL:
2537 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2539 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2540 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2541 PHY_M_LEDC_INIT_CTRL(7) |
2542 PHY_M_LEDC_STA1_CTRL(7) |
2543 PHY_M_LEDC_STA0_CTRL(7))
2544 : 0);
2545
2546 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2547 break;
2548
2549 default:
2550 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2551 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2552 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2553 PHY_M_LED_MO_10(MO_LED_ON) |
2554 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2555 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2556 PHY_M_LED_MO_RX(MO_LED_ON)
2557 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2558 PHY_M_LED_MO_10(MO_LED_OFF) |
2559 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2560 PHY_M_LED_MO_1000(MO_LED_OFF) |
2561 PHY_M_LED_MO_RX(MO_LED_OFF));
2562
793b883e 2563 }
cd28ab6a
SH		 2564 spin_unlock_bh(&hw->phy_lock);
2565}
2566
2567/* blink LED's for finding board */
2568static int sky2_phys_id(struct net_device *dev, u32 data)
2569{
2570 struct sky2_port *sky2 = netdev_priv(dev);
2571 struct sky2_hw *hw = sky2->hw;
2572 unsigned port = sky2->port;
793b883e 2573 u16 ledctrl, ledover = 0;
cd28ab6a
SH		 2574 long ms;
2575 int onoff = 1;
2576
793b883e 2577 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2578 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2579 else
2580 ms = data * 1000;
2581
2582 /* save initial values */
2583 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2584 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2585 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2587 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2589 } else {
2590 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2591 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2592 }
cd28ab6a
SH		 2593 spin_unlock_bh(&hw->phy_lock);
2594
2595 while (ms > 0) {
2596 sky2_led(hw, port, onoff);
2597 onoff = !onoff;
2598
2599 if (msleep_interruptible(250))
2600 break; /* interrupted */
2601 ms -= 250;
2602 }
2603
2604 /* resume regularly scheduled programming */
2605 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2606 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2607 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2609 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2611 } else {
2612 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2613 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2614 }
cd28ab6a
SH		 2615 spin_unlock_bh(&hw->phy_lock);
2616
2617 return 0;
2618}
2619
2620static void sky2_get_pauseparam(struct net_device *dev,
2621 struct ethtool_pauseparam *ecmd)
2622{
2623 struct sky2_port *sky2 = netdev_priv(dev);
2624
2625 ecmd->tx_pause = sky2->tx_pause;
2626 ecmd->rx_pause = sky2->rx_pause;
2627 ecmd->autoneg = sky2->autoneg;
2628}
2629
2630static int sky2_set_pauseparam(struct net_device *dev,
2631 struct ethtool_pauseparam *ecmd)
2632{
2633 struct sky2_port *sky2 = netdev_priv(dev);
2634 int err = 0;
2635
2636 sky2->autoneg = ecmd->autoneg;
2637 sky2->tx_pause = ecmd->tx_pause != 0;
2638 sky2->rx_pause = ecmd->rx_pause != 0;
2639
2640 if (netif_running(dev)) {
2641 sky2_down(dev);
2642 err = sky2_up(dev);
2643 }
2644
2645 return err;
2646}
2647
2648#ifdef CONFIG_PM
2649static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2650{
2651 struct sky2_port *sky2 = netdev_priv(dev);
2652
2653 wol->supported = WAKE_MAGIC;
2654 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2655}
2656
2657static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2658{
2659 struct sky2_port *sky2 = netdev_priv(dev);
2660 struct sky2_hw *hw = sky2->hw;
2661
2662 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2663 return -EOPNOTSUPP;
2664
2665 sky2->wol = wol->wolopts == WAKE_MAGIC;
2666
2667 if (sky2->wol) {
2668 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2669
2670 sky2_write16(hw, WOL_CTRL_STAT,
2671 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2672 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2673 } else
2674 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2675
2676 return 0;
2677}
2678#endif
2679
793b883e
SH		 2680static void sky2_get_ringparam(struct net_device *dev,
2681 struct ethtool_ringparam *ering)
2682{
2683 struct sky2_port *sky2 = netdev_priv(dev);
2684
2685 ering->rx_max_pending = RX_MAX_PENDING;
2686 ering->rx_mini_max_pending = 0;
2687 ering->rx_jumbo_max_pending = 0;
2688 ering->tx_max_pending = TX_RING_SIZE - 1;
2689
2690 ering->rx_pending = sky2->rx_pending;
2691 ering->rx_mini_pending = 0;
2692 ering->rx_jumbo_pending = 0;
2693 ering->tx_pending = sky2->tx_pending;
2694}
2695
2696static int sky2_set_ringparam(struct net_device *dev,
2697 struct ethtool_ringparam *ering)
2698{
2699 struct sky2_port *sky2 = netdev_priv(dev);
2700 int err = 0;
2701
2702 if (ering->rx_pending > RX_MAX_PENDING ||
2703 ering->rx_pending < 8 ||
2704 ering->tx_pending < MAX_SKB_TX_LE ||
2705 ering->tx_pending > TX_RING_SIZE - 1)
2706 return -EINVAL;
2707
2708 if (netif_running(dev))
2709 sky2_down(dev);
2710
2711 sky2->rx_pending = ering->rx_pending;
2712 sky2->tx_pending = ering->tx_pending;
2713
2714 if (netif_running(dev))
2715 err = sky2_up(dev);
2716
2717 return err;
2718}
2719
793b883e
SH		 2720static int sky2_get_regs_len(struct net_device *dev)
2721{
6e4cbb34 2722 return 0x4000;
793b883e
SH		 2723}
2724
2725/*
2726 * Returns copy of control register region
6e4cbb34 2727 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2728 */
2729static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2730 void *p)
2731{
2732 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2733 const void __iomem *io = sky2->hw->regs;
793b883e 2734
6e4cbb34 2735 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2736 regs->version = 1;
6e4cbb34 2737 memset(p, 0, regs->len);
793b883e 2738
6e4cbb34
SH		 2739 memcpy_fromio(p, io, B3_RAM_ADDR);
2740
2741 memcpy_fromio(p + B3_RI_WTO_R1,
2742 io + B3_RI_WTO_R1,
2743 regs->len - B3_RI_WTO_R1);
793b883e 2744}
cd28ab6a
SH		 2745
2746static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2747 .get_settings = sky2_get_settings,
2748 .set_settings = sky2_set_settings,
2749 .get_drvinfo = sky2_get_drvinfo,
2750 .get_msglevel = sky2_get_msglevel,
2751 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2752 .nway_reset = sky2_nway_reset,
793b883e
SH		 2753 .get_regs_len = sky2_get_regs_len,
2754 .get_regs = sky2_get_regs,
2755 .get_link = ethtool_op_get_link,
2756 .get_sg = ethtool_op_get_sg,
2757 .set_sg = ethtool_op_set_sg,
2758 .get_tx_csum = ethtool_op_get_tx_csum,
2759 .set_tx_csum = ethtool_op_set_tx_csum,
2760 .get_tso = ethtool_op_get_tso,
2761 .set_tso = ethtool_op_set_tso,
2762 .get_rx_csum = sky2_get_rx_csum,
2763 .set_rx_csum = sky2_set_rx_csum,
2764 .get_strings = sky2_get_strings,
2765 .get_ringparam = sky2_get_ringparam,
2766 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2767 .get_pauseparam = sky2_get_pauseparam,
2768 .set_pauseparam = sky2_set_pauseparam,
2769#ifdef CONFIG_PM
793b883e
SH		 2770 .get_wol = sky2_get_wol,
2771 .set_wol = sky2_set_wol,
cd28ab6a 2772#endif
793b883e 2773 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2774 .get_stats_count = sky2_get_stats_count,
2775 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2776 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2777};
2778
2779/* Initialize network device */
2780static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2781 unsigned port, int highmem)
2782{
2783 struct sky2_port *sky2;
2784 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2785
2786 if (!dev) {
2787 printk(KERN_ERR "sky2 etherdev alloc failed");
2788 return NULL;
2789 }
2790
2791 SET_MODULE_OWNER(dev);
2792 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2793 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 2794 dev->open = sky2_up;
2795 dev->stop = sky2_down;
ef743d33 2796 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 2797 dev->hard_start_xmit = sky2_xmit_frame;
2798 dev->get_stats = sky2_get_stats;
2799 dev->set_multicast_list = sky2_set_multicast;
2800 dev->set_mac_address = sky2_set_mac_address;
2801 dev->change_mtu = sky2_change_mtu;
2802 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2803 dev->tx_timeout = sky2_tx_timeout;
2804 dev->watchdog_timeo = TX_WATCHDOG;
2805 if (port == 0)
2806 dev->poll = sky2_poll;
2807 dev->weight = NAPI_WEIGHT;
2808#ifdef CONFIG_NET_POLL_CONTROLLER
2809 dev->poll_controller = sky2_netpoll;
2810#endif
cd28ab6a
SH		 2811
2812 sky2 = netdev_priv(dev);
2813 sky2->netdev = dev;
2814 sky2->hw = hw;
2815 sky2->msg_enable = netif_msg_init(debug, default_msg);
2816
2817 spin_lock_init(&sky2->tx_lock);
2818 /* Auto speed and flow control */
2819 sky2->autoneg = AUTONEG_ENABLE;
2820 sky2->tx_pause = 0;
2821 sky2->rx_pause = 1;
2822 sky2->duplex = -1;
2823 sky2->speed = -1;
2824 sky2->advertising = sky2_supported_modes(hw);
2825 sky2->rx_csum = 1;
793b883e
SH		 2826 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2827 sky2->tx_pending = TX_DEF_PENDING;
2828 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
cd28ab6a
SH		 2829
2830 hw->dev[port] = dev;
2831
2832 sky2->port = port;
2833
5a5b1ea0
SH		 2834 dev->features |= NETIF_F_LLTX;
2835 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2836 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 2837 if (highmem)
2838 dev->features |= NETIF_F_HIGHDMA;
793b883e 2839 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 2840
d1f13708
SH		 2841#ifdef SKY2_VLAN_TAG_USED
2842 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2843 dev->vlan_rx_register = sky2_vlan_rx_register;
2844 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2845#endif
2846
cd28ab6a 2847 /* read the mac address */
793b883e 2848 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 2849 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 2850
2851 /* device is off until link detection */
2852 netif_carrier_off(dev);
2853 netif_stop_queue(dev);
2854
2855 return dev;
2856}
2857
2858static inline void sky2_show_addr(struct net_device *dev)
2859{
2860 const struct sky2_port *sky2 = netdev_priv(dev);
2861
2862 if (netif_msg_probe(sky2))
2863 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2864 dev->name,
2865 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2866 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2867}
2868
2869static int __devinit sky2_probe(struct pci_dev *pdev,
2870 const struct pci_device_id *ent)
2871{
793b883e 2872 struct net_device *dev, *dev1 = NULL;
cd28ab6a 2873 struct sky2_hw *hw;
5afa0a9c 2874 int err, pm_cap, using_dac = 0;
cd28ab6a 2875
793b883e
SH		 2876 err = pci_enable_device(pdev);
2877 if (err) {
cd28ab6a
SH		 2878 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2879 pci_name(pdev));
2880 goto err_out;
2881 }
2882
793b883e
SH		 2883 err = pci_request_regions(pdev, DRV_NAME);
2884 if (err) {
cd28ab6a
SH		 2885 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2886 pci_name(pdev));
793b883e 2887 goto err_out;
cd28ab6a
SH		 2888 }
2889
2890 pci_set_master(pdev);
2891
5afa0a9c
SH		 2892 /* Find power-management capability. */
2893 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2894 if (pm_cap == 0) {
2895 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2896 "aborting.\n");
2897 err = -EIO;
2898 goto err_out_free_regions;
2899 }
2900
cd28ab6a
SH		 2901 if (sizeof(dma_addr_t) > sizeof(u32)) {
2902 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2903 if (!err)
2904 using_dac = 1;
2905 }
2906
2907 if (!using_dac) {
2908 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2909 if (err) {
2910 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2911 pci_name(pdev));
2912 goto err_out_free_regions;
2913 }
2914 }
cd28ab6a 2915#ifdef __BIG_ENDIAN
d571b694 2916 /* byte swap descriptors in hardware */
cd28ab6a
SH		 2917 {
2918 u32 reg;
2919
2920 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
2921 reg |= PCI_REV_DESC;
2922 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2923 }
2924#endif
2925
2926 err = -ENOMEM;
2927 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2928 if (!hw) {
2929 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2930 pci_name(pdev));
2931 goto err_out_free_regions;
2932 }
2933
2934 memset(hw, 0, sizeof(*hw));
2935 hw->pdev = pdev;
2936 spin_lock_init(&hw->phy_lock);
2937
2938 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2939 if (!hw->regs) {
2940 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2941 pci_name(pdev));
2942 goto err_out_free_hw;
2943 }
5afa0a9c 2944 hw->pm_cap = pm_cap;
cd28ab6a 2945
cd28ab6a
SH		 2946 err = sky2_reset(hw);
2947 if (err)
793b883e 2948 goto err_out_iounmap;
cd28ab6a 2949
5f4f9dc1
SH		 2950 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2951 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 2952 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 2953 hw->chip_id, hw->chip_rev);
cd28ab6a 2954
793b883e
SH		 2955 dev = sky2_init_netdev(hw, 0, using_dac);
2956 if (!dev)
cd28ab6a
SH		 2957 goto err_out_free_pci;
2958
793b883e
SH		 2959 err = register_netdev(dev);
2960 if (err) {
cd28ab6a
SH		 2961 printk(KERN_ERR PFX "%s: cannot register net device\n",
2962 pci_name(pdev));
2963 goto err_out_free_netdev;
2964 }
2965
2966 sky2_show_addr(dev);
2967
2968 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2969 if (register_netdev(dev1) == 0)
2970 sky2_show_addr(dev1);
2971 else {
2972 /* Failure to register second port need not be fatal */
793b883e
SH		 2973 printk(KERN_WARNING PFX
2974 "register of second port failed\n");
cd28ab6a
SH		 2975 hw->dev[1] = NULL;
2976 free_netdev(dev1);
2977 }
2978 }
2979
793b883e
SH		 2980 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2981 if (err) {
2982 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2983 pci_name(pdev), pdev->irq);
2984 goto err_out_unregister;
2985 }
2986
2987 hw->intr_mask = Y2_IS_BASE;
2988 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2989
2990 pci_set_drvdata(pdev, hw);
2991
cd28ab6a
SH		 2992 return 0;
2993
793b883e
SH		 2994err_out_unregister:
2995 if (dev1) {
2996 unregister_netdev(dev1);
2997 free_netdev(dev1);
2998 }
2999 unregister_netdev(dev);
cd28ab6a
SH		 3000err_out_free_netdev:
3001 free_netdev(dev);
cd28ab6a 3002err_out_free_pci:
793b883e 3003 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3004 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3005err_out_iounmap:
3006 iounmap(hw->regs);
3007err_out_free_hw:
3008 kfree(hw);
3009err_out_free_regions:
3010 pci_release_regions(pdev);
cd28ab6a 3011 pci_disable_device(pdev);
cd28ab6a
SH		 3012err_out:
3013 return err;
3014}
3015
3016static void __devexit sky2_remove(struct pci_dev *pdev)
3017{
793b883e 3018 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3019 struct net_device *dev0, *dev1;
3020
793b883e 3021 if (!hw)
cd28ab6a
SH		 3022 return;
3023
cd28ab6a 3024 dev0 = hw->dev[0];
793b883e
SH		 3025 dev1 = hw->dev[1];
3026 if (dev1)
3027 unregister_netdev(dev1);
cd28ab6a
SH		 3028 unregister_netdev(dev0);
3029
793b883e 3030 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 3031 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3032 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3033 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3034 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3035
3036 free_irq(pdev->irq, hw);
793b883e 3037 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3038 pci_release_regions(pdev);
3039 pci_disable_device(pdev);
793b883e 3040
cd28ab6a
SH		 3041 if (dev1)
3042 free_netdev(dev1);
3043 free_netdev(dev0);
3044 iounmap(hw->regs);
3045 kfree(hw);
5afa0a9c 3046
cd28ab6a
SH		 3047 pci_set_drvdata(pdev, NULL);
3048}
3049
3050#ifdef CONFIG_PM
3051static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3052{
793b883e 3053 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3054 int i;
cd28ab6a
SH		 3055
3056 for (i = 0; i < 2; i++) {
3057 struct net_device *dev = hw->dev[i];
3058
3059 if (dev) {
5afa0a9c
SH		 3060 if (!netif_running(dev))
3061 continue;
3062
3063 sky2_down(dev);
cd28ab6a 3064 netif_device_detach(dev);
cd28ab6a
SH		 3065 }
3066 }
3067
5afa0a9c 3068 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3069}
3070
3071static int sky2_resume(struct pci_dev *pdev)
3072{
793b883e 3073 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3074 int i;
3075
cd28ab6a
SH		 3076 pci_restore_state(pdev);
3077 pci_enable_wake(pdev, PCI_D0, 0);
5afa0a9c 3078 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 3079
3080 sky2_reset(hw);
3081
3082 for (i = 0; i < 2; i++) {
3083 struct net_device *dev = hw->dev[i];
3084 if (dev) {
5afa0a9c
SH		 3085 if (netif_running(dev)) {
3086 netif_device_attach(dev);
cd28ab6a 3087 sky2_up(dev);
5afa0a9c 3088 }
cd28ab6a
SH		 3089 }
3090 }
3091 return 0;
3092}
3093#endif
3094
3095static struct pci_driver sky2_driver = {
793b883e
SH		 3096 .name = DRV_NAME,
3097 .id_table = sky2_id_table,
3098 .probe = sky2_probe,
3099 .remove = __devexit_p(sky2_remove),
cd28ab6a 3100#ifdef CONFIG_PM
793b883e
SH		 3101 .suspend = sky2_suspend,
3102 .resume = sky2_resume,
cd28ab6a
SH		 3103#endif
3104};
3105
3106static int __init sky2_init_module(void)
3107{
50241c4c 3108 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3109}
3110
3111static void __exit sky2_cleanup_module(void)
3112{
3113 pci_unregister_driver(&sky2_driver);
3114}
3115
3116module_init(sky2_init_module);
3117module_exit(sky2_cleanup_module);
3118
3119MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3120MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3121MODULE_LICENSE("GPL");
5f4f9dc1 3122MODULE_VERSION(DRV_VERSION);
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