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[PATCH] sky2: don't lose multicast addresses
[mirror_ubuntu-zesty-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
cd28ab6a
SH		 27 * TOTEST
28 * - speed setting
724bca3c 29 * - suspend/resume
cd28ab6a
SH		 30 */
31
32#include <linux/config.h>
793b883e 33#include <linux/crc32.h>
cd28ab6a
SH		 34#include <linux/kernel.h>
35#include <linux/version.h>
36#include <linux/module.h>
37#include <linux/netdevice.h>
d0bbccfa 38#include <linux/dma-mapping.h>
cd28ab6a
SH		 39#include <linux/etherdevice.h>
40#include <linux/ethtool.h>
41#include <linux/pci.h>
42#include <linux/ip.h>
43#include <linux/tcp.h>
44#include <linux/in.h>
45#include <linux/delay.h>
91c86df5 46#include <linux/workqueue.h>
d1f13708 47#include <linux/if_vlan.h>
d70cd51a 48#include <linux/prefetch.h>
ef743d33 49#include <linux/mii.h>
cd28ab6a
SH		 50
51#include <asm/irq.h>
52
d1f13708
SH		 53#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
54#define SKY2_VLAN_TAG_USED 1
55#endif
56
cd28ab6a
SH		 57#include "sky2.h"
58
59#define DRV_NAME "sky2"
fed954da 60#define DRV_VERSION "0.10"
cd28ab6a
SH		 61#define PFX DRV_NAME " "
62
63/*
64 * The Yukon II chipset takes 64 bit command blocks (called list elements)
65 * that are organized into three (receive, transmit, status) different rings
66 * similar to Tigon3. A transmit can require several elements;
67 * a receive requires one (or two if using 64 bit dma).
68 */
69
cd28ab6a 70#define is_ec_a1(hw) \
21437643
SH		 71 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
72 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
cd28ab6a 73
13210ce5 74#define RX_LE_SIZE 512
cd28ab6a 75#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 76#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 77#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 78
79#define TX_RING_SIZE 512
80#define TX_DEF_PENDING (TX_RING_SIZE - 1)
81#define TX_MIN_PENDING 64
82#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 83
793b883e 84#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 85#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
86#define ETH_JUMBO_MTU 9000
87#define TX_WATCHDOG (5 * HZ)
88#define NAPI_WEIGHT 64
89#define PHY_RETRIES 1000
90
91static const u32 default_msg =
793b883e
SH		 92 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
93 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
94 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
cd28ab6a 95
793b883e 96static int debug = -1; /* defaults above */
cd28ab6a
SH		 97module_param(debug, int, 0);
98MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
99
bdb5c58e
SH		 100static int copybreak __read_mostly = 256;
101module_param(copybreak, int, 0);
102MODULE_PARM_DESC(copybreak, "Receive copy threshold");
103
cd28ab6a 104static const struct pci_device_id sky2_id_table[] = {
793b883e 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 124 { 0 }
125};
793b883e 126
cd28ab6a
SH		 127MODULE_DEVICE_TABLE(pci, sky2_id_table);
128
129/* Avoid conditionals by using array */
130static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
132
92f965e8
SH		 133/* This driver supports yukon2 chipset only */
134static const char *yukon2_name[] = {
135 "XL", /* 0xb3 */
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
138 "EC", /* 0xb6 */
139 "FE", /* 0xb7 */
793b883e
SH		 140};
141
793b883e 142/* Access to external PHY */
ef743d33 143static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 144{
145 int i;
146
147 gma_write16(hw, port, GM_SMI_DATA, val);
148 gma_write16(hw, port, GM_SMI_CTRL,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150
151 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 152 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 153 return 0;
793b883e 154 udelay(1);
cd28ab6a 155 }
ef743d33 156
793b883e 157 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 158 return -ETIMEDOUT;
cd28ab6a
SH		 159}
160
ef743d33 161static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 162{
163 int i;
164
793b883e 165 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 166 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167
168 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 169 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
170 *val = gma_read16(hw, port, GM_SMI_DATA);
171 return 0;
172 }
173
793b883e 174 udelay(1);
cd28ab6a
SH		 175 }
176
ef743d33
SH		 177 return -ETIMEDOUT;
178}
179
180static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
181{
182 u16 v;
183
184 if (__gm_phy_read(hw, port, reg, &v) != 0)
185 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
186 return v;
cd28ab6a
SH		 187}
188
5afa0a9c
SH		 189static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
190{
191 u16 power_control;
192 u32 reg1;
193 int vaux;
194 int ret = 0;
195
196 pr_debug("sky2_set_power_state %d\n", state);
197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198
199 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
200 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
201 (power_control & PCI_PM_CAP_PME_D3cold);
202
203 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
204
205 power_control |= PCI_PM_CTRL_PME_STATUS;
206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
207
208 switch (state) {
209 case PCI_D0:
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw, B0_POWER_CTRL,
212 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213
214 /* disable Core Clock Division, */
215 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216
217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 /* enable bits are inverted */
219 sky2_write8(hw, B2_Y2_CLK_GATE,
220 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 else
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225
226 /* Turn off phy power saving */
227 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229
d571b694 230 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
233 if (hw->ports > 1)
234 reg1 |= PCI_Y2_PHY2_COMA;
235 }
236 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
237 break;
238
239 case PCI_D3hot:
240 case PCI_D3cold:
241 /* Turn on phy power saving */
242 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
243 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
244 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
245 else
246 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
247 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
248
249 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
251 else
252 /* enable bits are inverted */
253 sky2_write8(hw, B2_Y2_CLK_GATE,
254 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
255 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
256 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
257
258 /* switch power to VAUX */
259 if (vaux && state != PCI_D3cold)
260 sky2_write8(hw, B0_POWER_CTRL,
261 (PC_VAUX_ENA | PC_VCC_ENA |
262 PC_VAUX_ON | PC_VCC_OFF));
263 break;
264 default:
265 printk(KERN_ERR PFX "Unknown power state %d\n", state);
266 ret = -1;
267 }
268
269 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
270 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
271 return ret;
272}
273
cd28ab6a
SH		 274static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
275{
276 u16 reg;
277
278 /* disable all GMAC IRQ's */
279 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
280 /* disable PHY IRQs */
281 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 282
cd28ab6a
SH		 283 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
284 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
285 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
287
288 reg = gma_read16(hw, port, GM_RX_CTRL);
289 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
290 gma_write16(hw, port, GM_RX_CTRL, reg);
291}
292
293static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
294{
295 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 296 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 297
793b883e 298 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 299 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
300
301 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 302 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 303 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
304
305 if (hw->chip_id == CHIP_ID_YUKON_EC)
306 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
307 else
308 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
309
310 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
311 }
312
313 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
314 if (hw->copper) {
315 if (hw->chip_id == CHIP_ID_YUKON_FE) {
316 /* enable automatic crossover */
317 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
318 } else {
319 /* disable energy detect */
320 ctrl &= ~PHY_M_PC_EN_DET_MSK;
321
322 /* enable automatic crossover */
323 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
324
325 if (sky2->autoneg == AUTONEG_ENABLE &&
326 hw->chip_id == CHIP_ID_YUKON_XL) {
327 ctrl &= ~PHY_M_PC_DSC_MSK;
328 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
329 }
330 }
331 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
332 } else {
333 /* workaround for deviation #4.88 (CRC errors) */
334 /* disable Automatic Crossover */
335
336 ctrl &= ~PHY_M_PC_MDIX_MSK;
337 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
338
339 if (hw->chip_id == CHIP_ID_YUKON_XL) {
340 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
341 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
342 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
343 ctrl &= ~PHY_M_MAC_MD_MSK;
344 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
345 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
346
347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
349 }
cd28ab6a
SH		 350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
353 if (sky2->autoneg == AUTONEG_DISABLE)
354 ctrl &= ~PHY_CT_ANE;
355 else
356 ctrl |= PHY_CT_ANE;
357
358 ctrl |= PHY_CT_RESET;
359 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
360
361 ctrl = 0;
362 ct1000 = 0;
363 adv = PHY_AN_CSMA;
364
365 if (sky2->autoneg == AUTONEG_ENABLE) {
366 if (hw->copper) {
367 if (sky2->advertising & ADVERTISED_1000baseT_Full)
368 ct1000 |= PHY_M_1000C_AFD;
369 if (sky2->advertising & ADVERTISED_1000baseT_Half)
370 ct1000 |= PHY_M_1000C_AHD;
371 if (sky2->advertising & ADVERTISED_100baseT_Full)
372 adv |= PHY_M_AN_100_FD;
373 if (sky2->advertising & ADVERTISED_100baseT_Half)
374 adv |= PHY_M_AN_100_HD;
375 if (sky2->advertising & ADVERTISED_10baseT_Full)
376 adv |= PHY_M_AN_10_FD;
377 if (sky2->advertising & ADVERTISED_10baseT_Half)
378 adv |= PHY_M_AN_10_HD;
793b883e 379 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 380 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
381
382 /* Set Flow-control capabilities */
383 if (sky2->tx_pause && sky2->rx_pause)
793b883e 384 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 385 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 386 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 387 else if (!sky2->rx_pause && sky2->tx_pause)
388 adv |= PHY_AN_PAUSE_ASYM; /* local */
389
390 /* Restart Auto-negotiation */
391 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
392 } else {
393 /* forced speed/duplex settings */
394 ct1000 = PHY_M_1000C_MSE;
395
396 if (sky2->duplex == DUPLEX_FULL)
397 ctrl |= PHY_CT_DUP_MD;
398
399 switch (sky2->speed) {
400 case SPEED_1000:
401 ctrl |= PHY_CT_SP1000;
402 break;
403 case SPEED_100:
404 ctrl |= PHY_CT_SP100;
405 break;
406 }
407
408 ctrl |= PHY_CT_RESET;
409 }
410
411 if (hw->chip_id != CHIP_ID_YUKON_FE)
412 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
413
414 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
415 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
416
417 /* Setup Phy LED's */
418 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
419 ledover = 0;
420
421 switch (hw->chip_id) {
422 case CHIP_ID_YUKON_FE:
423 /* on 88E3082 these bits are at 11..9 (shifted left) */
424 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
425
426 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
427
428 /* delete ACT LED control bits */
429 ctrl &= ~PHY_M_FELP_LED1_MSK;
430 /* change ACT LED control to blink mode */
431 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
432 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
433 break;
434
435 case CHIP_ID_YUKON_XL:
793b883e 436 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 437
438 /* select page 3 to access LED control register */
439 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
440
441 /* set LED Function Control register */
793b883e
SH		 442 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
443 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
444 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
445 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 446
447 /* set Polarity Control register */
448 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 449 (PHY_M_POLC_LS1_P_MIX(4) |
450 PHY_M_POLC_IS0_P_MIX(4) |
451 PHY_M_POLC_LOS_CTRL(2) |
452 PHY_M_POLC_INIT_CTRL(2) |
453 PHY_M_POLC_STA1_CTRL(2) |
454 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 455
456 /* restore page register */
793b883e 457 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 458 break;
459
460 default:
461 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
462 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
463 /* turn off the Rx LED (LED_RX) */
464 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
465 }
466
467 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
468
469 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
470 /* turn on 100 Mbps LED (LED_LINK100) */
471 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
472 }
473
474 if (ledover)
475 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
476
d571b694 477 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 478 if (sky2->autoneg == AUTONEG_ENABLE)
479 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
480 else
481 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
482}
483
1b537565
SH		 484/* Force a renegotiation */
485static void sky2_phy_reinit(struct sky2_port *sky2)
486{
487 down(&sky2->phy_sema);
488 sky2_phy_init(sky2->hw, sky2->port);
489 up(&sky2->phy_sema);
490}
491
cd28ab6a
SH		 492static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
493{
494 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
495 u16 reg;
496 int i;
497 const u8 *addr = hw->dev[port]->dev_addr;
498
42eeea01
SH		 499 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
500 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 501
502 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
503
793b883e 504 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 505 /* WA DEV_472 -- looks like crossed wires on port 2 */
506 /* clear GMAC 1 Control reset */
507 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
508 do {
509 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
510 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
511 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
512 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
513 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
514 }
515
cd28ab6a
SH		 516 if (sky2->autoneg == AUTONEG_DISABLE) {
517 reg = gma_read16(hw, port, GM_GP_CTRL);
518 reg |= GM_GPCR_AU_ALL_DIS;
519 gma_write16(hw, port, GM_GP_CTRL, reg);
520 gma_read16(hw, port, GM_GP_CTRL);
521
cd28ab6a
SH		 522 switch (sky2->speed) {
523 case SPEED_1000:
524 reg |= GM_GPCR_SPEED_1000;
525 /* fallthru */
526 case SPEED_100:
527 reg |= GM_GPCR_SPEED_100;
528 }
529
530 if (sky2->duplex == DUPLEX_FULL)
531 reg |= GM_GPCR_DUP_FULL;
532 } else
533 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
534
535 if (!sky2->tx_pause && !sky2->rx_pause) {
536 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 537 reg |=
538 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
539 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 540 /* disable Rx flow-control */
541 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
542 }
543
544 gma_write16(hw, port, GM_GP_CTRL, reg);
545
793b883e 546 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 547
91c86df5 548 down(&sky2->phy_sema);
cd28ab6a 549 sky2_phy_init(hw, port);
91c86df5 550 up(&sky2->phy_sema);
cd28ab6a
SH		 551
552 /* MIB clear */
553 reg = gma_read16(hw, port, GM_PHY_ADDR);
554 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
555
556 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 557 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 558 gma_write16(hw, port, GM_PHY_ADDR, reg);
559
560 /* transmit control */
561 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
562
563 /* receive control reg: unicast + multicast + no FCS */
564 gma_write16(hw, port, GM_RX_CTRL,
793b883e 565 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 566
567 /* transmit flow control */
568 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
569
570 /* transmit parameter */
571 gma_write16(hw, port, GM_TX_PARAM,
572 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
573 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
574 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
575 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
576
577 /* serial mode register */
578 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 579 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 580
6b1a3aef 581 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 582 reg |= GM_SMOD_JUMBO_ENA;
583
584 gma_write16(hw, port, GM_SERIAL_MODE, reg);
585
cd28ab6a
SH		 586 /* virtual address for data */
587 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
588
793b883e
SH		 589 /* physical address: used for pause frames */
590 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
591
592 /* ignore counter overflows */
cd28ab6a
SH		 593 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
594 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
595 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
596
597 /* Configure Rx MAC FIFO */
598 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 599 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 600 GMF_RX_CTRL_DEF);
cd28ab6a 601
d571b694 602 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 603 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 604
793b883e
SH		 605 /* Set threshold to 0xa (64 bytes)
606 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 607 */
608 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
609
610 /* Configure Tx MAC FIFO */
611 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
612 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 613
614 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
615 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
616 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
617 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
618 /* set Tx GMAC FIFO Almost Empty Threshold */
619 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
620 /* Disable Store & Forward mode for TX */
621 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
622 }
623 }
624
cd28ab6a
SH		 625}
626
627static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
628{
629 u32 end;
630
631 start /= 8;
632 len /= 8;
633 end = start + len - 1;
793b883e 634
cd28ab6a
SH		 635 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
636 sky2_write32(hw, RB_ADDR(q, RB_START), start);
637 sky2_write32(hw, RB_ADDR(q, RB_END), end);
638 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
639 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
640
641 if (q == Q_R1 || q == Q_R2) {
793b883e
SH		 642 u32 rxup, rxlo;
643
644 rxlo = len/2;
645 rxup = rxlo + len/4;
793b883e 646
cd28ab6a 647 /* Set thresholds on receive queue's */
793b883e
SH		 648 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
649 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
cd28ab6a
SH		 650 } else {
651 /* Enable store & forward on Tx queue's because
652 * Tx FIFO is only 1K on Yukon
653 */
654 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
655 }
656
657 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 658 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 659}
660
cd28ab6a 661/* Setup Bus Memory Interface */
af4ed7e6 662static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 663{
664 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
665 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
666 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 667 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 668}
669
cd28ab6a
SH		 670/* Setup prefetch unit registers. This is the interface between
671 * hardware and driver list elements
672 */
8cc048e3 673static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 674 u64 addr, u32 last)
675{
cd28ab6a
SH		 676 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
677 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
678 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
679 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
680 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
681 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 682
683 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 684}
685
793b883e
SH		 686static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
687{
688 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
689
690 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
691 return le;
692}
cd28ab6a
SH		 693
694/*
d571b694 695 * This is a workaround code taken from SysKonnect sk98lin driver
793b883e 696 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a
SH		 697 */
698static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
699 u16 idx, u16 *last, u16 size)
cd28ab6a 700{
cd28ab6a
SH		 701 if (is_ec_a1(hw) && idx < *last) {
702 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
703
704 if (hwget == 0) {
705 /* Start prefetching again */
793b883e 706 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 707 goto setnew;
708 }
709
793b883e 710 if (hwget == size - 1) {
cd28ab6a
SH		 711 /* set watermark to one list element */
712 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
713
714 /* set put index to first list element */
715 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 716 } else /* have hardware go to end of list */
717 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
718 size - 1);
cd28ab6a 719 } else {
793b883e 720setnew:
cd28ab6a 721 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 722 }
bea86103 723 *last = idx;
cd28ab6a
SH		 724}
725
793b883e 726
cd28ab6a
SH		 727static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
728{
729 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
730 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
731 return le;
732}
733
a018e330
SH		 734/* Return high part of DMA address (could be 32 or 64 bit) */
735static inline u32 high32(dma_addr_t a)
736{
737 return (a >> 16) >> 16;
738}
739
793b883e 740/* Build description to hardware about buffer */
734d1868 741static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 742{
743 struct sky2_rx_le *le;
734d1868
SH		 744 u32 hi = high32(map);
745 u16 len = sky2->rx_bufsize;
cd28ab6a 746
793b883e 747 if (sky2->rx_addr64 != hi) {
cd28ab6a 748 le = sky2_next_rx(sky2);
793b883e 749 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 750 le->ctrl = 0;
751 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 752 sky2->rx_addr64 = high32(map + len);
cd28ab6a 753 }
793b883e 754
cd28ab6a 755 le = sky2_next_rx(sky2);
734d1868
SH		 756 le->addr = cpu_to_le32((u32) map);
757 le->length = cpu_to_le16(len);
cd28ab6a
SH		 758 le->ctrl = 0;
759 le->opcode = OP_PACKET | HW_OWNER;
760}
761
793b883e 762
cd28ab6a
SH		 763/* Tell chip where to start receive checksum.
764 * Actually has two checksums, but set both same to avoid possible byte
765 * order problems.
766 */
793b883e 767static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 768{
769 struct sky2_rx_le *le;
770
cd28ab6a 771 le = sky2_next_rx(sky2);
793b883e 772 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 773 le->ctrl = 0;
774 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 775
793b883e
SH		 776 sky2_write32(sky2->hw,
777 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
778 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 779
780}
781
6b1a3aef
SH		 782/*
783 * The RX Stop command will not work for Yukon-2 if the BMU does not
784 * reach the end of packet and since we can't make sure that we have
785 * incoming data, we must reset the BMU while it is not doing a DMA
786 * transfer. Since it is possible that the RX path is still active,
787 * the RX RAM buffer will be stopped first, so any possible incoming
788 * data will not trigger a DMA. After the RAM buffer is stopped, the
789 * BMU is polled until any DMA in progress is ended and only then it
790 * will be reset.
791 */
792static void sky2_rx_stop(struct sky2_port *sky2)
793{
794 struct sky2_hw *hw = sky2->hw;
795 unsigned rxq = rxqaddr[sky2->port];
796 int i;
797
798 /* disable the RAM Buffer receive queue */
799 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
800
801 for (i = 0; i < 0xffff; i++)
802 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
803 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
804 goto stopped;
805
806 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
807 sky2->netdev->name);
808stopped:
809 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
810
811 /* reset the Rx prefetch unit */
812 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
813}
793b883e 814
d571b694 815/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 816static void sky2_rx_clean(struct sky2_port *sky2)
817{
818 unsigned i;
819
820 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 821 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 822 struct ring_info *re = sky2->rx_ring + i;
823
824 if (re->skb) {
793b883e 825 pci_unmap_single(sky2->hw->pdev,
734d1868 826 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 827 PCI_DMA_FROMDEVICE);
828 kfree_skb(re->skb);
829 re->skb = NULL;
830 }
831 }
832}
833
ef743d33
SH		 834/* Basic MII support */
835static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
836{
837 struct mii_ioctl_data *data = if_mii(ifr);
838 struct sky2_port *sky2 = netdev_priv(dev);
839 struct sky2_hw *hw = sky2->hw;
840 int err = -EOPNOTSUPP;
841
842 if (!netif_running(dev))
843 return -ENODEV; /* Phy still in reset */
844
845 switch(cmd) {
846 case SIOCGMIIPHY:
847 data->phy_id = PHY_ADDR_MARV;
848
849 /* fallthru */
850 case SIOCGMIIREG: {
851 u16 val = 0;
91c86df5
SH		 852
853 down(&sky2->phy_sema);
ef743d33 854 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
91c86df5
SH		 855 up(&sky2->phy_sema);
856
ef743d33
SH		 857 data->val_out = val;
858 break;
859 }
860
861 case SIOCSMIIREG:
862 if (!capable(CAP_NET_ADMIN))
863 return -EPERM;
864
91c86df5 865 down(&sky2->phy_sema);
ef743d33
SH		 866 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
867 data->val_in);
91c86df5 868 up(&sky2->phy_sema);
ef743d33
SH		 869 break;
870 }
871 return err;
872}
873
d1f13708
SH		 874#ifdef SKY2_VLAN_TAG_USED
875static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
876{
877 struct sky2_port *sky2 = netdev_priv(dev);
878 struct sky2_hw *hw = sky2->hw;
879 u16 port = sky2->port;
d1f13708 880
f2e46561 881 spin_lock(&sky2->tx_lock);
d1f13708
SH		 882
883 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
884 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
885 sky2->vlgrp = grp;
886
f2e46561 887 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 888}
889
890static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
891{
892 struct sky2_port *sky2 = netdev_priv(dev);
893 struct sky2_hw *hw = sky2->hw;
894 u16 port = sky2->port;
d1f13708 895
f2e46561 896 spin_lock(&sky2->tx_lock);
d1f13708
SH		 897
898 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
899 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
900 if (sky2->vlgrp)
901 sky2->vlgrp->vlan_devices[vid] = NULL;
902
f2e46561 903 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 904}
905#endif
906
cd28ab6a
SH		 907/*
908 * Allocate and setup receiver buffer pool.
909 * In case of 64 bit dma, there are 2X as many list elements
910 * available as ring entries
911 * and need to reserve one list element so we don't wrap around.
79e57d32
SH		 912 *
913 * It appears the hardware has a bug in the FIFO logic that
914 * cause it to hang if the FIFO gets overrun and the receive buffer
915 * is not aligned. This means we can't use skb_reserve to align
916 * the IP header.
cd28ab6a 917 */
6b1a3aef 918static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 919{
6b1a3aef 920 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 921 unsigned rxq = rxqaddr[sky2->port];
922 int i;
cd28ab6a 923
6b1a3aef 924 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 925 sky2_qset(hw, rxq);
6b1a3aef
SH		 926 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
927
928 rx_set_checksum(sky2);
793b883e 929 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 930 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 931
734d1868 932 re->skb = dev_alloc_skb(sky2->rx_bufsize);
cd28ab6a
SH		 933 if (!re->skb)
934 goto nomem;
935
6b1a3aef 936 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 937 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
938 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 939 }
940
6b1a3aef
SH		 941 /* Tell chip about available buffers */
942 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
943 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 944 return 0;
945nomem:
946 sky2_rx_clean(sky2);
947 return -ENOMEM;
948}
949
950/* Bring up network interface. */
951static int sky2_up(struct net_device *dev)
952{
953 struct sky2_port *sky2 = netdev_priv(dev);
954 struct sky2_hw *hw = sky2->hw;
955 unsigned port = sky2->port;
956 u32 ramsize, rxspace;
957 int err = -ENOMEM;
958
959 if (netif_msg_ifup(sky2))
960 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
961
962 /* must be power of 2 */
963 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 964 TX_RING_SIZE *
965 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 966 &sky2->tx_le_map);
967 if (!sky2->tx_le)
968 goto err_out;
969
6cdbbdf3 970 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 971 GFP_KERNEL);
972 if (!sky2->tx_ring)
973 goto err_out;
974 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 975
976 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
977 &sky2->rx_le_map);
978 if (!sky2->rx_le)
979 goto err_out;
980 memset(sky2->rx_le, 0, RX_LE_BYTES);
981
6cdbbdf3 982 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 983 GFP_KERNEL);
984 if (!sky2->rx_ring)
985 goto err_out;
986
987 sky2_mac_init(hw, port);
988
989 /* Configure RAM buffers */
990 if (hw->chip_id == CHIP_ID_YUKON_FE ||
991 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
992 ramsize = 4096;
993 else {
793b883e
SH		 994 u8 e0 = sky2_read8(hw, B2_E_0);
995 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
cd28ab6a
SH		 996 }
997
998 /* 2/3 for Rx */
999 rxspace = (2 * ramsize) / 3;
1000 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1001 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1002
793b883e
SH		 1003 /* Make sure SyncQ is disabled */
1004 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1005 RB_RST_SET);
1006
af4ed7e6 1007 sky2_qset(hw, txqaddr[port]);
5a5b1ea0
SH		 1008 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1009 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1010
1011
6b1a3aef
SH		 1012 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1013 TX_RING_SIZE - 1);
cd28ab6a 1014
6b1a3aef 1015 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1016 if (err)
1017 goto err_out;
1018
cd28ab6a
SH		 1019 /* Enable interrupts from phy/mac for port */
1020 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1021 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1022 return 0;
1023
1024err_out:
1b537565 1025 if (sky2->rx_le) {
cd28ab6a
SH		 1026 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1027 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1028 sky2->rx_le = NULL;
1029 }
1030 if (sky2->tx_le) {
cd28ab6a
SH		 1031 pci_free_consistent(hw->pdev,
1032 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1033 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1034 sky2->tx_le = NULL;
1035 }
1036 kfree(sky2->tx_ring);
1037 kfree(sky2->rx_ring);
cd28ab6a 1038
1b537565
SH		 1039 sky2->tx_ring = NULL;
1040 sky2->rx_ring = NULL;
cd28ab6a
SH		 1041 return err;
1042}
1043
793b883e
SH		 1044/* Modular subtraction in ring */
1045static inline int tx_dist(unsigned tail, unsigned head)
1046{
129372d0 1047 return (head - tail) % TX_RING_SIZE;
793b883e 1048}
cd28ab6a 1049
793b883e
SH		 1050/* Number of list elements available for next tx */
1051static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1052{
793b883e 1053 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1054}
1055
793b883e
SH		 1056/* Estimate of number of transmit list elements required */
1057static inline unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1058{
793b883e
SH		 1059 unsigned count;
1060
1061 count = sizeof(dma_addr_t) / sizeof(u32);
1062 count += skb_shinfo(skb)->nr_frags * count;
1063
1064 if (skb_shinfo(skb)->tso_size)
1065 ++count;
1066
0e3ff6aa 1067 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1068 ++count;
1069
1070 return count;
cd28ab6a
SH		 1071}
1072
793b883e
SH		 1073/*
1074 * Put one packet in ring for transmit.
1075 * A single packet can generate multiple list elements, and
1076 * the number of ring elements will probably be less than the number
1077 * of list elements used.
f2e46561
SH		 1078 *
1079 * No BH disabling for tx_lock here (like tg3)
793b883e 1080 */
cd28ab6a
SH		 1081static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1082{
1083 struct sky2_port *sky2 = netdev_priv(dev);
1084 struct sky2_hw *hw = sky2->hw;
d1f13708 1085 struct sky2_tx_le *le = NULL;
6cdbbdf3 1086 struct tx_ring_info *re;
cd28ab6a
SH		 1087 unsigned i, len;
1088 dma_addr_t mapping;
1089 u32 addr64;
1090 u16 mss;
1091 u8 ctrl;
1092
f2e46561 1093 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1094 return NETDEV_TX_LOCKED;
1095
793b883e 1096 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1097 /* There is a known but harmless race with lockless tx
1098 * and netif_stop_queue.
1099 */
1100 if (!netif_queue_stopped(dev)) {
1101 netif_stop_queue(dev);
1102 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1103 dev->name);
1104 }
f2e46561 1105 spin_unlock(&sky2->tx_lock);
cd28ab6a 1106
cd28ab6a
SH		 1107 return NETDEV_TX_BUSY;
1108 }
1109
793b883e 1110 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1111 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1112 dev->name, sky2->tx_prod, skb->len);
1113
cd28ab6a
SH		 1114 len = skb_headlen(skb);
1115 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1116 addr64 = high32(mapping);
793b883e
SH		 1117
1118 re = sky2->tx_ring + sky2->tx_prod;
1119
a018e330
SH		 1120 /* Send high bits if changed or crosses boundary */
1121 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1122 le = get_tx_le(sky2);
1123 le->tx.addr = cpu_to_le32(addr64);
1124 le->ctrl = 0;
1125 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1126 sky2->tx_addr64 = high32(mapping + len);
793b883e 1127 }
cd28ab6a
SH		 1128
1129 /* Check for TCP Segmentation Offload */
1130 mss = skb_shinfo(skb)->tso_size;
793b883e 1131 if (mss != 0) {
cd28ab6a
SH		 1132 /* just drop the packet if non-linear expansion fails */
1133 if (skb_header_cloned(skb) &&
1134 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1135 dev_kfree_skb_any(skb);
1136 goto out_unlock;
cd28ab6a
SH		 1137 }
1138
1139 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1140 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1141 mss += ETH_HLEN;
793b883e 1142 }
cd28ab6a 1143
793b883e 1144 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1145 le = get_tx_le(sky2);
1146 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1147 le->tx.tso.rsvd = 0;
cd28ab6a 1148 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1149 le->ctrl = 0;
793b883e 1150 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1151 }
1152
cd28ab6a 1153 ctrl = 0;
d1f13708
SH		 1154#ifdef SKY2_VLAN_TAG_USED
1155 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1156 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1157 if (!le) {
1158 le = get_tx_le(sky2);
1159 le->tx.addr = 0;
1160 le->opcode = OP_VLAN|HW_OWNER;
1161 le->ctrl = 0;
1162 } else
1163 le->opcode |= OP_VLAN;
1164 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1165 ctrl |= INS_VLAN;
1166 }
1167#endif
1168
1169 /* Handle TCP checksum offload */
cd28ab6a 1170 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1171 u16 hdr = skb->h.raw - skb->data;
1172 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1173
1174 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1175 if (skb->nh.iph->protocol == IPPROTO_UDP)
1176 ctrl |= UDPTCP;
1177
1178 le = get_tx_le(sky2);
1179 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1180 le->tx.csum.offset = cpu_to_le16(offset);
1181 le->length = 0; /* initial checksum value */
cd28ab6a 1182 le->ctrl = 1; /* one packet */
793b883e 1183 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1184 }
1185
1186 le = get_tx_le(sky2);
1187 le->tx.addr = cpu_to_le32((u32) mapping);
1188 le->length = cpu_to_le16(len);
1189 le->ctrl = ctrl;
793b883e 1190 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1191
793b883e 1192 /* Record the transmit mapping info */
cd28ab6a 1193 re->skb = skb;
6cdbbdf3 1194 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1195
1196 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1197 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1198 struct tx_ring_info *fre;
cd28ab6a
SH		 1199
1200 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1201 frag->size, PCI_DMA_TODEVICE);
793b883e
SH		 1202 addr64 = (mapping >> 16) >> 16;
1203 if (addr64 != sky2->tx_addr64) {
1204 le = get_tx_le(sky2);
1205 le->tx.addr = cpu_to_le32(addr64);
1206 le->ctrl = 0;
1207 le->opcode = OP_ADDR64 | HW_OWNER;
1208 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1209 }
1210
1211 le = get_tx_le(sky2);
1212 le->tx.addr = cpu_to_le32((u32) mapping);
1213 le->length = cpu_to_le16(frag->size);
1214 le->ctrl = ctrl;
793b883e 1215 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1216
793b883e
SH		 1217 fre = sky2->tx_ring
1218 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
6cdbbdf3 1219 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1220 }
6cdbbdf3 1221
793b883e 1222 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1223 le->ctrl |= EOP;
1224
724bca3c 1225 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
cd28ab6a
SH		 1226 &sky2->tx_last_put, TX_RING_SIZE);
1227
0e3ff6aa 1228 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
cd28ab6a 1229 netif_stop_queue(dev);
793b883e
SH		 1230
1231out_unlock:
1232 mmiowb();
f2e46561 1233 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1234
1235 dev->trans_start = jiffies;
1236 return NETDEV_TX_OK;
1237}
1238
cd28ab6a 1239/*
793b883e
SH		 1240 * Free ring elements from starting at tx_cons until "done"
1241 *
1242 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1243 * buffers; these are deferred until completion.
cd28ab6a 1244 */
d11c13e7 1245static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1246{
d11c13e7 1247 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1248 struct pci_dev *pdev = sky2->hw->pdev;
1249 u16 nxt, put;
793b883e 1250 unsigned i;
cd28ab6a 1251
0e3ff6aa 1252 BUG_ON(done >= TX_RING_SIZE);
2224795d 1253
d11c13e7 1254 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1255 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1256 dev->name, done);
cd28ab6a 1257
af2a58ac
SH		 1258 for (put = sky2->tx_cons; put != done; put = nxt) {
1259 struct tx_ring_info *re = sky2->tx_ring + put;
1260 struct sk_buff *skb = re->skb;
cd28ab6a 1261
af2a58ac
SH		 1262 nxt = re->idx;
1263 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1264 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1265
793b883e 1266 /* Check for partial status */
af2a58ac
SH		 1267 if (tx_dist(put, done) < tx_dist(put, nxt))
1268 break;
793b883e
SH		 1269
1270 skb = re->skb;
af2a58ac 1271 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1272 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1273
1274 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1275 struct tx_ring_info *fre;
af2a58ac
SH		 1276 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1277 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1278 skb_shinfo(skb)->frags[i].size,
734d1868 1279 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1280 }
1281
cd28ab6a 1282 dev_kfree_skb_any(skb);
793b883e 1283 }
793b883e 1284
af2a58ac
SH		 1285 spin_lock(&sky2->tx_lock);
1286 sky2->tx_cons = put;
793b883e 1287 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1288 netif_wake_queue(dev);
1289 spin_unlock(&sky2->tx_lock);
1290}
1291
1292/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1293static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1294{
d11c13e7 1295 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1296}
1297
1298/* Network shutdown */
1299static int sky2_down(struct net_device *dev)
1300{
1301 struct sky2_port *sky2 = netdev_priv(dev);
1302 struct sky2_hw *hw = sky2->hw;
1303 unsigned port = sky2->port;
1304 u16 ctrl;
cd28ab6a 1305
1b537565
SH		 1306 /* Never really got started! */
1307 if (!sky2->tx_le)
1308 return 0;
1309
cd28ab6a
SH		 1310 if (netif_msg_ifdown(sky2))
1311 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1312
018d1c66 1313 /* Stop more packets from being queued */
cd28ab6a
SH		 1314 netif_stop_queue(dev);
1315
018d1c66
SH		 1316 /* Disable port IRQ */
1317 local_irq_disable();
1318 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1319 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1320 local_irq_enable();
1321
91c86df5 1322 flush_scheduled_work();
018d1c66 1323
793b883e
SH		 1324 sky2_phy_reset(hw, port);
1325
cd28ab6a
SH		 1326 /* Stop transmitter */
1327 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1328 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1329
1330 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1331 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1332
1333 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1334 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1335 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1336
1337 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1338
1339 /* Workaround shared GMAC reset */
793b883e
SH		 1340 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1341 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1342 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1343
1344 /* Disable Force Sync bit and Enable Alloc bit */
1345 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1346 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1347
1348 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1349 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1350 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1351
1352 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1353 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1354 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1355
1356 /* Reset the Tx prefetch units */
1357 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1358 PREF_UNIT_RST_SET);
1359
1360 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1361
6b1a3aef 1362 sky2_rx_stop(sky2);
cd28ab6a
SH		 1363
1364 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1365 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1366
d571b694 1367 /* turn off LED's */
cd28ab6a
SH		 1368 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1369
018d1c66
SH		 1370 synchronize_irq(hw->pdev->irq);
1371
cd28ab6a
SH		 1372 sky2_tx_clean(sky2);
1373 sky2_rx_clean(sky2);
1374
1375 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1376 sky2->rx_le, sky2->rx_le_map);
1377 kfree(sky2->rx_ring);
1378
1379 pci_free_consistent(hw->pdev,
1380 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1381 sky2->tx_le, sky2->tx_le_map);
1382 kfree(sky2->tx_ring);
1383
1b537565
SH		 1384 sky2->tx_le = NULL;
1385 sky2->rx_le = NULL;
1386
1387 sky2->rx_ring = NULL;
1388 sky2->tx_ring = NULL;
1389
cd28ab6a
SH		 1390 return 0;
1391}
1392
1393static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1394{
793b883e
SH		 1395 if (!hw->copper)
1396 return SPEED_1000;
1397
cd28ab6a
SH		 1398 if (hw->chip_id == CHIP_ID_YUKON_FE)
1399 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1400
1401 switch (aux & PHY_M_PS_SPEED_MSK) {
1402 case PHY_M_PS_SPEED_1000:
1403 return SPEED_1000;
1404 case PHY_M_PS_SPEED_100:
1405 return SPEED_100;
1406 default:
1407 return SPEED_10;
1408 }
1409}
1410
1411static void sky2_link_up(struct sky2_port *sky2)
1412{
1413 struct sky2_hw *hw = sky2->hw;
1414 unsigned port = sky2->port;
1415 u16 reg;
1416
1417 /* Enable Transmit FIFO Underrun */
793b883e 1418 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1419
1420 reg = gma_read16(hw, port, GM_GP_CTRL);
1421 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1422 reg |= GM_GPCR_DUP_FULL;
1423
cd28ab6a
SH		 1424 /* enable Rx/Tx */
1425 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1426 gma_write16(hw, port, GM_GP_CTRL, reg);
1427 gma_read16(hw, port, GM_GP_CTRL);
1428
1429 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1430
1431 netif_carrier_on(sky2->netdev);
1432 netif_wake_queue(sky2->netdev);
1433
1434 /* Turn on link LED */
793b883e 1435 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1436 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1437
793b883e
SH		 1438 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1439 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1440
1441 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1442 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1443 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1444 SPEED_10 ? 7 : 0) |
1445 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1446 SPEED_100 ? 7 : 0) |
1447 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1448 SPEED_1000 ? 7 : 0));
1449 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1450 }
1451
cd28ab6a
SH		 1452 if (netif_msg_link(sky2))
1453 printk(KERN_INFO PFX
d571b694 1454 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1455 sky2->netdev->name, sky2->speed,
1456 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1457 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1458 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1459}
1460
1461static void sky2_link_down(struct sky2_port *sky2)
1462{
1463 struct sky2_hw *hw = sky2->hw;
1464 unsigned port = sky2->port;
1465 u16 reg;
1466
1467 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1468
1469 reg = gma_read16(hw, port, GM_GP_CTRL);
1470 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1471 gma_write16(hw, port, GM_GP_CTRL, reg);
1472 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1473
1474 if (sky2->rx_pause && !sky2->tx_pause) {
1475 /* restore Asymmetric Pause bit */
1476 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1477 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1478 | PHY_M_AN_ASP);
cd28ab6a
SH		 1479 }
1480
cd28ab6a
SH		 1481 netif_carrier_off(sky2->netdev);
1482 netif_stop_queue(sky2->netdev);
1483
1484 /* Turn on link LED */
1485 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1486
1487 if (netif_msg_link(sky2))
1488 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1489 sky2_phy_init(hw, port);
1490}
1491
793b883e
SH		 1492static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1493{
1494 struct sky2_hw *hw = sky2->hw;
1495 unsigned port = sky2->port;
1496 u16 lpa;
1497
1498 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1499
1500 if (lpa & PHY_M_AN_RF) {
1501 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1502 return -1;
1503 }
1504
1505 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1506 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1507 printk(KERN_ERR PFX "%s: master/slave fault",
1508 sky2->netdev->name);
1509 return -1;
1510 }
1511
1512 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1513 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1514 sky2->netdev->name);
1515 return -1;
1516 }
1517
1518 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1519
1520 sky2->speed = sky2_phy_speed(hw, aux);
1521
1522 /* Pause bits are offset (9..8) */
1523 if (hw->chip_id == CHIP_ID_YUKON_XL)
1524 aux >>= 6;
1525
1526 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1527 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1528
1529 if ((sky2->tx_pause || sky2->rx_pause)
1530 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1531 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1532 else
1533 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1534
1535 return 0;
1536}
cd28ab6a
SH		 1537
1538/*
91c86df5 1539 * Interrupt from PHY are handled outside of interrupt context
cd28ab6a
SH		 1540 * because accessing phy registers requires spin wait which might
1541 * cause excess interrupt latency.
1542 */
91c86df5 1543static void sky2_phy_task(void *arg)
cd28ab6a 1544{
91c86df5 1545 struct sky2_port *sky2 = arg;
cd28ab6a 1546 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1547 u16 istatus, phystat;
1548
91c86df5 1549 down(&sky2->phy_sema);
793b883e
SH		 1550 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1551 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1552
1553 if (netif_msg_intr(sky2))
1554 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1555 sky2->netdev->name, istatus, phystat);
1556
1557 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1558 if (sky2_autoneg_done(sky2, phystat) == 0)
1559 sky2_link_up(sky2);
1560 goto out;
1561 }
cd28ab6a 1562
793b883e
SH		 1563 if (istatus & PHY_M_IS_LSP_CHANGE)
1564 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1565
793b883e
SH		 1566 if (istatus & PHY_M_IS_DUP_CHANGE)
1567 sky2->duplex =
1568 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1569
793b883e
SH		 1570 if (istatus & PHY_M_IS_LST_CHANGE) {
1571 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1572 sky2_link_up(sky2);
793b883e
SH		 1573 else
1574 sky2_link_down(sky2);
cd28ab6a 1575 }
793b883e 1576out:
91c86df5 1577 up(&sky2->phy_sema);
cd28ab6a
SH		 1578
1579 local_irq_disable();
793b883e 1580 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1581 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1582 local_irq_enable();
1583}
1584
1585static void sky2_tx_timeout(struct net_device *dev)
1586{
1587 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1588 struct sky2_hw *hw = sky2->hw;
1589 unsigned txq = txqaddr[sky2->port];
cd28ab6a
SH		 1590
1591 if (netif_msg_timer(sky2))
1592 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1593
8cc048e3
SH		 1594 netif_stop_queue(dev);
1595
1596 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1597 sky2_read32(hw, Q_ADDR(txq, Q_CSR));
1598
1599 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
cd28ab6a
SH		 1600
1601 sky2_tx_clean(sky2);
8cc048e3
SH		 1602
1603 sky2_qset(hw, txq);
1604 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1605
1606 netif_wake_queue(dev);
cd28ab6a
SH		 1607}
1608
734d1868
SH		 1609
1610#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1611/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1612static inline unsigned sky2_buf_size(int mtu)
1613{
1614 return roundup(mtu + ETH_HLEN + 4, 8);
1615}
1616
cd28ab6a
SH		 1617static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1618{
6b1a3aef
SH		 1619 struct sky2_port *sky2 = netdev_priv(dev);
1620 struct sky2_hw *hw = sky2->hw;
1621 int err;
1622 u16 ctl, mode;
cd28ab6a
SH		 1623
1624 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1625 return -EINVAL;
1626
5a5b1ea0
SH		 1627 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1628 return -EINVAL;
1629
6b1a3aef
SH		 1630 if (!netif_running(dev)) {
1631 dev->mtu = new_mtu;
1632 return 0;
1633 }
1634
6b1a3aef
SH		 1635 sky2_write32(hw, B0_IMSK, 0);
1636
018d1c66
SH		 1637 dev->trans_start = jiffies; /* prevent tx timeout */
1638 netif_stop_queue(dev);
1639 netif_poll_disable(hw->dev[0]);
1640
6b1a3aef
SH		 1641 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1642 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1643 sky2_rx_stop(sky2);
1644 sky2_rx_clean(sky2);
cd28ab6a
SH		 1645
1646 dev->mtu = new_mtu;
734d1868 1647 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1648 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1649 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1650
1651 if (dev->mtu > ETH_DATA_LEN)
1652 mode |= GM_SMOD_JUMBO_ENA;
1653
1654 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1655
6b1a3aef 1656 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1657
6b1a3aef 1658 err = sky2_rx_start(sky2);
6b1a3aef 1659 sky2_write32(hw, B0_IMSK, hw->intr_mask);
018d1c66 1660
1b537565
SH		 1661 if (err)
1662 dev_close(dev);
1663 else {
1664 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1665
1666 netif_poll_enable(hw->dev[0]);
1667 netif_wake_queue(dev);
1668 }
1669
cd28ab6a
SH		 1670 return err;
1671}
1672
1673/*
1674 * Receive one packet.
1675 * For small packets or errors, just reuse existing skb.
d571b694 1676 * For larger packets, get new buffer.
cd28ab6a 1677 */
d11c13e7 1678static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1679 u16 length, u32 status)
1680{
cd28ab6a 1681 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1682 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1683
1684 if (unlikely(netif_msg_rx_status(sky2)))
1685 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1686 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1687
793b883e 1688 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1689 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1690
42eeea01 1691 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1692 goto error;
1693
42eeea01
SH		 1694 if (!(status & GMR_FS_RX_OK))
1695 goto resubmit;
1696
bdb5c58e 1697 if (length < copybreak) {
79e57d32
SH		 1698 skb = alloc_skb(length + 2, GFP_ATOMIC);
1699 if (!skb)
793b883e
SH		 1700 goto resubmit;
1701
79e57d32 1702 skb_reserve(skb, 2);
793b883e
SH		 1703 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1704 length, PCI_DMA_FROMDEVICE);
79e57d32 1705 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1706 skb->ip_summed = re->skb->ip_summed;
1707 skb->csum = re->skb->csum;
793b883e
SH		 1708 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1709 length, PCI_DMA_FROMDEVICE);
793b883e 1710 } else {
79e57d32
SH		 1711 struct sk_buff *nskb;
1712
734d1868 1713 nskb = dev_alloc_skb(sky2->rx_bufsize);
793b883e
SH		 1714 if (!nskb)
1715 goto resubmit;
cd28ab6a 1716
793b883e 1717 skb = re->skb;
79e57d32 1718 re->skb = nskb;
793b883e 1719 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1720 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1721 prefetch(skb->data);
cd28ab6a 1722
793b883e 1723 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1724 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1725 }
cd28ab6a 1726
79e57d32 1727 skb_put(skb, length);
793b883e 1728resubmit:
d11c13e7 1729 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1730 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1731
bea86103
SH		 1732 /* Tell receiver about new buffers. */
1733 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1734 &sky2->rx_last_put, RX_LE_SIZE);
1735
cd28ab6a
SH		 1736 return skb;
1737
1738error:
1739 if (netif_msg_rx_err(sky2))
1740 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1741 sky2->netdev->name, status, length);
793b883e
SH		 1742
1743 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1744 sky2->net_stats.rx_length_errors++;
1745 if (status & GMR_FS_FRAGMENT)
1746 sky2->net_stats.rx_frame_errors++;
1747 if (status & GMR_FS_CRC_ERR)
1748 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1749 if (status & GMR_FS_RX_FF_OV)
1750 sky2->net_stats.rx_fifo_errors++;
79e57d32 1751
793b883e 1752 goto resubmit;
cd28ab6a
SH		 1753}
1754
2224795d
SH		 1755/*
1756 * Check for transmit complete
793b883e 1757 */
13b97b74 1758#define TX_NO_STATUS 0xffff
2224795d 1759
13b97b74
SH		 1760static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1761{
1762 if (last != TX_NO_STATUS) {
1763 struct net_device *dev = hw->dev[port];
1764 if (dev && netif_running(dev)) {
1765 struct sky2_port *sky2 = netdev_priv(dev);
1766 sky2_tx_complete(sky2, last);
1767 }
2224795d 1768 }
cd28ab6a
SH		 1769}
1770
1771/*
cd28ab6a
SH		 1772 * Both ports share the same status interrupt, therefore there is only
1773 * one poll routine.
cd28ab6a 1774 */
d11c13e7 1775static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1776{
d11c13e7
SH		 1777 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1778 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1779 unsigned int work_done = 0;
793b883e 1780 u16 hwidx;
13b97b74 1781 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
cd28ab6a 1782
793b883e 1783 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1784 BUG_ON(hwidx >= STATUS_RING_SIZE);
af2a58ac 1785 rmb();
bea86103 1786
13210ce5
SH		 1787 while (hwidx != hw->st_idx) {
1788 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1789 struct net_device *dev;
d11c13e7 1790 struct sky2_port *sky2;
cd28ab6a 1791 struct sk_buff *skb;
cd28ab6a
SH		 1792 u32 status;
1793 u16 length;
13210ce5 1794 u8 op;
cd28ab6a 1795
13210ce5 1796 le = hw->st_le + hw->st_idx;
bea86103 1797 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
13210ce5 1798 prefetch(hw->st_le + hw->st_idx);
bea86103 1799
13210ce5
SH		 1800 BUG_ON(le->link >= 2);
1801 dev = hw->dev[le->link];
1802 if (dev == NULL || !netif_running(dev))
1803 continue;
1804
1805 sky2 = netdev_priv(dev);
cd28ab6a
SH		 1806 status = le32_to_cpu(le->status);
1807 length = le16_to_cpu(le->length);
13210ce5
SH		 1808 op = le->opcode & ~HW_OWNER;
1809 le->opcode = 0;
cd28ab6a 1810
13210ce5 1811 switch (op) {
cd28ab6a 1812 case OP_RXSTAT:
d11c13e7 1813 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1814 if (!skb)
1815 break;
13210ce5
SH		 1816
1817 skb->dev = dev;
1818 skb->protocol = eth_type_trans(skb, dev);
1819 dev->last_rx = jiffies;
1820
d1f13708
SH		 1821#ifdef SKY2_VLAN_TAG_USED
1822 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1823 vlan_hwaccel_receive_skb(skb,
1824 sky2->vlgrp,
1825 be16_to_cpu(sky2->rx_tag));
1826 } else
1827#endif
cd28ab6a 1828 netif_receive_skb(skb);
13210ce5
SH		 1829
1830 if (++work_done >= to_do)
1831 goto exit_loop;
cd28ab6a
SH		 1832 break;
1833
d1f13708
SH		 1834#ifdef SKY2_VLAN_TAG_USED
1835 case OP_RXVLAN:
1836 sky2->rx_tag = length;
1837 break;
1838
1839 case OP_RXCHKSVLAN:
1840 sky2->rx_tag = length;
1841 /* fall through */
1842#endif
cd28ab6a 1843 case OP_RXCHKS:
d11c13e7
SH		 1844 skb = sky2->rx_ring[sky2->rx_next].skb;
1845 skb->ip_summed = CHECKSUM_HW;
1846 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1847 break;
1848
1849 case OP_TXINDEXLE:
13b97b74
SH		 1850 /* TX index reports status for both ports */
1851 tx_done[0] = status & 0xffff;
1852 tx_done[1] = ((status >> 24) & 0xff)
1853 | (u16)(length & 0xf) << 8;
cd28ab6a
SH		 1854 break;
1855
cd28ab6a
SH		 1856 default:
1857 if (net_ratelimit())
793b883e 1858 printk(KERN_WARNING PFX
13210ce5 1859 "unknown status opcode 0x%x\n", op);
cd28ab6a
SH		 1860 break;
1861 }
13210ce5 1862 }
cd28ab6a 1863
13210ce5 1864exit_loop:
3e4b32e1 1865 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
793b883e
SH		 1866 mmiowb();
1867
13b97b74
SH		 1868 sky2_tx_check(hw, 0, tx_done[0]);
1869 sky2_tx_check(hw, 1, tx_done[1]);
1870
3e4b32e1 1871 if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
13b97b74 1872 /* need to restart TX timer */
cd28ab6a
SH		 1873 if (is_ec_a1(hw)) {
1874 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1875 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1876 }
1877
bea86103 1878 netif_rx_complete(dev0);
cd28ab6a
SH		 1879 hw->intr_mask |= Y2_IS_STAT_BMU;
1880 sky2_write32(hw, B0_IMSK, hw->intr_mask);
13210ce5
SH		 1881 mmiowb();
1882 return 0;
1883 } else {
1884 *budget -= work_done;
1885 dev0->quota -= work_done;
1886 return 1;
cd28ab6a 1887 }
cd28ab6a
SH		 1888}
1889
1890static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1891{
1892 struct net_device *dev = hw->dev[port];
1893
1894 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1895 dev->name, status);
1896
1897 if (status & Y2_IS_PAR_RD1) {
1898 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1899 dev->name);
1900 /* Clear IRQ */
1901 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1902 }
1903
1904 if (status & Y2_IS_PAR_WR1) {
1905 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1906 dev->name);
1907
1908 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1909 }
1910
1911 if (status & Y2_IS_PAR_MAC1) {
1912 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1913 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1914 }
1915
1916 if (status & Y2_IS_PAR_RX1) {
1917 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1918 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1919 }
1920
1921 if (status & Y2_IS_TCP_TXA1) {
1922 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1923 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1924 }
1925}
1926
1927static void sky2_hw_intr(struct sky2_hw *hw)
1928{
1929 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1930
793b883e 1931 if (status & Y2_IS_TIST_OV)
cd28ab6a 1932 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1933
1934 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1935 u16 pci_err;
1936
1937 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
cd28ab6a
SH		 1938 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1939 pci_name(hw->pdev), pci_err);
1940
1941 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1942 pci_write_config_word(hw->pdev, PCI_STATUS,
1943 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1944 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1945 }
1946
1947 if (status & Y2_IS_PCI_EXP) {
d571b694 1948 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 1949 u32 pex_err;
1950
1951 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1952
cd28ab6a
SH		 1953 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1954 pci_name(hw->pdev), pex_err);
1955
1956 /* clear the interrupt */
1957 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1958 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1959 0xffffffffUL);
cd28ab6a
SH		 1960 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1961
1962 if (pex_err & PEX_FATAL_ERRORS) {
1963 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1964 hwmsk &= ~Y2_IS_PCI_EXP;
1965 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1966 }
1967 }
1968
1969 if (status & Y2_HWE_L1_MASK)
1970 sky2_hw_error(hw, 0, status);
1971 status >>= 8;
1972 if (status & Y2_HWE_L1_MASK)
1973 sky2_hw_error(hw, 1, status);
1974}
1975
1976static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1977{
1978 struct net_device *dev = hw->dev[port];
1979 struct sky2_port *sky2 = netdev_priv(dev);
1980 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1981
1982 if (netif_msg_intr(sky2))
1983 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1984 dev->name, status);
1985
1986 if (status & GM_IS_RX_FF_OR) {
1987 ++sky2->net_stats.rx_fifo_errors;
1988 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1989 }
1990
1991 if (status & GM_IS_TX_FF_UR) {
1992 ++sky2->net_stats.tx_fifo_errors;
1993 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1994 }
cd28ab6a
SH		 1995}
1996
1997static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1998{
1999 struct net_device *dev = hw->dev[port];
2000 struct sky2_port *sky2 = netdev_priv(dev);
2001
2002 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2003 sky2_write32(hw, B0_IMSK, hw->intr_mask);
91c86df5 2004 schedule_work(&sky2->phy_task);
cd28ab6a
SH		 2005}
2006
2007static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2008{
2009 struct sky2_hw *hw = dev_id;
bea86103 2010 struct net_device *dev0 = hw->dev[0];
cd28ab6a
SH		 2011 u32 status;
2012
2013 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 2014 if (status == 0 || status == ~0)
cd28ab6a
SH		 2015 return IRQ_NONE;
2016
2017 if (status & Y2_IS_HW_ERR)
2018 sky2_hw_intr(hw);
2019
793b883e 2020 /* Do NAPI for Rx and Tx status */
bea86103 2021 if (status & Y2_IS_STAT_BMU) {
cd28ab6a
SH		 2022 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2023 sky2_write32(hw, B0_IMSK, hw->intr_mask);
bea86103 2024
0a122576
SH		 2025 if (likely(__netif_rx_schedule_prep(dev0))) {
2026 prefetch(&hw->st_le[hw->st_idx]);
bea86103 2027 __netif_rx_schedule(dev0);
0a122576 2028 }
cd28ab6a
SH		 2029 }
2030
793b883e 2031 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 2032 sky2_phy_intr(hw, 0);
2033
2034 if (status & Y2_IS_IRQ_PHY2)
2035 sky2_phy_intr(hw, 1);
2036
2037 if (status & Y2_IS_IRQ_MAC1)
2038 sky2_mac_intr(hw, 0);
2039
2040 if (status & Y2_IS_IRQ_MAC2)
2041 sky2_mac_intr(hw, 1);
2042
cd28ab6a 2043 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 2044
2045 sky2_read32(hw, B0_IMSK);
2046
cd28ab6a
SH		 2047 return IRQ_HANDLED;
2048}
2049
2050#ifdef CONFIG_NET_POLL_CONTROLLER
2051static void sky2_netpoll(struct net_device *dev)
2052{
2053 struct sky2_port *sky2 = netdev_priv(dev);
2054
793b883e 2055 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2056}
2057#endif
2058
2059/* Chip internal frequency for clock calculations */
fb17358f 2060static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2061{
793b883e 2062 switch (hw->chip_id) {
cd28ab6a 2063 case CHIP_ID_YUKON_EC:
5a5b1ea0 2064 case CHIP_ID_YUKON_EC_U:
fb17358f 2065 return 125; /* 125 Mhz */
cd28ab6a 2066 case CHIP_ID_YUKON_FE:
fb17358f 2067 return 100; /* 100 Mhz */
793b883e 2068 default: /* YUKON_XL */
fb17358f 2069 return 156; /* 156 Mhz */
cd28ab6a
SH		 2070 }
2071}
2072
fb17358f 2073static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2074{
fb17358f 2075 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2076}
2077
fb17358f 2078static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2079{
fb17358f 2080 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2081}
2082
fb17358f 2083
cd28ab6a
SH		 2084static int sky2_reset(struct sky2_hw *hw)
2085{
5afa0a9c 2086 u32 ctst;
cd28ab6a
SH		 2087 u16 status;
2088 u8 t8, pmd_type;
2089 int i;
2090
2091 ctst = sky2_read32(hw, B0_CTST);
2092
2093 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2094 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2095 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2096 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2097 pci_name(hw->pdev), hw->chip_id);
2098 return -EOPNOTSUPP;
2099 }
2100
793b883e
SH		 2101 /* ring for status responses */
2102 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2103 &hw->st_dma);
2104 if (!hw->st_le)
2105 return -ENOMEM;
2106
cd28ab6a
SH		 2107 /* disable ASF */
2108 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2109 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2110 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2111 }
2112
2113 /* do a SW reset */
2114 sky2_write8(hw, B0_CTST, CS_RST_SET);
2115 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2116
2117 /* clear PCI errors, if any */
793b883e 2118 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 2119 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 2120 pci_write_config_word(hw->pdev, PCI_STATUS,
2121 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2122
2123 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2124
2125 /* clear any PEX errors */
2126 if (is_pciex(hw)) {
793b883e
SH		 2127 u16 lstat;
2128 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2129 0xffffffffUL);
2130 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 2131 }
2132
2133 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2134 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2135
2136 hw->ports = 1;
2137 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2138 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2139 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2140 ++hw->ports;
2141 }
2142 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2143
5afa0a9c 2144 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2145
2146 for (i = 0; i < hw->ports; i++) {
2147 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2148 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2149 }
2150
2151 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2152
793b883e
SH		 2153 /* Clear I2C IRQ noise */
2154 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2155
2156 /* turn off hardware timer (unused) */
2157 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2158 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2159
cd28ab6a
SH		 2160 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2161
69634ee7
SH		 2162 /* Turn off descriptor polling */
2163 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2164
2165 /* Turn off receive timestamp */
2166 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2167 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2168
2169 /* enable the Tx Arbiters */
2170 for (i = 0; i < hw->ports; i++)
2171 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2172
2173 /* Initialize ram interface */
2174 for (i = 0; i < hw->ports; i++) {
793b883e 2175 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2176
2177 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2178 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2179 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2180 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2181 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2182 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2183 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2184 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2185 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2186 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2187 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2188 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2189 }
2190
cd28ab6a
SH		 2191 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2192
cd28ab6a
SH		 2193 for (i = 0; i < hw->ports; i++)
2194 sky2_phy_reset(hw, i);
cd28ab6a 2195
cd28ab6a
SH		 2196 memset(hw->st_le, 0, STATUS_LE_BYTES);
2197 hw->st_idx = 0;
2198
2199 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2200 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2201
2202 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2203 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2204
2205 /* Set the list last index */
793b883e 2206 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2207
793b883e 2208 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2209 if (is_ec_a1(hw)) {
2210 /* WA for dev. #4.3 */
793b883e 2211 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2212
2213 /* set Status-FIFO watermark */
2214 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2215
2216 /* set Status-FIFO ISR watermark */
793b883e 2217 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
69634ee7 2218 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
cd28ab6a 2219 } else {
69634ee7
SH		 2220 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2221 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a
SH		 2222
2223 /* set Status-FIFO ISR watermark */
2224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
69634ee7
SH		 2225 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2226 else
2227 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2228
69634ee7
SH		 2229 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2230 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2231 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
cd28ab6a
SH		 2232 }
2233
793b883e 2234 /* enable status unit */
cd28ab6a
SH		 2235 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2236
2237 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2238 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2239 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2240
2241 return 0;
2242}
2243
2244static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2245{
2246 u32 modes;
2247 if (hw->copper) {
793b883e
SH		 2248 modes = SUPPORTED_10baseT_Half
2249 | SUPPORTED_10baseT_Full
2250 | SUPPORTED_100baseT_Half
2251 | SUPPORTED_100baseT_Full
2252 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2253
2254 if (hw->chip_id != CHIP_ID_YUKON_FE)
2255 modes |= SUPPORTED_1000baseT_Half
793b883e 2256 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2257 } else
2258 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2259 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2260 return modes;
2261}
2262
793b883e 2263static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2264{
2265 struct sky2_port *sky2 = netdev_priv(dev);
2266 struct sky2_hw *hw = sky2->hw;
2267
2268 ecmd->transceiver = XCVR_INTERNAL;
2269 ecmd->supported = sky2_supported_modes(hw);
2270 ecmd->phy_address = PHY_ADDR_MARV;
2271 if (hw->copper) {
2272 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2273 | SUPPORTED_10baseT_Full
2274 | SUPPORTED_100baseT_Half
2275 | SUPPORTED_100baseT_Full
2276 | SUPPORTED_1000baseT_Half
2277 | SUPPORTED_1000baseT_Full
2278 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2279 ecmd->port = PORT_TP;
2280 } else
2281 ecmd->port = PORT_FIBRE;
2282
2283 ecmd->advertising = sky2->advertising;
2284 ecmd->autoneg = sky2->autoneg;
2285 ecmd->speed = sky2->speed;
2286 ecmd->duplex = sky2->duplex;
2287 return 0;
2288}
2289
2290static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2291{
2292 struct sky2_port *sky2 = netdev_priv(dev);
2293 const struct sky2_hw *hw = sky2->hw;
2294 u32 supported = sky2_supported_modes(hw);
2295
2296 if (ecmd->autoneg == AUTONEG_ENABLE) {
2297 ecmd->advertising = supported;
2298 sky2->duplex = -1;
2299 sky2->speed = -1;
2300 } else {
2301 u32 setting;
2302
793b883e 2303 switch (ecmd->speed) {
cd28ab6a
SH		 2304 case SPEED_1000:
2305 if (ecmd->duplex == DUPLEX_FULL)
2306 setting = SUPPORTED_1000baseT_Full;
2307 else if (ecmd->duplex == DUPLEX_HALF)
2308 setting = SUPPORTED_1000baseT_Half;
2309 else
2310 return -EINVAL;
2311 break;
2312 case SPEED_100:
2313 if (ecmd->duplex == DUPLEX_FULL)
2314 setting = SUPPORTED_100baseT_Full;
2315 else if (ecmd->duplex == DUPLEX_HALF)
2316 setting = SUPPORTED_100baseT_Half;
2317 else
2318 return -EINVAL;
2319 break;
2320
2321 case SPEED_10:
2322 if (ecmd->duplex == DUPLEX_FULL)
2323 setting = SUPPORTED_10baseT_Full;
2324 else if (ecmd->duplex == DUPLEX_HALF)
2325 setting = SUPPORTED_10baseT_Half;
2326 else
2327 return -EINVAL;
2328 break;
2329 default:
2330 return -EINVAL;
2331 }
2332
2333 if ((setting & supported) == 0)
2334 return -EINVAL;
2335
2336 sky2->speed = ecmd->speed;
2337 sky2->duplex = ecmd->duplex;
2338 }
2339
2340 sky2->autoneg = ecmd->autoneg;
2341 sky2->advertising = ecmd->advertising;
2342
1b537565
SH		 2343 if (netif_running(dev))
2344 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2345
2346 return 0;
2347}
2348
2349static void sky2_get_drvinfo(struct net_device *dev,
2350 struct ethtool_drvinfo *info)
2351{
2352 struct sky2_port *sky2 = netdev_priv(dev);
2353
2354 strcpy(info->driver, DRV_NAME);
2355 strcpy(info->version, DRV_VERSION);
2356 strcpy(info->fw_version, "N/A");
2357 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2358}
2359
2360static const struct sky2_stat {
793b883e
SH		 2361 char name[ETH_GSTRING_LEN];
2362 u16 offset;
cd28ab6a
SH		 2363} sky2_stats[] = {
2364 { "tx_bytes", GM_TXO_OK_HI },
2365 { "rx_bytes", GM_RXO_OK_HI },
2366 { "tx_broadcast", GM_TXF_BC_OK },
2367 { "rx_broadcast", GM_RXF_BC_OK },
2368 { "tx_multicast", GM_TXF_MC_OK },
2369 { "rx_multicast", GM_RXF_MC_OK },
2370 { "tx_unicast", GM_TXF_UC_OK },
2371 { "rx_unicast", GM_RXF_UC_OK },
2372 { "tx_mac_pause", GM_TXF_MPAUSE },
2373 { "rx_mac_pause", GM_RXF_MPAUSE },
2374 { "collisions", GM_TXF_SNG_COL },
2375 { "late_collision",GM_TXF_LAT_COL },
2376 { "aborted", GM_TXF_ABO_COL },
2377 { "multi_collisions", GM_TXF_MUL_COL },
2378 { "fifo_underrun", GM_TXE_FIFO_UR },
2379 { "fifo_overflow", GM_RXE_FIFO_OV },
2380 { "rx_toolong", GM_RXF_LNG_ERR },
2381 { "rx_jabber", GM_RXF_JAB_PKT },
2382 { "rx_runt", GM_RXE_FRAG },
2383 { "rx_too_long", GM_RXF_LNG_ERR },
2384 { "rx_fcs_error", GM_RXF_FCS_ERR },
2385};
2386
cd28ab6a
SH		 2387static u32 sky2_get_rx_csum(struct net_device *dev)
2388{
2389 struct sky2_port *sky2 = netdev_priv(dev);
2390
2391 return sky2->rx_csum;
2392}
2393
2394static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2395{
2396 struct sky2_port *sky2 = netdev_priv(dev);
2397
2398 sky2->rx_csum = data;
793b883e 2399
cd28ab6a
SH		 2400 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2401 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2402
2403 return 0;
2404}
2405
2406static u32 sky2_get_msglevel(struct net_device *netdev)
2407{
2408 struct sky2_port *sky2 = netdev_priv(netdev);
2409 return sky2->msg_enable;
2410}
2411
9a7ae0a9
SH		 2412static int sky2_nway_reset(struct net_device *dev)
2413{
2414 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2415
2416 if (sky2->autoneg != AUTONEG_ENABLE)
2417 return -EINVAL;
2418
1b537565 2419 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2420
2421 return 0;
2422}
2423
793b883e 2424static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2425{
2426 struct sky2_hw *hw = sky2->hw;
2427 unsigned port = sky2->port;
2428 int i;
2429
2430 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2431 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2432 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2433 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2434
793b883e 2435 for (i = 2; i < count; i++)
cd28ab6a
SH		 2436 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2437}
2438
cd28ab6a
SH		 2439static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2440{
2441 struct sky2_port *sky2 = netdev_priv(netdev);
2442 sky2->msg_enable = value;
2443}
2444
2445static int sky2_get_stats_count(struct net_device *dev)
2446{
2447 return ARRAY_SIZE(sky2_stats);
2448}
2449
2450static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2451 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2452{
2453 struct sky2_port *sky2 = netdev_priv(dev);
2454
793b883e 2455 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2456}
2457
793b883e 2458static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2459{
2460 int i;
2461
2462 switch (stringset) {
2463 case ETH_SS_STATS:
2464 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2465 memcpy(data + i * ETH_GSTRING_LEN,
2466 sky2_stats[i].name, ETH_GSTRING_LEN);
2467 break;
2468 }
2469}
2470
2471/* Use hardware MIB variables for critical path statistics and
2472 * transmit feedback not reported at interrupt.
2473 * Other errors are accounted for in interrupt handler.
2474 */
2475static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2476{
2477 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2478 u64 data[13];
cd28ab6a 2479
793b883e 2480 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2481
2482 sky2->net_stats.tx_bytes = data[0];
2483 sky2->net_stats.rx_bytes = data[1];
2484 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2485 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2486 sky2->net_stats.multicast = data[5] + data[7];
2487 sky2->net_stats.collisions = data[10];
2488 sky2->net_stats.tx_aborted_errors = data[12];
2489
2490 return &sky2->net_stats;
2491}
2492
2493static int sky2_set_mac_address(struct net_device *dev, void *p)
2494{
2495 struct sky2_port *sky2 = netdev_priv(dev);
2496 struct sockaddr *addr = p;
cd28ab6a
SH		 2497
2498 if (!is_valid_ether_addr(addr->sa_data))
2499 return -EADDRNOTAVAIL;
2500
cd28ab6a 2501 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2502 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2503 dev->dev_addr, ETH_ALEN);
793b883e 2504 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a 2505 dev->dev_addr, ETH_ALEN);
1b537565
SH		 2506
2507 if (netif_running(dev))
2508 sky2_phy_reinit(sky2);
2509
2510 return 0;
cd28ab6a
SH		 2511}
2512
2513static void sky2_set_multicast(struct net_device *dev)
2514{
2515 struct sky2_port *sky2 = netdev_priv(dev);
2516 struct sky2_hw *hw = sky2->hw;
2517 unsigned port = sky2->port;
2518 struct dev_mc_list *list = dev->mc_list;
2519 u16 reg;
2520 u8 filter[8];
2521
2522 memset(filter, 0, sizeof(filter));
2523
2524 reg = gma_read16(hw, port, GM_RX_CTRL);
2525 reg |= GM_RXCR_UCF_ENA;
2526
d571b694 2527 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2528 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2529 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2530 memset(filter, 0xff, sizeof(filter));
793b883e 2531 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2532 reg &= ~GM_RXCR_MCF_ENA;
2533 else {
2534 int i;
2535 reg |= GM_RXCR_MCF_ENA;
2536
2537 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2538 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2539 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2540 }
2541 }
2542
cd28ab6a 2543 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2544 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2545 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2546 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2547 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2548 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2549 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2550 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2551
2552 gma_write16(hw, port, GM_RX_CTRL, reg);
2553}
2554
2555/* Can have one global because blinking is controlled by
2556 * ethtool and that is always under RTNL mutex
2557 */
91c86df5 2558static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2559{
793b883e
SH		 2560 u16 pg;
2561
793b883e
SH		 2562 switch (hw->chip_id) {
2563 case CHIP_ID_YUKON_XL:
2564 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2566 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2567 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2568 PHY_M_LEDC_INIT_CTRL(7) |
2569 PHY_M_LEDC_STA1_CTRL(7) |
2570 PHY_M_LEDC_STA0_CTRL(7))
2571 : 0);
2572
2573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2574 break;
2575
2576 default:
2577 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2578 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2579 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2580 PHY_M_LED_MO_10(MO_LED_ON) |
2581 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2582 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2583 PHY_M_LED_MO_RX(MO_LED_ON)
2584 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2585 PHY_M_LED_MO_10(MO_LED_OFF) |
2586 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2587 PHY_M_LED_MO_1000(MO_LED_OFF) |
2588 PHY_M_LED_MO_RX(MO_LED_OFF));
2589
793b883e 2590 }
cd28ab6a
SH		 2591}
2592
2593/* blink LED's for finding board */
2594static int sky2_phys_id(struct net_device *dev, u32 data)
2595{
2596 struct sky2_port *sky2 = netdev_priv(dev);
2597 struct sky2_hw *hw = sky2->hw;
2598 unsigned port = sky2->port;
793b883e 2599 u16 ledctrl, ledover = 0;
cd28ab6a 2600 long ms;
91c86df5 2601 int interrupted;
cd28ab6a
SH		 2602 int onoff = 1;
2603
793b883e 2604 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2605 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2606 else
2607 ms = data * 1000;
2608
2609 /* save initial values */
91c86df5 2610 down(&sky2->phy_sema);
793b883e
SH		 2611 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2612 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2613 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2614 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2616 } else {
2617 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2618 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2619 }
cd28ab6a 2620
91c86df5
SH		 2621 interrupted = 0;
2622 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2623 sky2_led(hw, port, onoff);
2624 onoff = !onoff;
2625
91c86df5
SH		 2626 up(&sky2->phy_sema);
2627 interrupted = msleep_interruptible(250);
2628 down(&sky2->phy_sema);
2629
cd28ab6a
SH		 2630 ms -= 250;
2631 }
2632
2633 /* resume regularly scheduled programming */
793b883e
SH		 2634 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2635 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2636 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2637 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2638 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2639 } else {
2640 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2641 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2642 }
91c86df5 2643 up(&sky2->phy_sema);
cd28ab6a
SH		 2644
2645 return 0;
2646}
2647
2648static void sky2_get_pauseparam(struct net_device *dev,
2649 struct ethtool_pauseparam *ecmd)
2650{
2651 struct sky2_port *sky2 = netdev_priv(dev);
2652
2653 ecmd->tx_pause = sky2->tx_pause;
2654 ecmd->rx_pause = sky2->rx_pause;
2655 ecmd->autoneg = sky2->autoneg;
2656}
2657
2658static int sky2_set_pauseparam(struct net_device *dev,
2659 struct ethtool_pauseparam *ecmd)
2660{
2661 struct sky2_port *sky2 = netdev_priv(dev);
2662 int err = 0;
2663
2664 sky2->autoneg = ecmd->autoneg;
2665 sky2->tx_pause = ecmd->tx_pause != 0;
2666 sky2->rx_pause = ecmd->rx_pause != 0;
2667
1b537565 2668 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2669
2670 return err;
2671}
2672
2673#ifdef CONFIG_PM
2674static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2675{
2676 struct sky2_port *sky2 = netdev_priv(dev);
2677
2678 wol->supported = WAKE_MAGIC;
2679 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2680}
2681
2682static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2683{
2684 struct sky2_port *sky2 = netdev_priv(dev);
2685 struct sky2_hw *hw = sky2->hw;
2686
2687 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2688 return -EOPNOTSUPP;
2689
2690 sky2->wol = wol->wolopts == WAKE_MAGIC;
2691
2692 if (sky2->wol) {
2693 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2694
2695 sky2_write16(hw, WOL_CTRL_STAT,
2696 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2697 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2698 } else
2699 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2700
2701 return 0;
2702}
2703#endif
2704
fb17358f
SH		 2705static int sky2_get_coalesce(struct net_device *dev,
2706 struct ethtool_coalesce *ecmd)
2707{
2708 struct sky2_port *sky2 = netdev_priv(dev);
2709 struct sky2_hw *hw = sky2->hw;
2710
2711 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2712 ecmd->tx_coalesce_usecs = 0;
2713 else {
2714 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2715 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2716 }
2717 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2718
2719 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2720 ecmd->rx_coalesce_usecs = 0;
2721 else {
2722 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2723 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2724 }
2725 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2726
2727 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2728 ecmd->rx_coalesce_usecs_irq = 0;
2729 else {
2730 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2731 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2732 }
2733
2734 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2735
2736 return 0;
2737}
2738
2739/* Note: this affect both ports */
2740static int sky2_set_coalesce(struct net_device *dev,
2741 struct ethtool_coalesce *ecmd)
2742{
2743 struct sky2_port *sky2 = netdev_priv(dev);
2744 struct sky2_hw *hw = sky2->hw;
2745 const u32 tmin = sky2_clk2us(hw, 1);
2746 const u32 tmax = 5000;
2747
2748 if (ecmd->tx_coalesce_usecs != 0 &&
2749 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2750 return -EINVAL;
2751
2752 if (ecmd->rx_coalesce_usecs != 0 &&
2753 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2754 return -EINVAL;
2755
2756 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2757 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2758 return -EINVAL;
2759
2760 if (ecmd->tx_max_coalesced_frames > 0xffff)
2761 return -EINVAL;
2762 if (ecmd->rx_max_coalesced_frames > 0xff)
2763 return -EINVAL;
2764 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2765 return -EINVAL;
2766
2767 if (ecmd->tx_coalesce_usecs == 0)
2768 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2769 else {
2770 sky2_write32(hw, STAT_TX_TIMER_INI,
2771 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2772 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2773 }
2774 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2775
2776 if (ecmd->rx_coalesce_usecs == 0)
2777 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2778 else {
2779 sky2_write32(hw, STAT_LEV_TIMER_INI,
2780 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2781 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2782 }
2783 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2784
2785 if (ecmd->rx_coalesce_usecs_irq == 0)
2786 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2787 else {
2788 sky2_write32(hw, STAT_TX_TIMER_INI,
2789 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2790 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2791 }
2792 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2793 return 0;
2794}
2795
793b883e
SH		 2796static void sky2_get_ringparam(struct net_device *dev,
2797 struct ethtool_ringparam *ering)
2798{
2799 struct sky2_port *sky2 = netdev_priv(dev);
2800
2801 ering->rx_max_pending = RX_MAX_PENDING;
2802 ering->rx_mini_max_pending = 0;
2803 ering->rx_jumbo_max_pending = 0;
2804 ering->tx_max_pending = TX_RING_SIZE - 1;
2805
2806 ering->rx_pending = sky2->rx_pending;
2807 ering->rx_mini_pending = 0;
2808 ering->rx_jumbo_pending = 0;
2809 ering->tx_pending = sky2->tx_pending;
2810}
2811
2812static int sky2_set_ringparam(struct net_device *dev,
2813 struct ethtool_ringparam *ering)
2814{
2815 struct sky2_port *sky2 = netdev_priv(dev);
2816 int err = 0;
2817
2818 if (ering->rx_pending > RX_MAX_PENDING ||
2819 ering->rx_pending < 8 ||
2820 ering->tx_pending < MAX_SKB_TX_LE ||
2821 ering->tx_pending > TX_RING_SIZE - 1)
2822 return -EINVAL;
2823
2824 if (netif_running(dev))
2825 sky2_down(dev);
2826
2827 sky2->rx_pending = ering->rx_pending;
2828 sky2->tx_pending = ering->tx_pending;
2829
1b537565 2830 if (netif_running(dev)) {
793b883e 2831 err = sky2_up(dev);
1b537565
SH		 2832 if (err)
2833 dev_close(dev);
6ed995bb
SH		 2834 else
2835 sky2_set_multicast(dev);
1b537565 2836 }
793b883e
SH		 2837
2838 return err;
2839}
2840
793b883e
SH		 2841static int sky2_get_regs_len(struct net_device *dev)
2842{
6e4cbb34 2843 return 0x4000;
793b883e
SH		 2844}
2845
2846/*
2847 * Returns copy of control register region
6e4cbb34 2848 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2849 */
2850static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2851 void *p)
2852{
2853 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2854 const void __iomem *io = sky2->hw->regs;
793b883e 2855
6e4cbb34 2856 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2857 regs->version = 1;
6e4cbb34 2858 memset(p, 0, regs->len);
793b883e 2859
6e4cbb34
SH		 2860 memcpy_fromio(p, io, B3_RAM_ADDR);
2861
2862 memcpy_fromio(p + B3_RI_WTO_R1,
2863 io + B3_RI_WTO_R1,
2864 regs->len - B3_RI_WTO_R1);
793b883e 2865}
cd28ab6a
SH		 2866
2867static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2868 .get_settings = sky2_get_settings,
2869 .set_settings = sky2_set_settings,
2870 .get_drvinfo = sky2_get_drvinfo,
2871 .get_msglevel = sky2_get_msglevel,
2872 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2873 .nway_reset = sky2_nway_reset,
793b883e
SH		 2874 .get_regs_len = sky2_get_regs_len,
2875 .get_regs = sky2_get_regs,
2876 .get_link = ethtool_op_get_link,
2877 .get_sg = ethtool_op_get_sg,
2878 .set_sg = ethtool_op_set_sg,
2879 .get_tx_csum = ethtool_op_get_tx_csum,
2880 .set_tx_csum = ethtool_op_set_tx_csum,
2881 .get_tso = ethtool_op_get_tso,
2882 .set_tso = ethtool_op_set_tso,
2883 .get_rx_csum = sky2_get_rx_csum,
2884 .set_rx_csum = sky2_set_rx_csum,
2885 .get_strings = sky2_get_strings,
fb17358f
SH		 2886 .get_coalesce = sky2_get_coalesce,
2887 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 2888 .get_ringparam = sky2_get_ringparam,
2889 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2890 .get_pauseparam = sky2_get_pauseparam,
2891 .set_pauseparam = sky2_set_pauseparam,
2892#ifdef CONFIG_PM
793b883e
SH		 2893 .get_wol = sky2_get_wol,
2894 .set_wol = sky2_set_wol,
cd28ab6a 2895#endif
793b883e 2896 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2897 .get_stats_count = sky2_get_stats_count,
2898 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2899 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2900};
2901
2902/* Initialize network device */
2903static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2904 unsigned port, int highmem)
2905{
2906 struct sky2_port *sky2;
2907 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2908
2909 if (!dev) {
2910 printk(KERN_ERR "sky2 etherdev alloc failed");
2911 return NULL;
2912 }
2913
2914 SET_MODULE_OWNER(dev);
2915 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2916 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 2917 dev->open = sky2_up;
2918 dev->stop = sky2_down;
ef743d33 2919 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 2920 dev->hard_start_xmit = sky2_xmit_frame;
2921 dev->get_stats = sky2_get_stats;
2922 dev->set_multicast_list = sky2_set_multicast;
2923 dev->set_mac_address = sky2_set_mac_address;
2924 dev->change_mtu = sky2_change_mtu;
2925 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2926 dev->tx_timeout = sky2_tx_timeout;
2927 dev->watchdog_timeo = TX_WATCHDOG;
2928 if (port == 0)
2929 dev->poll = sky2_poll;
2930 dev->weight = NAPI_WEIGHT;
2931#ifdef CONFIG_NET_POLL_CONTROLLER
2932 dev->poll_controller = sky2_netpoll;
2933#endif
cd28ab6a
SH		 2934
2935 sky2 = netdev_priv(dev);
2936 sky2->netdev = dev;
2937 sky2->hw = hw;
2938 sky2->msg_enable = netif_msg_init(debug, default_msg);
2939
2940 spin_lock_init(&sky2->tx_lock);
2941 /* Auto speed and flow control */
2942 sky2->autoneg = AUTONEG_ENABLE;
585b5601 2943 sky2->tx_pause = 1;
cd28ab6a
SH		 2944 sky2->rx_pause = 1;
2945 sky2->duplex = -1;
2946 sky2->speed = -1;
2947 sky2->advertising = sky2_supported_modes(hw);
75d070c5
SH		 2948
2949 /* Receive checksum disabled for Yukon XL
2950 * because of observed problems with incorrect
2951 * values when multiple packets are received in one interrupt
2952 */
2953 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
2954
91c86df5
SH		 2955 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
2956 init_MUTEX(&sky2->phy_sema);
793b883e
SH		 2957 sky2->tx_pending = TX_DEF_PENDING;
2958 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
734d1868 2959 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 2960
2961 hw->dev[port] = dev;
2962
2963 sky2->port = port;
2964
5a5b1ea0
SH		 2965 dev->features |= NETIF_F_LLTX;
2966 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2967 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 2968 if (highmem)
2969 dev->features |= NETIF_F_HIGHDMA;
793b883e 2970 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 2971
d1f13708
SH		 2972#ifdef SKY2_VLAN_TAG_USED
2973 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2974 dev->vlan_rx_register = sky2_vlan_rx_register;
2975 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2976#endif
2977
cd28ab6a 2978 /* read the mac address */
793b883e 2979 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 2980 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 2981
2982 /* device is off until link detection */
2983 netif_carrier_off(dev);
2984 netif_stop_queue(dev);
2985
2986 return dev;
2987}
2988
2989static inline void sky2_show_addr(struct net_device *dev)
2990{
2991 const struct sky2_port *sky2 = netdev_priv(dev);
2992
2993 if (netif_msg_probe(sky2))
2994 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2995 dev->name,
2996 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2997 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2998}
2999
3000static int __devinit sky2_probe(struct pci_dev *pdev,
3001 const struct pci_device_id *ent)
3002{
793b883e 3003 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3004 struct sky2_hw *hw;
5afa0a9c 3005 int err, pm_cap, using_dac = 0;
cd28ab6a 3006
793b883e
SH		 3007 err = pci_enable_device(pdev);
3008 if (err) {
cd28ab6a
SH		 3009 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3010 pci_name(pdev));
3011 goto err_out;
3012 }
3013
793b883e
SH		 3014 err = pci_request_regions(pdev, DRV_NAME);
3015 if (err) {
cd28ab6a
SH		 3016 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3017 pci_name(pdev));
793b883e 3018 goto err_out;
cd28ab6a
SH		 3019 }
3020
3021 pci_set_master(pdev);
3022
5afa0a9c
SH		 3023 /* Find power-management capability. */
3024 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3025 if (pm_cap == 0) {
3026 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3027 "aborting.\n");
3028 err = -EIO;
3029 goto err_out_free_regions;
3030 }
3031
cd28ab6a
SH		 3032 if (sizeof(dma_addr_t) > sizeof(u32)) {
3033 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3034 if (!err)
3035 using_dac = 1;
3036 }
3037
3038 if (!using_dac) {
3039 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3040 if (err) {
3041 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3042 pci_name(pdev));
3043 goto err_out_free_regions;
3044 }
3045 }
cd28ab6a 3046#ifdef __BIG_ENDIAN
d571b694 3047 /* byte swap descriptors in hardware */
cd28ab6a
SH		 3048 {
3049 u32 reg;
3050
3051 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3052 reg |= PCI_REV_DESC;
3053 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3054 }
3055#endif
3056
3057 err = -ENOMEM;
3058 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3059 if (!hw) {
3060 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3061 pci_name(pdev));
3062 goto err_out_free_regions;
3063 }
3064
3065 memset(hw, 0, sizeof(*hw));
3066 hw->pdev = pdev;
cd28ab6a
SH		 3067
3068 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3069 if (!hw->regs) {
3070 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3071 pci_name(pdev));
3072 goto err_out_free_hw;
3073 }
5afa0a9c 3074 hw->pm_cap = pm_cap;
cd28ab6a 3075
cd28ab6a
SH		 3076 err = sky2_reset(hw);
3077 if (err)
793b883e 3078 goto err_out_iounmap;
cd28ab6a 3079
5f4f9dc1
SH		 3080 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3081 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3082 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3083 hw->chip_id, hw->chip_rev);
cd28ab6a 3084
793b883e
SH		 3085 dev = sky2_init_netdev(hw, 0, using_dac);
3086 if (!dev)
cd28ab6a
SH		 3087 goto err_out_free_pci;
3088
793b883e
SH		 3089 err = register_netdev(dev);
3090 if (err) {
cd28ab6a
SH		 3091 printk(KERN_ERR PFX "%s: cannot register net device\n",
3092 pci_name(pdev));
3093 goto err_out_free_netdev;
3094 }
3095
3096 sky2_show_addr(dev);
3097
3098 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3099 if (register_netdev(dev1) == 0)
3100 sky2_show_addr(dev1);
3101 else {
3102 /* Failure to register second port need not be fatal */
793b883e
SH		 3103 printk(KERN_WARNING PFX
3104 "register of second port failed\n");
cd28ab6a
SH		 3105 hw->dev[1] = NULL;
3106 free_netdev(dev1);
3107 }
3108 }
3109
793b883e
SH		 3110 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3111 if (err) {
3112 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3113 pci_name(pdev), pdev->irq);
3114 goto err_out_unregister;
3115 }
3116
3117 hw->intr_mask = Y2_IS_BASE;
3118 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3119
3120 pci_set_drvdata(pdev, hw);
3121
cd28ab6a
SH		 3122 return 0;
3123
793b883e
SH		 3124err_out_unregister:
3125 if (dev1) {
3126 unregister_netdev(dev1);
3127 free_netdev(dev1);
3128 }
3129 unregister_netdev(dev);
cd28ab6a
SH		 3130err_out_free_netdev:
3131 free_netdev(dev);
cd28ab6a 3132err_out_free_pci:
793b883e 3133 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3134 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3135err_out_iounmap:
3136 iounmap(hw->regs);
3137err_out_free_hw:
3138 kfree(hw);
3139err_out_free_regions:
3140 pci_release_regions(pdev);
cd28ab6a 3141 pci_disable_device(pdev);
cd28ab6a
SH		 3142err_out:
3143 return err;
3144}
3145
3146static void __devexit sky2_remove(struct pci_dev *pdev)
3147{
793b883e 3148 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3149 struct net_device *dev0, *dev1;
3150
793b883e 3151 if (!hw)
cd28ab6a
SH		 3152 return;
3153
cd28ab6a 3154 dev0 = hw->dev[0];
793b883e
SH		 3155 dev1 = hw->dev[1];
3156 if (dev1)
3157 unregister_netdev(dev1);
cd28ab6a
SH		 3158 unregister_netdev(dev0);
3159
793b883e 3160 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 3161 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3162 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3163 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3164 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3165
3166 free_irq(pdev->irq, hw);
793b883e 3167 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3168 pci_release_regions(pdev);
3169 pci_disable_device(pdev);
793b883e 3170
cd28ab6a
SH		 3171 if (dev1)
3172 free_netdev(dev1);
3173 free_netdev(dev0);
3174 iounmap(hw->regs);
3175 kfree(hw);
5afa0a9c 3176
cd28ab6a
SH		 3177 pci_set_drvdata(pdev, NULL);
3178}
3179
3180#ifdef CONFIG_PM
3181static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3182{
793b883e 3183 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3184 int i;
cd28ab6a
SH		 3185
3186 for (i = 0; i < 2; i++) {
3187 struct net_device *dev = hw->dev[i];
3188
3189 if (dev) {
5afa0a9c
SH		 3190 if (!netif_running(dev))
3191 continue;
3192
3193 sky2_down(dev);
cd28ab6a 3194 netif_device_detach(dev);
cd28ab6a
SH		 3195 }
3196 }
3197
5afa0a9c 3198 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3199}
3200
3201static int sky2_resume(struct pci_dev *pdev)
3202{
793b883e 3203 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3204 int i;
3205
cd28ab6a
SH		 3206 pci_restore_state(pdev);
3207 pci_enable_wake(pdev, PCI_D0, 0);
5afa0a9c 3208 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 3209
3210 sky2_reset(hw);
3211
3212 for (i = 0; i < 2; i++) {
3213 struct net_device *dev = hw->dev[i];
3214 if (dev) {
5afa0a9c
SH		 3215 if (netif_running(dev)) {
3216 netif_device_attach(dev);
1b537565
SH		 3217 if (sky2_up(dev))
3218 dev_close(dev);
5afa0a9c 3219 }
cd28ab6a
SH		 3220 }
3221 }
3222 return 0;
3223}
3224#endif
3225
3226static struct pci_driver sky2_driver = {
793b883e
SH		 3227 .name = DRV_NAME,
3228 .id_table = sky2_id_table,
3229 .probe = sky2_probe,
3230 .remove = __devexit_p(sky2_remove),
cd28ab6a 3231#ifdef CONFIG_PM
793b883e
SH		 3232 .suspend = sky2_suspend,
3233 .resume = sky2_resume,
cd28ab6a
SH		 3234#endif
3235};
3236
3237static int __init sky2_init_module(void)
3238{
50241c4c 3239 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3240}
3241
3242static void __exit sky2_cleanup_module(void)
3243{
3244 pci_unregister_driver(&sky2_driver);
3245}
3246
3247module_init(sky2_init_module);
3248module_exit(sky2_cleanup_module);
3249
3250MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3251MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3252MODULE_LICENSE("GPL");
5f4f9dc1 3253MODULE_VERSION(DRV_VERSION);
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