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[NETFILTER]: netbios conntrack: fix compile
[mirror_ubuntu-zesty-kernel.git] / drivers / net / sky2.c
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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
caa0371e 53#define DRV_VERSION "1.5"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
13210ce5 63#define RX_LE_SIZE 512
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
22e11703 68#define RX_BUF_WRITE 16
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
cd28ab6a
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 124 { 0 }
125};
793b883e 126
cd28ab6a
SH		 127MODULE_DEVICE_TABLE(pci, sky2_id_table);
128
129/* Avoid conditionals by using array */
130static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 132static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 133
92f965e8
SH		 134/* This driver supports yukon2 chipset only */
135static const char *yukon2_name[] = {
136 "XL", /* 0xb3 */
137 "EC Ultra", /* 0xb4 */
138 "UNKNOWN", /* 0xb5 */
139 "EC", /* 0xb6 */
140 "FE", /* 0xb7 */
793b883e
SH		 141};
142
793b883e 143/* Access to external PHY */
ef743d33 144static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 145{
146 int i;
147
148 gma_write16(hw, port, GM_SMI_DATA, val);
149 gma_write16(hw, port, GM_SMI_CTRL,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151
152 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 153 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 154 return 0;
793b883e 155 udelay(1);
cd28ab6a 156 }
ef743d33 157
793b883e 158 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 159 return -ETIMEDOUT;
cd28ab6a
SH		 160}
161
ef743d33 162static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 163{
164 int i;
165
793b883e 166 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 167 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168
169 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 170 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
171 *val = gma_read16(hw, port, GM_SMI_DATA);
172 return 0;
173 }
174
793b883e 175 udelay(1);
cd28ab6a
SH		 176 }
177
ef743d33
SH		 178 return -ETIMEDOUT;
179}
180
181static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
182{
183 u16 v;
184
185 if (__gm_phy_read(hw, port, reg, &v) != 0)
186 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
187 return v;
cd28ab6a
SH		 188}
189
2ccc99b7 190static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c
SH		 191{
192 u16 power_control;
193 u32 reg1;
194 int vaux;
5afa0a9c
SH		 195
196 pr_debug("sky2_set_power_state %d\n", state);
197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198
56a645cc 199 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 200 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 201 (power_control & PCI_PM_CAP_PME_D3cold);
202
56a645cc 203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 204
205 power_control |= PCI_PM_CTRL_PME_STATUS;
206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
207
208 switch (state) {
209 case PCI_D0:
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw, B0_POWER_CTRL,
212 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213
214 /* disable Core Clock Division, */
215 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216
217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 /* enable bits are inverted */
219 sky2_write8(hw, B2_Y2_CLK_GATE,
220 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 else
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225
226 /* Turn off phy power saving */
56a645cc 227 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229
d571b694 230 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
233 if (hw->ports > 1)
234 reg1 |= PCI_Y2_PHY2_COMA;
235 }
8d3d35b4
SH		 236 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
237 udelay(100);
977bdf06
SH		 238
239 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
56a645cc
SH		 240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
241 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 242 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 243 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
244 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 245 }
246
5afa0a9c
SH		 247 break;
248
249 case PCI_D3hot:
250 case PCI_D3cold:
251 /* Turn on phy power saving */
56a645cc 252 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 253 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
254 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
255 else
256 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 257 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
afa195da 258 udelay(100);
5afa0a9c
SH		 259
260 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
261 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
262 else
263 /* enable bits are inverted */
264 sky2_write8(hw, B2_Y2_CLK_GATE,
265 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
266 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
267 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
268
269 /* switch power to VAUX */
270 if (vaux && state != PCI_D3cold)
271 sky2_write8(hw, B0_POWER_CTRL,
272 (PC_VAUX_ENA | PC_VCC_ENA |
273 PC_VAUX_ON | PC_VCC_OFF));
274 break;
275 default:
276 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c
SH		 277 }
278
56a645cc 279 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c
SH		 281}
282
cd28ab6a
SH		 283static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
284{
285 u16 reg;
286
287 /* disable all GMAC IRQ's */
288 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
289 /* disable PHY IRQs */
290 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 291
cd28ab6a
SH		 292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300}
301
302static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
303{
304 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 305 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 306
ed6d32c7 307 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 308 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 309 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
310
311 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 312 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 313 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
314
315 if (hw->chip_id == CHIP_ID_YUKON_EC)
316 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
317 else
318 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
319
320 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
321 }
322
323 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
324 if (hw->copper) {
325 if (hw->chip_id == CHIP_ID_YUKON_FE) {
326 /* enable automatic crossover */
327 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
328 } else {
329 /* disable energy detect */
330 ctrl &= ~PHY_M_PC_EN_DET_MSK;
331
332 /* enable automatic crossover */
333 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
334
335 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 336 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 337 ctrl &= ~PHY_M_PC_DSC_MSK;
338 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
339 }
340 }
341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
342 } else {
343 /* workaround for deviation #4.88 (CRC errors) */
344 /* disable Automatic Crossover */
345
346 ctrl &= ~PHY_M_PC_MDIX_MSK;
347 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348
349 if (hw->chip_id == CHIP_ID_YUKON_XL) {
350 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 ctrl &= ~PHY_M_MAC_MD_MSK;
354 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
356
357 /* select page 1 to access Fiber registers */
358 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
359 }
cd28ab6a
SH		 360 }
361
362 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
363 if (sky2->autoneg == AUTONEG_DISABLE)
364 ctrl &= ~PHY_CT_ANE;
365 else
366 ctrl |= PHY_CT_ANE;
367
368 ctrl |= PHY_CT_RESET;
369 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
370
371 ctrl = 0;
372 ct1000 = 0;
373 adv = PHY_AN_CSMA;
374
375 if (sky2->autoneg == AUTONEG_ENABLE) {
376 if (hw->copper) {
377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
793b883e 389 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 390 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
391
392 /* Set Flow-control capabilities */
393 if (sky2->tx_pause && sky2->rx_pause)
793b883e 394 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 395 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 396 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 397 else if (!sky2->rx_pause && sky2->tx_pause)
398 adv |= PHY_AN_PAUSE_ASYM; /* local */
399
400 /* Restart Auto-negotiation */
401 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
402 } else {
403 /* forced speed/duplex settings */
404 ct1000 = PHY_M_1000C_MSE;
405
406 if (sky2->duplex == DUPLEX_FULL)
407 ctrl |= PHY_CT_DUP_MD;
408
409 switch (sky2->speed) {
410 case SPEED_1000:
411 ctrl |= PHY_CT_SP1000;
412 break;
413 case SPEED_100:
414 ctrl |= PHY_CT_SP100;
415 break;
416 }
417
418 ctrl |= PHY_CT_RESET;
419 }
420
421 if (hw->chip_id != CHIP_ID_YUKON_FE)
422 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
423
424 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
425 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
426
427 /* Setup Phy LED's */
428 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
429 ledover = 0;
430
431 switch (hw->chip_id) {
432 case CHIP_ID_YUKON_FE:
433 /* on 88E3082 these bits are at 11..9 (shifted left) */
434 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
435
436 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
437
438 /* delete ACT LED control bits */
439 ctrl &= ~PHY_M_FELP_LED1_MSK;
440 /* change ACT LED control to blink mode */
441 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
442 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
443 break;
444
445 case CHIP_ID_YUKON_XL:
793b883e 446 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 447
448 /* select page 3 to access LED control register */
449 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
450
451 /* set LED Function Control register */
ed6d32c7
SH		 452 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
453 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
454 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
455 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
456 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 457
458 /* set Polarity Control register */
459 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 460 (PHY_M_POLC_LS1_P_MIX(4) |
461 PHY_M_POLC_IS0_P_MIX(4) |
462 PHY_M_POLC_LOS_CTRL(2) |
463 PHY_M_POLC_INIT_CTRL(2) |
464 PHY_M_POLC_STA1_CTRL(2) |
465 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 466
467 /* restore page register */
793b883e 468 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 469 break;
ed6d32c7
SH		 470 case CHIP_ID_YUKON_EC_U:
471 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
472
473 /* select page 3 to access LED control register */
474 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
475
476 /* set LED Function Control register */
477 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
478 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
479 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
480 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
481 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
482
483 /* set Blink Rate in LED Timer Control Register */
484 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
485 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
486 /* restore page register */
487 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
488 break;
cd28ab6a
SH		 489
490 default:
491 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
492 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
493 /* turn off the Rx LED (LED_RX) */
494 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
495 }
496
ed6d32c7 497 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 498 /* apply fixes in PHY AFE */
ed6d32c7
SH		 499 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
500 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
501
977bdf06 502 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 503 gm_phy_write(hw, port, 0x18, 0xaa99);
504 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 505
977bdf06 506 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 507 gm_phy_write(hw, port, 0x18, 0xa204);
508 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 509
510 /* set page register to 0 */
ed6d32c7 511 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 512 } else {
513 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 514
977bdf06
SH		 515 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
516 /* turn on 100 Mbps LED (LED_LINK100) */
517 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
518 }
cd28ab6a 519
977bdf06
SH		 520 if (ledover)
521 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
522
523 }
d571b694 524 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 525 if (sky2->autoneg == AUTONEG_ENABLE)
526 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
527 else
528 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
529}
530
1b537565
SH		 531/* Force a renegotiation */
532static void sky2_phy_reinit(struct sky2_port *sky2)
533{
e07b1aa8 534 spin_lock_bh(&sky2->phy_lock);
1b537565 535 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 536 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 537}
538
cd28ab6a
SH		 539static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
540{
541 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
542 u16 reg;
543 int i;
544 const u8 *addr = hw->dev[port]->dev_addr;
545
42eeea01
SH		 546 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
547 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 548
549 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
550
793b883e 551 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 552 /* WA DEV_472 -- looks like crossed wires on port 2 */
553 /* clear GMAC 1 Control reset */
554 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
555 do {
556 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
557 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
558 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
559 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
560 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
561 }
562
cd28ab6a
SH		 563 if (sky2->autoneg == AUTONEG_DISABLE) {
564 reg = gma_read16(hw, port, GM_GP_CTRL);
565 reg |= GM_GPCR_AU_ALL_DIS;
566 gma_write16(hw, port, GM_GP_CTRL, reg);
567 gma_read16(hw, port, GM_GP_CTRL);
568
cd28ab6a
SH		 569 switch (sky2->speed) {
570 case SPEED_1000:
6f4c56b2 571 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 572 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 573 break;
cd28ab6a 574 case SPEED_100:
6f4c56b2 575 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 576 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 577 break;
578 case SPEED_10:
579 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
580 break;
cd28ab6a
SH		 581 }
582
583 if (sky2->duplex == DUPLEX_FULL)
584 reg |= GM_GPCR_DUP_FULL;
ed6d32c7
SH		 585
586 /* turn off pause in 10/100mbps half duplex */
587 else if (sky2->speed != SPEED_1000 &&
588 hw->chip_id != CHIP_ID_YUKON_EC_U)
589 sky2->tx_pause = sky2->rx_pause = 0;
cd28ab6a
SH		 590 } else
591 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
592
593 if (!sky2->tx_pause && !sky2->rx_pause) {
594 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 595 reg |=
596 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
597 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 598 /* disable Rx flow-control */
599 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
600 }
601
602 gma_write16(hw, port, GM_GP_CTRL, reg);
603
793b883e 604 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 605
e07b1aa8 606 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 607 sky2_phy_init(hw, port);
e07b1aa8 608 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 609
610 /* MIB clear */
611 reg = gma_read16(hw, port, GM_PHY_ADDR);
612 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
613
43f2f104
SH		 614 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
615 gma_read16(hw, port, i);
cd28ab6a
SH		 616 gma_write16(hw, port, GM_PHY_ADDR, reg);
617
618 /* transmit control */
619 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
620
621 /* receive control reg: unicast + multicast + no FCS */
622 gma_write16(hw, port, GM_RX_CTRL,
793b883e 623 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 624
625 /* transmit flow control */
626 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
627
628 /* transmit parameter */
629 gma_write16(hw, port, GM_TX_PARAM,
630 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
631 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
632 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
633 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
634
635 /* serial mode register */
636 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 637 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 638
6b1a3aef 639 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 640 reg |= GM_SMOD_JUMBO_ENA;
641
642 gma_write16(hw, port, GM_SERIAL_MODE, reg);
643
cd28ab6a
SH		 644 /* virtual address for data */
645 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
646
793b883e
SH		 647 /* physical address: used for pause frames */
648 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
649
650 /* ignore counter overflows */
cd28ab6a
SH		 651 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
652 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
653 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
654
655 /* Configure Rx MAC FIFO */
656 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 657 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
658 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 659
d571b694 660 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 661 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 662
793b883e
SH		 663 /* Set threshold to 0xa (64 bytes)
664 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 665 */
666 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
667
668 /* Configure Tx MAC FIFO */
669 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
670 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 671
672 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
673 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
674 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
675 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
676 /* set Tx GMAC FIFO Almost Empty Threshold */
677 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
678 /* Disable Store & Forward mode for TX */
679 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
680 }
681 }
682
cd28ab6a
SH		 683}
684
1c28f6ba
SH		 685/* Assign Ram Buffer allocation.
686 * start and end are in units of 4k bytes
687 * ram registers are in units of 64bit words
688 */
689static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 690{
1c28f6ba 691 u32 start, end;
cd28ab6a 692
1c28f6ba
SH		 693 start = startk * 4096/8;
694 end = (endk * 4096/8) - 1;
793b883e 695
cd28ab6a
SH		 696 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
697 sky2_write32(hw, RB_ADDR(q, RB_START), start);
698 sky2_write32(hw, RB_ADDR(q, RB_END), end);
699 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
700 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
701
702 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 703 u32 space = (endk - startk) * 4096/8;
704 u32 tp = space - space/4;
793b883e 705
1c28f6ba
SH		 706 /* On receive queue's set the thresholds
707 * give receiver priority when > 3/4 full
708 * send pause when down to 2K
709 */
710 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
711 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 712
1c28f6ba
SH		 713 tp = space - 2048/8;
714 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
715 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 716 } else {
717 /* Enable store & forward on Tx queue's because
718 * Tx FIFO is only 1K on Yukon
719 */
720 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
721 }
722
723 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 724 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 725}
726
cd28ab6a 727/* Setup Bus Memory Interface */
af4ed7e6 728static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 729{
730 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
731 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
732 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 733 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 734}
735
cd28ab6a
SH		 736/* Setup prefetch unit registers. This is the interface between
737 * hardware and driver list elements
738 */
8cc048e3 739static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 740 u64 addr, u32 last)
741{
cd28ab6a
SH		 742 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
743 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
744 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
745 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
746 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
747 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 748
749 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 750}
751
793b883e
SH		 752static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
753{
754 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
755
cb5d9547 756 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 757 return le;
758}
cd28ab6a 759
290d4de5
SH		 760/* Update chip's next pointer */
761static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 762{
762c2de2 763 wmb();
290d4de5 764 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 765 mmiowb();
cd28ab6a
SH		 766}
767
793b883e 768
cd28ab6a
SH		 769static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
770{
771 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 772 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 773 return le;
774}
775
a018e330
SH		 776/* Return high part of DMA address (could be 32 or 64 bit) */
777static inline u32 high32(dma_addr_t a)
778{
a036119f 779 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 780}
781
793b883e 782/* Build description to hardware about buffer */
28bd181a 783static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 784{
785 struct sky2_rx_le *le;
734d1868
SH		 786 u32 hi = high32(map);
787 u16 len = sky2->rx_bufsize;
cd28ab6a 788
793b883e 789 if (sky2->rx_addr64 != hi) {
cd28ab6a 790 le = sky2_next_rx(sky2);
793b883e 791 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 792 le->ctrl = 0;
793 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 794 sky2->rx_addr64 = high32(map + len);
cd28ab6a 795 }
793b883e 796
cd28ab6a 797 le = sky2_next_rx(sky2);
734d1868
SH		 798 le->addr = cpu_to_le32((u32) map);
799 le->length = cpu_to_le16(len);
cd28ab6a
SH		 800 le->ctrl = 0;
801 le->opcode = OP_PACKET | HW_OWNER;
802}
803
793b883e 804
cd28ab6a
SH		 805/* Tell chip where to start receive checksum.
806 * Actually has two checksums, but set both same to avoid possible byte
807 * order problems.
808 */
793b883e 809static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 810{
811 struct sky2_rx_le *le;
812
cd28ab6a 813 le = sky2_next_rx(sky2);
793b883e 814 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 815 le->ctrl = 0;
816 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 817
793b883e
SH		 818 sky2_write32(sky2->hw,
819 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
820 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 821
822}
823
6b1a3aef
SH		 824/*
825 * The RX Stop command will not work for Yukon-2 if the BMU does not
826 * reach the end of packet and since we can't make sure that we have
827 * incoming data, we must reset the BMU while it is not doing a DMA
828 * transfer. Since it is possible that the RX path is still active,
829 * the RX RAM buffer will be stopped first, so any possible incoming
830 * data will not trigger a DMA. After the RAM buffer is stopped, the
831 * BMU is polled until any DMA in progress is ended and only then it
832 * will be reset.
833 */
834static void sky2_rx_stop(struct sky2_port *sky2)
835{
836 struct sky2_hw *hw = sky2->hw;
837 unsigned rxq = rxqaddr[sky2->port];
838 int i;
839
840 /* disable the RAM Buffer receive queue */
841 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
842
843 for (i = 0; i < 0xffff; i++)
844 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
845 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
846 goto stopped;
847
848 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
849 sky2->netdev->name);
850stopped:
851 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
852
853 /* reset the Rx prefetch unit */
854 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
855}
793b883e 856
d571b694 857/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 858static void sky2_rx_clean(struct sky2_port *sky2)
859{
860 unsigned i;
861
862 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 863 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 864 struct ring_info *re = sky2->rx_ring + i;
865
866 if (re->skb) {
793b883e 867 pci_unmap_single(sky2->hw->pdev,
734d1868 868 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 869 PCI_DMA_FROMDEVICE);
870 kfree_skb(re->skb);
871 re->skb = NULL;
872 }
873 }
874}
875
ef743d33
SH		 876/* Basic MII support */
877static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
878{
879 struct mii_ioctl_data *data = if_mii(ifr);
880 struct sky2_port *sky2 = netdev_priv(dev);
881 struct sky2_hw *hw = sky2->hw;
882 int err = -EOPNOTSUPP;
883
884 if (!netif_running(dev))
885 return -ENODEV; /* Phy still in reset */
886
d89e1343 887 switch (cmd) {
ef743d33
SH		 888 case SIOCGMIIPHY:
889 data->phy_id = PHY_ADDR_MARV;
890
891 /* fallthru */
892 case SIOCGMIIREG: {
893 u16 val = 0;
91c86df5 894
e07b1aa8 895 spin_lock_bh(&sky2->phy_lock);
ef743d33 896 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 897 spin_unlock_bh(&sky2->phy_lock);
91c86df5 898
ef743d33
SH		 899 data->val_out = val;
900 break;
901 }
902
903 case SIOCSMIIREG:
904 if (!capable(CAP_NET_ADMIN))
905 return -EPERM;
906
e07b1aa8 907 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 908 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
909 data->val_in);
e07b1aa8 910 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 911 break;
912 }
913 return err;
914}
915
d1f13708
SH		 916#ifdef SKY2_VLAN_TAG_USED
917static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
918{
919 struct sky2_port *sky2 = netdev_priv(dev);
920 struct sky2_hw *hw = sky2->hw;
921 u16 port = sky2->port;
d1f13708 922
302d1252 923 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 924
925 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
926 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
927 sky2->vlgrp = grp;
928
302d1252 929 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 930}
931
932static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
933{
934 struct sky2_port *sky2 = netdev_priv(dev);
935 struct sky2_hw *hw = sky2->hw;
936 u16 port = sky2->port;
d1f13708 937
302d1252 938 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 939
940 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
941 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
942 if (sky2->vlgrp)
943 sky2->vlgrp->vlan_devices[vid] = NULL;
944
302d1252 945 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 946}
947#endif
948
82788c7a
SH		 949/*
950 * It appears the hardware has a bug in the FIFO logic that
951 * cause it to hang if the FIFO gets overrun and the receive buffer
952 * is not aligned. ALso alloc_skb() won't align properly if slab
953 * debugging is enabled.
954 */
955static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
956{
957 struct sk_buff *skb;
958
959 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
960 if (likely(skb)) {
961 unsigned long p = (unsigned long) skb->data;
4a15d56f 962 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 963 }
964
965 return skb;
966}
967
cd28ab6a
SH		 968/*
969 * Allocate and setup receiver buffer pool.
970 * In case of 64 bit dma, there are 2X as many list elements
971 * available as ring entries
972 * and need to reserve one list element so we don't wrap around.
973 */
6b1a3aef 974static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 975{
6b1a3aef 976 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 977 unsigned rxq = rxqaddr[sky2->port];
978 int i;
a1433ac4 979 unsigned thresh;
cd28ab6a 980
6b1a3aef 981 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 982 sky2_qset(hw, rxq);
977bdf06
SH		 983
984 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
985 /* MAC Rx RAM Read is controlled by hardware */
986 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
987 }
988
6b1a3aef
SH		 989 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
990
991 rx_set_checksum(sky2);
793b883e 992 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 993 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 994
82788c7a 995 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 996 if (!re->skb)
997 goto nomem;
998
6b1a3aef 999 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1000 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1001 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1002 }
1003
a1433ac4
SH		 1004
1005 /*
1006 * The receiver hangs if it receives frames larger than the
1007 * packet buffer. As a workaround, truncate oversize frames, but
1008 * the register is limited to 9 bits, so if you do frames > 2052
1009 * you better get the MTU right!
1010 */
1011 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1012 if (thresh > 0x1ff)
1013 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1014 else {
1015 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1016 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1017 }
1018
70f1be48 1019
6b1a3aef
SH		 1020 /* Tell chip about available buffers */
1021 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1022 return 0;
1023nomem:
1024 sky2_rx_clean(sky2);
1025 return -ENOMEM;
1026}
1027
1028/* Bring up network interface. */
1029static int sky2_up(struct net_device *dev)
1030{
1031 struct sky2_port *sky2 = netdev_priv(dev);
1032 struct sky2_hw *hw = sky2->hw;
1033 unsigned port = sky2->port;
e07b1aa8 1034 u32 ramsize, rxspace, imask;
ee7abb04 1035 int cap, err = -ENOMEM;
843a46f4 1036 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1037
ee7abb04
SH		 1038 /*
1039 * On dual port PCI-X card, there is an problem where status
1040 * can be received out of order due to split transactions
843a46f4 1041 */
ee7abb04
SH		 1042 if (otherdev && netif_running(otherdev) &&
1043 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1044 struct sky2_port *osky2 = netdev_priv(otherdev);
1045 u16 cmd;
1046
1047 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1048 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1049 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1050
1051 sky2->rx_csum = 0;
1052 osky2->rx_csum = 0;
1053 }
843a46f4 1054
cd28ab6a
SH		 1055 if (netif_msg_ifup(sky2))
1056 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1057
1058 /* must be power of 2 */
1059 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1060 TX_RING_SIZE *
1061 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1062 &sky2->tx_le_map);
1063 if (!sky2->tx_le)
1064 goto err_out;
1065
6cdbbdf3 1066 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1067 GFP_KERNEL);
1068 if (!sky2->tx_ring)
1069 goto err_out;
1070 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1071
1072 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1073 &sky2->rx_le_map);
1074 if (!sky2->rx_le)
1075 goto err_out;
1076 memset(sky2->rx_le, 0, RX_LE_BYTES);
1077
6cdbbdf3 1078 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1079 GFP_KERNEL);
1080 if (!sky2->rx_ring)
1081 goto err_out;
1082
1083 sky2_mac_init(hw, port);
1084
1c28f6ba
SH		 1085 /* Determine available ram buffer space (in 4K blocks).
1086 * Note: not sure about the FE setting below yet
1087 */
1088 if (hw->chip_id == CHIP_ID_YUKON_FE)
1089 ramsize = 4;
1090 else
1091 ramsize = sky2_read8(hw, B2_E_0);
1092
1093 /* Give transmitter one third (rounded up) */
1094 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1095
cd28ab6a 1096 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1097 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1098
793b883e
SH		 1099 /* Make sure SyncQ is disabled */
1100 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1101 RB_RST_SET);
1102
af4ed7e6 1103 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1104
977bdf06
SH		 1105 /* Set almost empty threshold */
1106 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1107 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1108
6b1a3aef
SH		 1109 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1110 TX_RING_SIZE - 1);
cd28ab6a 1111
6b1a3aef 1112 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1113 if (err)
1114 goto err_out;
1115
cd28ab6a 1116 /* Enable interrupts from phy/mac for port */
e07b1aa8 1117 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1118 imask |= portirq_msk[port];
e07b1aa8
SH		 1119 sky2_write32(hw, B0_IMSK, imask);
1120
cd28ab6a
SH		 1121 return 0;
1122
1123err_out:
1b537565 1124 if (sky2->rx_le) {
cd28ab6a
SH		 1125 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1126 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1127 sky2->rx_le = NULL;
1128 }
1129 if (sky2->tx_le) {
cd28ab6a
SH		 1130 pci_free_consistent(hw->pdev,
1131 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1132 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1133 sky2->tx_le = NULL;
1134 }
1135 kfree(sky2->tx_ring);
1136 kfree(sky2->rx_ring);
cd28ab6a 1137
1b537565
SH		 1138 sky2->tx_ring = NULL;
1139 sky2->rx_ring = NULL;
cd28ab6a
SH		 1140 return err;
1141}
1142
793b883e
SH		 1143/* Modular subtraction in ring */
1144static inline int tx_dist(unsigned tail, unsigned head)
1145{
cb5d9547 1146 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1147}
cd28ab6a 1148
793b883e
SH		 1149/* Number of list elements available for next tx */
1150static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1151{
793b883e 1152 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1153}
1154
793b883e 1155/* Estimate of number of transmit list elements required */
28bd181a 1156static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1157{
793b883e
SH		 1158 unsigned count;
1159
1160 count = sizeof(dma_addr_t) / sizeof(u32);
1161 count += skb_shinfo(skb)->nr_frags * count;
1162
89114afd 1163 if (skb_is_gso(skb))
793b883e
SH		 1164 ++count;
1165
0e3ff6aa 1166 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1167 ++count;
1168
1169 return count;
cd28ab6a
SH		 1170}
1171
793b883e
SH		 1172/*
1173 * Put one packet in ring for transmit.
1174 * A single packet can generate multiple list elements, and
1175 * the number of ring elements will probably be less than the number
1176 * of list elements used.
f2e46561
SH		 1177 *
1178 * No BH disabling for tx_lock here (like tg3)
793b883e 1179 */
cd28ab6a
SH		 1180static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1181{
1182 struct sky2_port *sky2 = netdev_priv(dev);
1183 struct sky2_hw *hw = sky2->hw;
d1f13708 1184 struct sky2_tx_le *le = NULL;
6cdbbdf3 1185 struct tx_ring_info *re;
cd28ab6a 1186 unsigned i, len;
b19666d9 1187 int avail;
cd28ab6a
SH		 1188 dma_addr_t mapping;
1189 u32 addr64;
1190 u16 mss;
1191 u8 ctrl;
1192
302d1252
SH		 1193 /* No BH disabling for tx_lock here. We are running in BH disabled
1194 * context and TX reclaim runs via poll inside of a software
1195 * interrupt, and no related locks in IRQ processing.
1196 */
f2e46561 1197 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1198 return NETDEV_TX_LOCKED;
1199
793b883e 1200 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1201 /* There is a known but harmless race with lockless tx
1202 * and netif_stop_queue.
1203 */
1204 if (!netif_queue_stopped(dev)) {
1205 netif_stop_queue(dev);
3be92a70
SH		 1206 if (net_ratelimit())
1207 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1208 dev->name);
8c463ef7 1209 }
f2e46561 1210 spin_unlock(&sky2->tx_lock);
cd28ab6a 1211
cd28ab6a
SH		 1212 return NETDEV_TX_BUSY;
1213 }
1214
793b883e 1215 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1216 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1217 dev->name, sky2->tx_prod, skb->len);
1218
cd28ab6a
SH		 1219 len = skb_headlen(skb);
1220 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1221 addr64 = high32(mapping);
793b883e
SH		 1222
1223 re = sky2->tx_ring + sky2->tx_prod;
1224
a018e330
SH		 1225 /* Send high bits if changed or crosses boundary */
1226 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1227 le = get_tx_le(sky2);
1228 le->tx.addr = cpu_to_le32(addr64);
1229 le->ctrl = 0;
1230 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1231 sky2->tx_addr64 = high32(mapping + len);
793b883e 1232 }
cd28ab6a
SH		 1233
1234 /* Check for TCP Segmentation Offload */
7967168c 1235 mss = skb_shinfo(skb)->gso_size;
793b883e 1236 if (mss != 0) {
cd28ab6a
SH		 1237 /* just drop the packet if non-linear expansion fails */
1238 if (skb_header_cloned(skb) &&
1239 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
15240072 1240 dev_kfree_skb(skb);
793b883e 1241 goto out_unlock;
cd28ab6a
SH		 1242 }
1243
1244 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1245 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1246 mss += ETH_HLEN;
793b883e 1247 }
cd28ab6a 1248
793b883e 1249 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1250 le = get_tx_le(sky2);
1251 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1252 le->tx.tso.rsvd = 0;
cd28ab6a 1253 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1254 le->ctrl = 0;
793b883e 1255 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1256 }
1257
cd28ab6a 1258 ctrl = 0;
d1f13708
SH		 1259#ifdef SKY2_VLAN_TAG_USED
1260 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1261 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1262 if (!le) {
1263 le = get_tx_le(sky2);
1264 le->tx.addr = 0;
1265 le->opcode = OP_VLAN|HW_OWNER;
1266 le->ctrl = 0;
1267 } else
1268 le->opcode |= OP_VLAN;
1269 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1270 ctrl |= INS_VLAN;
1271 }
1272#endif
1273
1274 /* Handle TCP checksum offload */
cd28ab6a 1275 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1276 u16 hdr = skb->h.raw - skb->data;
1277 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1278
1279 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1280 if (skb->nh.iph->protocol == IPPROTO_UDP)
1281 ctrl |= UDPTCP;
1282
1283 le = get_tx_le(sky2);
1284 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1285 le->tx.csum.offset = cpu_to_le16(offset);
1286 le->length = 0; /* initial checksum value */
cd28ab6a 1287 le->ctrl = 1; /* one packet */
793b883e 1288 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1289 }
1290
1291 le = get_tx_le(sky2);
1292 le->tx.addr = cpu_to_le32((u32) mapping);
1293 le->length = cpu_to_le16(len);
1294 le->ctrl = ctrl;
793b883e 1295 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1296
793b883e 1297 /* Record the transmit mapping info */
cd28ab6a 1298 re->skb = skb;
6cdbbdf3 1299 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1300
1301 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1302 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1303 struct tx_ring_info *fre;
cd28ab6a
SH		 1304
1305 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1306 frag->size, PCI_DMA_TODEVICE);
a036119f 1307 addr64 = high32(mapping);
793b883e
SH		 1308 if (addr64 != sky2->tx_addr64) {
1309 le = get_tx_le(sky2);
1310 le->tx.addr = cpu_to_le32(addr64);
1311 le->ctrl = 0;
1312 le->opcode = OP_ADDR64 | HW_OWNER;
1313 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1314 }
1315
1316 le = get_tx_le(sky2);
1317 le->tx.addr = cpu_to_le32((u32) mapping);
1318 le->length = cpu_to_le16(frag->size);
1319 le->ctrl = ctrl;
793b883e 1320 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1321
793b883e 1322 fre = sky2->tx_ring
cb5d9547 1323 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1324 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1325 }
6cdbbdf3 1326
793b883e 1327 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1328 le->ctrl |= EOP;
1329
b19666d9
SH		 1330 avail = tx_avail(sky2);
1331 if (mss != 0 || avail < TX_MIN_PENDING) {
1332 le->ctrl |= FRC_STAT;
1333 if (avail <= MAX_SKB_TX_LE)
1334 netif_stop_queue(dev);
1335 }
1336
290d4de5 1337 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1338
793b883e 1339out_unlock:
f2e46561 1340 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1341
1342 dev->trans_start = jiffies;
1343 return NETDEV_TX_OK;
1344}
1345
cd28ab6a 1346/*
793b883e
SH		 1347 * Free ring elements from starting at tx_cons until "done"
1348 *
1349 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1350 * buffers; these are deferred until completion.
cd28ab6a 1351 */
d11c13e7 1352static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1353{
d11c13e7 1354 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1355 struct pci_dev *pdev = sky2->hw->pdev;
1356 u16 nxt, put;
793b883e 1357 unsigned i;
cd28ab6a 1358
0e3ff6aa 1359 BUG_ON(done >= TX_RING_SIZE);
2224795d 1360
d11c13e7 1361 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1362 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1363 dev->name, done);
cd28ab6a 1364
af2a58ac
SH		 1365 for (put = sky2->tx_cons; put != done; put = nxt) {
1366 struct tx_ring_info *re = sky2->tx_ring + put;
1367 struct sk_buff *skb = re->skb;
cd28ab6a 1368
d89e1343 1369 nxt = re->idx;
af2a58ac 1370 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1371 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1372
793b883e 1373 /* Check for partial status */
af2a58ac
SH		 1374 if (tx_dist(put, done) < tx_dist(put, nxt))
1375 break;
793b883e
SH		 1376
1377 skb = re->skb;
af2a58ac 1378 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1379 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1380
1381 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1382 struct tx_ring_info *fre;
cb5d9547 1383 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1384 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1385 skb_shinfo(skb)->frags[i].size,
734d1868 1386 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1387 }
1388
15240072 1389 dev_kfree_skb(skb);
793b883e 1390 }
793b883e 1391
af2a58ac 1392 sky2->tx_cons = put;
22e11703 1393 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1394 netif_wake_queue(dev);
cd28ab6a
SH		 1395}
1396
1397/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1398static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1399{
302d1252 1400 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1401 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1402 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1403}
1404
1405/* Network shutdown */
1406static int sky2_down(struct net_device *dev)
1407{
1408 struct sky2_port *sky2 = netdev_priv(dev);
1409 struct sky2_hw *hw = sky2->hw;
1410 unsigned port = sky2->port;
1411 u16 ctrl;
e07b1aa8 1412 u32 imask;
cd28ab6a 1413
1b537565
SH		 1414 /* Never really got started! */
1415 if (!sky2->tx_le)
1416 return 0;
1417
cd28ab6a
SH		 1418 if (netif_msg_ifdown(sky2))
1419 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1420
018d1c66 1421 /* Stop more packets from being queued */
cd28ab6a
SH		 1422 netif_stop_queue(dev);
1423
793b883e
SH		 1424 sky2_phy_reset(hw, port);
1425
cd28ab6a
SH		 1426 /* Stop transmitter */
1427 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1428 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1429
1430 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1431 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1432
1433 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1434 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1435 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1436
1437 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1438
1439 /* Workaround shared GMAC reset */
793b883e
SH		 1440 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1441 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1442 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1443
1444 /* Disable Force Sync bit and Enable Alloc bit */
1445 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1446 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1447
1448 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1449 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1450 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1451
1452 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1453 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1454 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1455
1456 /* Reset the Tx prefetch units */
1457 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1458 PREF_UNIT_RST_SET);
1459
1460 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1461
6b1a3aef 1462 sky2_rx_stop(sky2);
cd28ab6a
SH		 1463
1464 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1465 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1466
e07b1aa8
SH		 1467 /* Disable port IRQ */
1468 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1469 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1470 sky2_write32(hw, B0_IMSK, imask);
1471
d571b694 1472 /* turn off LED's */
cd28ab6a
SH		 1473 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1474
018d1c66
SH		 1475 synchronize_irq(hw->pdev->irq);
1476
cd28ab6a
SH		 1477 sky2_tx_clean(sky2);
1478 sky2_rx_clean(sky2);
1479
1480 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1481 sky2->rx_le, sky2->rx_le_map);
1482 kfree(sky2->rx_ring);
1483
1484 pci_free_consistent(hw->pdev,
1485 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1486 sky2->tx_le, sky2->tx_le_map);
1487 kfree(sky2->tx_ring);
1488
1b537565
SH		 1489 sky2->tx_le = NULL;
1490 sky2->rx_le = NULL;
1491
1492 sky2->rx_ring = NULL;
1493 sky2->tx_ring = NULL;
1494
cd28ab6a
SH		 1495 return 0;
1496}
1497
1498static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1499{
793b883e
SH		 1500 if (!hw->copper)
1501 return SPEED_1000;
1502
cd28ab6a
SH		 1503 if (hw->chip_id == CHIP_ID_YUKON_FE)
1504 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1505
1506 switch (aux & PHY_M_PS_SPEED_MSK) {
1507 case PHY_M_PS_SPEED_1000:
1508 return SPEED_1000;
1509 case PHY_M_PS_SPEED_100:
1510 return SPEED_100;
1511 default:
1512 return SPEED_10;
1513 }
1514}
1515
1516static void sky2_link_up(struct sky2_port *sky2)
1517{
1518 struct sky2_hw *hw = sky2->hw;
1519 unsigned port = sky2->port;
1520 u16 reg;
1521
1522 /* Enable Transmit FIFO Underrun */
793b883e 1523 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1524
1525 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1526 if (sky2->autoneg == AUTONEG_DISABLE) {
1527 reg |= GM_GPCR_AU_ALL_DIS;
1528
1529 /* Is write/read necessary? Copied from sky2_mac_init */
1530 gma_write16(hw, port, GM_GP_CTRL, reg);
1531 gma_read16(hw, port, GM_GP_CTRL);
1532
1533 switch (sky2->speed) {
1534 case SPEED_1000:
1535 reg &= ~GM_GPCR_SPEED_100;
1536 reg |= GM_GPCR_SPEED_1000;
1537 break;
1538 case SPEED_100:
1539 reg &= ~GM_GPCR_SPEED_1000;
1540 reg |= GM_GPCR_SPEED_100;
1541 break;
1542 case SPEED_10:
1543 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1544 break;
1545 }
1546 } else
1547 reg &= ~GM_GPCR_AU_ALL_DIS;
1548
cd28ab6a
SH		 1549 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1550 reg |= GM_GPCR_DUP_FULL;
1551
cd28ab6a
SH		 1552 /* enable Rx/Tx */
1553 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1554 gma_write16(hw, port, GM_GP_CTRL, reg);
1555 gma_read16(hw, port, GM_GP_CTRL);
1556
1557 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1558
1559 netif_carrier_on(sky2->netdev);
1560 netif_wake_queue(sky2->netdev);
1561
1562 /* Turn on link LED */
793b883e 1563 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1564 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1565
ed6d32c7 1566 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1567 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1568 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1569
1570 switch(sky2->speed) {
1571 case SPEED_10:
1572 led |= PHY_M_LEDC_INIT_CTRL(7);
1573 break;
1574
1575 case SPEED_100:
1576 led |= PHY_M_LEDC_STA1_CTRL(7);
1577 break;
1578
1579 case SPEED_1000:
1580 led |= PHY_M_LEDC_STA0_CTRL(7);
1581 break;
1582 }
793b883e
SH		 1583
1584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1585 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1587 }
1588
cd28ab6a
SH		 1589 if (netif_msg_link(sky2))
1590 printk(KERN_INFO PFX
d571b694 1591 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1592 sky2->netdev->name, sky2->speed,
1593 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1594 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1595 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1596}
1597
1598static void sky2_link_down(struct sky2_port *sky2)
1599{
1600 struct sky2_hw *hw = sky2->hw;
1601 unsigned port = sky2->port;
1602 u16 reg;
1603
1604 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1605
1606 reg = gma_read16(hw, port, GM_GP_CTRL);
1607 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1608 gma_write16(hw, port, GM_GP_CTRL, reg);
1609 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1610
1611 if (sky2->rx_pause && !sky2->tx_pause) {
1612 /* restore Asymmetric Pause bit */
1613 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1614 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1615 | PHY_M_AN_ASP);
cd28ab6a
SH		 1616 }
1617
cd28ab6a
SH		 1618 netif_carrier_off(sky2->netdev);
1619 netif_stop_queue(sky2->netdev);
1620
1621 /* Turn on link LED */
1622 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1623
1624 if (netif_msg_link(sky2))
1625 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1626 sky2_phy_init(hw, port);
1627}
1628
793b883e
SH		 1629static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1630{
1631 struct sky2_hw *hw = sky2->hw;
1632 unsigned port = sky2->port;
1633 u16 lpa;
1634
1635 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1636
1637 if (lpa & PHY_M_AN_RF) {
1638 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1639 return -1;
1640 }
1641
1642 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1643 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1644 printk(KERN_ERR PFX "%s: master/slave fault",
1645 sky2->netdev->name);
1646 return -1;
1647 }
1648
1649 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1650 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1651 sky2->netdev->name);
1652 return -1;
1653 }
1654
1655 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1656
1657 sky2->speed = sky2_phy_speed(hw, aux);
1658
1659 /* Pause bits are offset (9..8) */
ed6d32c7 1660 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1661 aux >>= 6;
1662
1663 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1664 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1665
1666 if ((sky2->tx_pause || sky2->rx_pause)
1667 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1668 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1669 else
1670 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1671
1672 return 0;
1673}
cd28ab6a 1674
e07b1aa8
SH		 1675/* Interrupt from PHY */
1676static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1677{
e07b1aa8
SH		 1678 struct net_device *dev = hw->dev[port];
1679 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1680 u16 istatus, phystat;
1681
e07b1aa8
SH		 1682 spin_lock(&sky2->phy_lock);
1683 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1684 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1685
1686 if (!netif_running(dev))
1687 goto out;
cd28ab6a
SH		 1688
1689 if (netif_msg_intr(sky2))
1690 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1691 sky2->netdev->name, istatus, phystat);
1692
1693 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1694 if (sky2_autoneg_done(sky2, phystat) == 0)
1695 sky2_link_up(sky2);
1696 goto out;
1697 }
cd28ab6a 1698
793b883e
SH		 1699 if (istatus & PHY_M_IS_LSP_CHANGE)
1700 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1701
793b883e
SH		 1702 if (istatus & PHY_M_IS_DUP_CHANGE)
1703 sky2->duplex =
1704 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1705
793b883e
SH		 1706 if (istatus & PHY_M_IS_LST_CHANGE) {
1707 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1708 sky2_link_up(sky2);
793b883e
SH		 1709 else
1710 sky2_link_down(sky2);
cd28ab6a 1711 }
793b883e 1712out:
e07b1aa8 1713 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1714}
1715
302d1252
SH		 1716
1717/* Transmit timeout is only called if we are running, carries is up
1718 * and tx queue is full (stopped).
1719 */
cd28ab6a
SH		 1720static void sky2_tx_timeout(struct net_device *dev)
1721{
1722 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1723 struct sky2_hw *hw = sky2->hw;
1724 unsigned txq = txqaddr[sky2->port];
8f24664d 1725 u16 report, done;
cd28ab6a
SH		 1726
1727 if (netif_msg_timer(sky2))
1728 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1729
8f24664d
SH		 1730 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1731 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1732
8f24664d
SH		 1733 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1734 dev->name,
1735 sky2->tx_cons, sky2->tx_prod, report, done);
1736
1737 if (report != done) {
1738 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1739
1740 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1741 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1742 } else if (report != sky2->tx_cons) {
1743 printk(KERN_INFO PFX "status report lost?\n");
1744
1745 spin_lock_bh(&sky2->tx_lock);
1746 sky2_tx_complete(sky2, report);
1747 spin_unlock_bh(&sky2->tx_lock);
1748 } else {
1749 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1750
8f24664d
SH		 1751 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1752 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1753
1754 sky2_tx_clean(sky2);
1755
1756 sky2_qset(hw, txq);
1757 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1758 }
cd28ab6a
SH		 1759}
1760
734d1868 1761
70f1be48
SH		 1762/* Want receive buffer size to be multiple of 64 bits
1763 * and incl room for vlan and truncation
1764 */
734d1868
SH		 1765static inline unsigned sky2_buf_size(int mtu)
1766{
4a15d56f 1767 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1768}
1769
cd28ab6a
SH		 1770static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1771{
6b1a3aef
SH		 1772 struct sky2_port *sky2 = netdev_priv(dev);
1773 struct sky2_hw *hw = sky2->hw;
1774 int err;
1775 u16 ctl, mode;
e07b1aa8 1776 u32 imask;
cd28ab6a
SH		 1777
1778 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1779 return -EINVAL;
1780
5a5b1ea0
SH		 1781 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1782 return -EINVAL;
1783
6b1a3aef
SH		 1784 if (!netif_running(dev)) {
1785 dev->mtu = new_mtu;
1786 return 0;
1787 }
1788
e07b1aa8 1789 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1790 sky2_write32(hw, B0_IMSK, 0);
1791
018d1c66
SH		 1792 dev->trans_start = jiffies; /* prevent tx timeout */
1793 netif_stop_queue(dev);
1794 netif_poll_disable(hw->dev[0]);
1795
e07b1aa8
SH		 1796 synchronize_irq(hw->pdev->irq);
1797
6b1a3aef
SH		 1798 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1799 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1800 sky2_rx_stop(sky2);
1801 sky2_rx_clean(sky2);
cd28ab6a
SH		 1802
1803 dev->mtu = new_mtu;
734d1868 1804 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1805 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1806 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1807
1808 if (dev->mtu > ETH_DATA_LEN)
1809 mode |= GM_SMOD_JUMBO_ENA;
1810
1811 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1812
6b1a3aef 1813 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1814
6b1a3aef 1815 err = sky2_rx_start(sky2);
e07b1aa8 1816 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1817
1b537565
SH		 1818 if (err)
1819 dev_close(dev);
1820 else {
1821 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1822
1823 netif_poll_enable(hw->dev[0]);
1824 netif_wake_queue(dev);
1825 }
1826
cd28ab6a
SH		 1827 return err;
1828}
1829
1830/*
1831 * Receive one packet.
1832 * For small packets or errors, just reuse existing skb.
d571b694 1833 * For larger packets, get new buffer.
cd28ab6a 1834 */
d11c13e7 1835static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1836 u16 length, u32 status)
1837{
cd28ab6a 1838 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1839 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1840
1841 if (unlikely(netif_msg_rx_status(sky2)))
1842 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1843 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1844
793b883e 1845 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1846 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1847
42eeea01 1848 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1849 goto error;
1850
42eeea01
SH		 1851 if (!(status & GMR_FS_RX_OK))
1852 goto resubmit;
1853
70f1be48 1854 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1855 goto oversize;
1856
bdb5c58e 1857 if (length < copybreak) {
79e57d32
SH		 1858 skb = alloc_skb(length + 2, GFP_ATOMIC);
1859 if (!skb)
793b883e
SH		 1860 goto resubmit;
1861
79e57d32 1862 skb_reserve(skb, 2);
793b883e
SH		 1863 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1864 length, PCI_DMA_FROMDEVICE);
79e57d32 1865 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1866 skb->ip_summed = re->skb->ip_summed;
1867 skb->csum = re->skb->csum;
793b883e
SH		 1868 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1869 length, PCI_DMA_FROMDEVICE);
793b883e 1870 } else {
79e57d32
SH		 1871 struct sk_buff *nskb;
1872
82788c7a 1873 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1874 if (!nskb)
1875 goto resubmit;
cd28ab6a 1876
793b883e 1877 skb = re->skb;
79e57d32 1878 re->skb = nskb;
793b883e 1879 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1880 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1881 prefetch(skb->data);
cd28ab6a 1882
793b883e 1883 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1884 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1885 }
cd28ab6a 1886
79e57d32 1887 skb_put(skb, length);
793b883e 1888resubmit:
d11c13e7 1889 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1890 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1891
cd28ab6a
SH		 1892 return skb;
1893
6e15b712
SH		 1894oversize:
1895 ++sky2->net_stats.rx_over_errors;
1896 goto resubmit;
1897
cd28ab6a 1898error:
6e15b712
SH		 1899 ++sky2->net_stats.rx_errors;
1900
3be92a70 1901 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1902 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1903 sky2->netdev->name, status, length);
793b883e
SH		 1904
1905 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1906 sky2->net_stats.rx_length_errors++;
1907 if (status & GMR_FS_FRAGMENT)
1908 sky2->net_stats.rx_frame_errors++;
1909 if (status & GMR_FS_CRC_ERR)
1910 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1911 if (status & GMR_FS_RX_FF_OV)
1912 sky2->net_stats.rx_fifo_errors++;
79e57d32 1913
793b883e 1914 goto resubmit;
cd28ab6a
SH		 1915}
1916
e07b1aa8
SH		 1917/* Transmit complete */
1918static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1919{
e07b1aa8 1920 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1921
e07b1aa8
SH		 1922 if (netif_running(dev)) {
1923 spin_lock(&sky2->tx_lock);
1924 sky2_tx_complete(sky2, last);
1925 spin_unlock(&sky2->tx_lock);
2224795d 1926 }
cd28ab6a
SH		 1927}
1928
86fba634
SH		 1929/* Is status ring empty or is there more to do? */
1930static inline int sky2_more_work(const struct sky2_hw *hw)
1931{
1932 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1933}
1934
e07b1aa8
SH		 1935/* Process status response ring */
1936static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1937{
22e11703 1938 struct sky2_port *sky2;
e07b1aa8 1939 int work_done = 0;
22e11703 1940 unsigned buf_write[2] = { 0, 0 };
e71ebd73 1941 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1942
af2a58ac 1943 rmb();
bea86103 1944
e71ebd73 1945 while (hw->st_idx != hwidx) {
13210ce5
SH		 1946 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1947 struct net_device *dev;
cd28ab6a 1948 struct sk_buff *skb;
cd28ab6a
SH		 1949 u32 status;
1950 u16 length;
1951
cb5d9547 1952 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1953
e71ebd73
SH		 1954 BUG_ON(le->link >= 2);
1955 dev = hw->dev[le->link];
13210ce5
SH		 1956
1957 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1958 length = le->length;
1959 status = le->status;
cd28ab6a 1960
e71ebd73 1961 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1962 case OP_RXSTAT:
d11c13e7 1963 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1964 if (!skb)
1965 break;
13210ce5
SH		 1966
1967 skb->dev = dev;
1968 skb->protocol = eth_type_trans(skb, dev);
1969 dev->last_rx = jiffies;
1970
d1f13708
SH		 1971#ifdef SKY2_VLAN_TAG_USED
1972 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1973 vlan_hwaccel_receive_skb(skb,
1974 sky2->vlgrp,
1975 be16_to_cpu(sky2->rx_tag));
1976 } else
1977#endif
cd28ab6a 1978 netif_receive_skb(skb);
13210ce5 1979
22e11703
SH		 1980 /* Update receiver after 16 frames */
1981 if (++buf_write[le->link] == RX_BUF_WRITE) {
1982 sky2_put_idx(hw, rxqaddr[le->link],
1983 sky2->rx_put);
1984 buf_write[le->link] = 0;
1985 }
1986
1987 /* Stop after net poll weight */
13210ce5
SH		 1988 if (++work_done >= to_do)
1989 goto exit_loop;
cd28ab6a
SH		 1990 break;
1991
d1f13708
SH		 1992#ifdef SKY2_VLAN_TAG_USED
1993 case OP_RXVLAN:
1994 sky2->rx_tag = length;
1995 break;
1996
1997 case OP_RXCHKSVLAN:
1998 sky2->rx_tag = length;
1999 /* fall through */
2000#endif
cd28ab6a 2001 case OP_RXCHKS:
d11c13e7
SH		 2002 skb = sky2->rx_ring[sky2->rx_next].skb;
2003 skb->ip_summed = CHECKSUM_HW;
2004 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 2005 break;
2006
2007 case OP_TXINDEXLE:
13b97b74 2008 /* TX index reports status for both ports */
f55925d7
SH		 2009 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2010 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2011 if (hw->dev[1])
2012 sky2_tx_done(hw->dev[1],
2013 ((status >> 24) & 0xff)
2014 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2015 break;
2016
cd28ab6a
SH		 2017 default:
2018 if (net_ratelimit())
793b883e 2019 printk(KERN_WARNING PFX
e71ebd73
SH		 2020 "unknown status opcode 0x%x\n", le->opcode);
2021 goto exit_loop;
cd28ab6a 2022 }
13210ce5 2023 }
cd28ab6a 2024
13210ce5 2025exit_loop:
22e11703
SH		 2026 if (buf_write[0]) {
2027 sky2 = netdev_priv(hw->dev[0]);
2028 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2029 }
2030
2031 if (buf_write[1]) {
2032 sky2 = netdev_priv(hw->dev[1]);
2033 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2034 }
2035
e07b1aa8 2036 return work_done;
cd28ab6a
SH		 2037}
2038
2039static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2040{
2041 struct net_device *dev = hw->dev[port];
2042
3be92a70
SH		 2043 if (net_ratelimit())
2044 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2045 dev->name, status);
cd28ab6a
SH		 2046
2047 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2048 if (net_ratelimit())
2049 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2050 dev->name);
cd28ab6a
SH		 2051 /* Clear IRQ */
2052 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2053 }
2054
2055 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2056 if (net_ratelimit())
2057 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2058 dev->name);
cd28ab6a
SH		 2059
2060 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2061 }
2062
2063 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2064 if (net_ratelimit())
2065 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2066 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2067 }
2068
2069 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2070 if (net_ratelimit())
2071 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2072 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2073 }
2074
2075 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2076 if (net_ratelimit())
2077 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2078 dev->name);
cd28ab6a
SH		 2079 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2080 }
2081}
2082
2083static void sky2_hw_intr(struct sky2_hw *hw)
2084{
2085 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2086
793b883e 2087 if (status & Y2_IS_TIST_OV)
cd28ab6a 2088 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2089
2090 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2091 u16 pci_err;
2092
56a645cc 2093 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2094 if (net_ratelimit())
2095 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2096 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2097
2098 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2099 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2100 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2101 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2102 }
2103
2104 if (status & Y2_IS_PCI_EXP) {
d571b694 2105 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2106 u32 pex_err;
2107
56a645cc 2108 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2109
3be92a70
SH		 2110 if (net_ratelimit())
2111 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2112 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2113
2114 /* clear the interrupt */
2115 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2116 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2117 0xffffffffUL);
cd28ab6a
SH		 2118 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2119
2120 if (pex_err & PEX_FATAL_ERRORS) {
2121 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2122 hwmsk &= ~Y2_IS_PCI_EXP;
2123 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2124 }
2125 }
2126
2127 if (status & Y2_HWE_L1_MASK)
2128 sky2_hw_error(hw, 0, status);
2129 status >>= 8;
2130 if (status & Y2_HWE_L1_MASK)
2131 sky2_hw_error(hw, 1, status);
2132}
2133
2134static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2135{
2136 struct net_device *dev = hw->dev[port];
2137 struct sky2_port *sky2 = netdev_priv(dev);
2138 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2139
2140 if (netif_msg_intr(sky2))
2141 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2142 dev->name, status);
2143
2144 if (status & GM_IS_RX_FF_OR) {
2145 ++sky2->net_stats.rx_fifo_errors;
2146 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2147 }
2148
2149 if (status & GM_IS_TX_FF_UR) {
2150 ++sky2->net_stats.tx_fifo_errors;
2151 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2152 }
cd28ab6a
SH		 2153}
2154
d257924e
SH		 2155/* This should never happen it is a fatal situation */
2156static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2157 const char *rxtx, u32 mask)
2158{
2159 struct net_device *dev = hw->dev[port];
2160 struct sky2_port *sky2 = netdev_priv(dev);
2161 u32 imask;
2162
2163 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2164 dev ? dev->name : "<not registered>", rxtx);
2165
2166 imask = sky2_read32(hw, B0_IMSK);
2167 imask &= ~mask;
2168 sky2_write32(hw, B0_IMSK, imask);
2169
2170 if (dev) {
2171 spin_lock(&sky2->phy_lock);
2172 sky2_link_down(sky2);
2173 spin_unlock(&sky2->phy_lock);
2174 }
2175}
cd28ab6a 2176
d27ed387
SH		 2177/* If idle then force a fake soft NAPI poll once a second
2178 * to work around cases where sharing an edge triggered interrupt.
2179 */
eb35cf60
SH		 2180static inline void sky2_idle_start(struct sky2_hw *hw)
2181{
2182 if (idle_timeout > 0)
2183 mod_timer(&hw->idle_timer,
2184 jiffies + msecs_to_jiffies(idle_timeout));
2185}
2186
d27ed387
SH		 2187static void sky2_idle(unsigned long arg)
2188{
01bd7564
SH		 2189 struct sky2_hw *hw = (struct sky2_hw *) arg;
2190 struct net_device *dev = hw->dev[0];
d27ed387 2191
d27ed387
SH		 2192 if (__netif_rx_schedule_prep(dev))
2193 __netif_rx_schedule(dev);
01bd7564
SH		 2194
2195 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2196}
2197
2198
e07b1aa8 2199static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2200{
e07b1aa8
SH		 2201 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2202 int work_limit = min(dev0->quota, *budget);
2203 int work_done = 0;
fb2690a9 2204 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2205
1e5f1283
SH		 2206 if (status & Y2_IS_HW_ERR)
2207 sky2_hw_intr(hw);
d257924e 2208
1e5f1283
SH		 2209 if (status & Y2_IS_IRQ_PHY1)
2210 sky2_phy_intr(hw, 0);
cd28ab6a 2211
1e5f1283
SH		 2212 if (status & Y2_IS_IRQ_PHY2)
2213 sky2_phy_intr(hw, 1);
cd28ab6a 2214
1e5f1283
SH		 2215 if (status & Y2_IS_IRQ_MAC1)
2216 sky2_mac_intr(hw, 0);
cd28ab6a 2217
1e5f1283
SH		 2218 if (status & Y2_IS_IRQ_MAC2)
2219 sky2_mac_intr(hw, 1);
cd28ab6a 2220
1e5f1283
SH		 2221 if (status & Y2_IS_CHK_RX1)
2222 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2223
1e5f1283
SH		 2224 if (status & Y2_IS_CHK_RX2)
2225 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2226
1e5f1283
SH		 2227 if (status & Y2_IS_CHK_TXA1)
2228 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2229
1e5f1283
SH		 2230 if (status & Y2_IS_CHK_TXA2)
2231 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2232
1e5f1283
SH		 2233 work_done = sky2_status_intr(hw, work_limit);
2234 *budget -= work_done;
2235 dev0->quota -= work_done;
e07b1aa8 2236
86fba634
SH		 2237 if (status & Y2_IS_STAT_BMU)
2238 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2239
2240 if (sky2_more_work(hw))
1e5f1283 2241 return 1;
caa0371e 2242
d3240312 2243 netif_rx_complete(dev0);
e07b1aa8 2244
86fba634 2245 sky2_read32(hw, B0_Y2_SP_LISR);
e07b1aa8
SH		 2246 return 0;
2247}
2248
2249static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2250{
2251 struct sky2_hw *hw = dev_id;
2252 struct net_device *dev0 = hw->dev[0];
2253 u32 status;
2254
2255 /* Reading this mask interrupts as side effect */
2256 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2257 if (status == 0 || status == ~0)
2258 return IRQ_NONE;
793b883e 2259
e07b1aa8
SH		 2260 prefetch(&hw->st_le[hw->st_idx]);
2261 if (likely(__netif_rx_schedule_prep(dev0)))
2262 __netif_rx_schedule(dev0);
793b883e 2263
cd28ab6a
SH		 2264 return IRQ_HANDLED;
2265}
2266
2267#ifdef CONFIG_NET_POLL_CONTROLLER
2268static void sky2_netpoll(struct net_device *dev)
2269{
2270 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2271 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2272
88d11360
SH		 2273 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2274 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2275}
2276#endif
2277
2278/* Chip internal frequency for clock calculations */
fb17358f 2279static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2280{
793b883e 2281 switch (hw->chip_id) {
cd28ab6a 2282 case CHIP_ID_YUKON_EC:
5a5b1ea0 2283 case CHIP_ID_YUKON_EC_U:
fb17358f 2284 return 125; /* 125 Mhz */
cd28ab6a 2285 case CHIP_ID_YUKON_FE:
fb17358f 2286 return 100; /* 100 Mhz */
793b883e 2287 default: /* YUKON_XL */
fb17358f 2288 return 156; /* 156 Mhz */
cd28ab6a
SH		 2289 }
2290}
2291
fb17358f 2292static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2293{
fb17358f 2294 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2295}
2296
fb17358f 2297static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2298{
fb17358f 2299 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2300}
2301
fb17358f 2302
59139528 2303static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2304{
cd28ab6a
SH		 2305 u16 status;
2306 u8 t8, pmd_type;
56a645cc 2307 int i;
cd28ab6a 2308
cd28ab6a 2309 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2310
cd28ab6a
SH		 2311 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2312 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2313 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2314 pci_name(hw->pdev), hw->chip_id);
2315 return -EOPNOTSUPP;
2316 }
2317
290d4de5
SH		 2318 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2319
2320 /* This rev is really old, and requires untested workarounds */
2321 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2322 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2323 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2324 hw->chip_id, hw->chip_rev);
2325 return -EOPNOTSUPP;
2326 }
2327
cd28ab6a
SH		 2328 /* disable ASF */
2329 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2330 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2331 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2332 }
2333
2334 /* do a SW reset */
2335 sky2_write8(hw, B0_CTST, CS_RST_SET);
2336 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2337
2338 /* clear PCI errors, if any */
56a645cc 2339 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2340
cd28ab6a 2341 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2342 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2343
cd28ab6a
SH		 2344
2345 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2346
2347 /* clear any PEX errors */
d89e1343 2348 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2349 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2350
cd28ab6a
SH		 2351
2352 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2353 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2354
2355 hw->ports = 1;
2356 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2357 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2358 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2359 ++hw->ports;
2360 }
cd28ab6a 2361
5afa0a9c 2362 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2363
2364 for (i = 0; i < hw->ports; i++) {
2365 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2366 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2367 }
2368
2369 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2370
793b883e
SH		 2371 /* Clear I2C IRQ noise */
2372 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2373
2374 /* turn off hardware timer (unused) */
2375 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2376 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2377
cd28ab6a
SH		 2378 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2379
69634ee7
SH		 2380 /* Turn off descriptor polling */
2381 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2382
2383 /* Turn off receive timestamp */
2384 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2385 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2386
2387 /* enable the Tx Arbiters */
2388 for (i = 0; i < hw->ports; i++)
2389 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2390
2391 /* Initialize ram interface */
2392 for (i = 0; i < hw->ports; i++) {
793b883e 2393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2394
2395 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2396 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2398 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2400 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2401 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2402 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2404 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2407 }
2408
cd28ab6a
SH		 2409 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2410
cd28ab6a
SH		 2411 for (i = 0; i < hw->ports; i++)
2412 sky2_phy_reset(hw, i);
cd28ab6a 2413
cd28ab6a
SH		 2414 memset(hw->st_le, 0, STATUS_LE_BYTES);
2415 hw->st_idx = 0;
2416
2417 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2418 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2419
2420 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2421 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2422
2423 /* Set the list last index */
793b883e 2424 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2425
290d4de5
SH		 2426 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2427 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2428
290d4de5
SH		 2429 /* set Status-FIFO ISR watermark */
2430 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2431 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2432 else
2433 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2434
290d4de5 2435 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2436 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2437 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2438
793b883e 2439 /* enable status unit */
cd28ab6a
SH		 2440 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2441
2442 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2443 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2444 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2445
2446 return 0;
2447}
2448
28bd181a 2449static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2450{
2451 u32 modes;
2452 if (hw->copper) {
793b883e
SH		 2453 modes = SUPPORTED_10baseT_Half
2454 | SUPPORTED_10baseT_Full
2455 | SUPPORTED_100baseT_Half
2456 | SUPPORTED_100baseT_Full
2457 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2458
2459 if (hw->chip_id != CHIP_ID_YUKON_FE)
2460 modes |= SUPPORTED_1000baseT_Half
793b883e 2461 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2462 } else
2463 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2464 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2465 return modes;
2466}
2467
793b883e 2468static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2469{
2470 struct sky2_port *sky2 = netdev_priv(dev);
2471 struct sky2_hw *hw = sky2->hw;
2472
2473 ecmd->transceiver = XCVR_INTERNAL;
2474 ecmd->supported = sky2_supported_modes(hw);
2475 ecmd->phy_address = PHY_ADDR_MARV;
2476 if (hw->copper) {
2477 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2478 | SUPPORTED_10baseT_Full
2479 | SUPPORTED_100baseT_Half
2480 | SUPPORTED_100baseT_Full
2481 | SUPPORTED_1000baseT_Half
2482 | SUPPORTED_1000baseT_Full
2483 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2484 ecmd->port = PORT_TP;
2485 } else
2486 ecmd->port = PORT_FIBRE;
2487
2488 ecmd->advertising = sky2->advertising;
2489 ecmd->autoneg = sky2->autoneg;
2490 ecmd->speed = sky2->speed;
2491 ecmd->duplex = sky2->duplex;
2492 return 0;
2493}
2494
2495static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2496{
2497 struct sky2_port *sky2 = netdev_priv(dev);
2498 const struct sky2_hw *hw = sky2->hw;
2499 u32 supported = sky2_supported_modes(hw);
2500
2501 if (ecmd->autoneg == AUTONEG_ENABLE) {
2502 ecmd->advertising = supported;
2503 sky2->duplex = -1;
2504 sky2->speed = -1;
2505 } else {
2506 u32 setting;
2507
793b883e 2508 switch (ecmd->speed) {
cd28ab6a
SH		 2509 case SPEED_1000:
2510 if (ecmd->duplex == DUPLEX_FULL)
2511 setting = SUPPORTED_1000baseT_Full;
2512 else if (ecmd->duplex == DUPLEX_HALF)
2513 setting = SUPPORTED_1000baseT_Half;
2514 else
2515 return -EINVAL;
2516 break;
2517 case SPEED_100:
2518 if (ecmd->duplex == DUPLEX_FULL)
2519 setting = SUPPORTED_100baseT_Full;
2520 else if (ecmd->duplex == DUPLEX_HALF)
2521 setting = SUPPORTED_100baseT_Half;
2522 else
2523 return -EINVAL;
2524 break;
2525
2526 case SPEED_10:
2527 if (ecmd->duplex == DUPLEX_FULL)
2528 setting = SUPPORTED_10baseT_Full;
2529 else if (ecmd->duplex == DUPLEX_HALF)
2530 setting = SUPPORTED_10baseT_Half;
2531 else
2532 return -EINVAL;
2533 break;
2534 default:
2535 return -EINVAL;
2536 }
2537
2538 if ((setting & supported) == 0)
2539 return -EINVAL;
2540
2541 sky2->speed = ecmd->speed;
2542 sky2->duplex = ecmd->duplex;
2543 }
2544
2545 sky2->autoneg = ecmd->autoneg;
2546 sky2->advertising = ecmd->advertising;
2547
1b537565
SH		 2548 if (netif_running(dev))
2549 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2550
2551 return 0;
2552}
2553
2554static void sky2_get_drvinfo(struct net_device *dev,
2555 struct ethtool_drvinfo *info)
2556{
2557 struct sky2_port *sky2 = netdev_priv(dev);
2558
2559 strcpy(info->driver, DRV_NAME);
2560 strcpy(info->version, DRV_VERSION);
2561 strcpy(info->fw_version, "N/A");
2562 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2563}
2564
2565static const struct sky2_stat {
793b883e
SH		 2566 char name[ETH_GSTRING_LEN];
2567 u16 offset;
cd28ab6a
SH		 2568} sky2_stats[] = {
2569 { "tx_bytes", GM_TXO_OK_HI },
2570 { "rx_bytes", GM_RXO_OK_HI },
2571 { "tx_broadcast", GM_TXF_BC_OK },
2572 { "rx_broadcast", GM_RXF_BC_OK },
2573 { "tx_multicast", GM_TXF_MC_OK },
2574 { "rx_multicast", GM_RXF_MC_OK },
2575 { "tx_unicast", GM_TXF_UC_OK },
2576 { "rx_unicast", GM_RXF_UC_OK },
2577 { "tx_mac_pause", GM_TXF_MPAUSE },
2578 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2579 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2580 { "late_collision",GM_TXF_LAT_COL },
2581 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2582 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2583 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2584
d2604540 2585 { "rx_short", GM_RXF_SHT },
cd28ab6a 2586 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2587 { "rx_64_byte_packets", GM_RXF_64B },
2588 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2589 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2590 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2591 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2592 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2593 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2594 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2595 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2596 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2597 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2598
2599 { "tx_64_byte_packets", GM_TXF_64B },
2600 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2601 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2602 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2603 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2604 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2605 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2606 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2607};
2608
cd28ab6a
SH		 2609static u32 sky2_get_rx_csum(struct net_device *dev)
2610{
2611 struct sky2_port *sky2 = netdev_priv(dev);
2612
2613 return sky2->rx_csum;
2614}
2615
2616static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2617{
2618 struct sky2_port *sky2 = netdev_priv(dev);
2619
2620 sky2->rx_csum = data;
793b883e 2621
cd28ab6a
SH		 2622 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2623 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2624
2625 return 0;
2626}
2627
2628static u32 sky2_get_msglevel(struct net_device *netdev)
2629{
2630 struct sky2_port *sky2 = netdev_priv(netdev);
2631 return sky2->msg_enable;
2632}
2633
9a7ae0a9
SH		 2634static int sky2_nway_reset(struct net_device *dev)
2635{
2636 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2637
2638 if (sky2->autoneg != AUTONEG_ENABLE)
2639 return -EINVAL;
2640
1b537565 2641 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2642
2643 return 0;
2644}
2645
793b883e 2646static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2647{
2648 struct sky2_hw *hw = sky2->hw;
2649 unsigned port = sky2->port;
2650 int i;
2651
2652 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2653 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2654 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2655 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2656
793b883e 2657 for (i = 2; i < count; i++)
cd28ab6a
SH		 2658 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2659}
2660
cd28ab6a
SH		 2661static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2662{
2663 struct sky2_port *sky2 = netdev_priv(netdev);
2664 sky2->msg_enable = value;
2665}
2666
2667static int sky2_get_stats_count(struct net_device *dev)
2668{
2669 return ARRAY_SIZE(sky2_stats);
2670}
2671
2672static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2673 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2674{
2675 struct sky2_port *sky2 = netdev_priv(dev);
2676
793b883e 2677 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2678}
2679
793b883e 2680static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2681{
2682 int i;
2683
2684 switch (stringset) {
2685 case ETH_SS_STATS:
2686 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2687 memcpy(data + i * ETH_GSTRING_LEN,
2688 sky2_stats[i].name, ETH_GSTRING_LEN);
2689 break;
2690 }
2691}
2692
2693/* Use hardware MIB variables for critical path statistics and
2694 * transmit feedback not reported at interrupt.
2695 * Other errors are accounted for in interrupt handler.
2696 */
2697static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2698{
2699 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2700 u64 data[13];
cd28ab6a 2701
793b883e 2702 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2703
2704 sky2->net_stats.tx_bytes = data[0];
2705 sky2->net_stats.rx_bytes = data[1];
2706 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2707 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2708 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2709 sky2->net_stats.collisions = data[10];
2710 sky2->net_stats.tx_aborted_errors = data[12];
2711
2712 return &sky2->net_stats;
2713}
2714
2715static int sky2_set_mac_address(struct net_device *dev, void *p)
2716{
2717 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2718 struct sky2_hw *hw = sky2->hw;
2719 unsigned port = sky2->port;
2720 const struct sockaddr *addr = p;
cd28ab6a
SH		 2721
2722 if (!is_valid_ether_addr(addr->sa_data))
2723 return -EADDRNOTAVAIL;
2724
cd28ab6a 2725 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2726 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2727 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2728 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2729 dev->dev_addr, ETH_ALEN);
1b537565 2730
a8ab1ec0
SH		 2731 /* virtual address for data */
2732 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2733
2734 /* physical address: used for pause frames */
2735 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2736
2737 return 0;
cd28ab6a
SH		 2738}
2739
2740static void sky2_set_multicast(struct net_device *dev)
2741{
2742 struct sky2_port *sky2 = netdev_priv(dev);
2743 struct sky2_hw *hw = sky2->hw;
2744 unsigned port = sky2->port;
2745 struct dev_mc_list *list = dev->mc_list;
2746 u16 reg;
2747 u8 filter[8];
2748
2749 memset(filter, 0, sizeof(filter));
2750
2751 reg = gma_read16(hw, port, GM_RX_CTRL);
2752 reg |= GM_RXCR_UCF_ENA;
2753
d571b694 2754 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2755 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2756 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2757 memset(filter, 0xff, sizeof(filter));
793b883e 2758 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2759 reg &= ~GM_RXCR_MCF_ENA;
2760 else {
2761 int i;
2762 reg |= GM_RXCR_MCF_ENA;
2763
2764 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2765 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2766 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2767 }
2768 }
2769
cd28ab6a 2770 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2771 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2772 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2773 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2774 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2775 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2776 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2777 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2778
2779 gma_write16(hw, port, GM_RX_CTRL, reg);
2780}
2781
2782/* Can have one global because blinking is controlled by
2783 * ethtool and that is always under RTNL mutex
2784 */
91c86df5 2785static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2786{
793b883e
SH		 2787 u16 pg;
2788
793b883e
SH		 2789 switch (hw->chip_id) {
2790 case CHIP_ID_YUKON_XL:
2791 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2792 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2793 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2794 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2795 PHY_M_LEDC_INIT_CTRL(7) |
2796 PHY_M_LEDC_STA1_CTRL(7) |
2797 PHY_M_LEDC_STA0_CTRL(7))
2798 : 0);
2799
2800 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2801 break;
2802
2803 default:
2804 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2805 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2806 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2807 PHY_M_LED_MO_10(MO_LED_ON) |
2808 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2809 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2810 PHY_M_LED_MO_RX(MO_LED_ON)
2811 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2812 PHY_M_LED_MO_10(MO_LED_OFF) |
2813 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2814 PHY_M_LED_MO_1000(MO_LED_OFF) |
2815 PHY_M_LED_MO_RX(MO_LED_OFF));
2816
793b883e 2817 }
cd28ab6a
SH		 2818}
2819
2820/* blink LED's for finding board */
2821static int sky2_phys_id(struct net_device *dev, u32 data)
2822{
2823 struct sky2_port *sky2 = netdev_priv(dev);
2824 struct sky2_hw *hw = sky2->hw;
2825 unsigned port = sky2->port;
793b883e 2826 u16 ledctrl, ledover = 0;
cd28ab6a 2827 long ms;
91c86df5 2828 int interrupted;
cd28ab6a
SH		 2829 int onoff = 1;
2830
793b883e 2831 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2832 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2833 else
2834 ms = data * 1000;
2835
2836 /* save initial values */
e07b1aa8 2837 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2838 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2839 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2840 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2841 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2842 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2843 } else {
2844 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2845 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2846 }
cd28ab6a 2847
91c86df5
SH		 2848 interrupted = 0;
2849 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2850 sky2_led(hw, port, onoff);
2851 onoff = !onoff;
2852
e07b1aa8 2853 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2854 interrupted = msleep_interruptible(250);
e07b1aa8 2855 spin_lock_bh(&sky2->phy_lock);
91c86df5 2856
cd28ab6a
SH		 2857 ms -= 250;
2858 }
2859
2860 /* resume regularly scheduled programming */
793b883e
SH		 2861 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2862 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2863 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2864 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2865 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2866 } else {
2867 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2868 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2869 }
e07b1aa8 2870 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2871
2872 return 0;
2873}
2874
2875static void sky2_get_pauseparam(struct net_device *dev,
2876 struct ethtool_pauseparam *ecmd)
2877{
2878 struct sky2_port *sky2 = netdev_priv(dev);
2879
2880 ecmd->tx_pause = sky2->tx_pause;
2881 ecmd->rx_pause = sky2->rx_pause;
2882 ecmd->autoneg = sky2->autoneg;
2883}
2884
2885static int sky2_set_pauseparam(struct net_device *dev,
2886 struct ethtool_pauseparam *ecmd)
2887{
2888 struct sky2_port *sky2 = netdev_priv(dev);
2889 int err = 0;
2890
2891 sky2->autoneg = ecmd->autoneg;
2892 sky2->tx_pause = ecmd->tx_pause != 0;
2893 sky2->rx_pause = ecmd->rx_pause != 0;
2894
1b537565 2895 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2896
2897 return err;
2898}
2899
fb17358f
SH		 2900static int sky2_get_coalesce(struct net_device *dev,
2901 struct ethtool_coalesce *ecmd)
2902{
2903 struct sky2_port *sky2 = netdev_priv(dev);
2904 struct sky2_hw *hw = sky2->hw;
2905
2906 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2907 ecmd->tx_coalesce_usecs = 0;
2908 else {
2909 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2910 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2911 }
2912 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2913
2914 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2915 ecmd->rx_coalesce_usecs = 0;
2916 else {
2917 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2918 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2919 }
2920 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2921
2922 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2923 ecmd->rx_coalesce_usecs_irq = 0;
2924 else {
2925 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2926 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2927 }
2928
2929 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2930
2931 return 0;
2932}
2933
2934/* Note: this affect both ports */
2935static int sky2_set_coalesce(struct net_device *dev,
2936 struct ethtool_coalesce *ecmd)
2937{
2938 struct sky2_port *sky2 = netdev_priv(dev);
2939 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2940 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2941
77b3d6a2
SH		 2942 if (ecmd->tx_coalesce_usecs > tmax ||
2943 ecmd->rx_coalesce_usecs > tmax ||
2944 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2945 return -EINVAL;
2946
ff81fbbe 2947 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2948 return -EINVAL;
ff81fbbe 2949 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2950 return -EINVAL;
ff81fbbe 2951 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2952 return -EINVAL;
2953
2954 if (ecmd->tx_coalesce_usecs == 0)
2955 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2956 else {
2957 sky2_write32(hw, STAT_TX_TIMER_INI,
2958 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2959 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2960 }
2961 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2962
2963 if (ecmd->rx_coalesce_usecs == 0)
2964 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2965 else {
2966 sky2_write32(hw, STAT_LEV_TIMER_INI,
2967 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2968 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2969 }
2970 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2971
2972 if (ecmd->rx_coalesce_usecs_irq == 0)
2973 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2974 else {
d28d4870 2975 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2976 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2977 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2978 }
2979 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2980 return 0;
2981}
2982
793b883e
SH		 2983static void sky2_get_ringparam(struct net_device *dev,
2984 struct ethtool_ringparam *ering)
2985{
2986 struct sky2_port *sky2 = netdev_priv(dev);
2987
2988 ering->rx_max_pending = RX_MAX_PENDING;
2989 ering->rx_mini_max_pending = 0;
2990 ering->rx_jumbo_max_pending = 0;
2991 ering->tx_max_pending = TX_RING_SIZE - 1;
2992
2993 ering->rx_pending = sky2->rx_pending;
2994 ering->rx_mini_pending = 0;
2995 ering->rx_jumbo_pending = 0;
2996 ering->tx_pending = sky2->tx_pending;
2997}
2998
2999static int sky2_set_ringparam(struct net_device *dev,
3000 struct ethtool_ringparam *ering)
3001{
3002 struct sky2_port *sky2 = netdev_priv(dev);
3003 int err = 0;
3004
3005 if (ering->rx_pending > RX_MAX_PENDING ||
3006 ering->rx_pending < 8 ||
3007 ering->tx_pending < MAX_SKB_TX_LE ||
3008 ering->tx_pending > TX_RING_SIZE - 1)
3009 return -EINVAL;
3010
3011 if (netif_running(dev))
3012 sky2_down(dev);
3013
3014 sky2->rx_pending = ering->rx_pending;
3015 sky2->tx_pending = ering->tx_pending;
3016
1b537565 3017 if (netif_running(dev)) {
793b883e 3018 err = sky2_up(dev);
1b537565
SH		 3019 if (err)
3020 dev_close(dev);
6ed995bb
SH		 3021 else
3022 sky2_set_multicast(dev);
1b537565 3023 }
793b883e
SH		 3024
3025 return err;
3026}
3027
793b883e
SH		 3028static int sky2_get_regs_len(struct net_device *dev)
3029{
6e4cbb34 3030 return 0x4000;
793b883e
SH		 3031}
3032
3033/*
3034 * Returns copy of control register region
6e4cbb34 3035 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3036 */
3037static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3038 void *p)
3039{
3040 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3041 const void __iomem *io = sky2->hw->regs;
793b883e 3042
6e4cbb34 3043 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3044 regs->version = 1;
6e4cbb34 3045 memset(p, 0, regs->len);
793b883e 3046
6e4cbb34
SH		 3047 memcpy_fromio(p, io, B3_RAM_ADDR);
3048
3049 memcpy_fromio(p + B3_RI_WTO_R1,
3050 io + B3_RI_WTO_R1,
3051 regs->len - B3_RI_WTO_R1);
793b883e 3052}
cd28ab6a
SH		 3053
3054static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3055 .get_settings = sky2_get_settings,
3056 .set_settings = sky2_set_settings,
3057 .get_drvinfo = sky2_get_drvinfo,
3058 .get_msglevel = sky2_get_msglevel,
3059 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3060 .nway_reset = sky2_nway_reset,
793b883e
SH		 3061 .get_regs_len = sky2_get_regs_len,
3062 .get_regs = sky2_get_regs,
3063 .get_link = ethtool_op_get_link,
3064 .get_sg = ethtool_op_get_sg,
3065 .set_sg = ethtool_op_set_sg,
3066 .get_tx_csum = ethtool_op_get_tx_csum,
3067 .set_tx_csum = ethtool_op_set_tx_csum,
3068 .get_tso = ethtool_op_get_tso,
3069 .set_tso = ethtool_op_set_tso,
3070 .get_rx_csum = sky2_get_rx_csum,
3071 .set_rx_csum = sky2_set_rx_csum,
3072 .get_strings = sky2_get_strings,
fb17358f
SH		 3073 .get_coalesce = sky2_get_coalesce,
3074 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3075 .get_ringparam = sky2_get_ringparam,
3076 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3077 .get_pauseparam = sky2_get_pauseparam,
3078 .set_pauseparam = sky2_set_pauseparam,
793b883e 3079 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3080 .get_stats_count = sky2_get_stats_count,
3081 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3082 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3083};
3084
3085/* Initialize network device */
3086static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3087 unsigned port, int highmem)
3088{
3089 struct sky2_port *sky2;
3090 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3091
3092 if (!dev) {
3093 printk(KERN_ERR "sky2 etherdev alloc failed");
3094 return NULL;
3095 }
3096
3097 SET_MODULE_OWNER(dev);
3098 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3099 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3100 dev->open = sky2_up;
3101 dev->stop = sky2_down;
ef743d33 3102 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3103 dev->hard_start_xmit = sky2_xmit_frame;
3104 dev->get_stats = sky2_get_stats;
3105 dev->set_multicast_list = sky2_set_multicast;
3106 dev->set_mac_address = sky2_set_mac_address;
3107 dev->change_mtu = sky2_change_mtu;
3108 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3109 dev->tx_timeout = sky2_tx_timeout;
3110 dev->watchdog_timeo = TX_WATCHDOG;
3111 if (port == 0)
3112 dev->poll = sky2_poll;
3113 dev->weight = NAPI_WEIGHT;
3114#ifdef CONFIG_NET_POLL_CONTROLLER
3115 dev->poll_controller = sky2_netpoll;
3116#endif
cd28ab6a
SH		 3117
3118 sky2 = netdev_priv(dev);
3119 sky2->netdev = dev;
3120 sky2->hw = hw;
3121 sky2->msg_enable = netif_msg_init(debug, default_msg);
3122
3123 spin_lock_init(&sky2->tx_lock);
3124 /* Auto speed and flow control */
3125 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3126 sky2->tx_pause = 1;
cd28ab6a
SH		 3127 sky2->rx_pause = 1;
3128 sky2->duplex = -1;
3129 sky2->speed = -1;
3130 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3131 sky2->rx_csum = 1;
75d070c5 3132
e07b1aa8 3133 spin_lock_init(&sky2->phy_lock);
793b883e 3134 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3135 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3136 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3137
3138 hw->dev[port] = dev;
3139
3140 sky2->port = port;
3141
5a5b1ea0
SH		 3142 dev->features |= NETIF_F_LLTX;
3143 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3144 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3145 if (highmem)
3146 dev->features |= NETIF_F_HIGHDMA;
793b883e 3147 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3148
d1f13708
SH		 3149#ifdef SKY2_VLAN_TAG_USED
3150 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3151 dev->vlan_rx_register = sky2_vlan_rx_register;
3152 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3153#endif
3154
cd28ab6a 3155 /* read the mac address */
793b883e 3156 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3157 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3158
3159 /* device is off until link detection */
3160 netif_carrier_off(dev);
3161 netif_stop_queue(dev);
3162
3163 return dev;
3164}
3165
28bd181a 3166static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3167{
3168 const struct sky2_port *sky2 = netdev_priv(dev);
3169
3170 if (netif_msg_probe(sky2))
3171 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3172 dev->name,
3173 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3174 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3175}
3176
fb2690a9
SH		 3177/* Handle software interrupt used during MSI test */
3178static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3179 struct pt_regs *regs)
3180{
3181 struct sky2_hw *hw = dev_id;
3182 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3183
3184 if (status == 0)
3185 return IRQ_NONE;
3186
3187 if (status & Y2_IS_IRQ_SW) {
3188 hw->msi_detected = 1;
3189 wake_up(&hw->msi_wait);
3190 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3191 }
3192 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3193
3194 return IRQ_HANDLED;
3195}
3196
3197/* Test interrupt path by forcing a a software IRQ */
3198static int __devinit sky2_test_msi(struct sky2_hw *hw)
3199{
3200 struct pci_dev *pdev = hw->pdev;
3201 int err;
3202
3203 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3204
1fb9df5d 3205 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3206 if (err) {
3207 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3208 pci_name(pdev), pdev->irq);
3209 return err;
3210 }
3211
3212 init_waitqueue_head (&hw->msi_wait);
3213
3214 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3215 wmb();
3216
3217 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3218
3219 if (!hw->msi_detected) {
3220 /* MSI test failed, go back to INTx mode */
3221 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3222 "switching to INTx mode. Please report this failure to "
3223 "the PCI maintainer and include system chipset information.\n",
3224 pci_name(pdev));
3225
3226 err = -EOPNOTSUPP;
3227 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3228 }
3229
3230 sky2_write32(hw, B0_IMSK, 0);
3231
3232 free_irq(pdev->irq, hw);
3233
3234 return err;
3235}
3236
cd28ab6a
SH		 3237static int __devinit sky2_probe(struct pci_dev *pdev,
3238 const struct pci_device_id *ent)
3239{
793b883e 3240 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3241 struct sky2_hw *hw;
5afa0a9c 3242 int err, pm_cap, using_dac = 0;
cd28ab6a 3243
793b883e
SH		 3244 err = pci_enable_device(pdev);
3245 if (err) {
cd28ab6a
SH		 3246 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3247 pci_name(pdev));
3248 goto err_out;
3249 }
3250
793b883e
SH		 3251 err = pci_request_regions(pdev, DRV_NAME);
3252 if (err) {
cd28ab6a
SH		 3253 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3254 pci_name(pdev));
793b883e 3255 goto err_out;
cd28ab6a
SH		 3256 }
3257
3258 pci_set_master(pdev);
3259
5afa0a9c
SH		 3260 /* Find power-management capability. */
3261 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3262 if (pm_cap == 0) {
3263 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3264 "aborting.\n");
3265 err = -EIO;
3266 goto err_out_free_regions;
3267 }
3268
d1f3d4dd
SH		 3269 if (sizeof(dma_addr_t) > sizeof(u32) &&
3270 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3271 using_dac = 1;
3272 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3273 if (err < 0) {
3274 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3275 "for consistent allocations\n", pci_name(pdev));
3276 goto err_out_free_regions;
3277 }
cd28ab6a 3278
d1f3d4dd 3279 } else {
cd28ab6a
SH		 3280 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3281 if (err) {
3282 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3283 pci_name(pdev));
3284 goto err_out_free_regions;
3285 }
3286 }
d1f3d4dd 3287
cd28ab6a 3288 err = -ENOMEM;
6aad85d6 3289 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3290 if (!hw) {
3291 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3292 pci_name(pdev));
3293 goto err_out_free_regions;
3294 }
3295
cd28ab6a 3296 hw->pdev = pdev;
cd28ab6a
SH		 3297
3298 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3299 if (!hw->regs) {
3300 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3301 pci_name(pdev));
3302 goto err_out_free_hw;
3303 }
5afa0a9c 3304 hw->pm_cap = pm_cap;
cd28ab6a 3305
56a645cc
SH		 3306#ifdef __BIG_ENDIAN
3307 /* byte swap descriptors in hardware */
3308 {
3309 u32 reg;
3310
3311 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3312 reg |= PCI_REV_DESC;
3313 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3314 }
3315#endif
3316
08c06d8a
SH		 3317 /* ring for status responses */
3318 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3319 &hw->st_dma);
3320 if (!hw->st_le)
3321 goto err_out_iounmap;
3322
cd28ab6a
SH		 3323 err = sky2_reset(hw);
3324 if (err)
793b883e 3325 goto err_out_iounmap;
cd28ab6a 3326
7c7459d1
GKH		 3327 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3328 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3329 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3330 hw->chip_id, hw->chip_rev);
cd28ab6a 3331
793b883e
SH		 3332 dev = sky2_init_netdev(hw, 0, using_dac);
3333 if (!dev)
cd28ab6a
SH		 3334 goto err_out_free_pci;
3335
793b883e
SH		 3336 err = register_netdev(dev);
3337 if (err) {
cd28ab6a
SH		 3338 printk(KERN_ERR PFX "%s: cannot register net device\n",
3339 pci_name(pdev));
3340 goto err_out_free_netdev;
3341 }
3342
3343 sky2_show_addr(dev);
3344
3345 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3346 if (register_netdev(dev1) == 0)
3347 sky2_show_addr(dev1);
3348 else {
3349 /* Failure to register second port need not be fatal */
793b883e
SH		 3350 printk(KERN_WARNING PFX
3351 "register of second port failed\n");
cd28ab6a
SH		 3352 hw->dev[1] = NULL;
3353 free_netdev(dev1);
3354 }
3355 }
3356
fb2690a9
SH		 3357 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3358 err = sky2_test_msi(hw);
3359 if (err == -EOPNOTSUPP)
3360 pci_disable_msi(pdev);
3361 else if (err)
3362 goto err_out_unregister;
3363 }
3364
1fb9df5d 3365 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
793b883e
SH		 3366 if (err) {
3367 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3368 pci_name(pdev), pdev->irq);
3369 goto err_out_unregister;
3370 }
3371
e07b1aa8 3372 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3373
01bd7564 3374 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3375 sky2_idle_start(hw);
d27ed387 3376
793b883e
SH		 3377 pci_set_drvdata(pdev, hw);
3378
cd28ab6a
SH		 3379 return 0;
3380
793b883e 3381err_out_unregister:
fb2690a9 3382 pci_disable_msi(pdev);
793b883e
SH		 3383 if (dev1) {
3384 unregister_netdev(dev1);
3385 free_netdev(dev1);
3386 }
3387 unregister_netdev(dev);
cd28ab6a
SH		 3388err_out_free_netdev:
3389 free_netdev(dev);
cd28ab6a 3390err_out_free_pci:
793b883e 3391 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3392 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3393err_out_iounmap:
3394 iounmap(hw->regs);
3395err_out_free_hw:
3396 kfree(hw);
3397err_out_free_regions:
3398 pci_release_regions(pdev);
cd28ab6a 3399 pci_disable_device(pdev);
cd28ab6a
SH		 3400err_out:
3401 return err;
3402}
3403
3404static void __devexit sky2_remove(struct pci_dev *pdev)
3405{
793b883e 3406 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3407 struct net_device *dev0, *dev1;
3408
793b883e 3409 if (!hw)
cd28ab6a
SH		 3410 return;
3411
d27ed387
SH		 3412 del_timer_sync(&hw->idle_timer);
3413
3414 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3415 synchronize_irq(hw->pdev->irq);
3416
cd28ab6a 3417 dev0 = hw->dev[0];
793b883e
SH		 3418 dev1 = hw->dev[1];
3419 if (dev1)
3420 unregister_netdev(dev1);
cd28ab6a
SH		 3421 unregister_netdev(dev0);
3422
5afa0a9c 3423 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3424 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3425 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3426 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3427
3428 free_irq(pdev->irq, hw);
fb2690a9 3429 pci_disable_msi(pdev);
793b883e 3430 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3431 pci_release_regions(pdev);
3432 pci_disable_device(pdev);
793b883e 3433
cd28ab6a
SH		 3434 if (dev1)
3435 free_netdev(dev1);
3436 free_netdev(dev0);
3437 iounmap(hw->regs);
3438 kfree(hw);
5afa0a9c 3439
cd28ab6a
SH		 3440 pci_set_drvdata(pdev, NULL);
3441}
3442
3443#ifdef CONFIG_PM
3444static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3445{
793b883e 3446 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3447 int i;
2ccc99b7
SH		 3448 pci_power_t pstate = pci_choose_state(pdev, state);
3449
3450 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3451 return -EINVAL;
cd28ab6a 3452
eb35cf60 3453 del_timer_sync(&hw->idle_timer);
6a5706b9 3454 netif_poll_disable(hw->dev[0]);
eb35cf60 3455
f05267e7 3456 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3457 struct net_device *dev = hw->dev[i];
3458
6a5706b9 3459 if (netif_running(dev)) {
5afa0a9c 3460 sky2_down(dev);
cd28ab6a 3461 netif_device_detach(dev);
cd28ab6a
SH		 3462 }
3463 }
3464
8ab8fca2 3465 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3466 pci_save_state(pdev);
2ccc99b7
SH		 3467 sky2_set_power_state(hw, pstate);
3468 return 0;
cd28ab6a
SH		 3469}
3470
3471static int sky2_resume(struct pci_dev *pdev)
3472{
793b883e 3473 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3474 int i, err;
cd28ab6a 3475
cd28ab6a
SH		 3476 pci_restore_state(pdev);
3477 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3478 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3479
08c06d8a
SH		 3480 err = sky2_reset(hw);
3481 if (err)
3482 goto out;
cd28ab6a 3483
8ab8fca2
SH		 3484 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3485
f05267e7 3486 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3487 struct net_device *dev = hw->dev[i];
6a5706b9 3488 if (netif_running(dev)) {
08c06d8a 3489 netif_device_attach(dev);
88d11360 3490
08c06d8a
SH		 3491 err = sky2_up(dev);
3492 if (err) {
3493 printk(KERN_ERR PFX "%s: could not up: %d\n",
3494 dev->name, err);
3495 dev_close(dev);
eb35cf60 3496 goto out;
5afa0a9c 3497 }
cd28ab6a
SH		 3498 }
3499 }
eb35cf60 3500
6a5706b9 3501 netif_poll_enable(hw->dev[0]);
eb35cf60 3502 sky2_idle_start(hw);
08c06d8a
SH		 3503out:
3504 return err;
cd28ab6a
SH		 3505}
3506#endif
3507
3508static struct pci_driver sky2_driver = {
793b883e
SH		 3509 .name = DRV_NAME,
3510 .id_table = sky2_id_table,
3511 .probe = sky2_probe,
3512 .remove = __devexit_p(sky2_remove),
cd28ab6a 3513#ifdef CONFIG_PM
793b883e
SH		 3514 .suspend = sky2_suspend,
3515 .resume = sky2_resume,
cd28ab6a
SH		 3516#endif
3517};
3518
3519static int __init sky2_init_module(void)
3520{
50241c4c 3521 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3522}
3523
3524static void __exit sky2_cleanup_module(void)
3525{
3526 pci_unregister_driver(&sky2_driver);
3527}
3528
3529module_init(sky2_init_module);
3530module_exit(sky2_cleanup_module);
3531
3532MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3533MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3534MODULE_LICENSE("GPL");
5f4f9dc1 3535MODULE_VERSION(DRV_VERSION);
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