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Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | /* | |
27 | * TODO | |
28 | * - coalescing setting? | |
cd28ab6a SH |
29 | * |
30 | * TOTEST | |
31 | * - speed setting | |
724bca3c | 32 | * - suspend/resume |
cd28ab6a SH |
33 | */ |
34 | ||
35 | #include <linux/config.h> | |
793b883e | 36 | #include <linux/crc32.h> |
cd28ab6a SH |
37 | #include <linux/kernel.h> |
38 | #include <linux/version.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/netdevice.h> | |
d0bbccfa | 41 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
42 | #include <linux/etherdevice.h> |
43 | #include <linux/ethtool.h> | |
44 | #include <linux/pci.h> | |
45 | #include <linux/ip.h> | |
46 | #include <linux/tcp.h> | |
47 | #include <linux/in.h> | |
48 | #include <linux/delay.h> | |
d1f13708 | 49 | #include <linux/if_vlan.h> |
ef743d33 | 50 | #include <linux/mii.h> |
cd28ab6a SH |
51 | |
52 | #include <asm/irq.h> | |
53 | ||
d1f13708 SH |
54 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
55 | #define SKY2_VLAN_TAG_USED 1 | |
56 | #endif | |
57 | ||
cd28ab6a SH |
58 | #include "sky2.h" |
59 | ||
60 | #define DRV_NAME "sky2" | |
f1e691a2 | 61 | #define DRV_VERSION "0.7" |
cd28ab6a SH |
62 | #define PFX DRV_NAME " " |
63 | ||
64 | /* | |
65 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
66 | * that are organized into three (receive, transmit, status) different rings | |
67 | * similar to Tigon3. A transmit can require several elements; | |
68 | * a receive requires one (or two if using 64 bit dma). | |
69 | */ | |
70 | ||
cd28ab6a | 71 | #define is_ec_a1(hw) \ |
21437643 SH |
72 | unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \ |
73 | (hw)->chip_rev == CHIP_REV_YU_EC_A1) | |
cd28ab6a | 74 | |
13210ce5 | 75 | #define RX_LE_SIZE 512 |
cd28ab6a | 76 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
bea86103 | 77 | #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) |
13210ce5 | 78 | #define RX_DEF_PENDING RX_MAX_PENDING |
79e57d32 | 79 | #define RX_COPY_THRESHOLD 256 |
793b883e SH |
80 | |
81 | #define TX_RING_SIZE 512 | |
82 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
83 | #define TX_MIN_PENDING 64 | |
84 | #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS) | |
cd28ab6a | 85 | |
793b883e | 86 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a SH |
87 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
88 | #define ETH_JUMBO_MTU 9000 | |
89 | #define TX_WATCHDOG (5 * HZ) | |
90 | #define NAPI_WEIGHT 64 | |
91 | #define PHY_RETRIES 1000 | |
92 | ||
93 | static const u32 default_msg = | |
793b883e SH |
94 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
95 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
96 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR; | |
cd28ab6a | 97 | |
793b883e | 98 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
99 | module_param(debug, int, 0); |
100 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
101 | ||
102 | static const struct pci_device_id sky2_id_table[] = { | |
793b883e | 103 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
cd28ab6a SH |
104 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
105 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, | |
106 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, | |
107 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, | |
108 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | |
5a5b1ea0 | 117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, |
cd28ab6a SH |
118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | |
120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | |
5a5b1ea0 | 121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, |
cd28ab6a SH |
122 | { 0 } |
123 | }; | |
793b883e | 124 | |
cd28ab6a SH |
125 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
126 | ||
127 | /* Avoid conditionals by using array */ | |
128 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
129 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
130 | ||
793b883e SH |
131 | static const char *yukon_name[] = { |
132 | [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */ | |
133 | [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */ | |
134 | [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */ | |
5a5b1ea0 | 135 | [CHIP_ID_YUKON_EC_U - CHIP_ID_YUKON] = "EC Ultra", /* 0xb4 */ |
cd28ab6a | 136 | |
793b883e SH |
137 | [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */ |
138 | [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */ | |
139 | }; | |
140 | ||
141 | ||
142 | /* Access to external PHY */ | |
ef743d33 | 143 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
144 | { |
145 | int i; | |
146 | ||
147 | gma_write16(hw, port, GM_SMI_DATA, val); | |
148 | gma_write16(hw, port, GM_SMI_CTRL, | |
149 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
150 | ||
151 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 152 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
ef743d33 | 153 | return 0; |
793b883e | 154 | udelay(1); |
cd28ab6a | 155 | } |
ef743d33 | 156 | |
793b883e | 157 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 158 | return -ETIMEDOUT; |
cd28ab6a SH |
159 | } |
160 | ||
ef743d33 | 161 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
162 | { |
163 | int i; | |
164 | ||
793b883e | 165 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
166 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
167 | ||
168 | for (i = 0; i < PHY_RETRIES; i++) { | |
ef743d33 SH |
169 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { |
170 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
171 | return 0; | |
172 | } | |
173 | ||
793b883e | 174 | udelay(1); |
cd28ab6a SH |
175 | } |
176 | ||
ef743d33 SH |
177 | return -ETIMEDOUT; |
178 | } | |
179 | ||
180 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
181 | { | |
182 | u16 v; | |
183 | ||
184 | if (__gm_phy_read(hw, port, reg, &v) != 0) | |
185 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); | |
186 | return v; | |
cd28ab6a SH |
187 | } |
188 | ||
5afa0a9c SH |
189 | static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) |
190 | { | |
191 | u16 power_control; | |
192 | u32 reg1; | |
193 | int vaux; | |
194 | int ret = 0; | |
195 | ||
196 | pr_debug("sky2_set_power_state %d\n", state); | |
197 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
198 | ||
199 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control); | |
200 | vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) && | |
201 | (power_control & PCI_PM_CAP_PME_D3cold); | |
202 | ||
203 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control); | |
204 | ||
205 | power_control |= PCI_PM_CTRL_PME_STATUS; | |
206 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); | |
207 | ||
208 | switch (state) { | |
209 | case PCI_D0: | |
210 | /* switch power to VCC (WA for VAUX problem) */ | |
211 | sky2_write8(hw, B0_POWER_CTRL, | |
212 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
213 | ||
214 | /* disable Core Clock Division, */ | |
215 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
216 | ||
217 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
218 | /* enable bits are inverted */ | |
219 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
220 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
221 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
222 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
223 | else | |
224 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
225 | ||
226 | /* Turn off phy power saving */ | |
227 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
228 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
229 | ||
d571b694 | 230 | /* looks like this XL is back asswards .. */ |
5afa0a9c SH |
231 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { |
232 | reg1 |= PCI_Y2_PHY1_COMA; | |
233 | if (hw->ports > 1) | |
234 | reg1 |= PCI_Y2_PHY2_COMA; | |
235 | } | |
236 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | |
237 | break; | |
238 | ||
239 | case PCI_D3hot: | |
240 | case PCI_D3cold: | |
241 | /* Turn on phy power saving */ | |
242 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
243 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
244 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
245 | else | |
246 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
247 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | |
248 | ||
249 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
250 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
251 | else | |
252 | /* enable bits are inverted */ | |
253 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
254 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
255 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
256 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
257 | ||
258 | /* switch power to VAUX */ | |
259 | if (vaux && state != PCI_D3cold) | |
260 | sky2_write8(hw, B0_POWER_CTRL, | |
261 | (PC_VAUX_ENA | PC_VCC_ENA | | |
262 | PC_VAUX_ON | PC_VCC_OFF)); | |
263 | break; | |
264 | default: | |
265 | printk(KERN_ERR PFX "Unknown power state %d\n", state); | |
266 | ret = -1; | |
267 | } | |
268 | ||
269 | pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control); | |
270 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
271 | return ret; | |
272 | } | |
273 | ||
cd28ab6a SH |
274 | static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) |
275 | { | |
276 | u16 reg; | |
277 | ||
278 | /* disable all GMAC IRQ's */ | |
279 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
280 | /* disable PHY IRQs */ | |
281 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 282 | |
cd28ab6a SH |
283 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
284 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
285 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
286 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
287 | ||
288 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
289 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
290 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
291 | } | |
292 | ||
293 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |
294 | { | |
295 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
793b883e | 296 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; |
cd28ab6a | 297 | |
793b883e | 298 | if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) { |
cd28ab6a SH |
299 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
300 | ||
301 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 302 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
303 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
304 | ||
305 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
306 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; | |
307 | else | |
308 | ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); | |
309 | ||
310 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
311 | } | |
312 | ||
313 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
314 | if (hw->copper) { | |
315 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
316 | /* enable automatic crossover */ | |
317 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
318 | } else { | |
319 | /* disable energy detect */ | |
320 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
321 | ||
322 | /* enable automatic crossover */ | |
323 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
324 | ||
325 | if (sky2->autoneg == AUTONEG_ENABLE && | |
326 | hw->chip_id == CHIP_ID_YUKON_XL) { | |
327 | ctrl &= ~PHY_M_PC_DSC_MSK; | |
328 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
329 | } | |
330 | } | |
331 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
332 | } else { | |
333 | /* workaround for deviation #4.88 (CRC errors) */ | |
334 | /* disable Automatic Crossover */ | |
335 | ||
336 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
337 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
338 | ||
339 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | |
340 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | |
341 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
342 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
343 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
344 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
345 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
346 | ||
347 | /* select page 1 to access Fiber registers */ | |
348 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
349 | } | |
cd28ab6a SH |
350 | } |
351 | ||
352 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
353 | if (sky2->autoneg == AUTONEG_DISABLE) | |
354 | ctrl &= ~PHY_CT_ANE; | |
355 | else | |
356 | ctrl |= PHY_CT_ANE; | |
357 | ||
358 | ctrl |= PHY_CT_RESET; | |
359 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
360 | ||
361 | ctrl = 0; | |
362 | ct1000 = 0; | |
363 | adv = PHY_AN_CSMA; | |
364 | ||
365 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
366 | if (hw->copper) { | |
367 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
368 | ct1000 |= PHY_M_1000C_AFD; | |
369 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
370 | ct1000 |= PHY_M_1000C_AHD; | |
371 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
372 | adv |= PHY_M_AN_100_FD; | |
373 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
374 | adv |= PHY_M_AN_100_HD; | |
375 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
376 | adv |= PHY_M_AN_10_FD; | |
377 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
378 | adv |= PHY_M_AN_10_HD; | |
793b883e | 379 | } else /* special defines for FIBER (88E1011S only) */ |
cd28ab6a SH |
380 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
381 | ||
382 | /* Set Flow-control capabilities */ | |
383 | if (sky2->tx_pause && sky2->rx_pause) | |
793b883e | 384 | adv |= PHY_AN_PAUSE_CAP; /* symmetric */ |
cd28ab6a | 385 | else if (sky2->rx_pause && !sky2->tx_pause) |
793b883e | 386 | adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; |
cd28ab6a SH |
387 | else if (!sky2->rx_pause && sky2->tx_pause) |
388 | adv |= PHY_AN_PAUSE_ASYM; /* local */ | |
389 | ||
390 | /* Restart Auto-negotiation */ | |
391 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
392 | } else { | |
393 | /* forced speed/duplex settings */ | |
394 | ct1000 = PHY_M_1000C_MSE; | |
395 | ||
396 | if (sky2->duplex == DUPLEX_FULL) | |
397 | ctrl |= PHY_CT_DUP_MD; | |
398 | ||
399 | switch (sky2->speed) { | |
400 | case SPEED_1000: | |
401 | ctrl |= PHY_CT_SP1000; | |
402 | break; | |
403 | case SPEED_100: | |
404 | ctrl |= PHY_CT_SP100; | |
405 | break; | |
406 | } | |
407 | ||
408 | ctrl |= PHY_CT_RESET; | |
409 | } | |
410 | ||
411 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
412 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
413 | ||
414 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
415 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
416 | ||
417 | /* Setup Phy LED's */ | |
418 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
419 | ledover = 0; | |
420 | ||
421 | switch (hw->chip_id) { | |
422 | case CHIP_ID_YUKON_FE: | |
423 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
424 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
425 | ||
426 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
427 | ||
428 | /* delete ACT LED control bits */ | |
429 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
430 | /* change ACT LED control to blink mode */ | |
431 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
432 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
433 | break; | |
434 | ||
435 | case CHIP_ID_YUKON_XL: | |
793b883e | 436 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
437 | |
438 | /* select page 3 to access LED control register */ | |
439 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
440 | ||
441 | /* set LED Function Control register */ | |
793b883e SH |
442 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ |
443 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
444 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
445 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
446 | |
447 | /* set Polarity Control register */ | |
448 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
449 | (PHY_M_POLC_LS1_P_MIX(4) | |
450 | PHY_M_POLC_IS0_P_MIX(4) | | |
451 | PHY_M_POLC_LOS_CTRL(2) | | |
452 | PHY_M_POLC_INIT_CTRL(2) | | |
453 | PHY_M_POLC_STA1_CTRL(2) | | |
454 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
455 | |
456 | /* restore page register */ | |
793b883e | 457 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a SH |
458 | break; |
459 | ||
460 | default: | |
461 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
462 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
463 | /* turn off the Rx LED (LED_RX) */ | |
464 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
465 | } | |
466 | ||
467 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
468 | ||
469 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { | |
470 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
471 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
472 | } | |
473 | ||
474 | if (ledover) | |
475 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
476 | ||
d571b694 | 477 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
cd28ab6a SH |
478 | if (sky2->autoneg == AUTONEG_ENABLE) |
479 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
480 | else | |
481 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
482 | } | |
483 | ||
484 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) | |
485 | { | |
486 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
487 | u16 reg; | |
488 | int i; | |
489 | const u8 *addr = hw->dev[port]->dev_addr; | |
490 | ||
42eeea01 SH |
491 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
492 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); | |
cd28ab6a SH |
493 | |
494 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
495 | ||
793b883e | 496 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
497 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
498 | /* clear GMAC 1 Control reset */ | |
499 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
500 | do { | |
501 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
502 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
503 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
504 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
505 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
506 | } | |
507 | ||
cd28ab6a SH |
508 | if (sky2->autoneg == AUTONEG_DISABLE) { |
509 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
510 | reg |= GM_GPCR_AU_ALL_DIS; | |
511 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
512 | gma_read16(hw, port, GM_GP_CTRL); | |
513 | ||
cd28ab6a SH |
514 | switch (sky2->speed) { |
515 | case SPEED_1000: | |
516 | reg |= GM_GPCR_SPEED_1000; | |
517 | /* fallthru */ | |
518 | case SPEED_100: | |
519 | reg |= GM_GPCR_SPEED_100; | |
520 | } | |
521 | ||
522 | if (sky2->duplex == DUPLEX_FULL) | |
523 | reg |= GM_GPCR_DUP_FULL; | |
524 | } else | |
525 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
526 | ||
527 | if (!sky2->tx_pause && !sky2->rx_pause) { | |
528 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e SH |
529 | reg |= |
530 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
531 | } else if (sky2->tx_pause && !sky2->rx_pause) { | |
cd28ab6a SH |
532 | /* disable Rx flow-control */ |
533 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
534 | } | |
535 | ||
536 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
537 | ||
793b883e | 538 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a SH |
539 | |
540 | spin_lock_bh(&hw->phy_lock); | |
541 | sky2_phy_init(hw, port); | |
542 | spin_unlock_bh(&hw->phy_lock); | |
543 | ||
544 | /* MIB clear */ | |
545 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
546 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
547 | ||
548 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
793b883e | 549 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i); |
cd28ab6a SH |
550 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
551 | ||
552 | /* transmit control */ | |
553 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
554 | ||
555 | /* receive control reg: unicast + multicast + no FCS */ | |
556 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 557 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
558 | |
559 | /* transmit flow control */ | |
560 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
561 | ||
562 | /* transmit parameter */ | |
563 | gma_write16(hw, port, GM_TX_PARAM, | |
564 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
565 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
566 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
567 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
568 | ||
569 | /* serial mode register */ | |
570 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 571 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 572 | |
6b1a3aef | 573 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
574 | reg |= GM_SMOD_JUMBO_ENA; |
575 | ||
576 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
577 | ||
cd28ab6a SH |
578 | /* virtual address for data */ |
579 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
580 | ||
793b883e SH |
581 | /* physical address: used for pause frames */ |
582 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
583 | ||
584 | /* ignore counter overflows */ | |
cd28ab6a SH |
585 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
586 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
587 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
588 | ||
589 | /* Configure Rx MAC FIFO */ | |
590 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
793b883e | 591 | sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T), |
d1f13708 | 592 | GMF_RX_CTRL_DEF); |
cd28ab6a | 593 | |
d571b694 | 594 | /* Flush Rx MAC FIFO on any flow control or error */ |
42eeea01 | 595 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
cd28ab6a | 596 | |
793b883e SH |
597 | /* Set threshold to 0xa (64 bytes) |
598 | * ASF disabled so no need to do WA dev #4.30 | |
cd28ab6a SH |
599 | */ |
600 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
601 | ||
602 | /* Configure Tx MAC FIFO */ | |
603 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
604 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 SH |
605 | |
606 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
607 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); | |
608 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); | |
609 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | |
610 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
611 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); | |
612 | /* Disable Store & Forward mode for TX */ | |
613 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); | |
614 | } | |
615 | } | |
616 | ||
cd28ab6a SH |
617 | } |
618 | ||
619 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len) | |
620 | { | |
621 | u32 end; | |
622 | ||
623 | start /= 8; | |
624 | len /= 8; | |
625 | end = start + len - 1; | |
793b883e | 626 | |
cd28ab6a SH |
627 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
628 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
629 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
630 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
631 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
632 | ||
633 | if (q == Q_R1 || q == Q_R2) { | |
793b883e SH |
634 | u32 rxup, rxlo; |
635 | ||
636 | rxlo = len/2; | |
637 | rxup = rxlo + len/4; | |
793b883e | 638 | |
cd28ab6a | 639 | /* Set thresholds on receive queue's */ |
793b883e SH |
640 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup); |
641 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo); | |
cd28ab6a SH |
642 | } else { |
643 | /* Enable store & forward on Tx queue's because | |
644 | * Tx FIFO is only 1K on Yukon | |
645 | */ | |
646 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
647 | } | |
648 | ||
649 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 650 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
651 | } |
652 | ||
cd28ab6a SH |
653 | /* Setup Bus Memory Interface */ |
654 | static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm) | |
655 | { | |
656 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
657 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
658 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
659 | sky2_write32(hw, Q_ADDR(q, Q_WM), wm); | |
660 | } | |
661 | ||
cd28ab6a SH |
662 | /* Setup prefetch unit registers. This is the interface between |
663 | * hardware and driver list elements | |
664 | */ | |
665 | static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, | |
666 | u64 addr, u32 last) | |
667 | { | |
cd28ab6a SH |
668 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
669 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
670 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
671 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
672 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
673 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
674 | |
675 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
676 | } |
677 | ||
793b883e SH |
678 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
679 | { | |
680 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
681 | ||
682 | sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE; | |
683 | return le; | |
684 | } | |
cd28ab6a SH |
685 | |
686 | /* | |
d571b694 | 687 | * This is a workaround code taken from SysKonnect sk98lin driver |
793b883e | 688 | * to deal with chip bug on Yukon EC rev 0 in the wraparound case. |
cd28ab6a SH |
689 | */ |
690 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, | |
691 | u16 idx, u16 *last, u16 size) | |
cd28ab6a | 692 | { |
cd28ab6a SH |
693 | if (is_ec_a1(hw) && idx < *last) { |
694 | u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); | |
695 | ||
696 | if (hwget == 0) { | |
697 | /* Start prefetching again */ | |
793b883e | 698 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0); |
cd28ab6a SH |
699 | goto setnew; |
700 | } | |
701 | ||
793b883e | 702 | if (hwget == size - 1) { |
cd28ab6a SH |
703 | /* set watermark to one list element */ |
704 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8); | |
705 | ||
706 | /* set put index to first list element */ | |
707 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0); | |
793b883e SH |
708 | } else /* have hardware go to end of list */ |
709 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), | |
710 | size - 1); | |
cd28ab6a | 711 | } else { |
793b883e | 712 | setnew: |
cd28ab6a | 713 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
cd28ab6a | 714 | } |
bea86103 | 715 | *last = idx; |
cd28ab6a SH |
716 | } |
717 | ||
793b883e | 718 | |
cd28ab6a SH |
719 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
720 | { | |
721 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
722 | sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE; | |
723 | return le; | |
724 | } | |
725 | ||
a018e330 SH |
726 | /* Return high part of DMA address (could be 32 or 64 bit) */ |
727 | static inline u32 high32(dma_addr_t a) | |
728 | { | |
729 | return (a >> 16) >> 16; | |
730 | } | |
731 | ||
793b883e SH |
732 | /* Build description to hardware about buffer */ |
733 | static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re) | |
cd28ab6a SH |
734 | { |
735 | struct sky2_rx_le *le; | |
a018e330 | 736 | u32 hi = high32(re->mapaddr); |
cd28ab6a | 737 | |
793b883e SH |
738 | re->idx = sky2->rx_put; |
739 | if (sky2->rx_addr64 != hi) { | |
cd28ab6a | 740 | le = sky2_next_rx(sky2); |
793b883e | 741 | le->addr = cpu_to_le32(hi); |
cd28ab6a SH |
742 | le->ctrl = 0; |
743 | le->opcode = OP_ADDR64 | HW_OWNER; | |
a018e330 | 744 | sky2->rx_addr64 = high32(re->mapaddr + re->maplen); |
cd28ab6a | 745 | } |
793b883e | 746 | |
cd28ab6a | 747 | le = sky2_next_rx(sky2); |
793b883e SH |
748 | le->addr = cpu_to_le32((u32) re->mapaddr); |
749 | le->length = cpu_to_le16(re->maplen); | |
cd28ab6a SH |
750 | le->ctrl = 0; |
751 | le->opcode = OP_PACKET | HW_OWNER; | |
752 | } | |
753 | ||
793b883e | 754 | |
cd28ab6a SH |
755 | /* Tell chip where to start receive checksum. |
756 | * Actually has two checksums, but set both same to avoid possible byte | |
757 | * order problems. | |
758 | */ | |
793b883e | 759 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a SH |
760 | { |
761 | struct sky2_rx_le *le; | |
762 | ||
cd28ab6a | 763 | le = sky2_next_rx(sky2); |
793b883e | 764 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; |
cd28ab6a SH |
765 | le->ctrl = 0; |
766 | le->opcode = OP_TCPSTART | HW_OWNER; | |
793b883e | 767 | |
793b883e SH |
768 | sky2_write32(sky2->hw, |
769 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
770 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
771 | |
772 | } | |
773 | ||
6b1a3aef SH |
774 | /* |
775 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
776 | * reach the end of packet and since we can't make sure that we have | |
777 | * incoming data, we must reset the BMU while it is not doing a DMA | |
778 | * transfer. Since it is possible that the RX path is still active, | |
779 | * the RX RAM buffer will be stopped first, so any possible incoming | |
780 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
781 | * BMU is polled until any DMA in progress is ended and only then it | |
782 | * will be reset. | |
783 | */ | |
784 | static void sky2_rx_stop(struct sky2_port *sky2) | |
785 | { | |
786 | struct sky2_hw *hw = sky2->hw; | |
787 | unsigned rxq = rxqaddr[sky2->port]; | |
788 | int i; | |
789 | ||
790 | /* disable the RAM Buffer receive queue */ | |
791 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
792 | ||
793 | for (i = 0; i < 0xffff; i++) | |
794 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
795 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
796 | goto stopped; | |
797 | ||
798 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
799 | sky2->netdev->name); | |
800 | stopped: | |
801 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
802 | ||
803 | /* reset the Rx prefetch unit */ | |
804 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
805 | } | |
793b883e | 806 | |
d571b694 | 807 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
808 | static void sky2_rx_clean(struct sky2_port *sky2) |
809 | { | |
810 | unsigned i; | |
811 | ||
812 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 813 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a SH |
814 | struct ring_info *re = sky2->rx_ring + i; |
815 | ||
816 | if (re->skb) { | |
793b883e SH |
817 | pci_unmap_single(sky2->hw->pdev, |
818 | re->mapaddr, re->maplen, | |
cd28ab6a SH |
819 | PCI_DMA_FROMDEVICE); |
820 | kfree_skb(re->skb); | |
821 | re->skb = NULL; | |
822 | } | |
823 | } | |
824 | } | |
825 | ||
ef743d33 SH |
826 | /* Basic MII support */ |
827 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
828 | { | |
829 | struct mii_ioctl_data *data = if_mii(ifr); | |
830 | struct sky2_port *sky2 = netdev_priv(dev); | |
831 | struct sky2_hw *hw = sky2->hw; | |
832 | int err = -EOPNOTSUPP; | |
833 | ||
834 | if (!netif_running(dev)) | |
835 | return -ENODEV; /* Phy still in reset */ | |
836 | ||
837 | switch(cmd) { | |
838 | case SIOCGMIIPHY: | |
839 | data->phy_id = PHY_ADDR_MARV; | |
840 | ||
841 | /* fallthru */ | |
842 | case SIOCGMIIREG: { | |
843 | u16 val = 0; | |
844 | spin_lock_bh(&hw->phy_lock); | |
845 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); | |
846 | spin_unlock_bh(&hw->phy_lock); | |
847 | data->val_out = val; | |
848 | break; | |
849 | } | |
850 | ||
851 | case SIOCSMIIREG: | |
852 | if (!capable(CAP_NET_ADMIN)) | |
853 | return -EPERM; | |
854 | ||
855 | spin_lock_bh(&hw->phy_lock); | |
856 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, | |
857 | data->val_in); | |
858 | spin_unlock_bh(&hw->phy_lock); | |
859 | break; | |
860 | } | |
861 | return err; | |
862 | } | |
863 | ||
d1f13708 SH |
864 | #ifdef SKY2_VLAN_TAG_USED |
865 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
866 | { | |
867 | struct sky2_port *sky2 = netdev_priv(dev); | |
868 | struct sky2_hw *hw = sky2->hw; | |
869 | u16 port = sky2->port; | |
870 | unsigned long flags; | |
871 | ||
872 | spin_lock_irqsave(&sky2->tx_lock, flags); | |
873 | ||
874 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); | |
875 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); | |
876 | sky2->vlgrp = grp; | |
877 | ||
878 | spin_unlock_irqrestore(&sky2->tx_lock, flags); | |
879 | } | |
880 | ||
881 | static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
882 | { | |
883 | struct sky2_port *sky2 = netdev_priv(dev); | |
884 | struct sky2_hw *hw = sky2->hw; | |
885 | u16 port = sky2->port; | |
886 | unsigned long flags; | |
887 | ||
888 | spin_lock_irqsave(&sky2->tx_lock, flags); | |
889 | ||
890 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); | |
891 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); | |
892 | if (sky2->vlgrp) | |
893 | sky2->vlgrp->vlan_devices[vid] = NULL; | |
894 | ||
895 | spin_unlock_irqrestore(&sky2->tx_lock, flags); | |
896 | } | |
897 | #endif | |
898 | ||
79e57d32 | 899 | #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) |
6b1a3aef | 900 | static inline unsigned rx_size(const struct sky2_port *sky2) |
cd28ab6a | 901 | { |
79e57d32 | 902 | return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8); |
cd28ab6a SH |
903 | } |
904 | ||
905 | /* | |
906 | * Allocate and setup receiver buffer pool. | |
907 | * In case of 64 bit dma, there are 2X as many list elements | |
908 | * available as ring entries | |
909 | * and need to reserve one list element so we don't wrap around. | |
79e57d32 SH |
910 | * |
911 | * It appears the hardware has a bug in the FIFO logic that | |
912 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
913 | * is not aligned. This means we can't use skb_reserve to align | |
914 | * the IP header. | |
cd28ab6a | 915 | */ |
6b1a3aef | 916 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 917 | { |
6b1a3aef SH |
918 | struct sky2_hw *hw = sky2->hw; |
919 | unsigned size = rx_size(sky2); | |
920 | unsigned rxq = rxqaddr[sky2->port]; | |
921 | int i; | |
cd28ab6a | 922 | |
6b1a3aef SH |
923 | sky2->rx_put = sky2->rx_next = 0; |
924 | sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600); | |
925 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); | |
926 | ||
927 | rx_set_checksum(sky2); | |
793b883e | 928 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a | 929 | struct ring_info *re = sky2->rx_ring + i; |
cd28ab6a | 930 | |
79e57d32 | 931 | re->skb = dev_alloc_skb(size); |
cd28ab6a SH |
932 | if (!re->skb) |
933 | goto nomem; | |
934 | ||
6b1a3aef | 935 | re->mapaddr = pci_map_single(hw->pdev, re->skb->data, |
79e57d32 SH |
936 | size, PCI_DMA_FROMDEVICE); |
937 | re->maplen = size; | |
793b883e | 938 | sky2_rx_add(sky2, re); |
cd28ab6a SH |
939 | } |
940 | ||
6b1a3aef SH |
941 | /* Tell chip about available buffers */ |
942 | sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); | |
943 | sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX)); | |
cd28ab6a SH |
944 | return 0; |
945 | nomem: | |
946 | sky2_rx_clean(sky2); | |
947 | return -ENOMEM; | |
948 | } | |
949 | ||
950 | /* Bring up network interface. */ | |
951 | static int sky2_up(struct net_device *dev) | |
952 | { | |
953 | struct sky2_port *sky2 = netdev_priv(dev); | |
954 | struct sky2_hw *hw = sky2->hw; | |
955 | unsigned port = sky2->port; | |
956 | u32 ramsize, rxspace; | |
957 | int err = -ENOMEM; | |
958 | ||
959 | if (netif_msg_ifup(sky2)) | |
960 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
961 | ||
962 | /* must be power of 2 */ | |
963 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
964 | TX_RING_SIZE * |
965 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
966 | &sky2->tx_le_map); |
967 | if (!sky2->tx_le) | |
968 | goto err_out; | |
969 | ||
b2f5ad4f | 970 | sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info), |
cd28ab6a SH |
971 | GFP_KERNEL); |
972 | if (!sky2->tx_ring) | |
973 | goto err_out; | |
974 | sky2->tx_prod = sky2->tx_cons = 0; | |
cd28ab6a SH |
975 | |
976 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
977 | &sky2->rx_le_map); | |
978 | if (!sky2->rx_le) | |
979 | goto err_out; | |
980 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
981 | ||
b2f5ad4f | 982 | sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info), |
cd28ab6a SH |
983 | GFP_KERNEL); |
984 | if (!sky2->rx_ring) | |
985 | goto err_out; | |
986 | ||
987 | sky2_mac_init(hw, port); | |
988 | ||
989 | /* Configure RAM buffers */ | |
990 | if (hw->chip_id == CHIP_ID_YUKON_FE || | |
991 | (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2)) | |
992 | ramsize = 4096; | |
993 | else { | |
793b883e SH |
994 | u8 e0 = sky2_read8(hw, B2_E_0); |
995 | ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096); | |
cd28ab6a SH |
996 | } |
997 | ||
998 | /* 2/3 for Rx */ | |
999 | rxspace = (2 * ramsize) / 3; | |
1000 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); | |
1001 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); | |
1002 | ||
793b883e SH |
1003 | /* Make sure SyncQ is disabled */ |
1004 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1005 | RB_RST_SET); | |
1006 | ||
cd28ab6a | 1007 | sky2_qset(hw, txqaddr[port], 0x600); |
5a5b1ea0 SH |
1008 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) |
1009 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | |
1010 | ||
1011 | ||
6b1a3aef SH |
1012 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1013 | TX_RING_SIZE - 1); | |
cd28ab6a | 1014 | |
6b1a3aef | 1015 | err = sky2_rx_start(sky2); |
cd28ab6a SH |
1016 | if (err) |
1017 | goto err_out; | |
1018 | ||
cd28ab6a SH |
1019 | /* Enable interrupts from phy/mac for port */ |
1020 | hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; | |
1021 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1022 | return 0; | |
1023 | ||
1024 | err_out: | |
1025 | if (sky2->rx_le) | |
1026 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1027 | sky2->rx_le, sky2->rx_le_map); | |
1028 | if (sky2->tx_le) | |
1029 | pci_free_consistent(hw->pdev, | |
1030 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1031 | sky2->tx_le, sky2->tx_le_map); | |
1032 | if (sky2->tx_ring) | |
1033 | kfree(sky2->tx_ring); | |
1034 | if (sky2->rx_ring) | |
1035 | kfree(sky2->rx_ring); | |
1036 | ||
1037 | return err; | |
1038 | } | |
1039 | ||
793b883e SH |
1040 | /* Modular subtraction in ring */ |
1041 | static inline int tx_dist(unsigned tail, unsigned head) | |
1042 | { | |
1043 | return (head >= tail ? head : head + TX_RING_SIZE) - tail; | |
1044 | } | |
cd28ab6a | 1045 | |
793b883e SH |
1046 | /* Number of list elements available for next tx */ |
1047 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1048 | { |
793b883e | 1049 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
1050 | } |
1051 | ||
793b883e SH |
1052 | /* Estimate of number of transmit list elements required */ |
1053 | static inline unsigned tx_le_req(const struct sk_buff *skb) | |
cd28ab6a | 1054 | { |
793b883e SH |
1055 | unsigned count; |
1056 | ||
1057 | count = sizeof(dma_addr_t) / sizeof(u32); | |
1058 | count += skb_shinfo(skb)->nr_frags * count; | |
1059 | ||
1060 | if (skb_shinfo(skb)->tso_size) | |
1061 | ++count; | |
1062 | ||
1063 | if (skb->ip_summed) | |
1064 | ++count; | |
1065 | ||
1066 | return count; | |
cd28ab6a SH |
1067 | } |
1068 | ||
793b883e SH |
1069 | /* |
1070 | * Put one packet in ring for transmit. | |
1071 | * A single packet can generate multiple list elements, and | |
1072 | * the number of ring elements will probably be less than the number | |
1073 | * of list elements used. | |
1074 | */ | |
cd28ab6a SH |
1075 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
1076 | { | |
1077 | struct sky2_port *sky2 = netdev_priv(dev); | |
1078 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1079 | struct sky2_tx_le *le = NULL; |
cd28ab6a | 1080 | struct ring_info *re; |
793b883e | 1081 | unsigned long flags; |
cd28ab6a SH |
1082 | unsigned i, len; |
1083 | dma_addr_t mapping; | |
1084 | u32 addr64; | |
1085 | u16 mss; | |
1086 | u8 ctrl; | |
1087 | ||
793b883e SH |
1088 | local_irq_save(flags); |
1089 | if (!spin_trylock(&sky2->tx_lock)) { | |
1090 | local_irq_restore(flags); | |
cd28ab6a | 1091 | return NETDEV_TX_LOCKED; |
793b883e | 1092 | } |
cd28ab6a | 1093 | |
793b883e | 1094 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { |
cd28ab6a | 1095 | netif_stop_queue(dev); |
793b883e | 1096 | spin_unlock_irqrestore(&sky2->tx_lock, flags); |
cd28ab6a SH |
1097 | |
1098 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
1099 | dev->name); | |
1100 | return NETDEV_TX_BUSY; | |
1101 | } | |
1102 | ||
793b883e | 1103 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
1104 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
1105 | dev->name, sky2->tx_prod, skb->len); | |
1106 | ||
cd28ab6a SH |
1107 | len = skb_headlen(skb); |
1108 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
a018e330 | 1109 | addr64 = high32(mapping); |
793b883e SH |
1110 | |
1111 | re = sky2->tx_ring + sky2->tx_prod; | |
1112 | ||
a018e330 SH |
1113 | /* Send high bits if changed or crosses boundary */ |
1114 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { | |
793b883e SH |
1115 | le = get_tx_le(sky2); |
1116 | le->tx.addr = cpu_to_le32(addr64); | |
1117 | le->ctrl = 0; | |
1118 | le->opcode = OP_ADDR64 | HW_OWNER; | |
a018e330 | 1119 | sky2->tx_addr64 = high32(mapping + len); |
793b883e | 1120 | } |
cd28ab6a SH |
1121 | |
1122 | /* Check for TCP Segmentation Offload */ | |
1123 | mss = skb_shinfo(skb)->tso_size; | |
793b883e | 1124 | if (mss != 0) { |
cd28ab6a SH |
1125 | /* just drop the packet if non-linear expansion fails */ |
1126 | if (skb_header_cloned(skb) && | |
1127 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
793b883e SH |
1128 | dev_kfree_skb_any(skb); |
1129 | goto out_unlock; | |
cd28ab6a SH |
1130 | } |
1131 | ||
1132 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ | |
1133 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | |
1134 | mss += ETH_HLEN; | |
793b883e | 1135 | } |
cd28ab6a | 1136 | |
793b883e | 1137 | if (mss != sky2->tx_last_mss) { |
cd28ab6a SH |
1138 | le = get_tx_le(sky2); |
1139 | le->tx.tso.size = cpu_to_le16(mss); | |
793b883e | 1140 | le->tx.tso.rsvd = 0; |
cd28ab6a | 1141 | le->opcode = OP_LRGLEN | HW_OWNER; |
cd28ab6a | 1142 | le->ctrl = 0; |
793b883e | 1143 | sky2->tx_last_mss = mss; |
cd28ab6a SH |
1144 | } |
1145 | ||
cd28ab6a | 1146 | ctrl = 0; |
d1f13708 SH |
1147 | #ifdef SKY2_VLAN_TAG_USED |
1148 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ | |
1149 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | |
1150 | if (!le) { | |
1151 | le = get_tx_le(sky2); | |
1152 | le->tx.addr = 0; | |
1153 | le->opcode = OP_VLAN|HW_OWNER; | |
1154 | le->ctrl = 0; | |
1155 | } else | |
1156 | le->opcode |= OP_VLAN; | |
1157 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1158 | ctrl |= INS_VLAN; | |
1159 | } | |
1160 | #endif | |
1161 | ||
1162 | /* Handle TCP checksum offload */ | |
cd28ab6a | 1163 | if (skb->ip_summed == CHECKSUM_HW) { |
793b883e SH |
1164 | u16 hdr = skb->h.raw - skb->data; |
1165 | u16 offset = hdr + skb->csum; | |
cd28ab6a SH |
1166 | |
1167 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1168 | if (skb->nh.iph->protocol == IPPROTO_UDP) | |
1169 | ctrl |= UDPTCP; | |
1170 | ||
1171 | le = get_tx_le(sky2); | |
1172 | le->tx.csum.start = cpu_to_le16(hdr); | |
793b883e SH |
1173 | le->tx.csum.offset = cpu_to_le16(offset); |
1174 | le->length = 0; /* initial checksum value */ | |
cd28ab6a | 1175 | le->ctrl = 1; /* one packet */ |
793b883e | 1176 | le->opcode = OP_TCPLISW | HW_OWNER; |
cd28ab6a SH |
1177 | } |
1178 | ||
1179 | le = get_tx_le(sky2); | |
1180 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1181 | le->length = cpu_to_le16(len); | |
1182 | le->ctrl = ctrl; | |
793b883e | 1183 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1184 | |
793b883e | 1185 | /* Record the transmit mapping info */ |
cd28ab6a | 1186 | re->skb = skb; |
793b883e SH |
1187 | re->mapaddr = mapping; |
1188 | re->maplen = len; | |
cd28ab6a SH |
1189 | |
1190 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1191 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
793b883e | 1192 | struct ring_info *fre; |
cd28ab6a SH |
1193 | |
1194 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1195 | frag->size, PCI_DMA_TODEVICE); | |
793b883e SH |
1196 | addr64 = (mapping >> 16) >> 16; |
1197 | if (addr64 != sky2->tx_addr64) { | |
1198 | le = get_tx_le(sky2); | |
1199 | le->tx.addr = cpu_to_le32(addr64); | |
1200 | le->ctrl = 0; | |
1201 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1202 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1203 | } |
1204 | ||
1205 | le = get_tx_le(sky2); | |
1206 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1207 | le->length = cpu_to_le16(frag->size); | |
1208 | le->ctrl = ctrl; | |
793b883e | 1209 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1210 | |
793b883e SH |
1211 | fre = sky2->tx_ring |
1212 | + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE; | |
1213 | fre->skb = NULL; | |
1214 | fre->mapaddr = mapping; | |
1215 | fre->maplen = frag->size; | |
cd28ab6a | 1216 | } |
793b883e | 1217 | re->idx = sky2->tx_prod; |
cd28ab6a SH |
1218 | le->ctrl |= EOP; |
1219 | ||
724bca3c | 1220 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod, |
cd28ab6a SH |
1221 | &sky2->tx_last_put, TX_RING_SIZE); |
1222 | ||
793b883e | 1223 | if (tx_avail(sky2) < MAX_SKB_TX_LE + 1) |
cd28ab6a | 1224 | netif_stop_queue(dev); |
793b883e SH |
1225 | |
1226 | out_unlock: | |
1227 | mmiowb(); | |
1228 | spin_unlock_irqrestore(&sky2->tx_lock, flags); | |
cd28ab6a SH |
1229 | |
1230 | dev->trans_start = jiffies; | |
1231 | return NETDEV_TX_OK; | |
1232 | } | |
1233 | ||
cd28ab6a | 1234 | /* |
793b883e SH |
1235 | * Free ring elements from starting at tx_cons until "done" |
1236 | * | |
1237 | * NB: the hardware will tell us about partial completion of multi-part | |
d571b694 | 1238 | * buffers; these are deferred until completion. |
cd28ab6a | 1239 | */ |
d11c13e7 | 1240 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1241 | { |
d11c13e7 | 1242 | struct net_device *dev = sky2->netdev; |
793b883e | 1243 | unsigned i; |
cd28ab6a | 1244 | |
d11c13e7 | 1245 | if (unlikely(netif_msg_tx_done(sky2))) |
d571b694 | 1246 | printk(KERN_DEBUG "%s: tx done, up to %u\n", |
d11c13e7 | 1247 | dev->name, done); |
cd28ab6a SH |
1248 | |
1249 | spin_lock(&sky2->tx_lock); | |
cd28ab6a | 1250 | |
793b883e SH |
1251 | while (sky2->tx_cons != done) { |
1252 | struct ring_info *re = sky2->tx_ring + sky2->tx_cons; | |
1253 | struct sk_buff *skb; | |
cd28ab6a | 1254 | |
793b883e SH |
1255 | /* Check for partial status */ |
1256 | if (tx_dist(sky2->tx_cons, done) | |
1257 | < tx_dist(sky2->tx_cons, re->idx)) | |
1258 | goto out; | |
1259 | ||
1260 | skb = re->skb; | |
1261 | pci_unmap_single(sky2->hw->pdev, | |
1262 | re->mapaddr, re->maplen, PCI_DMA_TODEVICE); | |
1263 | ||
1264 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1265 | struct ring_info *fre; | |
1266 | fre = | |
1267 | sky2->tx_ring + (sky2->tx_cons + i + | |
1268 | 1) % TX_RING_SIZE; | |
1269 | pci_unmap_page(sky2->hw->pdev, fre->mapaddr, | |
1270 | fre->maplen, PCI_DMA_TODEVICE); | |
cd28ab6a SH |
1271 | } |
1272 | ||
cd28ab6a | 1273 | dev_kfree_skb_any(skb); |
cd28ab6a | 1274 | |
793b883e SH |
1275 | sky2->tx_cons = re->idx; |
1276 | } | |
1277 | out: | |
1278 | ||
1279 | if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE) | |
cd28ab6a SH |
1280 | netif_wake_queue(dev); |
1281 | spin_unlock(&sky2->tx_lock); | |
1282 | } | |
1283 | ||
1284 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
1285 | static inline void sky2_tx_clean(struct sky2_port *sky2) | |
1286 | { | |
d11c13e7 | 1287 | sky2_tx_complete(sky2, sky2->tx_prod); |
cd28ab6a SH |
1288 | } |
1289 | ||
1290 | /* Network shutdown */ | |
1291 | static int sky2_down(struct net_device *dev) | |
1292 | { | |
1293 | struct sky2_port *sky2 = netdev_priv(dev); | |
1294 | struct sky2_hw *hw = sky2->hw; | |
1295 | unsigned port = sky2->port; | |
1296 | u16 ctrl; | |
cd28ab6a SH |
1297 | |
1298 | if (netif_msg_ifdown(sky2)) | |
1299 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1300 | ||
1301 | netif_stop_queue(dev); | |
1302 | ||
793b883e SH |
1303 | sky2_phy_reset(hw, port); |
1304 | ||
cd28ab6a SH |
1305 | /* Stop transmitter */ |
1306 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1307 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1308 | ||
1309 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1310 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1311 | |
1312 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1313 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1314 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1315 | ||
1316 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1317 | ||
1318 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1319 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1320 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1321 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1322 | ||
1323 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1324 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1325 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1326 | ||
1327 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1328 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1329 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1330 | ||
1331 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1332 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1333 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1334 | |
1335 | /* Reset the Tx prefetch units */ | |
1336 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1337 | PREF_UNIT_RST_SET); | |
1338 | ||
1339 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1340 | ||
6b1a3aef | 1341 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1342 | |
1343 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1344 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1345 | ||
d571b694 | 1346 | /* turn off LED's */ |
cd28ab6a SH |
1347 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1348 | ||
1349 | sky2_tx_clean(sky2); | |
1350 | sky2_rx_clean(sky2); | |
1351 | ||
1352 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1353 | sky2->rx_le, sky2->rx_le_map); | |
1354 | kfree(sky2->rx_ring); | |
1355 | ||
1356 | pci_free_consistent(hw->pdev, | |
1357 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1358 | sky2->tx_le, sky2->tx_le_map); | |
1359 | kfree(sky2->tx_ring); | |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
1364 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1365 | { | |
793b883e SH |
1366 | if (!hw->copper) |
1367 | return SPEED_1000; | |
1368 | ||
cd28ab6a SH |
1369 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1370 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1371 | ||
1372 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1373 | case PHY_M_PS_SPEED_1000: | |
1374 | return SPEED_1000; | |
1375 | case PHY_M_PS_SPEED_100: | |
1376 | return SPEED_100; | |
1377 | default: | |
1378 | return SPEED_10; | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | static void sky2_link_up(struct sky2_port *sky2) | |
1383 | { | |
1384 | struct sky2_hw *hw = sky2->hw; | |
1385 | unsigned port = sky2->port; | |
1386 | u16 reg; | |
1387 | ||
1388 | /* Enable Transmit FIFO Underrun */ | |
793b883e | 1389 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
cd28ab6a SH |
1390 | |
1391 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1392 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) | |
1393 | reg |= GM_GPCR_DUP_FULL; | |
1394 | ||
cd28ab6a SH |
1395 | /* enable Rx/Tx */ |
1396 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1397 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1398 | gma_read16(hw, port, GM_GP_CTRL); | |
1399 | ||
1400 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1401 | ||
1402 | netif_carrier_on(sky2->netdev); | |
1403 | netif_wake_queue(sky2->netdev); | |
1404 | ||
1405 | /* Turn on link LED */ | |
793b883e | 1406 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1407 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1408 | ||
793b883e SH |
1409 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
1410 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
1411 | ||
1412 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
1413 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
1414 | PHY_M_LEDC_INIT_CTRL(sky2->speed == | |
1415 | SPEED_10 ? 7 : 0) | | |
1416 | PHY_M_LEDC_STA1_CTRL(sky2->speed == | |
1417 | SPEED_100 ? 7 : 0) | | |
1418 | PHY_M_LEDC_STA0_CTRL(sky2->speed == | |
1419 | SPEED_1000 ? 7 : 0)); | |
1420 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
1421 | } | |
1422 | ||
cd28ab6a SH |
1423 | if (netif_msg_link(sky2)) |
1424 | printk(KERN_INFO PFX | |
d571b694 | 1425 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
cd28ab6a SH |
1426 | sky2->netdev->name, sky2->speed, |
1427 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
1428 | (sky2->tx_pause && sky2->rx_pause) ? "both" : | |
793b883e | 1429 | sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); |
cd28ab6a SH |
1430 | } |
1431 | ||
1432 | static void sky2_link_down(struct sky2_port *sky2) | |
1433 | { | |
1434 | struct sky2_hw *hw = sky2->hw; | |
1435 | unsigned port = sky2->port; | |
1436 | u16 reg; | |
1437 | ||
1438 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1439 | ||
1440 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1441 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1442 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1443 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | |
1444 | ||
1445 | if (sky2->rx_pause && !sky2->tx_pause) { | |
1446 | /* restore Asymmetric Pause bit */ | |
1447 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
793b883e SH |
1448 | gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) |
1449 | | PHY_M_AN_ASP); | |
cd28ab6a SH |
1450 | } |
1451 | ||
1452 | sky2_phy_reset(hw, port); | |
1453 | ||
1454 | netif_carrier_off(sky2->netdev); | |
1455 | netif_stop_queue(sky2->netdev); | |
1456 | ||
1457 | /* Turn on link LED */ | |
1458 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1459 | ||
1460 | if (netif_msg_link(sky2)) | |
1461 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
1462 | sky2_phy_init(hw, port); | |
1463 | } | |
1464 | ||
793b883e SH |
1465 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1466 | { | |
1467 | struct sky2_hw *hw = sky2->hw; | |
1468 | unsigned port = sky2->port; | |
1469 | u16 lpa; | |
1470 | ||
1471 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); | |
1472 | ||
1473 | if (lpa & PHY_M_AN_RF) { | |
1474 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1475 | return -1; | |
1476 | } | |
1477 | ||
1478 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
1479 | gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { | |
1480 | printk(KERN_ERR PFX "%s: master/slave fault", | |
1481 | sky2->netdev->name); | |
1482 | return -1; | |
1483 | } | |
1484 | ||
1485 | if (!(aux & PHY_M_PS_SPDUP_RES)) { | |
1486 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1487 | sky2->netdev->name); | |
1488 | return -1; | |
1489 | } | |
1490 | ||
1491 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
1492 | ||
1493 | sky2->speed = sky2_phy_speed(hw, aux); | |
1494 | ||
1495 | /* Pause bits are offset (9..8) */ | |
1496 | if (hw->chip_id == CHIP_ID_YUKON_XL) | |
1497 | aux >>= 6; | |
1498 | ||
1499 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | |
1500 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | |
1501 | ||
1502 | if ((sky2->tx_pause || sky2->rx_pause) | |
1503 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | |
1504 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
1505 | else | |
1506 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1507 | ||
1508 | return 0; | |
1509 | } | |
cd28ab6a SH |
1510 | |
1511 | /* | |
d571b694 | 1512 | * Interrupt from PHY are handled in tasklet (soft irq) |
cd28ab6a SH |
1513 | * because accessing phy registers requires spin wait which might |
1514 | * cause excess interrupt latency. | |
1515 | */ | |
1516 | static void sky2_phy_task(unsigned long data) | |
1517 | { | |
793b883e | 1518 | struct sky2_port *sky2 = (struct sky2_port *)data; |
cd28ab6a | 1519 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a SH |
1520 | u16 istatus, phystat; |
1521 | ||
793b883e SH |
1522 | spin_lock(&hw->phy_lock); |
1523 | istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT); | |
1524 | phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT); | |
cd28ab6a SH |
1525 | |
1526 | if (netif_msg_intr(sky2)) | |
1527 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1528 | sky2->netdev->name, istatus, phystat); | |
1529 | ||
1530 | if (istatus & PHY_M_IS_AN_COMPL) { | |
793b883e SH |
1531 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1532 | sky2_link_up(sky2); | |
1533 | goto out; | |
1534 | } | |
cd28ab6a | 1535 | |
793b883e SH |
1536 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1537 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1538 | |
793b883e SH |
1539 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1540 | sky2->duplex = | |
1541 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1542 | |
793b883e SH |
1543 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1544 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1545 | sky2_link_up(sky2); |
793b883e SH |
1546 | else |
1547 | sky2_link_down(sky2); | |
cd28ab6a | 1548 | } |
793b883e SH |
1549 | out: |
1550 | spin_unlock(&hw->phy_lock); | |
cd28ab6a SH |
1551 | |
1552 | local_irq_disable(); | |
793b883e | 1553 | hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2; |
cd28ab6a SH |
1554 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
1555 | local_irq_enable(); | |
1556 | } | |
1557 | ||
1558 | static void sky2_tx_timeout(struct net_device *dev) | |
1559 | { | |
1560 | struct sky2_port *sky2 = netdev_priv(dev); | |
1561 | ||
1562 | if (netif_msg_timer(sky2)) | |
1563 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1564 | ||
1565 | sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP); | |
1566 | sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR)); | |
1567 | ||
1568 | sky2_tx_clean(sky2); | |
1569 | } | |
1570 | ||
1571 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) | |
1572 | { | |
6b1a3aef SH |
1573 | struct sky2_port *sky2 = netdev_priv(dev); |
1574 | struct sky2_hw *hw = sky2->hw; | |
1575 | int err; | |
1576 | u16 ctl, mode; | |
cd28ab6a SH |
1577 | |
1578 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
1579 | return -EINVAL; | |
1580 | ||
5a5b1ea0 SH |
1581 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) |
1582 | return -EINVAL; | |
1583 | ||
6b1a3aef SH |
1584 | if (!netif_running(dev)) { |
1585 | dev->mtu = new_mtu; | |
1586 | return 0; | |
1587 | } | |
1588 | ||
1589 | local_irq_disable(); | |
1590 | sky2_write32(hw, B0_IMSK, 0); | |
1591 | ||
1592 | ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); | |
1593 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
1594 | sky2_rx_stop(sky2); | |
1595 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
1596 | |
1597 | dev->mtu = new_mtu; | |
6b1a3aef SH |
1598 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
1599 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1600 | ||
1601 | if (dev->mtu > ETH_DATA_LEN) | |
1602 | mode |= GM_SMOD_JUMBO_ENA; | |
1603 | ||
1604 | gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); | |
cd28ab6a | 1605 | |
6b1a3aef | 1606 | sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 1607 | |
6b1a3aef SH |
1608 | err = sky2_rx_start(sky2); |
1609 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); | |
1610 | ||
1611 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1612 | sky2_read32(hw, B0_IMSK); | |
1613 | local_irq_enable(); | |
cd28ab6a SH |
1614 | return err; |
1615 | } | |
1616 | ||
1617 | /* | |
1618 | * Receive one packet. | |
1619 | * For small packets or errors, just reuse existing skb. | |
d571b694 | 1620 | * For larger packets, get new buffer. |
cd28ab6a | 1621 | */ |
d11c13e7 | 1622 | static struct sk_buff *sky2_receive(struct sky2_port *sky2, |
cd28ab6a SH |
1623 | u16 length, u32 status) |
1624 | { | |
cd28ab6a | 1625 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 1626 | struct sk_buff *skb = NULL; |
6b1a3aef | 1627 | const unsigned int bufsize = rx_size(sky2); |
cd28ab6a SH |
1628 | |
1629 | if (unlikely(netif_msg_rx_status(sky2))) | |
1630 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
d11c13e7 | 1631 | sky2->netdev->name, sky2->rx_next, status, length); |
cd28ab6a | 1632 | |
793b883e | 1633 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
cd28ab6a | 1634 | |
42eeea01 | 1635 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
1636 | goto error; |
1637 | ||
42eeea01 SH |
1638 | if (!(status & GMR_FS_RX_OK)) |
1639 | goto resubmit; | |
1640 | ||
793b883e | 1641 | if (length < RX_COPY_THRESHOLD) { |
79e57d32 SH |
1642 | skb = alloc_skb(length + 2, GFP_ATOMIC); |
1643 | if (!skb) | |
793b883e SH |
1644 | goto resubmit; |
1645 | ||
79e57d32 | 1646 | skb_reserve(skb, 2); |
793b883e SH |
1647 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, |
1648 | length, PCI_DMA_FROMDEVICE); | |
79e57d32 | 1649 | memcpy(skb->data, re->skb->data, length); |
d11c13e7 SH |
1650 | skb->ip_summed = re->skb->ip_summed; |
1651 | skb->csum = re->skb->csum; | |
793b883e SH |
1652 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, |
1653 | length, PCI_DMA_FROMDEVICE); | |
793b883e | 1654 | } else { |
79e57d32 SH |
1655 | struct sk_buff *nskb; |
1656 | ||
1657 | nskb = dev_alloc_skb(bufsize); | |
793b883e SH |
1658 | if (!nskb) |
1659 | goto resubmit; | |
cd28ab6a | 1660 | |
793b883e | 1661 | skb = re->skb; |
79e57d32 | 1662 | re->skb = nskb; |
793b883e SH |
1663 | pci_unmap_single(sky2->hw->pdev, re->mapaddr, |
1664 | re->maplen, PCI_DMA_FROMDEVICE); | |
1665 | prefetch(skb->data); | |
cd28ab6a | 1666 | |
793b883e | 1667 | re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, |
79e57d32 SH |
1668 | bufsize, PCI_DMA_FROMDEVICE); |
1669 | re->maplen = bufsize; | |
793b883e | 1670 | } |
cd28ab6a | 1671 | |
79e57d32 | 1672 | skb_put(skb, length); |
793b883e | 1673 | resubmit: |
d11c13e7 | 1674 | re->skb->ip_summed = CHECKSUM_NONE; |
793b883e | 1675 | sky2_rx_add(sky2, re); |
79e57d32 | 1676 | |
bea86103 SH |
1677 | /* Tell receiver about new buffers. */ |
1678 | sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put, | |
1679 | &sky2->rx_last_put, RX_LE_SIZE); | |
1680 | ||
cd28ab6a SH |
1681 | return skb; |
1682 | ||
1683 | error: | |
1684 | if (netif_msg_rx_err(sky2)) | |
1685 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", | |
1686 | sky2->netdev->name, status, length); | |
793b883e SH |
1687 | |
1688 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
cd28ab6a SH |
1689 | sky2->net_stats.rx_length_errors++; |
1690 | if (status & GMR_FS_FRAGMENT) | |
1691 | sky2->net_stats.rx_frame_errors++; | |
1692 | if (status & GMR_FS_CRC_ERR) | |
1693 | sky2->net_stats.rx_crc_errors++; | |
793b883e SH |
1694 | if (status & GMR_FS_RX_FF_OV) |
1695 | sky2->net_stats.rx_fifo_errors++; | |
79e57d32 | 1696 | |
793b883e | 1697 | goto resubmit; |
cd28ab6a SH |
1698 | } |
1699 | ||
793b883e SH |
1700 | /* Transmit ring index in reported status block is encoded as: |
1701 | * | |
1702 | * | TXS2 | TXA2 | TXS1 | TXA1 | |
1703 | */ | |
1704 | static inline u16 tx_index(u8 port, u32 status, u16 len) | |
cd28ab6a SH |
1705 | { |
1706 | if (port == 0) | |
1707 | return status & 0xfff; | |
1708 | else | |
1709 | return ((status >> 24) & 0xff) | (len & 0xf) << 8; | |
1710 | } | |
1711 | ||
1712 | /* | |
cd28ab6a SH |
1713 | * Both ports share the same status interrupt, therefore there is only |
1714 | * one poll routine. | |
cd28ab6a | 1715 | */ |
d11c13e7 | 1716 | static int sky2_poll(struct net_device *dev0, int *budget) |
cd28ab6a | 1717 | { |
d11c13e7 SH |
1718 | struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; |
1719 | unsigned int to_do = min(dev0->quota, *budget); | |
cd28ab6a | 1720 | unsigned int work_done = 0; |
793b883e | 1721 | u16 hwidx; |
cd28ab6a | 1722 | |
793b883e | 1723 | hwidx = sky2_read16(hw, STAT_PUT_IDX); |
79e57d32 | 1724 | BUG_ON(hwidx >= STATUS_RING_SIZE); |
793b883e | 1725 | rmb(); |
bea86103 | 1726 | |
13210ce5 SH |
1727 | while (hwidx != hw->st_idx) { |
1728 | struct sky2_status_le *le = hw->st_le + hw->st_idx; | |
1729 | struct net_device *dev; | |
d11c13e7 | 1730 | struct sky2_port *sky2; |
cd28ab6a | 1731 | struct sk_buff *skb; |
cd28ab6a SH |
1732 | u32 status; |
1733 | u16 length; | |
13210ce5 | 1734 | u8 op; |
cd28ab6a | 1735 | |
13210ce5 | 1736 | le = hw->st_le + hw->st_idx; |
bea86103 | 1737 | hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE; |
13210ce5 | 1738 | prefetch(hw->st_le + hw->st_idx); |
bea86103 SH |
1739 | |
1740 | BUG_ON(le->link >= hw->ports || !hw->dev[le->link]); | |
d1f13708 | 1741 | |
13210ce5 SH |
1742 | BUG_ON(le->link >= 2); |
1743 | dev = hw->dev[le->link]; | |
1744 | if (dev == NULL || !netif_running(dev)) | |
1745 | continue; | |
1746 | ||
1747 | sky2 = netdev_priv(dev); | |
cd28ab6a SH |
1748 | status = le32_to_cpu(le->status); |
1749 | length = le16_to_cpu(le->length); | |
13210ce5 SH |
1750 | op = le->opcode & ~HW_OWNER; |
1751 | le->opcode = 0; | |
cd28ab6a | 1752 | |
13210ce5 | 1753 | switch (op) { |
cd28ab6a | 1754 | case OP_RXSTAT: |
d11c13e7 | 1755 | skb = sky2_receive(sky2, length, status); |
d1f13708 SH |
1756 | if (!skb) |
1757 | break; | |
13210ce5 SH |
1758 | |
1759 | skb->dev = dev; | |
1760 | skb->protocol = eth_type_trans(skb, dev); | |
1761 | dev->last_rx = jiffies; | |
1762 | ||
d1f13708 SH |
1763 | #ifdef SKY2_VLAN_TAG_USED |
1764 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { | |
1765 | vlan_hwaccel_receive_skb(skb, | |
1766 | sky2->vlgrp, | |
1767 | be16_to_cpu(sky2->rx_tag)); | |
1768 | } else | |
1769 | #endif | |
cd28ab6a | 1770 | netif_receive_skb(skb); |
13210ce5 SH |
1771 | |
1772 | if (++work_done >= to_do) | |
1773 | goto exit_loop; | |
cd28ab6a SH |
1774 | break; |
1775 | ||
d1f13708 SH |
1776 | #ifdef SKY2_VLAN_TAG_USED |
1777 | case OP_RXVLAN: | |
1778 | sky2->rx_tag = length; | |
1779 | break; | |
1780 | ||
1781 | case OP_RXCHKSVLAN: | |
1782 | sky2->rx_tag = length; | |
1783 | /* fall through */ | |
1784 | #endif | |
cd28ab6a | 1785 | case OP_RXCHKS: |
d11c13e7 SH |
1786 | skb = sky2->rx_ring[sky2->rx_next].skb; |
1787 | skb->ip_summed = CHECKSUM_HW; | |
1788 | skb->csum = le16_to_cpu(status); | |
cd28ab6a SH |
1789 | break; |
1790 | ||
1791 | case OP_TXINDEXLE: | |
d11c13e7 SH |
1792 | sky2_tx_complete(sky2, |
1793 | tx_index(sky2->port, status, length)); | |
cd28ab6a SH |
1794 | break; |
1795 | ||
cd28ab6a SH |
1796 | default: |
1797 | if (net_ratelimit()) | |
793b883e | 1798 | printk(KERN_WARNING PFX |
13210ce5 | 1799 | "unknown status opcode 0x%x\n", op); |
cd28ab6a SH |
1800 | break; |
1801 | } | |
13210ce5 | 1802 | } |
cd28ab6a | 1803 | |
13210ce5 | 1804 | exit_loop: |
cd28ab6a | 1805 | |
793b883e SH |
1806 | mmiowb(); |
1807 | ||
cd28ab6a SH |
1808 | if (work_done < to_do) { |
1809 | /* | |
1810 | * Another chip workaround, need to restart TX timer if status | |
1811 | * LE was handled. WA_DEV_43_418 | |
1812 | */ | |
1813 | if (is_ec_a1(hw)) { | |
1814 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
1815 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
1816 | } | |
1817 | ||
bea86103 | 1818 | netif_rx_complete(dev0); |
cd28ab6a SH |
1819 | hw->intr_mask |= Y2_IS_STAT_BMU; |
1820 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
13210ce5 SH |
1821 | mmiowb(); |
1822 | return 0; | |
1823 | } else { | |
1824 | *budget -= work_done; | |
1825 | dev0->quota -= work_done; | |
1826 | return 1; | |
cd28ab6a | 1827 | } |
cd28ab6a SH |
1828 | } |
1829 | ||
1830 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
1831 | { | |
1832 | struct net_device *dev = hw->dev[port]; | |
1833 | ||
1834 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
1835 | dev->name, status); | |
1836 | ||
1837 | if (status & Y2_IS_PAR_RD1) { | |
1838 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
1839 | dev->name); | |
1840 | /* Clear IRQ */ | |
1841 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
1842 | } | |
1843 | ||
1844 | if (status & Y2_IS_PAR_WR1) { | |
1845 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
1846 | dev->name); | |
1847 | ||
1848 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
1849 | } | |
1850 | ||
1851 | if (status & Y2_IS_PAR_MAC1) { | |
1852 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
1853 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); | |
1854 | } | |
1855 | ||
1856 | if (status & Y2_IS_PAR_RX1) { | |
1857 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
1858 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); | |
1859 | } | |
1860 | ||
1861 | if (status & Y2_IS_TCP_TXA1) { | |
1862 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name); | |
1863 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); | |
1864 | } | |
1865 | } | |
1866 | ||
1867 | static void sky2_hw_intr(struct sky2_hw *hw) | |
1868 | { | |
1869 | u32 status = sky2_read32(hw, B0_HWE_ISRC); | |
1870 | ||
793b883e | 1871 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 1872 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
1873 | |
1874 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
1875 | u16 pci_err; |
1876 | ||
1877 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err); | |
cd28ab6a SH |
1878 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", |
1879 | pci_name(hw->pdev), pci_err); | |
1880 | ||
1881 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
1882 | pci_write_config_word(hw->pdev, PCI_STATUS, |
1883 | pci_err | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
1884 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
1885 | } | |
1886 | ||
1887 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 1888 | /* PCI-Express uncorrectable Error occurred */ |
793b883e SH |
1889 | u32 pex_err; |
1890 | ||
1891 | pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err); | |
cd28ab6a | 1892 | |
cd28ab6a SH |
1893 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", |
1894 | pci_name(hw->pdev), pex_err); | |
1895 | ||
1896 | /* clear the interrupt */ | |
1897 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
1898 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, |
1899 | 0xffffffffUL); | |
cd28ab6a SH |
1900 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
1901 | ||
1902 | if (pex_err & PEX_FATAL_ERRORS) { | |
1903 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); | |
1904 | hwmsk &= ~Y2_IS_PCI_EXP; | |
1905 | sky2_write32(hw, B0_HWE_IMSK, hwmsk); | |
1906 | } | |
1907 | } | |
1908 | ||
1909 | if (status & Y2_HWE_L1_MASK) | |
1910 | sky2_hw_error(hw, 0, status); | |
1911 | status >>= 8; | |
1912 | if (status & Y2_HWE_L1_MASK) | |
1913 | sky2_hw_error(hw, 1, status); | |
1914 | } | |
1915 | ||
1916 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
1917 | { | |
1918 | struct net_device *dev = hw->dev[port]; | |
1919 | struct sky2_port *sky2 = netdev_priv(dev); | |
1920 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
1921 | ||
1922 | if (netif_msg_intr(sky2)) | |
1923 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
1924 | dev->name, status); | |
1925 | ||
1926 | if (status & GM_IS_RX_FF_OR) { | |
1927 | ++sky2->net_stats.rx_fifo_errors; | |
1928 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); | |
1929 | } | |
1930 | ||
1931 | if (status & GM_IS_TX_FF_UR) { | |
1932 | ++sky2->net_stats.tx_fifo_errors; | |
1933 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); | |
1934 | } | |
cd28ab6a SH |
1935 | } |
1936 | ||
1937 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
1938 | { | |
1939 | struct net_device *dev = hw->dev[port]; | |
1940 | struct sky2_port *sky2 = netdev_priv(dev); | |
1941 | ||
1942 | hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
1943 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1944 | tasklet_schedule(&sky2->phy_task); | |
1945 | } | |
1946 | ||
1947 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |
1948 | { | |
1949 | struct sky2_hw *hw = dev_id; | |
bea86103 | 1950 | struct net_device *dev0 = hw->dev[0]; |
cd28ab6a SH |
1951 | u32 status; |
1952 | ||
1953 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
793b883e | 1954 | if (status == 0 || status == ~0) |
cd28ab6a SH |
1955 | return IRQ_NONE; |
1956 | ||
1957 | if (status & Y2_IS_HW_ERR) | |
1958 | sky2_hw_intr(hw); | |
1959 | ||
793b883e | 1960 | /* Do NAPI for Rx and Tx status */ |
bea86103 | 1961 | if (status & Y2_IS_STAT_BMU) { |
cd28ab6a SH |
1962 | hw->intr_mask &= ~Y2_IS_STAT_BMU; |
1963 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
bea86103 SH |
1964 | prefetch(&hw->st_le[hw->st_idx]); |
1965 | ||
1966 | if (netif_rx_schedule_test(dev0)) | |
1967 | __netif_rx_schedule(dev0); | |
cd28ab6a SH |
1968 | } |
1969 | ||
793b883e | 1970 | if (status & Y2_IS_IRQ_PHY1) |
cd28ab6a SH |
1971 | sky2_phy_intr(hw, 0); |
1972 | ||
1973 | if (status & Y2_IS_IRQ_PHY2) | |
1974 | sky2_phy_intr(hw, 1); | |
1975 | ||
1976 | if (status & Y2_IS_IRQ_MAC1) | |
1977 | sky2_mac_intr(hw, 0); | |
1978 | ||
1979 | if (status & Y2_IS_IRQ_MAC2) | |
1980 | sky2_mac_intr(hw, 1); | |
1981 | ||
cd28ab6a | 1982 | sky2_write32(hw, B0_Y2_SP_ICR, 2); |
793b883e SH |
1983 | |
1984 | sky2_read32(hw, B0_IMSK); | |
1985 | ||
cd28ab6a SH |
1986 | return IRQ_HANDLED; |
1987 | } | |
1988 | ||
1989 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1990 | static void sky2_netpoll(struct net_device *dev) | |
1991 | { | |
1992 | struct sky2_port *sky2 = netdev_priv(dev); | |
1993 | ||
793b883e | 1994 | sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL); |
cd28ab6a SH |
1995 | } |
1996 | #endif | |
1997 | ||
1998 | /* Chip internal frequency for clock calculations */ | |
1999 | static inline u32 sky2_khz(const struct sky2_hw *hw) | |
2000 | { | |
793b883e | 2001 | switch (hw->chip_id) { |
cd28ab6a | 2002 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2003 | case CHIP_ID_YUKON_EC_U: |
cd28ab6a SH |
2004 | return 125000; /* 125 Mhz */ |
2005 | case CHIP_ID_YUKON_FE: | |
2006 | return 100000; /* 100 Mhz */ | |
793b883e | 2007 | default: /* YUKON_XL */ |
cd28ab6a SH |
2008 | return 156000; /* 156 Mhz */ |
2009 | } | |
2010 | } | |
2011 | ||
2012 | static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms) | |
2013 | { | |
2014 | return sky2_khz(hw) * ms; | |
2015 | } | |
2016 | ||
2017 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) | |
2018 | { | |
793b883e | 2019 | return (sky2_khz(hw) * us) / 1000; |
cd28ab6a SH |
2020 | } |
2021 | ||
2022 | static int sky2_reset(struct sky2_hw *hw) | |
2023 | { | |
5afa0a9c | 2024 | u32 ctst; |
cd28ab6a SH |
2025 | u16 status; |
2026 | u8 t8, pmd_type; | |
2027 | int i; | |
2028 | ||
2029 | ctst = sky2_read32(hw, B0_CTST); | |
2030 | ||
2031 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2032 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); | |
2033 | if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { | |
2034 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
2035 | pci_name(hw->pdev), hw->chip_id); | |
2036 | return -EOPNOTSUPP; | |
2037 | } | |
2038 | ||
793b883e SH |
2039 | /* ring for status responses */ |
2040 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | |
2041 | &hw->st_dma); | |
2042 | if (!hw->st_le) | |
2043 | return -ENOMEM; | |
2044 | ||
cd28ab6a SH |
2045 | /* disable ASF */ |
2046 | if (hw->chip_id <= CHIP_ID_YUKON_EC) { | |
2047 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
2048 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
2049 | } | |
2050 | ||
2051 | /* do a SW reset */ | |
2052 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
2053 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2054 | ||
2055 | /* clear PCI errors, if any */ | |
793b883e | 2056 | pci_read_config_word(hw->pdev, PCI_STATUS, &status); |
cd28ab6a | 2057 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
793b883e SH |
2058 | pci_write_config_word(hw->pdev, PCI_STATUS, |
2059 | status | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
2060 | |
2061 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
2062 | ||
2063 | /* clear any PEX errors */ | |
2064 | if (is_pciex(hw)) { | |
793b883e SH |
2065 | u16 lstat; |
2066 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, | |
2067 | 0xffffffffUL); | |
2068 | pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat); | |
cd28ab6a SH |
2069 | } |
2070 | ||
2071 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | |
2072 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | |
2073 | ||
2074 | hw->ports = 1; | |
2075 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
2076 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
2077 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
2078 | ++hw->ports; | |
2079 | } | |
2080 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; | |
2081 | ||
5afa0a9c | 2082 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
2083 | |
2084 | for (i = 0; i < hw->ports; i++) { | |
2085 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
2086 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
2087 | } | |
2088 | ||
2089 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
2090 | ||
793b883e SH |
2091 | /* Clear I2C IRQ noise */ |
2092 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
2093 | |
2094 | /* turn off hardware timer (unused) */ | |
2095 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
2096 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 2097 | |
cd28ab6a SH |
2098 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
2099 | ||
793b883e | 2100 | /* Turn on descriptor polling (every 75us) */ |
cd28ab6a SH |
2101 | sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75)); |
2102 | sky2_write8(hw, B28_DPT_CTRL, DPT_START); | |
2103 | ||
2104 | /* Turn off receive timestamp */ | |
2105 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 2106 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2107 | |
2108 | /* enable the Tx Arbiters */ | |
2109 | for (i = 0; i < hw->ports; i++) | |
2110 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
2111 | ||
2112 | /* Initialize ram interface */ | |
2113 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 2114 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
2115 | |
2116 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
2117 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
2118 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
2119 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
2120 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
2121 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
2122 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
2123 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
2124 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
2125 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
2126 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
2127 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
2128 | } | |
2129 | ||
cd28ab6a | 2130 | if (is_pciex(hw)) { |
793b883e SH |
2131 | u16 pctrl; |
2132 | ||
2133 | /* change Max. Read Request Size to 2048 bytes */ | |
2134 | pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl); | |
2135 | pctrl &= ~PEX_DC_MAX_RRS_MSK; | |
2136 | pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4); | |
2137 | ||
2138 | ||
cd28ab6a | 2139 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
793b883e | 2140 | pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl); |
cd28ab6a SH |
2141 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2142 | } | |
2143 | ||
2144 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); | |
2145 | ||
cd28ab6a SH |
2146 | spin_lock_bh(&hw->phy_lock); |
2147 | for (i = 0; i < hw->ports; i++) | |
2148 | sky2_phy_reset(hw, i); | |
2149 | spin_unlock_bh(&hw->phy_lock); | |
2150 | ||
cd28ab6a SH |
2151 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2152 | hw->st_idx = 0; | |
2153 | ||
2154 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
2155 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
2156 | ||
2157 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 2158 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
2159 | |
2160 | /* Set the list last index */ | |
793b883e | 2161 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 2162 | |
793b883e SH |
2163 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10)); |
2164 | ||
2165 | /* These status setup values are copied from SysKonnect's driver */ | |
cd28ab6a SH |
2166 | if (is_ec_a1(hw)) { |
2167 | /* WA for dev. #4.3 */ | |
793b883e | 2168 | sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */ |
cd28ab6a SH |
2169 | |
2170 | /* set Status-FIFO watermark */ | |
2171 | sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */ | |
2172 | ||
2173 | /* set Status-FIFO ISR watermark */ | |
793b883e | 2174 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */ |
cd28ab6a | 2175 | |
cd28ab6a | 2176 | } else { |
cd28ab6a SH |
2177 | sky2_write16(hw, STAT_TX_IDX_TH, 0x000a); |
2178 | ||
2179 | /* set Status-FIFO watermark */ | |
2180 | sky2_write8(hw, STAT_FIFO_WM, 0x10); | |
2181 | ||
2182 | /* set Status-FIFO ISR watermark */ | |
2183 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
2184 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10); | |
2185 | ||
d571b694 | 2186 | else /* WA dev 4.109 */ |
cd28ab6a SH |
2187 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04); |
2188 | ||
2189 | sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190); | |
2190 | } | |
2191 | ||
793b883e | 2192 | /* enable status unit */ |
cd28ab6a SH |
2193 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2194 | ||
2195 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2196 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2197 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2198 | ||
2199 | return 0; | |
2200 | } | |
2201 | ||
2202 | static inline u32 sky2_supported_modes(const struct sky2_hw *hw) | |
2203 | { | |
2204 | u32 modes; | |
2205 | if (hw->copper) { | |
793b883e SH |
2206 | modes = SUPPORTED_10baseT_Half |
2207 | | SUPPORTED_10baseT_Full | |
2208 | | SUPPORTED_100baseT_Half | |
2209 | | SUPPORTED_100baseT_Full | |
2210 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2211 | |
2212 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
2213 | modes |= SUPPORTED_1000baseT_Half | |
793b883e | 2214 | | SUPPORTED_1000baseT_Full; |
cd28ab6a SH |
2215 | } else |
2216 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
793b883e | 2217 | | SUPPORTED_Autoneg; |
cd28ab6a SH |
2218 | return modes; |
2219 | } | |
2220 | ||
793b883e | 2221 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
2222 | { |
2223 | struct sky2_port *sky2 = netdev_priv(dev); | |
2224 | struct sky2_hw *hw = sky2->hw; | |
2225 | ||
2226 | ecmd->transceiver = XCVR_INTERNAL; | |
2227 | ecmd->supported = sky2_supported_modes(hw); | |
2228 | ecmd->phy_address = PHY_ADDR_MARV; | |
2229 | if (hw->copper) { | |
2230 | ecmd->supported = SUPPORTED_10baseT_Half | |
793b883e SH |
2231 | | SUPPORTED_10baseT_Full |
2232 | | SUPPORTED_100baseT_Half | |
2233 | | SUPPORTED_100baseT_Full | |
2234 | | SUPPORTED_1000baseT_Half | |
2235 | | SUPPORTED_1000baseT_Full | |
2236 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2237 | ecmd->port = PORT_TP; |
2238 | } else | |
2239 | ecmd->port = PORT_FIBRE; | |
2240 | ||
2241 | ecmd->advertising = sky2->advertising; | |
2242 | ecmd->autoneg = sky2->autoneg; | |
2243 | ecmd->speed = sky2->speed; | |
2244 | ecmd->duplex = sky2->duplex; | |
2245 | return 0; | |
2246 | } | |
2247 | ||
2248 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2249 | { | |
2250 | struct sky2_port *sky2 = netdev_priv(dev); | |
2251 | const struct sky2_hw *hw = sky2->hw; | |
2252 | u32 supported = sky2_supported_modes(hw); | |
2253 | ||
2254 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2255 | ecmd->advertising = supported; | |
2256 | sky2->duplex = -1; | |
2257 | sky2->speed = -1; | |
2258 | } else { | |
2259 | u32 setting; | |
2260 | ||
793b883e | 2261 | switch (ecmd->speed) { |
cd28ab6a SH |
2262 | case SPEED_1000: |
2263 | if (ecmd->duplex == DUPLEX_FULL) | |
2264 | setting = SUPPORTED_1000baseT_Full; | |
2265 | else if (ecmd->duplex == DUPLEX_HALF) | |
2266 | setting = SUPPORTED_1000baseT_Half; | |
2267 | else | |
2268 | return -EINVAL; | |
2269 | break; | |
2270 | case SPEED_100: | |
2271 | if (ecmd->duplex == DUPLEX_FULL) | |
2272 | setting = SUPPORTED_100baseT_Full; | |
2273 | else if (ecmd->duplex == DUPLEX_HALF) | |
2274 | setting = SUPPORTED_100baseT_Half; | |
2275 | else | |
2276 | return -EINVAL; | |
2277 | break; | |
2278 | ||
2279 | case SPEED_10: | |
2280 | if (ecmd->duplex == DUPLEX_FULL) | |
2281 | setting = SUPPORTED_10baseT_Full; | |
2282 | else if (ecmd->duplex == DUPLEX_HALF) | |
2283 | setting = SUPPORTED_10baseT_Half; | |
2284 | else | |
2285 | return -EINVAL; | |
2286 | break; | |
2287 | default: | |
2288 | return -EINVAL; | |
2289 | } | |
2290 | ||
2291 | if ((setting & supported) == 0) | |
2292 | return -EINVAL; | |
2293 | ||
2294 | sky2->speed = ecmd->speed; | |
2295 | sky2->duplex = ecmd->duplex; | |
2296 | } | |
2297 | ||
2298 | sky2->autoneg = ecmd->autoneg; | |
2299 | sky2->advertising = ecmd->advertising; | |
2300 | ||
2301 | if (netif_running(dev)) { | |
2302 | sky2_down(dev); | |
2303 | sky2_up(dev); | |
2304 | } | |
2305 | ||
2306 | return 0; | |
2307 | } | |
2308 | ||
2309 | static void sky2_get_drvinfo(struct net_device *dev, | |
2310 | struct ethtool_drvinfo *info) | |
2311 | { | |
2312 | struct sky2_port *sky2 = netdev_priv(dev); | |
2313 | ||
2314 | strcpy(info->driver, DRV_NAME); | |
2315 | strcpy(info->version, DRV_VERSION); | |
2316 | strcpy(info->fw_version, "N/A"); | |
2317 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
2318 | } | |
2319 | ||
2320 | static const struct sky2_stat { | |
793b883e SH |
2321 | char name[ETH_GSTRING_LEN]; |
2322 | u16 offset; | |
cd28ab6a SH |
2323 | } sky2_stats[] = { |
2324 | { "tx_bytes", GM_TXO_OK_HI }, | |
2325 | { "rx_bytes", GM_RXO_OK_HI }, | |
2326 | { "tx_broadcast", GM_TXF_BC_OK }, | |
2327 | { "rx_broadcast", GM_RXF_BC_OK }, | |
2328 | { "tx_multicast", GM_TXF_MC_OK }, | |
2329 | { "rx_multicast", GM_RXF_MC_OK }, | |
2330 | { "tx_unicast", GM_TXF_UC_OK }, | |
2331 | { "rx_unicast", GM_RXF_UC_OK }, | |
2332 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
2333 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
2334 | { "collisions", GM_TXF_SNG_COL }, | |
2335 | { "late_collision",GM_TXF_LAT_COL }, | |
2336 | { "aborted", GM_TXF_ABO_COL }, | |
2337 | { "multi_collisions", GM_TXF_MUL_COL }, | |
2338 | { "fifo_underrun", GM_TXE_FIFO_UR }, | |
2339 | { "fifo_overflow", GM_RXE_FIFO_OV }, | |
2340 | { "rx_toolong", GM_RXF_LNG_ERR }, | |
2341 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
2342 | { "rx_runt", GM_RXE_FRAG }, | |
2343 | { "rx_too_long", GM_RXF_LNG_ERR }, | |
2344 | { "rx_fcs_error", GM_RXF_FCS_ERR }, | |
2345 | }; | |
2346 | ||
cd28ab6a SH |
2347 | static u32 sky2_get_rx_csum(struct net_device *dev) |
2348 | { | |
2349 | struct sky2_port *sky2 = netdev_priv(dev); | |
2350 | ||
2351 | return sky2->rx_csum; | |
2352 | } | |
2353 | ||
2354 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
2355 | { | |
2356 | struct sky2_port *sky2 = netdev_priv(dev); | |
2357 | ||
2358 | sky2->rx_csum = data; | |
793b883e | 2359 | |
cd28ab6a SH |
2360 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2361 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
2362 | ||
2363 | return 0; | |
2364 | } | |
2365 | ||
2366 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
2367 | { | |
2368 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2369 | return sky2->msg_enable; | |
2370 | } | |
2371 | ||
9a7ae0a9 SH |
2372 | static int sky2_nway_reset(struct net_device *dev) |
2373 | { | |
2374 | struct sky2_port *sky2 = netdev_priv(dev); | |
2375 | struct sky2_hw *hw = sky2->hw; | |
2376 | ||
2377 | if (sky2->autoneg != AUTONEG_ENABLE) | |
2378 | return -EINVAL; | |
2379 | ||
2380 | netif_stop_queue(dev); | |
2381 | ||
2382 | spin_lock_irq(&hw->phy_lock); | |
2383 | sky2_phy_reset(hw, sky2->port); | |
2384 | sky2_phy_init(hw, sky2->port); | |
2385 | spin_unlock_irq(&hw->phy_lock); | |
2386 | ||
2387 | return 0; | |
2388 | } | |
2389 | ||
793b883e | 2390 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
2391 | { |
2392 | struct sky2_hw *hw = sky2->hw; | |
2393 | unsigned port = sky2->port; | |
2394 | int i; | |
2395 | ||
2396 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 2397 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 2398 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 2399 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 2400 | |
793b883e | 2401 | for (i = 2; i < count; i++) |
cd28ab6a SH |
2402 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
2403 | } | |
2404 | ||
cd28ab6a SH |
2405 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
2406 | { | |
2407 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2408 | sky2->msg_enable = value; | |
2409 | } | |
2410 | ||
2411 | static int sky2_get_stats_count(struct net_device *dev) | |
2412 | { | |
2413 | return ARRAY_SIZE(sky2_stats); | |
2414 | } | |
2415 | ||
2416 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 2417 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
2418 | { |
2419 | struct sky2_port *sky2 = netdev_priv(dev); | |
2420 | ||
793b883e | 2421 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
2422 | } |
2423 | ||
793b883e | 2424 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
2425 | { |
2426 | int i; | |
2427 | ||
2428 | switch (stringset) { | |
2429 | case ETH_SS_STATS: | |
2430 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
2431 | memcpy(data + i * ETH_GSTRING_LEN, | |
2432 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
2433 | break; | |
2434 | } | |
2435 | } | |
2436 | ||
2437 | /* Use hardware MIB variables for critical path statistics and | |
2438 | * transmit feedback not reported at interrupt. | |
2439 | * Other errors are accounted for in interrupt handler. | |
2440 | */ | |
2441 | static struct net_device_stats *sky2_get_stats(struct net_device *dev) | |
2442 | { | |
2443 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2444 | u64 data[13]; |
cd28ab6a | 2445 | |
793b883e | 2446 | sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); |
cd28ab6a SH |
2447 | |
2448 | sky2->net_stats.tx_bytes = data[0]; | |
2449 | sky2->net_stats.rx_bytes = data[1]; | |
2450 | sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
2451 | sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
2452 | sky2->net_stats.multicast = data[5] + data[7]; | |
2453 | sky2->net_stats.collisions = data[10]; | |
2454 | sky2->net_stats.tx_aborted_errors = data[12]; | |
2455 | ||
2456 | return &sky2->net_stats; | |
2457 | } | |
2458 | ||
2459 | static int sky2_set_mac_address(struct net_device *dev, void *p) | |
2460 | { | |
2461 | struct sky2_port *sky2 = netdev_priv(dev); | |
2462 | struct sockaddr *addr = p; | |
2463 | int err = 0; | |
2464 | ||
2465 | if (!is_valid_ether_addr(addr->sa_data)) | |
2466 | return -EADDRNOTAVAIL; | |
2467 | ||
2468 | sky2_down(dev); | |
2469 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
793b883e | 2470 | memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8, |
cd28ab6a | 2471 | dev->dev_addr, ETH_ALEN); |
793b883e | 2472 | memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8, |
cd28ab6a SH |
2473 | dev->dev_addr, ETH_ALEN); |
2474 | if (dev->flags & IFF_UP) | |
2475 | err = sky2_up(dev); | |
2476 | return err; | |
2477 | } | |
2478 | ||
2479 | static void sky2_set_multicast(struct net_device *dev) | |
2480 | { | |
2481 | struct sky2_port *sky2 = netdev_priv(dev); | |
2482 | struct sky2_hw *hw = sky2->hw; | |
2483 | unsigned port = sky2->port; | |
2484 | struct dev_mc_list *list = dev->mc_list; | |
2485 | u16 reg; | |
2486 | u8 filter[8]; | |
2487 | ||
2488 | memset(filter, 0, sizeof(filter)); | |
2489 | ||
2490 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
2491 | reg |= GM_RXCR_UCF_ENA; | |
2492 | ||
d571b694 | 2493 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 2494 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
793b883e | 2495 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ |
cd28ab6a | 2496 | memset(filter, 0xff, sizeof(filter)); |
793b883e | 2497 | else if (dev->mc_count == 0) /* no multicast */ |
cd28ab6a SH |
2498 | reg &= ~GM_RXCR_MCF_ENA; |
2499 | else { | |
2500 | int i; | |
2501 | reg |= GM_RXCR_MCF_ENA; | |
2502 | ||
2503 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2504 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
793b883e | 2505 | filter[bit / 8] |= 1 << (bit % 8); |
cd28ab6a SH |
2506 | } |
2507 | } | |
2508 | ||
cd28ab6a | 2509 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 2510 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 2511 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 2512 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 2513 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 2514 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 2515 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 2516 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
2517 | |
2518 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
2519 | } | |
2520 | ||
2521 | /* Can have one global because blinking is controlled by | |
2522 | * ethtool and that is always under RTNL mutex | |
2523 | */ | |
2524 | static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on) | |
2525 | { | |
793b883e SH |
2526 | u16 pg; |
2527 | ||
cd28ab6a | 2528 | spin_lock_bh(&hw->phy_lock); |
793b883e SH |
2529 | switch (hw->chip_id) { |
2530 | case CHIP_ID_YUKON_XL: | |
2531 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2532 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2533 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
2534 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
2535 | PHY_M_LEDC_INIT_CTRL(7) | | |
2536 | PHY_M_LEDC_STA1_CTRL(7) | | |
2537 | PHY_M_LEDC_STA0_CTRL(7)) | |
2538 | : 0); | |
2539 | ||
2540 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2541 | break; | |
2542 | ||
2543 | default: | |
2544 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
cd28ab6a | 2545 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
793b883e SH |
2546 | on ? PHY_M_LED_MO_DUP(MO_LED_ON) | |
2547 | PHY_M_LED_MO_10(MO_LED_ON) | | |
2548 | PHY_M_LED_MO_100(MO_LED_ON) | | |
cd28ab6a | 2549 | PHY_M_LED_MO_1000(MO_LED_ON) | |
793b883e SH |
2550 | PHY_M_LED_MO_RX(MO_LED_ON) |
2551 | : PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
2552 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
2553 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
cd28ab6a SH |
2554 | PHY_M_LED_MO_1000(MO_LED_OFF) | |
2555 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
2556 | ||
793b883e | 2557 | } |
cd28ab6a SH |
2558 | spin_unlock_bh(&hw->phy_lock); |
2559 | } | |
2560 | ||
2561 | /* blink LED's for finding board */ | |
2562 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
2563 | { | |
2564 | struct sky2_port *sky2 = netdev_priv(dev); | |
2565 | struct sky2_hw *hw = sky2->hw; | |
2566 | unsigned port = sky2->port; | |
793b883e | 2567 | u16 ledctrl, ledover = 0; |
cd28ab6a SH |
2568 | long ms; |
2569 | int onoff = 1; | |
2570 | ||
793b883e | 2571 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
2572 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
2573 | else | |
2574 | ms = data * 1000; | |
2575 | ||
2576 | /* save initial values */ | |
2577 | spin_lock_bh(&hw->phy_lock); | |
793b883e SH |
2578 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2579 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2580 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2581 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2582 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2583 | } else { | |
2584 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
2585 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
2586 | } | |
cd28ab6a SH |
2587 | spin_unlock_bh(&hw->phy_lock); |
2588 | ||
2589 | while (ms > 0) { | |
2590 | sky2_led(hw, port, onoff); | |
2591 | onoff = !onoff; | |
2592 | ||
2593 | if (msleep_interruptible(250)) | |
2594 | break; /* interrupted */ | |
2595 | ms -= 250; | |
2596 | } | |
2597 | ||
2598 | /* resume regularly scheduled programming */ | |
2599 | spin_lock_bh(&hw->phy_lock); | |
793b883e SH |
2600 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2601 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2602 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2603 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
2604 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2605 | } else { | |
2606 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
2607 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
2608 | } | |
cd28ab6a SH |
2609 | spin_unlock_bh(&hw->phy_lock); |
2610 | ||
2611 | return 0; | |
2612 | } | |
2613 | ||
2614 | static void sky2_get_pauseparam(struct net_device *dev, | |
2615 | struct ethtool_pauseparam *ecmd) | |
2616 | { | |
2617 | struct sky2_port *sky2 = netdev_priv(dev); | |
2618 | ||
2619 | ecmd->tx_pause = sky2->tx_pause; | |
2620 | ecmd->rx_pause = sky2->rx_pause; | |
2621 | ecmd->autoneg = sky2->autoneg; | |
2622 | } | |
2623 | ||
2624 | static int sky2_set_pauseparam(struct net_device *dev, | |
2625 | struct ethtool_pauseparam *ecmd) | |
2626 | { | |
2627 | struct sky2_port *sky2 = netdev_priv(dev); | |
2628 | int err = 0; | |
2629 | ||
2630 | sky2->autoneg = ecmd->autoneg; | |
2631 | sky2->tx_pause = ecmd->tx_pause != 0; | |
2632 | sky2->rx_pause = ecmd->rx_pause != 0; | |
2633 | ||
2634 | if (netif_running(dev)) { | |
2635 | sky2_down(dev); | |
2636 | err = sky2_up(dev); | |
2637 | } | |
2638 | ||
2639 | return err; | |
2640 | } | |
2641 | ||
2642 | #ifdef CONFIG_PM | |
2643 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2644 | { | |
2645 | struct sky2_port *sky2 = netdev_priv(dev); | |
2646 | ||
2647 | wol->supported = WAKE_MAGIC; | |
2648 | wol->wolopts = sky2->wol ? WAKE_MAGIC : 0; | |
2649 | } | |
2650 | ||
2651 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2652 | { | |
2653 | struct sky2_port *sky2 = netdev_priv(dev); | |
2654 | struct sky2_hw *hw = sky2->hw; | |
2655 | ||
2656 | if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) | |
2657 | return -EOPNOTSUPP; | |
2658 | ||
2659 | sky2->wol = wol->wolopts == WAKE_MAGIC; | |
2660 | ||
2661 | if (sky2->wol) { | |
2662 | memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN); | |
2663 | ||
2664 | sky2_write16(hw, WOL_CTRL_STAT, | |
2665 | WOL_CTL_ENA_PME_ON_MAGIC_PKT | | |
2666 | WOL_CTL_ENA_MAGIC_PKT_UNIT); | |
2667 | } else | |
2668 | sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT); | |
2669 | ||
2670 | return 0; | |
2671 | } | |
2672 | #endif | |
2673 | ||
793b883e SH |
2674 | static void sky2_get_ringparam(struct net_device *dev, |
2675 | struct ethtool_ringparam *ering) | |
2676 | { | |
2677 | struct sky2_port *sky2 = netdev_priv(dev); | |
2678 | ||
2679 | ering->rx_max_pending = RX_MAX_PENDING; | |
2680 | ering->rx_mini_max_pending = 0; | |
2681 | ering->rx_jumbo_max_pending = 0; | |
2682 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
2683 | ||
2684 | ering->rx_pending = sky2->rx_pending; | |
2685 | ering->rx_mini_pending = 0; | |
2686 | ering->rx_jumbo_pending = 0; | |
2687 | ering->tx_pending = sky2->tx_pending; | |
2688 | } | |
2689 | ||
2690 | static int sky2_set_ringparam(struct net_device *dev, | |
2691 | struct ethtool_ringparam *ering) | |
2692 | { | |
2693 | struct sky2_port *sky2 = netdev_priv(dev); | |
2694 | int err = 0; | |
2695 | ||
2696 | if (ering->rx_pending > RX_MAX_PENDING || | |
2697 | ering->rx_pending < 8 || | |
2698 | ering->tx_pending < MAX_SKB_TX_LE || | |
2699 | ering->tx_pending > TX_RING_SIZE - 1) | |
2700 | return -EINVAL; | |
2701 | ||
2702 | if (netif_running(dev)) | |
2703 | sky2_down(dev); | |
2704 | ||
2705 | sky2->rx_pending = ering->rx_pending; | |
2706 | sky2->tx_pending = ering->tx_pending; | |
2707 | ||
2708 | if (netif_running(dev)) | |
2709 | err = sky2_up(dev); | |
2710 | ||
2711 | return err; | |
2712 | } | |
2713 | ||
793b883e SH |
2714 | static int sky2_get_regs_len(struct net_device *dev) |
2715 | { | |
6e4cbb34 | 2716 | return 0x4000; |
793b883e SH |
2717 | } |
2718 | ||
2719 | /* | |
2720 | * Returns copy of control register region | |
6e4cbb34 | 2721 | * Note: access to the RAM address register set will cause timeouts. |
793b883e SH |
2722 | */ |
2723 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2724 | void *p) | |
2725 | { | |
2726 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2727 | const void __iomem *io = sky2->hw->regs; |
793b883e | 2728 | |
6e4cbb34 | 2729 | BUG_ON(regs->len < B3_RI_WTO_R1); |
793b883e | 2730 | regs->version = 1; |
6e4cbb34 | 2731 | memset(p, 0, regs->len); |
793b883e | 2732 | |
6e4cbb34 SH |
2733 | memcpy_fromio(p, io, B3_RAM_ADDR); |
2734 | ||
2735 | memcpy_fromio(p + B3_RI_WTO_R1, | |
2736 | io + B3_RI_WTO_R1, | |
2737 | regs->len - B3_RI_WTO_R1); | |
793b883e | 2738 | } |
cd28ab6a SH |
2739 | |
2740 | static struct ethtool_ops sky2_ethtool_ops = { | |
793b883e SH |
2741 | .get_settings = sky2_get_settings, |
2742 | .set_settings = sky2_set_settings, | |
2743 | .get_drvinfo = sky2_get_drvinfo, | |
2744 | .get_msglevel = sky2_get_msglevel, | |
2745 | .set_msglevel = sky2_set_msglevel, | |
9a7ae0a9 | 2746 | .nway_reset = sky2_nway_reset, |
793b883e SH |
2747 | .get_regs_len = sky2_get_regs_len, |
2748 | .get_regs = sky2_get_regs, | |
2749 | .get_link = ethtool_op_get_link, | |
2750 | .get_sg = ethtool_op_get_sg, | |
2751 | .set_sg = ethtool_op_set_sg, | |
2752 | .get_tx_csum = ethtool_op_get_tx_csum, | |
2753 | .set_tx_csum = ethtool_op_set_tx_csum, | |
2754 | .get_tso = ethtool_op_get_tso, | |
2755 | .set_tso = ethtool_op_set_tso, | |
2756 | .get_rx_csum = sky2_get_rx_csum, | |
2757 | .set_rx_csum = sky2_set_rx_csum, | |
2758 | .get_strings = sky2_get_strings, | |
2759 | .get_ringparam = sky2_get_ringparam, | |
2760 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
2761 | .get_pauseparam = sky2_get_pauseparam, |
2762 | .set_pauseparam = sky2_set_pauseparam, | |
2763 | #ifdef CONFIG_PM | |
793b883e SH |
2764 | .get_wol = sky2_get_wol, |
2765 | .set_wol = sky2_set_wol, | |
cd28ab6a | 2766 | #endif |
793b883e | 2767 | .phys_id = sky2_phys_id, |
cd28ab6a SH |
2768 | .get_stats_count = sky2_get_stats_count, |
2769 | .get_ethtool_stats = sky2_get_ethtool_stats, | |
2995bfb7 | 2770 | .get_perm_addr = ethtool_op_get_perm_addr, |
cd28ab6a SH |
2771 | }; |
2772 | ||
2773 | /* Initialize network device */ | |
2774 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
2775 | unsigned port, int highmem) | |
2776 | { | |
2777 | struct sky2_port *sky2; | |
2778 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
2779 | ||
2780 | if (!dev) { | |
2781 | printk(KERN_ERR "sky2 etherdev alloc failed"); | |
2782 | return NULL; | |
2783 | } | |
2784 | ||
2785 | SET_MODULE_OWNER(dev); | |
2786 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
ef743d33 | 2787 | dev->irq = hw->pdev->irq; |
cd28ab6a SH |
2788 | dev->open = sky2_up; |
2789 | dev->stop = sky2_down; | |
ef743d33 | 2790 | dev->do_ioctl = sky2_ioctl; |
cd28ab6a SH |
2791 | dev->hard_start_xmit = sky2_xmit_frame; |
2792 | dev->get_stats = sky2_get_stats; | |
2793 | dev->set_multicast_list = sky2_set_multicast; | |
2794 | dev->set_mac_address = sky2_set_mac_address; | |
2795 | dev->change_mtu = sky2_change_mtu; | |
2796 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
2797 | dev->tx_timeout = sky2_tx_timeout; | |
2798 | dev->watchdog_timeo = TX_WATCHDOG; | |
2799 | if (port == 0) | |
2800 | dev->poll = sky2_poll; | |
2801 | dev->weight = NAPI_WEIGHT; | |
2802 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2803 | dev->poll_controller = sky2_netpoll; | |
2804 | #endif | |
cd28ab6a SH |
2805 | |
2806 | sky2 = netdev_priv(dev); | |
2807 | sky2->netdev = dev; | |
2808 | sky2->hw = hw; | |
2809 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
2810 | ||
2811 | spin_lock_init(&sky2->tx_lock); | |
2812 | /* Auto speed and flow control */ | |
2813 | sky2->autoneg = AUTONEG_ENABLE; | |
2814 | sky2->tx_pause = 0; | |
2815 | sky2->rx_pause = 1; | |
2816 | sky2->duplex = -1; | |
2817 | sky2->speed = -1; | |
2818 | sky2->advertising = sky2_supported_modes(hw); | |
2819 | sky2->rx_csum = 1; | |
793b883e SH |
2820 | tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2); |
2821 | sky2->tx_pending = TX_DEF_PENDING; | |
2822 | sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING; | |
cd28ab6a SH |
2823 | |
2824 | hw->dev[port] = dev; | |
2825 | ||
2826 | sky2->port = port; | |
2827 | ||
5a5b1ea0 SH |
2828 | dev->features |= NETIF_F_LLTX; |
2829 | if (hw->chip_id != CHIP_ID_YUKON_EC_U) | |
2830 | dev->features |= NETIF_F_TSO; | |
cd28ab6a SH |
2831 | if (highmem) |
2832 | dev->features |= NETIF_F_HIGHDMA; | |
793b883e | 2833 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a | 2834 | |
d1f13708 SH |
2835 | #ifdef SKY2_VLAN_TAG_USED |
2836 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
2837 | dev->vlan_rx_register = sky2_vlan_rx_register; | |
2838 | dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid; | |
2839 | #endif | |
2840 | ||
cd28ab6a | 2841 | /* read the mac address */ |
793b883e | 2842 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 2843 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a SH |
2844 | |
2845 | /* device is off until link detection */ | |
2846 | netif_carrier_off(dev); | |
2847 | netif_stop_queue(dev); | |
2848 | ||
2849 | return dev; | |
2850 | } | |
2851 | ||
2852 | static inline void sky2_show_addr(struct net_device *dev) | |
2853 | { | |
2854 | const struct sky2_port *sky2 = netdev_priv(dev); | |
2855 | ||
2856 | if (netif_msg_probe(sky2)) | |
2857 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
2858 | dev->name, | |
2859 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
2860 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
2861 | } | |
2862 | ||
2863 | static int __devinit sky2_probe(struct pci_dev *pdev, | |
2864 | const struct pci_device_id *ent) | |
2865 | { | |
793b883e | 2866 | struct net_device *dev, *dev1 = NULL; |
cd28ab6a | 2867 | struct sky2_hw *hw; |
5afa0a9c | 2868 | int err, pm_cap, using_dac = 0; |
cd28ab6a | 2869 | |
793b883e SH |
2870 | err = pci_enable_device(pdev); |
2871 | if (err) { | |
cd28ab6a SH |
2872 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
2873 | pci_name(pdev)); | |
2874 | goto err_out; | |
2875 | } | |
2876 | ||
793b883e SH |
2877 | err = pci_request_regions(pdev, DRV_NAME); |
2878 | if (err) { | |
cd28ab6a SH |
2879 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
2880 | pci_name(pdev)); | |
793b883e | 2881 | goto err_out; |
cd28ab6a SH |
2882 | } |
2883 | ||
2884 | pci_set_master(pdev); | |
2885 | ||
5afa0a9c SH |
2886 | /* Find power-management capability. */ |
2887 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
2888 | if (pm_cap == 0) { | |
2889 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
2890 | "aborting.\n"); | |
2891 | err = -EIO; | |
2892 | goto err_out_free_regions; | |
2893 | } | |
2894 | ||
cd28ab6a SH |
2895 | if (sizeof(dma_addr_t) > sizeof(u32)) { |
2896 | err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
2897 | if (!err) | |
2898 | using_dac = 1; | |
2899 | } | |
2900 | ||
2901 | if (!using_dac) { | |
2902 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2903 | if (err) { | |
2904 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
2905 | pci_name(pdev)); | |
2906 | goto err_out_free_regions; | |
2907 | } | |
2908 | } | |
cd28ab6a | 2909 | #ifdef __BIG_ENDIAN |
d571b694 | 2910 | /* byte swap descriptors in hardware */ |
cd28ab6a SH |
2911 | { |
2912 | u32 reg; | |
2913 | ||
2914 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
2915 | reg |= PCI_REV_DESC; | |
2916 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
2917 | } | |
2918 | #endif | |
2919 | ||
2920 | err = -ENOMEM; | |
2921 | hw = kmalloc(sizeof(*hw), GFP_KERNEL); | |
2922 | if (!hw) { | |
2923 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
2924 | pci_name(pdev)); | |
2925 | goto err_out_free_regions; | |
2926 | } | |
2927 | ||
2928 | memset(hw, 0, sizeof(*hw)); | |
2929 | hw->pdev = pdev; | |
2930 | spin_lock_init(&hw->phy_lock); | |
2931 | ||
2932 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
2933 | if (!hw->regs) { | |
2934 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
2935 | pci_name(pdev)); | |
2936 | goto err_out_free_hw; | |
2937 | } | |
5afa0a9c | 2938 | hw->pm_cap = pm_cap; |
cd28ab6a | 2939 | |
cd28ab6a SH |
2940 | err = sky2_reset(hw); |
2941 | if (err) | |
793b883e | 2942 | goto err_out_iounmap; |
cd28ab6a | 2943 | |
793b883e | 2944 | printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n", |
cd28ab6a | 2945 | pci_resource_start(pdev, 0), pdev->irq, |
793b883e SH |
2946 | yukon_name[hw->chip_id - CHIP_ID_YUKON], |
2947 | hw->chip_id, hw->chip_rev); | |
cd28ab6a | 2948 | |
793b883e SH |
2949 | dev = sky2_init_netdev(hw, 0, using_dac); |
2950 | if (!dev) | |
cd28ab6a SH |
2951 | goto err_out_free_pci; |
2952 | ||
793b883e SH |
2953 | err = register_netdev(dev); |
2954 | if (err) { | |
cd28ab6a SH |
2955 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
2956 | pci_name(pdev)); | |
2957 | goto err_out_free_netdev; | |
2958 | } | |
2959 | ||
2960 | sky2_show_addr(dev); | |
2961 | ||
2962 | if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { | |
2963 | if (register_netdev(dev1) == 0) | |
2964 | sky2_show_addr(dev1); | |
2965 | else { | |
2966 | /* Failure to register second port need not be fatal */ | |
793b883e SH |
2967 | printk(KERN_WARNING PFX |
2968 | "register of second port failed\n"); | |
cd28ab6a SH |
2969 | hw->dev[1] = NULL; |
2970 | free_netdev(dev1); | |
2971 | } | |
2972 | } | |
2973 | ||
793b883e SH |
2974 | err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw); |
2975 | if (err) { | |
2976 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
2977 | pci_name(pdev), pdev->irq); | |
2978 | goto err_out_unregister; | |
2979 | } | |
2980 | ||
2981 | hw->intr_mask = Y2_IS_BASE; | |
2982 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
2983 | ||
2984 | pci_set_drvdata(pdev, hw); | |
2985 | ||
cd28ab6a SH |
2986 | return 0; |
2987 | ||
793b883e SH |
2988 | err_out_unregister: |
2989 | if (dev1) { | |
2990 | unregister_netdev(dev1); | |
2991 | free_netdev(dev1); | |
2992 | } | |
2993 | unregister_netdev(dev); | |
cd28ab6a SH |
2994 | err_out_free_netdev: |
2995 | free_netdev(dev); | |
cd28ab6a | 2996 | err_out_free_pci: |
793b883e | 2997 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
2998 | pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
2999 | err_out_iounmap: | |
3000 | iounmap(hw->regs); | |
3001 | err_out_free_hw: | |
3002 | kfree(hw); | |
3003 | err_out_free_regions: | |
3004 | pci_release_regions(pdev); | |
cd28ab6a | 3005 | pci_disable_device(pdev); |
cd28ab6a SH |
3006 | err_out: |
3007 | return err; | |
3008 | } | |
3009 | ||
3010 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
3011 | { | |
793b883e | 3012 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3013 | struct net_device *dev0, *dev1; |
3014 | ||
793b883e | 3015 | if (!hw) |
cd28ab6a SH |
3016 | return; |
3017 | ||
cd28ab6a | 3018 | dev0 = hw->dev[0]; |
793b883e SH |
3019 | dev1 = hw->dev[1]; |
3020 | if (dev1) | |
3021 | unregister_netdev(dev1); | |
cd28ab6a SH |
3022 | unregister_netdev(dev0); |
3023 | ||
793b883e | 3024 | sky2_write32(hw, B0_IMSK, 0); |
5afa0a9c | 3025 | sky2_set_power_state(hw, PCI_D3hot); |
cd28ab6a | 3026 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 3027 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 3028 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
3029 | |
3030 | free_irq(pdev->irq, hw); | |
793b883e | 3031 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
3032 | pci_release_regions(pdev); |
3033 | pci_disable_device(pdev); | |
793b883e | 3034 | |
cd28ab6a SH |
3035 | if (dev1) |
3036 | free_netdev(dev1); | |
3037 | free_netdev(dev0); | |
3038 | iounmap(hw->regs); | |
3039 | kfree(hw); | |
5afa0a9c | 3040 | |
cd28ab6a SH |
3041 | pci_set_drvdata(pdev, NULL); |
3042 | } | |
3043 | ||
3044 | #ifdef CONFIG_PM | |
3045 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
3046 | { | |
793b883e | 3047 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
5afa0a9c | 3048 | int i; |
cd28ab6a SH |
3049 | |
3050 | for (i = 0; i < 2; i++) { | |
3051 | struct net_device *dev = hw->dev[i]; | |
3052 | ||
3053 | if (dev) { | |
5afa0a9c SH |
3054 | if (!netif_running(dev)) |
3055 | continue; | |
3056 | ||
3057 | sky2_down(dev); | |
cd28ab6a | 3058 | netif_device_detach(dev); |
cd28ab6a SH |
3059 | } |
3060 | } | |
3061 | ||
5afa0a9c | 3062 | return sky2_set_power_state(hw, pci_choose_state(pdev, state)); |
cd28ab6a SH |
3063 | } |
3064 | ||
3065 | static int sky2_resume(struct pci_dev *pdev) | |
3066 | { | |
793b883e | 3067 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3068 | int i; |
3069 | ||
cd28ab6a SH |
3070 | pci_restore_state(pdev); |
3071 | pci_enable_wake(pdev, PCI_D0, 0); | |
5afa0a9c | 3072 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
3073 | |
3074 | sky2_reset(hw); | |
3075 | ||
3076 | for (i = 0; i < 2; i++) { | |
3077 | struct net_device *dev = hw->dev[i]; | |
3078 | if (dev) { | |
5afa0a9c SH |
3079 | if (netif_running(dev)) { |
3080 | netif_device_attach(dev); | |
cd28ab6a | 3081 | sky2_up(dev); |
5afa0a9c | 3082 | } |
cd28ab6a SH |
3083 | } |
3084 | } | |
3085 | return 0; | |
3086 | } | |
3087 | #endif | |
3088 | ||
3089 | static struct pci_driver sky2_driver = { | |
793b883e SH |
3090 | .name = DRV_NAME, |
3091 | .id_table = sky2_id_table, | |
3092 | .probe = sky2_probe, | |
3093 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 3094 | #ifdef CONFIG_PM |
793b883e SH |
3095 | .suspend = sky2_suspend, |
3096 | .resume = sky2_resume, | |
cd28ab6a SH |
3097 | #endif |
3098 | }; | |
3099 | ||
3100 | static int __init sky2_init_module(void) | |
3101 | { | |
cd28ab6a SH |
3102 | return pci_module_init(&sky2_driver); |
3103 | } | |
3104 | ||
3105 | static void __exit sky2_cleanup_module(void) | |
3106 | { | |
3107 | pci_unregister_driver(&sky2_driver); | |
3108 | } | |
3109 | ||
3110 | module_init(sky2_init_module); | |
3111 | module_exit(sky2_cleanup_module); | |
3112 | ||
3113 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
3114 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
3115 | MODULE_LICENSE("GPL"); |