]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/sky2.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'upstream' of master.kernel.org:/pub/scm/linux/kernel/git/linville/wirel...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
e981d47b 53#define DRV_VERSION "1.7"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
13210ce5 63#define RX_LE_SIZE 512
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
22e11703 68#define RX_BUF_WRITE 16
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
cd28ab6a
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33
SH		 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
2ccc99b7 195static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c
SH		 196{
197 u16 power_control;
5afa0a9c 198 int vaux;
5afa0a9c
SH		 199
200 pr_debug("sky2_set_power_state %d\n", state);
201 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
202
56a645cc 203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 204 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 205 (power_control & PCI_PM_CAP_PME_D3cold);
206
56a645cc 207 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 208
209 power_control |= PCI_PM_CTRL_PME_STATUS;
210 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
211
212 switch (state) {
213 case PCI_D0:
214 /* switch power to VCC (WA for VAUX problem) */
215 sky2_write8(hw, B0_POWER_CTRL,
216 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
217
218 /* disable Core Clock Division, */
219 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
220
221 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
222 /* enable bits are inverted */
223 sky2_write8(hw, B2_Y2_CLK_GATE,
224 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
225 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
226 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
227 else
228 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
229
977bdf06 230 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb
SH		 231 u32 reg1;
232
56a645cc
SH		 233 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
234 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 235 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 236 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
237 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 238 }
239
5afa0a9c
SH		 240 break;
241
242 case PCI_D3hot:
243 case PCI_D3cold:
5afa0a9c
SH		 244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
246 else
247 /* enable bits are inverted */
248 sky2_write8(hw, B2_Y2_CLK_GATE,
249 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
250 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
251 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
252
253 /* switch power to VAUX */
254 if (vaux && state != PCI_D3cold)
255 sky2_write8(hw, B0_POWER_CTRL,
256 (PC_VAUX_ENA | PC_VCC_ENA |
257 PC_VAUX_ON | PC_VCC_OFF));
258 break;
259 default:
260 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c
SH		 261 }
262
56a645cc 263 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 264 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c
SH		 265}
266
d3bcfbeb 267static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 268{
269 u16 reg;
270
271 /* disable all GMAC IRQ's */
272 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
273 /* disable PHY IRQs */
274 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 275
cd28ab6a
SH		 276 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
277 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
278 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
280
281 reg = gma_read16(hw, port, GM_RX_CTRL);
282 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
283 gma_write16(hw, port, GM_RX_CTRL, reg);
284}
285
286static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
287{
288 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 289 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 290
ed6d32c7 291 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 292 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 293 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
294
295 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 296 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 297 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
298
299 if (hw->chip_id == CHIP_ID_YUKON_EC)
300 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
301 else
302 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
303
304 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
305 }
306
307 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
308 if (hw->copper) {
309 if (hw->chip_id == CHIP_ID_YUKON_FE) {
310 /* enable automatic crossover */
311 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
312 } else {
313 /* disable energy detect */
314 ctrl &= ~PHY_M_PC_EN_DET_MSK;
315
316 /* enable automatic crossover */
317 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
318
319 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 320 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 321 ctrl &= ~PHY_M_PC_DSC_MSK;
322 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
323 }
324 }
325 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
326 } else {
327 /* workaround for deviation #4.88 (CRC errors) */
328 /* disable Automatic Crossover */
329
330 ctrl &= ~PHY_M_PC_MDIX_MSK;
331 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
332
333 if (hw->chip_id == CHIP_ID_YUKON_XL) {
334 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
335 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
336 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
337 ctrl &= ~PHY_M_MAC_MD_MSK;
338 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
339 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
340
341 /* select page 1 to access Fiber registers */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
343 }
cd28ab6a
SH		 344 }
345
346 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
347 if (sky2->autoneg == AUTONEG_DISABLE)
348 ctrl &= ~PHY_CT_ANE;
349 else
350 ctrl |= PHY_CT_ANE;
351
352 ctrl |= PHY_CT_RESET;
353 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
354
355 ctrl = 0;
356 ct1000 = 0;
357 adv = PHY_AN_CSMA;
358
359 if (sky2->autoneg == AUTONEG_ENABLE) {
360 if (hw->copper) {
361 if (sky2->advertising & ADVERTISED_1000baseT_Full)
362 ct1000 |= PHY_M_1000C_AFD;
363 if (sky2->advertising & ADVERTISED_1000baseT_Half)
364 ct1000 |= PHY_M_1000C_AHD;
365 if (sky2->advertising & ADVERTISED_100baseT_Full)
366 adv |= PHY_M_AN_100_FD;
367 if (sky2->advertising & ADVERTISED_100baseT_Half)
368 adv |= PHY_M_AN_100_HD;
369 if (sky2->advertising & ADVERTISED_10baseT_Full)
370 adv |= PHY_M_AN_10_FD;
371 if (sky2->advertising & ADVERTISED_10baseT_Half)
372 adv |= PHY_M_AN_10_HD;
793b883e 373 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 374 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
375
376 /* Set Flow-control capabilities */
377 if (sky2->tx_pause && sky2->rx_pause)
793b883e 378 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 379 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 380 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 381 else if (!sky2->rx_pause && sky2->tx_pause)
382 adv |= PHY_AN_PAUSE_ASYM; /* local */
383
384 /* Restart Auto-negotiation */
385 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
386 } else {
387 /* forced speed/duplex settings */
388 ct1000 = PHY_M_1000C_MSE;
389
390 if (sky2->duplex == DUPLEX_FULL)
391 ctrl |= PHY_CT_DUP_MD;
392
393 switch (sky2->speed) {
394 case SPEED_1000:
395 ctrl |= PHY_CT_SP1000;
396 break;
397 case SPEED_100:
398 ctrl |= PHY_CT_SP100;
399 break;
400 }
401
402 ctrl |= PHY_CT_RESET;
403 }
404
405 if (hw->chip_id != CHIP_ID_YUKON_FE)
406 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
407
408 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
409 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
410
411 /* Setup Phy LED's */
412 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
413 ledover = 0;
414
415 switch (hw->chip_id) {
416 case CHIP_ID_YUKON_FE:
417 /* on 88E3082 these bits are at 11..9 (shifted left) */
418 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
419
420 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
421
422 /* delete ACT LED control bits */
423 ctrl &= ~PHY_M_FELP_LED1_MSK;
424 /* change ACT LED control to blink mode */
425 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
426 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
427 break;
428
429 case CHIP_ID_YUKON_XL:
793b883e 430 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 431
432 /* select page 3 to access LED control register */
433 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
434
435 /* set LED Function Control register */
ed6d32c7
SH		 436 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
437 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
438 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
439 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
440 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 441
442 /* set Polarity Control register */
443 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 444 (PHY_M_POLC_LS1_P_MIX(4) |
445 PHY_M_POLC_IS0_P_MIX(4) |
446 PHY_M_POLC_LOS_CTRL(2) |
447 PHY_M_POLC_INIT_CTRL(2) |
448 PHY_M_POLC_STA1_CTRL(2) |
449 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 450
451 /* restore page register */
793b883e 452 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 453 break;
ed6d32c7
SH		 454 case CHIP_ID_YUKON_EC_U:
455 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
456
457 /* select page 3 to access LED control register */
458 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
459
460 /* set LED Function Control register */
461 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
462 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
463 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
464 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
465 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
466
467 /* set Blink Rate in LED Timer Control Register */
468 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
469 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
470 /* restore page register */
471 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
472 break;
cd28ab6a
SH		 473
474 default:
475 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
476 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
477 /* turn off the Rx LED (LED_RX) */
478 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
479 }
480
ed6d32c7 481 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 482 /* apply fixes in PHY AFE */
ed6d32c7
SH		 483 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
484 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
485
977bdf06 486 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 487 gm_phy_write(hw, port, 0x18, 0xaa99);
488 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 489
977bdf06 490 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 491 gm_phy_write(hw, port, 0x18, 0xa204);
492 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 493
494 /* set page register to 0 */
ed6d32c7 495 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 496 } else {
497 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 498
977bdf06
SH		 499 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
500 /* turn on 100 Mbps LED (LED_LINK100) */
501 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
502 }
cd28ab6a 503
977bdf06
SH		 504 if (ledover)
505 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
506
507 }
d571b694 508 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 509 if (sky2->autoneg == AUTONEG_ENABLE)
510 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
511 else
512 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
513}
514
d3bcfbeb
SH		 515static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
516{
517 u32 reg1;
518 static const u32 phy_power[]
519 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
520
521 /* looks like this XL is back asswards .. */
522 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
523 onoff = !onoff;
524
525 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
526
527 if (onoff)
528 /* Turn off phy power saving */
529 reg1 &= ~phy_power[port];
530 else
531 reg1 |= phy_power[port];
532
533 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 534 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 535 udelay(100);
536}
537
1b537565
SH		 538/* Force a renegotiation */
539static void sky2_phy_reinit(struct sky2_port *sky2)
540{
e07b1aa8 541 spin_lock_bh(&sky2->phy_lock);
1b537565 542 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 543 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 544}
545
cd28ab6a
SH		 546static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
547{
548 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
549 u16 reg;
550 int i;
551 const u8 *addr = hw->dev[port]->dev_addr;
552
42eeea01
SH		 553 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
554 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 555
556 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
557
793b883e 558 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 559 /* WA DEV_472 -- looks like crossed wires on port 2 */
560 /* clear GMAC 1 Control reset */
561 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
562 do {
563 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
564 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
565 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
566 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
567 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
568 }
569
cd28ab6a
SH		 570 if (sky2->autoneg == AUTONEG_DISABLE) {
571 reg = gma_read16(hw, port, GM_GP_CTRL);
572 reg |= GM_GPCR_AU_ALL_DIS;
573 gma_write16(hw, port, GM_GP_CTRL, reg);
574 gma_read16(hw, port, GM_GP_CTRL);
575
cd28ab6a
SH		 576 switch (sky2->speed) {
577 case SPEED_1000:
6f4c56b2 578 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 579 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 580 break;
cd28ab6a 581 case SPEED_100:
6f4c56b2 582 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 583 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 584 break;
585 case SPEED_10:
586 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
587 break;
cd28ab6a
SH		 588 }
589
590 if (sky2->duplex == DUPLEX_FULL)
591 reg |= GM_GPCR_DUP_FULL;
ed6d32c7
SH		 592
593 /* turn off pause in 10/100mbps half duplex */
594 else if (sky2->speed != SPEED_1000 &&
595 hw->chip_id != CHIP_ID_YUKON_EC_U)
596 sky2->tx_pause = sky2->rx_pause = 0;
cd28ab6a
SH		 597 } else
598 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
599
600 if (!sky2->tx_pause && !sky2->rx_pause) {
601 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 602 reg |=
603 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
604 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 605 /* disable Rx flow-control */
606 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
607 }
608
609 gma_write16(hw, port, GM_GP_CTRL, reg);
610
793b883e 611 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 612
e07b1aa8 613 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 614 sky2_phy_init(hw, port);
e07b1aa8 615 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 616
617 /* MIB clear */
618 reg = gma_read16(hw, port, GM_PHY_ADDR);
619 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
620
43f2f104
SH		 621 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
622 gma_read16(hw, port, i);
cd28ab6a
SH		 623 gma_write16(hw, port, GM_PHY_ADDR, reg);
624
625 /* transmit control */
626 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
627
628 /* receive control reg: unicast + multicast + no FCS */
629 gma_write16(hw, port, GM_RX_CTRL,
793b883e 630 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 631
632 /* transmit flow control */
633 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
634
635 /* transmit parameter */
636 gma_write16(hw, port, GM_TX_PARAM,
637 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
638 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
639 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
640 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
641
642 /* serial mode register */
643 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 644 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 645
6b1a3aef 646 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 647 reg |= GM_SMOD_JUMBO_ENA;
648
649 gma_write16(hw, port, GM_SERIAL_MODE, reg);
650
cd28ab6a
SH		 651 /* virtual address for data */
652 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
653
793b883e
SH		 654 /* physical address: used for pause frames */
655 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
656
657 /* ignore counter overflows */
cd28ab6a
SH		 658 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
659 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
660 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
661
662 /* Configure Rx MAC FIFO */
663 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 664 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
665 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 666
d571b694 667 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 668 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 669
793b883e
SH		 670 /* Set threshold to 0xa (64 bytes)
671 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 672 */
673 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
674
675 /* Configure Tx MAC FIFO */
676 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
677 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 678
679 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
680 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
681 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
682 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
683 /* set Tx GMAC FIFO Almost Empty Threshold */
684 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
685 /* Disable Store & Forward mode for TX */
686 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
687 }
688 }
689
cd28ab6a
SH		 690}
691
1c28f6ba
SH		 692/* Assign Ram Buffer allocation.
693 * start and end are in units of 4k bytes
694 * ram registers are in units of 64bit words
695 */
696static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 697{
1c28f6ba 698 u32 start, end;
cd28ab6a 699
1c28f6ba
SH		 700 start = startk * 4096/8;
701 end = (endk * 4096/8) - 1;
793b883e 702
cd28ab6a
SH		 703 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
704 sky2_write32(hw, RB_ADDR(q, RB_START), start);
705 sky2_write32(hw, RB_ADDR(q, RB_END), end);
706 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
707 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
708
709 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 710 u32 space = (endk - startk) * 4096/8;
711 u32 tp = space - space/4;
793b883e 712
1c28f6ba
SH		 713 /* On receive queue's set the thresholds
714 * give receiver priority when > 3/4 full
715 * send pause when down to 2K
716 */
717 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
718 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 719
1c28f6ba
SH		 720 tp = space - 2048/8;
721 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
722 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 723 } else {
724 /* Enable store & forward on Tx queue's because
725 * Tx FIFO is only 1K on Yukon
726 */
727 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
728 }
729
730 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 731 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 732}
733
cd28ab6a 734/* Setup Bus Memory Interface */
af4ed7e6 735static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 736{
737 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
738 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
739 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 740 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 741}
742
cd28ab6a
SH		 743/* Setup prefetch unit registers. This is the interface between
744 * hardware and driver list elements
745 */
8cc048e3 746static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 747 u64 addr, u32 last)
748{
cd28ab6a
SH		 749 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
750 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
751 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
752 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
753 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
754 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 755
756 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 757}
758
793b883e
SH		 759static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
760{
761 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
762
cb5d9547 763 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 764 return le;
765}
cd28ab6a 766
290d4de5
SH		 767/* Update chip's next pointer */
768static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 769{
98232f85 770 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 771 wmb();
98232f85
SH		 772 sky2_write16(hw, q, idx);
773 sky2_read16(hw, q);
cd28ab6a
SH		 774}
775
793b883e 776
cd28ab6a
SH		 777static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
778{
779 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 780 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 781 return le;
782}
783
a018e330
SH		 784/* Return high part of DMA address (could be 32 or 64 bit) */
785static inline u32 high32(dma_addr_t a)
786{
a036119f 787 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 788}
789
793b883e 790/* Build description to hardware about buffer */
28bd181a 791static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 792{
793 struct sky2_rx_le *le;
734d1868
SH		 794 u32 hi = high32(map);
795 u16 len = sky2->rx_bufsize;
cd28ab6a 796
793b883e 797 if (sky2->rx_addr64 != hi) {
cd28ab6a 798 le = sky2_next_rx(sky2);
793b883e 799 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 800 le->ctrl = 0;
801 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 802 sky2->rx_addr64 = high32(map + len);
cd28ab6a 803 }
793b883e 804
cd28ab6a 805 le = sky2_next_rx(sky2);
734d1868
SH		 806 le->addr = cpu_to_le32((u32) map);
807 le->length = cpu_to_le16(len);
cd28ab6a
SH		 808 le->ctrl = 0;
809 le->opcode = OP_PACKET | HW_OWNER;
810}
811
793b883e 812
cd28ab6a
SH		 813/* Tell chip where to start receive checksum.
814 * Actually has two checksums, but set both same to avoid possible byte
815 * order problems.
816 */
793b883e 817static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 818{
819 struct sky2_rx_le *le;
820
cd28ab6a 821 le = sky2_next_rx(sky2);
793b883e 822 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 823 le->ctrl = 0;
824 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 825
793b883e
SH		 826 sky2_write32(sky2->hw,
827 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
828 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 829
830}
831
6b1a3aef
SH		 832/*
833 * The RX Stop command will not work for Yukon-2 if the BMU does not
834 * reach the end of packet and since we can't make sure that we have
835 * incoming data, we must reset the BMU while it is not doing a DMA
836 * transfer. Since it is possible that the RX path is still active,
837 * the RX RAM buffer will be stopped first, so any possible incoming
838 * data will not trigger a DMA. After the RAM buffer is stopped, the
839 * BMU is polled until any DMA in progress is ended and only then it
840 * will be reset.
841 */
842static void sky2_rx_stop(struct sky2_port *sky2)
843{
844 struct sky2_hw *hw = sky2->hw;
845 unsigned rxq = rxqaddr[sky2->port];
846 int i;
847
848 /* disable the RAM Buffer receive queue */
849 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
850
851 for (i = 0; i < 0xffff; i++)
852 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
853 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
854 goto stopped;
855
856 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
857 sky2->netdev->name);
858stopped:
859 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
860
861 /* reset the Rx prefetch unit */
862 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
863}
793b883e 864
d571b694 865/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 866static void sky2_rx_clean(struct sky2_port *sky2)
867{
868 unsigned i;
869
870 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 871 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 872 struct ring_info *re = sky2->rx_ring + i;
873
874 if (re->skb) {
793b883e 875 pci_unmap_single(sky2->hw->pdev,
734d1868 876 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 877 PCI_DMA_FROMDEVICE);
878 kfree_skb(re->skb);
879 re->skb = NULL;
880 }
881 }
882}
883
ef743d33
SH		 884/* Basic MII support */
885static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
886{
887 struct mii_ioctl_data *data = if_mii(ifr);
888 struct sky2_port *sky2 = netdev_priv(dev);
889 struct sky2_hw *hw = sky2->hw;
890 int err = -EOPNOTSUPP;
891
892 if (!netif_running(dev))
893 return -ENODEV; /* Phy still in reset */
894
d89e1343 895 switch (cmd) {
ef743d33
SH		 896 case SIOCGMIIPHY:
897 data->phy_id = PHY_ADDR_MARV;
898
899 /* fallthru */
900 case SIOCGMIIREG: {
901 u16 val = 0;
91c86df5 902
e07b1aa8 903 spin_lock_bh(&sky2->phy_lock);
ef743d33 904 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 905 spin_unlock_bh(&sky2->phy_lock);
91c86df5 906
ef743d33
SH		 907 data->val_out = val;
908 break;
909 }
910
911 case SIOCSMIIREG:
912 if (!capable(CAP_NET_ADMIN))
913 return -EPERM;
914
e07b1aa8 915 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 916 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
917 data->val_in);
e07b1aa8 918 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 919 break;
920 }
921 return err;
922}
923
d1f13708
SH		 924#ifdef SKY2_VLAN_TAG_USED
925static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
926{
927 struct sky2_port *sky2 = netdev_priv(dev);
928 struct sky2_hw *hw = sky2->hw;
929 u16 port = sky2->port;
d1f13708 930
302d1252 931 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 932
933 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
934 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
935 sky2->vlgrp = grp;
936
302d1252 937 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 938}
939
940static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
941{
942 struct sky2_port *sky2 = netdev_priv(dev);
943 struct sky2_hw *hw = sky2->hw;
944 u16 port = sky2->port;
d1f13708 945
302d1252 946 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 947
948 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
949 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
950 if (sky2->vlgrp)
951 sky2->vlgrp->vlan_devices[vid] = NULL;
952
302d1252 953 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 954}
955#endif
956
82788c7a
SH		 957/*
958 * It appears the hardware has a bug in the FIFO logic that
959 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 960 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
961 * aligned except if slab debugging is enabled.
82788c7a 962 */
497d7c86
SH		 963static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev,
964 unsigned int length,
965 gfp_t gfp_mask)
82788c7a
SH		 966{
967 struct sk_buff *skb;
968
497d7c86 969 skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask);
82788c7a
SH		 970 if (likely(skb)) {
971 unsigned long p = (unsigned long) skb->data;
4a15d56f 972 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 973 }
974
975 return skb;
976}
977
cd28ab6a
SH		 978/*
979 * Allocate and setup receiver buffer pool.
980 * In case of 64 bit dma, there are 2X as many list elements
981 * available as ring entries
982 * and need to reserve one list element so we don't wrap around.
983 */
6b1a3aef 984static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 985{
6b1a3aef 986 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 987 unsigned rxq = rxqaddr[sky2->port];
988 int i;
a1433ac4 989 unsigned thresh;
cd28ab6a 990
6b1a3aef 991 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 992 sky2_qset(hw, rxq);
977bdf06
SH		 993
994 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
995 /* MAC Rx RAM Read is controlled by hardware */
996 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
997 }
998
6b1a3aef
SH		 999 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1000
1001 rx_set_checksum(sky2);
793b883e 1002 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 1003 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 1004
497d7c86
SH		 1005 re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize,
1006 GFP_KERNEL);
cd28ab6a
SH		 1007 if (!re->skb)
1008 goto nomem;
1009
6b1a3aef 1010 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1011 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1012 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1013 }
1014
a1433ac4
SH		 1015
1016 /*
1017 * The receiver hangs if it receives frames larger than the
1018 * packet buffer. As a workaround, truncate oversize frames, but
1019 * the register is limited to 9 bits, so if you do frames > 2052
1020 * you better get the MTU right!
1021 */
1022 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1023 if (thresh > 0x1ff)
1024 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1025 else {
1026 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1027 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1028 }
1029
70f1be48 1030
6b1a3aef
SH		 1031 /* Tell chip about available buffers */
1032 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1033 return 0;
1034nomem:
1035 sky2_rx_clean(sky2);
1036 return -ENOMEM;
1037}
1038
1039/* Bring up network interface. */
1040static int sky2_up(struct net_device *dev)
1041{
1042 struct sky2_port *sky2 = netdev_priv(dev);
1043 struct sky2_hw *hw = sky2->hw;
1044 unsigned port = sky2->port;
e07b1aa8 1045 u32 ramsize, rxspace, imask;
ee7abb04 1046 int cap, err = -ENOMEM;
843a46f4 1047 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1048
ee7abb04
SH		 1049 /*
1050 * On dual port PCI-X card, there is an problem where status
1051 * can be received out of order due to split transactions
843a46f4 1052 */
ee7abb04
SH		 1053 if (otherdev && netif_running(otherdev) &&
1054 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1055 struct sky2_port *osky2 = netdev_priv(otherdev);
1056 u16 cmd;
1057
1058 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1059 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1060 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1061
1062 sky2->rx_csum = 0;
1063 osky2->rx_csum = 0;
1064 }
843a46f4 1065
cd28ab6a
SH		 1066 if (netif_msg_ifup(sky2))
1067 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1068
1069 /* must be power of 2 */
1070 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1071 TX_RING_SIZE *
1072 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1073 &sky2->tx_le_map);
1074 if (!sky2->tx_le)
1075 goto err_out;
1076
6cdbbdf3 1077 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1078 GFP_KERNEL);
1079 if (!sky2->tx_ring)
1080 goto err_out;
1081 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1082
1083 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1084 &sky2->rx_le_map);
1085 if (!sky2->rx_le)
1086 goto err_out;
1087 memset(sky2->rx_le, 0, RX_LE_BYTES);
1088
6cdbbdf3 1089 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1090 GFP_KERNEL);
1091 if (!sky2->rx_ring)
1092 goto err_out;
1093
d3bcfbeb
SH		 1094 sky2_phy_power(hw, port, 1);
1095
cd28ab6a
SH		 1096 sky2_mac_init(hw, port);
1097
1c28f6ba
SH		 1098 /* Determine available ram buffer space (in 4K blocks).
1099 * Note: not sure about the FE setting below yet
1100 */
1101 if (hw->chip_id == CHIP_ID_YUKON_FE)
1102 ramsize = 4;
1103 else
1104 ramsize = sky2_read8(hw, B2_E_0);
1105
1106 /* Give transmitter one third (rounded up) */
1107 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1108
cd28ab6a 1109 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1110 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1111
793b883e
SH		 1112 /* Make sure SyncQ is disabled */
1113 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1114 RB_RST_SET);
1115
af4ed7e6 1116 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1117
977bdf06
SH		 1118 /* Set almost empty threshold */
1119 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1120 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1121
6b1a3aef
SH		 1122 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1123 TX_RING_SIZE - 1);
cd28ab6a 1124
6b1a3aef 1125 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1126 if (err)
1127 goto err_out;
1128
cd28ab6a 1129 /* Enable interrupts from phy/mac for port */
e07b1aa8 1130 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1131 imask |= portirq_msk[port];
e07b1aa8
SH		 1132 sky2_write32(hw, B0_IMSK, imask);
1133
cd28ab6a
SH		 1134 return 0;
1135
1136err_out:
1b537565 1137 if (sky2->rx_le) {
cd28ab6a
SH		 1138 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1139 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1140 sky2->rx_le = NULL;
1141 }
1142 if (sky2->tx_le) {
cd28ab6a
SH		 1143 pci_free_consistent(hw->pdev,
1144 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1145 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1146 sky2->tx_le = NULL;
1147 }
1148 kfree(sky2->tx_ring);
1149 kfree(sky2->rx_ring);
cd28ab6a 1150
1b537565
SH		 1151 sky2->tx_ring = NULL;
1152 sky2->rx_ring = NULL;
cd28ab6a
SH		 1153 return err;
1154}
1155
793b883e
SH		 1156/* Modular subtraction in ring */
1157static inline int tx_dist(unsigned tail, unsigned head)
1158{
cb5d9547 1159 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1160}
cd28ab6a 1161
793b883e
SH		 1162/* Number of list elements available for next tx */
1163static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1164{
793b883e 1165 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1166}
1167
793b883e 1168/* Estimate of number of transmit list elements required */
28bd181a 1169static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1170{
793b883e
SH		 1171 unsigned count;
1172
1173 count = sizeof(dma_addr_t) / sizeof(u32);
1174 count += skb_shinfo(skb)->nr_frags * count;
1175
89114afd 1176 if (skb_is_gso(skb))
793b883e
SH		 1177 ++count;
1178
0e3ff6aa 1179 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1180 ++count;
1181
1182 return count;
cd28ab6a
SH		 1183}
1184
793b883e
SH		 1185/*
1186 * Put one packet in ring for transmit.
1187 * A single packet can generate multiple list elements, and
1188 * the number of ring elements will probably be less than the number
1189 * of list elements used.
f2e46561
SH		 1190 *
1191 * No BH disabling for tx_lock here (like tg3)
793b883e 1192 */
cd28ab6a
SH		 1193static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1194{
1195 struct sky2_port *sky2 = netdev_priv(dev);
1196 struct sky2_hw *hw = sky2->hw;
d1f13708 1197 struct sky2_tx_le *le = NULL;
6cdbbdf3 1198 struct tx_ring_info *re;
cd28ab6a
SH		 1199 unsigned i, len;
1200 dma_addr_t mapping;
1201 u32 addr64;
1202 u16 mss;
1203 u8 ctrl;
1204
302d1252
SH		 1205 /* No BH disabling for tx_lock here. We are running in BH disabled
1206 * context and TX reclaim runs via poll inside of a software
1207 * interrupt, and no related locks in IRQ processing.
1208 */
f2e46561 1209 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1210 return NETDEV_TX_LOCKED;
1211
793b883e 1212 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1213 /* There is a known but harmless race with lockless tx
1214 * and netif_stop_queue.
1215 */
1216 if (!netif_queue_stopped(dev)) {
1217 netif_stop_queue(dev);
3be92a70
SH		 1218 if (net_ratelimit())
1219 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1220 dev->name);
8c463ef7 1221 }
f2e46561 1222 spin_unlock(&sky2->tx_lock);
cd28ab6a 1223
cd28ab6a
SH		 1224 return NETDEV_TX_BUSY;
1225 }
1226
793b883e 1227 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1228 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1229 dev->name, sky2->tx_prod, skb->len);
1230
cd28ab6a
SH		 1231 len = skb_headlen(skb);
1232 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1233 addr64 = high32(mapping);
793b883e
SH		 1234
1235 re = sky2->tx_ring + sky2->tx_prod;
1236
a018e330
SH		 1237 /* Send high bits if changed or crosses boundary */
1238 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1239 le = get_tx_le(sky2);
1240 le->tx.addr = cpu_to_le32(addr64);
1241 le->ctrl = 0;
1242 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1243 sky2->tx_addr64 = high32(mapping + len);
793b883e 1244 }
cd28ab6a
SH		 1245
1246 /* Check for TCP Segmentation Offload */
7967168c 1247 mss = skb_shinfo(skb)->gso_size;
793b883e 1248 if (mss != 0) {
cd28ab6a
SH		 1249 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1250 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1251 mss += ETH_HLEN;
1252
e07560cd
SH		 1253 if (mss != sky2->tx_last_mss) {
1254 le = get_tx_le(sky2);
1255 le->tx.tso.size = cpu_to_le16(mss);
1256 le->tx.tso.rsvd = 0;
1257 le->opcode = OP_LRGLEN | HW_OWNER;
1258 le->ctrl = 0;
1259 sky2->tx_last_mss = mss;
1260 }
cd28ab6a
SH		 1261 }
1262
cd28ab6a 1263 ctrl = 0;
d1f13708
SH		 1264#ifdef SKY2_VLAN_TAG_USED
1265 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1266 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1267 if (!le) {
1268 le = get_tx_le(sky2);
1269 le->tx.addr = 0;
1270 le->opcode = OP_VLAN|HW_OWNER;
1271 le->ctrl = 0;
1272 } else
1273 le->opcode |= OP_VLAN;
1274 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1275 ctrl |= INS_VLAN;
1276 }
1277#endif
1278
1279 /* Handle TCP checksum offload */
cd28ab6a 1280 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1281 u16 hdr = skb->h.raw - skb->data;
1282 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1283
1284 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1285 if (skb->nh.iph->protocol == IPPROTO_UDP)
1286 ctrl |= UDPTCP;
1287
1d179332
SH		 1288 if (hdr != sky2->tx_csum_start || offset != sky2->tx_csum_offset) {
1289 sky2->tx_csum_start = hdr;
1290 sky2->tx_csum_offset = offset;
1291
1292 le = get_tx_le(sky2);
1293 le->tx.csum.start = cpu_to_le16(hdr);
1294 le->tx.csum.offset = cpu_to_le16(offset);
1295 le->length = 0; /* initial checksum value */
1296 le->ctrl = 1; /* one packet */
1297 le->opcode = OP_TCPLISW | HW_OWNER;
1298 }
cd28ab6a
SH		 1299 }
1300
1301 le = get_tx_le(sky2);
1302 le->tx.addr = cpu_to_le32((u32) mapping);
1303 le->length = cpu_to_le16(len);
1304 le->ctrl = ctrl;
793b883e 1305 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1306
793b883e 1307 /* Record the transmit mapping info */
cd28ab6a 1308 re->skb = skb;
6cdbbdf3 1309 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1310
1311 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1312 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1313 struct tx_ring_info *fre;
cd28ab6a
SH		 1314
1315 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1316 frag->size, PCI_DMA_TODEVICE);
a036119f 1317 addr64 = high32(mapping);
793b883e
SH		 1318 if (addr64 != sky2->tx_addr64) {
1319 le = get_tx_le(sky2);
1320 le->tx.addr = cpu_to_le32(addr64);
1321 le->ctrl = 0;
1322 le->opcode = OP_ADDR64 | HW_OWNER;
1323 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1324 }
1325
1326 le = get_tx_le(sky2);
1327 le->tx.addr = cpu_to_le32((u32) mapping);
1328 le->length = cpu_to_le16(frag->size);
1329 le->ctrl = ctrl;
793b883e 1330 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1331
793b883e 1332 fre = sky2->tx_ring
e07560cd 1333 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1334 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1335 }
6cdbbdf3 1336
793b883e 1337 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1338 le->ctrl |= EOP;
1339
97bda706
SH		 1340 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1341 netif_stop_queue(dev);
b19666d9 1342
290d4de5 1343 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1344
f2e46561 1345 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1346
1347 dev->trans_start = jiffies;
1348 return NETDEV_TX_OK;
1349}
1350
cd28ab6a 1351/*
793b883e
SH		 1352 * Free ring elements from starting at tx_cons until "done"
1353 *
1354 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1355 * buffers; these are deferred until completion.
cd28ab6a 1356 */
d11c13e7 1357static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1358{
d11c13e7 1359 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1360 struct pci_dev *pdev = sky2->hw->pdev;
1361 u16 nxt, put;
793b883e 1362 unsigned i;
cd28ab6a 1363
0e3ff6aa 1364 BUG_ON(done >= TX_RING_SIZE);
2224795d 1365
d11c13e7 1366 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1367 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1368 dev->name, done);
cd28ab6a 1369
af2a58ac
SH		 1370 for (put = sky2->tx_cons; put != done; put = nxt) {
1371 struct tx_ring_info *re = sky2->tx_ring + put;
1372 struct sk_buff *skb = re->skb;
cd28ab6a 1373
d89e1343 1374 nxt = re->idx;
af2a58ac 1375 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1376 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1377
793b883e 1378 /* Check for partial status */
af2a58ac
SH		 1379 if (tx_dist(put, done) < tx_dist(put, nxt))
1380 break;
793b883e
SH		 1381
1382 skb = re->skb;
af2a58ac 1383 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1384 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1385
1386 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1387 struct tx_ring_info *fre;
cb5d9547 1388 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1389 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1390 skb_shinfo(skb)->frags[i].size,
734d1868 1391 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1392 }
1393
15240072 1394 dev_kfree_skb(skb);
793b883e 1395 }
793b883e 1396
af2a58ac 1397 sky2->tx_cons = put;
22e11703 1398 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1399 netif_wake_queue(dev);
cd28ab6a
SH		 1400}
1401
1402/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1403static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1404{
302d1252 1405 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1406 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1407 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1408}
1409
1410/* Network shutdown */
1411static int sky2_down(struct net_device *dev)
1412{
1413 struct sky2_port *sky2 = netdev_priv(dev);
1414 struct sky2_hw *hw = sky2->hw;
1415 unsigned port = sky2->port;
1416 u16 ctrl;
e07b1aa8 1417 u32 imask;
cd28ab6a 1418
1b537565
SH		 1419 /* Never really got started! */
1420 if (!sky2->tx_le)
1421 return 0;
1422
cd28ab6a
SH		 1423 if (netif_msg_ifdown(sky2))
1424 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1425
018d1c66 1426 /* Stop more packets from being queued */
cd28ab6a
SH		 1427 netif_stop_queue(dev);
1428
d3bcfbeb 1429 sky2_gmac_reset(hw, port);
793b883e 1430
cd28ab6a
SH		 1431 /* Stop transmitter */
1432 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1433 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1434
1435 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1436 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1437
1438 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1439 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1440 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1441
1442 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1443
1444 /* Workaround shared GMAC reset */
793b883e
SH		 1445 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1446 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1447 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1448
1449 /* Disable Force Sync bit and Enable Alloc bit */
1450 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1451 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1452
1453 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1454 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1455 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1456
1457 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1458 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1459 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1460
1461 /* Reset the Tx prefetch units */
1462 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1463 PREF_UNIT_RST_SET);
1464
1465 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1466
6b1a3aef 1467 sky2_rx_stop(sky2);
cd28ab6a
SH		 1468
1469 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1470 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1471
e07b1aa8
SH		 1472 /* Disable port IRQ */
1473 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1474 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1475 sky2_write32(hw, B0_IMSK, imask);
1476
d3bcfbeb
SH		 1477 sky2_phy_power(hw, port, 0);
1478
d571b694 1479 /* turn off LED's */
cd28ab6a
SH		 1480 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1481
018d1c66
SH		 1482 synchronize_irq(hw->pdev->irq);
1483
cd28ab6a
SH		 1484 sky2_tx_clean(sky2);
1485 sky2_rx_clean(sky2);
1486
1487 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1488 sky2->rx_le, sky2->rx_le_map);
1489 kfree(sky2->rx_ring);
1490
1491 pci_free_consistent(hw->pdev,
1492 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1493 sky2->tx_le, sky2->tx_le_map);
1494 kfree(sky2->tx_ring);
1495
1b537565
SH		 1496 sky2->tx_le = NULL;
1497 sky2->rx_le = NULL;
1498
1499 sky2->rx_ring = NULL;
1500 sky2->tx_ring = NULL;
1501
cd28ab6a
SH		 1502 return 0;
1503}
1504
1505static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1506{
793b883e
SH		 1507 if (!hw->copper)
1508 return SPEED_1000;
1509
cd28ab6a
SH		 1510 if (hw->chip_id == CHIP_ID_YUKON_FE)
1511 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1512
1513 switch (aux & PHY_M_PS_SPEED_MSK) {
1514 case PHY_M_PS_SPEED_1000:
1515 return SPEED_1000;
1516 case PHY_M_PS_SPEED_100:
1517 return SPEED_100;
1518 default:
1519 return SPEED_10;
1520 }
1521}
1522
1523static void sky2_link_up(struct sky2_port *sky2)
1524{
1525 struct sky2_hw *hw = sky2->hw;
1526 unsigned port = sky2->port;
1527 u16 reg;
1528
1529 /* Enable Transmit FIFO Underrun */
793b883e 1530 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1531
1532 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1533 if (sky2->autoneg == AUTONEG_DISABLE) {
1534 reg |= GM_GPCR_AU_ALL_DIS;
1535
1536 /* Is write/read necessary? Copied from sky2_mac_init */
1537 gma_write16(hw, port, GM_GP_CTRL, reg);
1538 gma_read16(hw, port, GM_GP_CTRL);
1539
1540 switch (sky2->speed) {
1541 case SPEED_1000:
1542 reg &= ~GM_GPCR_SPEED_100;
1543 reg |= GM_GPCR_SPEED_1000;
1544 break;
1545 case SPEED_100:
1546 reg &= ~GM_GPCR_SPEED_1000;
1547 reg |= GM_GPCR_SPEED_100;
1548 break;
1549 case SPEED_10:
1550 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1551 break;
1552 }
1553 } else
1554 reg &= ~GM_GPCR_AU_ALL_DIS;
1555
cd28ab6a
SH		 1556 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1557 reg |= GM_GPCR_DUP_FULL;
1558
cd28ab6a
SH		 1559 /* enable Rx/Tx */
1560 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1561 gma_write16(hw, port, GM_GP_CTRL, reg);
1562 gma_read16(hw, port, GM_GP_CTRL);
1563
1564 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1565
1566 netif_carrier_on(sky2->netdev);
1567 netif_wake_queue(sky2->netdev);
1568
1569 /* Turn on link LED */
793b883e 1570 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1571 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1572
ed6d32c7 1573 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1574 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1575 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1576
1577 switch(sky2->speed) {
1578 case SPEED_10:
1579 led |= PHY_M_LEDC_INIT_CTRL(7);
1580 break;
1581
1582 case SPEED_100:
1583 led |= PHY_M_LEDC_STA1_CTRL(7);
1584 break;
1585
1586 case SPEED_1000:
1587 led |= PHY_M_LEDC_STA0_CTRL(7);
1588 break;
1589 }
793b883e
SH		 1590
1591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1592 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1593 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1594 }
1595
cd28ab6a
SH		 1596 if (netif_msg_link(sky2))
1597 printk(KERN_INFO PFX
d571b694 1598 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1599 sky2->netdev->name, sky2->speed,
1600 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1601 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1602 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1603}
1604
1605static void sky2_link_down(struct sky2_port *sky2)
1606{
1607 struct sky2_hw *hw = sky2->hw;
1608 unsigned port = sky2->port;
1609 u16 reg;
1610
1611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1612
1613 reg = gma_read16(hw, port, GM_GP_CTRL);
1614 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1615 gma_write16(hw, port, GM_GP_CTRL, reg);
1616 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1617
1618 if (sky2->rx_pause && !sky2->tx_pause) {
1619 /* restore Asymmetric Pause bit */
1620 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1621 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1622 | PHY_M_AN_ASP);
cd28ab6a
SH		 1623 }
1624
cd28ab6a
SH		 1625 netif_carrier_off(sky2->netdev);
1626 netif_stop_queue(sky2->netdev);
1627
1628 /* Turn on link LED */
1629 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1630
1631 if (netif_msg_link(sky2))
1632 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1633 sky2_phy_init(hw, port);
1634}
1635
793b883e
SH		 1636static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1637{
1638 struct sky2_hw *hw = sky2->hw;
1639 unsigned port = sky2->port;
1640 u16 lpa;
1641
1642 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1643
1644 if (lpa & PHY_M_AN_RF) {
1645 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1646 return -1;
1647 }
1648
1649 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1650 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1651 printk(KERN_ERR PFX "%s: master/slave fault",
1652 sky2->netdev->name);
1653 return -1;
1654 }
1655
1656 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1657 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1658 sky2->netdev->name);
1659 return -1;
1660 }
1661
1662 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1663
1664 sky2->speed = sky2_phy_speed(hw, aux);
1665
1666 /* Pause bits are offset (9..8) */
ed6d32c7 1667 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1668 aux >>= 6;
1669
1670 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1671 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1672
1673 if ((sky2->tx_pause || sky2->rx_pause)
1674 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1676 else
1677 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1678
1679 return 0;
1680}
cd28ab6a 1681
e07b1aa8
SH		 1682/* Interrupt from PHY */
1683static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1684{
e07b1aa8
SH		 1685 struct net_device *dev = hw->dev[port];
1686 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1687 u16 istatus, phystat;
1688
e07b1aa8
SH		 1689 spin_lock(&sky2->phy_lock);
1690 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1691 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1692
1693 if (!netif_running(dev))
1694 goto out;
cd28ab6a
SH		 1695
1696 if (netif_msg_intr(sky2))
1697 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1698 sky2->netdev->name, istatus, phystat);
1699
1700 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1701 if (sky2_autoneg_done(sky2, phystat) == 0)
1702 sky2_link_up(sky2);
1703 goto out;
1704 }
cd28ab6a 1705
793b883e
SH		 1706 if (istatus & PHY_M_IS_LSP_CHANGE)
1707 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1708
793b883e
SH		 1709 if (istatus & PHY_M_IS_DUP_CHANGE)
1710 sky2->duplex =
1711 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1712
793b883e
SH		 1713 if (istatus & PHY_M_IS_LST_CHANGE) {
1714 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1715 sky2_link_up(sky2);
793b883e
SH		 1716 else
1717 sky2_link_down(sky2);
cd28ab6a 1718 }
793b883e 1719out:
e07b1aa8 1720 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1721}
1722
302d1252
SH		 1723
1724/* Transmit timeout is only called if we are running, carries is up
1725 * and tx queue is full (stopped).
1726 */
cd28ab6a
SH		 1727static void sky2_tx_timeout(struct net_device *dev)
1728{
1729 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1730 struct sky2_hw *hw = sky2->hw;
1731 unsigned txq = txqaddr[sky2->port];
8f24664d 1732 u16 report, done;
cd28ab6a
SH		 1733
1734 if (netif_msg_timer(sky2))
1735 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1736
8f24664d
SH		 1737 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1738 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1739
8f24664d
SH		 1740 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1741 dev->name,
1742 sky2->tx_cons, sky2->tx_prod, report, done);
1743
1744 if (report != done) {
1745 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1746
1747 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1748 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1749 } else if (report != sky2->tx_cons) {
1750 printk(KERN_INFO PFX "status report lost?\n");
1751
1752 spin_lock_bh(&sky2->tx_lock);
1753 sky2_tx_complete(sky2, report);
1754 spin_unlock_bh(&sky2->tx_lock);
1755 } else {
1756 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1757
8f24664d
SH		 1758 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1759 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1760
1761 sky2_tx_clean(sky2);
1762
1763 sky2_qset(hw, txq);
1764 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1765 }
cd28ab6a
SH		 1766}
1767
734d1868 1768
70f1be48
SH		 1769/* Want receive buffer size to be multiple of 64 bits
1770 * and incl room for vlan and truncation
1771 */
734d1868
SH		 1772static inline unsigned sky2_buf_size(int mtu)
1773{
4a15d56f 1774 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1775}
1776
cd28ab6a
SH		 1777static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1778{
6b1a3aef
SH		 1779 struct sky2_port *sky2 = netdev_priv(dev);
1780 struct sky2_hw *hw = sky2->hw;
1781 int err;
1782 u16 ctl, mode;
e07b1aa8 1783 u32 imask;
cd28ab6a
SH		 1784
1785 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1786 return -EINVAL;
1787
5a5b1ea0
SH		 1788 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1789 return -EINVAL;
1790
6b1a3aef
SH		 1791 if (!netif_running(dev)) {
1792 dev->mtu = new_mtu;
1793 return 0;
1794 }
1795
e07b1aa8 1796 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1797 sky2_write32(hw, B0_IMSK, 0);
1798
018d1c66
SH		 1799 dev->trans_start = jiffies; /* prevent tx timeout */
1800 netif_stop_queue(dev);
1801 netif_poll_disable(hw->dev[0]);
1802
e07b1aa8
SH		 1803 synchronize_irq(hw->pdev->irq);
1804
6b1a3aef
SH		 1805 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1806 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1807 sky2_rx_stop(sky2);
1808 sky2_rx_clean(sky2);
cd28ab6a
SH		 1809
1810 dev->mtu = new_mtu;
734d1868 1811 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1812 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1813 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1814
1815 if (dev->mtu > ETH_DATA_LEN)
1816 mode |= GM_SMOD_JUMBO_ENA;
1817
1818 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1819
6b1a3aef 1820 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1821
6b1a3aef 1822 err = sky2_rx_start(sky2);
e07b1aa8 1823 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1824
1b537565
SH		 1825 if (err)
1826 dev_close(dev);
1827 else {
1828 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1829
1830 netif_poll_enable(hw->dev[0]);
1831 netif_wake_queue(dev);
1832 }
1833
cd28ab6a
SH		 1834 return err;
1835}
1836
1837/*
1838 * Receive one packet.
1839 * For small packets or errors, just reuse existing skb.
d571b694 1840 * For larger packets, get new buffer.
cd28ab6a 1841 */
497d7c86 1842static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1843 u16 length, u32 status)
1844{
497d7c86 1845 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 1846 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1847 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1848
1849 if (unlikely(netif_msg_rx_status(sky2)))
1850 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1851 dev->name, sky2->rx_next, status, length);
cd28ab6a 1852
793b883e 1853 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1854 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1855
42eeea01 1856 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1857 goto error;
1858
42eeea01
SH		 1859 if (!(status & GMR_FS_RX_OK))
1860 goto resubmit;
1861
497d7c86 1862 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1863 goto oversize;
1864
bdb5c58e 1865 if (length < copybreak) {
497d7c86 1866 skb = netdev_alloc_skb(dev, length + 2);
79e57d32 1867 if (!skb)
793b883e
SH		 1868 goto resubmit;
1869
79e57d32 1870 skb_reserve(skb, 2);
793b883e
SH		 1871 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1872 length, PCI_DMA_FROMDEVICE);
79e57d32 1873 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1874 skb->ip_summed = re->skb->ip_summed;
1875 skb->csum = re->skb->csum;
793b883e
SH		 1876 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1877 length, PCI_DMA_FROMDEVICE);
793b883e 1878 } else {
79e57d32
SH		 1879 struct sk_buff *nskb;
1880
497d7c86 1881 nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1882 if (!nskb)
1883 goto resubmit;
cd28ab6a 1884
793b883e 1885 skb = re->skb;
79e57d32 1886 re->skb = nskb;
793b883e 1887 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1888 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1889 prefetch(skb->data);
cd28ab6a 1890
793b883e 1891 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1892 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1893 }
cd28ab6a 1894
79e57d32 1895 skb_put(skb, length);
793b883e 1896resubmit:
d11c13e7 1897 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1898 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1899
cd28ab6a
SH		 1900 return skb;
1901
6e15b712
SH		 1902oversize:
1903 ++sky2->net_stats.rx_over_errors;
1904 goto resubmit;
1905
cd28ab6a 1906error:
6e15b712
SH		 1907 ++sky2->net_stats.rx_errors;
1908
3be92a70 1909 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 1910 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 1911 dev->name, status, length);
793b883e
SH		 1912
1913 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1914 sky2->net_stats.rx_length_errors++;
1915 if (status & GMR_FS_FRAGMENT)
1916 sky2->net_stats.rx_frame_errors++;
1917 if (status & GMR_FS_CRC_ERR)
1918 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1919 if (status & GMR_FS_RX_FF_OV)
1920 sky2->net_stats.rx_fifo_errors++;
79e57d32 1921
793b883e 1922 goto resubmit;
cd28ab6a
SH		 1923}
1924
e07b1aa8
SH		 1925/* Transmit complete */
1926static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1927{
e07b1aa8 1928 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1929
e07b1aa8
SH		 1930 if (netif_running(dev)) {
1931 spin_lock(&sky2->tx_lock);
1932 sky2_tx_complete(sky2, last);
1933 spin_unlock(&sky2->tx_lock);
2224795d 1934 }
cd28ab6a
SH		 1935}
1936
e07b1aa8
SH		 1937/* Process status response ring */
1938static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1939{
22e11703 1940 struct sky2_port *sky2;
e07b1aa8 1941 int work_done = 0;
22e11703 1942 unsigned buf_write[2] = { 0, 0 };
e71ebd73 1943 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1944
af2a58ac 1945 rmb();
bea86103 1946
e71ebd73 1947 while (hw->st_idx != hwidx) {
13210ce5
SH		 1948 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1949 struct net_device *dev;
cd28ab6a 1950 struct sk_buff *skb;
cd28ab6a
SH		 1951 u32 status;
1952 u16 length;
1953
cb5d9547 1954 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1955
e71ebd73
SH		 1956 BUG_ON(le->link >= 2);
1957 dev = hw->dev[le->link];
13210ce5
SH		 1958
1959 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1960 length = le->length;
1961 status = le->status;
cd28ab6a 1962
e71ebd73 1963 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1964 case OP_RXSTAT:
497d7c86 1965 skb = sky2_receive(dev, length, status);
d1f13708
SH		 1966 if (!skb)
1967 break;
13210ce5 1968
13210ce5
SH		 1969 skb->protocol = eth_type_trans(skb, dev);
1970 dev->last_rx = jiffies;
1971
d1f13708
SH		 1972#ifdef SKY2_VLAN_TAG_USED
1973 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1974 vlan_hwaccel_receive_skb(skb,
1975 sky2->vlgrp,
1976 be16_to_cpu(sky2->rx_tag));
1977 } else
1978#endif
cd28ab6a 1979 netif_receive_skb(skb);
13210ce5 1980
22e11703
SH		 1981 /* Update receiver after 16 frames */
1982 if (++buf_write[le->link] == RX_BUF_WRITE) {
1983 sky2_put_idx(hw, rxqaddr[le->link],
1984 sky2->rx_put);
1985 buf_write[le->link] = 0;
1986 }
1987
1988 /* Stop after net poll weight */
13210ce5
SH		 1989 if (++work_done >= to_do)
1990 goto exit_loop;
cd28ab6a
SH		 1991 break;
1992
d1f13708
SH		 1993#ifdef SKY2_VLAN_TAG_USED
1994 case OP_RXVLAN:
1995 sky2->rx_tag = length;
1996 break;
1997
1998 case OP_RXCHKSVLAN:
1999 sky2->rx_tag = length;
2000 /* fall through */
2001#endif
cd28ab6a 2002 case OP_RXCHKS:
d11c13e7
SH		 2003 skb = sky2->rx_ring[sky2->rx_next].skb;
2004 skb->ip_summed = CHECKSUM_HW;
2005 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 2006 break;
2007
2008 case OP_TXINDEXLE:
13b97b74 2009 /* TX index reports status for both ports */
f55925d7
SH		 2010 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2011 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2012 if (hw->dev[1])
2013 sky2_tx_done(hw->dev[1],
2014 ((status >> 24) & 0xff)
2015 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2016 break;
2017
cd28ab6a
SH		 2018 default:
2019 if (net_ratelimit())
793b883e 2020 printk(KERN_WARNING PFX
e71ebd73
SH		 2021 "unknown status opcode 0x%x\n", le->opcode);
2022 goto exit_loop;
cd28ab6a 2023 }
13210ce5 2024 }
cd28ab6a 2025
fe2a24df
SH		 2026 /* Fully processed status ring so clear irq */
2027 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2028
13210ce5 2029exit_loop:
22e11703
SH		 2030 if (buf_write[0]) {
2031 sky2 = netdev_priv(hw->dev[0]);
2032 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2033 }
2034
2035 if (buf_write[1]) {
2036 sky2 = netdev_priv(hw->dev[1]);
2037 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2038 }
2039
e07b1aa8 2040 return work_done;
cd28ab6a
SH		 2041}
2042
2043static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2044{
2045 struct net_device *dev = hw->dev[port];
2046
3be92a70
SH		 2047 if (net_ratelimit())
2048 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2049 dev->name, status);
cd28ab6a
SH		 2050
2051 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2052 if (net_ratelimit())
2053 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2054 dev->name);
cd28ab6a
SH		 2055 /* Clear IRQ */
2056 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2057 }
2058
2059 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2060 if (net_ratelimit())
2061 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2062 dev->name);
cd28ab6a
SH		 2063
2064 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2065 }
2066
2067 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2068 if (net_ratelimit())
2069 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2070 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2071 }
2072
2073 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2074 if (net_ratelimit())
2075 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2076 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2077 }
2078
2079 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2080 if (net_ratelimit())
2081 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2082 dev->name);
cd28ab6a
SH		 2083 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2084 }
2085}
2086
2087static void sky2_hw_intr(struct sky2_hw *hw)
2088{
2089 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2090
793b883e 2091 if (status & Y2_IS_TIST_OV)
cd28ab6a 2092 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2093
2094 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2095 u16 pci_err;
2096
56a645cc 2097 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2098 if (net_ratelimit())
2099 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2100 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2101
2102 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2103 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2104 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2105 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2106 }
2107
2108 if (status & Y2_IS_PCI_EXP) {
d571b694 2109 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2110 u32 pex_err;
2111
56a645cc 2112 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2113
3be92a70
SH		 2114 if (net_ratelimit())
2115 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2116 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2117
2118 /* clear the interrupt */
2119 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2120 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2121 0xffffffffUL);
cd28ab6a
SH		 2122 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2123
2124 if (pex_err & PEX_FATAL_ERRORS) {
2125 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2126 hwmsk &= ~Y2_IS_PCI_EXP;
2127 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2128 }
2129 }
2130
2131 if (status & Y2_HWE_L1_MASK)
2132 sky2_hw_error(hw, 0, status);
2133 status >>= 8;
2134 if (status & Y2_HWE_L1_MASK)
2135 sky2_hw_error(hw, 1, status);
2136}
2137
2138static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2139{
2140 struct net_device *dev = hw->dev[port];
2141 struct sky2_port *sky2 = netdev_priv(dev);
2142 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2143
2144 if (netif_msg_intr(sky2))
2145 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2146 dev->name, status);
2147
2148 if (status & GM_IS_RX_FF_OR) {
2149 ++sky2->net_stats.rx_fifo_errors;
2150 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2151 }
2152
2153 if (status & GM_IS_TX_FF_UR) {
2154 ++sky2->net_stats.tx_fifo_errors;
2155 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2156 }
cd28ab6a
SH		 2157}
2158
d257924e
SH		 2159/* This should never happen it is a fatal situation */
2160static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2161 const char *rxtx, u32 mask)
2162{
2163 struct net_device *dev = hw->dev[port];
2164 struct sky2_port *sky2 = netdev_priv(dev);
2165 u32 imask;
2166
2167 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2168 dev ? dev->name : "<not registered>", rxtx);
2169
2170 imask = sky2_read32(hw, B0_IMSK);
2171 imask &= ~mask;
2172 sky2_write32(hw, B0_IMSK, imask);
2173
2174 if (dev) {
2175 spin_lock(&sky2->phy_lock);
2176 sky2_link_down(sky2);
2177 spin_unlock(&sky2->phy_lock);
2178 }
2179}
cd28ab6a 2180
d27ed387
SH		 2181/* If idle then force a fake soft NAPI poll once a second
2182 * to work around cases where sharing an edge triggered interrupt.
2183 */
eb35cf60
SH		 2184static inline void sky2_idle_start(struct sky2_hw *hw)
2185{
2186 if (idle_timeout > 0)
2187 mod_timer(&hw->idle_timer,
2188 jiffies + msecs_to_jiffies(idle_timeout));
2189}
2190
d27ed387
SH		 2191static void sky2_idle(unsigned long arg)
2192{
01bd7564
SH		 2193 struct sky2_hw *hw = (struct sky2_hw *) arg;
2194 struct net_device *dev = hw->dev[0];
d27ed387 2195
d27ed387
SH		 2196 if (__netif_rx_schedule_prep(dev))
2197 __netif_rx_schedule(dev);
01bd7564
SH		 2198
2199 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2200}
2201
2202
e07b1aa8 2203static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2204{
e07b1aa8
SH		 2205 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2206 int work_limit = min(dev0->quota, *budget);
2207 int work_done = 0;
fb2690a9 2208 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2209
1e5f1283
SH		 2210 if (status & Y2_IS_HW_ERR)
2211 sky2_hw_intr(hw);
d257924e 2212
1e5f1283
SH		 2213 if (status & Y2_IS_IRQ_PHY1)
2214 sky2_phy_intr(hw, 0);
cd28ab6a 2215
1e5f1283
SH		 2216 if (status & Y2_IS_IRQ_PHY2)
2217 sky2_phy_intr(hw, 1);
cd28ab6a 2218
1e5f1283
SH		 2219 if (status & Y2_IS_IRQ_MAC1)
2220 sky2_mac_intr(hw, 0);
cd28ab6a 2221
1e5f1283
SH		 2222 if (status & Y2_IS_IRQ_MAC2)
2223 sky2_mac_intr(hw, 1);
cd28ab6a 2224
1e5f1283
SH		 2225 if (status & Y2_IS_CHK_RX1)
2226 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2227
1e5f1283
SH		 2228 if (status & Y2_IS_CHK_RX2)
2229 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2230
1e5f1283
SH		 2231 if (status & Y2_IS_CHK_TXA1)
2232 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2233
1e5f1283
SH		 2234 if (status & Y2_IS_CHK_TXA2)
2235 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2236
1e5f1283 2237 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2238 if (work_done < work_limit) {
2239 netif_rx_complete(dev0);
86fba634 2240
fe2a24df
SH		 2241 sky2_read32(hw, B0_Y2_SP_LISR);
2242 return 0;
2243 } else {
2244 *budget -= work_done;
2245 dev0->quota -= work_done;
1e5f1283 2246 return 1;
fe2a24df 2247 }
e07b1aa8
SH		 2248}
2249
2250static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2251{
2252 struct sky2_hw *hw = dev_id;
2253 struct net_device *dev0 = hw->dev[0];
2254 u32 status;
2255
2256 /* Reading this mask interrupts as side effect */
2257 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2258 if (status == 0 || status == ~0)
2259 return IRQ_NONE;
793b883e 2260
e07b1aa8
SH		 2261 prefetch(&hw->st_le[hw->st_idx]);
2262 if (likely(__netif_rx_schedule_prep(dev0)))
2263 __netif_rx_schedule(dev0);
793b883e 2264
cd28ab6a
SH		 2265 return IRQ_HANDLED;
2266}
2267
2268#ifdef CONFIG_NET_POLL_CONTROLLER
2269static void sky2_netpoll(struct net_device *dev)
2270{
2271 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2272 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2273
88d11360
SH		 2274 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2275 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2276}
2277#endif
2278
2279/* Chip internal frequency for clock calculations */
fb17358f 2280static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2281{
793b883e 2282 switch (hw->chip_id) {
cd28ab6a 2283 case CHIP_ID_YUKON_EC:
5a5b1ea0 2284 case CHIP_ID_YUKON_EC_U:
fb17358f 2285 return 125; /* 125 Mhz */
cd28ab6a 2286 case CHIP_ID_YUKON_FE:
fb17358f 2287 return 100; /* 100 Mhz */
793b883e 2288 default: /* YUKON_XL */
fb17358f 2289 return 156; /* 156 Mhz */
cd28ab6a
SH		 2290 }
2291}
2292
fb17358f 2293static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2294{
fb17358f 2295 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2296}
2297
fb17358f 2298static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2299{
fb17358f 2300 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2301}
2302
fb17358f 2303
59139528 2304static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2305{
cd28ab6a
SH		 2306 u16 status;
2307 u8 t8, pmd_type;
56a645cc 2308 int i;
cd28ab6a 2309
cd28ab6a 2310 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2311
cd28ab6a
SH		 2312 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2313 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2314 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2315 pci_name(hw->pdev), hw->chip_id);
2316 return -EOPNOTSUPP;
2317 }
2318
290d4de5
SH		 2319 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2320
2321 /* This rev is really old, and requires untested workarounds */
2322 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2323 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2324 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2325 hw->chip_id, hw->chip_rev);
2326 return -EOPNOTSUPP;
2327 }
2328
cd28ab6a
SH		 2329 /* disable ASF */
2330 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2331 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2332 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2333 }
2334
2335 /* do a SW reset */
2336 sky2_write8(hw, B0_CTST, CS_RST_SET);
2337 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2338
2339 /* clear PCI errors, if any */
56a645cc 2340 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2341
cd28ab6a 2342 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2343 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2344
cd28ab6a
SH		 2345
2346 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2347
2348 /* clear any PEX errors */
d89e1343 2349 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2350 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2351
cd28ab6a
SH		 2352
2353 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2354 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2355
2356 hw->ports = 1;
2357 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2358 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2359 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2360 ++hw->ports;
2361 }
cd28ab6a 2362
5afa0a9c 2363 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2364
2365 for (i = 0; i < hw->ports; i++) {
2366 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2367 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2368 }
2369
2370 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2371
793b883e
SH		 2372 /* Clear I2C IRQ noise */
2373 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2374
2375 /* turn off hardware timer (unused) */
2376 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2377 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2378
cd28ab6a
SH		 2379 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2380
69634ee7
SH		 2381 /* Turn off descriptor polling */
2382 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2383
2384 /* Turn off receive timestamp */
2385 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2386 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2387
2388 /* enable the Tx Arbiters */
2389 for (i = 0; i < hw->ports; i++)
2390 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2391
2392 /* Initialize ram interface */
2393 for (i = 0; i < hw->ports; i++) {
793b883e 2394 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2395
2396 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2398 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2400 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2401 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2402 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2404 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2407 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2408 }
2409
cd28ab6a
SH		 2410 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2411
cd28ab6a 2412 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2413 sky2_gmac_reset(hw, i);
cd28ab6a 2414
cd28ab6a
SH		 2415 memset(hw->st_le, 0, STATUS_LE_BYTES);
2416 hw->st_idx = 0;
2417
2418 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2419 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2420
2421 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2422 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2423
2424 /* Set the list last index */
793b883e 2425 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2426
290d4de5
SH		 2427 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2428 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2429
290d4de5
SH		 2430 /* set Status-FIFO ISR watermark */
2431 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2432 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2433 else
2434 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2435
290d4de5 2436 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2437 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2438 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2439
793b883e 2440 /* enable status unit */
cd28ab6a
SH		 2441 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2442
2443 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2444 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2445 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2446
2447 return 0;
2448}
2449
28bd181a 2450static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2451{
2452 u32 modes;
2453 if (hw->copper) {
793b883e
SH		 2454 modes = SUPPORTED_10baseT_Half
2455 | SUPPORTED_10baseT_Full
2456 | SUPPORTED_100baseT_Half
2457 | SUPPORTED_100baseT_Full
2458 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2459
2460 if (hw->chip_id != CHIP_ID_YUKON_FE)
2461 modes |= SUPPORTED_1000baseT_Half
793b883e 2462 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2463 } else
2464 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2465 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2466 return modes;
2467}
2468
793b883e 2469static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2470{
2471 struct sky2_port *sky2 = netdev_priv(dev);
2472 struct sky2_hw *hw = sky2->hw;
2473
2474 ecmd->transceiver = XCVR_INTERNAL;
2475 ecmd->supported = sky2_supported_modes(hw);
2476 ecmd->phy_address = PHY_ADDR_MARV;
2477 if (hw->copper) {
2478 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2479 | SUPPORTED_10baseT_Full
2480 | SUPPORTED_100baseT_Half
2481 | SUPPORTED_100baseT_Full
2482 | SUPPORTED_1000baseT_Half
2483 | SUPPORTED_1000baseT_Full
2484 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2485 ecmd->port = PORT_TP;
2486 } else
2487 ecmd->port = PORT_FIBRE;
2488
2489 ecmd->advertising = sky2->advertising;
2490 ecmd->autoneg = sky2->autoneg;
2491 ecmd->speed = sky2->speed;
2492 ecmd->duplex = sky2->duplex;
2493 return 0;
2494}
2495
2496static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2497{
2498 struct sky2_port *sky2 = netdev_priv(dev);
2499 const struct sky2_hw *hw = sky2->hw;
2500 u32 supported = sky2_supported_modes(hw);
2501
2502 if (ecmd->autoneg == AUTONEG_ENABLE) {
2503 ecmd->advertising = supported;
2504 sky2->duplex = -1;
2505 sky2->speed = -1;
2506 } else {
2507 u32 setting;
2508
793b883e 2509 switch (ecmd->speed) {
cd28ab6a
SH		 2510 case SPEED_1000:
2511 if (ecmd->duplex == DUPLEX_FULL)
2512 setting = SUPPORTED_1000baseT_Full;
2513 else if (ecmd->duplex == DUPLEX_HALF)
2514 setting = SUPPORTED_1000baseT_Half;
2515 else
2516 return -EINVAL;
2517 break;
2518 case SPEED_100:
2519 if (ecmd->duplex == DUPLEX_FULL)
2520 setting = SUPPORTED_100baseT_Full;
2521 else if (ecmd->duplex == DUPLEX_HALF)
2522 setting = SUPPORTED_100baseT_Half;
2523 else
2524 return -EINVAL;
2525 break;
2526
2527 case SPEED_10:
2528 if (ecmd->duplex == DUPLEX_FULL)
2529 setting = SUPPORTED_10baseT_Full;
2530 else if (ecmd->duplex == DUPLEX_HALF)
2531 setting = SUPPORTED_10baseT_Half;
2532 else
2533 return -EINVAL;
2534 break;
2535 default:
2536 return -EINVAL;
2537 }
2538
2539 if ((setting & supported) == 0)
2540 return -EINVAL;
2541
2542 sky2->speed = ecmd->speed;
2543 sky2->duplex = ecmd->duplex;
2544 }
2545
2546 sky2->autoneg = ecmd->autoneg;
2547 sky2->advertising = ecmd->advertising;
2548
1b537565
SH		 2549 if (netif_running(dev))
2550 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2551
2552 return 0;
2553}
2554
2555static void sky2_get_drvinfo(struct net_device *dev,
2556 struct ethtool_drvinfo *info)
2557{
2558 struct sky2_port *sky2 = netdev_priv(dev);
2559
2560 strcpy(info->driver, DRV_NAME);
2561 strcpy(info->version, DRV_VERSION);
2562 strcpy(info->fw_version, "N/A");
2563 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2564}
2565
2566static const struct sky2_stat {
793b883e
SH		 2567 char name[ETH_GSTRING_LEN];
2568 u16 offset;
cd28ab6a
SH		 2569} sky2_stats[] = {
2570 { "tx_bytes", GM_TXO_OK_HI },
2571 { "rx_bytes", GM_RXO_OK_HI },
2572 { "tx_broadcast", GM_TXF_BC_OK },
2573 { "rx_broadcast", GM_RXF_BC_OK },
2574 { "tx_multicast", GM_TXF_MC_OK },
2575 { "rx_multicast", GM_RXF_MC_OK },
2576 { "tx_unicast", GM_TXF_UC_OK },
2577 { "rx_unicast", GM_RXF_UC_OK },
2578 { "tx_mac_pause", GM_TXF_MPAUSE },
2579 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2580 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2581 { "late_collision",GM_TXF_LAT_COL },
2582 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2583 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2584 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2585
d2604540 2586 { "rx_short", GM_RXF_SHT },
cd28ab6a 2587 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2588 { "rx_64_byte_packets", GM_RXF_64B },
2589 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2590 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2591 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2592 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2593 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2594 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2595 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2596 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2597 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2598 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2599
2600 { "tx_64_byte_packets", GM_TXF_64B },
2601 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2602 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2603 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2604 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2605 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2606 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2607 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2608};
2609
cd28ab6a
SH		 2610static u32 sky2_get_rx_csum(struct net_device *dev)
2611{
2612 struct sky2_port *sky2 = netdev_priv(dev);
2613
2614 return sky2->rx_csum;
2615}
2616
2617static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2618{
2619 struct sky2_port *sky2 = netdev_priv(dev);
2620
2621 sky2->rx_csum = data;
793b883e 2622
cd28ab6a
SH		 2623 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2624 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2625
2626 return 0;
2627}
2628
2629static u32 sky2_get_msglevel(struct net_device *netdev)
2630{
2631 struct sky2_port *sky2 = netdev_priv(netdev);
2632 return sky2->msg_enable;
2633}
2634
9a7ae0a9
SH		 2635static int sky2_nway_reset(struct net_device *dev)
2636{
2637 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2638
2639 if (sky2->autoneg != AUTONEG_ENABLE)
2640 return -EINVAL;
2641
1b537565 2642 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2643
2644 return 0;
2645}
2646
793b883e 2647static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2648{
2649 struct sky2_hw *hw = sky2->hw;
2650 unsigned port = sky2->port;
2651 int i;
2652
2653 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2654 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2655 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2656 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2657
793b883e 2658 for (i = 2; i < count; i++)
cd28ab6a
SH		 2659 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2660}
2661
cd28ab6a
SH		 2662static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2663{
2664 struct sky2_port *sky2 = netdev_priv(netdev);
2665 sky2->msg_enable = value;
2666}
2667
2668static int sky2_get_stats_count(struct net_device *dev)
2669{
2670 return ARRAY_SIZE(sky2_stats);
2671}
2672
2673static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2674 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2675{
2676 struct sky2_port *sky2 = netdev_priv(dev);
2677
793b883e 2678 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2679}
2680
793b883e 2681static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2682{
2683 int i;
2684
2685 switch (stringset) {
2686 case ETH_SS_STATS:
2687 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2688 memcpy(data + i * ETH_GSTRING_LEN,
2689 sky2_stats[i].name, ETH_GSTRING_LEN);
2690 break;
2691 }
2692}
2693
2694/* Use hardware MIB variables for critical path statistics and
2695 * transmit feedback not reported at interrupt.
2696 * Other errors are accounted for in interrupt handler.
2697 */
2698static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2699{
2700 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2701 u64 data[13];
cd28ab6a 2702
793b883e 2703 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2704
2705 sky2->net_stats.tx_bytes = data[0];
2706 sky2->net_stats.rx_bytes = data[1];
2707 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2708 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2709 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2710 sky2->net_stats.collisions = data[10];
2711 sky2->net_stats.tx_aborted_errors = data[12];
2712
2713 return &sky2->net_stats;
2714}
2715
2716static int sky2_set_mac_address(struct net_device *dev, void *p)
2717{
2718 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2719 struct sky2_hw *hw = sky2->hw;
2720 unsigned port = sky2->port;
2721 const struct sockaddr *addr = p;
cd28ab6a
SH		 2722
2723 if (!is_valid_ether_addr(addr->sa_data))
2724 return -EADDRNOTAVAIL;
2725
cd28ab6a 2726 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2727 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2728 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2729 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2730 dev->dev_addr, ETH_ALEN);
1b537565 2731
a8ab1ec0
SH		 2732 /* virtual address for data */
2733 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2734
2735 /* physical address: used for pause frames */
2736 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2737
2738 return 0;
cd28ab6a
SH		 2739}
2740
2741static void sky2_set_multicast(struct net_device *dev)
2742{
2743 struct sky2_port *sky2 = netdev_priv(dev);
2744 struct sky2_hw *hw = sky2->hw;
2745 unsigned port = sky2->port;
2746 struct dev_mc_list *list = dev->mc_list;
2747 u16 reg;
2748 u8 filter[8];
2749
2750 memset(filter, 0, sizeof(filter));
2751
2752 reg = gma_read16(hw, port, GM_RX_CTRL);
2753 reg |= GM_RXCR_UCF_ENA;
2754
d571b694 2755 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2756 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2757 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2758 memset(filter, 0xff, sizeof(filter));
793b883e 2759 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2760 reg &= ~GM_RXCR_MCF_ENA;
2761 else {
2762 int i;
2763 reg |= GM_RXCR_MCF_ENA;
2764
2765 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2766 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2767 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2768 }
2769 }
2770
cd28ab6a 2771 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2772 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2773 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2774 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2775 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2776 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2777 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2778 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2779
2780 gma_write16(hw, port, GM_RX_CTRL, reg);
2781}
2782
2783/* Can have one global because blinking is controlled by
2784 * ethtool and that is always under RTNL mutex
2785 */
91c86df5 2786static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2787{
793b883e
SH		 2788 u16 pg;
2789
793b883e
SH		 2790 switch (hw->chip_id) {
2791 case CHIP_ID_YUKON_XL:
2792 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2793 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2794 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2795 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2796 PHY_M_LEDC_INIT_CTRL(7) |
2797 PHY_M_LEDC_STA1_CTRL(7) |
2798 PHY_M_LEDC_STA0_CTRL(7))
2799 : 0);
2800
2801 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2802 break;
2803
2804 default:
2805 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2806 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2807 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2808 PHY_M_LED_MO_10(MO_LED_ON) |
2809 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2810 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2811 PHY_M_LED_MO_RX(MO_LED_ON)
2812 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2813 PHY_M_LED_MO_10(MO_LED_OFF) |
2814 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2815 PHY_M_LED_MO_1000(MO_LED_OFF) |
2816 PHY_M_LED_MO_RX(MO_LED_OFF));
2817
793b883e 2818 }
cd28ab6a
SH		 2819}
2820
2821/* blink LED's for finding board */
2822static int sky2_phys_id(struct net_device *dev, u32 data)
2823{
2824 struct sky2_port *sky2 = netdev_priv(dev);
2825 struct sky2_hw *hw = sky2->hw;
2826 unsigned port = sky2->port;
793b883e 2827 u16 ledctrl, ledover = 0;
cd28ab6a 2828 long ms;
91c86df5 2829 int interrupted;
cd28ab6a
SH		 2830 int onoff = 1;
2831
793b883e 2832 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2833 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2834 else
2835 ms = data * 1000;
2836
2837 /* save initial values */
e07b1aa8 2838 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2839 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2840 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2841 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2842 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2843 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2844 } else {
2845 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2846 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2847 }
cd28ab6a 2848
91c86df5
SH		 2849 interrupted = 0;
2850 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2851 sky2_led(hw, port, onoff);
2852 onoff = !onoff;
2853
e07b1aa8 2854 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2855 interrupted = msleep_interruptible(250);
e07b1aa8 2856 spin_lock_bh(&sky2->phy_lock);
91c86df5 2857
cd28ab6a
SH		 2858 ms -= 250;
2859 }
2860
2861 /* resume regularly scheduled programming */
793b883e
SH		 2862 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2863 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2864 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2865 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2866 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2867 } else {
2868 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2869 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2870 }
e07b1aa8 2871 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2872
2873 return 0;
2874}
2875
2876static void sky2_get_pauseparam(struct net_device *dev,
2877 struct ethtool_pauseparam *ecmd)
2878{
2879 struct sky2_port *sky2 = netdev_priv(dev);
2880
2881 ecmd->tx_pause = sky2->tx_pause;
2882 ecmd->rx_pause = sky2->rx_pause;
2883 ecmd->autoneg = sky2->autoneg;
2884}
2885
2886static int sky2_set_pauseparam(struct net_device *dev,
2887 struct ethtool_pauseparam *ecmd)
2888{
2889 struct sky2_port *sky2 = netdev_priv(dev);
2890 int err = 0;
2891
2892 sky2->autoneg = ecmd->autoneg;
2893 sky2->tx_pause = ecmd->tx_pause != 0;
2894 sky2->rx_pause = ecmd->rx_pause != 0;
2895
1b537565 2896 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2897
2898 return err;
2899}
2900
fb17358f
SH		 2901static int sky2_get_coalesce(struct net_device *dev,
2902 struct ethtool_coalesce *ecmd)
2903{
2904 struct sky2_port *sky2 = netdev_priv(dev);
2905 struct sky2_hw *hw = sky2->hw;
2906
2907 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2908 ecmd->tx_coalesce_usecs = 0;
2909 else {
2910 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2911 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2912 }
2913 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2914
2915 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2916 ecmd->rx_coalesce_usecs = 0;
2917 else {
2918 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2919 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2920 }
2921 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2922
2923 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2924 ecmd->rx_coalesce_usecs_irq = 0;
2925 else {
2926 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2927 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2928 }
2929
2930 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2931
2932 return 0;
2933}
2934
2935/* Note: this affect both ports */
2936static int sky2_set_coalesce(struct net_device *dev,
2937 struct ethtool_coalesce *ecmd)
2938{
2939 struct sky2_port *sky2 = netdev_priv(dev);
2940 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2941 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2942
77b3d6a2
SH		 2943 if (ecmd->tx_coalesce_usecs > tmax ||
2944 ecmd->rx_coalesce_usecs > tmax ||
2945 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2946 return -EINVAL;
2947
ff81fbbe 2948 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2949 return -EINVAL;
ff81fbbe 2950 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2951 return -EINVAL;
ff81fbbe 2952 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2953 return -EINVAL;
2954
2955 if (ecmd->tx_coalesce_usecs == 0)
2956 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2957 else {
2958 sky2_write32(hw, STAT_TX_TIMER_INI,
2959 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2960 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2961 }
2962 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2963
2964 if (ecmd->rx_coalesce_usecs == 0)
2965 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2966 else {
2967 sky2_write32(hw, STAT_LEV_TIMER_INI,
2968 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2969 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2970 }
2971 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2972
2973 if (ecmd->rx_coalesce_usecs_irq == 0)
2974 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2975 else {
d28d4870 2976 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2977 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2978 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2979 }
2980 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2981 return 0;
2982}
2983
793b883e
SH		 2984static void sky2_get_ringparam(struct net_device *dev,
2985 struct ethtool_ringparam *ering)
2986{
2987 struct sky2_port *sky2 = netdev_priv(dev);
2988
2989 ering->rx_max_pending = RX_MAX_PENDING;
2990 ering->rx_mini_max_pending = 0;
2991 ering->rx_jumbo_max_pending = 0;
2992 ering->tx_max_pending = TX_RING_SIZE - 1;
2993
2994 ering->rx_pending = sky2->rx_pending;
2995 ering->rx_mini_pending = 0;
2996 ering->rx_jumbo_pending = 0;
2997 ering->tx_pending = sky2->tx_pending;
2998}
2999
3000static int sky2_set_ringparam(struct net_device *dev,
3001 struct ethtool_ringparam *ering)
3002{
3003 struct sky2_port *sky2 = netdev_priv(dev);
3004 int err = 0;
3005
3006 if (ering->rx_pending > RX_MAX_PENDING ||
3007 ering->rx_pending < 8 ||
3008 ering->tx_pending < MAX_SKB_TX_LE ||
3009 ering->tx_pending > TX_RING_SIZE - 1)
3010 return -EINVAL;
3011
3012 if (netif_running(dev))
3013 sky2_down(dev);
3014
3015 sky2->rx_pending = ering->rx_pending;
3016 sky2->tx_pending = ering->tx_pending;
3017
1b537565 3018 if (netif_running(dev)) {
793b883e 3019 err = sky2_up(dev);
1b537565
SH		 3020 if (err)
3021 dev_close(dev);
6ed995bb
SH		 3022 else
3023 sky2_set_multicast(dev);
1b537565 3024 }
793b883e
SH		 3025
3026 return err;
3027}
3028
793b883e
SH		 3029static int sky2_get_regs_len(struct net_device *dev)
3030{
6e4cbb34 3031 return 0x4000;
793b883e
SH		 3032}
3033
3034/*
3035 * Returns copy of control register region
6e4cbb34 3036 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3037 */
3038static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3039 void *p)
3040{
3041 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3042 const void __iomem *io = sky2->hw->regs;
793b883e 3043
6e4cbb34 3044 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3045 regs->version = 1;
6e4cbb34 3046 memset(p, 0, regs->len);
793b883e 3047
6e4cbb34
SH		 3048 memcpy_fromio(p, io, B3_RAM_ADDR);
3049
3050 memcpy_fromio(p + B3_RI_WTO_R1,
3051 io + B3_RI_WTO_R1,
3052 regs->len - B3_RI_WTO_R1);
793b883e 3053}
cd28ab6a
SH		 3054
3055static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3056 .get_settings = sky2_get_settings,
3057 .set_settings = sky2_set_settings,
3058 .get_drvinfo = sky2_get_drvinfo,
3059 .get_msglevel = sky2_get_msglevel,
3060 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3061 .nway_reset = sky2_nway_reset,
793b883e
SH		 3062 .get_regs_len = sky2_get_regs_len,
3063 .get_regs = sky2_get_regs,
3064 .get_link = ethtool_op_get_link,
3065 .get_sg = ethtool_op_get_sg,
3066 .set_sg = ethtool_op_set_sg,
3067 .get_tx_csum = ethtool_op_get_tx_csum,
3068 .set_tx_csum = ethtool_op_set_tx_csum,
3069 .get_tso = ethtool_op_get_tso,
3070 .set_tso = ethtool_op_set_tso,
3071 .get_rx_csum = sky2_get_rx_csum,
3072 .set_rx_csum = sky2_set_rx_csum,
3073 .get_strings = sky2_get_strings,
fb17358f
SH		 3074 .get_coalesce = sky2_get_coalesce,
3075 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3076 .get_ringparam = sky2_get_ringparam,
3077 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3078 .get_pauseparam = sky2_get_pauseparam,
3079 .set_pauseparam = sky2_set_pauseparam,
793b883e 3080 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3081 .get_stats_count = sky2_get_stats_count,
3082 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3083 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3084};
3085
3086/* Initialize network device */
3087static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3088 unsigned port, int highmem)
3089{
3090 struct sky2_port *sky2;
3091 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3092
3093 if (!dev) {
3094 printk(KERN_ERR "sky2 etherdev alloc failed");
3095 return NULL;
3096 }
3097
3098 SET_MODULE_OWNER(dev);
3099 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3100 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3101 dev->open = sky2_up;
3102 dev->stop = sky2_down;
ef743d33 3103 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3104 dev->hard_start_xmit = sky2_xmit_frame;
3105 dev->get_stats = sky2_get_stats;
3106 dev->set_multicast_list = sky2_set_multicast;
3107 dev->set_mac_address = sky2_set_mac_address;
3108 dev->change_mtu = sky2_change_mtu;
3109 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3110 dev->tx_timeout = sky2_tx_timeout;
3111 dev->watchdog_timeo = TX_WATCHDOG;
3112 if (port == 0)
3113 dev->poll = sky2_poll;
3114 dev->weight = NAPI_WEIGHT;
3115#ifdef CONFIG_NET_POLL_CONTROLLER
3116 dev->poll_controller = sky2_netpoll;
3117#endif
cd28ab6a
SH		 3118
3119 sky2 = netdev_priv(dev);
3120 sky2->netdev = dev;
3121 sky2->hw = hw;
3122 sky2->msg_enable = netif_msg_init(debug, default_msg);
3123
3124 spin_lock_init(&sky2->tx_lock);
3125 /* Auto speed and flow control */
3126 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3127 sky2->tx_pause = 1;
cd28ab6a
SH		 3128 sky2->rx_pause = 1;
3129 sky2->duplex = -1;
3130 sky2->speed = -1;
3131 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3132 sky2->rx_csum = 1;
75d070c5 3133
e07b1aa8 3134 spin_lock_init(&sky2->phy_lock);
793b883e 3135 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3136 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3137 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3138
3139 hw->dev[port] = dev;
3140
3141 sky2->port = port;
3142
5a5b1ea0
SH		 3143 dev->features |= NETIF_F_LLTX;
3144 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3145 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3146 if (highmem)
3147 dev->features |= NETIF_F_HIGHDMA;
793b883e 3148 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3149
d1f13708
SH		 3150#ifdef SKY2_VLAN_TAG_USED
3151 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3152 dev->vlan_rx_register = sky2_vlan_rx_register;
3153 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3154#endif
3155
cd28ab6a 3156 /* read the mac address */
793b883e 3157 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3158 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3159
3160 /* device is off until link detection */
3161 netif_carrier_off(dev);
3162 netif_stop_queue(dev);
3163
3164 return dev;
3165}
3166
28bd181a 3167static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3168{
3169 const struct sky2_port *sky2 = netdev_priv(dev);
3170
3171 if (netif_msg_probe(sky2))
3172 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3173 dev->name,
3174 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3175 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3176}
3177
fb2690a9
SH		 3178/* Handle software interrupt used during MSI test */
3179static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3180 struct pt_regs *regs)
3181{
3182 struct sky2_hw *hw = dev_id;
3183 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3184
3185 if (status == 0)
3186 return IRQ_NONE;
3187
3188 if (status & Y2_IS_IRQ_SW) {
3189 hw->msi_detected = 1;
3190 wake_up(&hw->msi_wait);
3191 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3192 }
3193 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3194
3195 return IRQ_HANDLED;
3196}
3197
3198/* Test interrupt path by forcing a a software IRQ */
3199static int __devinit sky2_test_msi(struct sky2_hw *hw)
3200{
3201 struct pci_dev *pdev = hw->pdev;
3202 int err;
3203
bb507fe1
SH		 3204 init_waitqueue_head (&hw->msi_wait);
3205
fb2690a9
SH		 3206 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3207
1fb9df5d 3208 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3209 if (err) {
3210 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3211 pci_name(pdev), pdev->irq);
3212 return err;
3213 }
3214
fb2690a9 3215 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3216 sky2_read8(hw, B0_CTST);
fb2690a9
SH		 3217
3218 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3219
3220 if (!hw->msi_detected) {
3221 /* MSI test failed, go back to INTx mode */
3222 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3223 "switching to INTx mode. Please report this failure to "
3224 "the PCI maintainer and include system chipset information.\n",
3225 pci_name(pdev));
3226
3227 err = -EOPNOTSUPP;
3228 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3229 }
3230
3231 sky2_write32(hw, B0_IMSK, 0);
3232
3233 free_irq(pdev->irq, hw);
3234
3235 return err;
3236}
3237
cd28ab6a
SH		 3238static int __devinit sky2_probe(struct pci_dev *pdev,
3239 const struct pci_device_id *ent)
3240{
793b883e 3241 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3242 struct sky2_hw *hw;
5afa0a9c 3243 int err, pm_cap, using_dac = 0;
cd28ab6a 3244
793b883e
SH		 3245 err = pci_enable_device(pdev);
3246 if (err) {
cd28ab6a
SH		 3247 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3248 pci_name(pdev));
3249 goto err_out;
3250 }
3251
793b883e
SH		 3252 err = pci_request_regions(pdev, DRV_NAME);
3253 if (err) {
cd28ab6a
SH		 3254 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3255 pci_name(pdev));
793b883e 3256 goto err_out;
cd28ab6a
SH		 3257 }
3258
3259 pci_set_master(pdev);
3260
5afa0a9c
SH		 3261 /* Find power-management capability. */
3262 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3263 if (pm_cap == 0) {
3264 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3265 "aborting.\n");
3266 err = -EIO;
3267 goto err_out_free_regions;
3268 }
3269
d1f3d4dd
SH		 3270 if (sizeof(dma_addr_t) > sizeof(u32) &&
3271 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3272 using_dac = 1;
3273 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3274 if (err < 0) {
3275 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3276 "for consistent allocations\n", pci_name(pdev));
3277 goto err_out_free_regions;
3278 }
cd28ab6a 3279
d1f3d4dd 3280 } else {
cd28ab6a
SH		 3281 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3282 if (err) {
3283 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3284 pci_name(pdev));
3285 goto err_out_free_regions;
3286 }
3287 }
d1f3d4dd 3288
cd28ab6a 3289 err = -ENOMEM;
6aad85d6 3290 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3291 if (!hw) {
3292 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3293 pci_name(pdev));
3294 goto err_out_free_regions;
3295 }
3296
cd28ab6a 3297 hw->pdev = pdev;
cd28ab6a
SH		 3298
3299 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3300 if (!hw->regs) {
3301 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3302 pci_name(pdev));
3303 goto err_out_free_hw;
3304 }
5afa0a9c 3305 hw->pm_cap = pm_cap;
cd28ab6a 3306
56a645cc
SH		 3307#ifdef __BIG_ENDIAN
3308 /* byte swap descriptors in hardware */
3309 {
3310 u32 reg;
3311
3312 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3313 reg |= PCI_REV_DESC;
3314 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3315 }
3316#endif
3317
08c06d8a
SH		 3318 /* ring for status responses */
3319 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3320 &hw->st_dma);
3321 if (!hw->st_le)
3322 goto err_out_iounmap;
3323
cd28ab6a
SH		 3324 err = sky2_reset(hw);
3325 if (err)
793b883e 3326 goto err_out_iounmap;
cd28ab6a 3327
7c7459d1
GKH		 3328 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3329 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3330 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3331 hw->chip_id, hw->chip_rev);
cd28ab6a 3332
793b883e
SH		 3333 dev = sky2_init_netdev(hw, 0, using_dac);
3334 if (!dev)
cd28ab6a
SH		 3335 goto err_out_free_pci;
3336
793b883e
SH		 3337 err = register_netdev(dev);
3338 if (err) {
cd28ab6a
SH		 3339 printk(KERN_ERR PFX "%s: cannot register net device\n",
3340 pci_name(pdev));
3341 goto err_out_free_netdev;
3342 }
3343
3344 sky2_show_addr(dev);
3345
3346 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3347 if (register_netdev(dev1) == 0)
3348 sky2_show_addr(dev1);
3349 else {
3350 /* Failure to register second port need not be fatal */
793b883e
SH		 3351 printk(KERN_WARNING PFX
3352 "register of second port failed\n");
cd28ab6a
SH		 3353 hw->dev[1] = NULL;
3354 free_netdev(dev1);
3355 }
3356 }
3357
fb2690a9
SH		 3358 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3359 err = sky2_test_msi(hw);
3360 if (err == -EOPNOTSUPP)
3361 pci_disable_msi(pdev);
3362 else if (err)
3363 goto err_out_unregister;
3364 }
3365
1fb9df5d 3366 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
793b883e
SH		 3367 if (err) {
3368 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3369 pci_name(pdev), pdev->irq);
3370 goto err_out_unregister;
3371 }
3372
e07b1aa8 3373 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3374
01bd7564 3375 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3376 sky2_idle_start(hw);
d27ed387 3377
793b883e
SH		 3378 pci_set_drvdata(pdev, hw);
3379
cd28ab6a
SH		 3380 return 0;
3381
793b883e 3382err_out_unregister:
fb2690a9 3383 pci_disable_msi(pdev);
793b883e
SH		 3384 if (dev1) {
3385 unregister_netdev(dev1);
3386 free_netdev(dev1);
3387 }
3388 unregister_netdev(dev);
cd28ab6a
SH		 3389err_out_free_netdev:
3390 free_netdev(dev);
cd28ab6a 3391err_out_free_pci:
793b883e 3392 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3393 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3394err_out_iounmap:
3395 iounmap(hw->regs);
3396err_out_free_hw:
3397 kfree(hw);
3398err_out_free_regions:
3399 pci_release_regions(pdev);
cd28ab6a 3400 pci_disable_device(pdev);
cd28ab6a
SH		 3401err_out:
3402 return err;
3403}
3404
3405static void __devexit sky2_remove(struct pci_dev *pdev)
3406{
793b883e 3407 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3408 struct net_device *dev0, *dev1;
3409
793b883e 3410 if (!hw)
cd28ab6a
SH		 3411 return;
3412
d27ed387
SH		 3413 del_timer_sync(&hw->idle_timer);
3414
3415 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3416 synchronize_irq(hw->pdev->irq);
3417
cd28ab6a 3418 dev0 = hw->dev[0];
793b883e
SH		 3419 dev1 = hw->dev[1];
3420 if (dev1)
3421 unregister_netdev(dev1);
cd28ab6a
SH		 3422 unregister_netdev(dev0);
3423
5afa0a9c 3424 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3425 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3426 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3427 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3428
3429 free_irq(pdev->irq, hw);
fb2690a9 3430 pci_disable_msi(pdev);
793b883e 3431 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3432 pci_release_regions(pdev);
3433 pci_disable_device(pdev);
793b883e 3434
cd28ab6a
SH		 3435 if (dev1)
3436 free_netdev(dev1);
3437 free_netdev(dev0);
3438 iounmap(hw->regs);
3439 kfree(hw);
5afa0a9c 3440
cd28ab6a
SH		 3441 pci_set_drvdata(pdev, NULL);
3442}
3443
3444#ifdef CONFIG_PM
3445static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3446{
793b883e 3447 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3448 int i;
2ccc99b7
SH		 3449 pci_power_t pstate = pci_choose_state(pdev, state);
3450
3451 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3452 return -EINVAL;
cd28ab6a 3453
eb35cf60 3454 del_timer_sync(&hw->idle_timer);
6a5706b9 3455 netif_poll_disable(hw->dev[0]);
eb35cf60 3456
f05267e7 3457 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3458 struct net_device *dev = hw->dev[i];
3459
6a5706b9 3460 if (netif_running(dev)) {
5afa0a9c 3461 sky2_down(dev);
cd28ab6a 3462 netif_device_detach(dev);
cd28ab6a
SH		 3463 }
3464 }
3465
8ab8fca2 3466 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3467 pci_save_state(pdev);
2ccc99b7
SH		 3468 sky2_set_power_state(hw, pstate);
3469 return 0;
cd28ab6a
SH		 3470}
3471
3472static int sky2_resume(struct pci_dev *pdev)
3473{
793b883e 3474 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3475 int i, err;
cd28ab6a 3476
cd28ab6a
SH		 3477 pci_restore_state(pdev);
3478 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3479 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3480
08c06d8a
SH		 3481 err = sky2_reset(hw);
3482 if (err)
3483 goto out;
cd28ab6a 3484
8ab8fca2
SH		 3485 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3486
f05267e7 3487 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3488 struct net_device *dev = hw->dev[i];
6a5706b9 3489 if (netif_running(dev)) {
08c06d8a 3490 netif_device_attach(dev);
88d11360 3491
08c06d8a
SH		 3492 err = sky2_up(dev);
3493 if (err) {
3494 printk(KERN_ERR PFX "%s: could not up: %d\n",
3495 dev->name, err);
3496 dev_close(dev);
eb35cf60 3497 goto out;
5afa0a9c 3498 }
cd28ab6a
SH		 3499 }
3500 }
eb35cf60 3501
6a5706b9 3502 netif_poll_enable(hw->dev[0]);
eb35cf60 3503 sky2_idle_start(hw);
08c06d8a
SH		 3504out:
3505 return err;
cd28ab6a
SH		 3506}
3507#endif
3508
3509static struct pci_driver sky2_driver = {
793b883e
SH		 3510 .name = DRV_NAME,
3511 .id_table = sky2_id_table,
3512 .probe = sky2_probe,
3513 .remove = __devexit_p(sky2_remove),
cd28ab6a 3514#ifdef CONFIG_PM
793b883e
SH		 3515 .suspend = sky2_suspend,
3516 .resume = sky2_resume,
cd28ab6a
SH		 3517#endif
3518};
3519
3520static int __init sky2_init_module(void)
3521{
50241c4c 3522 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3523}
3524
3525static void __exit sky2_cleanup_module(void)
3526{
3527 pci_unregister_driver(&sky2_driver);
3528}
3529
3530module_init(sky2_init_module);
3531module_exit(sky2_cleanup_module);
3532
3533MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3534MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3535MODULE_LICENSE("GPL");
5f4f9dc1 3536MODULE_VERSION(DRV_VERSION);
Ubuntu Jammy Linux kernel mirror