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Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
798b6b19 | 13 | * the Free Software Foundation; either version 2 of the License. |
cd28ab6a SH |
14 | * |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
18 | * GNU General Public License for more details. |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
793b883e | 25 | #include <linux/crc32.h> |
cd28ab6a SH |
26 | #include <linux/kernel.h> |
27 | #include <linux/version.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/netdevice.h> | |
d0bbccfa | 30 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
31 | #include <linux/etherdevice.h> |
32 | #include <linux/ethtool.h> | |
33 | #include <linux/pci.h> | |
555382cb | 34 | #include <linux/aer.h> |
cd28ab6a | 35 | #include <linux/ip.h> |
c9bdd4b5 | 36 | #include <net/ip.h> |
cd28ab6a SH |
37 | #include <linux/tcp.h> |
38 | #include <linux/in.h> | |
39 | #include <linux/delay.h> | |
91c86df5 | 40 | #include <linux/workqueue.h> |
d1f13708 | 41 | #include <linux/if_vlan.h> |
d70cd51a | 42 | #include <linux/prefetch.h> |
3cf26753 | 43 | #include <linux/debugfs.h> |
ef743d33 | 44 | #include <linux/mii.h> |
cd28ab6a SH |
45 | |
46 | #include <asm/irq.h> | |
47 | ||
d1f13708 SH |
48 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
49 | #define SKY2_VLAN_TAG_USED 1 | |
50 | #endif | |
51 | ||
cd28ab6a SH |
52 | #include "sky2.h" |
53 | ||
54 | #define DRV_NAME "sky2" | |
a7b850ea | 55 | #define DRV_VERSION "1.19" |
cd28ab6a SH |
56 | #define PFX DRV_NAME " " |
57 | ||
58 | /* | |
59 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
60 | * that are organized into three (receive, transmit, status) different rings | |
14d0263f | 61 | * similar to Tigon3. |
cd28ab6a SH |
62 | */ |
63 | ||
14d0263f | 64 | #define RX_LE_SIZE 1024 |
cd28ab6a | 65 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
14d0263f | 66 | #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) |
13210ce5 | 67 | #define RX_DEF_PENDING RX_MAX_PENDING |
82788c7a | 68 | #define RX_SKB_ALIGN 8 |
793b883e SH |
69 | |
70 | #define TX_RING_SIZE 512 | |
71 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
72 | #define TX_MIN_PENDING 64 | |
b19666d9 | 73 | #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS) |
cd28ab6a | 74 | |
793b883e | 75 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a | 76 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
cd28ab6a SH |
77 | #define TX_WATCHDOG (5 * HZ) |
78 | #define NAPI_WEIGHT 64 | |
79 | #define PHY_RETRIES 1000 | |
80 | ||
f4331a6d SH |
81 | #define SKY2_EEPROM_MAGIC 0x9955aabb |
82 | ||
83 | ||
cb5d9547 SH |
84 | #define RING_NEXT(x,s) (((x)+1) & ((s)-1)) |
85 | ||
cd28ab6a | 86 | static const u32 default_msg = |
793b883e SH |
87 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
88 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
3be92a70 | 89 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
cd28ab6a | 90 | |
793b883e | 91 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
92 | module_param(debug, int, 0); |
93 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
94 | ||
14d0263f | 95 | static int copybreak __read_mostly = 128; |
bdb5c58e SH |
96 | module_param(copybreak, int, 0); |
97 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
98 | ||
fb2690a9 SH |
99 | static int disable_msi = 0; |
100 | module_param(disable_msi, int, 0); | |
101 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
102 | ||
cd28ab6a | 103 | static const struct pci_device_id sky2_id_table[] = { |
e5b74c7d SH |
104 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ |
105 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ | |
2d2a3871 | 106 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ |
2f4a66ad | 107 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ |
508f89e7 | 108 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ |
f1a0b6f5 | 109 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ |
e5b74c7d SH |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ | |
118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ | |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ | |
120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ | |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ | |
05745c4a | 122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ |
e5b74c7d | 123 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ |
05745c4a | 124 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ |
e5b74c7d SH |
125 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ |
126 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ | |
127 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ | |
128 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ | |
129 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ | |
05745c4a | 130 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ |
e5b74c7d SH |
131 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ |
132 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ | |
133 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ | |
f1a0b6f5 SH |
134 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ |
135 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ | |
69161611 | 136 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ |
cd28ab6a SH |
137 | { 0 } |
138 | }; | |
793b883e | 139 | |
cd28ab6a SH |
140 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
141 | ||
142 | /* Avoid conditionals by using array */ | |
143 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
144 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
f4ea431b | 145 | static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; |
cd28ab6a | 146 | |
92f965e8 SH |
147 | /* This driver supports yukon2 chipset only */ |
148 | static const char *yukon2_name[] = { | |
149 | "XL", /* 0xb3 */ | |
150 | "EC Ultra", /* 0xb4 */ | |
93745494 | 151 | "Extreme", /* 0xb5 */ |
92f965e8 SH |
152 | "EC", /* 0xb6 */ |
153 | "FE", /* 0xb7 */ | |
05745c4a | 154 | "FE+", /* 0xb8 */ |
793b883e SH |
155 | }; |
156 | ||
d1b139c0 SH |
157 | static void sky2_set_multicast(struct net_device *dev); |
158 | ||
793b883e | 159 | /* Access to external PHY */ |
ef743d33 | 160 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
161 | { |
162 | int i; | |
163 | ||
164 | gma_write16(hw, port, GM_SMI_DATA, val); | |
165 | gma_write16(hw, port, GM_SMI_CTRL, | |
166 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
167 | ||
168 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 169 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
ef743d33 | 170 | return 0; |
793b883e | 171 | udelay(1); |
cd28ab6a | 172 | } |
ef743d33 | 173 | |
793b883e | 174 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 175 | return -ETIMEDOUT; |
cd28ab6a SH |
176 | } |
177 | ||
ef743d33 | 178 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
179 | { |
180 | int i; | |
181 | ||
793b883e | 182 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
183 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
184 | ||
185 | for (i = 0; i < PHY_RETRIES; i++) { | |
ef743d33 SH |
186 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { |
187 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
188 | return 0; | |
189 | } | |
190 | ||
793b883e | 191 | udelay(1); |
cd28ab6a SH |
192 | } |
193 | ||
ef743d33 SH |
194 | return -ETIMEDOUT; |
195 | } | |
196 | ||
197 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
198 | { | |
199 | u16 v; | |
200 | ||
201 | if (__gm_phy_read(hw, port, reg, &v) != 0) | |
202 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); | |
203 | return v; | |
cd28ab6a SH |
204 | } |
205 | ||
5afa0a9c | 206 | |
ae306cca SH |
207 | static void sky2_power_on(struct sky2_hw *hw) |
208 | { | |
209 | /* switch power to VCC (WA for VAUX problem) */ | |
210 | sky2_write8(hw, B0_POWER_CTRL, | |
211 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
5afa0a9c | 212 | |
ae306cca SH |
213 | /* disable Core Clock Division, */ |
214 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
d3bcfbeb | 215 | |
ae306cca SH |
216 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
217 | /* enable bits are inverted */ | |
218 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
219 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
220 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
221 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
222 | else | |
223 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
977bdf06 | 224 | |
ea76e635 | 225 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { |
167f53d0 | 226 | struct pci_dev *pdev = hw->pdev; |
fc99fe06 | 227 | u32 reg; |
5afa0a9c | 228 | |
167f53d0 | 229 | pci_write_config_dword(pdev, PCI_DEV_REG3, 0); |
b2345773 | 230 | |
167f53d0 | 231 | pci_read_config_dword(pdev, PCI_DEV_REG4, ®); |
fc99fe06 SH |
232 | /* set all bits to 0 except bits 15..12 and 8 */ |
233 | reg &= P_ASPM_CONTROL_MSK; | |
167f53d0 | 234 | pci_write_config_dword(pdev, PCI_DEV_REG4, reg); |
fc99fe06 | 235 | |
167f53d0 | 236 | pci_read_config_dword(pdev, PCI_DEV_REG5, ®); |
fc99fe06 SH |
237 | /* set all bits to 0 except bits 28 & 27 */ |
238 | reg &= P_CTL_TIM_VMAIN_AV_MSK; | |
167f53d0 | 239 | pci_write_config_dword(pdev, PCI_DEV_REG5, reg); |
fc99fe06 | 240 | |
167f53d0 | 241 | pci_write_config_dword(pdev, PCI_CFG_REG_1, 0); |
8f70920f SH |
242 | |
243 | /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ | |
244 | reg = sky2_read32(hw, B2_GP_IO); | |
245 | reg |= GLB_GPIO_STAT_RACE_DIS; | |
246 | sky2_write32(hw, B2_GP_IO, reg); | |
b2345773 SH |
247 | |
248 | sky2_read32(hw, B2_GP_IO); | |
5afa0a9c | 249 | } |
ae306cca | 250 | } |
5afa0a9c | 251 | |
ae306cca SH |
252 | static void sky2_power_aux(struct sky2_hw *hw) |
253 | { | |
254 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
255 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
256 | else | |
257 | /* enable bits are inverted */ | |
258 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
259 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
260 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
261 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
262 | ||
263 | /* switch power to VAUX */ | |
264 | if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) | |
265 | sky2_write8(hw, B0_POWER_CTRL, | |
266 | (PC_VAUX_ENA | PC_VCC_ENA | | |
267 | PC_VAUX_ON | PC_VCC_OFF)); | |
5afa0a9c SH |
268 | } |
269 | ||
d3bcfbeb | 270 | static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) |
cd28ab6a SH |
271 | { |
272 | u16 reg; | |
273 | ||
274 | /* disable all GMAC IRQ's */ | |
275 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
276 | /* disable PHY IRQs */ | |
277 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 278 | |
cd28ab6a SH |
279 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
280 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
281 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
282 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
283 | ||
284 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
285 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
286 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
287 | } | |
288 | ||
16ad91e1 SH |
289 | /* flow control to advertise bits */ |
290 | static const u16 copper_fc_adv[] = { | |
291 | [FC_NONE] = 0, | |
292 | [FC_TX] = PHY_M_AN_ASP, | |
293 | [FC_RX] = PHY_M_AN_PC, | |
294 | [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, | |
295 | }; | |
296 | ||
297 | /* flow control to advertise bits when using 1000BaseX */ | |
298 | static const u16 fiber_fc_adv[] = { | |
df3fe1f3 | 299 | [FC_NONE] = PHY_M_P_NO_PAUSE_X, |
16ad91e1 SH |
300 | [FC_TX] = PHY_M_P_ASYM_MD_X, |
301 | [FC_RX] = PHY_M_P_SYM_MD_X, | |
df3fe1f3 | 302 | [FC_BOTH] = PHY_M_P_BOTH_MD_X, |
16ad91e1 SH |
303 | }; |
304 | ||
305 | /* flow control to GMA disable bits */ | |
306 | static const u16 gm_fc_disable[] = { | |
307 | [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, | |
308 | [FC_TX] = GM_GPCR_FC_RX_DIS, | |
309 | [FC_RX] = GM_GPCR_FC_TX_DIS, | |
310 | [FC_BOTH] = 0, | |
311 | }; | |
312 | ||
313 | ||
cd28ab6a SH |
314 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) |
315 | { | |
316 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
2eaba1a2 | 317 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; |
cd28ab6a | 318 | |
ea76e635 SH |
319 | if (sky2->autoneg == AUTONEG_ENABLE && |
320 | !(hw->flags & SKY2_HW_NEWER_PHY)) { | |
cd28ab6a SH |
321 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
322 | ||
323 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 324 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
325 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
326 | ||
53419c68 | 327 | /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ |
cd28ab6a | 328 | if (hw->chip_id == CHIP_ID_YUKON_EC) |
53419c68 | 329 | /* set downshift counter to 3x and enable downshift */ |
cd28ab6a SH |
330 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; |
331 | else | |
53419c68 SH |
332 | /* set master & slave downshift counter to 1x */ |
333 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); | |
cd28ab6a SH |
334 | |
335 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
336 | } | |
337 | ||
338 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
b89165f2 | 339 | if (sky2_is_copper(hw)) { |
05745c4a | 340 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
cd28ab6a SH |
341 | /* enable automatic crossover */ |
342 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
6d3105d5 SH |
343 | |
344 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && | |
345 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
346 | u16 spec; | |
347 | ||
348 | /* Enable Class A driver for FE+ A0 */ | |
349 | spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); | |
350 | spec |= PHY_M_FESC_SEL_CL_A; | |
351 | gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); | |
352 | } | |
cd28ab6a SH |
353 | } else { |
354 | /* disable energy detect */ | |
355 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
356 | ||
357 | /* enable automatic crossover */ | |
358 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
359 | ||
53419c68 | 360 | /* downshift on PHY 88E1112 and 88E1149 is changed */ |
93745494 | 361 | if (sky2->autoneg == AUTONEG_ENABLE |
ea76e635 | 362 | && (hw->flags & SKY2_HW_NEWER_PHY)) { |
53419c68 | 363 | /* set downshift counter to 3x and enable downshift */ |
cd28ab6a SH |
364 | ctrl &= ~PHY_M_PC_DSC_MSK; |
365 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
366 | } | |
367 | } | |
cd28ab6a SH |
368 | } else { |
369 | /* workaround for deviation #4.88 (CRC errors) */ | |
370 | /* disable Automatic Crossover */ | |
371 | ||
372 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
b89165f2 | 373 | } |
cd28ab6a | 374 | |
b89165f2 SH |
375 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
376 | ||
377 | /* special setup for PHY 88E1112 Fiber */ | |
ea76e635 | 378 | if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { |
b89165f2 | 379 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a | 380 | |
b89165f2 SH |
381 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ |
382 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
383 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
384 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
385 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
386 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
387 | ||
388 | if (hw->pmd_type == 'P') { | |
cd28ab6a SH |
389 | /* select page 1 to access Fiber registers */ |
390 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
b89165f2 SH |
391 | |
392 | /* for SFP-module set SIGDET polarity to low */ | |
393 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
394 | ctrl |= PHY_M_FIB_SIGD_POL; | |
34dd962b | 395 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
cd28ab6a | 396 | } |
b89165f2 SH |
397 | |
398 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
cd28ab6a SH |
399 | } |
400 | ||
7800fddc | 401 | ctrl = PHY_CT_RESET; |
cd28ab6a SH |
402 | ct1000 = 0; |
403 | adv = PHY_AN_CSMA; | |
2eaba1a2 | 404 | reg = 0; |
cd28ab6a SH |
405 | |
406 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
b89165f2 | 407 | if (sky2_is_copper(hw)) { |
cd28ab6a SH |
408 | if (sky2->advertising & ADVERTISED_1000baseT_Full) |
409 | ct1000 |= PHY_M_1000C_AFD; | |
410 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
411 | ct1000 |= PHY_M_1000C_AHD; | |
412 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
413 | adv |= PHY_M_AN_100_FD; | |
414 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
415 | adv |= PHY_M_AN_100_HD; | |
416 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
417 | adv |= PHY_M_AN_10_FD; | |
418 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
419 | adv |= PHY_M_AN_10_HD; | |
709c6e7b | 420 | |
16ad91e1 | 421 | adv |= copper_fc_adv[sky2->flow_mode]; |
b89165f2 SH |
422 | } else { /* special defines for FIBER (88E1040S only) */ |
423 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
424 | adv |= PHY_M_AN_1000X_AFD; | |
425 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
426 | adv |= PHY_M_AN_1000X_AHD; | |
cd28ab6a | 427 | |
16ad91e1 | 428 | adv |= fiber_fc_adv[sky2->flow_mode]; |
709c6e7b | 429 | } |
cd28ab6a SH |
430 | |
431 | /* Restart Auto-negotiation */ | |
432 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
433 | } else { | |
434 | /* forced speed/duplex settings */ | |
435 | ct1000 = PHY_M_1000C_MSE; | |
436 | ||
2eaba1a2 SH |
437 | /* Disable auto update for duplex flow control and speed */ |
438 | reg |= GM_GPCR_AU_ALL_DIS; | |
cd28ab6a SH |
439 | |
440 | switch (sky2->speed) { | |
441 | case SPEED_1000: | |
442 | ctrl |= PHY_CT_SP1000; | |
2eaba1a2 | 443 | reg |= GM_GPCR_SPEED_1000; |
cd28ab6a SH |
444 | break; |
445 | case SPEED_100: | |
446 | ctrl |= PHY_CT_SP100; | |
2eaba1a2 | 447 | reg |= GM_GPCR_SPEED_100; |
cd28ab6a SH |
448 | break; |
449 | } | |
450 | ||
2eaba1a2 SH |
451 | if (sky2->duplex == DUPLEX_FULL) { |
452 | reg |= GM_GPCR_DUP_FULL; | |
453 | ctrl |= PHY_CT_DUP_MD; | |
16ad91e1 SH |
454 | } else if (sky2->speed < SPEED_1000) |
455 | sky2->flow_mode = FC_NONE; | |
2eaba1a2 | 456 | |
2eaba1a2 | 457 | |
16ad91e1 | 458 | reg |= gm_fc_disable[sky2->flow_mode]; |
2eaba1a2 SH |
459 | |
460 | /* Forward pause packets to GMAC? */ | |
16ad91e1 | 461 | if (sky2->flow_mode & FC_RX) |
2eaba1a2 SH |
462 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
463 | else | |
464 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
cd28ab6a SH |
465 | } |
466 | ||
2eaba1a2 SH |
467 | gma_write16(hw, port, GM_GP_CTRL, reg); |
468 | ||
05745c4a | 469 | if (hw->flags & SKY2_HW_GIGABIT) |
cd28ab6a SH |
470 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
471 | ||
472 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
473 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
474 | ||
475 | /* Setup Phy LED's */ | |
476 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
477 | ledover = 0; | |
478 | ||
479 | switch (hw->chip_id) { | |
480 | case CHIP_ID_YUKON_FE: | |
481 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
482 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
483 | ||
484 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
485 | ||
486 | /* delete ACT LED control bits */ | |
487 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
488 | /* change ACT LED control to blink mode */ | |
489 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
490 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
491 | break; | |
492 | ||
05745c4a SH |
493 | case CHIP_ID_YUKON_FE_P: |
494 | /* Enable Link Partner Next Page */ | |
495 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
496 | ctrl |= PHY_M_PC_ENA_LIP_NP; | |
497 | ||
498 | /* disable Energy Detect and enable scrambler */ | |
499 | ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); | |
500 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
501 | ||
502 | /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ | |
503 | ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | | |
504 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | | |
505 | PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); | |
506 | ||
507 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
508 | break; | |
509 | ||
cd28ab6a | 510 | case CHIP_ID_YUKON_XL: |
793b883e | 511 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
512 | |
513 | /* select page 3 to access LED control register */ | |
514 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
515 | ||
516 | /* set LED Function Control register */ | |
ed6d32c7 SH |
517 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
518 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
519 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
520 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
521 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
522 | |
523 | /* set Polarity Control register */ | |
524 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
525 | (PHY_M_POLC_LS1_P_MIX(4) | |
526 | PHY_M_POLC_IS0_P_MIX(4) | | |
527 | PHY_M_POLC_LOS_CTRL(2) | | |
528 | PHY_M_POLC_INIT_CTRL(2) | | |
529 | PHY_M_POLC_STA1_CTRL(2) | | |
530 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
531 | |
532 | /* restore page register */ | |
793b883e | 533 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a | 534 | break; |
93745494 | 535 | |
ed6d32c7 | 536 | case CHIP_ID_YUKON_EC_U: |
93745494 | 537 | case CHIP_ID_YUKON_EX: |
ed6d32c7 SH |
538 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
539 | ||
540 | /* select page 3 to access LED control register */ | |
541 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
542 | ||
543 | /* set LED Function Control register */ | |
544 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
545 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
546 | PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ | |
547 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
548 | PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ | |
549 | ||
550 | /* set Blink Rate in LED Timer Control Register */ | |
551 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, | |
552 | ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); | |
553 | /* restore page register */ | |
554 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
555 | break; | |
cd28ab6a SH |
556 | |
557 | default: | |
558 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
559 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
560 | /* turn off the Rx LED (LED_RX) */ | |
0efdf262 | 561 | ledover &= ~PHY_M_LED_MO_RX; |
cd28ab6a SH |
562 | } |
563 | ||
9467a8fc SH |
564 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
565 | hw->chip_rev == CHIP_REV_YU_EC_U_A1) { | |
977bdf06 | 566 | /* apply fixes in PHY AFE */ |
ed6d32c7 SH |
567 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); |
568 | ||
977bdf06 | 569 | /* increase differential signal amplitude in 10BASE-T */ |
ed6d32c7 SH |
570 | gm_phy_write(hw, port, 0x18, 0xaa99); |
571 | gm_phy_write(hw, port, 0x17, 0x2011); | |
cd28ab6a | 572 | |
977bdf06 | 573 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ |
ed6d32c7 SH |
574 | gm_phy_write(hw, port, 0x18, 0xa204); |
575 | gm_phy_write(hw, port, 0x17, 0x2002); | |
977bdf06 SH |
576 | |
577 | /* set page register to 0 */ | |
9467a8fc | 578 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); |
05745c4a SH |
579 | } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
580 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
581 | /* apply workaround for integrated resistors calibration */ | |
582 | gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); | |
583 | gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); | |
93745494 | 584 | } else if (hw->chip_id != CHIP_ID_YUKON_EX) { |
05745c4a | 585 | /* no effect on Yukon-XL */ |
977bdf06 | 586 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); |
cd28ab6a | 587 | |
977bdf06 SH |
588 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { |
589 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
0efdf262 | 590 | ledover |= PHY_M_LED_MO_100; |
977bdf06 | 591 | } |
cd28ab6a | 592 | |
977bdf06 SH |
593 | if (ledover) |
594 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
595 | ||
596 | } | |
2eaba1a2 | 597 | |
d571b694 | 598 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
cd28ab6a SH |
599 | if (sky2->autoneg == AUTONEG_ENABLE) |
600 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
601 | else | |
602 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
603 | } | |
604 | ||
d3bcfbeb SH |
605 | static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) |
606 | { | |
167f53d0 | 607 | struct pci_dev *pdev = hw->pdev; |
d3bcfbeb | 608 | u32 reg1; |
ff35164e SH |
609 | static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; |
610 | static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; | |
d3bcfbeb | 611 | |
167f53d0 | 612 | pci_read_config_dword(pdev, PCI_DEV_REG1, ®1); |
ff35164e | 613 | /* Turn on/off phy power saving */ |
d3bcfbeb | 614 | if (onoff) |
d3bcfbeb SH |
615 | reg1 &= ~phy_power[port]; |
616 | else | |
617 | reg1 |= phy_power[port]; | |
618 | ||
ff35164e SH |
619 | if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
620 | reg1 |= coma_mode[port]; | |
621 | ||
167f53d0 SH |
622 | pci_write_config_dword(pdev, PCI_DEV_REG1, reg1); |
623 | pci_read_config_dword(pdev, PCI_DEV_REG1, ®1); | |
624 | ||
d3bcfbeb SH |
625 | udelay(100); |
626 | } | |
627 | ||
1b537565 SH |
628 | /* Force a renegotiation */ |
629 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
630 | { | |
e07b1aa8 | 631 | spin_lock_bh(&sky2->phy_lock); |
1b537565 | 632 | sky2_phy_init(sky2->hw, sky2->port); |
e07b1aa8 | 633 | spin_unlock_bh(&sky2->phy_lock); |
1b537565 SH |
634 | } |
635 | ||
e3173832 SH |
636 | /* Put device in state to listen for Wake On Lan */ |
637 | static void sky2_wol_init(struct sky2_port *sky2) | |
638 | { | |
639 | struct sky2_hw *hw = sky2->hw; | |
640 | unsigned port = sky2->port; | |
641 | enum flow_control save_mode; | |
642 | u16 ctrl; | |
643 | u32 reg1; | |
644 | ||
645 | /* Bring hardware out of reset */ | |
646 | sky2_write16(hw, B0_CTST, CS_RST_CLR); | |
647 | sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
648 | ||
649 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
650 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
651 | ||
652 | /* Force to 10/100 | |
653 | * sky2_reset will re-enable on resume | |
654 | */ | |
655 | save_mode = sky2->flow_mode; | |
656 | ctrl = sky2->advertising; | |
657 | ||
658 | sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); | |
659 | sky2->flow_mode = FC_NONE; | |
660 | sky2_phy_power(hw, port, 1); | |
661 | sky2_phy_reinit(sky2); | |
662 | ||
663 | sky2->flow_mode = save_mode; | |
664 | sky2->advertising = ctrl; | |
665 | ||
666 | /* Set GMAC to no flow control and auto update for speed/duplex */ | |
667 | gma_write16(hw, port, GM_GP_CTRL, | |
668 | GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| | |
669 | GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); | |
670 | ||
671 | /* Set WOL address */ | |
672 | memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), | |
673 | sky2->netdev->dev_addr, ETH_ALEN); | |
674 | ||
675 | /* Turn on appropriate WOL control bits */ | |
676 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); | |
677 | ctrl = 0; | |
678 | if (sky2->wol & WAKE_PHY) | |
679 | ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; | |
680 | else | |
681 | ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; | |
682 | ||
683 | if (sky2->wol & WAKE_MAGIC) | |
684 | ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; | |
685 | else | |
686 | ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;; | |
687 | ||
688 | ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; | |
689 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); | |
690 | ||
691 | /* Turn on legacy PCI-Express PME mode */ | |
167f53d0 | 692 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); |
e3173832 | 693 | reg1 |= PCI_Y2_PME_LEGACY; |
167f53d0 | 694 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); |
e3173832 SH |
695 | |
696 | /* block receiver */ | |
697 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
698 | ||
699 | } | |
700 | ||
69161611 SH |
701 | static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) |
702 | { | |
05745c4a SH |
703 | struct net_device *dev = hw->dev[port]; |
704 | ||
705 | if (dev->mtu <= ETH_DATA_LEN) | |
69161611 | 706 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
05745c4a SH |
707 | TX_JUMBO_DIS | TX_STFW_ENA); |
708 | ||
709 | else if (hw->chip_id != CHIP_ID_YUKON_EC_U) | |
710 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), | |
711 | TX_STFW_ENA | TX_JUMBO_ENA); | |
712 | else { | |
713 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
714 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), | |
715 | (ECU_JUMBO_WM << 16) | ECU_AE_THR); | |
69161611 | 716 | |
05745c4a SH |
717 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
718 | TX_JUMBO_ENA | TX_STFW_DIS); | |
69161611 | 719 | |
05745c4a SH |
720 | /* Can't do offload because of lack of store/forward */ |
721 | dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM); | |
69161611 SH |
722 | } |
723 | } | |
724 | ||
cd28ab6a SH |
725 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
726 | { | |
727 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
728 | u16 reg; | |
25cccecc | 729 | u32 rx_reg; |
cd28ab6a SH |
730 | int i; |
731 | const u8 *addr = hw->dev[port]->dev_addr; | |
732 | ||
f350339c SH |
733 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
734 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
cd28ab6a SH |
735 | |
736 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
737 | ||
793b883e | 738 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
739 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
740 | /* clear GMAC 1 Control reset */ | |
741 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
742 | do { | |
743 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
744 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
745 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
746 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
747 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
748 | } | |
749 | ||
793b883e | 750 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 751 | |
2eaba1a2 SH |
752 | /* Enable Transmit FIFO Underrun */ |
753 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); | |
754 | ||
e07b1aa8 | 755 | spin_lock_bh(&sky2->phy_lock); |
cd28ab6a | 756 | sky2_phy_init(hw, port); |
e07b1aa8 | 757 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
758 | |
759 | /* MIB clear */ | |
760 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
761 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
762 | ||
43f2f104 SH |
763 | for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) |
764 | gma_read16(hw, port, i); | |
cd28ab6a SH |
765 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
766 | ||
767 | /* transmit control */ | |
768 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
769 | ||
770 | /* receive control reg: unicast + multicast + no FCS */ | |
771 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 772 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
773 | |
774 | /* transmit flow control */ | |
775 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
776 | ||
777 | /* transmit parameter */ | |
778 | gma_write16(hw, port, GM_TX_PARAM, | |
779 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
780 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
781 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
782 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
783 | ||
784 | /* serial mode register */ | |
785 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 786 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 787 | |
6b1a3aef | 788 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
789 | reg |= GM_SMOD_JUMBO_ENA; |
790 | ||
791 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
792 | ||
cd28ab6a SH |
793 | /* virtual address for data */ |
794 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
795 | ||
793b883e SH |
796 | /* physical address: used for pause frames */ |
797 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
798 | ||
799 | /* ignore counter overflows */ | |
cd28ab6a SH |
800 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
801 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
802 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
803 | ||
804 | /* Configure Rx MAC FIFO */ | |
805 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
25cccecc | 806 | rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; |
05745c4a SH |
807 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
808 | hw->chip_id == CHIP_ID_YUKON_FE_P) | |
25cccecc | 809 | rx_reg |= GMF_RX_OVER_ON; |
69161611 | 810 | |
25cccecc | 811 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); |
cd28ab6a | 812 | |
d571b694 | 813 | /* Flush Rx MAC FIFO on any flow control or error */ |
42eeea01 | 814 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
cd28ab6a | 815 | |
8df9a876 | 816 | /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ |
05745c4a SH |
817 | reg = RX_GMF_FL_THR_DEF + 1; |
818 | /* Another magic mystery workaround from sk98lin */ | |
819 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && | |
820 | hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
821 | reg = 0x178; | |
822 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); | |
cd28ab6a SH |
823 | |
824 | /* Configure Tx MAC FIFO */ | |
825 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
826 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 | 827 | |
e0c28116 SH |
828 | /* On chips without ram buffer, pause is controled by MAC level */ |
829 | if (sky2_read8(hw, B2_E_0) == 0) { | |
8df9a876 | 830 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); |
5a5b1ea0 | 831 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); |
b628ed98 | 832 | |
69161611 | 833 | sky2_set_tx_stfwd(hw, port); |
5a5b1ea0 SH |
834 | } |
835 | ||
cd28ab6a SH |
836 | } |
837 | ||
67712901 SH |
838 | /* Assign Ram Buffer allocation to queue */ |
839 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) | |
cd28ab6a | 840 | { |
67712901 SH |
841 | u32 end; |
842 | ||
843 | /* convert from K bytes to qwords used for hw register */ | |
844 | start *= 1024/8; | |
845 | space *= 1024/8; | |
846 | end = start + space - 1; | |
793b883e | 847 | |
cd28ab6a SH |
848 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
849 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
850 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
851 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
852 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
853 | ||
854 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba | 855 | u32 tp = space - space/4; |
793b883e | 856 | |
1c28f6ba SH |
857 | /* On receive queue's set the thresholds |
858 | * give receiver priority when > 3/4 full | |
859 | * send pause when down to 2K | |
860 | */ | |
861 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
862 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 863 | |
1c28f6ba SH |
864 | tp = space - 2048/8; |
865 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); | |
866 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
867 | } else { |
868 | /* Enable store & forward on Tx queue's because | |
869 | * Tx FIFO is only 1K on Yukon | |
870 | */ | |
871 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
872 | } | |
873 | ||
874 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 875 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
876 | } |
877 | ||
cd28ab6a | 878 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 879 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
880 | { |
881 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
882 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
883 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 884 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
885 | } |
886 | ||
cd28ab6a SH |
887 | /* Setup prefetch unit registers. This is the interface between |
888 | * hardware and driver list elements | |
889 | */ | |
8cc048e3 | 890 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
cd28ab6a SH |
891 | u64 addr, u32 last) |
892 | { | |
cd28ab6a SH |
893 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
894 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
895 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
896 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
897 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
898 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
899 | |
900 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
901 | } |
902 | ||
793b883e SH |
903 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
904 | { | |
905 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
906 | ||
cb5d9547 | 907 | sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE); |
291ea614 | 908 | le->ctrl = 0; |
793b883e SH |
909 | return le; |
910 | } | |
cd28ab6a | 911 | |
88f5f0ca SH |
912 | static void tx_init(struct sky2_port *sky2) |
913 | { | |
914 | struct sky2_tx_le *le; | |
915 | ||
916 | sky2->tx_prod = sky2->tx_cons = 0; | |
917 | sky2->tx_tcpsum = 0; | |
918 | sky2->tx_last_mss = 0; | |
919 | ||
920 | le = get_tx_le(sky2); | |
921 | le->addr = 0; | |
922 | le->opcode = OP_ADDR64 | HW_OWNER; | |
923 | sky2->tx_addr64 = 0; | |
924 | } | |
925 | ||
291ea614 SH |
926 | static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2, |
927 | struct sky2_tx_le *le) | |
928 | { | |
929 | return sky2->tx_ring + (le - sky2->tx_le); | |
930 | } | |
931 | ||
290d4de5 SH |
932 | /* Update chip's next pointer */ |
933 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) | |
cd28ab6a | 934 | { |
50432cb5 | 935 | /* Make sure write' to descriptors are complete before we tell hardware */ |
762c2de2 | 936 | wmb(); |
50432cb5 SH |
937 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
938 | ||
939 | /* Synchronize I/O on since next processor may write to tail */ | |
940 | mmiowb(); | |
cd28ab6a SH |
941 | } |
942 | ||
793b883e | 943 | |
cd28ab6a SH |
944 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
945 | { | |
946 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
cb5d9547 | 947 | sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); |
291ea614 | 948 | le->ctrl = 0; |
cd28ab6a SH |
949 | return le; |
950 | } | |
951 | ||
14d0263f SH |
952 | /* Build description to hardware for one receive segment */ |
953 | static void sky2_rx_add(struct sky2_port *sky2, u8 op, | |
954 | dma_addr_t map, unsigned len) | |
cd28ab6a SH |
955 | { |
956 | struct sky2_rx_le *le; | |
36eb0c71 | 957 | u32 hi = upper_32_bits(map); |
cd28ab6a | 958 | |
793b883e | 959 | if (sky2->rx_addr64 != hi) { |
cd28ab6a | 960 | le = sky2_next_rx(sky2); |
793b883e | 961 | le->addr = cpu_to_le32(hi); |
cd28ab6a | 962 | le->opcode = OP_ADDR64 | HW_OWNER; |
36eb0c71 | 963 | sky2->rx_addr64 = upper_32_bits(map + len); |
cd28ab6a | 964 | } |
793b883e | 965 | |
cd28ab6a | 966 | le = sky2_next_rx(sky2); |
734d1868 SH |
967 | le->addr = cpu_to_le32((u32) map); |
968 | le->length = cpu_to_le16(len); | |
14d0263f | 969 | le->opcode = op | HW_OWNER; |
cd28ab6a SH |
970 | } |
971 | ||
14d0263f SH |
972 | /* Build description to hardware for one possibly fragmented skb */ |
973 | static void sky2_rx_submit(struct sky2_port *sky2, | |
974 | const struct rx_ring_info *re) | |
975 | { | |
976 | int i; | |
977 | ||
978 | sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); | |
979 | ||
980 | for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) | |
981 | sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); | |
982 | } | |
983 | ||
984 | ||
985 | static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, | |
986 | unsigned size) | |
987 | { | |
988 | struct sk_buff *skb = re->skb; | |
989 | int i; | |
990 | ||
991 | re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); | |
992 | pci_unmap_len_set(re, data_size, size); | |
993 | ||
994 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) | |
995 | re->frag_addr[i] = pci_map_page(pdev, | |
996 | skb_shinfo(skb)->frags[i].page, | |
997 | skb_shinfo(skb)->frags[i].page_offset, | |
998 | skb_shinfo(skb)->frags[i].size, | |
999 | PCI_DMA_FROMDEVICE); | |
1000 | } | |
1001 | ||
1002 | static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) | |
1003 | { | |
1004 | struct sk_buff *skb = re->skb; | |
1005 | int i; | |
1006 | ||
1007 | pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size), | |
1008 | PCI_DMA_FROMDEVICE); | |
1009 | ||
1010 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) | |
1011 | pci_unmap_page(pdev, re->frag_addr[i], | |
1012 | skb_shinfo(skb)->frags[i].size, | |
1013 | PCI_DMA_FROMDEVICE); | |
1014 | } | |
793b883e | 1015 | |
cd28ab6a SH |
1016 | /* Tell chip where to start receive checksum. |
1017 | * Actually has two checksums, but set both same to avoid possible byte | |
1018 | * order problems. | |
1019 | */ | |
793b883e | 1020 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a | 1021 | { |
ea76e635 | 1022 | struct sky2_rx_le *le = sky2_next_rx(sky2); |
793b883e | 1023 | |
ea76e635 SH |
1024 | le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); |
1025 | le->ctrl = 0; | |
1026 | le->opcode = OP_TCPSTART | HW_OWNER; | |
cd28ab6a | 1027 | |
ea76e635 SH |
1028 | sky2_write32(sky2->hw, |
1029 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
1030 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
1031 | } |
1032 | ||
6b1a3aef SH |
1033 | /* |
1034 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
1035 | * reach the end of packet and since we can't make sure that we have | |
1036 | * incoming data, we must reset the BMU while it is not doing a DMA | |
1037 | * transfer. Since it is possible that the RX path is still active, | |
1038 | * the RX RAM buffer will be stopped first, so any possible incoming | |
1039 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
1040 | * BMU is polled until any DMA in progress is ended and only then it | |
1041 | * will be reset. | |
1042 | */ | |
1043 | static void sky2_rx_stop(struct sky2_port *sky2) | |
1044 | { | |
1045 | struct sky2_hw *hw = sky2->hw; | |
1046 | unsigned rxq = rxqaddr[sky2->port]; | |
1047 | int i; | |
1048 | ||
1049 | /* disable the RAM Buffer receive queue */ | |
1050 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
1051 | ||
1052 | for (i = 0; i < 0xffff; i++) | |
1053 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
1054 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
1055 | goto stopped; | |
1056 | ||
1057 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
1058 | sky2->netdev->name); | |
1059 | stopped: | |
1060 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
1061 | ||
1062 | /* reset the Rx prefetch unit */ | |
1063 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
50432cb5 | 1064 | mmiowb(); |
6b1a3aef | 1065 | } |
793b883e | 1066 | |
d571b694 | 1067 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
1068 | static void sky2_rx_clean(struct sky2_port *sky2) |
1069 | { | |
1070 | unsigned i; | |
1071 | ||
1072 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 1073 | for (i = 0; i < sky2->rx_pending; i++) { |
291ea614 | 1074 | struct rx_ring_info *re = sky2->rx_ring + i; |
cd28ab6a SH |
1075 | |
1076 | if (re->skb) { | |
14d0263f | 1077 | sky2_rx_unmap_skb(sky2->hw->pdev, re); |
cd28ab6a SH |
1078 | kfree_skb(re->skb); |
1079 | re->skb = NULL; | |
1080 | } | |
1081 | } | |
1082 | } | |
1083 | ||
ef743d33 SH |
1084 | /* Basic MII support */ |
1085 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1086 | { | |
1087 | struct mii_ioctl_data *data = if_mii(ifr); | |
1088 | struct sky2_port *sky2 = netdev_priv(dev); | |
1089 | struct sky2_hw *hw = sky2->hw; | |
1090 | int err = -EOPNOTSUPP; | |
1091 | ||
1092 | if (!netif_running(dev)) | |
1093 | return -ENODEV; /* Phy still in reset */ | |
1094 | ||
d89e1343 | 1095 | switch (cmd) { |
ef743d33 SH |
1096 | case SIOCGMIIPHY: |
1097 | data->phy_id = PHY_ADDR_MARV; | |
1098 | ||
1099 | /* fallthru */ | |
1100 | case SIOCGMIIREG: { | |
1101 | u16 val = 0; | |
91c86df5 | 1102 | |
e07b1aa8 | 1103 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 | 1104 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
e07b1aa8 | 1105 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 1106 | |
ef743d33 SH |
1107 | data->val_out = val; |
1108 | break; | |
1109 | } | |
1110 | ||
1111 | case SIOCSMIIREG: | |
1112 | if (!capable(CAP_NET_ADMIN)) | |
1113 | return -EPERM; | |
1114 | ||
e07b1aa8 | 1115 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 SH |
1116 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
1117 | data->val_in); | |
e07b1aa8 | 1118 | spin_unlock_bh(&sky2->phy_lock); |
ef743d33 SH |
1119 | break; |
1120 | } | |
1121 | return err; | |
1122 | } | |
1123 | ||
d1f13708 SH |
1124 | #ifdef SKY2_VLAN_TAG_USED |
1125 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
1126 | { | |
1127 | struct sky2_port *sky2 = netdev_priv(dev); | |
1128 | struct sky2_hw *hw = sky2->hw; | |
1129 | u16 port = sky2->port; | |
d1f13708 | 1130 | |
2bb8c262 | 1131 | netif_tx_lock_bh(dev); |
bea3348e | 1132 | napi_disable(&hw->napi); |
d1f13708 | 1133 | |
d1f13708 | 1134 | sky2->vlgrp = grp; |
3d4e66f5 SH |
1135 | if (grp) { |
1136 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), | |
1137 | RX_VLAN_STRIP_ON); | |
1138 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), | |
1139 | TX_VLAN_TAG_ON); | |
1140 | } else { | |
1141 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), | |
1142 | RX_VLAN_STRIP_OFF); | |
1143 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), | |
1144 | TX_VLAN_TAG_OFF); | |
1145 | } | |
d1f13708 | 1146 | |
bea3348e | 1147 | napi_enable(&hw->napi); |
2bb8c262 | 1148 | netif_tx_unlock_bh(dev); |
d1f13708 SH |
1149 | } |
1150 | #endif | |
1151 | ||
82788c7a | 1152 | /* |
14d0263f SH |
1153 | * Allocate an skb for receiving. If the MTU is large enough |
1154 | * make the skb non-linear with a fragment list of pages. | |
1155 | * | |
82788c7a SH |
1156 | * It appears the hardware has a bug in the FIFO logic that |
1157 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
497d7c86 SH |
1158 | * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is |
1159 | * aligned except if slab debugging is enabled. | |
82788c7a | 1160 | */ |
14d0263f | 1161 | static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2) |
82788c7a SH |
1162 | { |
1163 | struct sk_buff *skb; | |
14d0263f SH |
1164 | unsigned long p; |
1165 | int i; | |
82788c7a | 1166 | |
14d0263f SH |
1167 | skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN); |
1168 | if (!skb) | |
1169 | goto nomem; | |
1170 | ||
1171 | p = (unsigned long) skb->data; | |
1172 | skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); | |
1173 | ||
1174 | for (i = 0; i < sky2->rx_nfrags; i++) { | |
1175 | struct page *page = alloc_page(GFP_ATOMIC); | |
1176 | ||
1177 | if (!page) | |
1178 | goto free_partial; | |
1179 | skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); | |
82788c7a SH |
1180 | } |
1181 | ||
1182 | return skb; | |
14d0263f SH |
1183 | free_partial: |
1184 | kfree_skb(skb); | |
1185 | nomem: | |
1186 | return NULL; | |
82788c7a SH |
1187 | } |
1188 | ||
55c9dd35 SH |
1189 | static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) |
1190 | { | |
1191 | sky2_put_idx(sky2->hw, rxq, sky2->rx_put); | |
1192 | } | |
1193 | ||
cd28ab6a SH |
1194 | /* |
1195 | * Allocate and setup receiver buffer pool. | |
14d0263f SH |
1196 | * Normal case this ends up creating one list element for skb |
1197 | * in the receive ring. Worst case if using large MTU and each | |
1198 | * allocation falls on a different 64 bit region, that results | |
1199 | * in 6 list elements per ring entry. | |
1200 | * One element is used for checksum enable/disable, and one | |
1201 | * extra to avoid wrap. | |
cd28ab6a | 1202 | */ |
6b1a3aef | 1203 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 1204 | { |
6b1a3aef | 1205 | struct sky2_hw *hw = sky2->hw; |
14d0263f | 1206 | struct rx_ring_info *re; |
6b1a3aef | 1207 | unsigned rxq = rxqaddr[sky2->port]; |
14d0263f | 1208 | unsigned i, size, space, thresh; |
cd28ab6a | 1209 | |
6b1a3aef | 1210 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 1211 | sky2_qset(hw, rxq); |
977bdf06 | 1212 | |
c3905bc4 SH |
1213 | /* On PCI express lowering the watermark gives better performance */ |
1214 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) | |
1215 | sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); | |
1216 | ||
1217 | /* These chips have no ram buffer? | |
1218 | * MAC Rx RAM Read is controlled by hardware */ | |
8df9a876 | 1219 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
c3905bc4 SH |
1220 | (hw->chip_rev == CHIP_REV_YU_EC_U_A1 |
1221 | || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) | |
f449c7c1 | 1222 | sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); |
977bdf06 | 1223 | |
6b1a3aef SH |
1224 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
1225 | ||
ea76e635 SH |
1226 | if (!(hw->flags & SKY2_HW_NEW_LE)) |
1227 | rx_set_checksum(sky2); | |
14d0263f SH |
1228 | |
1229 | /* Space needed for frame data + headers rounded up */ | |
f957da2a | 1230 | size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); |
14d0263f SH |
1231 | |
1232 | /* Stopping point for hardware truncation */ | |
1233 | thresh = (size - 8) / sizeof(u32); | |
1234 | ||
1235 | /* Account for overhead of skb - to avoid order > 0 allocation */ | |
1236 | space = SKB_DATA_ALIGN(size) + NET_SKB_PAD | |
1237 | + sizeof(struct skb_shared_info); | |
1238 | ||
1239 | sky2->rx_nfrags = space >> PAGE_SHIFT; | |
1240 | BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); | |
1241 | ||
1242 | if (sky2->rx_nfrags != 0) { | |
1243 | /* Compute residue after pages */ | |
1244 | space = sky2->rx_nfrags << PAGE_SHIFT; | |
1245 | ||
1246 | if (space < size) | |
1247 | size -= space; | |
1248 | else | |
1249 | size = 0; | |
1250 | ||
1251 | /* Optimize to handle small packets and headers */ | |
1252 | if (size < copybreak) | |
1253 | size = copybreak; | |
1254 | if (size < ETH_HLEN) | |
1255 | size = ETH_HLEN; | |
1256 | } | |
1257 | sky2->rx_data_size = size; | |
1258 | ||
1259 | /* Fill Rx ring */ | |
793b883e | 1260 | for (i = 0; i < sky2->rx_pending; i++) { |
14d0263f | 1261 | re = sky2->rx_ring + i; |
cd28ab6a | 1262 | |
14d0263f | 1263 | re->skb = sky2_rx_alloc(sky2); |
cd28ab6a SH |
1264 | if (!re->skb) |
1265 | goto nomem; | |
1266 | ||
14d0263f SH |
1267 | sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size); |
1268 | sky2_rx_submit(sky2, re); | |
cd28ab6a SH |
1269 | } |
1270 | ||
a1433ac4 SH |
1271 | /* |
1272 | * The receiver hangs if it receives frames larger than the | |
1273 | * packet buffer. As a workaround, truncate oversize frames, but | |
1274 | * the register is limited to 9 bits, so if you do frames > 2052 | |
1275 | * you better get the MTU right! | |
1276 | */ | |
a1433ac4 SH |
1277 | if (thresh > 0x1ff) |
1278 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); | |
1279 | else { | |
1280 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); | |
1281 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); | |
1282 | } | |
1283 | ||
6b1a3aef | 1284 | /* Tell chip about available buffers */ |
55c9dd35 | 1285 | sky2_rx_update(sky2, rxq); |
cd28ab6a SH |
1286 | return 0; |
1287 | nomem: | |
1288 | sky2_rx_clean(sky2); | |
1289 | return -ENOMEM; | |
1290 | } | |
1291 | ||
1292 | /* Bring up network interface. */ | |
1293 | static int sky2_up(struct net_device *dev) | |
1294 | { | |
1295 | struct sky2_port *sky2 = netdev_priv(dev); | |
1296 | struct sky2_hw *hw = sky2->hw; | |
1297 | unsigned port = sky2->port; | |
e0c28116 | 1298 | u32 imask, ramsize; |
ee7abb04 | 1299 | int cap, err = -ENOMEM; |
843a46f4 | 1300 | struct net_device *otherdev = hw->dev[sky2->port^1]; |
cd28ab6a | 1301 | |
ee7abb04 SH |
1302 | /* |
1303 | * On dual port PCI-X card, there is an problem where status | |
1304 | * can be received out of order due to split transactions | |
843a46f4 | 1305 | */ |
ee7abb04 SH |
1306 | if (otherdev && netif_running(otherdev) && |
1307 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { | |
1308 | struct sky2_port *osky2 = netdev_priv(otherdev); | |
1309 | u16 cmd; | |
1310 | ||
167f53d0 | 1311 | pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd); |
ee7abb04 | 1312 | cmd &= ~PCI_X_CMD_MAX_SPLIT; |
167f53d0 | 1313 | pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd); |
ee7abb04 SH |
1314 | |
1315 | sky2->rx_csum = 0; | |
1316 | osky2->rx_csum = 0; | |
1317 | } | |
843a46f4 | 1318 | |
cd28ab6a SH |
1319 | if (netif_msg_ifup(sky2)) |
1320 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
1321 | ||
55d7b4e6 SH |
1322 | netif_carrier_off(dev); |
1323 | ||
cd28ab6a SH |
1324 | /* must be power of 2 */ |
1325 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
1326 | TX_RING_SIZE * |
1327 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
1328 | &sky2->tx_le_map); |
1329 | if (!sky2->tx_le) | |
1330 | goto err_out; | |
1331 | ||
6cdbbdf3 | 1332 | sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), |
cd28ab6a SH |
1333 | GFP_KERNEL); |
1334 | if (!sky2->tx_ring) | |
1335 | goto err_out; | |
88f5f0ca SH |
1336 | |
1337 | tx_init(sky2); | |
cd28ab6a SH |
1338 | |
1339 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
1340 | &sky2->rx_le_map); | |
1341 | if (!sky2->rx_le) | |
1342 | goto err_out; | |
1343 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1344 | ||
291ea614 | 1345 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), |
cd28ab6a SH |
1346 | GFP_KERNEL); |
1347 | if (!sky2->rx_ring) | |
1348 | goto err_out; | |
1349 | ||
d3bcfbeb SH |
1350 | sky2_phy_power(hw, port, 1); |
1351 | ||
cd28ab6a SH |
1352 | sky2_mac_init(hw, port); |
1353 | ||
e0c28116 SH |
1354 | /* Register is number of 4K blocks on internal RAM buffer. */ |
1355 | ramsize = sky2_read8(hw, B2_E_0) * 4; | |
1356 | if (ramsize > 0) { | |
67712901 | 1357 | u32 rxspace; |
cd28ab6a | 1358 | |
e0c28116 | 1359 | pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize); |
67712901 SH |
1360 | if (ramsize < 16) |
1361 | rxspace = ramsize / 2; | |
1362 | else | |
1363 | rxspace = 8 + (2*(ramsize - 16))/3; | |
cd28ab6a | 1364 | |
67712901 SH |
1365 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1366 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); | |
1367 | ||
1368 | /* Make sure SyncQ is disabled */ | |
1369 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1370 | RB_RST_SET); | |
1371 | } | |
793b883e | 1372 | |
af4ed7e6 | 1373 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 | 1374 | |
69161611 SH |
1375 | /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ |
1376 | if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) | |
1377 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); | |
1378 | ||
977bdf06 | 1379 | /* Set almost empty threshold */ |
c2716fb4 SH |
1380 | if (hw->chip_id == CHIP_ID_YUKON_EC_U |
1381 | && hw->chip_rev == CHIP_REV_YU_EC_U_A0) | |
b628ed98 | 1382 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); |
5a5b1ea0 | 1383 | |
6b1a3aef SH |
1384 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1385 | TX_RING_SIZE - 1); | |
cd28ab6a | 1386 | |
6b1a3aef | 1387 | err = sky2_rx_start(sky2); |
6de16237 | 1388 | if (err) |
cd28ab6a SH |
1389 | goto err_out; |
1390 | ||
cd28ab6a | 1391 | /* Enable interrupts from phy/mac for port */ |
e07b1aa8 | 1392 | imask = sky2_read32(hw, B0_IMSK); |
f4ea431b | 1393 | imask |= portirq_msk[port]; |
e07b1aa8 SH |
1394 | sky2_write32(hw, B0_IMSK, imask); |
1395 | ||
cd28ab6a SH |
1396 | return 0; |
1397 | ||
1398 | err_out: | |
1b537565 | 1399 | if (sky2->rx_le) { |
cd28ab6a SH |
1400 | pci_free_consistent(hw->pdev, RX_LE_BYTES, |
1401 | sky2->rx_le, sky2->rx_le_map); | |
1b537565 SH |
1402 | sky2->rx_le = NULL; |
1403 | } | |
1404 | if (sky2->tx_le) { | |
cd28ab6a SH |
1405 | pci_free_consistent(hw->pdev, |
1406 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1407 | sky2->tx_le, sky2->tx_le_map); | |
1b537565 SH |
1408 | sky2->tx_le = NULL; |
1409 | } | |
1410 | kfree(sky2->tx_ring); | |
1411 | kfree(sky2->rx_ring); | |
cd28ab6a | 1412 | |
1b537565 SH |
1413 | sky2->tx_ring = NULL; |
1414 | sky2->rx_ring = NULL; | |
cd28ab6a SH |
1415 | return err; |
1416 | } | |
1417 | ||
793b883e SH |
1418 | /* Modular subtraction in ring */ |
1419 | static inline int tx_dist(unsigned tail, unsigned head) | |
1420 | { | |
cb5d9547 | 1421 | return (head - tail) & (TX_RING_SIZE - 1); |
793b883e | 1422 | } |
cd28ab6a | 1423 | |
793b883e SH |
1424 | /* Number of list elements available for next tx */ |
1425 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1426 | { |
793b883e | 1427 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
1428 | } |
1429 | ||
793b883e | 1430 | /* Estimate of number of transmit list elements required */ |
28bd181a | 1431 | static unsigned tx_le_req(const struct sk_buff *skb) |
cd28ab6a | 1432 | { |
793b883e SH |
1433 | unsigned count; |
1434 | ||
1435 | count = sizeof(dma_addr_t) / sizeof(u32); | |
1436 | count += skb_shinfo(skb)->nr_frags * count; | |
1437 | ||
89114afd | 1438 | if (skb_is_gso(skb)) |
793b883e SH |
1439 | ++count; |
1440 | ||
84fa7933 | 1441 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
793b883e SH |
1442 | ++count; |
1443 | ||
1444 | return count; | |
cd28ab6a SH |
1445 | } |
1446 | ||
793b883e SH |
1447 | /* |
1448 | * Put one packet in ring for transmit. | |
1449 | * A single packet can generate multiple list elements, and | |
1450 | * the number of ring elements will probably be less than the number | |
1451 | * of list elements used. | |
1452 | */ | |
cd28ab6a SH |
1453 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
1454 | { | |
1455 | struct sky2_port *sky2 = netdev_priv(dev); | |
1456 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1457 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1458 | struct tx_ring_info *re; |
cd28ab6a SH |
1459 | unsigned i, len; |
1460 | dma_addr_t mapping; | |
1461 | u32 addr64; | |
1462 | u16 mss; | |
1463 | u8 ctrl; | |
1464 | ||
2bb8c262 SH |
1465 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) |
1466 | return NETDEV_TX_BUSY; | |
cd28ab6a | 1467 | |
793b883e | 1468 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
1469 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
1470 | dev->name, sky2->tx_prod, skb->len); | |
1471 | ||
cd28ab6a SH |
1472 | len = skb_headlen(skb); |
1473 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
36eb0c71 | 1474 | addr64 = upper_32_bits(mapping); |
793b883e | 1475 | |
a018e330 | 1476 | /* Send high bits if changed or crosses boundary */ |
36eb0c71 SH |
1477 | if (addr64 != sky2->tx_addr64 || |
1478 | upper_32_bits(mapping + len) != sky2->tx_addr64) { | |
793b883e | 1479 | le = get_tx_le(sky2); |
f65b138c | 1480 | le->addr = cpu_to_le32(addr64); |
793b883e | 1481 | le->opcode = OP_ADDR64 | HW_OWNER; |
36eb0c71 | 1482 | sky2->tx_addr64 = upper_32_bits(mapping + len); |
793b883e | 1483 | } |
cd28ab6a SH |
1484 | |
1485 | /* Check for TCP Segmentation Offload */ | |
7967168c | 1486 | mss = skb_shinfo(skb)->gso_size; |
793b883e | 1487 | if (mss != 0) { |
ea76e635 SH |
1488 | |
1489 | if (!(hw->flags & SKY2_HW_NEW_LE)) | |
69161611 SH |
1490 | mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); |
1491 | ||
1492 | if (mss != sky2->tx_last_mss) { | |
1493 | le = get_tx_le(sky2); | |
1494 | le->addr = cpu_to_le32(mss); | |
ea76e635 SH |
1495 | |
1496 | if (hw->flags & SKY2_HW_NEW_LE) | |
69161611 SH |
1497 | le->opcode = OP_MSS | HW_OWNER; |
1498 | else | |
1499 | le->opcode = OP_LRGLEN | HW_OWNER; | |
e07560cd SH |
1500 | sky2->tx_last_mss = mss; |
1501 | } | |
cd28ab6a SH |
1502 | } |
1503 | ||
cd28ab6a | 1504 | ctrl = 0; |
d1f13708 SH |
1505 | #ifdef SKY2_VLAN_TAG_USED |
1506 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ | |
1507 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | |
1508 | if (!le) { | |
1509 | le = get_tx_le(sky2); | |
f65b138c | 1510 | le->addr = 0; |
d1f13708 | 1511 | le->opcode = OP_VLAN|HW_OWNER; |
d1f13708 SH |
1512 | } else |
1513 | le->opcode |= OP_VLAN; | |
1514 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1515 | ctrl |= INS_VLAN; | |
1516 | } | |
1517 | #endif | |
1518 | ||
1519 | /* Handle TCP checksum offload */ | |
84fa7933 | 1520 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
69161611 | 1521 | /* On Yukon EX (some versions) encoding change. */ |
ea76e635 | 1522 | if (hw->flags & SKY2_HW_AUTO_TX_SUM) |
69161611 SH |
1523 | ctrl |= CALSUM; /* auto checksum */ |
1524 | else { | |
1525 | const unsigned offset = skb_transport_offset(skb); | |
1526 | u32 tcpsum; | |
1527 | ||
1528 | tcpsum = offset << 16; /* sum start */ | |
1529 | tcpsum |= offset + skb->csum_offset; /* sum write */ | |
1530 | ||
1531 | ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1532 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) | |
1533 | ctrl |= UDPTCP; | |
1534 | ||
1535 | if (tcpsum != sky2->tx_tcpsum) { | |
1536 | sky2->tx_tcpsum = tcpsum; | |
1537 | ||
1538 | le = get_tx_le(sky2); | |
1539 | le->addr = cpu_to_le32(tcpsum); | |
1540 | le->length = 0; /* initial checksum value */ | |
1541 | le->ctrl = 1; /* one packet */ | |
1542 | le->opcode = OP_TCPLISW | HW_OWNER; | |
1543 | } | |
1d179332 | 1544 | } |
cd28ab6a SH |
1545 | } |
1546 | ||
1547 | le = get_tx_le(sky2); | |
f65b138c | 1548 | le->addr = cpu_to_le32((u32) mapping); |
cd28ab6a SH |
1549 | le->length = cpu_to_le16(len); |
1550 | le->ctrl = ctrl; | |
793b883e | 1551 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1552 | |
291ea614 | 1553 | re = tx_le_re(sky2, le); |
cd28ab6a | 1554 | re->skb = skb; |
6cdbbdf3 | 1555 | pci_unmap_addr_set(re, mapaddr, mapping); |
291ea614 | 1556 | pci_unmap_len_set(re, maplen, len); |
cd28ab6a SH |
1557 | |
1558 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
291ea614 | 1559 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
cd28ab6a SH |
1560 | |
1561 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1562 | frag->size, PCI_DMA_TODEVICE); | |
36eb0c71 | 1563 | addr64 = upper_32_bits(mapping); |
793b883e SH |
1564 | if (addr64 != sky2->tx_addr64) { |
1565 | le = get_tx_le(sky2); | |
f65b138c | 1566 | le->addr = cpu_to_le32(addr64); |
793b883e SH |
1567 | le->ctrl = 0; |
1568 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1569 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1570 | } |
1571 | ||
1572 | le = get_tx_le(sky2); | |
f65b138c | 1573 | le->addr = cpu_to_le32((u32) mapping); |
cd28ab6a SH |
1574 | le->length = cpu_to_le16(frag->size); |
1575 | le->ctrl = ctrl; | |
793b883e | 1576 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1577 | |
291ea614 SH |
1578 | re = tx_le_re(sky2, le); |
1579 | re->skb = skb; | |
1580 | pci_unmap_addr_set(re, mapaddr, mapping); | |
1581 | pci_unmap_len_set(re, maplen, frag->size); | |
cd28ab6a | 1582 | } |
6cdbbdf3 | 1583 | |
cd28ab6a SH |
1584 | le->ctrl |= EOP; |
1585 | ||
97bda706 SH |
1586 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
1587 | netif_stop_queue(dev); | |
b19666d9 | 1588 | |
290d4de5 | 1589 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); |
cd28ab6a | 1590 | |
cd28ab6a SH |
1591 | dev->trans_start = jiffies; |
1592 | return NETDEV_TX_OK; | |
1593 | } | |
1594 | ||
cd28ab6a | 1595 | /* |
793b883e SH |
1596 | * Free ring elements from starting at tx_cons until "done" |
1597 | * | |
1598 | * NB: the hardware will tell us about partial completion of multi-part | |
291ea614 | 1599 | * buffers so make sure not to free skb to early. |
cd28ab6a | 1600 | */ |
d11c13e7 | 1601 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1602 | { |
d11c13e7 | 1603 | struct net_device *dev = sky2->netdev; |
af2a58ac | 1604 | struct pci_dev *pdev = sky2->hw->pdev; |
291ea614 | 1605 | unsigned idx; |
cd28ab6a | 1606 | |
0e3ff6aa | 1607 | BUG_ON(done >= TX_RING_SIZE); |
2224795d | 1608 | |
291ea614 SH |
1609 | for (idx = sky2->tx_cons; idx != done; |
1610 | idx = RING_NEXT(idx, TX_RING_SIZE)) { | |
1611 | struct sky2_tx_le *le = sky2->tx_le + idx; | |
1612 | struct tx_ring_info *re = sky2->tx_ring + idx; | |
1613 | ||
1614 | switch(le->opcode & ~HW_OWNER) { | |
1615 | case OP_LARGESEND: | |
1616 | case OP_PACKET: | |
1617 | pci_unmap_single(pdev, | |
1618 | pci_unmap_addr(re, mapaddr), | |
1619 | pci_unmap_len(re, maplen), | |
1620 | PCI_DMA_TODEVICE); | |
af2a58ac | 1621 | break; |
291ea614 SH |
1622 | case OP_BUFFER: |
1623 | pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr), | |
1624 | pci_unmap_len(re, maplen), | |
734d1868 | 1625 | PCI_DMA_TODEVICE); |
291ea614 SH |
1626 | break; |
1627 | } | |
1628 | ||
1629 | if (le->ctrl & EOP) { | |
1630 | if (unlikely(netif_msg_tx_done(sky2))) | |
1631 | printk(KERN_DEBUG "%s: tx done %u\n", | |
1632 | dev->name, idx); | |
3cf26753 | 1633 | |
7138a0f5 SH |
1634 | dev->stats.tx_packets++; |
1635 | dev->stats.tx_bytes += re->skb->len; | |
2bf56fe2 | 1636 | |
794b2bd2 | 1637 | dev_kfree_skb_any(re->skb); |
3cf26753 | 1638 | sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE); |
cd28ab6a | 1639 | } |
793b883e | 1640 | } |
793b883e | 1641 | |
291ea614 | 1642 | sky2->tx_cons = idx; |
50432cb5 SH |
1643 | smp_mb(); |
1644 | ||
22e11703 | 1645 | if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) |
cd28ab6a | 1646 | netif_wake_queue(dev); |
cd28ab6a SH |
1647 | } |
1648 | ||
1649 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
2bb8c262 | 1650 | static void sky2_tx_clean(struct net_device *dev) |
cd28ab6a | 1651 | { |
2bb8c262 SH |
1652 | struct sky2_port *sky2 = netdev_priv(dev); |
1653 | ||
1654 | netif_tx_lock_bh(dev); | |
d11c13e7 | 1655 | sky2_tx_complete(sky2, sky2->tx_prod); |
2bb8c262 | 1656 | netif_tx_unlock_bh(dev); |
cd28ab6a SH |
1657 | } |
1658 | ||
1659 | /* Network shutdown */ | |
1660 | static int sky2_down(struct net_device *dev) | |
1661 | { | |
1662 | struct sky2_port *sky2 = netdev_priv(dev); | |
1663 | struct sky2_hw *hw = sky2->hw; | |
1664 | unsigned port = sky2->port; | |
1665 | u16 ctrl; | |
e07b1aa8 | 1666 | u32 imask; |
cd28ab6a | 1667 | |
1b537565 SH |
1668 | /* Never really got started! */ |
1669 | if (!sky2->tx_le) | |
1670 | return 0; | |
1671 | ||
cd28ab6a SH |
1672 | if (netif_msg_ifdown(sky2)) |
1673 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1674 | ||
018d1c66 | 1675 | /* Stop more packets from being queued */ |
cd28ab6a SH |
1676 | netif_stop_queue(dev); |
1677 | ||
ebc646f6 SH |
1678 | /* Disable port IRQ */ |
1679 | imask = sky2_read32(hw, B0_IMSK); | |
1680 | imask &= ~portirq_msk[port]; | |
1681 | sky2_write32(hw, B0_IMSK, imask); | |
1682 | ||
6de16237 SH |
1683 | synchronize_irq(hw->pdev->irq); |
1684 | ||
d3bcfbeb | 1685 | sky2_gmac_reset(hw, port); |
793b883e | 1686 | |
cd28ab6a SH |
1687 | /* Stop transmitter */ |
1688 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1689 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1690 | ||
1691 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1692 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1693 | |
1694 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1695 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1696 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1697 | ||
6de16237 SH |
1698 | /* Make sure no packets are pending */ |
1699 | napi_synchronize(&hw->napi); | |
1700 | ||
cd28ab6a SH |
1701 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
1702 | ||
1703 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1704 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1705 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1706 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1707 | ||
1708 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1709 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1710 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1711 | ||
1712 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1713 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1714 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1715 | ||
1716 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1717 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1718 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1719 | |
1720 | /* Reset the Tx prefetch units */ | |
1721 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1722 | PREF_UNIT_RST_SET); | |
1723 | ||
1724 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1725 | ||
6b1a3aef | 1726 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1727 | |
1728 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1729 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1730 | ||
d3bcfbeb SH |
1731 | sky2_phy_power(hw, port, 0); |
1732 | ||
55d7b4e6 SH |
1733 | netif_carrier_off(dev); |
1734 | ||
d571b694 | 1735 | /* turn off LED's */ |
cd28ab6a SH |
1736 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1737 | ||
2bb8c262 | 1738 | sky2_tx_clean(dev); |
cd28ab6a SH |
1739 | sky2_rx_clean(sky2); |
1740 | ||
1741 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1742 | sky2->rx_le, sky2->rx_le_map); | |
1743 | kfree(sky2->rx_ring); | |
1744 | ||
1745 | pci_free_consistent(hw->pdev, | |
1746 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1747 | sky2->tx_le, sky2->tx_le_map); | |
1748 | kfree(sky2->tx_ring); | |
1749 | ||
1b537565 SH |
1750 | sky2->tx_le = NULL; |
1751 | sky2->rx_le = NULL; | |
1752 | ||
1753 | sky2->rx_ring = NULL; | |
1754 | sky2->tx_ring = NULL; | |
1755 | ||
cd28ab6a SH |
1756 | return 0; |
1757 | } | |
1758 | ||
1759 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1760 | { | |
ea76e635 | 1761 | if (hw->flags & SKY2_HW_FIBRE_PHY) |
793b883e SH |
1762 | return SPEED_1000; |
1763 | ||
05745c4a SH |
1764 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
1765 | if (aux & PHY_M_PS_SPEED_100) | |
1766 | return SPEED_100; | |
1767 | else | |
1768 | return SPEED_10; | |
1769 | } | |
cd28ab6a SH |
1770 | |
1771 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1772 | case PHY_M_PS_SPEED_1000: | |
1773 | return SPEED_1000; | |
1774 | case PHY_M_PS_SPEED_100: | |
1775 | return SPEED_100; | |
1776 | default: | |
1777 | return SPEED_10; | |
1778 | } | |
1779 | } | |
1780 | ||
1781 | static void sky2_link_up(struct sky2_port *sky2) | |
1782 | { | |
1783 | struct sky2_hw *hw = sky2->hw; | |
1784 | unsigned port = sky2->port; | |
1785 | u16 reg; | |
16ad91e1 SH |
1786 | static const char *fc_name[] = { |
1787 | [FC_NONE] = "none", | |
1788 | [FC_TX] = "tx", | |
1789 | [FC_RX] = "rx", | |
1790 | [FC_BOTH] = "both", | |
1791 | }; | |
cd28ab6a | 1792 | |
cd28ab6a | 1793 | /* enable Rx/Tx */ |
2eaba1a2 | 1794 | reg = gma_read16(hw, port, GM_GP_CTRL); |
cd28ab6a SH |
1795 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; |
1796 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
cd28ab6a SH |
1797 | |
1798 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1799 | ||
1800 | netif_carrier_on(sky2->netdev); | |
cd28ab6a | 1801 | |
75e80683 | 1802 | mod_timer(&hw->watchdog_timer, jiffies + 1); |
32c2c300 | 1803 | |
cd28ab6a | 1804 | /* Turn on link LED */ |
793b883e | 1805 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1806 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1807 | ||
ea76e635 | 1808 | if (hw->flags & SKY2_HW_NEWER_PHY) { |
793b883e | 1809 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
ed6d32c7 SH |
1810 | u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */ |
1811 | ||
1812 | switch(sky2->speed) { | |
1813 | case SPEED_10: | |
1814 | led |= PHY_M_LEDC_INIT_CTRL(7); | |
1815 | break; | |
1816 | ||
1817 | case SPEED_100: | |
1818 | led |= PHY_M_LEDC_STA1_CTRL(7); | |
1819 | break; | |
1820 | ||
1821 | case SPEED_1000: | |
1822 | led |= PHY_M_LEDC_STA0_CTRL(7); | |
1823 | break; | |
1824 | } | |
793b883e SH |
1825 | |
1826 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
ed6d32c7 | 1827 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led); |
793b883e SH |
1828 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
1829 | } | |
1830 | ||
cd28ab6a SH |
1831 | if (netif_msg_link(sky2)) |
1832 | printk(KERN_INFO PFX | |
d571b694 | 1833 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
cd28ab6a SH |
1834 | sky2->netdev->name, sky2->speed, |
1835 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
16ad91e1 | 1836 | fc_name[sky2->flow_status]); |
cd28ab6a SH |
1837 | } |
1838 | ||
1839 | static void sky2_link_down(struct sky2_port *sky2) | |
1840 | { | |
1841 | struct sky2_hw *hw = sky2->hw; | |
1842 | unsigned port = sky2->port; | |
1843 | u16 reg; | |
1844 | ||
1845 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1846 | ||
1847 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1848 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1849 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
cd28ab6a | 1850 | |
cd28ab6a | 1851 | netif_carrier_off(sky2->netdev); |
cd28ab6a SH |
1852 | |
1853 | /* Turn on link LED */ | |
1854 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1855 | ||
1856 | if (netif_msg_link(sky2)) | |
1857 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
2eaba1a2 | 1858 | |
cd28ab6a SH |
1859 | sky2_phy_init(hw, port); |
1860 | } | |
1861 | ||
16ad91e1 SH |
1862 | static enum flow_control sky2_flow(int rx, int tx) |
1863 | { | |
1864 | if (rx) | |
1865 | return tx ? FC_BOTH : FC_RX; | |
1866 | else | |
1867 | return tx ? FC_TX : FC_NONE; | |
1868 | } | |
1869 | ||
793b883e SH |
1870 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1871 | { | |
1872 | struct sky2_hw *hw = sky2->hw; | |
1873 | unsigned port = sky2->port; | |
da4c1ff4 | 1874 | u16 advert, lpa; |
793b883e | 1875 | |
da4c1ff4 | 1876 | advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); |
793b883e | 1877 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); |
793b883e SH |
1878 | if (lpa & PHY_M_AN_RF) { |
1879 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1880 | return -1; | |
1881 | } | |
1882 | ||
793b883e SH |
1883 | if (!(aux & PHY_M_PS_SPDUP_RES)) { |
1884 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1885 | sky2->netdev->name); | |
1886 | return -1; | |
1887 | } | |
1888 | ||
793b883e | 1889 | sky2->speed = sky2_phy_speed(hw, aux); |
7c74ac1c | 1890 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; |
793b883e | 1891 | |
da4c1ff4 SH |
1892 | /* Since the pause result bits seem to in different positions on |
1893 | * different chips. look at registers. | |
1894 | */ | |
ea76e635 | 1895 | if (hw->flags & SKY2_HW_FIBRE_PHY) { |
da4c1ff4 SH |
1896 | /* Shift for bits in fiber PHY */ |
1897 | advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); | |
1898 | lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); | |
1899 | ||
1900 | if (advert & ADVERTISE_1000XPAUSE) | |
1901 | advert |= ADVERTISE_PAUSE_CAP; | |
1902 | if (advert & ADVERTISE_1000XPSE_ASYM) | |
1903 | advert |= ADVERTISE_PAUSE_ASYM; | |
1904 | if (lpa & LPA_1000XPAUSE) | |
1905 | lpa |= LPA_PAUSE_CAP; | |
1906 | if (lpa & LPA_1000XPAUSE_ASYM) | |
1907 | lpa |= LPA_PAUSE_ASYM; | |
1908 | } | |
793b883e | 1909 | |
da4c1ff4 SH |
1910 | sky2->flow_status = FC_NONE; |
1911 | if (advert & ADVERTISE_PAUSE_CAP) { | |
1912 | if (lpa & LPA_PAUSE_CAP) | |
1913 | sky2->flow_status = FC_BOTH; | |
1914 | else if (advert & ADVERTISE_PAUSE_ASYM) | |
1915 | sky2->flow_status = FC_RX; | |
1916 | } else if (advert & ADVERTISE_PAUSE_ASYM) { | |
1917 | if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) | |
1918 | sky2->flow_status = FC_TX; | |
1919 | } | |
793b883e | 1920 | |
16ad91e1 | 1921 | if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 |
93745494 | 1922 | && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) |
16ad91e1 | 1923 | sky2->flow_status = FC_NONE; |
2eaba1a2 | 1924 | |
da4c1ff4 | 1925 | if (sky2->flow_status & FC_TX) |
793b883e SH |
1926 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
1927 | else | |
1928 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1929 | ||
1930 | return 0; | |
1931 | } | |
cd28ab6a | 1932 | |
e07b1aa8 SH |
1933 | /* Interrupt from PHY */ |
1934 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
cd28ab6a | 1935 | { |
e07b1aa8 SH |
1936 | struct net_device *dev = hw->dev[port]; |
1937 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a SH |
1938 | u16 istatus, phystat; |
1939 | ||
ebc646f6 SH |
1940 | if (!netif_running(dev)) |
1941 | return; | |
1942 | ||
e07b1aa8 SH |
1943 | spin_lock(&sky2->phy_lock); |
1944 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); | |
1945 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
1946 | ||
cd28ab6a SH |
1947 | if (netif_msg_intr(sky2)) |
1948 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1949 | sky2->netdev->name, istatus, phystat); | |
1950 | ||
2eaba1a2 | 1951 | if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) { |
793b883e SH |
1952 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1953 | sky2_link_up(sky2); | |
1954 | goto out; | |
1955 | } | |
cd28ab6a | 1956 | |
793b883e SH |
1957 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1958 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1959 | |
793b883e SH |
1960 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1961 | sky2->duplex = | |
1962 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1963 | |
793b883e SH |
1964 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1965 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1966 | sky2_link_up(sky2); |
793b883e SH |
1967 | else |
1968 | sky2_link_down(sky2); | |
cd28ab6a | 1969 | } |
793b883e | 1970 | out: |
e07b1aa8 | 1971 | spin_unlock(&sky2->phy_lock); |
cd28ab6a SH |
1972 | } |
1973 | ||
62335ab0 | 1974 | /* Transmit timeout is only called if we are running, carrier is up |
302d1252 SH |
1975 | * and tx queue is full (stopped). |
1976 | */ | |
cd28ab6a SH |
1977 | static void sky2_tx_timeout(struct net_device *dev) |
1978 | { | |
1979 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 | 1980 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a SH |
1981 | |
1982 | if (netif_msg_timer(sky2)) | |
1983 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1984 | ||
8f24664d | 1985 | printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n", |
62335ab0 SH |
1986 | dev->name, sky2->tx_cons, sky2->tx_prod, |
1987 | sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), | |
1988 | sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); | |
8f24664d | 1989 | |
81906791 SH |
1990 | /* can't restart safely under softirq */ |
1991 | schedule_work(&hw->restart_work); | |
cd28ab6a SH |
1992 | } |
1993 | ||
1994 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) | |
1995 | { | |
6b1a3aef SH |
1996 | struct sky2_port *sky2 = netdev_priv(dev); |
1997 | struct sky2_hw *hw = sky2->hw; | |
b628ed98 | 1998 | unsigned port = sky2->port; |
6b1a3aef SH |
1999 | int err; |
2000 | u16 ctl, mode; | |
e07b1aa8 | 2001 | u32 imask; |
cd28ab6a SH |
2002 | |
2003 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
2004 | return -EINVAL; | |
2005 | ||
05745c4a SH |
2006 | if (new_mtu > ETH_DATA_LEN && |
2007 | (hw->chip_id == CHIP_ID_YUKON_FE || | |
2008 | hw->chip_id == CHIP_ID_YUKON_FE_P)) | |
d2adf4f6 SH |
2009 | return -EINVAL; |
2010 | ||
6b1a3aef SH |
2011 | if (!netif_running(dev)) { |
2012 | dev->mtu = new_mtu; | |
2013 | return 0; | |
2014 | } | |
2015 | ||
e07b1aa8 | 2016 | imask = sky2_read32(hw, B0_IMSK); |
6b1a3aef SH |
2017 | sky2_write32(hw, B0_IMSK, 0); |
2018 | ||
018d1c66 SH |
2019 | dev->trans_start = jiffies; /* prevent tx timeout */ |
2020 | netif_stop_queue(dev); | |
bea3348e | 2021 | napi_disable(&hw->napi); |
018d1c66 | 2022 | |
e07b1aa8 SH |
2023 | synchronize_irq(hw->pdev->irq); |
2024 | ||
e0c28116 | 2025 | if (sky2_read8(hw, B2_E_0) == 0) |
69161611 | 2026 | sky2_set_tx_stfwd(hw, port); |
b628ed98 SH |
2027 | |
2028 | ctl = gma_read16(hw, port, GM_GP_CTRL); | |
2029 | gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
6b1a3aef SH |
2030 | sky2_rx_stop(sky2); |
2031 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
2032 | |
2033 | dev->mtu = new_mtu; | |
14d0263f | 2034 | |
6b1a3aef SH |
2035 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
2036 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
2037 | ||
2038 | if (dev->mtu > ETH_DATA_LEN) | |
2039 | mode |= GM_SMOD_JUMBO_ENA; | |
2040 | ||
b628ed98 | 2041 | gma_write16(hw, port, GM_SERIAL_MODE, mode); |
cd28ab6a | 2042 | |
b628ed98 | 2043 | sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 2044 | |
6b1a3aef | 2045 | err = sky2_rx_start(sky2); |
e07b1aa8 | 2046 | sky2_write32(hw, B0_IMSK, imask); |
018d1c66 | 2047 | |
bea3348e SH |
2048 | napi_enable(&hw->napi); |
2049 | ||
1b537565 SH |
2050 | if (err) |
2051 | dev_close(dev); | |
2052 | else { | |
b628ed98 | 2053 | gma_write16(hw, port, GM_GP_CTRL, ctl); |
1b537565 | 2054 | |
1b537565 SH |
2055 | netif_wake_queue(dev); |
2056 | } | |
2057 | ||
cd28ab6a SH |
2058 | return err; |
2059 | } | |
2060 | ||
14d0263f SH |
2061 | /* For small just reuse existing skb for next receive */ |
2062 | static struct sk_buff *receive_copy(struct sky2_port *sky2, | |
2063 | const struct rx_ring_info *re, | |
2064 | unsigned length) | |
2065 | { | |
2066 | struct sk_buff *skb; | |
2067 | ||
2068 | skb = netdev_alloc_skb(sky2->netdev, length + 2); | |
2069 | if (likely(skb)) { | |
2070 | skb_reserve(skb, 2); | |
2071 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, | |
2072 | length, PCI_DMA_FROMDEVICE); | |
d626f62b | 2073 | skb_copy_from_linear_data(re->skb, skb->data, length); |
14d0263f SH |
2074 | skb->ip_summed = re->skb->ip_summed; |
2075 | skb->csum = re->skb->csum; | |
2076 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, | |
2077 | length, PCI_DMA_FROMDEVICE); | |
2078 | re->skb->ip_summed = CHECKSUM_NONE; | |
489b10c1 | 2079 | skb_put(skb, length); |
14d0263f SH |
2080 | } |
2081 | return skb; | |
2082 | } | |
2083 | ||
2084 | /* Adjust length of skb with fragments to match received data */ | |
2085 | static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, | |
2086 | unsigned int length) | |
2087 | { | |
2088 | int i, num_frags; | |
2089 | unsigned int size; | |
2090 | ||
2091 | /* put header into skb */ | |
2092 | size = min(length, hdr_space); | |
2093 | skb->tail += size; | |
2094 | skb->len += size; | |
2095 | length -= size; | |
2096 | ||
2097 | num_frags = skb_shinfo(skb)->nr_frags; | |
2098 | for (i = 0; i < num_frags; i++) { | |
2099 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2100 | ||
2101 | if (length == 0) { | |
2102 | /* don't need this page */ | |
2103 | __free_page(frag->page); | |
2104 | --skb_shinfo(skb)->nr_frags; | |
2105 | } else { | |
2106 | size = min(length, (unsigned) PAGE_SIZE); | |
2107 | ||
2108 | frag->size = size; | |
2109 | skb->data_len += size; | |
2110 | skb->truesize += size; | |
2111 | skb->len += size; | |
2112 | length -= size; | |
2113 | } | |
2114 | } | |
2115 | } | |
2116 | ||
2117 | /* Normal packet - take skb from ring element and put in a new one */ | |
2118 | static struct sk_buff *receive_new(struct sky2_port *sky2, | |
2119 | struct rx_ring_info *re, | |
2120 | unsigned int length) | |
2121 | { | |
2122 | struct sk_buff *skb, *nskb; | |
2123 | unsigned hdr_space = sky2->rx_data_size; | |
2124 | ||
14d0263f SH |
2125 | /* Don't be tricky about reusing pages (yet) */ |
2126 | nskb = sky2_rx_alloc(sky2); | |
2127 | if (unlikely(!nskb)) | |
2128 | return NULL; | |
2129 | ||
2130 | skb = re->skb; | |
2131 | sky2_rx_unmap_skb(sky2->hw->pdev, re); | |
2132 | ||
2133 | prefetch(skb->data); | |
2134 | re->skb = nskb; | |
2135 | sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space); | |
2136 | ||
2137 | if (skb_shinfo(skb)->nr_frags) | |
2138 | skb_put_frags(skb, hdr_space, length); | |
2139 | else | |
489b10c1 | 2140 | skb_put(skb, length); |
14d0263f SH |
2141 | return skb; |
2142 | } | |
2143 | ||
cd28ab6a SH |
2144 | /* |
2145 | * Receive one packet. | |
d571b694 | 2146 | * For larger packets, get new buffer. |
cd28ab6a | 2147 | */ |
497d7c86 | 2148 | static struct sk_buff *sky2_receive(struct net_device *dev, |
cd28ab6a SH |
2149 | u16 length, u32 status) |
2150 | { | |
497d7c86 | 2151 | struct sky2_port *sky2 = netdev_priv(dev); |
291ea614 | 2152 | struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 2153 | struct sk_buff *skb = NULL; |
d6532232 SH |
2154 | u16 count = (status & GMR_FS_LEN) >> 16; |
2155 | ||
2156 | #ifdef SKY2_VLAN_TAG_USED | |
2157 | /* Account for vlan tag */ | |
2158 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) | |
2159 | count -= VLAN_HLEN; | |
2160 | #endif | |
cd28ab6a SH |
2161 | |
2162 | if (unlikely(netif_msg_rx_status(sky2))) | |
2163 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
497d7c86 | 2164 | dev->name, sky2->rx_next, status, length); |
cd28ab6a | 2165 | |
793b883e | 2166 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 2167 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 2168 | |
3b12e014 SH |
2169 | /* This chip has hardware problems that generates bogus status. |
2170 | * So do only marginal checking and expect higher level protocols | |
2171 | * to handle crap frames. | |
2172 | */ | |
2173 | if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && | |
2174 | sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && | |
2175 | length != count) | |
2176 | goto okay; | |
2177 | ||
42eeea01 | 2178 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
2179 | goto error; |
2180 | ||
42eeea01 SH |
2181 | if (!(status & GMR_FS_RX_OK)) |
2182 | goto resubmit; | |
2183 | ||
d6532232 SH |
2184 | /* if length reported by DMA does not match PHY, packet was truncated */ |
2185 | if (length != count) | |
3b12e014 | 2186 | goto len_error; |
71749531 | 2187 | |
3b12e014 | 2188 | okay: |
14d0263f SH |
2189 | if (length < copybreak) |
2190 | skb = receive_copy(sky2, re, length); | |
2191 | else | |
2192 | skb = receive_new(sky2, re, length); | |
793b883e | 2193 | resubmit: |
14d0263f | 2194 | sky2_rx_submit(sky2, re); |
79e57d32 | 2195 | |
cd28ab6a SH |
2196 | return skb; |
2197 | ||
3b12e014 | 2198 | len_error: |
71749531 SH |
2199 | /* Truncation of overlength packets |
2200 | causes PHY length to not match MAC length */ | |
7138a0f5 | 2201 | ++dev->stats.rx_length_errors; |
d6532232 | 2202 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
3b12e014 SH |
2203 | pr_info(PFX "%s: rx length error: status %#x length %d\n", |
2204 | dev->name, status, length); | |
d6532232 | 2205 | goto resubmit; |
71749531 | 2206 | |
cd28ab6a | 2207 | error: |
7138a0f5 | 2208 | ++dev->stats.rx_errors; |
b6d77734 | 2209 | if (status & GMR_FS_RX_FF_OV) { |
7138a0f5 | 2210 | dev->stats.rx_over_errors++; |
b6d77734 SH |
2211 | goto resubmit; |
2212 | } | |
6e15b712 | 2213 | |
3be92a70 | 2214 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
cd28ab6a | 2215 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", |
497d7c86 | 2216 | dev->name, status, length); |
793b883e SH |
2217 | |
2218 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
7138a0f5 | 2219 | dev->stats.rx_length_errors++; |
cd28ab6a | 2220 | if (status & GMR_FS_FRAGMENT) |
7138a0f5 | 2221 | dev->stats.rx_frame_errors++; |
cd28ab6a | 2222 | if (status & GMR_FS_CRC_ERR) |
7138a0f5 | 2223 | dev->stats.rx_crc_errors++; |
79e57d32 | 2224 | |
793b883e | 2225 | goto resubmit; |
cd28ab6a SH |
2226 | } |
2227 | ||
e07b1aa8 SH |
2228 | /* Transmit complete */ |
2229 | static inline void sky2_tx_done(struct net_device *dev, u16 last) | |
13b97b74 | 2230 | { |
e07b1aa8 | 2231 | struct sky2_port *sky2 = netdev_priv(dev); |
302d1252 | 2232 | |
e07b1aa8 | 2233 | if (netif_running(dev)) { |
2bb8c262 | 2234 | netif_tx_lock(dev); |
e07b1aa8 | 2235 | sky2_tx_complete(sky2, last); |
2bb8c262 | 2236 | netif_tx_unlock(dev); |
2224795d | 2237 | } |
cd28ab6a SH |
2238 | } |
2239 | ||
e07b1aa8 | 2240 | /* Process status response ring */ |
26691830 | 2241 | static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) |
cd28ab6a | 2242 | { |
e07b1aa8 | 2243 | int work_done = 0; |
55c9dd35 | 2244 | unsigned rx[2] = { 0, 0 }; |
a8fd6266 | 2245 | |
af2a58ac | 2246 | rmb(); |
26691830 | 2247 | do { |
55c9dd35 | 2248 | struct sky2_port *sky2; |
13210ce5 | 2249 | struct sky2_status_le *le = hw->st_le + hw->st_idx; |
ab5adecb | 2250 | unsigned port; |
13210ce5 | 2251 | struct net_device *dev; |
cd28ab6a | 2252 | struct sk_buff *skb; |
cd28ab6a SH |
2253 | u32 status; |
2254 | u16 length; | |
ab5adecb SH |
2255 | u8 opcode = le->opcode; |
2256 | ||
2257 | if (!(opcode & HW_OWNER)) | |
2258 | break; | |
cd28ab6a | 2259 | |
cb5d9547 | 2260 | hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE); |
bea86103 | 2261 | |
ab5adecb | 2262 | port = le->css & CSS_LINK_BIT; |
69161611 | 2263 | dev = hw->dev[port]; |
13210ce5 | 2264 | sky2 = netdev_priv(dev); |
f65b138c SH |
2265 | length = le16_to_cpu(le->length); |
2266 | status = le32_to_cpu(le->status); | |
cd28ab6a | 2267 | |
ab5adecb SH |
2268 | le->opcode = 0; |
2269 | switch (opcode & ~HW_OWNER) { | |
cd28ab6a | 2270 | case OP_RXSTAT: |
55c9dd35 | 2271 | ++rx[port]; |
497d7c86 | 2272 | skb = sky2_receive(dev, length, status); |
3225b919 | 2273 | if (unlikely(!skb)) { |
7138a0f5 | 2274 | dev->stats.rx_dropped++; |
55c9dd35 | 2275 | break; |
3225b919 | 2276 | } |
13210ce5 | 2277 | |
69161611 | 2278 | /* This chip reports checksum status differently */ |
05745c4a | 2279 | if (hw->flags & SKY2_HW_NEW_LE) { |
69161611 SH |
2280 | if (sky2->rx_csum && |
2281 | (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && | |
2282 | (le->css & CSS_TCPUDPCSOK)) | |
2283 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2284 | else | |
2285 | skb->ip_summed = CHECKSUM_NONE; | |
2286 | } | |
2287 | ||
13210ce5 | 2288 | skb->protocol = eth_type_trans(skb, dev); |
7138a0f5 SH |
2289 | dev->stats.rx_packets++; |
2290 | dev->stats.rx_bytes += skb->len; | |
13210ce5 SH |
2291 | dev->last_rx = jiffies; |
2292 | ||
d1f13708 SH |
2293 | #ifdef SKY2_VLAN_TAG_USED |
2294 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { | |
2295 | vlan_hwaccel_receive_skb(skb, | |
2296 | sky2->vlgrp, | |
2297 | be16_to_cpu(sky2->rx_tag)); | |
2298 | } else | |
2299 | #endif | |
cd28ab6a | 2300 | netif_receive_skb(skb); |
13210ce5 | 2301 | |
22e11703 | 2302 | /* Stop after net poll weight */ |
13210ce5 SH |
2303 | if (++work_done >= to_do) |
2304 | goto exit_loop; | |
cd28ab6a SH |
2305 | break; |
2306 | ||
d1f13708 SH |
2307 | #ifdef SKY2_VLAN_TAG_USED |
2308 | case OP_RXVLAN: | |
2309 | sky2->rx_tag = length; | |
2310 | break; | |
2311 | ||
2312 | case OP_RXCHKSVLAN: | |
2313 | sky2->rx_tag = length; | |
2314 | /* fall through */ | |
2315 | #endif | |
cd28ab6a | 2316 | case OP_RXCHKS: |
87418307 SH |
2317 | if (!sky2->rx_csum) |
2318 | break; | |
2319 | ||
05745c4a SH |
2320 | /* If this happens then driver assuming wrong format */ |
2321 | if (unlikely(hw->flags & SKY2_HW_NEW_LE)) { | |
2322 | if (net_ratelimit()) | |
2323 | printk(KERN_NOTICE "%s: unexpected" | |
2324 | " checksum status\n", | |
2325 | dev->name); | |
69161611 | 2326 | break; |
05745c4a | 2327 | } |
69161611 | 2328 | |
87418307 SH |
2329 | /* Both checksum counters are programmed to start at |
2330 | * the same offset, so unless there is a problem they | |
2331 | * should match. This failure is an early indication that | |
2332 | * hardware receive checksumming won't work. | |
2333 | */ | |
2334 | if (likely(status >> 16 == (status & 0xffff))) { | |
2335 | skb = sky2->rx_ring[sky2->rx_next].skb; | |
2336 | skb->ip_summed = CHECKSUM_COMPLETE; | |
2337 | skb->csum = status & 0xffff; | |
2338 | } else { | |
2339 | printk(KERN_NOTICE PFX "%s: hardware receive " | |
2340 | "checksum problem (status = %#x)\n", | |
2341 | dev->name, status); | |
2342 | sky2->rx_csum = 0; | |
2343 | sky2_write32(sky2->hw, | |
69161611 | 2344 | Q_ADDR(rxqaddr[port], Q_CSR), |
87418307 SH |
2345 | BMU_DIS_RX_CHKSUM); |
2346 | } | |
cd28ab6a SH |
2347 | break; |
2348 | ||
2349 | case OP_TXINDEXLE: | |
13b97b74 | 2350 | /* TX index reports status for both ports */ |
f55925d7 SH |
2351 | BUILD_BUG_ON(TX_RING_SIZE > 0x1000); |
2352 | sky2_tx_done(hw->dev[0], status & 0xfff); | |
e07b1aa8 SH |
2353 | if (hw->dev[1]) |
2354 | sky2_tx_done(hw->dev[1], | |
2355 | ((status >> 24) & 0xff) | |
2356 | | (u16)(length & 0xf) << 8); | |
cd28ab6a SH |
2357 | break; |
2358 | ||
cd28ab6a SH |
2359 | default: |
2360 | if (net_ratelimit()) | |
793b883e | 2361 | printk(KERN_WARNING PFX |
ab5adecb | 2362 | "unknown status opcode 0x%x\n", opcode); |
cd28ab6a | 2363 | } |
26691830 | 2364 | } while (hw->st_idx != idx); |
cd28ab6a | 2365 | |
fe2a24df SH |
2366 | /* Fully processed status ring so clear irq */ |
2367 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | |
2368 | ||
13210ce5 | 2369 | exit_loop: |
55c9dd35 SH |
2370 | if (rx[0]) |
2371 | sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1); | |
22e11703 | 2372 | |
55c9dd35 SH |
2373 | if (rx[1]) |
2374 | sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2); | |
22e11703 | 2375 | |
e07b1aa8 | 2376 | return work_done; |
cd28ab6a SH |
2377 | } |
2378 | ||
2379 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
2380 | { | |
2381 | struct net_device *dev = hw->dev[port]; | |
2382 | ||
3be92a70 SH |
2383 | if (net_ratelimit()) |
2384 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
2385 | dev->name, status); | |
cd28ab6a SH |
2386 | |
2387 | if (status & Y2_IS_PAR_RD1) { | |
3be92a70 SH |
2388 | if (net_ratelimit()) |
2389 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
2390 | dev->name); | |
cd28ab6a SH |
2391 | /* Clear IRQ */ |
2392 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
2393 | } | |
2394 | ||
2395 | if (status & Y2_IS_PAR_WR1) { | |
3be92a70 SH |
2396 | if (net_ratelimit()) |
2397 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
2398 | dev->name); | |
cd28ab6a SH |
2399 | |
2400 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
2401 | } | |
2402 | ||
2403 | if (status & Y2_IS_PAR_MAC1) { | |
3be92a70 SH |
2404 | if (net_ratelimit()) |
2405 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
cd28ab6a SH |
2406 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
2407 | } | |
2408 | ||
2409 | if (status & Y2_IS_PAR_RX1) { | |
3be92a70 SH |
2410 | if (net_ratelimit()) |
2411 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
cd28ab6a SH |
2412 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
2413 | } | |
2414 | ||
2415 | if (status & Y2_IS_TCP_TXA1) { | |
3be92a70 SH |
2416 | if (net_ratelimit()) |
2417 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", | |
2418 | dev->name); | |
cd28ab6a SH |
2419 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
2420 | } | |
2421 | } | |
2422 | ||
2423 | static void sky2_hw_intr(struct sky2_hw *hw) | |
2424 | { | |
555382cb | 2425 | struct pci_dev *pdev = hw->pdev; |
cd28ab6a | 2426 | u32 status = sky2_read32(hw, B0_HWE_ISRC); |
555382cb SH |
2427 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); |
2428 | ||
2429 | status &= hwmsk; | |
cd28ab6a | 2430 | |
793b883e | 2431 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 2432 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2433 | |
2434 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
2435 | u16 pci_err; |
2436 | ||
167f53d0 | 2437 | pci_read_config_word(pdev, PCI_STATUS, &pci_err); |
3be92a70 | 2438 | if (net_ratelimit()) |
555382cb | 2439 | dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", |
b02a9258 | 2440 | pci_err); |
cd28ab6a | 2441 | |
167f53d0 SH |
2442 | pci_write_config_word(pdev, PCI_STATUS, |
2443 | pci_err | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
2444 | } |
2445 | ||
2446 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 2447 | /* PCI-Express uncorrectable Error occurred */ |
555382cb SH |
2448 | int pos = pci_find_aer_capability(hw->pdev); |
2449 | u32 err; | |
cd28ab6a | 2450 | |
555382cb | 2451 | pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_STATUS, &err); |
3be92a70 | 2452 | if (net_ratelimit()) |
555382cb SH |
2453 | dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); |
2454 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
cd28ab6a SH |
2455 | } |
2456 | ||
2457 | if (status & Y2_HWE_L1_MASK) | |
2458 | sky2_hw_error(hw, 0, status); | |
2459 | status >>= 8; | |
2460 | if (status & Y2_HWE_L1_MASK) | |
2461 | sky2_hw_error(hw, 1, status); | |
2462 | } | |
2463 | ||
2464 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2465 | { | |
2466 | struct net_device *dev = hw->dev[port]; | |
2467 | struct sky2_port *sky2 = netdev_priv(dev); | |
2468 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2469 | ||
2470 | if (netif_msg_intr(sky2)) | |
2471 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
2472 | dev->name, status); | |
2473 | ||
a3caeada SH |
2474 | if (status & GM_IS_RX_CO_OV) |
2475 | gma_read16(hw, port, GM_RX_IRQ_SRC); | |
2476 | ||
2477 | if (status & GM_IS_TX_CO_OV) | |
2478 | gma_read16(hw, port, GM_TX_IRQ_SRC); | |
2479 | ||
cd28ab6a | 2480 | if (status & GM_IS_RX_FF_OR) { |
7138a0f5 | 2481 | ++dev->stats.rx_fifo_errors; |
cd28ab6a SH |
2482 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); |
2483 | } | |
2484 | ||
2485 | if (status & GM_IS_TX_FF_UR) { | |
7138a0f5 | 2486 | ++dev->stats.tx_fifo_errors; |
cd28ab6a SH |
2487 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); |
2488 | } | |
cd28ab6a SH |
2489 | } |
2490 | ||
40b01727 SH |
2491 | /* This should never happen it is a bug. */ |
2492 | static void sky2_le_error(struct sky2_hw *hw, unsigned port, | |
2493 | u16 q, unsigned ring_size) | |
d257924e SH |
2494 | { |
2495 | struct net_device *dev = hw->dev[port]; | |
2496 | struct sky2_port *sky2 = netdev_priv(dev); | |
40b01727 SH |
2497 | unsigned idx; |
2498 | const u64 *le = (q == Q_R1 || q == Q_R2) | |
2499 | ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le; | |
d257924e | 2500 | |
40b01727 SH |
2501 | idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); |
2502 | printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n", | |
2503 | dev->name, (unsigned) q, idx, (unsigned long long) le[idx], | |
2504 | (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); | |
d257924e | 2505 | |
40b01727 | 2506 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); |
d257924e | 2507 | } |
cd28ab6a | 2508 | |
75e80683 SH |
2509 | static int sky2_rx_hung(struct net_device *dev) |
2510 | { | |
2511 | struct sky2_port *sky2 = netdev_priv(dev); | |
2512 | struct sky2_hw *hw = sky2->hw; | |
2513 | unsigned port = sky2->port; | |
2514 | unsigned rxq = rxqaddr[port]; | |
2515 | u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); | |
2516 | u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); | |
2517 | u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); | |
2518 | u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); | |
2519 | ||
2520 | /* If idle and MAC or PCI is stuck */ | |
2521 | if (sky2->check.last == dev->last_rx && | |
2522 | ((mac_rp == sky2->check.mac_rp && | |
2523 | mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || | |
2524 | /* Check if the PCI RX hang */ | |
2525 | (fifo_rp == sky2->check.fifo_rp && | |
2526 | fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { | |
2527 | printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n", | |
2528 | dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp, | |
2529 | sky2_read8(hw, Q_ADDR(rxq, Q_WP))); | |
2530 | return 1; | |
2531 | } else { | |
2532 | sky2->check.last = dev->last_rx; | |
2533 | sky2->check.mac_rp = mac_rp; | |
2534 | sky2->check.mac_lev = mac_lev; | |
2535 | sky2->check.fifo_rp = fifo_rp; | |
2536 | sky2->check.fifo_lev = fifo_lev; | |
2537 | return 0; | |
2538 | } | |
2539 | } | |
2540 | ||
32c2c300 | 2541 | static void sky2_watchdog(unsigned long arg) |
d27ed387 | 2542 | { |
01bd7564 | 2543 | struct sky2_hw *hw = (struct sky2_hw *) arg; |
d27ed387 | 2544 | |
75e80683 | 2545 | /* Check for lost IRQ once a second */ |
32c2c300 | 2546 | if (sky2_read32(hw, B0_ISRC)) { |
bea3348e | 2547 | napi_schedule(&hw->napi); |
75e80683 SH |
2548 | } else { |
2549 | int i, active = 0; | |
2550 | ||
2551 | for (i = 0; i < hw->ports; i++) { | |
bea3348e | 2552 | struct net_device *dev = hw->dev[i]; |
75e80683 SH |
2553 | if (!netif_running(dev)) |
2554 | continue; | |
2555 | ++active; | |
2556 | ||
2557 | /* For chips with Rx FIFO, check if stuck */ | |
e0c28116 | 2558 | if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) && |
75e80683 SH |
2559 | sky2_rx_hung(dev)) { |
2560 | pr_info(PFX "%s: receiver hang detected\n", | |
2561 | dev->name); | |
2562 | schedule_work(&hw->restart_work); | |
2563 | return; | |
2564 | } | |
2565 | } | |
2566 | ||
2567 | if (active == 0) | |
2568 | return; | |
32c2c300 | 2569 | } |
01bd7564 | 2570 | |
75e80683 | 2571 | mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); |
d27ed387 SH |
2572 | } |
2573 | ||
40b01727 SH |
2574 | /* Hardware/software error handling */ |
2575 | static void sky2_err_intr(struct sky2_hw *hw, u32 status) | |
cd28ab6a | 2576 | { |
40b01727 SH |
2577 | if (net_ratelimit()) |
2578 | dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); | |
cd28ab6a | 2579 | |
1e5f1283 SH |
2580 | if (status & Y2_IS_HW_ERR) |
2581 | sky2_hw_intr(hw); | |
d257924e | 2582 | |
1e5f1283 SH |
2583 | if (status & Y2_IS_IRQ_MAC1) |
2584 | sky2_mac_intr(hw, 0); | |
cd28ab6a | 2585 | |
1e5f1283 SH |
2586 | if (status & Y2_IS_IRQ_MAC2) |
2587 | sky2_mac_intr(hw, 1); | |
cd28ab6a | 2588 | |
1e5f1283 | 2589 | if (status & Y2_IS_CHK_RX1) |
40b01727 | 2590 | sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE); |
d257924e | 2591 | |
1e5f1283 | 2592 | if (status & Y2_IS_CHK_RX2) |
40b01727 | 2593 | sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE); |
d257924e | 2594 | |
1e5f1283 | 2595 | if (status & Y2_IS_CHK_TXA1) |
40b01727 | 2596 | sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE); |
d257924e | 2597 | |
1e5f1283 | 2598 | if (status & Y2_IS_CHK_TXA2) |
40b01727 SH |
2599 | sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE); |
2600 | } | |
2601 | ||
bea3348e | 2602 | static int sky2_poll(struct napi_struct *napi, int work_limit) |
40b01727 | 2603 | { |
bea3348e | 2604 | struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); |
40b01727 | 2605 | u32 status = sky2_read32(hw, B0_Y2_SP_EISR); |
6f535763 | 2606 | int work_done = 0; |
26691830 | 2607 | u16 idx; |
40b01727 SH |
2608 | |
2609 | if (unlikely(status & Y2_IS_ERROR)) | |
2610 | sky2_err_intr(hw, status); | |
2611 | ||
2612 | if (status & Y2_IS_IRQ_PHY1) | |
2613 | sky2_phy_intr(hw, 0); | |
2614 | ||
2615 | if (status & Y2_IS_IRQ_PHY2) | |
2616 | sky2_phy_intr(hw, 1); | |
cd28ab6a | 2617 | |
26691830 SH |
2618 | while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { |
2619 | work_done += sky2_status_intr(hw, work_limit - work_done, idx); | |
6f535763 DM |
2620 | |
2621 | if (work_done >= work_limit) | |
26691830 SH |
2622 | goto done; |
2623 | } | |
6f535763 | 2624 | |
26691830 SH |
2625 | /* Bug/Errata workaround? |
2626 | * Need to kick the TX irq moderation timer. | |
2627 | */ | |
2628 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) { | |
2629 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
2630 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
fe2a24df | 2631 | } |
26691830 SH |
2632 | napi_complete(napi); |
2633 | sky2_read32(hw, B0_Y2_SP_LISR); | |
2634 | done: | |
6f535763 | 2635 | |
bea3348e | 2636 | return work_done; |
e07b1aa8 SH |
2637 | } |
2638 | ||
7d12e780 | 2639 | static irqreturn_t sky2_intr(int irq, void *dev_id) |
e07b1aa8 SH |
2640 | { |
2641 | struct sky2_hw *hw = dev_id; | |
e07b1aa8 SH |
2642 | u32 status; |
2643 | ||
2644 | /* Reading this mask interrupts as side effect */ | |
2645 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
2646 | if (status == 0 || status == ~0) | |
2647 | return IRQ_NONE; | |
793b883e | 2648 | |
e07b1aa8 | 2649 | prefetch(&hw->st_le[hw->st_idx]); |
bea3348e SH |
2650 | |
2651 | napi_schedule(&hw->napi); | |
793b883e | 2652 | |
cd28ab6a SH |
2653 | return IRQ_HANDLED; |
2654 | } | |
2655 | ||
2656 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2657 | static void sky2_netpoll(struct net_device *dev) | |
2658 | { | |
2659 | struct sky2_port *sky2 = netdev_priv(dev); | |
2660 | ||
bea3348e | 2661 | napi_schedule(&sky2->hw->napi); |
cd28ab6a SH |
2662 | } |
2663 | #endif | |
2664 | ||
2665 | /* Chip internal frequency for clock calculations */ | |
05745c4a | 2666 | static u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 2667 | { |
793b883e | 2668 | switch (hw->chip_id) { |
cd28ab6a | 2669 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2670 | case CHIP_ID_YUKON_EC_U: |
93745494 | 2671 | case CHIP_ID_YUKON_EX: |
05745c4a SH |
2672 | return 125; |
2673 | ||
cd28ab6a | 2674 | case CHIP_ID_YUKON_FE: |
05745c4a SH |
2675 | return 100; |
2676 | ||
2677 | case CHIP_ID_YUKON_FE_P: | |
2678 | return 50; | |
2679 | ||
2680 | case CHIP_ID_YUKON_XL: | |
2681 | return 156; | |
2682 | ||
2683 | default: | |
2684 | BUG(); | |
cd28ab6a SH |
2685 | } |
2686 | } | |
2687 | ||
fb17358f | 2688 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 2689 | { |
fb17358f | 2690 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
2691 | } |
2692 | ||
fb17358f | 2693 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 2694 | { |
fb17358f | 2695 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
2696 | } |
2697 | ||
fb17358f | 2698 | |
e3173832 | 2699 | static int __devinit sky2_init(struct sky2_hw *hw) |
cd28ab6a | 2700 | { |
167f53d0 | 2701 | int rc; |
b89165f2 | 2702 | u8 t8; |
cd28ab6a | 2703 | |
167f53d0 SH |
2704 | /* Enable all clocks and check for bad PCI access */ |
2705 | rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0); | |
2706 | if (rc) | |
2707 | return rc; | |
451af335 | 2708 | |
cd28ab6a | 2709 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
08c06d8a | 2710 | |
cd28ab6a | 2711 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
ea76e635 SH |
2712 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; |
2713 | ||
2714 | switch(hw->chip_id) { | |
2715 | case CHIP_ID_YUKON_XL: | |
2716 | hw->flags = SKY2_HW_GIGABIT | |
e0c28116 SH |
2717 | | SKY2_HW_NEWER_PHY; |
2718 | if (hw->chip_rev < 3) | |
2719 | hw->flags |= SKY2_HW_FIFO_HANG_CHECK; | |
2720 | ||
ea76e635 SH |
2721 | break; |
2722 | ||
2723 | case CHIP_ID_YUKON_EC_U: | |
2724 | hw->flags = SKY2_HW_GIGABIT | |
2725 | | SKY2_HW_NEWER_PHY | |
2726 | | SKY2_HW_ADV_POWER_CTL; | |
2727 | break; | |
2728 | ||
2729 | case CHIP_ID_YUKON_EX: | |
2730 | hw->flags = SKY2_HW_GIGABIT | |
2731 | | SKY2_HW_NEWER_PHY | |
2732 | | SKY2_HW_NEW_LE | |
2733 | | SKY2_HW_ADV_POWER_CTL; | |
2734 | ||
2735 | /* New transmit checksum */ | |
2736 | if (hw->chip_rev != CHIP_REV_YU_EX_B0) | |
2737 | hw->flags |= SKY2_HW_AUTO_TX_SUM; | |
2738 | break; | |
2739 | ||
2740 | case CHIP_ID_YUKON_EC: | |
2741 | /* This rev is really old, and requires untested workarounds */ | |
2742 | if (hw->chip_rev == CHIP_REV_YU_EC_A1) { | |
2743 | dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); | |
2744 | return -EOPNOTSUPP; | |
2745 | } | |
e0c28116 | 2746 | hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK; |
ea76e635 SH |
2747 | break; |
2748 | ||
2749 | case CHIP_ID_YUKON_FE: | |
ea76e635 SH |
2750 | break; |
2751 | ||
05745c4a SH |
2752 | case CHIP_ID_YUKON_FE_P: |
2753 | hw->flags = SKY2_HW_NEWER_PHY | |
2754 | | SKY2_HW_NEW_LE | |
2755 | | SKY2_HW_AUTO_TX_SUM | |
2756 | | SKY2_HW_ADV_POWER_CTL; | |
2757 | break; | |
ea76e635 | 2758 | default: |
b02a9258 SH |
2759 | dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", |
2760 | hw->chip_id); | |
cd28ab6a SH |
2761 | return -EOPNOTSUPP; |
2762 | } | |
2763 | ||
ea76e635 SH |
2764 | hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); |
2765 | if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') | |
2766 | hw->flags |= SKY2_HW_FIBRE_PHY; | |
290d4de5 | 2767 | |
290d4de5 | 2768 | |
e3173832 SH |
2769 | hw->ports = 1; |
2770 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
2771 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
2772 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
2773 | ++hw->ports; | |
2774 | } | |
2775 | ||
2776 | return 0; | |
2777 | } | |
2778 | ||
2779 | static void sky2_reset(struct sky2_hw *hw) | |
2780 | { | |
555382cb | 2781 | struct pci_dev *pdev = hw->pdev; |
e3173832 | 2782 | u16 status; |
555382cb SH |
2783 | int i, cap; |
2784 | u32 hwe_mask = Y2_HWE_ALL_MASK; | |
e3173832 | 2785 | |
cd28ab6a | 2786 | /* disable ASF */ |
4f44d8ba SH |
2787 | if (hw->chip_id == CHIP_ID_YUKON_EX) { |
2788 | status = sky2_read16(hw, HCU_CCSR); | |
2789 | status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | | |
2790 | HCU_CCSR_UC_STATE_MSK); | |
2791 | sky2_write16(hw, HCU_CCSR, status); | |
2792 | } else | |
2793 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
2794 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
cd28ab6a SH |
2795 | |
2796 | /* do a SW reset */ | |
2797 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
2798 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2799 | ||
ac93a394 SH |
2800 | /* allow writes to PCI config */ |
2801 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
2802 | ||
cd28ab6a | 2803 | /* clear PCI errors, if any */ |
167f53d0 SH |
2804 | pci_read_config_word(pdev, PCI_STATUS, &status); |
2805 | status |= PCI_STATUS_ERROR_BITS; | |
2806 | pci_write_config_word(pdev, PCI_STATUS, status); | |
cd28ab6a SH |
2807 | |
2808 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
2809 | ||
555382cb SH |
2810 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
2811 | if (cap) { | |
2812 | /* Check for advanced error reporting */ | |
2813 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2814 | pci_cleanup_aer_correct_error_status(pdev); | |
2815 | ||
2816 | /* If error bit is stuck on ignore it */ | |
2817 | if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) | |
2818 | dev_info(&pdev->dev, "ignoring stuck error report bit\n"); | |
7bd656d1 | 2819 | |
555382cb SH |
2820 | else if (pci_enable_pcie_error_reporting(pdev)) |
2821 | hwe_mask |= Y2_IS_PCI_EXP; | |
2822 | } | |
cd28ab6a | 2823 | |
ae306cca | 2824 | sky2_power_on(hw); |
cd28ab6a SH |
2825 | |
2826 | for (i = 0; i < hw->ports; i++) { | |
2827 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
2828 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
69161611 SH |
2829 | |
2830 | if (hw->chip_id == CHIP_ID_YUKON_EX) | |
2831 | sky2_write16(hw, SK_REG(i, GMAC_CTRL), | |
2832 | GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | |
2833 | | GMC_BYP_RETR_ON); | |
cd28ab6a SH |
2834 | } |
2835 | ||
793b883e SH |
2836 | /* Clear I2C IRQ noise */ |
2837 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
2838 | |
2839 | /* turn off hardware timer (unused) */ | |
2840 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
2841 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 2842 | |
cd28ab6a SH |
2843 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
2844 | ||
69634ee7 SH |
2845 | /* Turn off descriptor polling */ |
2846 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
2847 | |
2848 | /* Turn off receive timestamp */ | |
2849 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 2850 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2851 | |
2852 | /* enable the Tx Arbiters */ | |
2853 | for (i = 0; i < hw->ports; i++) | |
2854 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
2855 | ||
2856 | /* Initialize ram interface */ | |
2857 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 2858 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
2859 | |
2860 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
2861 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
2862 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
2863 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
2864 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
2865 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
2866 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
2867 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
2868 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
2869 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
2870 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
2871 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
2872 | } | |
2873 | ||
555382cb | 2874 | sky2_write32(hw, B0_HWE_IMSK, hwe_mask); |
cd28ab6a | 2875 | |
cd28ab6a | 2876 | for (i = 0; i < hw->ports; i++) |
d3bcfbeb | 2877 | sky2_gmac_reset(hw, i); |
cd28ab6a | 2878 | |
cd28ab6a SH |
2879 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2880 | hw->st_idx = 0; | |
2881 | ||
2882 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
2883 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
2884 | ||
2885 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 2886 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
2887 | |
2888 | /* Set the list last index */ | |
793b883e | 2889 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 2890 | |
290d4de5 SH |
2891 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
2892 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a | 2893 | |
290d4de5 SH |
2894 | /* set Status-FIFO ISR watermark */ |
2895 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
2896 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); | |
2897 | else | |
2898 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 2899 | |
290d4de5 | 2900 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
77b3d6a2 SH |
2901 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); |
2902 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
cd28ab6a | 2903 | |
793b883e | 2904 | /* enable status unit */ |
cd28ab6a SH |
2905 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2906 | ||
2907 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2908 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2909 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
e3173832 SH |
2910 | } |
2911 | ||
81906791 SH |
2912 | static void sky2_restart(struct work_struct *work) |
2913 | { | |
2914 | struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); | |
2915 | struct net_device *dev; | |
2916 | int i, err; | |
2917 | ||
81906791 SH |
2918 | rtnl_lock(); |
2919 | sky2_write32(hw, B0_IMSK, 0); | |
2920 | sky2_read32(hw, B0_IMSK); | |
6de16237 | 2921 | napi_disable(&hw->napi); |
81906791 | 2922 | |
81906791 SH |
2923 | for (i = 0; i < hw->ports; i++) { |
2924 | dev = hw->dev[i]; | |
2925 | if (netif_running(dev)) | |
2926 | sky2_down(dev); | |
2927 | } | |
2928 | ||
2929 | sky2_reset(hw); | |
2930 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); | |
6de16237 | 2931 | napi_enable(&hw->napi); |
81906791 SH |
2932 | |
2933 | for (i = 0; i < hw->ports; i++) { | |
2934 | dev = hw->dev[i]; | |
2935 | if (netif_running(dev)) { | |
2936 | err = sky2_up(dev); | |
2937 | if (err) { | |
2938 | printk(KERN_INFO PFX "%s: could not restart %d\n", | |
2939 | dev->name, err); | |
2940 | dev_close(dev); | |
2941 | } | |
2942 | } | |
2943 | } | |
2944 | ||
81906791 SH |
2945 | rtnl_unlock(); |
2946 | } | |
2947 | ||
e3173832 SH |
2948 | static inline u8 sky2_wol_supported(const struct sky2_hw *hw) |
2949 | { | |
2950 | return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; | |
2951 | } | |
2952 | ||
2953 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2954 | { | |
2955 | const struct sky2_port *sky2 = netdev_priv(dev); | |
2956 | ||
2957 | wol->supported = sky2_wol_supported(sky2->hw); | |
2958 | wol->wolopts = sky2->wol; | |
2959 | } | |
2960 | ||
2961 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2962 | { | |
2963 | struct sky2_port *sky2 = netdev_priv(dev); | |
2964 | struct sky2_hw *hw = sky2->hw; | |
cd28ab6a | 2965 | |
e3173832 SH |
2966 | if (wol->wolopts & ~sky2_wol_supported(sky2->hw)) |
2967 | return -EOPNOTSUPP; | |
2968 | ||
2969 | sky2->wol = wol->wolopts; | |
2970 | ||
05745c4a SH |
2971 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || |
2972 | hw->chip_id == CHIP_ID_YUKON_EX || | |
2973 | hw->chip_id == CHIP_ID_YUKON_FE_P) | |
e3173832 SH |
2974 | sky2_write32(hw, B0_CTST, sky2->wol |
2975 | ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF); | |
2976 | ||
2977 | if (!netif_running(dev)) | |
2978 | sky2_wol_init(sky2); | |
cd28ab6a SH |
2979 | return 0; |
2980 | } | |
2981 | ||
28bd181a | 2982 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
cd28ab6a | 2983 | { |
b89165f2 SH |
2984 | if (sky2_is_copper(hw)) { |
2985 | u32 modes = SUPPORTED_10baseT_Half | |
2986 | | SUPPORTED_10baseT_Full | |
2987 | | SUPPORTED_100baseT_Half | |
2988 | | SUPPORTED_100baseT_Full | |
2989 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a | 2990 | |
ea76e635 | 2991 | if (hw->flags & SKY2_HW_GIGABIT) |
cd28ab6a | 2992 | modes |= SUPPORTED_1000baseT_Half |
b89165f2 SH |
2993 | | SUPPORTED_1000baseT_Full; |
2994 | return modes; | |
cd28ab6a | 2995 | } else |
b89165f2 SH |
2996 | return SUPPORTED_1000baseT_Half |
2997 | | SUPPORTED_1000baseT_Full | |
2998 | | SUPPORTED_Autoneg | |
2999 | | SUPPORTED_FIBRE; | |
cd28ab6a SH |
3000 | } |
3001 | ||
793b883e | 3002 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
3003 | { |
3004 | struct sky2_port *sky2 = netdev_priv(dev); | |
3005 | struct sky2_hw *hw = sky2->hw; | |
3006 | ||
3007 | ecmd->transceiver = XCVR_INTERNAL; | |
3008 | ecmd->supported = sky2_supported_modes(hw); | |
3009 | ecmd->phy_address = PHY_ADDR_MARV; | |
b89165f2 | 3010 | if (sky2_is_copper(hw)) { |
cd28ab6a | 3011 | ecmd->port = PORT_TP; |
b89165f2 SH |
3012 | ecmd->speed = sky2->speed; |
3013 | } else { | |
3014 | ecmd->speed = SPEED_1000; | |
cd28ab6a | 3015 | ecmd->port = PORT_FIBRE; |
b89165f2 | 3016 | } |
cd28ab6a SH |
3017 | |
3018 | ecmd->advertising = sky2->advertising; | |
3019 | ecmd->autoneg = sky2->autoneg; | |
cd28ab6a SH |
3020 | ecmd->duplex = sky2->duplex; |
3021 | return 0; | |
3022 | } | |
3023 | ||
3024 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
3025 | { | |
3026 | struct sky2_port *sky2 = netdev_priv(dev); | |
3027 | const struct sky2_hw *hw = sky2->hw; | |
3028 | u32 supported = sky2_supported_modes(hw); | |
3029 | ||
3030 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
3031 | ecmd->advertising = supported; | |
3032 | sky2->duplex = -1; | |
3033 | sky2->speed = -1; | |
3034 | } else { | |
3035 | u32 setting; | |
3036 | ||
793b883e | 3037 | switch (ecmd->speed) { |
cd28ab6a SH |
3038 | case SPEED_1000: |
3039 | if (ecmd->duplex == DUPLEX_FULL) | |
3040 | setting = SUPPORTED_1000baseT_Full; | |
3041 | else if (ecmd->duplex == DUPLEX_HALF) | |
3042 | setting = SUPPORTED_1000baseT_Half; | |
3043 | else | |
3044 | return -EINVAL; | |
3045 | break; | |
3046 | case SPEED_100: | |
3047 | if (ecmd->duplex == DUPLEX_FULL) | |
3048 | setting = SUPPORTED_100baseT_Full; | |
3049 | else if (ecmd->duplex == DUPLEX_HALF) | |
3050 | setting = SUPPORTED_100baseT_Half; | |
3051 | else | |
3052 | return -EINVAL; | |
3053 | break; | |
3054 | ||
3055 | case SPEED_10: | |
3056 | if (ecmd->duplex == DUPLEX_FULL) | |
3057 | setting = SUPPORTED_10baseT_Full; | |
3058 | else if (ecmd->duplex == DUPLEX_HALF) | |
3059 | setting = SUPPORTED_10baseT_Half; | |
3060 | else | |
3061 | return -EINVAL; | |
3062 | break; | |
3063 | default: | |
3064 | return -EINVAL; | |
3065 | } | |
3066 | ||
3067 | if ((setting & supported) == 0) | |
3068 | return -EINVAL; | |
3069 | ||
3070 | sky2->speed = ecmd->speed; | |
3071 | sky2->duplex = ecmd->duplex; | |
3072 | } | |
3073 | ||
3074 | sky2->autoneg = ecmd->autoneg; | |
3075 | sky2->advertising = ecmd->advertising; | |
3076 | ||
d1b139c0 | 3077 | if (netif_running(dev)) { |
1b537565 | 3078 | sky2_phy_reinit(sky2); |
d1b139c0 SH |
3079 | sky2_set_multicast(dev); |
3080 | } | |
cd28ab6a SH |
3081 | |
3082 | return 0; | |
3083 | } | |
3084 | ||
3085 | static void sky2_get_drvinfo(struct net_device *dev, | |
3086 | struct ethtool_drvinfo *info) | |
3087 | { | |
3088 | struct sky2_port *sky2 = netdev_priv(dev); | |
3089 | ||
3090 | strcpy(info->driver, DRV_NAME); | |
3091 | strcpy(info->version, DRV_VERSION); | |
3092 | strcpy(info->fw_version, "N/A"); | |
3093 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
3094 | } | |
3095 | ||
3096 | static const struct sky2_stat { | |
793b883e SH |
3097 | char name[ETH_GSTRING_LEN]; |
3098 | u16 offset; | |
cd28ab6a SH |
3099 | } sky2_stats[] = { |
3100 | { "tx_bytes", GM_TXO_OK_HI }, | |
3101 | { "rx_bytes", GM_RXO_OK_HI }, | |
3102 | { "tx_broadcast", GM_TXF_BC_OK }, | |
3103 | { "rx_broadcast", GM_RXF_BC_OK }, | |
3104 | { "tx_multicast", GM_TXF_MC_OK }, | |
3105 | { "rx_multicast", GM_RXF_MC_OK }, | |
3106 | { "tx_unicast", GM_TXF_UC_OK }, | |
3107 | { "rx_unicast", GM_RXF_UC_OK }, | |
3108 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
3109 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
eadfa7dd | 3110 | { "collisions", GM_TXF_COL }, |
cd28ab6a SH |
3111 | { "late_collision",GM_TXF_LAT_COL }, |
3112 | { "aborted", GM_TXF_ABO_COL }, | |
eadfa7dd | 3113 | { "single_collisions", GM_TXF_SNG_COL }, |
cd28ab6a | 3114 | { "multi_collisions", GM_TXF_MUL_COL }, |
eadfa7dd | 3115 | |
d2604540 | 3116 | { "rx_short", GM_RXF_SHT }, |
cd28ab6a | 3117 | { "rx_runt", GM_RXE_FRAG }, |
eadfa7dd SH |
3118 | { "rx_64_byte_packets", GM_RXF_64B }, |
3119 | { "rx_65_to_127_byte_packets", GM_RXF_127B }, | |
3120 | { "rx_128_to_255_byte_packets", GM_RXF_255B }, | |
3121 | { "rx_256_to_511_byte_packets", GM_RXF_511B }, | |
3122 | { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, | |
3123 | { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, | |
3124 | { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, | |
cd28ab6a | 3125 | { "rx_too_long", GM_RXF_LNG_ERR }, |
eadfa7dd SH |
3126 | { "rx_fifo_overflow", GM_RXE_FIFO_OV }, |
3127 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
cd28ab6a | 3128 | { "rx_fcs_error", GM_RXF_FCS_ERR }, |
eadfa7dd SH |
3129 | |
3130 | { "tx_64_byte_packets", GM_TXF_64B }, | |
3131 | { "tx_65_to_127_byte_packets", GM_TXF_127B }, | |
3132 | { "tx_128_to_255_byte_packets", GM_TXF_255B }, | |
3133 | { "tx_256_to_511_byte_packets", GM_TXF_511B }, | |
3134 | { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, | |
3135 | { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, | |
3136 | { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, | |
3137 | { "tx_fifo_underrun", GM_TXE_FIFO_UR }, | |
cd28ab6a SH |
3138 | }; |
3139 | ||
cd28ab6a SH |
3140 | static u32 sky2_get_rx_csum(struct net_device *dev) |
3141 | { | |
3142 | struct sky2_port *sky2 = netdev_priv(dev); | |
3143 | ||
3144 | return sky2->rx_csum; | |
3145 | } | |
3146 | ||
3147 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
3148 | { | |
3149 | struct sky2_port *sky2 = netdev_priv(dev); | |
3150 | ||
3151 | sky2->rx_csum = data; | |
793b883e | 3152 | |
cd28ab6a SH |
3153 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
3154 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
3155 | ||
3156 | return 0; | |
3157 | } | |
3158 | ||
3159 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
3160 | { | |
3161 | struct sky2_port *sky2 = netdev_priv(netdev); | |
3162 | return sky2->msg_enable; | |
3163 | } | |
3164 | ||
9a7ae0a9 SH |
3165 | static int sky2_nway_reset(struct net_device *dev) |
3166 | { | |
3167 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 | 3168 | |
16ad91e1 | 3169 | if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE) |
9a7ae0a9 SH |
3170 | return -EINVAL; |
3171 | ||
1b537565 | 3172 | sky2_phy_reinit(sky2); |
d1b139c0 | 3173 | sky2_set_multicast(dev); |
9a7ae0a9 SH |
3174 | |
3175 | return 0; | |
3176 | } | |
3177 | ||
793b883e | 3178 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
3179 | { |
3180 | struct sky2_hw *hw = sky2->hw; | |
3181 | unsigned port = sky2->port; | |
3182 | int i; | |
3183 | ||
3184 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 3185 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 3186 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 3187 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 3188 | |
793b883e | 3189 | for (i = 2; i < count; i++) |
cd28ab6a SH |
3190 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
3191 | } | |
3192 | ||
cd28ab6a SH |
3193 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
3194 | { | |
3195 | struct sky2_port *sky2 = netdev_priv(netdev); | |
3196 | sky2->msg_enable = value; | |
3197 | } | |
3198 | ||
b9f2c044 | 3199 | static int sky2_get_sset_count(struct net_device *dev, int sset) |
cd28ab6a | 3200 | { |
b9f2c044 JG |
3201 | switch (sset) { |
3202 | case ETH_SS_STATS: | |
3203 | return ARRAY_SIZE(sky2_stats); | |
3204 | default: | |
3205 | return -EOPNOTSUPP; | |
3206 | } | |
cd28ab6a SH |
3207 | } |
3208 | ||
3209 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 3210 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
3211 | { |
3212 | struct sky2_port *sky2 = netdev_priv(dev); | |
3213 | ||
793b883e | 3214 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
3215 | } |
3216 | ||
793b883e | 3217 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
3218 | { |
3219 | int i; | |
3220 | ||
3221 | switch (stringset) { | |
3222 | case ETH_SS_STATS: | |
3223 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
3224 | memcpy(data + i * ETH_GSTRING_LEN, | |
3225 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
3226 | break; | |
3227 | } | |
3228 | } | |
3229 | ||
cd28ab6a SH |
3230 | static int sky2_set_mac_address(struct net_device *dev, void *p) |
3231 | { | |
3232 | struct sky2_port *sky2 = netdev_priv(dev); | |
a8ab1ec0 SH |
3233 | struct sky2_hw *hw = sky2->hw; |
3234 | unsigned port = sky2->port; | |
3235 | const struct sockaddr *addr = p; | |
cd28ab6a SH |
3236 | |
3237 | if (!is_valid_ether_addr(addr->sa_data)) | |
3238 | return -EADDRNOTAVAIL; | |
3239 | ||
cd28ab6a | 3240 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
a8ab1ec0 | 3241 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
cd28ab6a | 3242 | dev->dev_addr, ETH_ALEN); |
a8ab1ec0 | 3243 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
cd28ab6a | 3244 | dev->dev_addr, ETH_ALEN); |
1b537565 | 3245 | |
a8ab1ec0 SH |
3246 | /* virtual address for data */ |
3247 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
3248 | ||
3249 | /* physical address: used for pause frames */ | |
3250 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
1b537565 SH |
3251 | |
3252 | return 0; | |
cd28ab6a SH |
3253 | } |
3254 | ||
a052b52f SH |
3255 | static void inline sky2_add_filter(u8 filter[8], const u8 *addr) |
3256 | { | |
3257 | u32 bit; | |
3258 | ||
3259 | bit = ether_crc(ETH_ALEN, addr) & 63; | |
3260 | filter[bit >> 3] |= 1 << (bit & 7); | |
3261 | } | |
3262 | ||
cd28ab6a SH |
3263 | static void sky2_set_multicast(struct net_device *dev) |
3264 | { | |
3265 | struct sky2_port *sky2 = netdev_priv(dev); | |
3266 | struct sky2_hw *hw = sky2->hw; | |
3267 | unsigned port = sky2->port; | |
3268 | struct dev_mc_list *list = dev->mc_list; | |
3269 | u16 reg; | |
3270 | u8 filter[8]; | |
a052b52f SH |
3271 | int rx_pause; |
3272 | static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; | |
cd28ab6a | 3273 | |
a052b52f | 3274 | rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); |
cd28ab6a SH |
3275 | memset(filter, 0, sizeof(filter)); |
3276 | ||
3277 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
3278 | reg |= GM_RXCR_UCF_ENA; | |
3279 | ||
d571b694 | 3280 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 3281 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
a052b52f | 3282 | else if (dev->flags & IFF_ALLMULTI) |
cd28ab6a | 3283 | memset(filter, 0xff, sizeof(filter)); |
a052b52f | 3284 | else if (dev->mc_count == 0 && !rx_pause) |
cd28ab6a SH |
3285 | reg &= ~GM_RXCR_MCF_ENA; |
3286 | else { | |
3287 | int i; | |
3288 | reg |= GM_RXCR_MCF_ENA; | |
3289 | ||
a052b52f SH |
3290 | if (rx_pause) |
3291 | sky2_add_filter(filter, pause_mc_addr); | |
3292 | ||
3293 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) | |
3294 | sky2_add_filter(filter, list->dmi_addr); | |
cd28ab6a SH |
3295 | } |
3296 | ||
cd28ab6a | 3297 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 3298 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 3299 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 3300 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 3301 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 3302 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 3303 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 3304 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
3305 | |
3306 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
3307 | } | |
3308 | ||
3309 | /* Can have one global because blinking is controlled by | |
3310 | * ethtool and that is always under RTNL mutex | |
3311 | */ | |
91c86df5 | 3312 | static void sky2_led(struct sky2_hw *hw, unsigned port, int on) |
cd28ab6a | 3313 | { |
793b883e SH |
3314 | u16 pg; |
3315 | ||
793b883e SH |
3316 | switch (hw->chip_id) { |
3317 | case CHIP_ID_YUKON_XL: | |
3318 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
3319 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
3320 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3321 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
3322 | PHY_M_LEDC_INIT_CTRL(7) | | |
3323 | PHY_M_LEDC_STA1_CTRL(7) | | |
3324 | PHY_M_LEDC_STA0_CTRL(7)) | |
3325 | : 0); | |
3326 | ||
3327 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
3328 | break; | |
3329 | ||
3330 | default: | |
3331 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
0efdf262 SH |
3332 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
3333 | on ? PHY_M_LED_ALL : 0); | |
793b883e | 3334 | } |
cd28ab6a SH |
3335 | } |
3336 | ||
3337 | /* blink LED's for finding board */ | |
3338 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
3339 | { | |
3340 | struct sky2_port *sky2 = netdev_priv(dev); | |
3341 | struct sky2_hw *hw = sky2->hw; | |
3342 | unsigned port = sky2->port; | |
793b883e | 3343 | u16 ledctrl, ledover = 0; |
cd28ab6a | 3344 | long ms; |
91c86df5 | 3345 | int interrupted; |
cd28ab6a SH |
3346 | int onoff = 1; |
3347 | ||
793b883e | 3348 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
3349 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
3350 | else | |
3351 | ms = data * 1000; | |
3352 | ||
3353 | /* save initial values */ | |
e07b1aa8 | 3354 | spin_lock_bh(&sky2->phy_lock); |
793b883e SH |
3355 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
3356 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
3357 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
3358 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
3359 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
3360 | } else { | |
3361 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
3362 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
3363 | } | |
cd28ab6a | 3364 | |
91c86df5 SH |
3365 | interrupted = 0; |
3366 | while (!interrupted && ms > 0) { | |
cd28ab6a SH |
3367 | sky2_led(hw, port, onoff); |
3368 | onoff = !onoff; | |
3369 | ||
e07b1aa8 | 3370 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 3371 | interrupted = msleep_interruptible(250); |
e07b1aa8 | 3372 | spin_lock_bh(&sky2->phy_lock); |
91c86df5 | 3373 | |
cd28ab6a SH |
3374 | ms -= 250; |
3375 | } | |
3376 | ||
3377 | /* resume regularly scheduled programming */ | |
793b883e SH |
3378 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
3379 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
3380 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
3381 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
3382 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
3383 | } else { | |
3384 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
3385 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
3386 | } | |
e07b1aa8 | 3387 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
3388 | |
3389 | return 0; | |
3390 | } | |
3391 | ||
3392 | static void sky2_get_pauseparam(struct net_device *dev, | |
3393 | struct ethtool_pauseparam *ecmd) | |
3394 | { | |
3395 | struct sky2_port *sky2 = netdev_priv(dev); | |
3396 | ||
16ad91e1 SH |
3397 | switch (sky2->flow_mode) { |
3398 | case FC_NONE: | |
3399 | ecmd->tx_pause = ecmd->rx_pause = 0; | |
3400 | break; | |
3401 | case FC_TX: | |
3402 | ecmd->tx_pause = 1, ecmd->rx_pause = 0; | |
3403 | break; | |
3404 | case FC_RX: | |
3405 | ecmd->tx_pause = 0, ecmd->rx_pause = 1; | |
3406 | break; | |
3407 | case FC_BOTH: | |
3408 | ecmd->tx_pause = ecmd->rx_pause = 1; | |
3409 | } | |
3410 | ||
cd28ab6a SH |
3411 | ecmd->autoneg = sky2->autoneg; |
3412 | } | |
3413 | ||
3414 | static int sky2_set_pauseparam(struct net_device *dev, | |
3415 | struct ethtool_pauseparam *ecmd) | |
3416 | { | |
3417 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a SH |
3418 | |
3419 | sky2->autoneg = ecmd->autoneg; | |
16ad91e1 | 3420 | sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); |
cd28ab6a | 3421 | |
16ad91e1 SH |
3422 | if (netif_running(dev)) |
3423 | sky2_phy_reinit(sky2); | |
cd28ab6a | 3424 | |
2eaba1a2 | 3425 | return 0; |
cd28ab6a SH |
3426 | } |
3427 | ||
fb17358f SH |
3428 | static int sky2_get_coalesce(struct net_device *dev, |
3429 | struct ethtool_coalesce *ecmd) | |
3430 | { | |
3431 | struct sky2_port *sky2 = netdev_priv(dev); | |
3432 | struct sky2_hw *hw = sky2->hw; | |
3433 | ||
3434 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
3435 | ecmd->tx_coalesce_usecs = 0; | |
3436 | else { | |
3437 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
3438 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
3439 | } | |
3440 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
3441 | ||
3442 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
3443 | ecmd->rx_coalesce_usecs = 0; | |
3444 | else { | |
3445 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
3446 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
3447 | } | |
3448 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
3449 | ||
3450 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
3451 | ecmd->rx_coalesce_usecs_irq = 0; | |
3452 | else { | |
3453 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
3454 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
3455 | } | |
3456 | ||
3457 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
3458 | ||
3459 | return 0; | |
3460 | } | |
3461 | ||
3462 | /* Note: this affect both ports */ | |
3463 | static int sky2_set_coalesce(struct net_device *dev, | |
3464 | struct ethtool_coalesce *ecmd) | |
3465 | { | |
3466 | struct sky2_port *sky2 = netdev_priv(dev); | |
3467 | struct sky2_hw *hw = sky2->hw; | |
77b3d6a2 | 3468 | const u32 tmax = sky2_clk2us(hw, 0x0ffffff); |
fb17358f | 3469 | |
77b3d6a2 SH |
3470 | if (ecmd->tx_coalesce_usecs > tmax || |
3471 | ecmd->rx_coalesce_usecs > tmax || | |
3472 | ecmd->rx_coalesce_usecs_irq > tmax) | |
fb17358f SH |
3473 | return -EINVAL; |
3474 | ||
ff81fbbe | 3475 | if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1) |
fb17358f | 3476 | return -EINVAL; |
ff81fbbe | 3477 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
fb17358f | 3478 | return -EINVAL; |
ff81fbbe | 3479 | if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING) |
fb17358f SH |
3480 | return -EINVAL; |
3481 | ||
3482 | if (ecmd->tx_coalesce_usecs == 0) | |
3483 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
3484 | else { | |
3485 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
3486 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
3487 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
3488 | } | |
3489 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
3490 | ||
3491 | if (ecmd->rx_coalesce_usecs == 0) | |
3492 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
3493 | else { | |
3494 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
3495 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
3496 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
3497 | } | |
3498 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
3499 | ||
3500 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
3501 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
3502 | else { | |
d28d4870 | 3503 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
fb17358f SH |
3504 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
3505 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
3506 | } | |
3507 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
3508 | return 0; | |
3509 | } | |
3510 | ||
793b883e SH |
3511 | static void sky2_get_ringparam(struct net_device *dev, |
3512 | struct ethtool_ringparam *ering) | |
3513 | { | |
3514 | struct sky2_port *sky2 = netdev_priv(dev); | |
3515 | ||
3516 | ering->rx_max_pending = RX_MAX_PENDING; | |
3517 | ering->rx_mini_max_pending = 0; | |
3518 | ering->rx_jumbo_max_pending = 0; | |
3519 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
3520 | ||
3521 | ering->rx_pending = sky2->rx_pending; | |
3522 | ering->rx_mini_pending = 0; | |
3523 | ering->rx_jumbo_pending = 0; | |
3524 | ering->tx_pending = sky2->tx_pending; | |
3525 | } | |
3526 | ||
3527 | static int sky2_set_ringparam(struct net_device *dev, | |
3528 | struct ethtool_ringparam *ering) | |
3529 | { | |
3530 | struct sky2_port *sky2 = netdev_priv(dev); | |
3531 | int err = 0; | |
3532 | ||
3533 | if (ering->rx_pending > RX_MAX_PENDING || | |
3534 | ering->rx_pending < 8 || | |
3535 | ering->tx_pending < MAX_SKB_TX_LE || | |
3536 | ering->tx_pending > TX_RING_SIZE - 1) | |
3537 | return -EINVAL; | |
3538 | ||
3539 | if (netif_running(dev)) | |
3540 | sky2_down(dev); | |
3541 | ||
3542 | sky2->rx_pending = ering->rx_pending; | |
3543 | sky2->tx_pending = ering->tx_pending; | |
3544 | ||
1b537565 | 3545 | if (netif_running(dev)) { |
793b883e | 3546 | err = sky2_up(dev); |
1b537565 SH |
3547 | if (err) |
3548 | dev_close(dev); | |
6ed995bb SH |
3549 | else |
3550 | sky2_set_multicast(dev); | |
1b537565 | 3551 | } |
793b883e SH |
3552 | |
3553 | return err; | |
3554 | } | |
3555 | ||
793b883e SH |
3556 | static int sky2_get_regs_len(struct net_device *dev) |
3557 | { | |
6e4cbb34 | 3558 | return 0x4000; |
793b883e SH |
3559 | } |
3560 | ||
3561 | /* | |
3562 | * Returns copy of control register region | |
3ead5db7 | 3563 | * Note: ethtool_get_regs always provides full size (16k) buffer |
793b883e SH |
3564 | */ |
3565 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
3566 | void *p) | |
3567 | { | |
3568 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 3569 | const void __iomem *io = sky2->hw->regs; |
295b54c4 | 3570 | unsigned int b; |
793b883e SH |
3571 | |
3572 | regs->version = 1; | |
793b883e | 3573 | |
295b54c4 SH |
3574 | for (b = 0; b < 128; b++) { |
3575 | /* This complicated switch statement is to make sure and | |
3576 | * only access regions that are unreserved. | |
3577 | * Some blocks are only valid on dual port cards. | |
3578 | * and block 3 has some special diagnostic registers that | |
3579 | * are poison. | |
3580 | */ | |
3581 | switch (b) { | |
3582 | case 3: | |
3583 | /* skip diagnostic ram region */ | |
3584 | memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); | |
3585 | break; | |
3ead5db7 | 3586 | |
295b54c4 SH |
3587 | /* dual port cards only */ |
3588 | case 5: /* Tx Arbiter 2 */ | |
3589 | case 9: /* RX2 */ | |
3590 | case 14 ... 15: /* TX2 */ | |
3591 | case 17: case 19: /* Ram Buffer 2 */ | |
3592 | case 22 ... 23: /* Tx Ram Buffer 2 */ | |
3593 | case 25: /* Rx MAC Fifo 1 */ | |
3594 | case 27: /* Tx MAC Fifo 2 */ | |
3595 | case 31: /* GPHY 2 */ | |
3596 | case 40 ... 47: /* Pattern Ram 2 */ | |
3597 | case 52: case 54: /* TCP Segmentation 2 */ | |
3598 | case 112 ... 116: /* GMAC 2 */ | |
3599 | if (sky2->hw->ports == 1) | |
3600 | goto reserved; | |
3601 | /* fall through */ | |
3602 | case 0: /* Control */ | |
3603 | case 2: /* Mac address */ | |
3604 | case 4: /* Tx Arbiter 1 */ | |
3605 | case 7: /* PCI express reg */ | |
3606 | case 8: /* RX1 */ | |
3607 | case 12 ... 13: /* TX1 */ | |
3608 | case 16: case 18:/* Rx Ram Buffer 1 */ | |
3609 | case 20 ... 21: /* Tx Ram Buffer 1 */ | |
3610 | case 24: /* Rx MAC Fifo 1 */ | |
3611 | case 26: /* Tx MAC Fifo 1 */ | |
3612 | case 28 ... 29: /* Descriptor and status unit */ | |
3613 | case 30: /* GPHY 1*/ | |
3614 | case 32 ... 39: /* Pattern Ram 1 */ | |
3615 | case 48: case 50: /* TCP Segmentation 1 */ | |
3616 | case 56 ... 60: /* PCI space */ | |
3617 | case 80 ... 84: /* GMAC 1 */ | |
3618 | memcpy_fromio(p, io, 128); | |
3619 | break; | |
3620 | default: | |
3621 | reserved: | |
3622 | memset(p, 0, 128); | |
3623 | } | |
3ead5db7 | 3624 | |
295b54c4 SH |
3625 | p += 128; |
3626 | io += 128; | |
3627 | } | |
793b883e | 3628 | } |
cd28ab6a | 3629 | |
b628ed98 SH |
3630 | /* In order to do Jumbo packets on these chips, need to turn off the |
3631 | * transmit store/forward. Therefore checksum offload won't work. | |
3632 | */ | |
3633 | static int no_tx_offload(struct net_device *dev) | |
3634 | { | |
3635 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3636 | const struct sky2_hw *hw = sky2->hw; | |
3637 | ||
69161611 | 3638 | return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U; |
b628ed98 SH |
3639 | } |
3640 | ||
3641 | static int sky2_set_tx_csum(struct net_device *dev, u32 data) | |
3642 | { | |
3643 | if (data && no_tx_offload(dev)) | |
3644 | return -EINVAL; | |
3645 | ||
3646 | return ethtool_op_set_tx_csum(dev, data); | |
3647 | } | |
3648 | ||
3649 | ||
3650 | static int sky2_set_tso(struct net_device *dev, u32 data) | |
3651 | { | |
3652 | if (data && no_tx_offload(dev)) | |
3653 | return -EINVAL; | |
3654 | ||
3655 | return ethtool_op_set_tso(dev, data); | |
3656 | } | |
3657 | ||
f4331a6d SH |
3658 | static int sky2_get_eeprom_len(struct net_device *dev) |
3659 | { | |
3660 | struct sky2_port *sky2 = netdev_priv(dev); | |
3661 | u16 reg2; | |
3662 | ||
167f53d0 | 3663 | pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, ®2); |
f4331a6d SH |
3664 | return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); |
3665 | } | |
3666 | ||
167f53d0 | 3667 | static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset) |
f4331a6d | 3668 | { |
167f53d0 | 3669 | u32 val; |
f4331a6d | 3670 | |
167f53d0 SH |
3671 | pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset); |
3672 | ||
3673 | do { | |
3674 | pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); | |
3675 | } while (!(offset & PCI_VPD_ADDR_F)); | |
3676 | ||
3677 | pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val); | |
3678 | return val; | |
f4331a6d SH |
3679 | } |
3680 | ||
167f53d0 | 3681 | static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val) |
f4331a6d | 3682 | { |
167f53d0 SH |
3683 | pci_write_config_word(pdev, cap + PCI_VPD_DATA, val); |
3684 | pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); | |
f4331a6d | 3685 | do { |
167f53d0 SH |
3686 | pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); |
3687 | } while (offset & PCI_VPD_ADDR_F); | |
f4331a6d SH |
3688 | } |
3689 | ||
3690 | static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
3691 | u8 *data) | |
3692 | { | |
3693 | struct sky2_port *sky2 = netdev_priv(dev); | |
3694 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); | |
3695 | int length = eeprom->len; | |
3696 | u16 offset = eeprom->offset; | |
3697 | ||
3698 | if (!cap) | |
3699 | return -EINVAL; | |
3700 | ||
3701 | eeprom->magic = SKY2_EEPROM_MAGIC; | |
3702 | ||
3703 | while (length > 0) { | |
167f53d0 | 3704 | u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset); |
f4331a6d SH |
3705 | int n = min_t(int, length, sizeof(val)); |
3706 | ||
3707 | memcpy(data, &val, n); | |
3708 | length -= n; | |
3709 | data += n; | |
3710 | offset += n; | |
3711 | } | |
3712 | return 0; | |
3713 | } | |
3714 | ||
3715 | static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
3716 | u8 *data) | |
3717 | { | |
3718 | struct sky2_port *sky2 = netdev_priv(dev); | |
3719 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); | |
3720 | int length = eeprom->len; | |
3721 | u16 offset = eeprom->offset; | |
3722 | ||
3723 | if (!cap) | |
3724 | return -EINVAL; | |
3725 | ||
3726 | if (eeprom->magic != SKY2_EEPROM_MAGIC) | |
3727 | return -EINVAL; | |
3728 | ||
3729 | while (length > 0) { | |
3730 | u32 val; | |
3731 | int n = min_t(int, length, sizeof(val)); | |
3732 | ||
3733 | if (n < sizeof(val)) | |
167f53d0 | 3734 | val = sky2_vpd_read(sky2->hw->pdev, cap, offset); |
f4331a6d SH |
3735 | memcpy(&val, data, n); |
3736 | ||
167f53d0 | 3737 | sky2_vpd_write(sky2->hw->pdev, cap, offset, val); |
f4331a6d SH |
3738 | |
3739 | length -= n; | |
3740 | data += n; | |
3741 | offset += n; | |
3742 | } | |
3743 | return 0; | |
3744 | } | |
3745 | ||
3746 | ||
7282d491 | 3747 | static const struct ethtool_ops sky2_ethtool_ops = { |
f4331a6d SH |
3748 | .get_settings = sky2_get_settings, |
3749 | .set_settings = sky2_set_settings, | |
3750 | .get_drvinfo = sky2_get_drvinfo, | |
3751 | .get_wol = sky2_get_wol, | |
3752 | .set_wol = sky2_set_wol, | |
3753 | .get_msglevel = sky2_get_msglevel, | |
3754 | .set_msglevel = sky2_set_msglevel, | |
3755 | .nway_reset = sky2_nway_reset, | |
3756 | .get_regs_len = sky2_get_regs_len, | |
3757 | .get_regs = sky2_get_regs, | |
3758 | .get_link = ethtool_op_get_link, | |
3759 | .get_eeprom_len = sky2_get_eeprom_len, | |
3760 | .get_eeprom = sky2_get_eeprom, | |
3761 | .set_eeprom = sky2_set_eeprom, | |
f4331a6d | 3762 | .set_sg = ethtool_op_set_sg, |
f4331a6d | 3763 | .set_tx_csum = sky2_set_tx_csum, |
f4331a6d SH |
3764 | .set_tso = sky2_set_tso, |
3765 | .get_rx_csum = sky2_get_rx_csum, | |
3766 | .set_rx_csum = sky2_set_rx_csum, | |
3767 | .get_strings = sky2_get_strings, | |
3768 | .get_coalesce = sky2_get_coalesce, | |
3769 | .set_coalesce = sky2_set_coalesce, | |
3770 | .get_ringparam = sky2_get_ringparam, | |
3771 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
3772 | .get_pauseparam = sky2_get_pauseparam, |
3773 | .set_pauseparam = sky2_set_pauseparam, | |
f4331a6d | 3774 | .phys_id = sky2_phys_id, |
b9f2c044 | 3775 | .get_sset_count = sky2_get_sset_count, |
cd28ab6a SH |
3776 | .get_ethtool_stats = sky2_get_ethtool_stats, |
3777 | }; | |
3778 | ||
3cf26753 SH |
3779 | #ifdef CONFIG_SKY2_DEBUG |
3780 | ||
3781 | static struct dentry *sky2_debug; | |
3782 | ||
3783 | static int sky2_debug_show(struct seq_file *seq, void *v) | |
3784 | { | |
3785 | struct net_device *dev = seq->private; | |
3786 | const struct sky2_port *sky2 = netdev_priv(dev); | |
bea3348e | 3787 | struct sky2_hw *hw = sky2->hw; |
3cf26753 SH |
3788 | unsigned port = sky2->port; |
3789 | unsigned idx, last; | |
3790 | int sop; | |
3791 | ||
3792 | if (!netif_running(dev)) | |
3793 | return -ENETDOWN; | |
3794 | ||
3795 | seq_printf(seq, "IRQ src=%x mask=%x control=%x\n", | |
3796 | sky2_read32(hw, B0_ISRC), | |
3797 | sky2_read32(hw, B0_IMSK), | |
3798 | sky2_read32(hw, B0_Y2_SP_ICR)); | |
3799 | ||
bea3348e | 3800 | napi_disable(&hw->napi); |
3cf26753 SH |
3801 | last = sky2_read16(hw, STAT_PUT_IDX); |
3802 | ||
3803 | if (hw->st_idx == last) | |
3804 | seq_puts(seq, "Status ring (empty)\n"); | |
3805 | else { | |
3806 | seq_puts(seq, "Status ring\n"); | |
3807 | for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE; | |
3808 | idx = RING_NEXT(idx, STATUS_RING_SIZE)) { | |
3809 | const struct sky2_status_le *le = hw->st_le + idx; | |
3810 | seq_printf(seq, "[%d] %#x %d %#x\n", | |
3811 | idx, le->opcode, le->length, le->status); | |
3812 | } | |
3813 | seq_puts(seq, "\n"); | |
3814 | } | |
3815 | ||
3816 | seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", | |
3817 | sky2->tx_cons, sky2->tx_prod, | |
3818 | sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), | |
3819 | sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); | |
3820 | ||
3821 | /* Dump contents of tx ring */ | |
3822 | sop = 1; | |
3823 | for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE; | |
3824 | idx = RING_NEXT(idx, TX_RING_SIZE)) { | |
3825 | const struct sky2_tx_le *le = sky2->tx_le + idx; | |
3826 | u32 a = le32_to_cpu(le->addr); | |
3827 | ||
3828 | if (sop) | |
3829 | seq_printf(seq, "%u:", idx); | |
3830 | sop = 0; | |
3831 | ||
3832 | switch(le->opcode & ~HW_OWNER) { | |
3833 | case OP_ADDR64: | |
3834 | seq_printf(seq, " %#x:", a); | |
3835 | break; | |
3836 | case OP_LRGLEN: | |
3837 | seq_printf(seq, " mtu=%d", a); | |
3838 | break; | |
3839 | case OP_VLAN: | |
3840 | seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); | |
3841 | break; | |
3842 | case OP_TCPLISW: | |
3843 | seq_printf(seq, " csum=%#x", a); | |
3844 | break; | |
3845 | case OP_LARGESEND: | |
3846 | seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); | |
3847 | break; | |
3848 | case OP_PACKET: | |
3849 | seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); | |
3850 | break; | |
3851 | case OP_BUFFER: | |
3852 | seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); | |
3853 | break; | |
3854 | default: | |
3855 | seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, | |
3856 | a, le16_to_cpu(le->length)); | |
3857 | } | |
3858 | ||
3859 | if (le->ctrl & EOP) { | |
3860 | seq_putc(seq, '\n'); | |
3861 | sop = 1; | |
3862 | } | |
3863 | } | |
3864 | ||
3865 | seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", | |
3866 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), | |
3867 | last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), | |
3868 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); | |
3869 | ||
bea3348e | 3870 | napi_enable(&hw->napi); |
3cf26753 SH |
3871 | return 0; |
3872 | } | |
3873 | ||
3874 | static int sky2_debug_open(struct inode *inode, struct file *file) | |
3875 | { | |
3876 | return single_open(file, sky2_debug_show, inode->i_private); | |
3877 | } | |
3878 | ||
3879 | static const struct file_operations sky2_debug_fops = { | |
3880 | .owner = THIS_MODULE, | |
3881 | .open = sky2_debug_open, | |
3882 | .read = seq_read, | |
3883 | .llseek = seq_lseek, | |
3884 | .release = single_release, | |
3885 | }; | |
3886 | ||
3887 | /* | |
3888 | * Use network device events to create/remove/rename | |
3889 | * debugfs file entries | |
3890 | */ | |
3891 | static int sky2_device_event(struct notifier_block *unused, | |
3892 | unsigned long event, void *ptr) | |
3893 | { | |
3894 | struct net_device *dev = ptr; | |
5b296bc9 | 3895 | struct sky2_port *sky2 = netdev_priv(dev); |
3cf26753 | 3896 | |
5b296bc9 SH |
3897 | if (dev->open != sky2_up || !sky2_debug) |
3898 | return NOTIFY_DONE; | |
3cf26753 | 3899 | |
5b296bc9 SH |
3900 | switch(event) { |
3901 | case NETDEV_CHANGENAME: | |
3902 | if (sky2->debugfs) { | |
3903 | sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, | |
3904 | sky2_debug, dev->name); | |
3905 | } | |
3906 | break; | |
3cf26753 | 3907 | |
5b296bc9 SH |
3908 | case NETDEV_GOING_DOWN: |
3909 | if (sky2->debugfs) { | |
3910 | printk(KERN_DEBUG PFX "%s: remove debugfs\n", | |
3911 | dev->name); | |
3912 | debugfs_remove(sky2->debugfs); | |
3913 | sky2->debugfs = NULL; | |
3cf26753 | 3914 | } |
5b296bc9 SH |
3915 | break; |
3916 | ||
3917 | case NETDEV_UP: | |
3918 | sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, | |
3919 | sky2_debug, dev, | |
3920 | &sky2_debug_fops); | |
3921 | if (IS_ERR(sky2->debugfs)) | |
3922 | sky2->debugfs = NULL; | |
3cf26753 SH |
3923 | } |
3924 | ||
3925 | return NOTIFY_DONE; | |
3926 | } | |
3927 | ||
3928 | static struct notifier_block sky2_notifier = { | |
3929 | .notifier_call = sky2_device_event, | |
3930 | }; | |
3931 | ||
3932 | ||
3933 | static __init void sky2_debug_init(void) | |
3934 | { | |
3935 | struct dentry *ent; | |
3936 | ||
3937 | ent = debugfs_create_dir("sky2", NULL); | |
3938 | if (!ent || IS_ERR(ent)) | |
3939 | return; | |
3940 | ||
3941 | sky2_debug = ent; | |
3942 | register_netdevice_notifier(&sky2_notifier); | |
3943 | } | |
3944 | ||
3945 | static __exit void sky2_debug_cleanup(void) | |
3946 | { | |
3947 | if (sky2_debug) { | |
3948 | unregister_netdevice_notifier(&sky2_notifier); | |
3949 | debugfs_remove(sky2_debug); | |
3950 | sky2_debug = NULL; | |
3951 | } | |
3952 | } | |
3953 | ||
3954 | #else | |
3955 | #define sky2_debug_init() | |
3956 | #define sky2_debug_cleanup() | |
3957 | #endif | |
3958 | ||
3959 | ||
cd28ab6a SH |
3960 | /* Initialize network device */ |
3961 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
e3173832 SH |
3962 | unsigned port, |
3963 | int highmem, int wol) | |
cd28ab6a SH |
3964 | { |
3965 | struct sky2_port *sky2; | |
3966 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
3967 | ||
3968 | if (!dev) { | |
898eb71c | 3969 | dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); |
cd28ab6a SH |
3970 | return NULL; |
3971 | } | |
3972 | ||
cd28ab6a | 3973 | SET_NETDEV_DEV(dev, &hw->pdev->dev); |
ef743d33 | 3974 | dev->irq = hw->pdev->irq; |
cd28ab6a SH |
3975 | dev->open = sky2_up; |
3976 | dev->stop = sky2_down; | |
ef743d33 | 3977 | dev->do_ioctl = sky2_ioctl; |
cd28ab6a | 3978 | dev->hard_start_xmit = sky2_xmit_frame; |
cd28ab6a SH |
3979 | dev->set_multicast_list = sky2_set_multicast; |
3980 | dev->set_mac_address = sky2_set_mac_address; | |
3981 | dev->change_mtu = sky2_change_mtu; | |
3982 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
3983 | dev->tx_timeout = sky2_tx_timeout; | |
3984 | dev->watchdog_timeo = TX_WATCHDOG; | |
cd28ab6a | 3985 | #ifdef CONFIG_NET_POLL_CONTROLLER |
bea3348e | 3986 | dev->poll_controller = sky2_netpoll; |
cd28ab6a | 3987 | #endif |
cd28ab6a SH |
3988 | |
3989 | sky2 = netdev_priv(dev); | |
3990 | sky2->netdev = dev; | |
3991 | sky2->hw = hw; | |
3992 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
3993 | ||
cd28ab6a SH |
3994 | /* Auto speed and flow control */ |
3995 | sky2->autoneg = AUTONEG_ENABLE; | |
16ad91e1 SH |
3996 | sky2->flow_mode = FC_BOTH; |
3997 | ||
cd28ab6a SH |
3998 | sky2->duplex = -1; |
3999 | sky2->speed = -1; | |
4000 | sky2->advertising = sky2_supported_modes(hw); | |
ee7abb04 | 4001 | sky2->rx_csum = 1; |
e3173832 | 4002 | sky2->wol = wol; |
75d070c5 | 4003 | |
e07b1aa8 | 4004 | spin_lock_init(&sky2->phy_lock); |
793b883e | 4005 | sky2->tx_pending = TX_DEF_PENDING; |
290d4de5 | 4006 | sky2->rx_pending = RX_DEF_PENDING; |
cd28ab6a SH |
4007 | |
4008 | hw->dev[port] = dev; | |
4009 | ||
4010 | sky2->port = port; | |
4011 | ||
4a50a876 | 4012 | dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a SH |
4013 | if (highmem) |
4014 | dev->features |= NETIF_F_HIGHDMA; | |
cd28ab6a | 4015 | |
d1f13708 | 4016 | #ifdef SKY2_VLAN_TAG_USED |
d6c9bc1e SH |
4017 | /* The workaround for FE+ status conflicts with VLAN tag detection. */ |
4018 | if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && | |
4019 | sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) { | |
4020 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
4021 | dev->vlan_rx_register = sky2_vlan_rx_register; | |
4022 | } | |
d1f13708 SH |
4023 | #endif |
4024 | ||
cd28ab6a | 4025 | /* read the mac address */ |
793b883e | 4026 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 4027 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a | 4028 | |
cd28ab6a SH |
4029 | return dev; |
4030 | } | |
4031 | ||
28bd181a | 4032 | static void __devinit sky2_show_addr(struct net_device *dev) |
cd28ab6a SH |
4033 | { |
4034 | const struct sky2_port *sky2 = netdev_priv(dev); | |
0795af57 | 4035 | DECLARE_MAC_BUF(mac); |
cd28ab6a SH |
4036 | |
4037 | if (netif_msg_probe(sky2)) | |
0795af57 JP |
4038 | printk(KERN_INFO PFX "%s: addr %s\n", |
4039 | dev->name, print_mac(mac, dev->dev_addr)); | |
cd28ab6a SH |
4040 | } |
4041 | ||
fb2690a9 | 4042 | /* Handle software interrupt used during MSI test */ |
7d12e780 | 4043 | static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id) |
fb2690a9 SH |
4044 | { |
4045 | struct sky2_hw *hw = dev_id; | |
4046 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
4047 | ||
4048 | if (status == 0) | |
4049 | return IRQ_NONE; | |
4050 | ||
4051 | if (status & Y2_IS_IRQ_SW) { | |
ea76e635 | 4052 | hw->flags |= SKY2_HW_USE_MSI; |
fb2690a9 SH |
4053 | wake_up(&hw->msi_wait); |
4054 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
4055 | } | |
4056 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
4057 | ||
4058 | return IRQ_HANDLED; | |
4059 | } | |
4060 | ||
4061 | /* Test interrupt path by forcing a a software IRQ */ | |
4062 | static int __devinit sky2_test_msi(struct sky2_hw *hw) | |
4063 | { | |
4064 | struct pci_dev *pdev = hw->pdev; | |
4065 | int err; | |
4066 | ||
bb507fe1 SH |
4067 | init_waitqueue_head (&hw->msi_wait); |
4068 | ||
fb2690a9 SH |
4069 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); |
4070 | ||
b0a20ded | 4071 | err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); |
fb2690a9 | 4072 | if (err) { |
b02a9258 | 4073 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); |
fb2690a9 SH |
4074 | return err; |
4075 | } | |
4076 | ||
fb2690a9 | 4077 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); |
bb507fe1 | 4078 | sky2_read8(hw, B0_CTST); |
fb2690a9 | 4079 | |
ea76e635 | 4080 | wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); |
fb2690a9 | 4081 | |
ea76e635 | 4082 | if (!(hw->flags & SKY2_HW_USE_MSI)) { |
fb2690a9 | 4083 | /* MSI test failed, go back to INTx mode */ |
b02a9258 SH |
4084 | dev_info(&pdev->dev, "No interrupt generated using MSI, " |
4085 | "switching to INTx mode.\n"); | |
fb2690a9 SH |
4086 | |
4087 | err = -EOPNOTSUPP; | |
4088 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
4089 | } | |
4090 | ||
4091 | sky2_write32(hw, B0_IMSK, 0); | |
2bffc23a | 4092 | sky2_read32(hw, B0_IMSK); |
fb2690a9 SH |
4093 | |
4094 | free_irq(pdev->irq, hw); | |
4095 | ||
4096 | return err; | |
4097 | } | |
4098 | ||
e3173832 SH |
4099 | static int __devinit pci_wake_enabled(struct pci_dev *dev) |
4100 | { | |
4101 | int pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
4102 | u16 value; | |
4103 | ||
4104 | if (!pm) | |
4105 | return 0; | |
4106 | if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value)) | |
4107 | return 0; | |
4108 | return value & PCI_PM_CTRL_PME_ENABLE; | |
4109 | } | |
4110 | ||
cd28ab6a SH |
4111 | static int __devinit sky2_probe(struct pci_dev *pdev, |
4112 | const struct pci_device_id *ent) | |
4113 | { | |
7f60c64b | 4114 | struct net_device *dev; |
cd28ab6a | 4115 | struct sky2_hw *hw; |
e3173832 | 4116 | int err, using_dac = 0, wol_default; |
cd28ab6a | 4117 | |
793b883e SH |
4118 | err = pci_enable_device(pdev); |
4119 | if (err) { | |
b02a9258 | 4120 | dev_err(&pdev->dev, "cannot enable PCI device\n"); |
cd28ab6a SH |
4121 | goto err_out; |
4122 | } | |
4123 | ||
793b883e SH |
4124 | err = pci_request_regions(pdev, DRV_NAME); |
4125 | if (err) { | |
b02a9258 | 4126 | dev_err(&pdev->dev, "cannot obtain PCI resources\n"); |
44a1d2e5 | 4127 | goto err_out_disable; |
cd28ab6a SH |
4128 | } |
4129 | ||
4130 | pci_set_master(pdev); | |
4131 | ||
d1f3d4dd SH |
4132 | if (sizeof(dma_addr_t) > sizeof(u32) && |
4133 | !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { | |
4134 | using_dac = 1; | |
4135 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
4136 | if (err < 0) { | |
b02a9258 SH |
4137 | dev_err(&pdev->dev, "unable to obtain 64 bit DMA " |
4138 | "for consistent allocations\n"); | |
d1f3d4dd SH |
4139 | goto err_out_free_regions; |
4140 | } | |
d1f3d4dd | 4141 | } else { |
cd28ab6a SH |
4142 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
4143 | if (err) { | |
b02a9258 | 4144 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
cd28ab6a SH |
4145 | goto err_out_free_regions; |
4146 | } | |
4147 | } | |
d1f3d4dd | 4148 | |
e3173832 SH |
4149 | wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0; |
4150 | ||
cd28ab6a | 4151 | err = -ENOMEM; |
6aad85d6 | 4152 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
cd28ab6a | 4153 | if (!hw) { |
b02a9258 | 4154 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); |
cd28ab6a SH |
4155 | goto err_out_free_regions; |
4156 | } | |
4157 | ||
cd28ab6a | 4158 | hw->pdev = pdev; |
cd28ab6a SH |
4159 | |
4160 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
4161 | if (!hw->regs) { | |
b02a9258 | 4162 | dev_err(&pdev->dev, "cannot map device registers\n"); |
cd28ab6a SH |
4163 | goto err_out_free_hw; |
4164 | } | |
4165 | ||
56a645cc | 4166 | #ifdef __BIG_ENDIAN |
f65b138c SH |
4167 | /* The sk98lin vendor driver uses hardware byte swapping but |
4168 | * this driver uses software swapping. | |
4169 | */ | |
56a645cc SH |
4170 | { |
4171 | u32 reg; | |
167f53d0 | 4172 | pci_read_config_dword(pdev,PCI_DEV_REG2, ®); |
f65b138c | 4173 | reg &= ~PCI_REV_DESC; |
167f53d0 | 4174 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); |
56a645cc SH |
4175 | } |
4176 | #endif | |
4177 | ||
08c06d8a | 4178 | /* ring for status responses */ |
167f53d0 | 4179 | hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma); |
08c06d8a SH |
4180 | if (!hw->st_le) |
4181 | goto err_out_iounmap; | |
4182 | ||
e3173832 | 4183 | err = sky2_init(hw); |
cd28ab6a | 4184 | if (err) |
793b883e | 4185 | goto err_out_iounmap; |
cd28ab6a | 4186 | |
b02a9258 | 4187 | dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n", |
7c7459d1 GKH |
4188 | DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0), |
4189 | pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], | |
793b883e | 4190 | hw->chip_id, hw->chip_rev); |
cd28ab6a | 4191 | |
e3173832 SH |
4192 | sky2_reset(hw); |
4193 | ||
4194 | dev = sky2_init_netdev(hw, 0, using_dac, wol_default); | |
7f60c64b | 4195 | if (!dev) { |
4196 | err = -ENOMEM; | |
cd28ab6a | 4197 | goto err_out_free_pci; |
7f60c64b | 4198 | } |
cd28ab6a | 4199 | |
9fa1b1f3 SH |
4200 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
4201 | err = sky2_test_msi(hw); | |
4202 | if (err == -EOPNOTSUPP) | |
4203 | pci_disable_msi(pdev); | |
4204 | else if (err) | |
4205 | goto err_out_free_netdev; | |
4206 | } | |
4207 | ||
793b883e SH |
4208 | err = register_netdev(dev); |
4209 | if (err) { | |
b02a9258 | 4210 | dev_err(&pdev->dev, "cannot register net device\n"); |
cd28ab6a SH |
4211 | goto err_out_free_netdev; |
4212 | } | |
4213 | ||
6de16237 SH |
4214 | netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); |
4215 | ||
ea76e635 SH |
4216 | err = request_irq(pdev->irq, sky2_intr, |
4217 | (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, | |
b0a20ded | 4218 | dev->name, hw); |
9fa1b1f3 | 4219 | if (err) { |
b02a9258 | 4220 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); |
9fa1b1f3 SH |
4221 | goto err_out_unregister; |
4222 | } | |
4223 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); | |
6de16237 | 4224 | napi_enable(&hw->napi); |
9fa1b1f3 | 4225 | |
cd28ab6a SH |
4226 | sky2_show_addr(dev); |
4227 | ||
7f60c64b | 4228 | if (hw->ports > 1) { |
4229 | struct net_device *dev1; | |
4230 | ||
e3173832 | 4231 | dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); |
b02a9258 SH |
4232 | if (!dev1) |
4233 | dev_warn(&pdev->dev, "allocation for second device failed\n"); | |
4234 | else if ((err = register_netdev(dev1))) { | |
4235 | dev_warn(&pdev->dev, | |
4236 | "register of second port failed (%d)\n", err); | |
cd28ab6a SH |
4237 | hw->dev[1] = NULL; |
4238 | free_netdev(dev1); | |
b02a9258 SH |
4239 | } else |
4240 | sky2_show_addr(dev1); | |
cd28ab6a SH |
4241 | } |
4242 | ||
32c2c300 | 4243 | setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); |
81906791 SH |
4244 | INIT_WORK(&hw->restart_work, sky2_restart); |
4245 | ||
793b883e SH |
4246 | pci_set_drvdata(pdev, hw); |
4247 | ||
cd28ab6a SH |
4248 | return 0; |
4249 | ||
793b883e | 4250 | err_out_unregister: |
ea76e635 | 4251 | if (hw->flags & SKY2_HW_USE_MSI) |
b0a20ded | 4252 | pci_disable_msi(pdev); |
793b883e | 4253 | unregister_netdev(dev); |
cd28ab6a SH |
4254 | err_out_free_netdev: |
4255 | free_netdev(dev); | |
cd28ab6a | 4256 | err_out_free_pci: |
793b883e | 4257 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
167f53d0 | 4258 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
4259 | err_out_iounmap: |
4260 | iounmap(hw->regs); | |
4261 | err_out_free_hw: | |
4262 | kfree(hw); | |
4263 | err_out_free_regions: | |
4264 | pci_release_regions(pdev); | |
44a1d2e5 | 4265 | err_out_disable: |
cd28ab6a | 4266 | pci_disable_device(pdev); |
cd28ab6a | 4267 | err_out: |
549a68c3 | 4268 | pci_set_drvdata(pdev, NULL); |
cd28ab6a SH |
4269 | return err; |
4270 | } | |
4271 | ||
4272 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
4273 | { | |
793b883e | 4274 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
6de16237 | 4275 | int i; |
cd28ab6a | 4276 | |
793b883e | 4277 | if (!hw) |
cd28ab6a SH |
4278 | return; |
4279 | ||
32c2c300 | 4280 | del_timer_sync(&hw->watchdog_timer); |
6de16237 | 4281 | cancel_work_sync(&hw->restart_work); |
d27ed387 | 4282 | |
b877fe28 | 4283 | for (i = hw->ports-1; i >= 0; --i) |
6de16237 | 4284 | unregister_netdev(hw->dev[i]); |
81906791 | 4285 | |
d27ed387 | 4286 | sky2_write32(hw, B0_IMSK, 0); |
cd28ab6a | 4287 | |
ae306cca SH |
4288 | sky2_power_aux(hw); |
4289 | ||
cd28ab6a | 4290 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 4291 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 4292 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
4293 | |
4294 | free_irq(pdev->irq, hw); | |
ea76e635 | 4295 | if (hw->flags & SKY2_HW_USE_MSI) |
b0a20ded | 4296 | pci_disable_msi(pdev); |
793b883e | 4297 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
4298 | pci_release_regions(pdev); |
4299 | pci_disable_device(pdev); | |
793b883e | 4300 | |
b877fe28 | 4301 | for (i = hw->ports-1; i >= 0; --i) |
6de16237 SH |
4302 | free_netdev(hw->dev[i]); |
4303 | ||
cd28ab6a SH |
4304 | iounmap(hw->regs); |
4305 | kfree(hw); | |
5afa0a9c | 4306 | |
cd28ab6a SH |
4307 | pci_set_drvdata(pdev, NULL); |
4308 | } | |
4309 | ||
4310 | #ifdef CONFIG_PM | |
4311 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
4312 | { | |
793b883e | 4313 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
e3173832 | 4314 | int i, wol = 0; |
cd28ab6a | 4315 | |
549a68c3 SH |
4316 | if (!hw) |
4317 | return 0; | |
4318 | ||
f05267e7 | 4319 | for (i = 0; i < hw->ports; i++) { |
cd28ab6a | 4320 | struct net_device *dev = hw->dev[i]; |
e3173832 | 4321 | struct sky2_port *sky2 = netdev_priv(dev); |
cd28ab6a | 4322 | |
e3173832 | 4323 | if (netif_running(dev)) |
5afa0a9c | 4324 | sky2_down(dev); |
e3173832 SH |
4325 | |
4326 | if (sky2->wol) | |
4327 | sky2_wol_init(sky2); | |
4328 | ||
4329 | wol |= sky2->wol; | |
cd28ab6a SH |
4330 | } |
4331 | ||
8ab8fca2 | 4332 | sky2_write32(hw, B0_IMSK, 0); |
6de16237 | 4333 | napi_disable(&hw->napi); |
ae306cca | 4334 | sky2_power_aux(hw); |
e3173832 | 4335 | |
d374c1c1 | 4336 | pci_save_state(pdev); |
e3173832 | 4337 | pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); |
ae306cca SH |
4338 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
4339 | ||
2ccc99b7 | 4340 | return 0; |
cd28ab6a SH |
4341 | } |
4342 | ||
4343 | static int sky2_resume(struct pci_dev *pdev) | |
4344 | { | |
793b883e | 4345 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
08c06d8a | 4346 | int i, err; |
cd28ab6a | 4347 | |
549a68c3 SH |
4348 | if (!hw) |
4349 | return 0; | |
4350 | ||
ae306cca SH |
4351 | err = pci_set_power_state(pdev, PCI_D0); |
4352 | if (err) | |
4353 | goto out; | |
4354 | ||
4355 | err = pci_restore_state(pdev); | |
4356 | if (err) | |
4357 | goto out; | |
4358 | ||
cd28ab6a | 4359 | pci_enable_wake(pdev, PCI_D0, 0); |
1ad5b4a5 SH |
4360 | |
4361 | /* Re-enable all clocks */ | |
05745c4a SH |
4362 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
4363 | hw->chip_id == CHIP_ID_YUKON_EC_U || | |
4364 | hw->chip_id == CHIP_ID_YUKON_FE_P) | |
167f53d0 | 4365 | pci_write_config_dword(pdev, PCI_DEV_REG3, 0); |
1ad5b4a5 | 4366 | |
e3173832 | 4367 | sky2_reset(hw); |
8ab8fca2 | 4368 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |
6de16237 | 4369 | napi_enable(&hw->napi); |
8ab8fca2 | 4370 | |
f05267e7 | 4371 | for (i = 0; i < hw->ports; i++) { |
cd28ab6a | 4372 | struct net_device *dev = hw->dev[i]; |
6a5706b9 | 4373 | if (netif_running(dev)) { |
08c06d8a SH |
4374 | err = sky2_up(dev); |
4375 | if (err) { | |
4376 | printk(KERN_ERR PFX "%s: could not up: %d\n", | |
4377 | dev->name, err); | |
4378 | dev_close(dev); | |
eb35cf60 | 4379 | goto out; |
5afa0a9c | 4380 | } |
d1b139c0 SH |
4381 | |
4382 | sky2_set_multicast(dev); | |
cd28ab6a SH |
4383 | } |
4384 | } | |
eb35cf60 | 4385 | |
ae306cca | 4386 | return 0; |
08c06d8a | 4387 | out: |
b02a9258 | 4388 | dev_err(&pdev->dev, "resume failed (%d)\n", err); |
ae306cca | 4389 | pci_disable_device(pdev); |
08c06d8a | 4390 | return err; |
cd28ab6a SH |
4391 | } |
4392 | #endif | |
4393 | ||
e3173832 SH |
4394 | static void sky2_shutdown(struct pci_dev *pdev) |
4395 | { | |
4396 | struct sky2_hw *hw = pci_get_drvdata(pdev); | |
4397 | int i, wol = 0; | |
4398 | ||
549a68c3 SH |
4399 | if (!hw) |
4400 | return; | |
4401 | ||
5c0d6b34 | 4402 | del_timer_sync(&hw->watchdog_timer); |
e3173832 SH |
4403 | |
4404 | for (i = 0; i < hw->ports; i++) { | |
4405 | struct net_device *dev = hw->dev[i]; | |
4406 | struct sky2_port *sky2 = netdev_priv(dev); | |
4407 | ||
4408 | if (sky2->wol) { | |
4409 | wol = 1; | |
4410 | sky2_wol_init(sky2); | |
4411 | } | |
4412 | } | |
4413 | ||
4414 | if (wol) | |
4415 | sky2_power_aux(hw); | |
4416 | ||
4417 | pci_enable_wake(pdev, PCI_D3hot, wol); | |
4418 | pci_enable_wake(pdev, PCI_D3cold, wol); | |
4419 | ||
4420 | pci_disable_device(pdev); | |
4421 | pci_set_power_state(pdev, PCI_D3hot); | |
4422 | ||
4423 | } | |
4424 | ||
cd28ab6a | 4425 | static struct pci_driver sky2_driver = { |
793b883e SH |
4426 | .name = DRV_NAME, |
4427 | .id_table = sky2_id_table, | |
4428 | .probe = sky2_probe, | |
4429 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 4430 | #ifdef CONFIG_PM |
793b883e SH |
4431 | .suspend = sky2_suspend, |
4432 | .resume = sky2_resume, | |
cd28ab6a | 4433 | #endif |
e3173832 | 4434 | .shutdown = sky2_shutdown, |
cd28ab6a SH |
4435 | }; |
4436 | ||
4437 | static int __init sky2_init_module(void) | |
4438 | { | |
3cf26753 | 4439 | sky2_debug_init(); |
50241c4c | 4440 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
4441 | } |
4442 | ||
4443 | static void __exit sky2_cleanup_module(void) | |
4444 | { | |
4445 | pci_unregister_driver(&sky2_driver); | |
3cf26753 | 4446 | sky2_debug_cleanup(); |
cd28ab6a SH |
4447 | } |
4448 | ||
4449 | module_init(sky2_init_module); | |
4450 | module_exit(sky2_cleanup_module); | |
4451 | ||
4452 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
65ebe634 | 4453 | MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); |
cd28ab6a | 4454 | MODULE_LICENSE("GPL"); |
5f4f9dc1 | 4455 | MODULE_VERSION(DRV_VERSION); |