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sky2: split phy power into two functions
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
bcc52894 54#define DRV_VERSION "1.21"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
f4331a6d
SH		 79#define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
cd28ab6a 101static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
cd28ab6a
SH		 139 { 0 }
140};
793b883e 141
cd28ab6a
SH		 142MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144/* Avoid conditionals by using array */
145static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 148
92f965e8
SH		 149/* This driver supports yukon2 chipset only */
150static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
93745494 153 "Extreme", /* 0xb5 */
92f965e8
SH		 154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
05745c4a 156 "FE+", /* 0xb8 */
c63eddb2 157 "Supreme", /* 0xb9 */
793b883e
SH		 158};
159
d1b139c0
SH		 160static void sky2_set_multicast(struct net_device *dev);
161
af043aa5 162/* Access to PHY via serial interconnect */
ef743d33 163static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 164{
165 int i;
166
167 gma_write16(hw, port, GM_SMI_DATA, val);
168 gma_write16(hw, port, GM_SMI_CTRL,
169 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
170
171 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 172 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
173 if (ctrl == 0xffff)
174 goto io_error;
175
176 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 177 return 0;
af043aa5
SH		 178
179 udelay(10);
cd28ab6a 180 }
ef743d33 181
af043aa5 182 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 183 return -ETIMEDOUT;
af043aa5
SH		 184
185io_error:
186 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
187 return -EIO;
cd28ab6a
SH		 188}
189
ef743d33 190static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 191{
192 int i;
193
793b883e 194 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 195 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
196
197 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 198 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
199 if (ctrl == 0xffff)
200 goto io_error;
201
202 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 203 *val = gma_read16(hw, port, GM_SMI_DATA);
204 return 0;
205 }
206
af043aa5 207 udelay(10);
cd28ab6a
SH		 208 }
209
af043aa5 210 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 211 return -ETIMEDOUT;
af043aa5
SH		 212io_error:
213 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
214 return -EIO;
ef743d33
SH		 215}
216
af043aa5 217static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 218{
219 u16 v;
af043aa5 220 __gm_phy_read(hw, port, reg, &v);
ef743d33 221 return v;
cd28ab6a
SH		 222}
223
5afa0a9c 224
ae306cca
SH		 225static void sky2_power_on(struct sky2_hw *hw)
226{
227 /* switch power to VCC (WA for VAUX problem) */
228 sky2_write8(hw, B0_POWER_CTRL,
229 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 230
ae306cca
SH		 231 /* disable Core Clock Division, */
232 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 233
ae306cca
SH		 234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240 else
241 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 242
ea76e635 243 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 244 u32 reg;
5afa0a9c 245
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 247
b32f40c4 248 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 249 /* set all bits to 0 except bits 15..12 and 8 */
250 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 251 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 252
b32f40c4 253 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 254 /* set all bits to 0 except bits 28 & 27 */
255 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 256 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 257
b32f40c4 258 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 259
260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 reg = sky2_read32(hw, B2_GP_IO);
262 reg |= GLB_GPIO_STAT_RACE_DIS;
263 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 264
265 sky2_read32(hw, B2_GP_IO);
5afa0a9c 266 }
ae306cca 267}
5afa0a9c 268
ae306cca
SH		 269static void sky2_power_aux(struct sky2_hw *hw)
270{
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
280 /* switch power to VAUX */
281 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 285}
286
d3bcfbeb 287static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 288{
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 293
cd28ab6a
SH		 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302}
303
16ad91e1
SH		 304/* flow control to advertise bits */
305static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310};
311
312/* flow control to advertise bits when using 1000BaseX */
313static const u16 fiber_fc_adv[] = {
df3fe1f3 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 318};
319
320/* flow control to GMA disable bits */
321static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326};
327
328
cd28ab6a
SH		 329static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330{
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 333
ea76e635
SH		 334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 339 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
53419c68 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 343 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 344 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
53419c68
SH		 347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 354 if (sky2_is_copper(hw)) {
05745c4a 355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
cd28ab6a
SH		 368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
53419c68 375 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 376 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 377 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 378 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
cd28ab6a
SH		 383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 388 }
cd28ab6a 389
b89165f2
SH		 390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
ea76e635 393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 395
b89165f2
SH		 396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 411 }
b89165f2
SH		 412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 414 }
415
7800fddc 416 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
2eaba1a2 419 reg = 0;
cd28ab6a
SH		 420
421 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 422 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
709c6e7b 435
16ad91e1 436 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 442
16ad91e1 443 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 444 }
cd28ab6a
SH		 445
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 } else {
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
451
2eaba1a2
SH		 452 /* Disable auto update for duplex flow control and speed */
453 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 454
455 switch (sky2->speed) {
456 case SPEED_1000:
457 ctrl |= PHY_CT_SP1000;
2eaba1a2 458 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 459 break;
460 case SPEED_100:
461 ctrl |= PHY_CT_SP100;
2eaba1a2 462 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 463 break;
464 }
465
2eaba1a2
SH		 466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
2eaba1a2 471
2eaba1a2 472
16ad91e1 473 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 474
475 /* Forward pause packets to GMAC? */
16ad91e1 476 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
478 else
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 480 }
481
2eaba1a2
SH		 482 gma_write16(hw, port, GM_GP_CTRL, reg);
483
05745c4a 484 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 485 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
486
487 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
488 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
489
490 /* Setup Phy LED's */
491 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
492 ledover = 0;
493
494 switch (hw->chip_id) {
495 case CHIP_ID_YUKON_FE:
496 /* on 88E3082 these bits are at 11..9 (shifted left) */
497 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
498
499 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
500
501 /* delete ACT LED control bits */
502 ctrl &= ~PHY_M_FELP_LED1_MSK;
503 /* change ACT LED control to blink mode */
504 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
506 break;
507
05745c4a
SH		 508 case CHIP_ID_YUKON_FE_P:
509 /* Enable Link Partner Next Page */
510 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
511 ctrl |= PHY_M_PC_ENA_LIP_NP;
512
513 /* disable Energy Detect and enable scrambler */
514 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
516
517 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
518 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
519 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
520 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
521
522 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
523 break;
524
cd28ab6a 525 case CHIP_ID_YUKON_XL:
793b883e 526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 527
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
530
531 /* set LED Function Control register */
ed6d32c7
SH		 532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 537
538 /* set Polarity Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 540 (PHY_M_POLC_LS1_P_MIX(4) |
541 PHY_M_POLC_IS0_P_MIX(4) |
542 PHY_M_POLC_LOS_CTRL(2) |
543 PHY_M_POLC_INIT_CTRL(2) |
544 PHY_M_POLC_STA1_CTRL(2) |
545 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 546
547 /* restore page register */
793b883e 548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 549 break;
93745494 550
ed6d32c7 551 case CHIP_ID_YUKON_EC_U:
93745494 552 case CHIP_ID_YUKON_EX:
ed4d4161 553 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 554 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
555
556 /* select page 3 to access LED control register */
557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
558
559 /* set LED Function Control register */
560 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
561 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
562 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
563 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
564 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
565
566 /* set Blink Rate in LED Timer Control Register */
567 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
568 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
569 /* restore page register */
570 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
571 break;
cd28ab6a
SH		 572
573 default:
574 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
575 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 576
cd28ab6a 577 /* turn off the Rx LED (LED_RX) */
a84d0a3d 578 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 579 }
580
9467a8fc
SH		 581 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
582 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 583 /* apply fixes in PHY AFE */
ed6d32c7
SH		 584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
585
977bdf06 586 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 587 gm_phy_write(hw, port, 0x18, 0xaa99);
588 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 589
977bdf06 590 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 591 gm_phy_write(hw, port, 0x18, 0xa204);
592 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 593
594 /* set page register to 0 */
9467a8fc 595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 596 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
597 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
598 /* apply workaround for integrated resistors calibration */
599 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
600 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 601 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 602 /* no effect on Yukon-XL */
977bdf06 603 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 604
977bdf06
SH		 605 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
606 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 607 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 608 }
cd28ab6a 609
977bdf06
SH		 610 if (ledover)
611 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
612
613 }
2eaba1a2 614
d571b694 615 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 616 if (sky2->autoneg == AUTONEG_ENABLE)
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
618 else
619 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
620}
621
b96936da
SH		 622static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
623static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
624
625static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 626{
627 u32 reg1;
d3bcfbeb 628
82637e80 629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 630 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 631 reg1 &= ~phy_power[port];
d3bcfbeb 632
b96936da 633 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 634 reg1 |= coma_mode[port];
635
b32f40c4 636 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 637 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
638 sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 639}
167f53d0 640
b96936da
SH		 641static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
642{
643 u32 reg1;
644
645 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
646 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
647 reg1 |= phy_power[port];
648
649 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
650 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 651}
652
1b537565
SH		 653/* Force a renegotiation */
654static void sky2_phy_reinit(struct sky2_port *sky2)
655{
e07b1aa8 656 spin_lock_bh(&sky2->phy_lock);
1b537565 657 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 658 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 659}
660
e3173832
SH		 661/* Put device in state to listen for Wake On Lan */
662static void sky2_wol_init(struct sky2_port *sky2)
663{
664 struct sky2_hw *hw = sky2->hw;
665 unsigned port = sky2->port;
666 enum flow_control save_mode;
667 u16 ctrl;
668 u32 reg1;
669
670 /* Bring hardware out of reset */
671 sky2_write16(hw, B0_CTST, CS_RST_CLR);
672 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
673
674 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
676
677 /* Force to 10/100
678 * sky2_reset will re-enable on resume
679 */
680 save_mode = sky2->flow_mode;
681 ctrl = sky2->advertising;
682
683 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
684 sky2->flow_mode = FC_NONE;
b96936da
SH		 685
686 spin_lock_bh(&sky2->phy_lock);
687 sky2_phy_power_up(hw, port);
688 sky2_phy_init(hw, port);
689 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 690
691 sky2->flow_mode = save_mode;
692 sky2->advertising = ctrl;
693
694 /* Set GMAC to no flow control and auto update for speed/duplex */
695 gma_write16(hw, port, GM_GP_CTRL,
696 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
697 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
698
699 /* Set WOL address */
700 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
701 sky2->netdev->dev_addr, ETH_ALEN);
702
703 /* Turn on appropriate WOL control bits */
704 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
705 ctrl = 0;
706 if (sky2->wol & WAKE_PHY)
707 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
708 else
709 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
710
711 if (sky2->wol & WAKE_MAGIC)
712 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
713 else
714 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
715
716 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
717 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
718
719 /* Turn on legacy PCI-Express PME mode */
b32f40c4 720 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 721 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 722 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 723
724 /* block receiver */
725 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
726
727}
728
69161611
SH		 729static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
730{
05745c4a
SH		 731 struct net_device *dev = hw->dev[port];
732
ed4d4161
SH		 733 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
734 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
735 hw->chip_id == CHIP_ID_YUKON_FE_P ||
736 hw->chip_id == CHIP_ID_YUKON_SUPR) {
737 /* Yukon-Extreme B0 and further Extreme devices */
738 /* enable Store & Forward mode for TX */
05745c4a 739
ed4d4161
SH		 740 if (dev->mtu <= ETH_DATA_LEN)
741 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
742 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 743
ed4d4161
SH		 744 else
745 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
746 TX_JUMBO_ENA| TX_STFW_ENA);
747 } else {
748 if (dev->mtu <= ETH_DATA_LEN)
749 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
750 else {
751 /* set Tx GMAC FIFO Almost Empty Threshold */
752 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
753 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 754
ed4d4161
SH		 755 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
756
757 /* Can't do offload because of lack of store/forward */
758 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
759 }
69161611
SH		 760 }
761}
762
cd28ab6a
SH		 763static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
764{
765 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
766 u16 reg;
25cccecc 767 u32 rx_reg;
cd28ab6a
SH		 768 int i;
769 const u8 *addr = hw->dev[port]->dev_addr;
770
f350339c
SH		 771 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
772 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 773
774 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
775
793b883e 776 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 777 /* WA DEV_472 -- looks like crossed wires on port 2 */
778 /* clear GMAC 1 Control reset */
779 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
780 do {
781 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
782 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
783 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
784 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
785 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
786 }
787
793b883e 788 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 789
2eaba1a2
SH		 790 /* Enable Transmit FIFO Underrun */
791 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
792
e07b1aa8 793 spin_lock_bh(&sky2->phy_lock);
b96936da 794 sky2_phy_power_up(hw, port);
cd28ab6a 795 sky2_phy_init(hw, port);
e07b1aa8 796 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 797
798 /* MIB clear */
799 reg = gma_read16(hw, port, GM_PHY_ADDR);
800 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
801
43f2f104
SH		 802 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
803 gma_read16(hw, port, i);
cd28ab6a
SH		 804 gma_write16(hw, port, GM_PHY_ADDR, reg);
805
806 /* transmit control */
807 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
808
809 /* receive control reg: unicast + multicast + no FCS */
810 gma_write16(hw, port, GM_RX_CTRL,
793b883e 811 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 812
813 /* transmit flow control */
814 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
815
816 /* transmit parameter */
817 gma_write16(hw, port, GM_TX_PARAM,
818 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
819 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
820 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
821 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
822
823 /* serial mode register */
824 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 825 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 826
6b1a3aef 827 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 828 reg |= GM_SMOD_JUMBO_ENA;
829
830 gma_write16(hw, port, GM_SERIAL_MODE, reg);
831
cd28ab6a
SH		 832 /* virtual address for data */
833 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
834
793b883e
SH		 835 /* physical address: used for pause frames */
836 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
837
838 /* ignore counter overflows */
cd28ab6a
SH		 839 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
840 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
841 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
842
843 /* Configure Rx MAC FIFO */
844 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 845 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 846 if (hw->chip_id == CHIP_ID_YUKON_EX ||
847 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 848 rx_reg |= GMF_RX_OVER_ON;
69161611 849
25cccecc 850 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 851
798fdd07
SH		 852 if (hw->chip_id == CHIP_ID_YUKON_XL) {
853 /* Hardware errata - clear flush mask */
854 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
855 } else {
856 /* Flush Rx MAC FIFO on any flow control or error */
857 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
858 }
cd28ab6a 859
8df9a876 860 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 861 reg = RX_GMF_FL_THR_DEF + 1;
862 /* Another magic mystery workaround from sk98lin */
863 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
864 hw->chip_rev == CHIP_REV_YU_FE2_A0)
865 reg = 0x178;
866 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 867
868 /* Configure Tx MAC FIFO */
869 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
870 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 871
e0c28116 872 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 873 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 874 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 875 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 876
69161611 877 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 878 }
879
e970d1f8
SH		 880 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
881 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
882 /* disable dynamic watermark */
883 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
884 reg &= ~TX_DYN_WM_ENA;
885 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
886 }
cd28ab6a
SH		 887}
888
67712901
SH		 889/* Assign Ram Buffer allocation to queue */
890static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 891{
67712901
SH		 892 u32 end;
893
894 /* convert from K bytes to qwords used for hw register */
895 start *= 1024/8;
896 space *= 1024/8;
897 end = start + space - 1;
793b883e 898
cd28ab6a
SH		 899 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
900 sky2_write32(hw, RB_ADDR(q, RB_START), start);
901 sky2_write32(hw, RB_ADDR(q, RB_END), end);
902 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
903 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
904
905 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 906 u32 tp = space - space/4;
793b883e 907
1c28f6ba
SH		 908 /* On receive queue's set the thresholds
909 * give receiver priority when > 3/4 full
910 * send pause when down to 2K
911 */
912 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
913 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 914
1c28f6ba
SH		 915 tp = space - 2048/8;
916 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
917 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 918 } else {
919 /* Enable store & forward on Tx queue's because
920 * Tx FIFO is only 1K on Yukon
921 */
922 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
923 }
924
925 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 926 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 927}
928
cd28ab6a 929/* Setup Bus Memory Interface */
af4ed7e6 930static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 931{
932 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
933 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
934 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 935 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 936}
937
cd28ab6a
SH		 938/* Setup prefetch unit registers. This is the interface between
939 * hardware and driver list elements
940 */
8cc048e3 941static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 942 u64 addr, u32 last)
943{
cd28ab6a
SH		 944 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
945 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
946 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
947 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
948 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
949 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 950
951 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 952}
953
793b883e
SH		 954static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
955{
956 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
957
cb5d9547 958 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 959 le->ctrl = 0;
793b883e
SH		 960 return le;
961}
cd28ab6a 962
88f5f0ca
SH		 963static void tx_init(struct sky2_port *sky2)
964{
965 struct sky2_tx_le *le;
966
967 sky2->tx_prod = sky2->tx_cons = 0;
968 sky2->tx_tcpsum = 0;
969 sky2->tx_last_mss = 0;
970
971 le = get_tx_le(sky2);
972 le->addr = 0;
973 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 974}
975
291ea614
SH		 976static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
977 struct sky2_tx_le *le)
978{
979 return sky2->tx_ring + (le - sky2->tx_le);
980}
981
290d4de5
SH		 982/* Update chip's next pointer */
983static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 984{
50432cb5 985 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 986 wmb();
50432cb5
SH		 987 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
988
989 /* Synchronize I/O on since next processor may write to tail */
990 mmiowb();
cd28ab6a
SH		 991}
992
793b883e 993
cd28ab6a
SH		 994static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
995{
996 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 997 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 998 le->ctrl = 0;
cd28ab6a
SH		 999 return le;
1000}
1001
14d0263f
SH		 1002/* Build description to hardware for one receive segment */
1003static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1004 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1005{
1006 struct sky2_rx_le *le;
1007
86c6887e 1008 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1009 le = sky2_next_rx(sky2);
86c6887e 1010 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1011 le->opcode = OP_ADDR64 | HW_OWNER;
1012 }
793b883e 1013
cd28ab6a 1014 le = sky2_next_rx(sky2);
734d1868
SH		 1015 le->addr = cpu_to_le32((u32) map);
1016 le->length = cpu_to_le16(len);
14d0263f 1017 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1018}
1019
14d0263f
SH		 1020/* Build description to hardware for one possibly fragmented skb */
1021static void sky2_rx_submit(struct sky2_port *sky2,
1022 const struct rx_ring_info *re)
1023{
1024 int i;
1025
1026 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1027
1028 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1029 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1030}
1031
1032
1033static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1034 unsigned size)
1035{
1036 struct sk_buff *skb = re->skb;
1037 int i;
1038
1039 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1040 pci_unmap_len_set(re, data_size, size);
1041
1042 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1043 re->frag_addr[i] = pci_map_page(pdev,
1044 skb_shinfo(skb)->frags[i].page,
1045 skb_shinfo(skb)->frags[i].page_offset,
1046 skb_shinfo(skb)->frags[i].size,
1047 PCI_DMA_FROMDEVICE);
1048}
1049
1050static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1051{
1052 struct sk_buff *skb = re->skb;
1053 int i;
1054
1055 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1056 PCI_DMA_FROMDEVICE);
1057
1058 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1059 pci_unmap_page(pdev, re->frag_addr[i],
1060 skb_shinfo(skb)->frags[i].size,
1061 PCI_DMA_FROMDEVICE);
1062}
793b883e 1063
cd28ab6a
SH		 1064/* Tell chip where to start receive checksum.
1065 * Actually has two checksums, but set both same to avoid possible byte
1066 * order problems.
1067 */
793b883e 1068static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1069{
ea76e635 1070 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1071
ea76e635
SH		 1072 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1073 le->ctrl = 0;
1074 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1075
ea76e635
SH		 1076 sky2_write32(sky2->hw,
1077 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1078 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1079}
1080
6b1a3aef
SH		 1081/*
1082 * The RX Stop command will not work for Yukon-2 if the BMU does not
1083 * reach the end of packet and since we can't make sure that we have
1084 * incoming data, we must reset the BMU while it is not doing a DMA
1085 * transfer. Since it is possible that the RX path is still active,
1086 * the RX RAM buffer will be stopped first, so any possible incoming
1087 * data will not trigger a DMA. After the RAM buffer is stopped, the
1088 * BMU is polled until any DMA in progress is ended and only then it
1089 * will be reset.
1090 */
1091static void sky2_rx_stop(struct sky2_port *sky2)
1092{
1093 struct sky2_hw *hw = sky2->hw;
1094 unsigned rxq = rxqaddr[sky2->port];
1095 int i;
1096
1097 /* disable the RAM Buffer receive queue */
1098 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1099
1100 for (i = 0; i < 0xffff; i++)
1101 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1102 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1103 goto stopped;
1104
1105 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1106 sky2->netdev->name);
1107stopped:
1108 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1109
1110 /* reset the Rx prefetch unit */
1111 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1112 mmiowb();
6b1a3aef 1113}
793b883e 1114
d571b694 1115/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1116static void sky2_rx_clean(struct sky2_port *sky2)
1117{
1118 unsigned i;
1119
1120 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1121 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1122 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1123
1124 if (re->skb) {
14d0263f 1125 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1126 kfree_skb(re->skb);
1127 re->skb = NULL;
1128 }
1129 }
1130}
1131
ef743d33
SH		 1132/* Basic MII support */
1133static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1134{
1135 struct mii_ioctl_data *data = if_mii(ifr);
1136 struct sky2_port *sky2 = netdev_priv(dev);
1137 struct sky2_hw *hw = sky2->hw;
1138 int err = -EOPNOTSUPP;
1139
1140 if (!netif_running(dev))
1141 return -ENODEV; /* Phy still in reset */
1142
d89e1343 1143 switch (cmd) {
ef743d33
SH		 1144 case SIOCGMIIPHY:
1145 data->phy_id = PHY_ADDR_MARV;
1146
1147 /* fallthru */
1148 case SIOCGMIIREG: {
1149 u16 val = 0;
91c86df5 1150
e07b1aa8 1151 spin_lock_bh(&sky2->phy_lock);
ef743d33 1152 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1153 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1154
ef743d33
SH		 1155 data->val_out = val;
1156 break;
1157 }
1158
1159 case SIOCSMIIREG:
1160 if (!capable(CAP_NET_ADMIN))
1161 return -EPERM;
1162
e07b1aa8 1163 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1164 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1165 data->val_in);
e07b1aa8 1166 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1167 break;
1168 }
1169 return err;
1170}
1171
d1f13708 1172#ifdef SKY2_VLAN_TAG_USED
d494eacd 1173static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1174{
d494eacd 1175 if (onoff) {
3d4e66f5
SH		 1176 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1177 RX_VLAN_STRIP_ON);
1178 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1179 TX_VLAN_TAG_ON);
1180 } else {
1181 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1182 RX_VLAN_STRIP_OFF);
1183 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1184 TX_VLAN_TAG_OFF);
1185 }
d494eacd
SH		 1186}
1187
1188static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1189{
1190 struct sky2_port *sky2 = netdev_priv(dev);
1191 struct sky2_hw *hw = sky2->hw;
1192 u16 port = sky2->port;
1193
1194 netif_tx_lock_bh(dev);
1195 napi_disable(&hw->napi);
1196
1197 sky2->vlgrp = grp;
1198 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1199
d1d08d12 1200 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1201 napi_enable(&hw->napi);
2bb8c262 1202 netif_tx_unlock_bh(dev);
d1f13708
SH		 1203}
1204#endif
1205
82788c7a 1206/*
14d0263f
SH		 1207 * Allocate an skb for receiving. If the MTU is large enough
1208 * make the skb non-linear with a fragment list of pages.
82788c7a 1209 */
14d0263f 1210static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1211{
1212 struct sk_buff *skb;
14d0263f 1213 int i;
82788c7a 1214
39dbd958 1215 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1216 unsigned char *start;
1217 /*
1218 * Workaround for a bug in FIFO that cause hang
1219 * if the FIFO if the receive buffer is not 64 byte aligned.
1220 * The buffer returned from netdev_alloc_skb is
1221 * aligned except if slab debugging is enabled.
1222 */
1223 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1224 if (!skb)
1225 goto nomem;
1226 start = PTR_ALIGN(skb->data, 8);
1227 skb_reserve(skb, start - skb->data);
1228 } else {
1229 skb = netdev_alloc_skb(sky2->netdev,
1230 sky2->rx_data_size + NET_IP_ALIGN);
1231 if (!skb)
1232 goto nomem;
1233 skb_reserve(skb, NET_IP_ALIGN);
1234 }
14d0263f
SH		 1235
1236 for (i = 0; i < sky2->rx_nfrags; i++) {
1237 struct page *page = alloc_page(GFP_ATOMIC);
1238
1239 if (!page)
1240 goto free_partial;
1241 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1242 }
1243
1244 return skb;
14d0263f
SH		 1245free_partial:
1246 kfree_skb(skb);
1247nomem:
1248 return NULL;
82788c7a
SH		 1249}
1250
55c9dd35
SH		 1251static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1252{
1253 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1254}
1255
cd28ab6a
SH		 1256/*
1257 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1258 * Normal case this ends up creating one list element for skb
1259 * in the receive ring. Worst case if using large MTU and each
1260 * allocation falls on a different 64 bit region, that results
1261 * in 6 list elements per ring entry.
1262 * One element is used for checksum enable/disable, and one
1263 * extra to avoid wrap.
cd28ab6a 1264 */
6b1a3aef 1265static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1266{
6b1a3aef 1267 struct sky2_hw *hw = sky2->hw;
14d0263f 1268 struct rx_ring_info *re;
6b1a3aef 1269 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1270 unsigned i, size, thresh;
cd28ab6a 1271
6b1a3aef 1272 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1273 sky2_qset(hw, rxq);
977bdf06 1274
c3905bc4
SH		 1275 /* On PCI express lowering the watermark gives better performance */
1276 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1277 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1278
1279 /* These chips have no ram buffer?
1280 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1281 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1282 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1283 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1284 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1285
6b1a3aef
SH		 1286 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1287
ea76e635
SH		 1288 if (!(hw->flags & SKY2_HW_NEW_LE))
1289 rx_set_checksum(sky2);
14d0263f
SH		 1290
1291 /* Space needed for frame data + headers rounded up */
f957da2a 1292 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1293
1294 /* Stopping point for hardware truncation */
1295 thresh = (size - 8) / sizeof(u32);
1296
5f06eba4 1297 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1298 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1299
5f06eba4
SH		 1300 /* Compute residue after pages */
1301 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1302
5f06eba4
SH		 1303 /* Optimize to handle small packets and headers */
1304 if (size < copybreak)
1305 size = copybreak;
1306 if (size < ETH_HLEN)
1307 size = ETH_HLEN;
14d0263f 1308
14d0263f
SH		 1309 sky2->rx_data_size = size;
1310
1311 /* Fill Rx ring */
793b883e 1312 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1313 re = sky2->rx_ring + i;
cd28ab6a 1314
14d0263f 1315 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1316 if (!re->skb)
1317 goto nomem;
1318
14d0263f
SH		 1319 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1320 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1321 }
1322
a1433ac4
SH		 1323 /*
1324 * The receiver hangs if it receives frames larger than the
1325 * packet buffer. As a workaround, truncate oversize frames, but
1326 * the register is limited to 9 bits, so if you do frames > 2052
1327 * you better get the MTU right!
1328 */
a1433ac4
SH		 1329 if (thresh > 0x1ff)
1330 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1331 else {
1332 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1333 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1334 }
1335
6b1a3aef 1336 /* Tell chip about available buffers */
55c9dd35 1337 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1338 return 0;
1339nomem:
1340 sky2_rx_clean(sky2);
1341 return -ENOMEM;
1342}
1343
1344/* Bring up network interface. */
1345static int sky2_up(struct net_device *dev)
1346{
1347 struct sky2_port *sky2 = netdev_priv(dev);
1348 struct sky2_hw *hw = sky2->hw;
1349 unsigned port = sky2->port;
e0c28116 1350 u32 imask, ramsize;
ee7abb04 1351 int cap, err = -ENOMEM;
843a46f4 1352 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1353
ee7abb04
SH		 1354 /*
1355 * On dual port PCI-X card, there is an problem where status
1356 * can be received out of order due to split transactions
843a46f4 1357 */
ee7abb04
SH		 1358 if (otherdev && netif_running(otherdev) &&
1359 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1360 u16 cmd;
1361
b32f40c4 1362 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1363 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1364 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1365
ee7abb04 1366 }
843a46f4 1367
cd28ab6a
SH		 1368 if (netif_msg_ifup(sky2))
1369 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1370
55d7b4e6
SH		 1371 netif_carrier_off(dev);
1372
cd28ab6a
SH		 1373 /* must be power of 2 */
1374 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1375 TX_RING_SIZE *
1376 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1377 &sky2->tx_le_map);
1378 if (!sky2->tx_le)
1379 goto err_out;
1380
6cdbbdf3 1381 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1382 GFP_KERNEL);
1383 if (!sky2->tx_ring)
1384 goto err_out;
88f5f0ca
SH		 1385
1386 tx_init(sky2);
cd28ab6a
SH		 1387
1388 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1389 &sky2->rx_le_map);
1390 if (!sky2->rx_le)
1391 goto err_out;
1392 memset(sky2->rx_le, 0, RX_LE_BYTES);
1393
291ea614 1394 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1395 GFP_KERNEL);
1396 if (!sky2->rx_ring)
1397 goto err_out;
1398
1399 sky2_mac_init(hw, port);
1400
e0c28116
SH		 1401 /* Register is number of 4K blocks on internal RAM buffer. */
1402 ramsize = sky2_read8(hw, B2_E_0) * 4;
1403 if (ramsize > 0) {
67712901 1404 u32 rxspace;
cd28ab6a 1405
39dbd958 1406 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1407 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1408 if (ramsize < 16)
1409 rxspace = ramsize / 2;
1410 else
1411 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1412
67712901
SH		 1413 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1414 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1415
1416 /* Make sure SyncQ is disabled */
1417 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1418 RB_RST_SET);
1419 }
793b883e 1420
af4ed7e6 1421 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1422
69161611
SH		 1423 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1424 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1425 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1426
977bdf06 1427 /* Set almost empty threshold */
c2716fb4
SH		 1428 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1429 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1430 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1431
6b1a3aef
SH		 1432 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1433 TX_RING_SIZE - 1);
cd28ab6a 1434
d494eacd
SH		 1435#ifdef SKY2_VLAN_TAG_USED
1436 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1437#endif
1438
6b1a3aef 1439 err = sky2_rx_start(sky2);
6de16237 1440 if (err)
cd28ab6a
SH		 1441 goto err_out;
1442
cd28ab6a 1443 /* Enable interrupts from phy/mac for port */
e07b1aa8 1444 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1445 imask |= portirq_msk[port];
e07b1aa8
SH		 1446 sky2_write32(hw, B0_IMSK, imask);
1447
a7bffe72 1448 sky2_set_multicast(dev);
cd28ab6a
SH		 1449 return 0;
1450
1451err_out:
1b537565 1452 if (sky2->rx_le) {
cd28ab6a
SH		 1453 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1454 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1455 sky2->rx_le = NULL;
1456 }
1457 if (sky2->tx_le) {
cd28ab6a
SH		 1458 pci_free_consistent(hw->pdev,
1459 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1460 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1461 sky2->tx_le = NULL;
1462 }
1463 kfree(sky2->tx_ring);
1464 kfree(sky2->rx_ring);
cd28ab6a 1465
1b537565
SH		 1466 sky2->tx_ring = NULL;
1467 sky2->rx_ring = NULL;
cd28ab6a
SH		 1468 return err;
1469}
1470
793b883e
SH		 1471/* Modular subtraction in ring */
1472static inline int tx_dist(unsigned tail, unsigned head)
1473{
cb5d9547 1474 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1475}
cd28ab6a 1476
793b883e
SH		 1477/* Number of list elements available for next tx */
1478static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1479{
793b883e 1480 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1481}
1482
793b883e 1483/* Estimate of number of transmit list elements required */
28bd181a 1484static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1485{
793b883e
SH		 1486 unsigned count;
1487
1488 count = sizeof(dma_addr_t) / sizeof(u32);
1489 count += skb_shinfo(skb)->nr_frags * count;
1490
89114afd 1491 if (skb_is_gso(skb))
793b883e
SH		 1492 ++count;
1493
84fa7933 1494 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1495 ++count;
1496
1497 return count;
cd28ab6a
SH		 1498}
1499
793b883e
SH		 1500/*
1501 * Put one packet in ring for transmit.
1502 * A single packet can generate multiple list elements, and
1503 * the number of ring elements will probably be less than the number
1504 * of list elements used.
1505 */
cd28ab6a
SH		 1506static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1507{
1508 struct sky2_port *sky2 = netdev_priv(dev);
1509 struct sky2_hw *hw = sky2->hw;
d1f13708 1510 struct sky2_tx_le *le = NULL;
6cdbbdf3 1511 struct tx_ring_info *re;
cd28ab6a
SH		 1512 unsigned i, len;
1513 dma_addr_t mapping;
cd28ab6a
SH		 1514 u16 mss;
1515 u8 ctrl;
1516
2bb8c262
SH		 1517 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1518 return NETDEV_TX_BUSY;
cd28ab6a 1519
793b883e 1520 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1521 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1522 dev->name, sky2->tx_prod, skb->len);
1523
cd28ab6a
SH		 1524 len = skb_headlen(skb);
1525 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1526
86c6887e
SH		 1527 /* Send high bits if needed */
1528 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1529 le = get_tx_le(sky2);
86c6887e 1530 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1531 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1532 }
cd28ab6a
SH		 1533
1534 /* Check for TCP Segmentation Offload */
7967168c 1535 mss = skb_shinfo(skb)->gso_size;
793b883e 1536 if (mss != 0) {
ea76e635
SH		 1537
1538 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1539 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1540
1541 if (mss != sky2->tx_last_mss) {
1542 le = get_tx_le(sky2);
1543 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1544
1545 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1546 le->opcode = OP_MSS | HW_OWNER;
1547 else
1548 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1549 sky2->tx_last_mss = mss;
1550 }
cd28ab6a
SH		 1551 }
1552
cd28ab6a 1553 ctrl = 0;
d1f13708
SH		 1554#ifdef SKY2_VLAN_TAG_USED
1555 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1556 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1557 if (!le) {
1558 le = get_tx_le(sky2);
f65b138c 1559 le->addr = 0;
d1f13708 1560 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1561 } else
1562 le->opcode |= OP_VLAN;
1563 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1564 ctrl |= INS_VLAN;
1565 }
1566#endif
1567
1568 /* Handle TCP checksum offload */
84fa7933 1569 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1570 /* On Yukon EX (some versions) encoding change. */
ea76e635 1571 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1572 ctrl |= CALSUM; /* auto checksum */
1573 else {
1574 const unsigned offset = skb_transport_offset(skb);
1575 u32 tcpsum;
1576
1577 tcpsum = offset << 16; /* sum start */
1578 tcpsum |= offset + skb->csum_offset; /* sum write */
1579
1580 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1581 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1582 ctrl |= UDPTCP;
1583
1584 if (tcpsum != sky2->tx_tcpsum) {
1585 sky2->tx_tcpsum = tcpsum;
1586
1587 le = get_tx_le(sky2);
1588 le->addr = cpu_to_le32(tcpsum);
1589 le->length = 0; /* initial checksum value */
1590 le->ctrl = 1; /* one packet */
1591 le->opcode = OP_TCPLISW | HW_OWNER;
1592 }
1d179332 1593 }
cd28ab6a
SH		 1594 }
1595
1596 le = get_tx_le(sky2);
f65b138c 1597 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1598 le->length = cpu_to_le16(len);
1599 le->ctrl = ctrl;
793b883e 1600 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1601
291ea614 1602 re = tx_le_re(sky2, le);
cd28ab6a 1603 re->skb = skb;
6cdbbdf3 1604 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1605 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1606
1607 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1608 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1609
1610 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1611 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1612
1613 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1614 le = get_tx_le(sky2);
86c6887e 1615 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1616 le->ctrl = 0;
1617 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1618 }
1619
1620 le = get_tx_le(sky2);
f65b138c 1621 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1622 le->length = cpu_to_le16(frag->size);
1623 le->ctrl = ctrl;
793b883e 1624 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1625
291ea614
SH		 1626 re = tx_le_re(sky2, le);
1627 re->skb = skb;
1628 pci_unmap_addr_set(re, mapaddr, mapping);
1629 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1630 }
6cdbbdf3 1631
cd28ab6a
SH		 1632 le->ctrl |= EOP;
1633
97bda706
SH		 1634 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1635 netif_stop_queue(dev);
b19666d9 1636
290d4de5 1637 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1638
cd28ab6a
SH		 1639 dev->trans_start = jiffies;
1640 return NETDEV_TX_OK;
1641}
1642
cd28ab6a 1643/*
793b883e
SH		 1644 * Free ring elements from starting at tx_cons until "done"
1645 *
1646 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1647 * buffers so make sure not to free skb to early.
cd28ab6a 1648 */
d11c13e7 1649static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1650{
d11c13e7 1651 struct net_device *dev = sky2->netdev;
af2a58ac 1652 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1653 unsigned idx;
cd28ab6a 1654
0e3ff6aa 1655 BUG_ON(done >= TX_RING_SIZE);
2224795d 1656
291ea614
SH		 1657 for (idx = sky2->tx_cons; idx != done;
1658 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1659 struct sky2_tx_le *le = sky2->tx_le + idx;
1660 struct tx_ring_info *re = sky2->tx_ring + idx;
1661
1662 switch(le->opcode & ~HW_OWNER) {
1663 case OP_LARGESEND:
1664 case OP_PACKET:
1665 pci_unmap_single(pdev,
1666 pci_unmap_addr(re, mapaddr),
1667 pci_unmap_len(re, maplen),
1668 PCI_DMA_TODEVICE);
af2a58ac 1669 break;
291ea614
SH		 1670 case OP_BUFFER:
1671 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1672 pci_unmap_len(re, maplen),
734d1868 1673 PCI_DMA_TODEVICE);
291ea614
SH		 1674 break;
1675 }
1676
1677 if (le->ctrl & EOP) {
1678 if (unlikely(netif_msg_tx_done(sky2)))
1679 printk(KERN_DEBUG "%s: tx done %u\n",
1680 dev->name, idx);
3cf26753 1681
7138a0f5
SH		 1682 dev->stats.tx_packets++;
1683 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1684
794b2bd2 1685 dev_kfree_skb_any(re->skb);
3cf26753 1686 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1687 }
793b883e 1688 }
793b883e 1689
291ea614 1690 sky2->tx_cons = idx;
50432cb5
SH		 1691 smp_mb();
1692
22e11703 1693 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1694 netif_wake_queue(dev);
cd28ab6a
SH		 1695}
1696
1697/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1698static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1699{
2bb8c262
SH		 1700 struct sky2_port *sky2 = netdev_priv(dev);
1701
1702 netif_tx_lock_bh(dev);
d11c13e7 1703 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1704 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1705}
1706
1707/* Network shutdown */
1708static int sky2_down(struct net_device *dev)
1709{
1710 struct sky2_port *sky2 = netdev_priv(dev);
1711 struct sky2_hw *hw = sky2->hw;
1712 unsigned port = sky2->port;
1713 u16 ctrl;
e07b1aa8 1714 u32 imask;
cd28ab6a 1715
1b537565
SH		 1716 /* Never really got started! */
1717 if (!sky2->tx_le)
1718 return 0;
1719
cd28ab6a
SH		 1720 if (netif_msg_ifdown(sky2))
1721 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1722
018d1c66 1723 /* Stop more packets from being queued */
cd28ab6a
SH		 1724 netif_stop_queue(dev);
1725
ebc646f6
SH		 1726 /* Disable port IRQ */
1727 imask = sky2_read32(hw, B0_IMSK);
1728 imask &= ~portirq_msk[port];
1729 sky2_write32(hw, B0_IMSK, imask);
1730
6de16237
SH		 1731 synchronize_irq(hw->pdev->irq);
1732
d3bcfbeb 1733 sky2_gmac_reset(hw, port);
793b883e 1734
cd28ab6a
SH		 1735 /* Stop transmitter */
1736 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1737 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1738
1739 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1740 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1741
1742 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1743 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1744 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1745
6de16237
SH		 1746 /* Make sure no packets are pending */
1747 napi_synchronize(&hw->napi);
1748
cd28ab6a
SH		 1749 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1750
1751 /* Workaround shared GMAC reset */
793b883e
SH		 1752 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1753 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1754 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1755
1756 /* Disable Force Sync bit and Enable Alloc bit */
1757 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1758 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1759
1760 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1761 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1762 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1763
1764 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1765 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1766 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1767
1768 /* Reset the Tx prefetch units */
1769 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1770 PREF_UNIT_RST_SET);
1771
1772 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1773
6b1a3aef 1774 sky2_rx_stop(sky2);
cd28ab6a
SH		 1775
1776 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1777 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1778
b96936da 1779 sky2_phy_power_down(hw, port);
d3bcfbeb 1780
55d7b4e6
SH		 1781 netif_carrier_off(dev);
1782
d571b694 1783 /* turn off LED's */
cd28ab6a
SH		 1784 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1785
2bb8c262 1786 sky2_tx_clean(dev);
cd28ab6a
SH		 1787 sky2_rx_clean(sky2);
1788
1789 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1790 sky2->rx_le, sky2->rx_le_map);
1791 kfree(sky2->rx_ring);
1792
1793 pci_free_consistent(hw->pdev,
1794 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1795 sky2->tx_le, sky2->tx_le_map);
1796 kfree(sky2->tx_ring);
1797
1b537565
SH		 1798 sky2->tx_le = NULL;
1799 sky2->rx_le = NULL;
1800
1801 sky2->rx_ring = NULL;
1802 sky2->tx_ring = NULL;
1803
cd28ab6a
SH		 1804 return 0;
1805}
1806
1807static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1808{
ea76e635 1809 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1810 return SPEED_1000;
1811
05745c4a
SH		 1812 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1813 if (aux & PHY_M_PS_SPEED_100)
1814 return SPEED_100;
1815 else
1816 return SPEED_10;
1817 }
cd28ab6a
SH		 1818
1819 switch (aux & PHY_M_PS_SPEED_MSK) {
1820 case PHY_M_PS_SPEED_1000:
1821 return SPEED_1000;
1822 case PHY_M_PS_SPEED_100:
1823 return SPEED_100;
1824 default:
1825 return SPEED_10;
1826 }
1827}
1828
1829static void sky2_link_up(struct sky2_port *sky2)
1830{
1831 struct sky2_hw *hw = sky2->hw;
1832 unsigned port = sky2->port;
1833 u16 reg;
16ad91e1
SH		 1834 static const char *fc_name[] = {
1835 [FC_NONE] = "none",
1836 [FC_TX] = "tx",
1837 [FC_RX] = "rx",
1838 [FC_BOTH] = "both",
1839 };
cd28ab6a 1840
cd28ab6a 1841 /* enable Rx/Tx */
2eaba1a2 1842 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1843 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1844 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1845
1846 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1847
1848 netif_carrier_on(sky2->netdev);
cd28ab6a 1849
75e80683 1850 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1851
cd28ab6a 1852 /* Turn on link LED */
793b883e 1853 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1854 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1855
1856 if (netif_msg_link(sky2))
1857 printk(KERN_INFO PFX
d571b694 1858 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1859 sky2->netdev->name, sky2->speed,
1860 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1861 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1862}
1863
1864static void sky2_link_down(struct sky2_port *sky2)
1865{
1866 struct sky2_hw *hw = sky2->hw;
1867 unsigned port = sky2->port;
1868 u16 reg;
1869
1870 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1871
1872 reg = gma_read16(hw, port, GM_GP_CTRL);
1873 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1874 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1875
cd28ab6a 1876 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1877
1878 /* Turn on link LED */
1879 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1880
1881 if (netif_msg_link(sky2))
1882 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1883
cd28ab6a
SH		 1884 sky2_phy_init(hw, port);
1885}
1886
16ad91e1
SH		 1887static enum flow_control sky2_flow(int rx, int tx)
1888{
1889 if (rx)
1890 return tx ? FC_BOTH : FC_RX;
1891 else
1892 return tx ? FC_TX : FC_NONE;
1893}
1894
793b883e
SH		 1895static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1896{
1897 struct sky2_hw *hw = sky2->hw;
1898 unsigned port = sky2->port;
da4c1ff4 1899 u16 advert, lpa;
793b883e 1900
da4c1ff4 1901 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1902 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1903 if (lpa & PHY_M_AN_RF) {
1904 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1905 return -1;
1906 }
1907
793b883e
SH		 1908 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1909 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1910 sky2->netdev->name);
1911 return -1;
1912 }
1913
793b883e 1914 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1915 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1916
da4c1ff4
SH		 1917 /* Since the pause result bits seem to in different positions on
1918 * different chips. look at registers.
1919 */
ea76e635 1920 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1921 /* Shift for bits in fiber PHY */
1922 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1923 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1924
1925 if (advert & ADVERTISE_1000XPAUSE)
1926 advert |= ADVERTISE_PAUSE_CAP;
1927 if (advert & ADVERTISE_1000XPSE_ASYM)
1928 advert |= ADVERTISE_PAUSE_ASYM;
1929 if (lpa & LPA_1000XPAUSE)
1930 lpa |= LPA_PAUSE_CAP;
1931 if (lpa & LPA_1000XPAUSE_ASYM)
1932 lpa |= LPA_PAUSE_ASYM;
1933 }
793b883e 1934
da4c1ff4
SH		 1935 sky2->flow_status = FC_NONE;
1936 if (advert & ADVERTISE_PAUSE_CAP) {
1937 if (lpa & LPA_PAUSE_CAP)
1938 sky2->flow_status = FC_BOTH;
1939 else if (advert & ADVERTISE_PAUSE_ASYM)
1940 sky2->flow_status = FC_RX;
1941 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1942 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1943 sky2->flow_status = FC_TX;
1944 }
793b883e 1945
16ad91e1 1946 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1947 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1948 sky2->flow_status = FC_NONE;
2eaba1a2 1949
da4c1ff4 1950 if (sky2->flow_status & FC_TX)
793b883e
SH		 1951 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1952 else
1953 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1954
1955 return 0;
1956}
cd28ab6a 1957
e07b1aa8
SH		 1958/* Interrupt from PHY */
1959static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1960{
e07b1aa8
SH		 1961 struct net_device *dev = hw->dev[port];
1962 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1963 u16 istatus, phystat;
1964
ebc646f6
SH		 1965 if (!netif_running(dev))
1966 return;
1967
e07b1aa8
SH		 1968 spin_lock(&sky2->phy_lock);
1969 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1970 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1971
cd28ab6a
SH		 1972 if (netif_msg_intr(sky2))
1973 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1974 sky2->netdev->name, istatus, phystat);
1975
2eaba1a2 1976 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1977 if (sky2_autoneg_done(sky2, phystat) == 0)
1978 sky2_link_up(sky2);
1979 goto out;
1980 }
cd28ab6a 1981
793b883e
SH		 1982 if (istatus & PHY_M_IS_LSP_CHANGE)
1983 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1984
793b883e
SH		 1985 if (istatus & PHY_M_IS_DUP_CHANGE)
1986 sky2->duplex =
1987 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1988
793b883e
SH		 1989 if (istatus & PHY_M_IS_LST_CHANGE) {
1990 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1991 sky2_link_up(sky2);
793b883e
SH		 1992 else
1993 sky2_link_down(sky2);
cd28ab6a 1994 }
793b883e 1995out:
e07b1aa8 1996 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1997}
1998
62335ab0 1999/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2000 * and tx queue is full (stopped).
2001 */
cd28ab6a
SH		 2002static void sky2_tx_timeout(struct net_device *dev)
2003{
2004 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2005 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2006
2007 if (netif_msg_timer(sky2))
2008 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2009
8f24664d 2010 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2011 dev->name, sky2->tx_cons, sky2->tx_prod,
2012 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2013 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2014
81906791
SH		 2015 /* can't restart safely under softirq */
2016 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2017}
2018
2019static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2020{
6b1a3aef
SH		 2021 struct sky2_port *sky2 = netdev_priv(dev);
2022 struct sky2_hw *hw = sky2->hw;
b628ed98 2023 unsigned port = sky2->port;
6b1a3aef
SH		 2024 int err;
2025 u16 ctl, mode;
e07b1aa8 2026 u32 imask;
cd28ab6a
SH		 2027
2028 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2029 return -EINVAL;
2030
05745c4a
SH		 2031 if (new_mtu > ETH_DATA_LEN &&
2032 (hw->chip_id == CHIP_ID_YUKON_FE ||
2033 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2034 return -EINVAL;
2035
6b1a3aef
SH		 2036 if (!netif_running(dev)) {
2037 dev->mtu = new_mtu;
2038 return 0;
2039 }
2040
e07b1aa8 2041 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2042 sky2_write32(hw, B0_IMSK, 0);
2043
018d1c66
SH		 2044 dev->trans_start = jiffies; /* prevent tx timeout */
2045 netif_stop_queue(dev);
bea3348e 2046 napi_disable(&hw->napi);
018d1c66 2047
e07b1aa8
SH		 2048 synchronize_irq(hw->pdev->irq);
2049
39dbd958 2050 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2051 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2052
2053 ctl = gma_read16(hw, port, GM_GP_CTRL);
2054 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2055 sky2_rx_stop(sky2);
2056 sky2_rx_clean(sky2);
cd28ab6a
SH		 2057
2058 dev->mtu = new_mtu;
14d0263f 2059
6b1a3aef
SH		 2060 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2061 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2062
2063 if (dev->mtu > ETH_DATA_LEN)
2064 mode |= GM_SMOD_JUMBO_ENA;
2065
b628ed98 2066 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2067
b628ed98 2068 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2069
6b1a3aef 2070 err = sky2_rx_start(sky2);
e07b1aa8 2071 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2072
d1d08d12 2073 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2074 napi_enable(&hw->napi);
2075
1b537565
SH		 2076 if (err)
2077 dev_close(dev);
2078 else {
b628ed98 2079 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2080
1b537565
SH		 2081 netif_wake_queue(dev);
2082 }
2083
cd28ab6a
SH		 2084 return err;
2085}
2086
14d0263f
SH		 2087/* For small just reuse existing skb for next receive */
2088static struct sk_buff *receive_copy(struct sky2_port *sky2,
2089 const struct rx_ring_info *re,
2090 unsigned length)
2091{
2092 struct sk_buff *skb;
2093
2094 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2095 if (likely(skb)) {
2096 skb_reserve(skb, 2);
2097 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2098 length, PCI_DMA_FROMDEVICE);
d626f62b 2099 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2100 skb->ip_summed = re->skb->ip_summed;
2101 skb->csum = re->skb->csum;
2102 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2103 length, PCI_DMA_FROMDEVICE);
2104 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2105 skb_put(skb, length);
14d0263f
SH		 2106 }
2107 return skb;
2108}
2109
2110/* Adjust length of skb with fragments to match received data */
2111static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2112 unsigned int length)
2113{
2114 int i, num_frags;
2115 unsigned int size;
2116
2117 /* put header into skb */
2118 size = min(length, hdr_space);
2119 skb->tail += size;
2120 skb->len += size;
2121 length -= size;
2122
2123 num_frags = skb_shinfo(skb)->nr_frags;
2124 for (i = 0; i < num_frags; i++) {
2125 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2126
2127 if (length == 0) {
2128 /* don't need this page */
2129 __free_page(frag->page);
2130 --skb_shinfo(skb)->nr_frags;
2131 } else {
2132 size = min(length, (unsigned) PAGE_SIZE);
2133
2134 frag->size = size;
2135 skb->data_len += size;
2136 skb->truesize += size;
2137 skb->len += size;
2138 length -= size;
2139 }
2140 }
2141}
2142
2143/* Normal packet - take skb from ring element and put in a new one */
2144static struct sk_buff *receive_new(struct sky2_port *sky2,
2145 struct rx_ring_info *re,
2146 unsigned int length)
2147{
2148 struct sk_buff *skb, *nskb;
2149 unsigned hdr_space = sky2->rx_data_size;
2150
14d0263f
SH		 2151 /* Don't be tricky about reusing pages (yet) */
2152 nskb = sky2_rx_alloc(sky2);
2153 if (unlikely(!nskb))
2154 return NULL;
2155
2156 skb = re->skb;
2157 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2158
2159 prefetch(skb->data);
2160 re->skb = nskb;
2161 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2162
2163 if (skb_shinfo(skb)->nr_frags)
2164 skb_put_frags(skb, hdr_space, length);
2165 else
489b10c1 2166 skb_put(skb, length);
14d0263f
SH		 2167 return skb;
2168}
2169
cd28ab6a
SH		 2170/*
2171 * Receive one packet.
d571b694 2172 * For larger packets, get new buffer.
cd28ab6a 2173 */
497d7c86 2174static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2175 u16 length, u32 status)
2176{
497d7c86 2177 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2178 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2179 struct sk_buff *skb = NULL;
d6532232
SH		 2180 u16 count = (status & GMR_FS_LEN) >> 16;
2181
2182#ifdef SKY2_VLAN_TAG_USED
2183 /* Account for vlan tag */
2184 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2185 count -= VLAN_HLEN;
2186#endif
cd28ab6a
SH		 2187
2188 if (unlikely(netif_msg_rx_status(sky2)))
2189 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2190 dev->name, sky2->rx_next, status, length);
cd28ab6a 2191
793b883e 2192 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2193 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2194
3b12e014
SH		 2195 /* This chip has hardware problems that generates bogus status.
2196 * So do only marginal checking and expect higher level protocols
2197 * to handle crap frames.
2198 */
2199 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2200 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2201 length != count)
2202 goto okay;
2203
42eeea01 2204 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2205 goto error;
2206
42eeea01
SH		 2207 if (!(status & GMR_FS_RX_OK))
2208 goto resubmit;
2209
d6532232
SH		 2210 /* if length reported by DMA does not match PHY, packet was truncated */
2211 if (length != count)
3b12e014 2212 goto len_error;
71749531 2213
3b12e014 2214okay:
14d0263f
SH		 2215 if (length < copybreak)
2216 skb = receive_copy(sky2, re, length);
2217 else
2218 skb = receive_new(sky2, re, length);
793b883e 2219resubmit:
14d0263f 2220 sky2_rx_submit(sky2, re);
79e57d32 2221
cd28ab6a
SH		 2222 return skb;
2223
3b12e014 2224len_error:
71749531
SH		 2225 /* Truncation of overlength packets
2226 causes PHY length to not match MAC length */
7138a0f5 2227 ++dev->stats.rx_length_errors;
d6532232 2228 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2229 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2230 dev->name, status, length);
d6532232 2231 goto resubmit;
71749531 2232
cd28ab6a 2233error:
7138a0f5 2234 ++dev->stats.rx_errors;
b6d77734 2235 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2236 dev->stats.rx_over_errors++;
b6d77734
SH		 2237 goto resubmit;
2238 }
6e15b712 2239
3be92a70 2240 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2241 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2242 dev->name, status, length);
793b883e
SH		 2243
2244 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2245 dev->stats.rx_length_errors++;
cd28ab6a 2246 if (status & GMR_FS_FRAGMENT)
7138a0f5 2247 dev->stats.rx_frame_errors++;
cd28ab6a 2248 if (status & GMR_FS_CRC_ERR)
7138a0f5 2249 dev->stats.rx_crc_errors++;
79e57d32 2250
793b883e 2251 goto resubmit;
cd28ab6a
SH		 2252}
2253
e07b1aa8
SH		 2254/* Transmit complete */
2255static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2256{
e07b1aa8 2257 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2258
e07b1aa8 2259 if (netif_running(dev)) {
2bb8c262 2260 netif_tx_lock(dev);
e07b1aa8 2261 sky2_tx_complete(sky2, last);
2bb8c262 2262 netif_tx_unlock(dev);
2224795d 2263 }
cd28ab6a
SH		 2264}
2265
e07b1aa8 2266/* Process status response ring */
26691830 2267static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2268{
e07b1aa8 2269 int work_done = 0;
55c9dd35 2270 unsigned rx[2] = { 0, 0 };
a8fd6266 2271
af2a58ac 2272 rmb();
26691830 2273 do {
55c9dd35 2274 struct sky2_port *sky2;
13210ce5 2275 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2276 unsigned port;
13210ce5 2277 struct net_device *dev;
cd28ab6a 2278 struct sk_buff *skb;
cd28ab6a
SH		 2279 u32 status;
2280 u16 length;
ab5adecb
SH		 2281 u8 opcode = le->opcode;
2282
2283 if (!(opcode & HW_OWNER))
2284 break;
cd28ab6a 2285
cb5d9547 2286 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2287
ab5adecb 2288 port = le->css & CSS_LINK_BIT;
69161611 2289 dev = hw->dev[port];
13210ce5 2290 sky2 = netdev_priv(dev);
f65b138c
SH		 2291 length = le16_to_cpu(le->length);
2292 status = le32_to_cpu(le->status);
cd28ab6a 2293
ab5adecb
SH		 2294 le->opcode = 0;
2295 switch (opcode & ~HW_OWNER) {
cd28ab6a 2296 case OP_RXSTAT:
55c9dd35 2297 ++rx[port];
497d7c86 2298 skb = sky2_receive(dev, length, status);
3225b919 2299 if (unlikely(!skb)) {
7138a0f5 2300 dev->stats.rx_dropped++;
55c9dd35 2301 break;
3225b919 2302 }
13210ce5 2303
69161611 2304 /* This chip reports checksum status differently */
05745c4a 2305 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2306 if (sky2->rx_csum &&
2307 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2308 (le->css & CSS_TCPUDPCSOK))
2309 skb->ip_summed = CHECKSUM_UNNECESSARY;
2310 else
2311 skb->ip_summed = CHECKSUM_NONE;
2312 }
2313
13210ce5 2314 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2315 dev->stats.rx_packets++;
2316 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2317 dev->last_rx = jiffies;
2318
d1f13708
SH		 2319#ifdef SKY2_VLAN_TAG_USED
2320 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2321 vlan_hwaccel_receive_skb(skb,
2322 sky2->vlgrp,
2323 be16_to_cpu(sky2->rx_tag));
2324 } else
2325#endif
cd28ab6a 2326 netif_receive_skb(skb);
13210ce5 2327
22e11703 2328 /* Stop after net poll weight */
13210ce5
SH		 2329 if (++work_done >= to_do)
2330 goto exit_loop;
cd28ab6a
SH		 2331 break;
2332
d1f13708
SH		 2333#ifdef SKY2_VLAN_TAG_USED
2334 case OP_RXVLAN:
2335 sky2->rx_tag = length;
2336 break;
2337
2338 case OP_RXCHKSVLAN:
2339 sky2->rx_tag = length;
2340 /* fall through */
2341#endif
cd28ab6a 2342 case OP_RXCHKS:
87418307
SH		 2343 if (!sky2->rx_csum)
2344 break;
2345
05745c4a
SH		 2346 /* If this happens then driver assuming wrong format */
2347 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2348 if (net_ratelimit())
2349 printk(KERN_NOTICE "%s: unexpected"
2350 " checksum status\n",
2351 dev->name);
69161611 2352 break;
05745c4a 2353 }
69161611 2354
87418307
SH		 2355 /* Both checksum counters are programmed to start at
2356 * the same offset, so unless there is a problem they
2357 * should match. This failure is an early indication that
2358 * hardware receive checksumming won't work.
2359 */
2360 if (likely(status >> 16 == (status & 0xffff))) {
2361 skb = sky2->rx_ring[sky2->rx_next].skb;
2362 skb->ip_summed = CHECKSUM_COMPLETE;
2363 skb->csum = status & 0xffff;
2364 } else {
2365 printk(KERN_NOTICE PFX "%s: hardware receive "
2366 "checksum problem (status = %#x)\n",
2367 dev->name, status);
2368 sky2->rx_csum = 0;
2369 sky2_write32(sky2->hw,
69161611 2370 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2371 BMU_DIS_RX_CHKSUM);
2372 }
cd28ab6a
SH		 2373 break;
2374
2375 case OP_TXINDEXLE:
13b97b74 2376 /* TX index reports status for both ports */
f55925d7
SH		 2377 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2378 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2379 if (hw->dev[1])
2380 sky2_tx_done(hw->dev[1],
2381 ((status >> 24) & 0xff)
2382 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2383 break;
2384
cd28ab6a
SH		 2385 default:
2386 if (net_ratelimit())
793b883e 2387 printk(KERN_WARNING PFX
ab5adecb 2388 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2389 }
26691830 2390 } while (hw->st_idx != idx);
cd28ab6a 2391
fe2a24df
SH		 2392 /* Fully processed status ring so clear irq */
2393 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2394
13210ce5 2395exit_loop:
55c9dd35
SH		 2396 if (rx[0])
2397 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2398
55c9dd35
SH		 2399 if (rx[1])
2400 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2401
e07b1aa8 2402 return work_done;
cd28ab6a
SH		 2403}
2404
2405static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2406{
2407 struct net_device *dev = hw->dev[port];
2408
3be92a70
SH		 2409 if (net_ratelimit())
2410 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2411 dev->name, status);
cd28ab6a
SH		 2412
2413 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2414 if (net_ratelimit())
2415 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2416 dev->name);
cd28ab6a
SH		 2417 /* Clear IRQ */
2418 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2419 }
2420
2421 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2422 if (net_ratelimit())
2423 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2424 dev->name);
cd28ab6a
SH		 2425
2426 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2427 }
2428
2429 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2430 if (net_ratelimit())
2431 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2432 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2433 }
2434
2435 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2436 if (net_ratelimit())
2437 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2438 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2439 }
2440
2441 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2442 if (net_ratelimit())
2443 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2444 dev->name);
cd28ab6a
SH		 2445 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2446 }
2447}
2448
2449static void sky2_hw_intr(struct sky2_hw *hw)
2450{
555382cb 2451 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2452 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2453 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2454
2455 status &= hwmsk;
cd28ab6a 2456
793b883e 2457 if (status & Y2_IS_TIST_OV)
cd28ab6a 2458 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2459
2460 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2461 u16 pci_err;
2462
82637e80 2463 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2464 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2465 if (net_ratelimit())
555382cb 2466 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2467 pci_err);
cd28ab6a 2468
b32f40c4 2469 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2470 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2471 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2472 }
2473
2474 if (status & Y2_IS_PCI_EXP) {
d571b694 2475 /* PCI-Express uncorrectable Error occurred */
555382cb 2476 u32 err;
cd28ab6a 2477
82637e80 2478 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2479 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2480 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2481 0xfffffffful);
3be92a70 2482 if (net_ratelimit())
555382cb 2483 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2484
7782c8c4 2485 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2486 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2487 }
2488
2489 if (status & Y2_HWE_L1_MASK)
2490 sky2_hw_error(hw, 0, status);
2491 status >>= 8;
2492 if (status & Y2_HWE_L1_MASK)
2493 sky2_hw_error(hw, 1, status);
2494}
2495
2496static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2497{
2498 struct net_device *dev = hw->dev[port];
2499 struct sky2_port *sky2 = netdev_priv(dev);
2500 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2501
2502 if (netif_msg_intr(sky2))
2503 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2504 dev->name, status);
2505
a3caeada
SH		 2506 if (status & GM_IS_RX_CO_OV)
2507 gma_read16(hw, port, GM_RX_IRQ_SRC);
2508
2509 if (status & GM_IS_TX_CO_OV)
2510 gma_read16(hw, port, GM_TX_IRQ_SRC);
2511
cd28ab6a 2512 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2513 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2514 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2515 }
2516
2517 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2518 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2519 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2520 }
cd28ab6a
SH		 2521}
2522
40b01727
SH		 2523/* This should never happen it is a bug. */
2524static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2525 u16 q, unsigned ring_size)
d257924e
SH		 2526{
2527 struct net_device *dev = hw->dev[port];
2528 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2529 unsigned idx;
2530 const u64 *le = (q == Q_R1 || q == Q_R2)
2531 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2532
40b01727
SH		 2533 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2534 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2535 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2536 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2537
40b01727 2538 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2539}
cd28ab6a 2540
75e80683
SH		 2541static int sky2_rx_hung(struct net_device *dev)
2542{
2543 struct sky2_port *sky2 = netdev_priv(dev);
2544 struct sky2_hw *hw = sky2->hw;
2545 unsigned port = sky2->port;
2546 unsigned rxq = rxqaddr[port];
2547 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2548 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2549 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2550 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2551
2552 /* If idle and MAC or PCI is stuck */
2553 if (sky2->check.last == dev->last_rx &&
2554 ((mac_rp == sky2->check.mac_rp &&
2555 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2556 /* Check if the PCI RX hang */
2557 (fifo_rp == sky2->check.fifo_rp &&
2558 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2559 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2560 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2561 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2562 return 1;
2563 } else {
2564 sky2->check.last = dev->last_rx;
2565 sky2->check.mac_rp = mac_rp;
2566 sky2->check.mac_lev = mac_lev;
2567 sky2->check.fifo_rp = fifo_rp;
2568 sky2->check.fifo_lev = fifo_lev;
2569 return 0;
2570 }
2571}
2572
32c2c300 2573static void sky2_watchdog(unsigned long arg)
d27ed387 2574{
01bd7564 2575 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2576
75e80683 2577 /* Check for lost IRQ once a second */
32c2c300 2578 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2579 napi_schedule(&hw->napi);
75e80683
SH		 2580 } else {
2581 int i, active = 0;
2582
2583 for (i = 0; i < hw->ports; i++) {
bea3348e 2584 struct net_device *dev = hw->dev[i];
75e80683
SH		 2585 if (!netif_running(dev))
2586 continue;
2587 ++active;
2588
2589 /* For chips with Rx FIFO, check if stuck */
39dbd958 2590 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2591 sky2_rx_hung(dev)) {
2592 pr_info(PFX "%s: receiver hang detected\n",
2593 dev->name);
2594 schedule_work(&hw->restart_work);
2595 return;
2596 }
2597 }
2598
2599 if (active == 0)
2600 return;
32c2c300 2601 }
01bd7564 2602
75e80683 2603 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2604}
2605
40b01727
SH		 2606/* Hardware/software error handling */
2607static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2608{
40b01727
SH		 2609 if (net_ratelimit())
2610 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2611
1e5f1283
SH		 2612 if (status & Y2_IS_HW_ERR)
2613 sky2_hw_intr(hw);
d257924e 2614
1e5f1283
SH		 2615 if (status & Y2_IS_IRQ_MAC1)
2616 sky2_mac_intr(hw, 0);
cd28ab6a 2617
1e5f1283
SH		 2618 if (status & Y2_IS_IRQ_MAC2)
2619 sky2_mac_intr(hw, 1);
cd28ab6a 2620
1e5f1283 2621 if (status & Y2_IS_CHK_RX1)
40b01727 2622 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2623
1e5f1283 2624 if (status & Y2_IS_CHK_RX2)
40b01727 2625 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2626
1e5f1283 2627 if (status & Y2_IS_CHK_TXA1)
40b01727 2628 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2629
1e5f1283 2630 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2631 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2632}
2633
bea3348e 2634static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2635{
bea3348e 2636 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2637 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2638 int work_done = 0;
26691830 2639 u16 idx;
40b01727
SH		 2640
2641 if (unlikely(status & Y2_IS_ERROR))
2642 sky2_err_intr(hw, status);
2643
2644 if (status & Y2_IS_IRQ_PHY1)
2645 sky2_phy_intr(hw, 0);
2646
2647 if (status & Y2_IS_IRQ_PHY2)
2648 sky2_phy_intr(hw, 1);
cd28ab6a 2649
26691830
SH		 2650 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2651 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2652
2653 if (work_done >= work_limit)
26691830
SH		 2654 goto done;
2655 }
6f535763 2656
26691830
SH		 2657 /* Bug/Errata workaround?
2658 * Need to kick the TX irq moderation timer.
2659 */
2660 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2661 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2662 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2663 }
26691830
SH		 2664 napi_complete(napi);
2665 sky2_read32(hw, B0_Y2_SP_LISR);
2666done:
6f535763 2667
bea3348e 2668 return work_done;
e07b1aa8
SH		 2669}
2670
7d12e780 2671static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2672{
2673 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2674 u32 status;
2675
2676 /* Reading this mask interrupts as side effect */
2677 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2678 if (status == 0 || status == ~0)
2679 return IRQ_NONE;
793b883e 2680
e07b1aa8 2681 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2682
2683 napi_schedule(&hw->napi);
793b883e 2684
cd28ab6a
SH		 2685 return IRQ_HANDLED;
2686}
2687
2688#ifdef CONFIG_NET_POLL_CONTROLLER
2689static void sky2_netpoll(struct net_device *dev)
2690{
2691 struct sky2_port *sky2 = netdev_priv(dev);
2692
bea3348e 2693 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2694}
2695#endif
2696
2697/* Chip internal frequency for clock calculations */
05745c4a 2698static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2699{
793b883e 2700 switch (hw->chip_id) {
cd28ab6a 2701 case CHIP_ID_YUKON_EC:
5a5b1ea0 2702 case CHIP_ID_YUKON_EC_U:
93745494 2703 case CHIP_ID_YUKON_EX:
ed4d4161 2704 case CHIP_ID_YUKON_SUPR:
05745c4a
SH		 2705 return 125;
2706
cd28ab6a 2707 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2708 return 100;
2709
2710 case CHIP_ID_YUKON_FE_P:
2711 return 50;
2712
2713 case CHIP_ID_YUKON_XL:
2714 return 156;
2715
2716 default:
2717 BUG();
cd28ab6a
SH		 2718 }
2719}
2720
fb17358f 2721static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2722{
fb17358f 2723 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2724}
2725
fb17358f 2726static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2727{
fb17358f 2728 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2729}
2730
fb17358f 2731
e3173832 2732static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2733{
b89165f2 2734 u8 t8;
cd28ab6a 2735
167f53d0 2736 /* Enable all clocks and check for bad PCI access */
b32f40c4 2737 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2738
cd28ab6a 2739 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2740
cd28ab6a 2741 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2742 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2743
2744 switch(hw->chip_id) {
2745 case CHIP_ID_YUKON_XL:
39dbd958 2746 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2747 break;
2748
2749 case CHIP_ID_YUKON_EC_U:
2750 hw->flags = SKY2_HW_GIGABIT
2751 | SKY2_HW_NEWER_PHY
2752 | SKY2_HW_ADV_POWER_CTL;
2753 break;
2754
2755 case CHIP_ID_YUKON_EX:
2756 hw->flags = SKY2_HW_GIGABIT
2757 | SKY2_HW_NEWER_PHY
2758 | SKY2_HW_NEW_LE
2759 | SKY2_HW_ADV_POWER_CTL;
2760
2761 /* New transmit checksum */
2762 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2763 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2764 break;
2765
2766 case CHIP_ID_YUKON_EC:
2767 /* This rev is really old, and requires untested workarounds */
2768 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2769 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2770 return -EOPNOTSUPP;
2771 }
39dbd958 2772 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2773 break;
2774
2775 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2776 break;
2777
05745c4a
SH		 2778 case CHIP_ID_YUKON_FE_P:
2779 hw->flags = SKY2_HW_NEWER_PHY
2780 | SKY2_HW_NEW_LE
2781 | SKY2_HW_AUTO_TX_SUM
2782 | SKY2_HW_ADV_POWER_CTL;
2783 break;
ed4d4161
SH		 2784
2785 case CHIP_ID_YUKON_SUPR:
2786 hw->flags = SKY2_HW_GIGABIT
2787 | SKY2_HW_NEWER_PHY
2788 | SKY2_HW_NEW_LE
2789 | SKY2_HW_AUTO_TX_SUM
2790 | SKY2_HW_ADV_POWER_CTL;
2791 break;
2792
ea76e635 2793 default:
b02a9258
SH		 2794 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2795 hw->chip_id);
cd28ab6a
SH		 2796 return -EOPNOTSUPP;
2797 }
2798
ea76e635
SH		 2799 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2800 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2801 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2802
290d4de5 2803
e3173832
SH		 2804 hw->ports = 1;
2805 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2806 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2807 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2808 ++hw->ports;
2809 }
2810
2811 return 0;
2812}
2813
2814static void sky2_reset(struct sky2_hw *hw)
2815{
555382cb 2816 struct pci_dev *pdev = hw->pdev;
e3173832 2817 u16 status;
555382cb
SH		 2818 int i, cap;
2819 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2820
cd28ab6a 2821 /* disable ASF */
4f44d8ba
SH		 2822 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2823 status = sky2_read16(hw, HCU_CCSR);
2824 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2825 HCU_CCSR_UC_STATE_MSK);
2826 sky2_write16(hw, HCU_CCSR, status);
2827 } else
2828 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2829 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2830
2831 /* do a SW reset */
2832 sky2_write8(hw, B0_CTST, CS_RST_SET);
2833 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2834
ac93a394
SH		 2835 /* allow writes to PCI config */
2836 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2837
cd28ab6a 2838 /* clear PCI errors, if any */
b32f40c4 2839 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2840 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2841 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2842
2843 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2844
555382cb
SH		 2845 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2846 if (cap) {
7782c8c4
SH		 2847 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2848 0xfffffffful);
555382cb
SH		 2849
2850 /* If error bit is stuck on ignore it */
2851 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2852 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2853 else
555382cb
SH		 2854 hwe_mask |= Y2_IS_PCI_EXP;
2855 }
cd28ab6a 2856
ae306cca 2857 sky2_power_on(hw);
82637e80 2858 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2859
2860 for (i = 0; i < hw->ports; i++) {
2861 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2862 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2863
ed4d4161
SH		 2864 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2865 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2866 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2867 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2868 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2869 }
2870
793b883e
SH		 2871 /* Clear I2C IRQ noise */
2872 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2873
2874 /* turn off hardware timer (unused) */
2875 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2876 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2877
cd28ab6a
SH		 2878 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2879
69634ee7
SH		 2880 /* Turn off descriptor polling */
2881 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2882
2883 /* Turn off receive timestamp */
2884 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2885 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2886
2887 /* enable the Tx Arbiters */
2888 for (i = 0; i < hw->ports; i++)
2889 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2890
2891 /* Initialize ram interface */
2892 for (i = 0; i < hw->ports; i++) {
793b883e 2893 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2894
2895 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2896 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2897 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2898 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2899 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2900 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2901 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2902 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2903 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2904 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2905 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2906 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2907 }
2908
555382cb 2909 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2910
cd28ab6a 2911 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2912 sky2_gmac_reset(hw, i);
cd28ab6a 2913
cd28ab6a
SH		 2914 memset(hw->st_le, 0, STATUS_LE_BYTES);
2915 hw->st_idx = 0;
2916
2917 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2918 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2919
2920 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2921 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2922
2923 /* Set the list last index */
793b883e 2924 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2925
290d4de5
SH		 2926 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2927 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2928
290d4de5
SH		 2929 /* set Status-FIFO ISR watermark */
2930 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2931 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2932 else
2933 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2934
290d4de5 2935 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2936 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2937 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2938
793b883e 2939 /* enable status unit */
cd28ab6a
SH		 2940 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2941
2942 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2943 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2944 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2945}
2946
81906791
SH		 2947static void sky2_restart(struct work_struct *work)
2948{
2949 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2950 struct net_device *dev;
2951 int i, err;
2952
81906791 2953 rtnl_lock();
81906791
SH		 2954 for (i = 0; i < hw->ports; i++) {
2955 dev = hw->dev[i];
2956 if (netif_running(dev))
2957 sky2_down(dev);
2958 }
2959
8cfcbe99
SH		 2960 napi_disable(&hw->napi);
2961 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 2962 sky2_reset(hw);
2963 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2964 napi_enable(&hw->napi);
81906791
SH		 2965
2966 for (i = 0; i < hw->ports; i++) {
2967 dev = hw->dev[i];
2968 if (netif_running(dev)) {
2969 err = sky2_up(dev);
2970 if (err) {
2971 printk(KERN_INFO PFX "%s: could not restart %d\n",
2972 dev->name, err);
2973 dev_close(dev);
2974 }
2975 }
2976 }
2977
81906791
SH		 2978 rtnl_unlock();
2979}
2980
e3173832
SH		 2981static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2982{
2983 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2984}
2985
2986static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2987{
2988 const struct sky2_port *sky2 = netdev_priv(dev);
2989
2990 wol->supported = sky2_wol_supported(sky2->hw);
2991 wol->wolopts = sky2->wol;
2992}
2993
2994static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2995{
2996 struct sky2_port *sky2 = netdev_priv(dev);
2997 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2998
e3173832
SH		 2999 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3000 return -EOPNOTSUPP;
3001
3002 sky2->wol = wol->wolopts;
3003
05745c4a
SH		 3004 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3005 hw->chip_id == CHIP_ID_YUKON_EX ||
3006 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3007 sky2_write32(hw, B0_CTST, sky2->wol
3008 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3009
3010 if (!netif_running(dev))
3011 sky2_wol_init(sky2);
cd28ab6a
SH		 3012 return 0;
3013}
3014
28bd181a 3015static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3016{
b89165f2
SH		 3017 if (sky2_is_copper(hw)) {
3018 u32 modes = SUPPORTED_10baseT_Half
3019 | SUPPORTED_10baseT_Full
3020 | SUPPORTED_100baseT_Half
3021 | SUPPORTED_100baseT_Full
3022 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3023
ea76e635 3024 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3025 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3026 | SUPPORTED_1000baseT_Full;
3027 return modes;
cd28ab6a 3028 } else
b89165f2
SH		 3029 return SUPPORTED_1000baseT_Half
3030 | SUPPORTED_1000baseT_Full
3031 | SUPPORTED_Autoneg
3032 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3033}
3034
793b883e 3035static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3036{
3037 struct sky2_port *sky2 = netdev_priv(dev);
3038 struct sky2_hw *hw = sky2->hw;
3039
3040 ecmd->transceiver = XCVR_INTERNAL;
3041 ecmd->supported = sky2_supported_modes(hw);
3042 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3043 if (sky2_is_copper(hw)) {
cd28ab6a 3044 ecmd->port = PORT_TP;
b89165f2
SH		 3045 ecmd->speed = sky2->speed;
3046 } else {
3047 ecmd->speed = SPEED_1000;
cd28ab6a 3048 ecmd->port = PORT_FIBRE;
b89165f2 3049 }
cd28ab6a
SH		 3050
3051 ecmd->advertising = sky2->advertising;
3052 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3053 ecmd->duplex = sky2->duplex;
3054 return 0;
3055}
3056
3057static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3058{
3059 struct sky2_port *sky2 = netdev_priv(dev);
3060 const struct sky2_hw *hw = sky2->hw;
3061 u32 supported = sky2_supported_modes(hw);
3062
3063 if (ecmd->autoneg == AUTONEG_ENABLE) {
3064 ecmd->advertising = supported;
3065 sky2->duplex = -1;
3066 sky2->speed = -1;
3067 } else {
3068 u32 setting;
3069
793b883e 3070 switch (ecmd->speed) {
cd28ab6a
SH		 3071 case SPEED_1000:
3072 if (ecmd->duplex == DUPLEX_FULL)
3073 setting = SUPPORTED_1000baseT_Full;
3074 else if (ecmd->duplex == DUPLEX_HALF)
3075 setting = SUPPORTED_1000baseT_Half;
3076 else
3077 return -EINVAL;
3078 break;
3079 case SPEED_100:
3080 if (ecmd->duplex == DUPLEX_FULL)
3081 setting = SUPPORTED_100baseT_Full;
3082 else if (ecmd->duplex == DUPLEX_HALF)
3083 setting = SUPPORTED_100baseT_Half;
3084 else
3085 return -EINVAL;
3086 break;
3087
3088 case SPEED_10:
3089 if (ecmd->duplex == DUPLEX_FULL)
3090 setting = SUPPORTED_10baseT_Full;
3091 else if (ecmd->duplex == DUPLEX_HALF)
3092 setting = SUPPORTED_10baseT_Half;
3093 else
3094 return -EINVAL;
3095 break;
3096 default:
3097 return -EINVAL;
3098 }
3099
3100 if ((setting & supported) == 0)
3101 return -EINVAL;
3102
3103 sky2->speed = ecmd->speed;
3104 sky2->duplex = ecmd->duplex;
3105 }
3106
3107 sky2->autoneg = ecmd->autoneg;
3108 sky2->advertising = ecmd->advertising;
3109
d1b139c0 3110 if (netif_running(dev)) {
1b537565 3111 sky2_phy_reinit(sky2);
d1b139c0
SH		 3112 sky2_set_multicast(dev);
3113 }
cd28ab6a
SH		 3114
3115 return 0;
3116}
3117
3118static void sky2_get_drvinfo(struct net_device *dev,
3119 struct ethtool_drvinfo *info)
3120{
3121 struct sky2_port *sky2 = netdev_priv(dev);
3122
3123 strcpy(info->driver, DRV_NAME);
3124 strcpy(info->version, DRV_VERSION);
3125 strcpy(info->fw_version, "N/A");
3126 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3127}
3128
3129static const struct sky2_stat {
793b883e
SH		 3130 char name[ETH_GSTRING_LEN];
3131 u16 offset;
cd28ab6a
SH		 3132} sky2_stats[] = {
3133 { "tx_bytes", GM_TXO_OK_HI },
3134 { "rx_bytes", GM_RXO_OK_HI },
3135 { "tx_broadcast", GM_TXF_BC_OK },
3136 { "rx_broadcast", GM_RXF_BC_OK },
3137 { "tx_multicast", GM_TXF_MC_OK },
3138 { "rx_multicast", GM_RXF_MC_OK },
3139 { "tx_unicast", GM_TXF_UC_OK },
3140 { "rx_unicast", GM_RXF_UC_OK },
3141 { "tx_mac_pause", GM_TXF_MPAUSE },
3142 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3143 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3144 { "late_collision",GM_TXF_LAT_COL },
3145 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3146 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3147 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3148
d2604540 3149 { "rx_short", GM_RXF_SHT },
cd28ab6a 3150 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3151 { "rx_64_byte_packets", GM_RXF_64B },
3152 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3153 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3154 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3155 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3156 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3157 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3158 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3159 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3160 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3161 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3162
3163 { "tx_64_byte_packets", GM_TXF_64B },
3164 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3165 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3166 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3167 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3168 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3169 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3170 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3171};
3172
cd28ab6a
SH		 3173static u32 sky2_get_rx_csum(struct net_device *dev)
3174{
3175 struct sky2_port *sky2 = netdev_priv(dev);
3176
3177 return sky2->rx_csum;
3178}
3179
3180static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3181{
3182 struct sky2_port *sky2 = netdev_priv(dev);
3183
3184 sky2->rx_csum = data;
793b883e 3185
cd28ab6a
SH		 3186 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3187 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3188
3189 return 0;
3190}
3191
3192static u32 sky2_get_msglevel(struct net_device *netdev)
3193{
3194 struct sky2_port *sky2 = netdev_priv(netdev);
3195 return sky2->msg_enable;
3196}
3197
9a7ae0a9
SH		 3198static int sky2_nway_reset(struct net_device *dev)
3199{
3200 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3201
16ad91e1 3202 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3203 return -EINVAL;
3204
1b537565 3205 sky2_phy_reinit(sky2);
d1b139c0 3206 sky2_set_multicast(dev);
9a7ae0a9
SH		 3207
3208 return 0;
3209}
3210
793b883e 3211static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3212{
3213 struct sky2_hw *hw = sky2->hw;
3214 unsigned port = sky2->port;
3215 int i;
3216
3217 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3218 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3219 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3220 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3221
793b883e 3222 for (i = 2; i < count; i++)
cd28ab6a
SH		 3223 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3224}
3225
cd28ab6a
SH		 3226static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3227{
3228 struct sky2_port *sky2 = netdev_priv(netdev);
3229 sky2->msg_enable = value;
3230}
3231
b9f2c044 3232static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3233{
b9f2c044
JG		 3234 switch (sset) {
3235 case ETH_SS_STATS:
3236 return ARRAY_SIZE(sky2_stats);
3237 default:
3238 return -EOPNOTSUPP;
3239 }
cd28ab6a
SH		 3240}
3241
3242static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3243 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3244{
3245 struct sky2_port *sky2 = netdev_priv(dev);
3246
793b883e 3247 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3248}
3249
793b883e 3250static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3251{
3252 int i;
3253
3254 switch (stringset) {
3255 case ETH_SS_STATS:
3256 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3257 memcpy(data + i * ETH_GSTRING_LEN,
3258 sky2_stats[i].name, ETH_GSTRING_LEN);
3259 break;
3260 }
3261}
3262
cd28ab6a
SH		 3263static int sky2_set_mac_address(struct net_device *dev, void *p)
3264{
3265 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3266 struct sky2_hw *hw = sky2->hw;
3267 unsigned port = sky2->port;
3268 const struct sockaddr *addr = p;
cd28ab6a
SH		 3269
3270 if (!is_valid_ether_addr(addr->sa_data))
3271 return -EADDRNOTAVAIL;
3272
cd28ab6a 3273 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3274 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3275 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3276 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3277 dev->dev_addr, ETH_ALEN);
1b537565 3278
a8ab1ec0
SH		 3279 /* virtual address for data */
3280 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3281
3282 /* physical address: used for pause frames */
3283 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3284
3285 return 0;
cd28ab6a
SH		 3286}
3287
a052b52f
SH		 3288static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3289{
3290 u32 bit;
3291
3292 bit = ether_crc(ETH_ALEN, addr) & 63;
3293 filter[bit >> 3] |= 1 << (bit & 7);
3294}
3295
cd28ab6a
SH		 3296static void sky2_set_multicast(struct net_device *dev)
3297{
3298 struct sky2_port *sky2 = netdev_priv(dev);
3299 struct sky2_hw *hw = sky2->hw;
3300 unsigned port = sky2->port;
3301 struct dev_mc_list *list = dev->mc_list;
3302 u16 reg;
3303 u8 filter[8];
a052b52f
SH		 3304 int rx_pause;
3305 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3306
a052b52f 3307 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3308 memset(filter, 0, sizeof(filter));
3309
3310 reg = gma_read16(hw, port, GM_RX_CTRL);
3311 reg |= GM_RXCR_UCF_ENA;
3312
d571b694 3313 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3314 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3315 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3316 memset(filter, 0xff, sizeof(filter));
a052b52f 3317 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3318 reg &= ~GM_RXCR_MCF_ENA;
3319 else {
3320 int i;
3321 reg |= GM_RXCR_MCF_ENA;
3322
a052b52f
SH		 3323 if (rx_pause)
3324 sky2_add_filter(filter, pause_mc_addr);
3325
3326 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3327 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3328 }
3329
cd28ab6a 3330 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3331 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3332 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3333 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3334 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3335 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3336 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3337 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3338
3339 gma_write16(hw, port, GM_RX_CTRL, reg);
3340}
3341
3342/* Can have one global because blinking is controlled by
3343 * ethtool and that is always under RTNL mutex
3344 */
a84d0a3d 3345static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3346{
a84d0a3d
SH		 3347 struct sky2_hw *hw = sky2->hw;
3348 unsigned port = sky2->port;
793b883e 3349
a84d0a3d
SH		 3350 spin_lock_bh(&sky2->phy_lock);
3351 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3352 hw->chip_id == CHIP_ID_YUKON_EX ||
3353 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3354 u16 pg;
793b883e
SH		 3355 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3357
a84d0a3d
SH		 3358 switch (mode) {
3359 case MO_LED_OFF:
3360 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3361 PHY_M_LEDC_LOS_CTRL(8) |
3362 PHY_M_LEDC_INIT_CTRL(8) |
3363 PHY_M_LEDC_STA1_CTRL(8) |
3364 PHY_M_LEDC_STA0_CTRL(8));
3365 break;
3366 case MO_LED_ON:
3367 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3368 PHY_M_LEDC_LOS_CTRL(9) |
3369 PHY_M_LEDC_INIT_CTRL(9) |
3370 PHY_M_LEDC_STA1_CTRL(9) |
3371 PHY_M_LEDC_STA0_CTRL(9));
3372 break;
3373 case MO_LED_BLINK:
3374 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3375 PHY_M_LEDC_LOS_CTRL(0xa) |
3376 PHY_M_LEDC_INIT_CTRL(0xa) |
3377 PHY_M_LEDC_STA1_CTRL(0xa) |
3378 PHY_M_LEDC_STA0_CTRL(0xa));
3379 break;
3380 case MO_LED_NORM:
3381 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3382 PHY_M_LEDC_LOS_CTRL(1) |
3383 PHY_M_LEDC_INIT_CTRL(8) |
3384 PHY_M_LEDC_STA1_CTRL(7) |
3385 PHY_M_LEDC_STA0_CTRL(7));
3386 }
793b883e 3387
a84d0a3d
SH		 3388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3389 } else
7d2e3cb7 3390 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3391 PHY_M_LED_MO_DUP(mode) |
3392 PHY_M_LED_MO_10(mode) |
3393 PHY_M_LED_MO_100(mode) |
3394 PHY_M_LED_MO_1000(mode) |
3395 PHY_M_LED_MO_RX(mode) |
3396 PHY_M_LED_MO_TX(mode));
3397
3398 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3399}
3400
3401/* blink LED's for finding board */
3402static int sky2_phys_id(struct net_device *dev, u32 data)
3403{
3404 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3405 unsigned int i;
cd28ab6a 3406
a84d0a3d
SH		 3407 if (data == 0)
3408 data = UINT_MAX;
cd28ab6a 3409
a84d0a3d
SH		 3410 for (i = 0; i < data; i++) {
3411 sky2_led(sky2, MO_LED_ON);
3412 if (msleep_interruptible(500))
3413 break;
3414 sky2_led(sky2, MO_LED_OFF);
3415 if (msleep_interruptible(500))
3416 break;
793b883e 3417 }
a84d0a3d 3418 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3419
3420 return 0;
3421}
3422
3423static void sky2_get_pauseparam(struct net_device *dev,
3424 struct ethtool_pauseparam *ecmd)
3425{
3426 struct sky2_port *sky2 = netdev_priv(dev);
3427
16ad91e1
SH		 3428 switch (sky2->flow_mode) {
3429 case FC_NONE:
3430 ecmd->tx_pause = ecmd->rx_pause = 0;
3431 break;
3432 case FC_TX:
3433 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3434 break;
3435 case FC_RX:
3436 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3437 break;
3438 case FC_BOTH:
3439 ecmd->tx_pause = ecmd->rx_pause = 1;
3440 }
3441
cd28ab6a
SH		 3442 ecmd->autoneg = sky2->autoneg;
3443}
3444
3445static int sky2_set_pauseparam(struct net_device *dev,
3446 struct ethtool_pauseparam *ecmd)
3447{
3448 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3449
3450 sky2->autoneg = ecmd->autoneg;
16ad91e1 3451 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3452
16ad91e1
SH		 3453 if (netif_running(dev))
3454 sky2_phy_reinit(sky2);
cd28ab6a 3455
2eaba1a2 3456 return 0;
cd28ab6a
SH		 3457}
3458
fb17358f
SH		 3459static int sky2_get_coalesce(struct net_device *dev,
3460 struct ethtool_coalesce *ecmd)
3461{
3462 struct sky2_port *sky2 = netdev_priv(dev);
3463 struct sky2_hw *hw = sky2->hw;
3464
3465 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3466 ecmd->tx_coalesce_usecs = 0;
3467 else {
3468 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3469 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3470 }
3471 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3472
3473 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3474 ecmd->rx_coalesce_usecs = 0;
3475 else {
3476 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3477 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3478 }
3479 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3480
3481 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3482 ecmd->rx_coalesce_usecs_irq = 0;
3483 else {
3484 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3485 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3486 }
3487
3488 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3489
3490 return 0;
3491}
3492
3493/* Note: this affect both ports */
3494static int sky2_set_coalesce(struct net_device *dev,
3495 struct ethtool_coalesce *ecmd)
3496{
3497 struct sky2_port *sky2 = netdev_priv(dev);
3498 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3499 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3500
77b3d6a2
SH		 3501 if (ecmd->tx_coalesce_usecs > tmax ||
3502 ecmd->rx_coalesce_usecs > tmax ||
3503 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3504 return -EINVAL;
3505
ff81fbbe 3506 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3507 return -EINVAL;
ff81fbbe 3508 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3509 return -EINVAL;
ff81fbbe 3510 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3511 return -EINVAL;
3512
3513 if (ecmd->tx_coalesce_usecs == 0)
3514 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3515 else {
3516 sky2_write32(hw, STAT_TX_TIMER_INI,
3517 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3518 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3519 }
3520 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3521
3522 if (ecmd->rx_coalesce_usecs == 0)
3523 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3524 else {
3525 sky2_write32(hw, STAT_LEV_TIMER_INI,
3526 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3527 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3528 }
3529 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3530
3531 if (ecmd->rx_coalesce_usecs_irq == 0)
3532 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3533 else {
d28d4870 3534 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3535 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3536 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3537 }
3538 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3539 return 0;
3540}
3541
793b883e
SH		 3542static void sky2_get_ringparam(struct net_device *dev,
3543 struct ethtool_ringparam *ering)
3544{
3545 struct sky2_port *sky2 = netdev_priv(dev);
3546
3547 ering->rx_max_pending = RX_MAX_PENDING;
3548 ering->rx_mini_max_pending = 0;
3549 ering->rx_jumbo_max_pending = 0;
3550 ering->tx_max_pending = TX_RING_SIZE - 1;
3551
3552 ering->rx_pending = sky2->rx_pending;
3553 ering->rx_mini_pending = 0;
3554 ering->rx_jumbo_pending = 0;
3555 ering->tx_pending = sky2->tx_pending;
3556}
3557
3558static int sky2_set_ringparam(struct net_device *dev,
3559 struct ethtool_ringparam *ering)
3560{
3561 struct sky2_port *sky2 = netdev_priv(dev);
3562 int err = 0;
3563
3564 if (ering->rx_pending > RX_MAX_PENDING ||
3565 ering->rx_pending < 8 ||
3566 ering->tx_pending < MAX_SKB_TX_LE ||
3567 ering->tx_pending > TX_RING_SIZE - 1)
3568 return -EINVAL;
3569
3570 if (netif_running(dev))
3571 sky2_down(dev);
3572
3573 sky2->rx_pending = ering->rx_pending;
3574 sky2->tx_pending = ering->tx_pending;
3575
1b537565 3576 if (netif_running(dev)) {
793b883e 3577 err = sky2_up(dev);
1b537565
SH		 3578 if (err)
3579 dev_close(dev);
3580 }
793b883e
SH		 3581
3582 return err;
3583}
3584
793b883e
SH		 3585static int sky2_get_regs_len(struct net_device *dev)
3586{
6e4cbb34 3587 return 0x4000;
793b883e
SH		 3588}
3589
3590/*
3591 * Returns copy of control register region
3ead5db7 3592 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3593 */
3594static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3595 void *p)
3596{
3597 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3598 const void __iomem *io = sky2->hw->regs;
295b54c4 3599 unsigned int b;
793b883e
SH		 3600
3601 regs->version = 1;
793b883e 3602
295b54c4
SH		 3603 for (b = 0; b < 128; b++) {
3604 /* This complicated switch statement is to make sure and
3605 * only access regions that are unreserved.
3606 * Some blocks are only valid on dual port cards.
3607 * and block 3 has some special diagnostic registers that
3608 * are poison.
3609 */
3610 switch (b) {
3611 case 3:
3612 /* skip diagnostic ram region */
3613 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3614 break;
3ead5db7 3615
295b54c4
SH		 3616 /* dual port cards only */
3617 case 5: /* Tx Arbiter 2 */
3618 case 9: /* RX2 */
3619 case 14 ... 15: /* TX2 */
3620 case 17: case 19: /* Ram Buffer 2 */
3621 case 22 ... 23: /* Tx Ram Buffer 2 */
3622 case 25: /* Rx MAC Fifo 1 */
3623 case 27: /* Tx MAC Fifo 2 */
3624 case 31: /* GPHY 2 */
3625 case 40 ... 47: /* Pattern Ram 2 */
3626 case 52: case 54: /* TCP Segmentation 2 */
3627 case 112 ... 116: /* GMAC 2 */
3628 if (sky2->hw->ports == 1)
3629 goto reserved;
3630 /* fall through */
3631 case 0: /* Control */
3632 case 2: /* Mac address */
3633 case 4: /* Tx Arbiter 1 */
3634 case 7: /* PCI express reg */
3635 case 8: /* RX1 */
3636 case 12 ... 13: /* TX1 */
3637 case 16: case 18:/* Rx Ram Buffer 1 */
3638 case 20 ... 21: /* Tx Ram Buffer 1 */
3639 case 24: /* Rx MAC Fifo 1 */
3640 case 26: /* Tx MAC Fifo 1 */
3641 case 28 ... 29: /* Descriptor and status unit */
3642 case 30: /* GPHY 1*/
3643 case 32 ... 39: /* Pattern Ram 1 */
3644 case 48: case 50: /* TCP Segmentation 1 */
3645 case 56 ... 60: /* PCI space */
3646 case 80 ... 84: /* GMAC 1 */
3647 memcpy_fromio(p, io, 128);
3648 break;
3649 default:
3650reserved:
3651 memset(p, 0, 128);
3652 }
3ead5db7 3653
295b54c4
SH		 3654 p += 128;
3655 io += 128;
3656 }
793b883e 3657}
cd28ab6a 3658
b628ed98
SH		 3659/* In order to do Jumbo packets on these chips, need to turn off the
3660 * transmit store/forward. Therefore checksum offload won't work.
3661 */
3662static int no_tx_offload(struct net_device *dev)
3663{
3664 const struct sky2_port *sky2 = netdev_priv(dev);
3665 const struct sky2_hw *hw = sky2->hw;
3666
69161611 3667 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3668}
3669
3670static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3671{
3672 if (data && no_tx_offload(dev))
3673 return -EINVAL;
3674
3675 return ethtool_op_set_tx_csum(dev, data);
3676}
3677
3678
3679static int sky2_set_tso(struct net_device *dev, u32 data)
3680{
3681 if (data && no_tx_offload(dev))
3682 return -EINVAL;
3683
3684 return ethtool_op_set_tso(dev, data);
3685}
3686
f4331a6d
SH		 3687static int sky2_get_eeprom_len(struct net_device *dev)
3688{
3689 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3690 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3691 u16 reg2;
3692
b32f40c4 3693 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3694 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3695}
3696
b32f40c4 3697static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3698{
167f53d0 3699 u32 val;
f4331a6d 3700
b32f40c4 3701 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3702
3703 do {
b32f40c4 3704 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3705 } while (!(offset & PCI_VPD_ADDR_F));
3706
b32f40c4 3707 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3708 return val;
f4331a6d
SH		 3709}
3710
b32f40c4 3711static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3712{
b32f40c4
SH		 3713 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3714 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3715 do {
b32f40c4 3716 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3717 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3718}
3719
3720static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3721 u8 *data)
3722{
3723 struct sky2_port *sky2 = netdev_priv(dev);
3724 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3725 int length = eeprom->len;
3726 u16 offset = eeprom->offset;
3727
3728 if (!cap)
3729 return -EINVAL;
3730
3731 eeprom->magic = SKY2_EEPROM_MAGIC;
3732
3733 while (length > 0) {
b32f40c4 3734 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3735 int n = min_t(int, length, sizeof(val));
3736
3737 memcpy(data, &val, n);
3738 length -= n;
3739 data += n;
3740 offset += n;
3741 }
3742 return 0;
3743}
3744
3745static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3746 u8 *data)
3747{
3748 struct sky2_port *sky2 = netdev_priv(dev);
3749 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3750 int length = eeprom->len;
3751 u16 offset = eeprom->offset;
3752
3753 if (!cap)
3754 return -EINVAL;
3755
3756 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3757 return -EINVAL;
3758
3759 while (length > 0) {
3760 u32 val;
3761 int n = min_t(int, length, sizeof(val));
3762
3763 if (n < sizeof(val))
b32f40c4 3764 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3765 memcpy(&val, data, n);
3766
b32f40c4 3767 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3768
3769 length -= n;
3770 data += n;
3771 offset += n;
3772 }
3773 return 0;
3774}
3775
3776
7282d491 3777static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3778 .get_settings = sky2_get_settings,
3779 .set_settings = sky2_set_settings,
3780 .get_drvinfo = sky2_get_drvinfo,
3781 .get_wol = sky2_get_wol,
3782 .set_wol = sky2_set_wol,
3783 .get_msglevel = sky2_get_msglevel,
3784 .set_msglevel = sky2_set_msglevel,
3785 .nway_reset = sky2_nway_reset,
3786 .get_regs_len = sky2_get_regs_len,
3787 .get_regs = sky2_get_regs,
3788 .get_link = ethtool_op_get_link,
3789 .get_eeprom_len = sky2_get_eeprom_len,
3790 .get_eeprom = sky2_get_eeprom,
3791 .set_eeprom = sky2_set_eeprom,
f4331a6d 3792 .set_sg = ethtool_op_set_sg,
f4331a6d 3793 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3794 .set_tso = sky2_set_tso,
3795 .get_rx_csum = sky2_get_rx_csum,
3796 .set_rx_csum = sky2_set_rx_csum,
3797 .get_strings = sky2_get_strings,
3798 .get_coalesce = sky2_get_coalesce,
3799 .set_coalesce = sky2_set_coalesce,
3800 .get_ringparam = sky2_get_ringparam,
3801 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3802 .get_pauseparam = sky2_get_pauseparam,
3803 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3804 .phys_id = sky2_phys_id,
b9f2c044 3805 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3806 .get_ethtool_stats = sky2_get_ethtool_stats,
3807};
3808
3cf26753
SH		 3809#ifdef CONFIG_SKY2_DEBUG
3810
3811static struct dentry *sky2_debug;
3812
3813static int sky2_debug_show(struct seq_file *seq, void *v)
3814{
3815 struct net_device *dev = seq->private;
3816 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3817 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3818 unsigned port = sky2->port;
3819 unsigned idx, last;
3820 int sop;
3821
3822 if (!netif_running(dev))
3823 return -ENETDOWN;
3824
3825 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3826 sky2_read32(hw, B0_ISRC),
3827 sky2_read32(hw, B0_IMSK),
3828 sky2_read32(hw, B0_Y2_SP_ICR));
3829
bea3348e 3830 napi_disable(&hw->napi);
3cf26753
SH		 3831 last = sky2_read16(hw, STAT_PUT_IDX);
3832
3833 if (hw->st_idx == last)
3834 seq_puts(seq, "Status ring (empty)\n");
3835 else {
3836 seq_puts(seq, "Status ring\n");
3837 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3838 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3839 const struct sky2_status_le *le = hw->st_le + idx;
3840 seq_printf(seq, "[%d] %#x %d %#x\n",
3841 idx, le->opcode, le->length, le->status);
3842 }
3843 seq_puts(seq, "\n");
3844 }
3845
3846 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3847 sky2->tx_cons, sky2->tx_prod,
3848 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3849 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3850
3851 /* Dump contents of tx ring */
3852 sop = 1;
3853 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3854 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3855 const struct sky2_tx_le *le = sky2->tx_le + idx;
3856 u32 a = le32_to_cpu(le->addr);
3857
3858 if (sop)
3859 seq_printf(seq, "%u:", idx);
3860 sop = 0;
3861
3862 switch(le->opcode & ~HW_OWNER) {
3863 case OP_ADDR64:
3864 seq_printf(seq, " %#x:", a);
3865 break;
3866 case OP_LRGLEN:
3867 seq_printf(seq, " mtu=%d", a);
3868 break;
3869 case OP_VLAN:
3870 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3871 break;
3872 case OP_TCPLISW:
3873 seq_printf(seq, " csum=%#x", a);
3874 break;
3875 case OP_LARGESEND:
3876 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3877 break;
3878 case OP_PACKET:
3879 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3880 break;
3881 case OP_BUFFER:
3882 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3883 break;
3884 default:
3885 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3886 a, le16_to_cpu(le->length));
3887 }
3888
3889 if (le->ctrl & EOP) {
3890 seq_putc(seq, '\n');
3891 sop = 1;
3892 }
3893 }
3894
3895 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3896 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3897 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3898 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3899
d1d08d12 3900 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 3901 napi_enable(&hw->napi);
3cf26753
SH		 3902 return 0;
3903}
3904
3905static int sky2_debug_open(struct inode *inode, struct file *file)
3906{
3907 return single_open(file, sky2_debug_show, inode->i_private);
3908}
3909
3910static const struct file_operations sky2_debug_fops = {
3911 .owner = THIS_MODULE,
3912 .open = sky2_debug_open,
3913 .read = seq_read,
3914 .llseek = seq_lseek,
3915 .release = single_release,
3916};
3917
3918/*
3919 * Use network device events to create/remove/rename
3920 * debugfs file entries
3921 */
3922static int sky2_device_event(struct notifier_block *unused,
3923 unsigned long event, void *ptr)
3924{
3925 struct net_device *dev = ptr;
5b296bc9 3926 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3927
5b296bc9
SH		 3928 if (dev->open != sky2_up || !sky2_debug)
3929 return NOTIFY_DONE;
3cf26753 3930
5b296bc9
SH		 3931 switch(event) {
3932 case NETDEV_CHANGENAME:
3933 if (sky2->debugfs) {
3934 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3935 sky2_debug, dev->name);
3936 }
3937 break;
3cf26753 3938
5b296bc9
SH		 3939 case NETDEV_GOING_DOWN:
3940 if (sky2->debugfs) {
3941 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3942 dev->name);
3943 debugfs_remove(sky2->debugfs);
3944 sky2->debugfs = NULL;
3cf26753 3945 }
5b296bc9
SH		 3946 break;
3947
3948 case NETDEV_UP:
3949 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3950 sky2_debug, dev,
3951 &sky2_debug_fops);
3952 if (IS_ERR(sky2->debugfs))
3953 sky2->debugfs = NULL;
3cf26753
SH		 3954 }
3955
3956 return NOTIFY_DONE;
3957}
3958
3959static struct notifier_block sky2_notifier = {
3960 .notifier_call = sky2_device_event,
3961};
3962
3963
3964static __init void sky2_debug_init(void)
3965{
3966 struct dentry *ent;
3967
3968 ent = debugfs_create_dir("sky2", NULL);
3969 if (!ent || IS_ERR(ent))
3970 return;
3971
3972 sky2_debug = ent;
3973 register_netdevice_notifier(&sky2_notifier);
3974}
3975
3976static __exit void sky2_debug_cleanup(void)
3977{
3978 if (sky2_debug) {
3979 unregister_netdevice_notifier(&sky2_notifier);
3980 debugfs_remove(sky2_debug);
3981 sky2_debug = NULL;
3982 }
3983}
3984
3985#else
3986#define sky2_debug_init()
3987#define sky2_debug_cleanup()
3988#endif
3989
3990
cd28ab6a
SH		 3991/* Initialize network device */
3992static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 3993 unsigned port,
be63a21c 3994 int highmem, int wol)
cd28ab6a
SH		 3995{
3996 struct sky2_port *sky2;
3997 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3998
3999 if (!dev) {
898eb71c 4000 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4001 return NULL;
4002 }
4003
cd28ab6a 4004 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4005 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 4006 dev->open = sky2_up;
4007 dev->stop = sky2_down;
ef743d33 4008 dev->do_ioctl = sky2_ioctl;
cd28ab6a 4009 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 4010 dev->set_multicast_list = sky2_set_multicast;
4011 dev->set_mac_address = sky2_set_mac_address;
4012 dev->change_mtu = sky2_change_mtu;
4013 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4014 dev->tx_timeout = sky2_tx_timeout;
4015 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 4016#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 4017 if (port == 0)
4018 dev->poll_controller = sky2_netpoll;
cd28ab6a 4019#endif
cd28ab6a
SH		 4020
4021 sky2 = netdev_priv(dev);
4022 sky2->netdev = dev;
4023 sky2->hw = hw;
4024 sky2->msg_enable = netif_msg_init(debug, default_msg);
4025
cd28ab6a
SH		 4026 /* Auto speed and flow control */
4027 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4028 sky2->flow_mode = FC_BOTH;
4029
cd28ab6a
SH		 4030 sky2->duplex = -1;
4031 sky2->speed = -1;
4032 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4033 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4034 sky2->wol = wol;
75d070c5 4035
e07b1aa8 4036 spin_lock_init(&sky2->phy_lock);
793b883e 4037 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4038 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4039
4040 hw->dev[port] = dev;
4041
4042 sky2->port = port;
4043
4a50a876 4044 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4045 if (highmem)
4046 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4047
d1f13708 4048#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4049 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4050 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4051 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4052 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4053 dev->vlan_rx_register = sky2_vlan_rx_register;
4054 }
d1f13708
SH		 4055#endif
4056
cd28ab6a 4057 /* read the mac address */
793b883e 4058 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4059 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4060
cd28ab6a
SH		 4061 return dev;
4062}
4063
28bd181a 4064static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4065{
4066 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4067 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4068
4069 if (netif_msg_probe(sky2))
0795af57
JP		 4070 printk(KERN_INFO PFX "%s: addr %s\n",
4071 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4072}
4073
fb2690a9 4074/* Handle software interrupt used during MSI test */
7d12e780 4075static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4076{
4077 struct sky2_hw *hw = dev_id;
4078 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4079
4080 if (status == 0)
4081 return IRQ_NONE;
4082
4083 if (status & Y2_IS_IRQ_SW) {
ea76e635 4084 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4085 wake_up(&hw->msi_wait);
4086 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4087 }
4088 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4089
4090 return IRQ_HANDLED;
4091}
4092
4093/* Test interrupt path by forcing a a software IRQ */
4094static int __devinit sky2_test_msi(struct sky2_hw *hw)
4095{
4096 struct pci_dev *pdev = hw->pdev;
4097 int err;
4098
bb507fe1
SH		 4099 init_waitqueue_head (&hw->msi_wait);
4100
fb2690a9
SH		 4101 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4102
b0a20ded 4103 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4104 if (err) {
b02a9258 4105 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4106 return err;
4107 }
4108
fb2690a9 4109 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4110 sky2_read8(hw, B0_CTST);
fb2690a9 4111
ea76e635 4112 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4113
ea76e635 4114 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4115 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4116 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4117 "switching to INTx mode.\n");
fb2690a9
SH		 4118
4119 err = -EOPNOTSUPP;
4120 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4121 }
4122
4123 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4124 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4125
4126 free_irq(pdev->irq, hw);
4127
4128 return err;
4129}
4130
be63a21c
SH		 4131static int __devinit pci_wake_enabled(struct pci_dev *dev)
4132{
4133 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4134 u16 value;
4135
4136 if (!pm)
4137 return 0;
4138 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4139 return 0;
4140 return value & PCI_PM_CTRL_PME_ENABLE;
4141}
4142
cd28ab6a
SH		 4143static int __devinit sky2_probe(struct pci_dev *pdev,
4144 const struct pci_device_id *ent)
4145{
7f60c64b 4146 struct net_device *dev;
cd28ab6a 4147 struct sky2_hw *hw;
be63a21c 4148 int err, using_dac = 0, wol_default;
cd28ab6a 4149
793b883e
SH		 4150 err = pci_enable_device(pdev);
4151 if (err) {
b02a9258 4152 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4153 goto err_out;
4154 }
4155
793b883e
SH		 4156 err = pci_request_regions(pdev, DRV_NAME);
4157 if (err) {
b02a9258 4158 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4159 goto err_out_disable;
cd28ab6a
SH		 4160 }
4161
4162 pci_set_master(pdev);
4163
d1f3d4dd
SH		 4164 if (sizeof(dma_addr_t) > sizeof(u32) &&
4165 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4166 using_dac = 1;
4167 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4168 if (err < 0) {
b02a9258
SH		 4169 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4170 "for consistent allocations\n");
d1f3d4dd
SH		 4171 goto err_out_free_regions;
4172 }
d1f3d4dd 4173 } else {
cd28ab6a
SH		 4174 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4175 if (err) {
b02a9258 4176 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4177 goto err_out_free_regions;
4178 }
4179 }
d1f3d4dd 4180
be63a21c
SH		 4181 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4182
cd28ab6a 4183 err = -ENOMEM;
6aad85d6 4184 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4185 if (!hw) {
b02a9258 4186 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4187 goto err_out_free_regions;
4188 }
4189
cd28ab6a 4190 hw->pdev = pdev;
cd28ab6a
SH		 4191
4192 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4193 if (!hw->regs) {
b02a9258 4194 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4195 goto err_out_free_hw;
4196 }
4197
56a645cc 4198#ifdef __BIG_ENDIAN
f65b138c
SH		 4199 /* The sk98lin vendor driver uses hardware byte swapping but
4200 * this driver uses software swapping.
4201 */
56a645cc
SH		 4202 {
4203 u32 reg;
b32f40c4 4204 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4205 reg &= ~PCI_REV_DESC;
b32f40c4 4206 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4207 }
4208#endif
4209
08c06d8a 4210 /* ring for status responses */
167f53d0 4211 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4212 if (!hw->st_le)
4213 goto err_out_iounmap;
4214
e3173832 4215 err = sky2_init(hw);
cd28ab6a 4216 if (err)
793b883e 4217 goto err_out_iounmap;
cd28ab6a 4218
b02a9258 4219 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4220 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4221 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4222 hw->chip_id, hw->chip_rev);
cd28ab6a 4223
e3173832
SH		 4224 sky2_reset(hw);
4225
be63a21c 4226 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4227 if (!dev) {
4228 err = -ENOMEM;
cd28ab6a 4229 goto err_out_free_pci;
7f60c64b 4230 }
cd28ab6a 4231
9fa1b1f3
SH		 4232 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4233 err = sky2_test_msi(hw);
4234 if (err == -EOPNOTSUPP)
4235 pci_disable_msi(pdev);
4236 else if (err)
4237 goto err_out_free_netdev;
4238 }
4239
793b883e
SH		 4240 err = register_netdev(dev);
4241 if (err) {
b02a9258 4242 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4243 goto err_out_free_netdev;
4244 }
4245
6de16237
SH		 4246 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4247
ea76e635
SH		 4248 err = request_irq(pdev->irq, sky2_intr,
4249 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4250 dev->name, hw);
9fa1b1f3 4251 if (err) {
b02a9258 4252 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4253 goto err_out_unregister;
4254 }
4255 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4256 napi_enable(&hw->napi);
9fa1b1f3 4257
cd28ab6a
SH		 4258 sky2_show_addr(dev);
4259
7f60c64b 4260 if (hw->ports > 1) {
4261 struct net_device *dev1;
4262
be63a21c 4263 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4264 if (!dev1)
4265 dev_warn(&pdev->dev, "allocation for second device failed\n");
4266 else if ((err = register_netdev(dev1))) {
4267 dev_warn(&pdev->dev,
4268 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4269 hw->dev[1] = NULL;
4270 free_netdev(dev1);
b02a9258
SH		 4271 } else
4272 sky2_show_addr(dev1);
cd28ab6a
SH		 4273 }
4274
32c2c300 4275 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4276 INIT_WORK(&hw->restart_work, sky2_restart);
4277
793b883e
SH		 4278 pci_set_drvdata(pdev, hw);
4279
cd28ab6a
SH		 4280 return 0;
4281
793b883e 4282err_out_unregister:
ea76e635 4283 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4284 pci_disable_msi(pdev);
793b883e 4285 unregister_netdev(dev);
cd28ab6a
SH		 4286err_out_free_netdev:
4287 free_netdev(dev);
cd28ab6a 4288err_out_free_pci:
793b883e 4289 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4290 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4291err_out_iounmap:
4292 iounmap(hw->regs);
4293err_out_free_hw:
4294 kfree(hw);
4295err_out_free_regions:
4296 pci_release_regions(pdev);
44a1d2e5 4297err_out_disable:
cd28ab6a 4298 pci_disable_device(pdev);
cd28ab6a 4299err_out:
549a68c3 4300 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4301 return err;
4302}
4303
4304static void __devexit sky2_remove(struct pci_dev *pdev)
4305{
793b883e 4306 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4307 int i;
cd28ab6a 4308
793b883e 4309 if (!hw)
cd28ab6a
SH		 4310 return;
4311
32c2c300 4312 del_timer_sync(&hw->watchdog_timer);
6de16237 4313 cancel_work_sync(&hw->restart_work);
d27ed387 4314
b877fe28 4315 for (i = hw->ports-1; i >= 0; --i)
6de16237 4316 unregister_netdev(hw->dev[i]);
81906791 4317
d27ed387 4318 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4319
ae306cca
SH		 4320 sky2_power_aux(hw);
4321
cd28ab6a 4322 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4323 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4324 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4325
4326 free_irq(pdev->irq, hw);
ea76e635 4327 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4328 pci_disable_msi(pdev);
793b883e 4329 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4330 pci_release_regions(pdev);
4331 pci_disable_device(pdev);
793b883e 4332
b877fe28 4333 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4334 free_netdev(hw->dev[i]);
4335
cd28ab6a
SH		 4336 iounmap(hw->regs);
4337 kfree(hw);
5afa0a9c 4338
cd28ab6a
SH		 4339 pci_set_drvdata(pdev, NULL);
4340}
4341
4342#ifdef CONFIG_PM
4343static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4344{
793b883e 4345 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4346 int i, wol = 0;
cd28ab6a 4347
549a68c3
SH		 4348 if (!hw)
4349 return 0;
4350
063a0b38
SH		 4351 del_timer_sync(&hw->watchdog_timer);
4352 cancel_work_sync(&hw->restart_work);
4353
f05267e7 4354 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4355 struct net_device *dev = hw->dev[i];
e3173832 4356 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4357
063a0b38 4358 netif_device_detach(dev);
e3173832 4359 if (netif_running(dev))
5afa0a9c 4360 sky2_down(dev);
e3173832
SH		 4361
4362 if (sky2->wol)
4363 sky2_wol_init(sky2);
4364
4365 wol |= sky2->wol;
cd28ab6a
SH		 4366 }
4367
8ab8fca2 4368 sky2_write32(hw, B0_IMSK, 0);
6de16237 4369 napi_disable(&hw->napi);
ae306cca 4370 sky2_power_aux(hw);
e3173832 4371
d374c1c1 4372 pci_save_state(pdev);
e3173832 4373 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4374 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4375
2ccc99b7 4376 return 0;
cd28ab6a
SH		 4377}
4378
4379static int sky2_resume(struct pci_dev *pdev)
4380{
793b883e 4381 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4382 int i, err;
cd28ab6a 4383
549a68c3
SH		 4384 if (!hw)
4385 return 0;
4386
ae306cca
SH		 4387 err = pci_set_power_state(pdev, PCI_D0);
4388 if (err)
4389 goto out;
4390
4391 err = pci_restore_state(pdev);
4392 if (err)
4393 goto out;
4394
cd28ab6a 4395 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4396
4397 /* Re-enable all clocks */
05745c4a
SH		 4398 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4399 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4400 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4401 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4402
e3173832 4403 sky2_reset(hw);
8ab8fca2 4404 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4405 napi_enable(&hw->napi);
8ab8fca2 4406
f05267e7 4407 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4408 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4409
4410 netif_device_attach(dev);
6a5706b9 4411 if (netif_running(dev)) {
08c06d8a
SH		 4412 err = sky2_up(dev);
4413 if (err) {
4414 printk(KERN_ERR PFX "%s: could not up: %d\n",
4415 dev->name, err);
4416 dev_close(dev);
eb35cf60 4417 goto out;
5afa0a9c 4418 }
cd28ab6a
SH		 4419 }
4420 }
eb35cf60 4421
ae306cca 4422 return 0;
08c06d8a 4423out:
b02a9258 4424 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4425 pci_disable_device(pdev);
08c06d8a 4426 return err;
cd28ab6a
SH		 4427}
4428#endif
4429
e3173832
SH		 4430static void sky2_shutdown(struct pci_dev *pdev)
4431{
4432 struct sky2_hw *hw = pci_get_drvdata(pdev);
4433 int i, wol = 0;
4434
549a68c3
SH		 4435 if (!hw)
4436 return;
4437
5c0d6b34 4438 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4439
4440 for (i = 0; i < hw->ports; i++) {
4441 struct net_device *dev = hw->dev[i];
4442 struct sky2_port *sky2 = netdev_priv(dev);
4443
4444 if (sky2->wol) {
4445 wol = 1;
4446 sky2_wol_init(sky2);
4447 }
4448 }
4449
4450 if (wol)
4451 sky2_power_aux(hw);
4452
4453 pci_enable_wake(pdev, PCI_D3hot, wol);
4454 pci_enable_wake(pdev, PCI_D3cold, wol);
4455
4456 pci_disable_device(pdev);
4457 pci_set_power_state(pdev, PCI_D3hot);
4458
4459}
4460
cd28ab6a 4461static struct pci_driver sky2_driver = {
793b883e
SH		 4462 .name = DRV_NAME,
4463 .id_table = sky2_id_table,
4464 .probe = sky2_probe,
4465 .remove = __devexit_p(sky2_remove),
cd28ab6a 4466#ifdef CONFIG_PM
793b883e
SH		 4467 .suspend = sky2_suspend,
4468 .resume = sky2_resume,
cd28ab6a 4469#endif
e3173832 4470 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4471};
4472
4473static int __init sky2_init_module(void)
4474{
3cf26753 4475 sky2_debug_init();
50241c4c 4476 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4477}
4478
4479static void __exit sky2_cleanup_module(void)
4480{
4481 pci_unregister_driver(&sky2_driver);
3cf26753 4482 sky2_debug_cleanup();
cd28ab6a
SH		 4483}
4484
4485module_init(sky2_init_module);
4486module_exit(sky2_cleanup_module);
4487
4488MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4489MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4490MODULE_LICENSE("GPL");
5f4f9dc1 4491MODULE_VERSION(DRV_VERSION);
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