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sky2: more receive shutdown
[mirror_ubuntu-jammy-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
743d32ad 53#define DRV_VERSION "1.22"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 66
67#define TX_RING_SIZE 512
68#define TX_DEF_PENDING (TX_RING_SIZE - 1)
69#define TX_MIN_PENDING 64
b19666d9 70#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH		 78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33
SH		 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH		 259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH		 294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH		 319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
ea76e635
SH		 324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH		 337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH		 358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 366 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH		 373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH		 380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH		 386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH		 402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a
SH		 410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
16ad91e1 426 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 432
16ad91e1 433 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 434 }
cd28ab6a
SH		 435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
2eaba1a2
SH		 442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
2eaba1a2 448 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
2eaba1a2 452 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 453 break;
454 }
455
2eaba1a2
SH		 456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
2eaba1a2 461
2eaba1a2 462
16ad91e1 463 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 464
465 /* Forward pause packets to GMAC? */
16ad91e1 466 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 470 }
471
2eaba1a2
SH		 472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
05745c4a 474 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
05745c4a
SH		 498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
cd28ab6a 515 case CHIP_ID_YUKON_XL:
793b883e 516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 536
537 /* restore page register */
793b883e 538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 539 break;
93745494 540
ed6d32c7 541 case CHIP_ID_YUKON_EC_U:
93745494 542 case CHIP_ID_YUKON_EX:
ed4d4161 543 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
cd28ab6a
SH		 562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 566
cd28ab6a 567 /* turn off the Rx LED (LED_RX) */
a84d0a3d 568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 569 }
570
0ce8b98d 571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 572 /* apply fixes in PHY AFE */
ed6d32c7
SH		 573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
977bdf06 575 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 578
0ce8b98d
SH		 579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
977bdf06
SH		 584
585 /* set page register to 0 */
9467a8fc 586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 594 /* no effect on Yukon-XL */
977bdf06 595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 596
977bdf06
SH		 597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 600 }
cd28ab6a 601
977bdf06
SH		 602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
2eaba1a2 606
d571b694 607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612}
613
b96936da
SH		 614static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 618{
619 u32 reg1;
d3bcfbeb 620
82637e80 621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 623 reg1 &= ~phy_power[port];
d3bcfbeb 624
b96936da 625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 626 reg1 |= coma_mode[port];
627
b32f40c4 628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 636}
167f53d0 637
b96936da
SH		 638static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639{
640 u32 reg1;
db99b988
SH		 641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 670
e484d5f5 671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
b96936da
SH		 683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 689}
690
1b537565
SH		 691/* Force a renegotiation */
692static void sky2_phy_reinit(struct sky2_port *sky2)
693{
e07b1aa8 694 spin_lock_bh(&sky2->phy_lock);
1b537565 695 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 696 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 697}
698
e3173832
SH		 699/* Put device in state to listen for Wake On Lan */
700static void sky2_wol_init(struct sky2_port *sky2)
701{
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
b96936da
SH		 723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
b32f40c4 758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 759 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765}
766
69161611
SH		 767static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768{
05745c4a
SH		 769 struct net_device *dev = hw->dev[port];
770
ed4d4161
SH		 771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
05745c4a 777
ed4d4161
SH		 778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 781
ed4d4161
SH		 782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 792
ed4d4161
SH		 793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
69161611
SH		 798 }
799}
800
cd28ab6a
SH		 801static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802{
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
25cccecc 805 u32 rx_reg;
cd28ab6a
SH		 806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
f350339c
SH		 809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
793b883e 814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
793b883e 826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 827
2eaba1a2
SH		 828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
e07b1aa8 831 spin_lock_bh(&sky2->phy_lock);
b96936da 832 sky2_phy_power_up(hw, port);
cd28ab6a 833 sky2_phy_init(hw, port);
e07b1aa8 834 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
43f2f104
SH		 840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
cd28ab6a
SH		 842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
793b883e 849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 864
6b1a3aef 865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
cd28ab6a
SH		 870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
793b883e
SH		 873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
cd28ab6a
SH		 877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 886 rx_reg |= GMF_RX_OVER_ON;
69161611 887
25cccecc 888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 889
798fdd07
SH		 890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
cd28ab6a 897
8df9a876 898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 909
e0c28116 910 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 914
69161611 915 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 916 }
917
e970d1f8
SH		 918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
cd28ab6a
SH		 925}
926
67712901
SH		 927/* Assign Ram Buffer allocation to queue */
928static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 929{
67712901
SH		 930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
793b883e 936
cd28ab6a
SH		 937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 944 u32 tp = space - space/4;
793b883e 945
1c28f6ba
SH		 946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 952
1c28f6ba
SH		 953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 965}
966
cd28ab6a 967/* Setup Bus Memory Interface */
af4ed7e6 968static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 969{
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 974}
975
cd28ab6a
SH		 976/* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
8cc048e3 979static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 980 u64 addr, u32 last)
981{
cd28ab6a
SH		 982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 990}
991
793b883e
SH		 992static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993{
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
cb5d9547 996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 997 le->ctrl = 0;
793b883e
SH		 998 return le;
999}
cd28ab6a 1000
88f5f0ca
SH		 1001static void tx_init(struct sky2_port *sky2)
1002{
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1012}
1013
291ea614
SH		 1014static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016{
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018}
1019
290d4de5
SH		 1020/* Update chip's next pointer */
1021static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1022{
50432cb5 1023 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1024 wmb();
50432cb5
SH		 1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
cd28ab6a
SH		 1029}
1030
793b883e 1031
cd28ab6a
SH		 1032static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033{
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1036 le->ctrl = 0;
cd28ab6a
SH		 1037 return le;
1038}
1039
14d0263f
SH		 1040/* Build description to hardware for one receive segment */
1041static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1043{
1044 struct sky2_rx_le *le;
1045
86c6887e 1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1047 le = sky2_next_rx(sky2);
86c6887e 1048 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
793b883e 1051
cd28ab6a 1052 le = sky2_next_rx(sky2);
734d1868
SH		 1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
14d0263f 1055 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1056}
1057
14d0263f
SH		 1058/* Build description to hardware for one possibly fragmented skb */
1059static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061{
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068}
1069
1070
454e6cb6 1071static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1072 unsigned size)
1073{
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
14d0263f
SH		 1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
454e6cb6 1089 return 0;
14d0263f
SH		 1090}
1091
1092static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093{
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104}
793b883e 1105
cd28ab6a
SH		 1106/* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
793b883e 1110static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1111{
ea76e635 1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1113
ea76e635
SH		 1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1117
ea76e635
SH		 1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1121}
1122
6b1a3aef
SH		 1123/*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133static void sky2_rx_stop(struct sky2_port *sky2)
1134{
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
c0bad0f2
SH		 1154
1155 /* Reset the RAM Buffer receive queue */
1156 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);
1157
1158 /* Reset Rx MAC FIFO */
1159 sky2_write8(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), GMF_RST_SET);
1160
1161 sky2_read8(hw, B0_CTST);
6b1a3aef 1162}
793b883e 1163
d571b694 1164/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1165static void sky2_rx_clean(struct sky2_port *sky2)
1166{
1167 unsigned i;
1168
1169 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1170 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1171 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1172
1173 if (re->skb) {
14d0263f 1174 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1175 kfree_skb(re->skb);
1176 re->skb = NULL;
1177 }
1178 }
1179}
1180
ef743d33
SH		 1181/* Basic MII support */
1182static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1183{
1184 struct mii_ioctl_data *data = if_mii(ifr);
1185 struct sky2_port *sky2 = netdev_priv(dev);
1186 struct sky2_hw *hw = sky2->hw;
1187 int err = -EOPNOTSUPP;
1188
1189 if (!netif_running(dev))
1190 return -ENODEV; /* Phy still in reset */
1191
d89e1343 1192 switch (cmd) {
ef743d33
SH		 1193 case SIOCGMIIPHY:
1194 data->phy_id = PHY_ADDR_MARV;
1195
1196 /* fallthru */
1197 case SIOCGMIIREG: {
1198 u16 val = 0;
91c86df5 1199
e07b1aa8 1200 spin_lock_bh(&sky2->phy_lock);
ef743d33 1201 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1202 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1203
ef743d33
SH		 1204 data->val_out = val;
1205 break;
1206 }
1207
1208 case SIOCSMIIREG:
1209 if (!capable(CAP_NET_ADMIN))
1210 return -EPERM;
1211
e07b1aa8 1212 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1213 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1214 data->val_in);
e07b1aa8 1215 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1216 break;
1217 }
1218 return err;
1219}
1220
d1f13708 1221#ifdef SKY2_VLAN_TAG_USED
d494eacd 1222static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1223{
d494eacd 1224 if (onoff) {
3d4e66f5
SH		 1225 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1226 RX_VLAN_STRIP_ON);
1227 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1228 TX_VLAN_TAG_ON);
1229 } else {
1230 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1231 RX_VLAN_STRIP_OFF);
1232 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1233 TX_VLAN_TAG_OFF);
1234 }
d494eacd
SH		 1235}
1236
1237static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1238{
1239 struct sky2_port *sky2 = netdev_priv(dev);
1240 struct sky2_hw *hw = sky2->hw;
1241 u16 port = sky2->port;
1242
1243 netif_tx_lock_bh(dev);
1244 napi_disable(&hw->napi);
1245
1246 sky2->vlgrp = grp;
1247 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1248
d1d08d12 1249 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1250 napi_enable(&hw->napi);
2bb8c262 1251 netif_tx_unlock_bh(dev);
d1f13708
SH		 1252}
1253#endif
1254
82788c7a 1255/*
14d0263f
SH		 1256 * Allocate an skb for receiving. If the MTU is large enough
1257 * make the skb non-linear with a fragment list of pages.
82788c7a 1258 */
14d0263f 1259static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1260{
1261 struct sk_buff *skb;
14d0263f 1262 int i;
82788c7a 1263
39dbd958 1264 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1265 unsigned char *start;
1266 /*
1267 * Workaround for a bug in FIFO that cause hang
1268 * if the FIFO if the receive buffer is not 64 byte aligned.
1269 * The buffer returned from netdev_alloc_skb is
1270 * aligned except if slab debugging is enabled.
1271 */
1272 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1273 if (!skb)
1274 goto nomem;
1275 start = PTR_ALIGN(skb->data, 8);
1276 skb_reserve(skb, start - skb->data);
1277 } else {
1278 skb = netdev_alloc_skb(sky2->netdev,
1279 sky2->rx_data_size + NET_IP_ALIGN);
1280 if (!skb)
1281 goto nomem;
1282 skb_reserve(skb, NET_IP_ALIGN);
1283 }
14d0263f
SH		 1284
1285 for (i = 0; i < sky2->rx_nfrags; i++) {
1286 struct page *page = alloc_page(GFP_ATOMIC);
1287
1288 if (!page)
1289 goto free_partial;
1290 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1291 }
1292
1293 return skb;
14d0263f
SH		 1294free_partial:
1295 kfree_skb(skb);
1296nomem:
1297 return NULL;
82788c7a
SH		 1298}
1299
55c9dd35
SH		 1300static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1301{
1302 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1303}
1304
cd28ab6a
SH		 1305/*
1306 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1307 * Normal case this ends up creating one list element for skb
1308 * in the receive ring. Worst case if using large MTU and each
1309 * allocation falls on a different 64 bit region, that results
1310 * in 6 list elements per ring entry.
1311 * One element is used for checksum enable/disable, and one
1312 * extra to avoid wrap.
cd28ab6a 1313 */
6b1a3aef 1314static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1315{
6b1a3aef 1316 struct sky2_hw *hw = sky2->hw;
14d0263f 1317 struct rx_ring_info *re;
6b1a3aef 1318 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1319 unsigned i, size, thresh;
cd28ab6a 1320
6b1a3aef 1321 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1322 sky2_qset(hw, rxq);
977bdf06 1323
c3905bc4
SH		 1324 /* On PCI express lowering the watermark gives better performance */
1325 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1326 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1327
1328 /* These chips have no ram buffer?
1329 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1330 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1331 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1332 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1333 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1334
6b1a3aef
SH		 1335 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1336
ea76e635
SH		 1337 if (!(hw->flags & SKY2_HW_NEW_LE))
1338 rx_set_checksum(sky2);
14d0263f
SH		 1339
1340 /* Space needed for frame data + headers rounded up */
f957da2a 1341 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1342
1343 /* Stopping point for hardware truncation */
1344 thresh = (size - 8) / sizeof(u32);
1345
5f06eba4 1346 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1347 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1348
5f06eba4
SH		 1349 /* Compute residue after pages */
1350 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1351
5f06eba4
SH		 1352 /* Optimize to handle small packets and headers */
1353 if (size < copybreak)
1354 size = copybreak;
1355 if (size < ETH_HLEN)
1356 size = ETH_HLEN;
14d0263f 1357
14d0263f
SH		 1358 sky2->rx_data_size = size;
1359
1360 /* Fill Rx ring */
793b883e 1361 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1362 re = sky2->rx_ring + i;
cd28ab6a 1363
14d0263f 1364 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1365 if (!re->skb)
1366 goto nomem;
1367
454e6cb6
SH		 1368 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1369 dev_kfree_skb(re->skb);
1370 re->skb = NULL;
1371 goto nomem;
1372 }
1373
14d0263f 1374 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1375 }
1376
a1433ac4
SH		 1377 /*
1378 * The receiver hangs if it receives frames larger than the
1379 * packet buffer. As a workaround, truncate oversize frames, but
1380 * the register is limited to 9 bits, so if you do frames > 2052
1381 * you better get the MTU right!
1382 */
a1433ac4
SH		 1383 if (thresh > 0x1ff)
1384 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1385 else {
1386 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1387 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1388 }
1389
6b1a3aef 1390 /* Tell chip about available buffers */
55c9dd35 1391 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1392 return 0;
1393nomem:
1394 sky2_rx_clean(sky2);
1395 return -ENOMEM;
1396}
1397
1398/* Bring up network interface. */
1399static int sky2_up(struct net_device *dev)
1400{
1401 struct sky2_port *sky2 = netdev_priv(dev);
1402 struct sky2_hw *hw = sky2->hw;
1403 unsigned port = sky2->port;
e0c28116 1404 u32 imask, ramsize;
ee7abb04 1405 int cap, err = -ENOMEM;
843a46f4 1406 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1407
ee7abb04
SH		 1408 /*
1409 * On dual port PCI-X card, there is an problem where status
1410 * can be received out of order due to split transactions
843a46f4 1411 */
ee7abb04
SH		 1412 if (otherdev && netif_running(otherdev) &&
1413 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1414 u16 cmd;
1415
b32f40c4 1416 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1417 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1418 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1419
ee7abb04 1420 }
843a46f4 1421
55d7b4e6
SH		 1422 netif_carrier_off(dev);
1423
cd28ab6a
SH		 1424 /* must be power of 2 */
1425 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1426 TX_RING_SIZE *
1427 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1428 &sky2->tx_le_map);
1429 if (!sky2->tx_le)
1430 goto err_out;
1431
6cdbbdf3 1432 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1433 GFP_KERNEL);
1434 if (!sky2->tx_ring)
1435 goto err_out;
88f5f0ca
SH		 1436
1437 tx_init(sky2);
cd28ab6a
SH		 1438
1439 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1440 &sky2->rx_le_map);
1441 if (!sky2->rx_le)
1442 goto err_out;
1443 memset(sky2->rx_le, 0, RX_LE_BYTES);
1444
291ea614 1445 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1446 GFP_KERNEL);
1447 if (!sky2->rx_ring)
1448 goto err_out;
1449
1450 sky2_mac_init(hw, port);
1451
e0c28116
SH		 1452 /* Register is number of 4K blocks on internal RAM buffer. */
1453 ramsize = sky2_read8(hw, B2_E_0) * 4;
1454 if (ramsize > 0) {
67712901 1455 u32 rxspace;
cd28ab6a 1456
39dbd958 1457 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1458 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1459 if (ramsize < 16)
1460 rxspace = ramsize / 2;
1461 else
1462 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1463
67712901
SH		 1464 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1465 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1466
1467 /* Make sure SyncQ is disabled */
1468 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1469 RB_RST_SET);
1470 }
793b883e 1471
af4ed7e6 1472 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1473
69161611
SH		 1474 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1475 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1476 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1477
977bdf06 1478 /* Set almost empty threshold */
c2716fb4
SH		 1479 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1480 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1481 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1482
6b1a3aef
SH		 1483 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1484 TX_RING_SIZE - 1);
cd28ab6a 1485
d494eacd
SH		 1486#ifdef SKY2_VLAN_TAG_USED
1487 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1488#endif
1489
6b1a3aef 1490 err = sky2_rx_start(sky2);
6de16237 1491 if (err)
cd28ab6a
SH		 1492 goto err_out;
1493
cd28ab6a 1494 /* Enable interrupts from phy/mac for port */
e07b1aa8 1495 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1496 imask |= portirq_msk[port];
e07b1aa8
SH		 1497 sky2_write32(hw, B0_IMSK, imask);
1498
a7bffe72 1499 sky2_set_multicast(dev);
a11da890
AD		 1500
1501 if (netif_msg_ifup(sky2))
1502 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
cd28ab6a
SH		 1503 return 0;
1504
1505err_out:
1b537565 1506 if (sky2->rx_le) {
cd28ab6a
SH		 1507 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1508 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1509 sky2->rx_le = NULL;
1510 }
1511 if (sky2->tx_le) {
cd28ab6a
SH		 1512 pci_free_consistent(hw->pdev,
1513 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1514 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1515 sky2->tx_le = NULL;
1516 }
1517 kfree(sky2->tx_ring);
1518 kfree(sky2->rx_ring);
cd28ab6a 1519
1b537565
SH		 1520 sky2->tx_ring = NULL;
1521 sky2->rx_ring = NULL;
cd28ab6a
SH		 1522 return err;
1523}
1524
793b883e
SH		 1525/* Modular subtraction in ring */
1526static inline int tx_dist(unsigned tail, unsigned head)
1527{
cb5d9547 1528 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1529}
cd28ab6a 1530
793b883e
SH		 1531/* Number of list elements available for next tx */
1532static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1533{
793b883e 1534 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1535}
1536
793b883e 1537/* Estimate of number of transmit list elements required */
28bd181a 1538static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1539{
793b883e
SH		 1540 unsigned count;
1541
1542 count = sizeof(dma_addr_t) / sizeof(u32);
1543 count += skb_shinfo(skb)->nr_frags * count;
1544
89114afd 1545 if (skb_is_gso(skb))
793b883e
SH		 1546 ++count;
1547
84fa7933 1548 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1549 ++count;
1550
1551 return count;
cd28ab6a
SH		 1552}
1553
793b883e
SH		 1554/*
1555 * Put one packet in ring for transmit.
1556 * A single packet can generate multiple list elements, and
1557 * the number of ring elements will probably be less than the number
1558 * of list elements used.
1559 */
cd28ab6a
SH		 1560static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1561{
1562 struct sky2_port *sky2 = netdev_priv(dev);
1563 struct sky2_hw *hw = sky2->hw;
d1f13708 1564 struct sky2_tx_le *le = NULL;
6cdbbdf3 1565 struct tx_ring_info *re;
454e6cb6 1566 unsigned i, len, first_slot;
cd28ab6a 1567 dma_addr_t mapping;
cd28ab6a
SH		 1568 u16 mss;
1569 u8 ctrl;
1570
2bb8c262
SH		 1571 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1572 return NETDEV_TX_BUSY;
cd28ab6a 1573
cd28ab6a
SH		 1574 len = skb_headlen(skb);
1575 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1576
454e6cb6
SH		 1577 if (pci_dma_mapping_error(hw->pdev, mapping))
1578 goto mapping_error;
1579
1580 first_slot = sky2->tx_prod;
1581 if (unlikely(netif_msg_tx_queued(sky2)))
1582 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1583 dev->name, first_slot, skb->len);
1584
86c6887e
SH		 1585 /* Send high bits if needed */
1586 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1587 le = get_tx_le(sky2);
86c6887e 1588 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1589 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1590 }
cd28ab6a
SH		 1591
1592 /* Check for TCP Segmentation Offload */
7967168c 1593 mss = skb_shinfo(skb)->gso_size;
793b883e 1594 if (mss != 0) {
ea76e635
SH		 1595
1596 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1597 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1598
1599 if (mss != sky2->tx_last_mss) {
1600 le = get_tx_le(sky2);
1601 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1602
1603 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1604 le->opcode = OP_MSS | HW_OWNER;
1605 else
1606 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1607 sky2->tx_last_mss = mss;
1608 }
cd28ab6a
SH		 1609 }
1610
cd28ab6a 1611 ctrl = 0;
d1f13708
SH		 1612#ifdef SKY2_VLAN_TAG_USED
1613 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1614 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1615 if (!le) {
1616 le = get_tx_le(sky2);
f65b138c 1617 le->addr = 0;
d1f13708 1618 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1619 } else
1620 le->opcode |= OP_VLAN;
1621 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1622 ctrl |= INS_VLAN;
1623 }
1624#endif
1625
1626 /* Handle TCP checksum offload */
84fa7933 1627 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1628 /* On Yukon EX (some versions) encoding change. */
ea76e635 1629 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1630 ctrl |= CALSUM; /* auto checksum */
1631 else {
1632 const unsigned offset = skb_transport_offset(skb);
1633 u32 tcpsum;
1634
1635 tcpsum = offset << 16; /* sum start */
1636 tcpsum |= offset + skb->csum_offset; /* sum write */
1637
1638 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1639 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1640 ctrl |= UDPTCP;
1641
1642 if (tcpsum != sky2->tx_tcpsum) {
1643 sky2->tx_tcpsum = tcpsum;
1644
1645 le = get_tx_le(sky2);
1646 le->addr = cpu_to_le32(tcpsum);
1647 le->length = 0; /* initial checksum value */
1648 le->ctrl = 1; /* one packet */
1649 le->opcode = OP_TCPLISW | HW_OWNER;
1650 }
1d179332 1651 }
cd28ab6a
SH		 1652 }
1653
1654 le = get_tx_le(sky2);
f65b138c 1655 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1656 le->length = cpu_to_le16(len);
1657 le->ctrl = ctrl;
793b883e 1658 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1659
291ea614 1660 re = tx_le_re(sky2, le);
cd28ab6a 1661 re->skb = skb;
6cdbbdf3 1662 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1663 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1664
1665 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1666 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1667
1668 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1669 frag->size, PCI_DMA_TODEVICE);
86c6887e 1670
454e6cb6
SH		 1671 if (pci_dma_mapping_error(hw->pdev, mapping))
1672 goto mapping_unwind;
1673
86c6887e 1674 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1675 le = get_tx_le(sky2);
86c6887e 1676 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1677 le->ctrl = 0;
1678 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1679 }
1680
1681 le = get_tx_le(sky2);
f65b138c 1682 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1683 le->length = cpu_to_le16(frag->size);
1684 le->ctrl = ctrl;
793b883e 1685 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1686
291ea614
SH		 1687 re = tx_le_re(sky2, le);
1688 re->skb = skb;
1689 pci_unmap_addr_set(re, mapaddr, mapping);
1690 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1691 }
6cdbbdf3 1692
cd28ab6a
SH		 1693 le->ctrl |= EOP;
1694
97bda706
SH		 1695 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1696 netif_stop_queue(dev);
b19666d9 1697
290d4de5 1698 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1699
cd28ab6a 1700 return NETDEV_TX_OK;
454e6cb6
SH		 1701
1702mapping_unwind:
1703 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1704 le = sky2->tx_le + i;
1705 re = sky2->tx_ring + i;
1706
1707 switch(le->opcode & ~HW_OWNER) {
1708 case OP_LARGESEND:
1709 case OP_PACKET:
1710 pci_unmap_single(hw->pdev,
1711 pci_unmap_addr(re, mapaddr),
1712 pci_unmap_len(re, maplen),
1713 PCI_DMA_TODEVICE);
1714 break;
1715 case OP_BUFFER:
1716 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1717 pci_unmap_len(re, maplen),
1718 PCI_DMA_TODEVICE);
1719 break;
1720 }
1721 }
1722
1723 sky2->tx_prod = first_slot;
1724mapping_error:
1725 if (net_ratelimit())
1726 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1727 dev_kfree_skb(skb);
1728 return NETDEV_TX_OK;
cd28ab6a
SH		 1729}
1730
cd28ab6a 1731/*
793b883e
SH		 1732 * Free ring elements from starting at tx_cons until "done"
1733 *
1734 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1735 * buffers so make sure not to free skb to early.
cd28ab6a 1736 */
d11c13e7 1737static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1738{
d11c13e7 1739 struct net_device *dev = sky2->netdev;
af2a58ac 1740 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1741 unsigned idx;
cd28ab6a 1742
0e3ff6aa 1743 BUG_ON(done >= TX_RING_SIZE);
2224795d 1744
291ea614
SH		 1745 for (idx = sky2->tx_cons; idx != done;
1746 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1747 struct sky2_tx_le *le = sky2->tx_le + idx;
1748 struct tx_ring_info *re = sky2->tx_ring + idx;
1749
1750 switch(le->opcode & ~HW_OWNER) {
1751 case OP_LARGESEND:
1752 case OP_PACKET:
1753 pci_unmap_single(pdev,
1754 pci_unmap_addr(re, mapaddr),
1755 pci_unmap_len(re, maplen),
1756 PCI_DMA_TODEVICE);
af2a58ac 1757 break;
291ea614
SH		 1758 case OP_BUFFER:
1759 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1760 pci_unmap_len(re, maplen),
734d1868 1761 PCI_DMA_TODEVICE);
291ea614
SH		 1762 break;
1763 }
1764
1765 if (le->ctrl & EOP) {
1766 if (unlikely(netif_msg_tx_done(sky2)))
1767 printk(KERN_DEBUG "%s: tx done %u\n",
1768 dev->name, idx);
3cf26753 1769
7138a0f5
SH		 1770 dev->stats.tx_packets++;
1771 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1772
794b2bd2 1773 dev_kfree_skb_any(re->skb);
3cf26753 1774 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1775 }
793b883e 1776 }
793b883e 1777
291ea614 1778 sky2->tx_cons = idx;
50432cb5
SH		 1779 smp_mb();
1780
22e11703 1781 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1782 netif_wake_queue(dev);
cd28ab6a
SH		 1783}
1784
1785/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1786static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1787{
2bb8c262
SH		 1788 struct sky2_port *sky2 = netdev_priv(dev);
1789
1790 netif_tx_lock_bh(dev);
d11c13e7 1791 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1792 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1793}
1794
1795/* Network shutdown */
1796static int sky2_down(struct net_device *dev)
1797{
1798 struct sky2_port *sky2 = netdev_priv(dev);
1799 struct sky2_hw *hw = sky2->hw;
1800 unsigned port = sky2->port;
1801 u16 ctrl;
e07b1aa8 1802 u32 imask;
cd28ab6a 1803
1b537565
SH		 1804 /* Never really got started! */
1805 if (!sky2->tx_le)
1806 return 0;
1807
cd28ab6a
SH		 1808 if (netif_msg_ifdown(sky2))
1809 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1810
ebc646f6
SH		 1811 /* Disable port IRQ */
1812 imask = sky2_read32(hw, B0_IMSK);
1813 imask &= ~portirq_msk[port];
1814 sky2_write32(hw, B0_IMSK, imask);
1815
6de16237
SH		 1816 synchronize_irq(hw->pdev->irq);
1817
d104acaf
SH		 1818 /* Force flow control off */
1819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1820
cd28ab6a
SH		 1821 /* Stop transmitter */
1822 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1823 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1824
1825 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1826 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1827
1828 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1829 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1830 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1831
6de16237
SH		 1832 /* Make sure no packets are pending */
1833 napi_synchronize(&hw->napi);
1834
cd28ab6a
SH		 1835 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1836
1837 /* Workaround shared GMAC reset */
793b883e
SH		 1838 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1839 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1840 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1841
1842 /* Disable Force Sync bit and Enable Alloc bit */
1843 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1844 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1845
1846 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1847 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1848 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1849
1850 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1851 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1852 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1853
1854 /* Reset the Tx prefetch units */
1855 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1856 PREF_UNIT_RST_SET);
1857
1858 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1859
6b1a3aef 1860 sky2_rx_stop(sky2);
cd28ab6a
SH		 1861
1862 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1863 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1864
b96936da 1865 sky2_phy_power_down(hw, port);
d3bcfbeb 1866
d571b694 1867 /* turn off LED's */
cd28ab6a
SH		 1868 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1869
2bb8c262 1870 sky2_tx_clean(dev);
cd28ab6a
SH		 1871 sky2_rx_clean(sky2);
1872
1873 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1874 sky2->rx_le, sky2->rx_le_map);
1875 kfree(sky2->rx_ring);
1876
1877 pci_free_consistent(hw->pdev,
1878 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1879 sky2->tx_le, sky2->tx_le_map);
1880 kfree(sky2->tx_ring);
1881
1b537565
SH		 1882 sky2->tx_le = NULL;
1883 sky2->rx_le = NULL;
1884
1885 sky2->rx_ring = NULL;
1886 sky2->tx_ring = NULL;
1887
cd28ab6a
SH		 1888 return 0;
1889}
1890
1891static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1892{
ea76e635 1893 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1894 return SPEED_1000;
1895
05745c4a
SH		 1896 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1897 if (aux & PHY_M_PS_SPEED_100)
1898 return SPEED_100;
1899 else
1900 return SPEED_10;
1901 }
cd28ab6a
SH		 1902
1903 switch (aux & PHY_M_PS_SPEED_MSK) {
1904 case PHY_M_PS_SPEED_1000:
1905 return SPEED_1000;
1906 case PHY_M_PS_SPEED_100:
1907 return SPEED_100;
1908 default:
1909 return SPEED_10;
1910 }
1911}
1912
1913static void sky2_link_up(struct sky2_port *sky2)
1914{
1915 struct sky2_hw *hw = sky2->hw;
1916 unsigned port = sky2->port;
1917 u16 reg;
16ad91e1
SH		 1918 static const char *fc_name[] = {
1919 [FC_NONE] = "none",
1920 [FC_TX] = "tx",
1921 [FC_RX] = "rx",
1922 [FC_BOTH] = "both",
1923 };
cd28ab6a 1924
cd28ab6a 1925 /* enable Rx/Tx */
2eaba1a2 1926 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1927 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1928 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1929
1930 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1931
1932 netif_carrier_on(sky2->netdev);
cd28ab6a 1933
75e80683 1934 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1935
cd28ab6a 1936 /* Turn on link LED */
793b883e 1937 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1938 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1939
1940 if (netif_msg_link(sky2))
1941 printk(KERN_INFO PFX
d571b694 1942 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1943 sky2->netdev->name, sky2->speed,
1944 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1945 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1946}
1947
1948static void sky2_link_down(struct sky2_port *sky2)
1949{
1950 struct sky2_hw *hw = sky2->hw;
1951 unsigned port = sky2->port;
1952 u16 reg;
1953
1954 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1955
1956 reg = gma_read16(hw, port, GM_GP_CTRL);
1957 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1958 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1959
cd28ab6a 1960 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1961
1962 /* Turn on link LED */
1963 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1964
1965 if (netif_msg_link(sky2))
1966 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1967
cd28ab6a
SH		 1968 sky2_phy_init(hw, port);
1969}
1970
16ad91e1
SH		 1971static enum flow_control sky2_flow(int rx, int tx)
1972{
1973 if (rx)
1974 return tx ? FC_BOTH : FC_RX;
1975 else
1976 return tx ? FC_TX : FC_NONE;
1977}
1978
793b883e
SH		 1979static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1980{
1981 struct sky2_hw *hw = sky2->hw;
1982 unsigned port = sky2->port;
da4c1ff4 1983 u16 advert, lpa;
793b883e 1984
da4c1ff4 1985 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1986 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1987 if (lpa & PHY_M_AN_RF) {
1988 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1989 return -1;
1990 }
1991
793b883e
SH		 1992 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1993 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1994 sky2->netdev->name);
1995 return -1;
1996 }
1997
793b883e 1998 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1999 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2000
da4c1ff4
SH		 2001 /* Since the pause result bits seem to in different positions on
2002 * different chips. look at registers.
2003 */
ea76e635 2004 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2005 /* Shift for bits in fiber PHY */
2006 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2007 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2008
2009 if (advert & ADVERTISE_1000XPAUSE)
2010 advert |= ADVERTISE_PAUSE_CAP;
2011 if (advert & ADVERTISE_1000XPSE_ASYM)
2012 advert |= ADVERTISE_PAUSE_ASYM;
2013 if (lpa & LPA_1000XPAUSE)
2014 lpa |= LPA_PAUSE_CAP;
2015 if (lpa & LPA_1000XPAUSE_ASYM)
2016 lpa |= LPA_PAUSE_ASYM;
2017 }
793b883e 2018
da4c1ff4
SH		 2019 sky2->flow_status = FC_NONE;
2020 if (advert & ADVERTISE_PAUSE_CAP) {
2021 if (lpa & LPA_PAUSE_CAP)
2022 sky2->flow_status = FC_BOTH;
2023 else if (advert & ADVERTISE_PAUSE_ASYM)
2024 sky2->flow_status = FC_RX;
2025 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2026 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2027 sky2->flow_status = FC_TX;
2028 }
793b883e 2029
16ad91e1 2030 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2031 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2032 sky2->flow_status = FC_NONE;
2eaba1a2 2033
da4c1ff4 2034 if (sky2->flow_status & FC_TX)
793b883e
SH		 2035 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2036 else
2037 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2038
2039 return 0;
2040}
cd28ab6a 2041
e07b1aa8
SH		 2042/* Interrupt from PHY */
2043static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2044{
e07b1aa8
SH		 2045 struct net_device *dev = hw->dev[port];
2046 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2047 u16 istatus, phystat;
2048
ebc646f6
SH		 2049 if (!netif_running(dev))
2050 return;
2051
e07b1aa8
SH		 2052 spin_lock(&sky2->phy_lock);
2053 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2054 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2055
cd28ab6a
SH		 2056 if (netif_msg_intr(sky2))
2057 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2058 sky2->netdev->name, istatus, phystat);
2059
2eaba1a2 2060 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2061 if (sky2_autoneg_done(sky2, phystat) == 0)
2062 sky2_link_up(sky2);
2063 goto out;
2064 }
cd28ab6a 2065
793b883e
SH		 2066 if (istatus & PHY_M_IS_LSP_CHANGE)
2067 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2068
793b883e
SH		 2069 if (istatus & PHY_M_IS_DUP_CHANGE)
2070 sky2->duplex =
2071 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2072
793b883e
SH		 2073 if (istatus & PHY_M_IS_LST_CHANGE) {
2074 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2075 sky2_link_up(sky2);
793b883e
SH		 2076 else
2077 sky2_link_down(sky2);
cd28ab6a 2078 }
793b883e 2079out:
e07b1aa8 2080 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2081}
2082
62335ab0 2083/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2084 * and tx queue is full (stopped).
2085 */
cd28ab6a
SH		 2086static void sky2_tx_timeout(struct net_device *dev)
2087{
2088 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2089 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2090
2091 if (netif_msg_timer(sky2))
2092 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2093
8f24664d 2094 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2095 dev->name, sky2->tx_cons, sky2->tx_prod,
2096 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2097 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2098
81906791
SH		 2099 /* can't restart safely under softirq */
2100 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2101}
2102
2103static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2104{
6b1a3aef
SH		 2105 struct sky2_port *sky2 = netdev_priv(dev);
2106 struct sky2_hw *hw = sky2->hw;
b628ed98 2107 unsigned port = sky2->port;
6b1a3aef
SH		 2108 int err;
2109 u16 ctl, mode;
e07b1aa8 2110 u32 imask;
cd28ab6a
SH		 2111
2112 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2113 return -EINVAL;
2114
05745c4a
SH		 2115 if (new_mtu > ETH_DATA_LEN &&
2116 (hw->chip_id == CHIP_ID_YUKON_FE ||
2117 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2118 return -EINVAL;
2119
6b1a3aef
SH		 2120 if (!netif_running(dev)) {
2121 dev->mtu = new_mtu;
2122 return 0;
2123 }
2124
e07b1aa8 2125 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2126 sky2_write32(hw, B0_IMSK, 0);
2127
018d1c66
SH		 2128 dev->trans_start = jiffies; /* prevent tx timeout */
2129 netif_stop_queue(dev);
bea3348e 2130 napi_disable(&hw->napi);
018d1c66 2131
e07b1aa8
SH		 2132 synchronize_irq(hw->pdev->irq);
2133
39dbd958 2134 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2135 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2136
2137 ctl = gma_read16(hw, port, GM_GP_CTRL);
2138 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2139 sky2_rx_stop(sky2);
2140 sky2_rx_clean(sky2);
cd28ab6a
SH		 2141
2142 dev->mtu = new_mtu;
14d0263f 2143
6b1a3aef
SH		 2144 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2145 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2146
2147 if (dev->mtu > ETH_DATA_LEN)
2148 mode |= GM_SMOD_JUMBO_ENA;
2149
b628ed98 2150 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2151
b628ed98 2152 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2153
6b1a3aef 2154 err = sky2_rx_start(sky2);
e07b1aa8 2155 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2156
d1d08d12 2157 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2158 napi_enable(&hw->napi);
2159
1b537565
SH		 2160 if (err)
2161 dev_close(dev);
2162 else {
b628ed98 2163 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2164
1b537565
SH		 2165 netif_wake_queue(dev);
2166 }
2167
cd28ab6a
SH		 2168 return err;
2169}
2170
14d0263f
SH		 2171/* For small just reuse existing skb for next receive */
2172static struct sk_buff *receive_copy(struct sky2_port *sky2,
2173 const struct rx_ring_info *re,
2174 unsigned length)
2175{
2176 struct sk_buff *skb;
2177
2178 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2179 if (likely(skb)) {
2180 skb_reserve(skb, 2);
2181 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2182 length, PCI_DMA_FROMDEVICE);
d626f62b 2183 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2184 skb->ip_summed = re->skb->ip_summed;
2185 skb->csum = re->skb->csum;
2186 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2187 length, PCI_DMA_FROMDEVICE);
2188 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2189 skb_put(skb, length);
14d0263f
SH		 2190 }
2191 return skb;
2192}
2193
2194/* Adjust length of skb with fragments to match received data */
2195static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2196 unsigned int length)
2197{
2198 int i, num_frags;
2199 unsigned int size;
2200
2201 /* put header into skb */
2202 size = min(length, hdr_space);
2203 skb->tail += size;
2204 skb->len += size;
2205 length -= size;
2206
2207 num_frags = skb_shinfo(skb)->nr_frags;
2208 for (i = 0; i < num_frags; i++) {
2209 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2210
2211 if (length == 0) {
2212 /* don't need this page */
2213 __free_page(frag->page);
2214 --skb_shinfo(skb)->nr_frags;
2215 } else {
2216 size = min(length, (unsigned) PAGE_SIZE);
2217
2218 frag->size = size;
2219 skb->data_len += size;
2220 skb->truesize += size;
2221 skb->len += size;
2222 length -= size;
2223 }
2224 }
2225}
2226
2227/* Normal packet - take skb from ring element and put in a new one */
2228static struct sk_buff *receive_new(struct sky2_port *sky2,
2229 struct rx_ring_info *re,
2230 unsigned int length)
2231{
2232 struct sk_buff *skb, *nskb;
2233 unsigned hdr_space = sky2->rx_data_size;
2234
14d0263f
SH		 2235 /* Don't be tricky about reusing pages (yet) */
2236 nskb = sky2_rx_alloc(sky2);
2237 if (unlikely(!nskb))
2238 return NULL;
2239
2240 skb = re->skb;
2241 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2242
2243 prefetch(skb->data);
2244 re->skb = nskb;
454e6cb6
SH		 2245 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2246 dev_kfree_skb(nskb);
2247 re->skb = skb;
2248 return NULL;
2249 }
14d0263f
SH		 2250
2251 if (skb_shinfo(skb)->nr_frags)
2252 skb_put_frags(skb, hdr_space, length);
2253 else
489b10c1 2254 skb_put(skb, length);
14d0263f
SH		 2255 return skb;
2256}
2257
cd28ab6a
SH		 2258/*
2259 * Receive one packet.
d571b694 2260 * For larger packets, get new buffer.
cd28ab6a 2261 */
497d7c86 2262static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2263 u16 length, u32 status)
2264{
497d7c86 2265 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2266 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2267 struct sk_buff *skb = NULL;
d6532232
SH		 2268 u16 count = (status & GMR_FS_LEN) >> 16;
2269
2270#ifdef SKY2_VLAN_TAG_USED
2271 /* Account for vlan tag */
2272 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2273 count -= VLAN_HLEN;
2274#endif
cd28ab6a
SH		 2275
2276 if (unlikely(netif_msg_rx_status(sky2)))
2277 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2278 dev->name, sky2->rx_next, status, length);
cd28ab6a 2279
793b883e 2280 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2281 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2282
3b12e014
SH		 2283 /* This chip has hardware problems that generates bogus status.
2284 * So do only marginal checking and expect higher level protocols
2285 * to handle crap frames.
2286 */
2287 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2288 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2289 length != count)
2290 goto okay;
2291
42eeea01 2292 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2293 goto error;
2294
42eeea01
SH		 2295 if (!(status & GMR_FS_RX_OK))
2296 goto resubmit;
2297
d6532232
SH		 2298 /* if length reported by DMA does not match PHY, packet was truncated */
2299 if (length != count)
3b12e014 2300 goto len_error;
71749531 2301
3b12e014 2302okay:
14d0263f
SH		 2303 if (length < copybreak)
2304 skb = receive_copy(sky2, re, length);
2305 else
2306 skb = receive_new(sky2, re, length);
793b883e 2307resubmit:
14d0263f 2308 sky2_rx_submit(sky2, re);
79e57d32 2309
cd28ab6a
SH		 2310 return skb;
2311
3b12e014 2312len_error:
71749531
SH		 2313 /* Truncation of overlength packets
2314 causes PHY length to not match MAC length */
7138a0f5 2315 ++dev->stats.rx_length_errors;
d6532232 2316 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2317 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2318 dev->name, status, length);
d6532232 2319 goto resubmit;
71749531 2320
cd28ab6a 2321error:
7138a0f5 2322 ++dev->stats.rx_errors;
b6d77734 2323 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2324 dev->stats.rx_over_errors++;
b6d77734
SH		 2325 goto resubmit;
2326 }
6e15b712 2327
3be92a70 2328 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2329 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2330 dev->name, status, length);
793b883e
SH		 2331
2332 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2333 dev->stats.rx_length_errors++;
cd28ab6a 2334 if (status & GMR_FS_FRAGMENT)
7138a0f5 2335 dev->stats.rx_frame_errors++;
cd28ab6a 2336 if (status & GMR_FS_CRC_ERR)
7138a0f5 2337 dev->stats.rx_crc_errors++;
79e57d32 2338
793b883e 2339 goto resubmit;
cd28ab6a
SH		 2340}
2341
e07b1aa8
SH		 2342/* Transmit complete */
2343static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2344{
e07b1aa8 2345 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2346
e07b1aa8 2347 if (netif_running(dev)) {
2bb8c262 2348 netif_tx_lock(dev);
e07b1aa8 2349 sky2_tx_complete(sky2, last);
2bb8c262 2350 netif_tx_unlock(dev);
2224795d 2351 }
cd28ab6a
SH		 2352}
2353
e07b1aa8 2354/* Process status response ring */
26691830 2355static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2356{
e07b1aa8 2357 int work_done = 0;
55c9dd35 2358 unsigned rx[2] = { 0, 0 };
a8fd6266 2359
af2a58ac 2360 rmb();
26691830 2361 do {
55c9dd35 2362 struct sky2_port *sky2;
13210ce5 2363 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2364 unsigned port;
13210ce5 2365 struct net_device *dev;
cd28ab6a 2366 struct sk_buff *skb;
cd28ab6a
SH		 2367 u32 status;
2368 u16 length;
ab5adecb
SH		 2369 u8 opcode = le->opcode;
2370
2371 if (!(opcode & HW_OWNER))
2372 break;
cd28ab6a 2373
cb5d9547 2374 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2375
ab5adecb 2376 port = le->css & CSS_LINK_BIT;
69161611 2377 dev = hw->dev[port];
13210ce5 2378 sky2 = netdev_priv(dev);
f65b138c
SH		 2379 length = le16_to_cpu(le->length);
2380 status = le32_to_cpu(le->status);
cd28ab6a 2381
ab5adecb
SH		 2382 le->opcode = 0;
2383 switch (opcode & ~HW_OWNER) {
cd28ab6a 2384 case OP_RXSTAT:
55c9dd35 2385 ++rx[port];
497d7c86 2386 skb = sky2_receive(dev, length, status);
3225b919 2387 if (unlikely(!skb)) {
7138a0f5 2388 dev->stats.rx_dropped++;
55c9dd35 2389 break;
3225b919 2390 }
13210ce5 2391
69161611 2392 /* This chip reports checksum status differently */
05745c4a 2393 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2394 if (sky2->rx_csum &&
2395 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2396 (le->css & CSS_TCPUDPCSOK))
2397 skb->ip_summed = CHECKSUM_UNNECESSARY;
2398 else
2399 skb->ip_summed = CHECKSUM_NONE;
2400 }
2401
13210ce5 2402 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2403 dev->stats.rx_packets++;
2404 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2405 dev->last_rx = jiffies;
2406
d1f13708
SH		 2407#ifdef SKY2_VLAN_TAG_USED
2408 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2409 vlan_hwaccel_receive_skb(skb,
2410 sky2->vlgrp,
2411 be16_to_cpu(sky2->rx_tag));
2412 } else
2413#endif
cd28ab6a 2414 netif_receive_skb(skb);
13210ce5 2415
22e11703 2416 /* Stop after net poll weight */
13210ce5
SH		 2417 if (++work_done >= to_do)
2418 goto exit_loop;
cd28ab6a
SH		 2419 break;
2420
d1f13708
SH		 2421#ifdef SKY2_VLAN_TAG_USED
2422 case OP_RXVLAN:
2423 sky2->rx_tag = length;
2424 break;
2425
2426 case OP_RXCHKSVLAN:
2427 sky2->rx_tag = length;
2428 /* fall through */
2429#endif
cd28ab6a 2430 case OP_RXCHKS:
87418307
SH		 2431 if (!sky2->rx_csum)
2432 break;
2433
05745c4a
SH		 2434 /* If this happens then driver assuming wrong format */
2435 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2436 if (net_ratelimit())
2437 printk(KERN_NOTICE "%s: unexpected"
2438 " checksum status\n",
2439 dev->name);
69161611 2440 break;
05745c4a 2441 }
69161611 2442
87418307
SH		 2443 /* Both checksum counters are programmed to start at
2444 * the same offset, so unless there is a problem they
2445 * should match. This failure is an early indication that
2446 * hardware receive checksumming won't work.
2447 */
2448 if (likely(status >> 16 == (status & 0xffff))) {
2449 skb = sky2->rx_ring[sky2->rx_next].skb;
2450 skb->ip_summed = CHECKSUM_COMPLETE;
2451 skb->csum = status & 0xffff;
2452 } else {
2453 printk(KERN_NOTICE PFX "%s: hardware receive "
2454 "checksum problem (status = %#x)\n",
2455 dev->name, status);
2456 sky2->rx_csum = 0;
2457 sky2_write32(sky2->hw,
69161611 2458 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2459 BMU_DIS_RX_CHKSUM);
2460 }
cd28ab6a
SH		 2461 break;
2462
2463 case OP_TXINDEXLE:
13b97b74 2464 /* TX index reports status for both ports */
f55925d7
SH		 2465 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2466 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2467 if (hw->dev[1])
2468 sky2_tx_done(hw->dev[1],
2469 ((status >> 24) & 0xff)
2470 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2471 break;
2472
cd28ab6a
SH		 2473 default:
2474 if (net_ratelimit())
793b883e 2475 printk(KERN_WARNING PFX
ab5adecb 2476 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2477 }
26691830 2478 } while (hw->st_idx != idx);
cd28ab6a 2479
fe2a24df
SH		 2480 /* Fully processed status ring so clear irq */
2481 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2482
13210ce5 2483exit_loop:
55c9dd35
SH		 2484 if (rx[0])
2485 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2486
55c9dd35
SH		 2487 if (rx[1])
2488 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2489
e07b1aa8 2490 return work_done;
cd28ab6a
SH		 2491}
2492
2493static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2494{
2495 struct net_device *dev = hw->dev[port];
2496
3be92a70
SH		 2497 if (net_ratelimit())
2498 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2499 dev->name, status);
cd28ab6a
SH		 2500
2501 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2502 if (net_ratelimit())
2503 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2504 dev->name);
cd28ab6a
SH		 2505 /* Clear IRQ */
2506 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2507 }
2508
2509 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2510 if (net_ratelimit())
2511 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2512 dev->name);
cd28ab6a
SH		 2513
2514 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2515 }
2516
2517 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2518 if (net_ratelimit())
2519 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2520 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2521 }
2522
2523 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2524 if (net_ratelimit())
2525 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2526 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2527 }
2528
2529 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2530 if (net_ratelimit())
2531 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2532 dev->name);
cd28ab6a
SH		 2533 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2534 }
2535}
2536
2537static void sky2_hw_intr(struct sky2_hw *hw)
2538{
555382cb 2539 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2540 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2541 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2542
2543 status &= hwmsk;
cd28ab6a 2544
793b883e 2545 if (status & Y2_IS_TIST_OV)
cd28ab6a 2546 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2547
2548 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2549 u16 pci_err;
2550
82637e80 2551 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2552 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2553 if (net_ratelimit())
555382cb 2554 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2555 pci_err);
cd28ab6a 2556
b32f40c4 2557 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2558 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2559 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2560 }
2561
2562 if (status & Y2_IS_PCI_EXP) {
d571b694 2563 /* PCI-Express uncorrectable Error occurred */
555382cb 2564 u32 err;
cd28ab6a 2565
82637e80 2566 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2567 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2568 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2569 0xfffffffful);
3be92a70 2570 if (net_ratelimit())
555382cb 2571 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2572
7782c8c4 2573 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2574 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2575 }
2576
2577 if (status & Y2_HWE_L1_MASK)
2578 sky2_hw_error(hw, 0, status);
2579 status >>= 8;
2580 if (status & Y2_HWE_L1_MASK)
2581 sky2_hw_error(hw, 1, status);
2582}
2583
2584static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2585{
2586 struct net_device *dev = hw->dev[port];
2587 struct sky2_port *sky2 = netdev_priv(dev);
2588 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2589
2590 if (netif_msg_intr(sky2))
2591 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2592 dev->name, status);
2593
a3caeada
SH		 2594 if (status & GM_IS_RX_CO_OV)
2595 gma_read16(hw, port, GM_RX_IRQ_SRC);
2596
2597 if (status & GM_IS_TX_CO_OV)
2598 gma_read16(hw, port, GM_TX_IRQ_SRC);
2599
cd28ab6a 2600 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2601 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2602 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2603 }
2604
2605 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2606 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2607 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2608 }
cd28ab6a
SH		 2609}
2610
40b01727
SH		 2611/* This should never happen it is a bug. */
2612static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2613 u16 q, unsigned ring_size)
d257924e
SH		 2614{
2615 struct net_device *dev = hw->dev[port];
2616 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2617 unsigned idx;
2618 const u64 *le = (q == Q_R1 || q == Q_R2)
2619 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2620
40b01727
SH		 2621 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2622 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2623 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2624 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2625
40b01727 2626 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2627}
cd28ab6a 2628
75e80683
SH		 2629static int sky2_rx_hung(struct net_device *dev)
2630{
2631 struct sky2_port *sky2 = netdev_priv(dev);
2632 struct sky2_hw *hw = sky2->hw;
2633 unsigned port = sky2->port;
2634 unsigned rxq = rxqaddr[port];
2635 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2636 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2637 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2638 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2639
2640 /* If idle and MAC or PCI is stuck */
2641 if (sky2->check.last == dev->last_rx &&
2642 ((mac_rp == sky2->check.mac_rp &&
2643 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2644 /* Check if the PCI RX hang */
2645 (fifo_rp == sky2->check.fifo_rp &&
2646 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2647 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2648 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2649 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2650 return 1;
2651 } else {
2652 sky2->check.last = dev->last_rx;
2653 sky2->check.mac_rp = mac_rp;
2654 sky2->check.mac_lev = mac_lev;
2655 sky2->check.fifo_rp = fifo_rp;
2656 sky2->check.fifo_lev = fifo_lev;
2657 return 0;
2658 }
2659}
2660
32c2c300 2661static void sky2_watchdog(unsigned long arg)
d27ed387 2662{
01bd7564 2663 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2664
75e80683 2665 /* Check for lost IRQ once a second */
32c2c300 2666 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2667 napi_schedule(&hw->napi);
75e80683
SH		 2668 } else {
2669 int i, active = 0;
2670
2671 for (i = 0; i < hw->ports; i++) {
bea3348e 2672 struct net_device *dev = hw->dev[i];
75e80683
SH		 2673 if (!netif_running(dev))
2674 continue;
2675 ++active;
2676
2677 /* For chips with Rx FIFO, check if stuck */
39dbd958 2678 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2679 sky2_rx_hung(dev)) {
2680 pr_info(PFX "%s: receiver hang detected\n",
2681 dev->name);
2682 schedule_work(&hw->restart_work);
2683 return;
2684 }
2685 }
2686
2687 if (active == 0)
2688 return;
32c2c300 2689 }
01bd7564 2690
75e80683 2691 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2692}
2693
40b01727
SH		 2694/* Hardware/software error handling */
2695static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2696{
40b01727
SH		 2697 if (net_ratelimit())
2698 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2699
1e5f1283
SH		 2700 if (status & Y2_IS_HW_ERR)
2701 sky2_hw_intr(hw);
d257924e 2702
1e5f1283
SH		 2703 if (status & Y2_IS_IRQ_MAC1)
2704 sky2_mac_intr(hw, 0);
cd28ab6a 2705
1e5f1283
SH		 2706 if (status & Y2_IS_IRQ_MAC2)
2707 sky2_mac_intr(hw, 1);
cd28ab6a 2708
1e5f1283 2709 if (status & Y2_IS_CHK_RX1)
40b01727 2710 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2711
1e5f1283 2712 if (status & Y2_IS_CHK_RX2)
40b01727 2713 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2714
1e5f1283 2715 if (status & Y2_IS_CHK_TXA1)
40b01727 2716 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2717
1e5f1283 2718 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2719 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2720}
2721
bea3348e 2722static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2723{
bea3348e 2724 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2725 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2726 int work_done = 0;
26691830 2727 u16 idx;
40b01727
SH		 2728
2729 if (unlikely(status & Y2_IS_ERROR))
2730 sky2_err_intr(hw, status);
2731
2732 if (status & Y2_IS_IRQ_PHY1)
2733 sky2_phy_intr(hw, 0);
2734
2735 if (status & Y2_IS_IRQ_PHY2)
2736 sky2_phy_intr(hw, 1);
cd28ab6a 2737
26691830
SH		 2738 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2739 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2740
2741 if (work_done >= work_limit)
26691830
SH		 2742 goto done;
2743 }
6f535763 2744
26691830
SH		 2745 napi_complete(napi);
2746 sky2_read32(hw, B0_Y2_SP_LISR);
2747done:
6f535763 2748
bea3348e 2749 return work_done;
e07b1aa8
SH		 2750}
2751
7d12e780 2752static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2753{
2754 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2755 u32 status;
2756
2757 /* Reading this mask interrupts as side effect */
2758 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2759 if (status == 0 || status == ~0)
2760 return IRQ_NONE;
793b883e 2761
e07b1aa8 2762 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2763
2764 napi_schedule(&hw->napi);
793b883e 2765
cd28ab6a
SH		 2766 return IRQ_HANDLED;
2767}
2768
2769#ifdef CONFIG_NET_POLL_CONTROLLER
2770static void sky2_netpoll(struct net_device *dev)
2771{
2772 struct sky2_port *sky2 = netdev_priv(dev);
2773
bea3348e 2774 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2775}
2776#endif
2777
2778/* Chip internal frequency for clock calculations */
05745c4a 2779static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2780{
793b883e 2781 switch (hw->chip_id) {
cd28ab6a 2782 case CHIP_ID_YUKON_EC:
5a5b1ea0 2783 case CHIP_ID_YUKON_EC_U:
93745494 2784 case CHIP_ID_YUKON_EX:
ed4d4161 2785 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2786 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2787 return 125;
2788
cd28ab6a 2789 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2790 return 100;
2791
2792 case CHIP_ID_YUKON_FE_P:
2793 return 50;
2794
2795 case CHIP_ID_YUKON_XL:
2796 return 156;
2797
2798 default:
2799 BUG();
cd28ab6a
SH		 2800 }
2801}
2802
fb17358f 2803static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2804{
fb17358f 2805 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2806}
2807
fb17358f 2808static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2809{
fb17358f 2810 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2811}
2812
fb17358f 2813
e3173832 2814static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2815{
b89165f2 2816 u8 t8;
cd28ab6a 2817
167f53d0 2818 /* Enable all clocks and check for bad PCI access */
b32f40c4 2819 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2820
cd28ab6a 2821 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2822
cd28ab6a 2823 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2824 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2825
2826 switch(hw->chip_id) {
2827 case CHIP_ID_YUKON_XL:
39dbd958 2828 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2829 break;
2830
2831 case CHIP_ID_YUKON_EC_U:
2832 hw->flags = SKY2_HW_GIGABIT
2833 | SKY2_HW_NEWER_PHY
2834 | SKY2_HW_ADV_POWER_CTL;
2835 break;
2836
2837 case CHIP_ID_YUKON_EX:
2838 hw->flags = SKY2_HW_GIGABIT
2839 | SKY2_HW_NEWER_PHY
2840 | SKY2_HW_NEW_LE
2841 | SKY2_HW_ADV_POWER_CTL;
2842
2843 /* New transmit checksum */
2844 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2845 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2846 break;
2847
2848 case CHIP_ID_YUKON_EC:
2849 /* This rev is really old, and requires untested workarounds */
2850 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2851 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2852 return -EOPNOTSUPP;
2853 }
39dbd958 2854 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2855 break;
2856
2857 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2858 break;
2859
05745c4a
SH		 2860 case CHIP_ID_YUKON_FE_P:
2861 hw->flags = SKY2_HW_NEWER_PHY
2862 | SKY2_HW_NEW_LE
2863 | SKY2_HW_AUTO_TX_SUM
2864 | SKY2_HW_ADV_POWER_CTL;
2865 break;
ed4d4161
SH		 2866
2867 case CHIP_ID_YUKON_SUPR:
2868 hw->flags = SKY2_HW_GIGABIT
2869 | SKY2_HW_NEWER_PHY
2870 | SKY2_HW_NEW_LE
2871 | SKY2_HW_AUTO_TX_SUM
2872 | SKY2_HW_ADV_POWER_CTL;
2873 break;
2874
0ce8b98d
SH		 2875 case CHIP_ID_YUKON_UL_2:
2876 hw->flags = SKY2_HW_GIGABIT
2877 | SKY2_HW_ADV_POWER_CTL;
2878 break;
2879
ea76e635 2880 default:
b02a9258
SH		 2881 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2882 hw->chip_id);
cd28ab6a
SH		 2883 return -EOPNOTSUPP;
2884 }
2885
ea76e635
SH		 2886 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2887 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2888 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2889
e3173832
SH		 2890 hw->ports = 1;
2891 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2892 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2893 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2894 ++hw->ports;
2895 }
2896
2897 return 0;
2898}
2899
2900static void sky2_reset(struct sky2_hw *hw)
2901{
555382cb 2902 struct pci_dev *pdev = hw->pdev;
e3173832 2903 u16 status;
555382cb
SH		 2904 int i, cap;
2905 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2906
cd28ab6a 2907 /* disable ASF */
4f44d8ba
SH		 2908 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2909 status = sky2_read16(hw, HCU_CCSR);
2910 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2911 HCU_CCSR_UC_STATE_MSK);
2912 sky2_write16(hw, HCU_CCSR, status);
2913 } else
2914 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2915 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2916
2917 /* do a SW reset */
2918 sky2_write8(hw, B0_CTST, CS_RST_SET);
2919 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2920
ac93a394
SH		 2921 /* allow writes to PCI config */
2922 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2923
cd28ab6a 2924 /* clear PCI errors, if any */
b32f40c4 2925 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2926 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2927 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2928
2929 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2930
555382cb
SH		 2931 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2932 if (cap) {
7782c8c4
SH		 2933 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2934 0xfffffffful);
555382cb
SH		 2935
2936 /* If error bit is stuck on ignore it */
2937 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2938 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2939 else
555382cb
SH		 2940 hwe_mask |= Y2_IS_PCI_EXP;
2941 }
cd28ab6a 2942
ae306cca 2943 sky2_power_on(hw);
82637e80 2944 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2945
2946 for (i = 0; i < hw->ports; i++) {
2947 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2948 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2949
ed4d4161
SH		 2950 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2951 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2952 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2953 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2954 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2955 }
2956
793b883e
SH		 2957 /* Clear I2C IRQ noise */
2958 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2959
2960 /* turn off hardware timer (unused) */
2961 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2962 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2963
cd28ab6a
SH		 2964 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2965
69634ee7
SH		 2966 /* Turn off descriptor polling */
2967 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2968
2969 /* Turn off receive timestamp */
2970 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2971 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2972
2973 /* enable the Tx Arbiters */
2974 for (i = 0; i < hw->ports; i++)
2975 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2976
2977 /* Initialize ram interface */
2978 for (i = 0; i < hw->ports; i++) {
793b883e 2979 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2980
2981 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2982 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2983 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2984 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2985 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2986 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2987 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2988 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2989 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2990 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2991 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2992 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2993 }
2994
555382cb 2995 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2996
cd28ab6a 2997 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2998 sky2_gmac_reset(hw, i);
cd28ab6a 2999
cd28ab6a
SH		 3000 memset(hw->st_le, 0, STATUS_LE_BYTES);
3001 hw->st_idx = 0;
3002
3003 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3004 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3005
3006 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3007 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3008
3009 /* Set the list last index */
793b883e 3010 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3011
290d4de5
SH		 3012 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3013 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3014
290d4de5
SH		 3015 /* set Status-FIFO ISR watermark */
3016 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3017 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3018 else
3019 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3020
290d4de5 3021 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3022 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3023 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3024
793b883e 3025 /* enable status unit */
cd28ab6a
SH		 3026 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3027
3028 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3029 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3030 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3031}
3032
81906791
SH		 3033static void sky2_restart(struct work_struct *work)
3034{
3035 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3036 struct net_device *dev;
3037 int i, err;
3038
81906791 3039 rtnl_lock();
81906791
SH		 3040 for (i = 0; i < hw->ports; i++) {
3041 dev = hw->dev[i];
3042 if (netif_running(dev))
3043 sky2_down(dev);
3044 }
3045
8cfcbe99
SH		 3046 napi_disable(&hw->napi);
3047 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3048 sky2_reset(hw);
3049 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3050 napi_enable(&hw->napi);
81906791
SH		 3051
3052 for (i = 0; i < hw->ports; i++) {
3053 dev = hw->dev[i];
3054 if (netif_running(dev)) {
3055 err = sky2_up(dev);
3056 if (err) {
3057 printk(KERN_INFO PFX "%s: could not restart %d\n",
3058 dev->name, err);
3059 dev_close(dev);
3060 }
3061 }
3062 }
3063
81906791
SH		 3064 rtnl_unlock();
3065}
3066
e3173832
SH		 3067static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3068{
3069 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3070}
3071
3072static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3073{
3074 const struct sky2_port *sky2 = netdev_priv(dev);
3075
3076 wol->supported = sky2_wol_supported(sky2->hw);
3077 wol->wolopts = sky2->wol;
3078}
3079
3080static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3081{
3082 struct sky2_port *sky2 = netdev_priv(dev);
3083 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3084
9d731d77
RW		 3085 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3086 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3087 return -EOPNOTSUPP;
3088
3089 sky2->wol = wol->wolopts;
3090
05745c4a
SH		 3091 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3092 hw->chip_id == CHIP_ID_YUKON_EX ||
3093 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3094 sky2_write32(hw, B0_CTST, sky2->wol
3095 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3096
9d731d77
RW		 3097 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3098
e3173832
SH		 3099 if (!netif_running(dev))
3100 sky2_wol_init(sky2);
cd28ab6a
SH		 3101 return 0;
3102}
3103
28bd181a 3104static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3105{
b89165f2
SH		 3106 if (sky2_is_copper(hw)) {
3107 u32 modes = SUPPORTED_10baseT_Half
3108 | SUPPORTED_10baseT_Full
3109 | SUPPORTED_100baseT_Half
3110 | SUPPORTED_100baseT_Full
3111 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3112
ea76e635 3113 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3114 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3115 | SUPPORTED_1000baseT_Full;
3116 return modes;
cd28ab6a 3117 } else
b89165f2
SH		 3118 return SUPPORTED_1000baseT_Half
3119 | SUPPORTED_1000baseT_Full
3120 | SUPPORTED_Autoneg
3121 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3122}
3123
793b883e 3124static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3125{
3126 struct sky2_port *sky2 = netdev_priv(dev);
3127 struct sky2_hw *hw = sky2->hw;
3128
3129 ecmd->transceiver = XCVR_INTERNAL;
3130 ecmd->supported = sky2_supported_modes(hw);
3131 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3132 if (sky2_is_copper(hw)) {
cd28ab6a 3133 ecmd->port = PORT_TP;
b89165f2
SH		 3134 ecmd->speed = sky2->speed;
3135 } else {
3136 ecmd->speed = SPEED_1000;
cd28ab6a 3137 ecmd->port = PORT_FIBRE;
b89165f2 3138 }
cd28ab6a
SH		 3139
3140 ecmd->advertising = sky2->advertising;
3141 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3142 ecmd->duplex = sky2->duplex;
3143 return 0;
3144}
3145
3146static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3147{
3148 struct sky2_port *sky2 = netdev_priv(dev);
3149 const struct sky2_hw *hw = sky2->hw;
3150 u32 supported = sky2_supported_modes(hw);
3151
3152 if (ecmd->autoneg == AUTONEG_ENABLE) {
3153 ecmd->advertising = supported;
3154 sky2->duplex = -1;
3155 sky2->speed = -1;
3156 } else {
3157 u32 setting;
3158
793b883e 3159 switch (ecmd->speed) {
cd28ab6a
SH		 3160 case SPEED_1000:
3161 if (ecmd->duplex == DUPLEX_FULL)
3162 setting = SUPPORTED_1000baseT_Full;
3163 else if (ecmd->duplex == DUPLEX_HALF)
3164 setting = SUPPORTED_1000baseT_Half;
3165 else
3166 return -EINVAL;
3167 break;
3168 case SPEED_100:
3169 if (ecmd->duplex == DUPLEX_FULL)
3170 setting = SUPPORTED_100baseT_Full;
3171 else if (ecmd->duplex == DUPLEX_HALF)
3172 setting = SUPPORTED_100baseT_Half;
3173 else
3174 return -EINVAL;
3175 break;
3176
3177 case SPEED_10:
3178 if (ecmd->duplex == DUPLEX_FULL)
3179 setting = SUPPORTED_10baseT_Full;
3180 else if (ecmd->duplex == DUPLEX_HALF)
3181 setting = SUPPORTED_10baseT_Half;
3182 else
3183 return -EINVAL;
3184 break;
3185 default:
3186 return -EINVAL;
3187 }
3188
3189 if ((setting & supported) == 0)
3190 return -EINVAL;
3191
3192 sky2->speed = ecmd->speed;
3193 sky2->duplex = ecmd->duplex;
3194 }
3195
3196 sky2->autoneg = ecmd->autoneg;
3197 sky2->advertising = ecmd->advertising;
3198
d1b139c0 3199 if (netif_running(dev)) {
1b537565 3200 sky2_phy_reinit(sky2);
d1b139c0
SH		 3201 sky2_set_multicast(dev);
3202 }
cd28ab6a
SH		 3203
3204 return 0;
3205}
3206
3207static void sky2_get_drvinfo(struct net_device *dev,
3208 struct ethtool_drvinfo *info)
3209{
3210 struct sky2_port *sky2 = netdev_priv(dev);
3211
3212 strcpy(info->driver, DRV_NAME);
3213 strcpy(info->version, DRV_VERSION);
3214 strcpy(info->fw_version, "N/A");
3215 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3216}
3217
3218static const struct sky2_stat {
793b883e
SH		 3219 char name[ETH_GSTRING_LEN];
3220 u16 offset;
cd28ab6a
SH		 3221} sky2_stats[] = {
3222 { "tx_bytes", GM_TXO_OK_HI },
3223 { "rx_bytes", GM_RXO_OK_HI },
3224 { "tx_broadcast", GM_TXF_BC_OK },
3225 { "rx_broadcast", GM_RXF_BC_OK },
3226 { "tx_multicast", GM_TXF_MC_OK },
3227 { "rx_multicast", GM_RXF_MC_OK },
3228 { "tx_unicast", GM_TXF_UC_OK },
3229 { "rx_unicast", GM_RXF_UC_OK },
3230 { "tx_mac_pause", GM_TXF_MPAUSE },
3231 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3232 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3233 { "late_collision",GM_TXF_LAT_COL },
3234 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3235 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3236 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3237
d2604540 3238 { "rx_short", GM_RXF_SHT },
cd28ab6a 3239 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3240 { "rx_64_byte_packets", GM_RXF_64B },
3241 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3242 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3243 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3244 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3245 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3246 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3247 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3248 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3249 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3250 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3251
3252 { "tx_64_byte_packets", GM_TXF_64B },
3253 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3254 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3255 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3256 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3257 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3258 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3259 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3260};
3261
cd28ab6a
SH		 3262static u32 sky2_get_rx_csum(struct net_device *dev)
3263{
3264 struct sky2_port *sky2 = netdev_priv(dev);
3265
3266 return sky2->rx_csum;
3267}
3268
3269static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3270{
3271 struct sky2_port *sky2 = netdev_priv(dev);
3272
3273 sky2->rx_csum = data;
793b883e 3274
cd28ab6a
SH		 3275 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3276 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3277
3278 return 0;
3279}
3280
3281static u32 sky2_get_msglevel(struct net_device *netdev)
3282{
3283 struct sky2_port *sky2 = netdev_priv(netdev);
3284 return sky2->msg_enable;
3285}
3286
9a7ae0a9
SH		 3287static int sky2_nway_reset(struct net_device *dev)
3288{
3289 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3290
16ad91e1 3291 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3292 return -EINVAL;
3293
1b537565 3294 sky2_phy_reinit(sky2);
d1b139c0 3295 sky2_set_multicast(dev);
9a7ae0a9
SH		 3296
3297 return 0;
3298}
3299
793b883e 3300static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3301{
3302 struct sky2_hw *hw = sky2->hw;
3303 unsigned port = sky2->port;
3304 int i;
3305
3306 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3307 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3308 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3309 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3310
793b883e 3311 for (i = 2; i < count; i++)
cd28ab6a
SH		 3312 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3313}
3314
cd28ab6a
SH		 3315static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3316{
3317 struct sky2_port *sky2 = netdev_priv(netdev);
3318 sky2->msg_enable = value;
3319}
3320
b9f2c044 3321static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3322{
b9f2c044
JG		 3323 switch (sset) {
3324 case ETH_SS_STATS:
3325 return ARRAY_SIZE(sky2_stats);
3326 default:
3327 return -EOPNOTSUPP;
3328 }
cd28ab6a
SH		 3329}
3330
3331static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3332 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3333{
3334 struct sky2_port *sky2 = netdev_priv(dev);
3335
793b883e 3336 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3337}
3338
793b883e 3339static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3340{
3341 int i;
3342
3343 switch (stringset) {
3344 case ETH_SS_STATS:
3345 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3346 memcpy(data + i * ETH_GSTRING_LEN,
3347 sky2_stats[i].name, ETH_GSTRING_LEN);
3348 break;
3349 }
3350}
3351
cd28ab6a
SH		 3352static int sky2_set_mac_address(struct net_device *dev, void *p)
3353{
3354 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3355 struct sky2_hw *hw = sky2->hw;
3356 unsigned port = sky2->port;
3357 const struct sockaddr *addr = p;
cd28ab6a
SH		 3358
3359 if (!is_valid_ether_addr(addr->sa_data))
3360 return -EADDRNOTAVAIL;
3361
cd28ab6a 3362 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3363 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3364 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3365 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3366 dev->dev_addr, ETH_ALEN);
1b537565 3367
a8ab1ec0
SH		 3368 /* virtual address for data */
3369 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3370
3371 /* physical address: used for pause frames */
3372 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3373
3374 return 0;
cd28ab6a
SH		 3375}
3376
a052b52f
SH		 3377static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3378{
3379 u32 bit;
3380
3381 bit = ether_crc(ETH_ALEN, addr) & 63;
3382 filter[bit >> 3] |= 1 << (bit & 7);
3383}
3384
cd28ab6a
SH		 3385static void sky2_set_multicast(struct net_device *dev)
3386{
3387 struct sky2_port *sky2 = netdev_priv(dev);
3388 struct sky2_hw *hw = sky2->hw;
3389 unsigned port = sky2->port;
3390 struct dev_mc_list *list = dev->mc_list;
3391 u16 reg;
3392 u8 filter[8];
a052b52f
SH		 3393 int rx_pause;
3394 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3395
a052b52f 3396 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3397 memset(filter, 0, sizeof(filter));
3398
3399 reg = gma_read16(hw, port, GM_RX_CTRL);
3400 reg |= GM_RXCR_UCF_ENA;
3401
d571b694 3402 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3403 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3404 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3405 memset(filter, 0xff, sizeof(filter));
a052b52f 3406 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3407 reg &= ~GM_RXCR_MCF_ENA;
3408 else {
3409 int i;
3410 reg |= GM_RXCR_MCF_ENA;
3411
a052b52f
SH		 3412 if (rx_pause)
3413 sky2_add_filter(filter, pause_mc_addr);
3414
3415 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3416 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3417 }
3418
cd28ab6a 3419 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3420 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3421 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3422 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3423 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3424 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3425 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3426 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3427
3428 gma_write16(hw, port, GM_RX_CTRL, reg);
3429}
3430
3431/* Can have one global because blinking is controlled by
3432 * ethtool and that is always under RTNL mutex
3433 */
a84d0a3d 3434static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3435{
a84d0a3d
SH		 3436 struct sky2_hw *hw = sky2->hw;
3437 unsigned port = sky2->port;
793b883e 3438
a84d0a3d
SH		 3439 spin_lock_bh(&sky2->phy_lock);
3440 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3441 hw->chip_id == CHIP_ID_YUKON_EX ||
3442 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3443 u16 pg;
793b883e
SH		 3444 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3445 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3446
a84d0a3d
SH		 3447 switch (mode) {
3448 case MO_LED_OFF:
3449 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3450 PHY_M_LEDC_LOS_CTRL(8) |
3451 PHY_M_LEDC_INIT_CTRL(8) |
3452 PHY_M_LEDC_STA1_CTRL(8) |
3453 PHY_M_LEDC_STA0_CTRL(8));
3454 break;
3455 case MO_LED_ON:
3456 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3457 PHY_M_LEDC_LOS_CTRL(9) |
3458 PHY_M_LEDC_INIT_CTRL(9) |
3459 PHY_M_LEDC_STA1_CTRL(9) |
3460 PHY_M_LEDC_STA0_CTRL(9));
3461 break;
3462 case MO_LED_BLINK:
3463 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3464 PHY_M_LEDC_LOS_CTRL(0xa) |
3465 PHY_M_LEDC_INIT_CTRL(0xa) |
3466 PHY_M_LEDC_STA1_CTRL(0xa) |
3467 PHY_M_LEDC_STA0_CTRL(0xa));
3468 break;
3469 case MO_LED_NORM:
3470 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3471 PHY_M_LEDC_LOS_CTRL(1) |
3472 PHY_M_LEDC_INIT_CTRL(8) |
3473 PHY_M_LEDC_STA1_CTRL(7) |
3474 PHY_M_LEDC_STA0_CTRL(7));
3475 }
793b883e 3476
a84d0a3d
SH		 3477 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3478 } else
7d2e3cb7 3479 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3480 PHY_M_LED_MO_DUP(mode) |
3481 PHY_M_LED_MO_10(mode) |
3482 PHY_M_LED_MO_100(mode) |
3483 PHY_M_LED_MO_1000(mode) |
3484 PHY_M_LED_MO_RX(mode) |
3485 PHY_M_LED_MO_TX(mode));
3486
3487 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3488}
3489
3490/* blink LED's for finding board */
3491static int sky2_phys_id(struct net_device *dev, u32 data)
3492{
3493 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3494 unsigned int i;
cd28ab6a 3495
a84d0a3d
SH		 3496 if (data == 0)
3497 data = UINT_MAX;
cd28ab6a 3498
a84d0a3d
SH		 3499 for (i = 0; i < data; i++) {
3500 sky2_led(sky2, MO_LED_ON);
3501 if (msleep_interruptible(500))
3502 break;
3503 sky2_led(sky2, MO_LED_OFF);
3504 if (msleep_interruptible(500))
3505 break;
793b883e 3506 }
a84d0a3d 3507 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3508
3509 return 0;
3510}
3511
3512static void sky2_get_pauseparam(struct net_device *dev,
3513 struct ethtool_pauseparam *ecmd)
3514{
3515 struct sky2_port *sky2 = netdev_priv(dev);
3516
16ad91e1
SH		 3517 switch (sky2->flow_mode) {
3518 case FC_NONE:
3519 ecmd->tx_pause = ecmd->rx_pause = 0;
3520 break;
3521 case FC_TX:
3522 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3523 break;
3524 case FC_RX:
3525 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3526 break;
3527 case FC_BOTH:
3528 ecmd->tx_pause = ecmd->rx_pause = 1;
3529 }
3530
cd28ab6a
SH		 3531 ecmd->autoneg = sky2->autoneg;
3532}
3533
3534static int sky2_set_pauseparam(struct net_device *dev,
3535 struct ethtool_pauseparam *ecmd)
3536{
3537 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3538
3539 sky2->autoneg = ecmd->autoneg;
16ad91e1 3540 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3541
16ad91e1
SH		 3542 if (netif_running(dev))
3543 sky2_phy_reinit(sky2);
cd28ab6a 3544
2eaba1a2 3545 return 0;
cd28ab6a
SH		 3546}
3547
fb17358f
SH		 3548static int sky2_get_coalesce(struct net_device *dev,
3549 struct ethtool_coalesce *ecmd)
3550{
3551 struct sky2_port *sky2 = netdev_priv(dev);
3552 struct sky2_hw *hw = sky2->hw;
3553
3554 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3555 ecmd->tx_coalesce_usecs = 0;
3556 else {
3557 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3558 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3559 }
3560 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3561
3562 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3563 ecmd->rx_coalesce_usecs = 0;
3564 else {
3565 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3566 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3567 }
3568 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3569
3570 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3571 ecmd->rx_coalesce_usecs_irq = 0;
3572 else {
3573 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3574 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3575 }
3576
3577 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3578
3579 return 0;
3580}
3581
3582/* Note: this affect both ports */
3583static int sky2_set_coalesce(struct net_device *dev,
3584 struct ethtool_coalesce *ecmd)
3585{
3586 struct sky2_port *sky2 = netdev_priv(dev);
3587 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3588 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3589
77b3d6a2
SH		 3590 if (ecmd->tx_coalesce_usecs > tmax ||
3591 ecmd->rx_coalesce_usecs > tmax ||
3592 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3593 return -EINVAL;
3594
ff81fbbe 3595 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3596 return -EINVAL;
ff81fbbe 3597 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3598 return -EINVAL;
ff81fbbe 3599 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3600 return -EINVAL;
3601
3602 if (ecmd->tx_coalesce_usecs == 0)
3603 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3604 else {
3605 sky2_write32(hw, STAT_TX_TIMER_INI,
3606 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3607 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3608 }
3609 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3610
3611 if (ecmd->rx_coalesce_usecs == 0)
3612 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3613 else {
3614 sky2_write32(hw, STAT_LEV_TIMER_INI,
3615 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3616 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3617 }
3618 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3619
3620 if (ecmd->rx_coalesce_usecs_irq == 0)
3621 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3622 else {
d28d4870 3623 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3624 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3625 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3626 }
3627 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3628 return 0;
3629}
3630
793b883e
SH		 3631static void sky2_get_ringparam(struct net_device *dev,
3632 struct ethtool_ringparam *ering)
3633{
3634 struct sky2_port *sky2 = netdev_priv(dev);
3635
3636 ering->rx_max_pending = RX_MAX_PENDING;
3637 ering->rx_mini_max_pending = 0;
3638 ering->rx_jumbo_max_pending = 0;
3639 ering->tx_max_pending = TX_RING_SIZE - 1;
3640
3641 ering->rx_pending = sky2->rx_pending;
3642 ering->rx_mini_pending = 0;
3643 ering->rx_jumbo_pending = 0;
3644 ering->tx_pending = sky2->tx_pending;
3645}
3646
3647static int sky2_set_ringparam(struct net_device *dev,
3648 struct ethtool_ringparam *ering)
3649{
3650 struct sky2_port *sky2 = netdev_priv(dev);
3651 int err = 0;
3652
3653 if (ering->rx_pending > RX_MAX_PENDING ||
3654 ering->rx_pending < 8 ||
3655 ering->tx_pending < MAX_SKB_TX_LE ||
3656 ering->tx_pending > TX_RING_SIZE - 1)
3657 return -EINVAL;
3658
3659 if (netif_running(dev))
3660 sky2_down(dev);
3661
3662 sky2->rx_pending = ering->rx_pending;
3663 sky2->tx_pending = ering->tx_pending;
3664
1b537565 3665 if (netif_running(dev)) {
793b883e 3666 err = sky2_up(dev);
1b537565
SH		 3667 if (err)
3668 dev_close(dev);
3669 }
793b883e
SH		 3670
3671 return err;
3672}
3673
793b883e
SH		 3674static int sky2_get_regs_len(struct net_device *dev)
3675{
6e4cbb34 3676 return 0x4000;
793b883e
SH		 3677}
3678
3679/*
3680 * Returns copy of control register region
3ead5db7 3681 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3682 */
3683static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3684 void *p)
3685{
3686 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3687 const void __iomem *io = sky2->hw->regs;
295b54c4 3688 unsigned int b;
793b883e
SH		 3689
3690 regs->version = 1;
793b883e 3691
295b54c4
SH		 3692 for (b = 0; b < 128; b++) {
3693 /* This complicated switch statement is to make sure and
3694 * only access regions that are unreserved.
3695 * Some blocks are only valid on dual port cards.
3696 * and block 3 has some special diagnostic registers that
3697 * are poison.
3698 */
3699 switch (b) {
3700 case 3:
3701 /* skip diagnostic ram region */
3702 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3703 break;
3ead5db7 3704
295b54c4
SH		 3705 /* dual port cards only */
3706 case 5: /* Tx Arbiter 2 */
3707 case 9: /* RX2 */
3708 case 14 ... 15: /* TX2 */
3709 case 17: case 19: /* Ram Buffer 2 */
3710 case 22 ... 23: /* Tx Ram Buffer 2 */
3711 case 25: /* Rx MAC Fifo 1 */
3712 case 27: /* Tx MAC Fifo 2 */
3713 case 31: /* GPHY 2 */
3714 case 40 ... 47: /* Pattern Ram 2 */
3715 case 52: case 54: /* TCP Segmentation 2 */
3716 case 112 ... 116: /* GMAC 2 */
3717 if (sky2->hw->ports == 1)
3718 goto reserved;
3719 /* fall through */
3720 case 0: /* Control */
3721 case 2: /* Mac address */
3722 case 4: /* Tx Arbiter 1 */
3723 case 7: /* PCI express reg */
3724 case 8: /* RX1 */
3725 case 12 ... 13: /* TX1 */
3726 case 16: case 18:/* Rx Ram Buffer 1 */
3727 case 20 ... 21: /* Tx Ram Buffer 1 */
3728 case 24: /* Rx MAC Fifo 1 */
3729 case 26: /* Tx MAC Fifo 1 */
3730 case 28 ... 29: /* Descriptor and status unit */
3731 case 30: /* GPHY 1*/
3732 case 32 ... 39: /* Pattern Ram 1 */
3733 case 48: case 50: /* TCP Segmentation 1 */
3734 case 56 ... 60: /* PCI space */
3735 case 80 ... 84: /* GMAC 1 */
3736 memcpy_fromio(p, io, 128);
3737 break;
3738 default:
3739reserved:
3740 memset(p, 0, 128);
3741 }
3ead5db7 3742
295b54c4
SH		 3743 p += 128;
3744 io += 128;
3745 }
793b883e 3746}
cd28ab6a 3747
b628ed98
SH		 3748/* In order to do Jumbo packets on these chips, need to turn off the
3749 * transmit store/forward. Therefore checksum offload won't work.
3750 */
3751static int no_tx_offload(struct net_device *dev)
3752{
3753 const struct sky2_port *sky2 = netdev_priv(dev);
3754 const struct sky2_hw *hw = sky2->hw;
3755
69161611 3756 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3757}
3758
3759static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3760{
3761 if (data && no_tx_offload(dev))
3762 return -EINVAL;
3763
3764 return ethtool_op_set_tx_csum(dev, data);
3765}
3766
3767
3768static int sky2_set_tso(struct net_device *dev, u32 data)
3769{
3770 if (data && no_tx_offload(dev))
3771 return -EINVAL;
3772
3773 return ethtool_op_set_tso(dev, data);
3774}
3775
f4331a6d
SH		 3776static int sky2_get_eeprom_len(struct net_device *dev)
3777{
3778 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3779 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3780 u16 reg2;
3781
b32f40c4 3782 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3783 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3784}
3785
1413235c 3786static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3787{
1413235c 3788 unsigned long start = jiffies;
f4331a6d 3789
1413235c
SH		 3790 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3791 /* Can take up to 10.6 ms for write */
3792 if (time_after(jiffies, start + HZ/4)) {
3793 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3794 return -ETIMEDOUT;
3795 }
3796 mdelay(1);
3797 }
167f53d0 3798
1413235c
SH		 3799 return 0;
3800}
167f53d0 3801
1413235c
SH		 3802static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3803 u16 offset, size_t length)
3804{
3805 int rc = 0;
3806
3807 while (length > 0) {
3808 u32 val;
3809
3810 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3811 rc = sky2_vpd_wait(hw, cap, 0);
3812 if (rc)
3813 break;
3814
3815 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3816
3817 memcpy(data, &val, min(sizeof(val), length));
3818 offset += sizeof(u32);
3819 data += sizeof(u32);
3820 length -= sizeof(u32);
3821 }
3822
3823 return rc;
f4331a6d
SH		 3824}
3825
1413235c
SH		 3826static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3827 u16 offset, unsigned int length)
f4331a6d 3828{
1413235c
SH		 3829 unsigned int i;
3830 int rc = 0;
3831
3832 for (i = 0; i < length; i += sizeof(u32)) {
3833 u32 val = *(u32 *)(data + i);
3834
3835 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3836 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3837
3838 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3839 if (rc)
3840 break;
3841 }
3842 return rc;
f4331a6d
SH		 3843}
3844
3845static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3846 u8 *data)
3847{
3848 struct sky2_port *sky2 = netdev_priv(dev);
3849 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3850
3851 if (!cap)
3852 return -EINVAL;
3853
3854 eeprom->magic = SKY2_EEPROM_MAGIC;
3855
1413235c 3856 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3857}
3858
3859static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3860 u8 *data)
3861{
3862 struct sky2_port *sky2 = netdev_priv(dev);
3863 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3864
3865 if (!cap)
3866 return -EINVAL;
3867
3868 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3869 return -EINVAL;
3870
1413235c
SH		 3871 /* Partial writes not supported */
3872 if ((eeprom->offset & 3) || (eeprom->len & 3))
3873 return -EINVAL;
f4331a6d 3874
1413235c 3875 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3876}
3877
3878
7282d491 3879static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3880 .get_settings = sky2_get_settings,
3881 .set_settings = sky2_set_settings,
3882 .get_drvinfo = sky2_get_drvinfo,
3883 .get_wol = sky2_get_wol,
3884 .set_wol = sky2_set_wol,
3885 .get_msglevel = sky2_get_msglevel,
3886 .set_msglevel = sky2_set_msglevel,
3887 .nway_reset = sky2_nway_reset,
3888 .get_regs_len = sky2_get_regs_len,
3889 .get_regs = sky2_get_regs,
3890 .get_link = ethtool_op_get_link,
3891 .get_eeprom_len = sky2_get_eeprom_len,
3892 .get_eeprom = sky2_get_eeprom,
3893 .set_eeprom = sky2_set_eeprom,
f4331a6d 3894 .set_sg = ethtool_op_set_sg,
f4331a6d 3895 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3896 .set_tso = sky2_set_tso,
3897 .get_rx_csum = sky2_get_rx_csum,
3898 .set_rx_csum = sky2_set_rx_csum,
3899 .get_strings = sky2_get_strings,
3900 .get_coalesce = sky2_get_coalesce,
3901 .set_coalesce = sky2_set_coalesce,
3902 .get_ringparam = sky2_get_ringparam,
3903 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3904 .get_pauseparam = sky2_get_pauseparam,
3905 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3906 .phys_id = sky2_phys_id,
b9f2c044 3907 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3908 .get_ethtool_stats = sky2_get_ethtool_stats,
3909};
3910
3cf26753
SH		 3911#ifdef CONFIG_SKY2_DEBUG
3912
3913static struct dentry *sky2_debug;
3914
e4c2abe2
SH		 3915
3916/*
3917 * Read and parse the first part of Vital Product Data
3918 */
3919#define VPD_SIZE 128
3920#define VPD_MAGIC 0x82
3921
3922static const struct vpd_tag {
3923 char tag[2];
3924 char *label;
3925} vpd_tags[] = {
3926 { "PN", "Part Number" },
3927 { "EC", "Engineering Level" },
3928 { "MN", "Manufacturer" },
3929 { "SN", "Serial Number" },
3930 { "YA", "Asset Tag" },
3931 { "VL", "First Error Log Message" },
3932 { "VF", "Second Error Log Message" },
3933 { "VB", "Boot Agent ROM Configuration" },
3934 { "VE", "EFI UNDI Configuration" },
3935};
3936
3937static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3938{
3939 size_t vpd_size;
3940 loff_t offs;
3941 u8 len;
3942 unsigned char *buf;
3943 u16 reg2;
3944
3945 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3946 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3947
3948 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3949 buf = kmalloc(vpd_size, GFP_KERNEL);
3950 if (!buf) {
3951 seq_puts(seq, "no memory!\n");
3952 return;
3953 }
3954
3955 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
3956 seq_puts(seq, "VPD read failed\n");
3957 goto out;
3958 }
3959
3960 if (buf[0] != VPD_MAGIC) {
3961 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
3962 goto out;
3963 }
3964 len = buf[1];
3965 if (len == 0 || len > vpd_size - 4) {
3966 seq_printf(seq, "Invalid id length: %d\n", len);
3967 goto out;
3968 }
3969
3970 seq_printf(seq, "%.*s\n", len, buf + 3);
3971 offs = len + 3;
3972
3973 while (offs < vpd_size - 4) {
3974 int i;
3975
3976 if (!memcmp("RW", buf + offs, 2)) /* end marker */
3977 break;
3978 len = buf[offs + 2];
3979 if (offs + len + 3 >= vpd_size)
3980 break;
3981
3982 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
3983 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
3984 seq_printf(seq, " %s: %.*s\n",
3985 vpd_tags[i].label, len, buf + offs + 3);
3986 break;
3987 }
3988 }
3989 offs += len + 3;
3990 }
3991out:
3992 kfree(buf);
3993}
3994
3cf26753
SH		 3995static int sky2_debug_show(struct seq_file *seq, void *v)
3996{
3997 struct net_device *dev = seq->private;
3998 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3999 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4000 unsigned port = sky2->port;
4001 unsigned idx, last;
4002 int sop;
4003
e4c2abe2 4004 sky2_show_vpd(seq, hw);
3cf26753 4005
e4c2abe2 4006 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4007 sky2_read32(hw, B0_ISRC),
4008 sky2_read32(hw, B0_IMSK),
4009 sky2_read32(hw, B0_Y2_SP_ICR));
4010
e4c2abe2
SH		 4011 if (!netif_running(dev)) {
4012 seq_printf(seq, "network not running\n");
4013 return 0;
4014 }
4015
bea3348e 4016 napi_disable(&hw->napi);
3cf26753
SH		 4017 last = sky2_read16(hw, STAT_PUT_IDX);
4018
4019 if (hw->st_idx == last)
4020 seq_puts(seq, "Status ring (empty)\n");
4021 else {
4022 seq_puts(seq, "Status ring\n");
4023 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4024 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4025 const struct sky2_status_le *le = hw->st_le + idx;
4026 seq_printf(seq, "[%d] %#x %d %#x\n",
4027 idx, le->opcode, le->length, le->status);
4028 }
4029 seq_puts(seq, "\n");
4030 }
4031
4032 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4033 sky2->tx_cons, sky2->tx_prod,
4034 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4035 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4036
4037 /* Dump contents of tx ring */
4038 sop = 1;
4039 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4040 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4041 const struct sky2_tx_le *le = sky2->tx_le + idx;
4042 u32 a = le32_to_cpu(le->addr);
4043
4044 if (sop)
4045 seq_printf(seq, "%u:", idx);
4046 sop = 0;
4047
4048 switch(le->opcode & ~HW_OWNER) {
4049 case OP_ADDR64:
4050 seq_printf(seq, " %#x:", a);
4051 break;
4052 case OP_LRGLEN:
4053 seq_printf(seq, " mtu=%d", a);
4054 break;
4055 case OP_VLAN:
4056 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4057 break;
4058 case OP_TCPLISW:
4059 seq_printf(seq, " csum=%#x", a);
4060 break;
4061 case OP_LARGESEND:
4062 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4063 break;
4064 case OP_PACKET:
4065 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4066 break;
4067 case OP_BUFFER:
4068 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4069 break;
4070 default:
4071 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4072 a, le16_to_cpu(le->length));
4073 }
4074
4075 if (le->ctrl & EOP) {
4076 seq_putc(seq, '\n');
4077 sop = 1;
4078 }
4079 }
4080
4081 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4082 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4083 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4084 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4085
d1d08d12 4086 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4087 napi_enable(&hw->napi);
3cf26753
SH		 4088 return 0;
4089}
4090
4091static int sky2_debug_open(struct inode *inode, struct file *file)
4092{
4093 return single_open(file, sky2_debug_show, inode->i_private);
4094}
4095
4096static const struct file_operations sky2_debug_fops = {
4097 .owner = THIS_MODULE,
4098 .open = sky2_debug_open,
4099 .read = seq_read,
4100 .llseek = seq_lseek,
4101 .release = single_release,
4102};
4103
4104/*
4105 * Use network device events to create/remove/rename
4106 * debugfs file entries
4107 */
4108static int sky2_device_event(struct notifier_block *unused,
4109 unsigned long event, void *ptr)
4110{
4111 struct net_device *dev = ptr;
5b296bc9 4112 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4113
1436b301 4114 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4115 return NOTIFY_DONE;
3cf26753 4116
5b296bc9
SH		 4117 switch(event) {
4118 case NETDEV_CHANGENAME:
4119 if (sky2->debugfs) {
4120 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4121 sky2_debug, dev->name);
4122 }
4123 break;
3cf26753 4124
5b296bc9
SH		 4125 case NETDEV_GOING_DOWN:
4126 if (sky2->debugfs) {
4127 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4128 dev->name);
4129 debugfs_remove(sky2->debugfs);
4130 sky2->debugfs = NULL;
3cf26753 4131 }
5b296bc9
SH		 4132 break;
4133
4134 case NETDEV_UP:
4135 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4136 sky2_debug, dev,
4137 &sky2_debug_fops);
4138 if (IS_ERR(sky2->debugfs))
4139 sky2->debugfs = NULL;
3cf26753
SH		 4140 }
4141
4142 return NOTIFY_DONE;
4143}
4144
4145static struct notifier_block sky2_notifier = {
4146 .notifier_call = sky2_device_event,
4147};
4148
4149
4150static __init void sky2_debug_init(void)
4151{
4152 struct dentry *ent;
4153
4154 ent = debugfs_create_dir("sky2", NULL);
4155 if (!ent || IS_ERR(ent))
4156 return;
4157
4158 sky2_debug = ent;
4159 register_netdevice_notifier(&sky2_notifier);
4160}
4161
4162static __exit void sky2_debug_cleanup(void)
4163{
4164 if (sky2_debug) {
4165 unregister_netdevice_notifier(&sky2_notifier);
4166 debugfs_remove(sky2_debug);
4167 sky2_debug = NULL;
4168 }
4169}
4170
4171#else
4172#define sky2_debug_init()
4173#define sky2_debug_cleanup()
4174#endif
4175
1436b301
SH		 4176/* Two copies of network device operations to handle special case of
4177 not allowing netpoll on second port */
4178static const struct net_device_ops sky2_netdev_ops[2] = {
4179 {
4180 .ndo_open = sky2_up,
4181 .ndo_stop = sky2_down,
00829823 4182 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4183 .ndo_do_ioctl = sky2_ioctl,
4184 .ndo_validate_addr = eth_validate_addr,
4185 .ndo_set_mac_address = sky2_set_mac_address,
4186 .ndo_set_multicast_list = sky2_set_multicast,
4187 .ndo_change_mtu = sky2_change_mtu,
4188 .ndo_tx_timeout = sky2_tx_timeout,
4189#ifdef SKY2_VLAN_TAG_USED
4190 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4191#endif
4192#ifdef CONFIG_NET_POLL_CONTROLLER
4193 .ndo_poll_controller = sky2_netpoll,
4194#endif
4195 },
4196 {
4197 .ndo_open = sky2_up,
4198 .ndo_stop = sky2_down,
00829823 4199 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4200 .ndo_do_ioctl = sky2_ioctl,
4201 .ndo_validate_addr = eth_validate_addr,
4202 .ndo_set_mac_address = sky2_set_mac_address,
4203 .ndo_set_multicast_list = sky2_set_multicast,
4204 .ndo_change_mtu = sky2_change_mtu,
4205 .ndo_tx_timeout = sky2_tx_timeout,
4206#ifdef SKY2_VLAN_TAG_USED
4207 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4208#endif
4209 },
4210};
3cf26753 4211
cd28ab6a
SH		 4212/* Initialize network device */
4213static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4214 unsigned port,
be63a21c 4215 int highmem, int wol)
cd28ab6a
SH		 4216{
4217 struct sky2_port *sky2;
4218 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4219
4220 if (!dev) {
898eb71c 4221 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4222 return NULL;
4223 }
4224
cd28ab6a 4225 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4226 dev->irq = hw->pdev->irq;
cd28ab6a 4227 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4228 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4229 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4230
4231 sky2 = netdev_priv(dev);
4232 sky2->netdev = dev;
4233 sky2->hw = hw;
4234 sky2->msg_enable = netif_msg_init(debug, default_msg);
4235
cd28ab6a
SH		 4236 /* Auto speed and flow control */
4237 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4238 sky2->flow_mode = FC_BOTH;
4239
cd28ab6a
SH		 4240 sky2->duplex = -1;
4241 sky2->speed = -1;
4242 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4243 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4244 sky2->wol = wol;
75d070c5 4245
e07b1aa8 4246 spin_lock_init(&sky2->phy_lock);
793b883e 4247 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4248 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4249
4250 hw->dev[port] = dev;
4251
4252 sky2->port = port;
4253
4a50a876 4254 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4255 if (highmem)
4256 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4257
d1f13708 4258#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4259 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4260 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4261 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4262 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4263 }
d1f13708
SH		 4264#endif
4265
cd28ab6a 4266 /* read the mac address */
793b883e 4267 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4268 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4269
cd28ab6a
SH		 4270 return dev;
4271}
4272
28bd181a 4273static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4274{
4275 const struct sky2_port *sky2 = netdev_priv(dev);
4276
4277 if (netif_msg_probe(sky2))
e174961c
JB		 4278 printk(KERN_INFO PFX "%s: addr %pM\n",
4279 dev->name, dev->dev_addr);
cd28ab6a
SH		 4280}
4281
fb2690a9 4282/* Handle software interrupt used during MSI test */
7d12e780 4283static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4284{
4285 struct sky2_hw *hw = dev_id;
4286 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4287
4288 if (status == 0)
4289 return IRQ_NONE;
4290
4291 if (status & Y2_IS_IRQ_SW) {
ea76e635 4292 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4293 wake_up(&hw->msi_wait);
4294 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4295 }
4296 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4297
4298 return IRQ_HANDLED;
4299}
4300
4301/* Test interrupt path by forcing a a software IRQ */
4302static int __devinit sky2_test_msi(struct sky2_hw *hw)
4303{
4304 struct pci_dev *pdev = hw->pdev;
4305 int err;
4306
bb507fe1
SH		 4307 init_waitqueue_head (&hw->msi_wait);
4308
fb2690a9
SH		 4309 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4310
b0a20ded 4311 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4312 if (err) {
b02a9258 4313 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4314 return err;
4315 }
4316
fb2690a9 4317 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4318 sky2_read8(hw, B0_CTST);
fb2690a9 4319
ea76e635 4320 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4321
ea76e635 4322 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4323 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4324 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4325 "switching to INTx mode.\n");
fb2690a9
SH		 4326
4327 err = -EOPNOTSUPP;
4328 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4329 }
4330
4331 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4332 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4333
4334 free_irq(pdev->irq, hw);
4335
4336 return err;
4337}
4338
c7127a34
SH		 4339/* This driver supports yukon2 chipset only */
4340static const char *sky2_name(u8 chipid, char *buf, int sz)
4341{
4342 const char *name[] = {
4343 "XL", /* 0xb3 */
4344 "EC Ultra", /* 0xb4 */
4345 "Extreme", /* 0xb5 */
4346 "EC", /* 0xb6 */
4347 "FE", /* 0xb7 */
4348 "FE+", /* 0xb8 */
4349 "Supreme", /* 0xb9 */
0ce8b98d 4350 "UL 2", /* 0xba */
c7127a34
SH		 4351 };
4352
0ce8b98d 4353 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4354 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4355 else
4356 snprintf(buf, sz, "(chip %#x)", chipid);
4357 return buf;
4358}
4359
cd28ab6a
SH		 4360static int __devinit sky2_probe(struct pci_dev *pdev,
4361 const struct pci_device_id *ent)
4362{
7f60c64b 4363 struct net_device *dev;
cd28ab6a 4364 struct sky2_hw *hw;
be63a21c 4365 int err, using_dac = 0, wol_default;
3834507d 4366 u32 reg;
c7127a34 4367 char buf1[16];
cd28ab6a 4368
793b883e
SH		 4369 err = pci_enable_device(pdev);
4370 if (err) {
b02a9258 4371 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4372 goto err_out;
4373 }
4374
6cc90a5a
SH		 4375 /* Get configuration information
4376 * Note: only regular PCI config access once to test for HW issues
4377 * other PCI access through shared memory for speed and to
4378 * avoid MMCONFIG problems.
4379 */
4380 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4381 if (err) {
4382 dev_err(&pdev->dev, "PCI read config failed\n");
4383 goto err_out;
4384 }
4385
4386 if (~reg == 0) {
4387 dev_err(&pdev->dev, "PCI configuration read error\n");
4388 goto err_out;
4389 }
4390
793b883e
SH		 4391 err = pci_request_regions(pdev, DRV_NAME);
4392 if (err) {
b02a9258 4393 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4394 goto err_out_disable;
cd28ab6a
SH		 4395 }
4396
4397 pci_set_master(pdev);
4398
d1f3d4dd 4399 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4400 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4401 using_dac = 1;
6a35528a 4402 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4403 if (err < 0) {
b02a9258
SH		 4404 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4405 "for consistent allocations\n");
d1f3d4dd
SH		 4406 goto err_out_free_regions;
4407 }
d1f3d4dd 4408 } else {
284901a9 4409 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4410 if (err) {
b02a9258 4411 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4412 goto err_out_free_regions;
4413 }
4414 }
d1f3d4dd 4415
3834507d
SH		 4416
4417#ifdef __BIG_ENDIAN
4418 /* The sk98lin vendor driver uses hardware byte swapping but
4419 * this driver uses software swapping.
4420 */
4421 reg &= ~PCI_REV_DESC;
4422 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4423 if (err) {
4424 dev_err(&pdev->dev, "PCI write config failed\n");
4425 goto err_out_free_regions;
4426 }
4427#endif
4428
9d731d77 4429 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4430
cd28ab6a 4431 err = -ENOMEM;
6aad85d6 4432 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4433 if (!hw) {
b02a9258 4434 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4435 goto err_out_free_regions;
4436 }
4437
cd28ab6a 4438 hw->pdev = pdev;
cd28ab6a
SH		 4439
4440 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4441 if (!hw->regs) {
b02a9258 4442 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4443 goto err_out_free_hw;
4444 }
4445
08c06d8a 4446 /* ring for status responses */
167f53d0 4447 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4448 if (!hw->st_le)
4449 goto err_out_iounmap;
4450
e3173832 4451 err = sky2_init(hw);
cd28ab6a 4452 if (err)
793b883e 4453 goto err_out_iounmap;
cd28ab6a 4454
c844d483
SH		 4455 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4456 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4457
e3173832
SH		 4458 sky2_reset(hw);
4459
be63a21c 4460 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4461 if (!dev) {
4462 err = -ENOMEM;
cd28ab6a 4463 goto err_out_free_pci;
7f60c64b 4464 }
cd28ab6a 4465
9fa1b1f3
SH		 4466 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4467 err = sky2_test_msi(hw);
4468 if (err == -EOPNOTSUPP)
4469 pci_disable_msi(pdev);
4470 else if (err)
4471 goto err_out_free_netdev;
4472 }
4473
793b883e
SH		 4474 err = register_netdev(dev);
4475 if (err) {
b02a9258 4476 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4477 goto err_out_free_netdev;
4478 }
4479
6de16237
SH		 4480 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4481
ea76e635
SH		 4482 err = request_irq(pdev->irq, sky2_intr,
4483 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4484 dev->name, hw);
9fa1b1f3 4485 if (err) {
b02a9258 4486 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4487 goto err_out_unregister;
4488 }
4489 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4490 napi_enable(&hw->napi);
9fa1b1f3 4491
cd28ab6a
SH		 4492 sky2_show_addr(dev);
4493
7f60c64b 4494 if (hw->ports > 1) {
4495 struct net_device *dev1;
4496
be63a21c 4497 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4498 if (!dev1)
4499 dev_warn(&pdev->dev, "allocation for second device failed\n");
4500 else if ((err = register_netdev(dev1))) {
4501 dev_warn(&pdev->dev,
4502 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4503 hw->dev[1] = NULL;
4504 free_netdev(dev1);
b02a9258
SH		 4505 } else
4506 sky2_show_addr(dev1);
cd28ab6a
SH		 4507 }
4508
32c2c300 4509 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4510 INIT_WORK(&hw->restart_work, sky2_restart);
4511
793b883e
SH		 4512 pci_set_drvdata(pdev, hw);
4513
cd28ab6a
SH		 4514 return 0;
4515
793b883e 4516err_out_unregister:
ea76e635 4517 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4518 pci_disable_msi(pdev);
793b883e 4519 unregister_netdev(dev);
cd28ab6a
SH		 4520err_out_free_netdev:
4521 free_netdev(dev);
cd28ab6a 4522err_out_free_pci:
793b883e 4523 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4524 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4525err_out_iounmap:
4526 iounmap(hw->regs);
4527err_out_free_hw:
4528 kfree(hw);
4529err_out_free_regions:
4530 pci_release_regions(pdev);
44a1d2e5 4531err_out_disable:
cd28ab6a 4532 pci_disable_device(pdev);
cd28ab6a 4533err_out:
549a68c3 4534 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4535 return err;
4536}
4537
4538static void __devexit sky2_remove(struct pci_dev *pdev)
4539{
793b883e 4540 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4541 int i;
cd28ab6a 4542
793b883e 4543 if (!hw)
cd28ab6a
SH		 4544 return;
4545
32c2c300 4546 del_timer_sync(&hw->watchdog_timer);
6de16237 4547 cancel_work_sync(&hw->restart_work);
d27ed387 4548
b877fe28 4549 for (i = hw->ports-1; i >= 0; --i)
6de16237 4550 unregister_netdev(hw->dev[i]);
81906791 4551
d27ed387 4552 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4553
ae306cca
SH		 4554 sky2_power_aux(hw);
4555
cd28ab6a 4556 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4557 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4558 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4559
4560 free_irq(pdev->irq, hw);
ea76e635 4561 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4562 pci_disable_msi(pdev);
793b883e 4563 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4564 pci_release_regions(pdev);
4565 pci_disable_device(pdev);
793b883e 4566
b877fe28 4567 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4568 free_netdev(hw->dev[i]);
4569
cd28ab6a
SH		 4570 iounmap(hw->regs);
4571 kfree(hw);
5afa0a9c 4572
cd28ab6a
SH		 4573 pci_set_drvdata(pdev, NULL);
4574}
4575
4576#ifdef CONFIG_PM
4577static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4578{
793b883e 4579 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4580 int i, wol = 0;
cd28ab6a 4581
549a68c3
SH		 4582 if (!hw)
4583 return 0;
4584
063a0b38
SH		 4585 del_timer_sync(&hw->watchdog_timer);
4586 cancel_work_sync(&hw->restart_work);
4587
f05267e7 4588 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4589 struct net_device *dev = hw->dev[i];
e3173832 4590 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4591
063a0b38 4592 netif_device_detach(dev);
e3173832 4593 if (netif_running(dev))
5afa0a9c 4594 sky2_down(dev);
e3173832
SH		 4595
4596 if (sky2->wol)
4597 sky2_wol_init(sky2);
4598
4599 wol |= sky2->wol;
cd28ab6a
SH		 4600 }
4601
8ab8fca2 4602 sky2_write32(hw, B0_IMSK, 0);
6de16237 4603 napi_disable(&hw->napi);
ae306cca 4604 sky2_power_aux(hw);
e3173832 4605
d374c1c1 4606 pci_save_state(pdev);
e3173832 4607 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4608 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4609
2ccc99b7 4610 return 0;
cd28ab6a
SH		 4611}
4612
4613static int sky2_resume(struct pci_dev *pdev)
4614{
793b883e 4615 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4616 int i, err;
cd28ab6a 4617
549a68c3
SH		 4618 if (!hw)
4619 return 0;
4620
f71eb1a2
SH		 4621 err = pci_set_power_state(pdev, PCI_D0);
4622 if (err)
4623 goto out;
ae306cca
SH		 4624
4625 err = pci_restore_state(pdev);
4626 if (err)
4627 goto out;
4628
cd28ab6a 4629 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4630
4631 /* Re-enable all clocks */
05745c4a
SH		 4632 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4633 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4634 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4635 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4636
e3173832 4637 sky2_reset(hw);
8ab8fca2 4638 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4639 napi_enable(&hw->napi);
8ab8fca2 4640
f05267e7 4641 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4642 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4643
4644 netif_device_attach(dev);
6a5706b9 4645 if (netif_running(dev)) {
08c06d8a
SH		 4646 err = sky2_up(dev);
4647 if (err) {
4648 printk(KERN_ERR PFX "%s: could not up: %d\n",
4649 dev->name, err);
68c28898 4650 rtnl_lock();
08c06d8a 4651 dev_close(dev);
68c28898 4652 rtnl_unlock();
eb35cf60 4653 goto out;
5afa0a9c 4654 }
cd28ab6a
SH		 4655 }
4656 }
eb35cf60 4657
ae306cca 4658 return 0;
08c06d8a 4659out:
b02a9258 4660 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4661 pci_disable_device(pdev);
08c06d8a 4662 return err;
cd28ab6a
SH		 4663}
4664#endif
4665
e3173832
SH		 4666static void sky2_shutdown(struct pci_dev *pdev)
4667{
4668 struct sky2_hw *hw = pci_get_drvdata(pdev);
4669 int i, wol = 0;
4670
549a68c3
SH		 4671 if (!hw)
4672 return;
4673
5c0d6b34 4674 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4675
4676 for (i = 0; i < hw->ports; i++) {
4677 struct net_device *dev = hw->dev[i];
4678 struct sky2_port *sky2 = netdev_priv(dev);
4679
4680 if (sky2->wol) {
4681 wol = 1;
4682 sky2_wol_init(sky2);
4683 }
4684 }
4685
4686 if (wol)
4687 sky2_power_aux(hw);
4688
4689 pci_enable_wake(pdev, PCI_D3hot, wol);
4690 pci_enable_wake(pdev, PCI_D3cold, wol);
4691
4692 pci_disable_device(pdev);
f71eb1a2 4693 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4694}
4695
cd28ab6a 4696static struct pci_driver sky2_driver = {
793b883e
SH		 4697 .name = DRV_NAME,
4698 .id_table = sky2_id_table,
4699 .probe = sky2_probe,
4700 .remove = __devexit_p(sky2_remove),
cd28ab6a 4701#ifdef CONFIG_PM
793b883e
SH		 4702 .suspend = sky2_suspend,
4703 .resume = sky2_resume,
cd28ab6a 4704#endif
e3173832 4705 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4706};
4707
4708static int __init sky2_init_module(void)
4709{
c844d483
SH		 4710 pr_info(PFX "driver version " DRV_VERSION "\n");
4711
3cf26753 4712 sky2_debug_init();
50241c4c 4713 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4714}
4715
4716static void __exit sky2_cleanup_module(void)
4717{
4718 pci_unregister_driver(&sky2_driver);
3cf26753 4719 sky2_debug_cleanup();
cd28ab6a
SH		 4720}
4721
4722module_init(sky2_init_module);
4723module_exit(sky2_cleanup_module);
4724
4725MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4726MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4727MODULE_LICENSE("GPL");
5f4f9dc1 4728MODULE_VERSION(DRV_VERSION);
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