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Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
cd28ab6a | 26 | #include <linux/config.h> |
793b883e | 27 | #include <linux/crc32.h> |
cd28ab6a SH |
28 | #include <linux/kernel.h> |
29 | #include <linux/version.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/netdevice.h> | |
d0bbccfa | 32 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
33 | #include <linux/etherdevice.h> |
34 | #include <linux/ethtool.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/ip.h> | |
37 | #include <linux/tcp.h> | |
38 | #include <linux/in.h> | |
39 | #include <linux/delay.h> | |
91c86df5 | 40 | #include <linux/workqueue.h> |
d1f13708 | 41 | #include <linux/if_vlan.h> |
d70cd51a | 42 | #include <linux/prefetch.h> |
ef743d33 | 43 | #include <linux/mii.h> |
cd28ab6a SH |
44 | |
45 | #include <asm/irq.h> | |
46 | ||
d1f13708 SH |
47 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
48 | #define SKY2_VLAN_TAG_USED 1 | |
49 | #endif | |
50 | ||
cd28ab6a SH |
51 | #include "sky2.h" |
52 | ||
53 | #define DRV_NAME "sky2" | |
fa8d3549 | 54 | #define DRV_VERSION "0.15" |
cd28ab6a SH |
55 | #define PFX DRV_NAME " " |
56 | ||
57 | /* | |
58 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
59 | * that are organized into three (receive, transmit, status) different rings | |
60 | * similar to Tigon3. A transmit can require several elements; | |
61 | * a receive requires one (or two if using 64 bit dma). | |
62 | */ | |
63 | ||
cd28ab6a | 64 | #define is_ec_a1(hw) \ |
21437643 SH |
65 | unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \ |
66 | (hw)->chip_rev == CHIP_REV_YU_EC_A1) | |
cd28ab6a | 67 | |
13210ce5 | 68 | #define RX_LE_SIZE 512 |
cd28ab6a | 69 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
bea86103 | 70 | #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) |
13210ce5 | 71 | #define RX_DEF_PENDING RX_MAX_PENDING |
82788c7a | 72 | #define RX_SKB_ALIGN 8 |
793b883e SH |
73 | |
74 | #define TX_RING_SIZE 512 | |
75 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
76 | #define TX_MIN_PENDING 64 | |
77 | #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS) | |
cd28ab6a | 78 | |
793b883e | 79 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a SH |
80 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
81 | #define ETH_JUMBO_MTU 9000 | |
82 | #define TX_WATCHDOG (5 * HZ) | |
83 | #define NAPI_WEIGHT 64 | |
84 | #define PHY_RETRIES 1000 | |
85 | ||
86 | static const u32 default_msg = | |
793b883e SH |
87 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
88 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
3be92a70 | 89 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
cd28ab6a | 90 | |
793b883e | 91 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
92 | module_param(debug, int, 0); |
93 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
94 | ||
bdb5c58e SH |
95 | static int copybreak __read_mostly = 256; |
96 | module_param(copybreak, int, 0); | |
97 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
98 | ||
4d52b48b SH |
99 | static int disable_msi = 0; |
100 | module_param(disable_msi, int, 0); | |
101 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
102 | ||
cd28ab6a | 103 | static const struct pci_device_id sky2_id_table[] = { |
793b883e | 104 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
cd28ab6a SH |
105 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
106 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, | |
107 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, | |
108 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | |
5a5b1ea0 | 118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, |
cd28ab6a SH |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, |
120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | |
5a5b1ea0 | 122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, |
cd28ab6a SH |
123 | { 0 } |
124 | }; | |
793b883e | 125 | |
cd28ab6a SH |
126 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
127 | ||
128 | /* Avoid conditionals by using array */ | |
129 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
130 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
131 | ||
92f965e8 SH |
132 | /* This driver supports yukon2 chipset only */ |
133 | static const char *yukon2_name[] = { | |
134 | "XL", /* 0xb3 */ | |
135 | "EC Ultra", /* 0xb4 */ | |
136 | "UNKNOWN", /* 0xb5 */ | |
137 | "EC", /* 0xb6 */ | |
138 | "FE", /* 0xb7 */ | |
793b883e SH |
139 | }; |
140 | ||
793b883e | 141 | /* Access to external PHY */ |
ef743d33 | 142 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
143 | { |
144 | int i; | |
145 | ||
146 | gma_write16(hw, port, GM_SMI_DATA, val); | |
147 | gma_write16(hw, port, GM_SMI_CTRL, | |
148 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
149 | ||
150 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 151 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
ef743d33 | 152 | return 0; |
793b883e | 153 | udelay(1); |
cd28ab6a | 154 | } |
ef743d33 | 155 | |
793b883e | 156 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 157 | return -ETIMEDOUT; |
cd28ab6a SH |
158 | } |
159 | ||
ef743d33 | 160 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
161 | { |
162 | int i; | |
163 | ||
793b883e | 164 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
165 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
166 | ||
167 | for (i = 0; i < PHY_RETRIES; i++) { | |
ef743d33 SH |
168 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { |
169 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
170 | return 0; | |
171 | } | |
172 | ||
793b883e | 173 | udelay(1); |
cd28ab6a SH |
174 | } |
175 | ||
ef743d33 SH |
176 | return -ETIMEDOUT; |
177 | } | |
178 | ||
179 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
180 | { | |
181 | u16 v; | |
182 | ||
183 | if (__gm_phy_read(hw, port, reg, &v) != 0) | |
184 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); | |
185 | return v; | |
cd28ab6a SH |
186 | } |
187 | ||
5afa0a9c SH |
188 | static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) |
189 | { | |
190 | u16 power_control; | |
191 | u32 reg1; | |
192 | int vaux; | |
193 | int ret = 0; | |
194 | ||
195 | pr_debug("sky2_set_power_state %d\n", state); | |
196 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
197 | ||
198 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control); | |
08c06d8a | 199 | vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && |
5afa0a9c SH |
200 | (power_control & PCI_PM_CAP_PME_D3cold); |
201 | ||
202 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control); | |
203 | ||
204 | power_control |= PCI_PM_CTRL_PME_STATUS; | |
205 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); | |
206 | ||
207 | switch (state) { | |
208 | case PCI_D0: | |
209 | /* switch power to VCC (WA for VAUX problem) */ | |
210 | sky2_write8(hw, B0_POWER_CTRL, | |
211 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
212 | ||
213 | /* disable Core Clock Division, */ | |
214 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
215 | ||
216 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
217 | /* enable bits are inverted */ | |
218 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
219 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
220 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
221 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
222 | else | |
223 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
224 | ||
225 | /* Turn off phy power saving */ | |
226 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
227 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
228 | ||
d571b694 | 229 | /* looks like this XL is back asswards .. */ |
5afa0a9c SH |
230 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { |
231 | reg1 |= PCI_Y2_PHY1_COMA; | |
232 | if (hw->ports > 1) | |
233 | reg1 |= PCI_Y2_PHY2_COMA; | |
234 | } | |
235 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | |
236 | break; | |
237 | ||
238 | case PCI_D3hot: | |
239 | case PCI_D3cold: | |
240 | /* Turn on phy power saving */ | |
241 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
242 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
243 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
244 | else | |
245 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
246 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | |
247 | ||
248 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
249 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
250 | else | |
251 | /* enable bits are inverted */ | |
252 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
253 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
254 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
255 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
256 | ||
257 | /* switch power to VAUX */ | |
258 | if (vaux && state != PCI_D3cold) | |
259 | sky2_write8(hw, B0_POWER_CTRL, | |
260 | (PC_VAUX_ENA | PC_VCC_ENA | | |
261 | PC_VAUX_ON | PC_VCC_OFF)); | |
262 | break; | |
263 | default: | |
264 | printk(KERN_ERR PFX "Unknown power state %d\n", state); | |
265 | ret = -1; | |
266 | } | |
267 | ||
268 | pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control); | |
269 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
270 | return ret; | |
271 | } | |
272 | ||
cd28ab6a SH |
273 | static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) |
274 | { | |
275 | u16 reg; | |
276 | ||
277 | /* disable all GMAC IRQ's */ | |
278 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
279 | /* disable PHY IRQs */ | |
280 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 281 | |
cd28ab6a SH |
282 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
283 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
284 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
285 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
286 | ||
287 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
288 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
289 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
290 | } | |
291 | ||
292 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |
293 | { | |
294 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
793b883e | 295 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; |
cd28ab6a | 296 | |
793b883e | 297 | if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) { |
cd28ab6a SH |
298 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
299 | ||
300 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 301 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
302 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
303 | ||
304 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
305 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; | |
306 | else | |
307 | ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); | |
308 | ||
309 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
310 | } | |
311 | ||
312 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
313 | if (hw->copper) { | |
314 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
315 | /* enable automatic crossover */ | |
316 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
317 | } else { | |
318 | /* disable energy detect */ | |
319 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
320 | ||
321 | /* enable automatic crossover */ | |
322 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
323 | ||
324 | if (sky2->autoneg == AUTONEG_ENABLE && | |
325 | hw->chip_id == CHIP_ID_YUKON_XL) { | |
326 | ctrl &= ~PHY_M_PC_DSC_MSK; | |
327 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
328 | } | |
329 | } | |
330 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
331 | } else { | |
332 | /* workaround for deviation #4.88 (CRC errors) */ | |
333 | /* disable Automatic Crossover */ | |
334 | ||
335 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
336 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
337 | ||
338 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | |
339 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | |
340 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
341 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
342 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
343 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
344 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
345 | ||
346 | /* select page 1 to access Fiber registers */ | |
347 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
348 | } | |
cd28ab6a SH |
349 | } |
350 | ||
351 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
352 | if (sky2->autoneg == AUTONEG_DISABLE) | |
353 | ctrl &= ~PHY_CT_ANE; | |
354 | else | |
355 | ctrl |= PHY_CT_ANE; | |
356 | ||
357 | ctrl |= PHY_CT_RESET; | |
358 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
359 | ||
360 | ctrl = 0; | |
361 | ct1000 = 0; | |
362 | adv = PHY_AN_CSMA; | |
363 | ||
364 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
365 | if (hw->copper) { | |
366 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
367 | ct1000 |= PHY_M_1000C_AFD; | |
368 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
369 | ct1000 |= PHY_M_1000C_AHD; | |
370 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
371 | adv |= PHY_M_AN_100_FD; | |
372 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
373 | adv |= PHY_M_AN_100_HD; | |
374 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
375 | adv |= PHY_M_AN_10_FD; | |
376 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
377 | adv |= PHY_M_AN_10_HD; | |
793b883e | 378 | } else /* special defines for FIBER (88E1011S only) */ |
cd28ab6a SH |
379 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
380 | ||
381 | /* Set Flow-control capabilities */ | |
382 | if (sky2->tx_pause && sky2->rx_pause) | |
793b883e | 383 | adv |= PHY_AN_PAUSE_CAP; /* symmetric */ |
cd28ab6a | 384 | else if (sky2->rx_pause && !sky2->tx_pause) |
793b883e | 385 | adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; |
cd28ab6a SH |
386 | else if (!sky2->rx_pause && sky2->tx_pause) |
387 | adv |= PHY_AN_PAUSE_ASYM; /* local */ | |
388 | ||
389 | /* Restart Auto-negotiation */ | |
390 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
391 | } else { | |
392 | /* forced speed/duplex settings */ | |
393 | ct1000 = PHY_M_1000C_MSE; | |
394 | ||
395 | if (sky2->duplex == DUPLEX_FULL) | |
396 | ctrl |= PHY_CT_DUP_MD; | |
397 | ||
398 | switch (sky2->speed) { | |
399 | case SPEED_1000: | |
400 | ctrl |= PHY_CT_SP1000; | |
401 | break; | |
402 | case SPEED_100: | |
403 | ctrl |= PHY_CT_SP100; | |
404 | break; | |
405 | } | |
406 | ||
407 | ctrl |= PHY_CT_RESET; | |
408 | } | |
409 | ||
410 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
411 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
412 | ||
413 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
414 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
415 | ||
416 | /* Setup Phy LED's */ | |
417 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
418 | ledover = 0; | |
419 | ||
420 | switch (hw->chip_id) { | |
421 | case CHIP_ID_YUKON_FE: | |
422 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
423 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
424 | ||
425 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
426 | ||
427 | /* delete ACT LED control bits */ | |
428 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
429 | /* change ACT LED control to blink mode */ | |
430 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
431 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
432 | break; | |
433 | ||
434 | case CHIP_ID_YUKON_XL: | |
793b883e | 435 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
436 | |
437 | /* select page 3 to access LED control register */ | |
438 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
439 | ||
440 | /* set LED Function Control register */ | |
793b883e SH |
441 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ |
442 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
443 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
444 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
445 | |
446 | /* set Polarity Control register */ | |
447 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
448 | (PHY_M_POLC_LS1_P_MIX(4) | |
449 | PHY_M_POLC_IS0_P_MIX(4) | | |
450 | PHY_M_POLC_LOS_CTRL(2) | | |
451 | PHY_M_POLC_INIT_CTRL(2) | | |
452 | PHY_M_POLC_STA1_CTRL(2) | | |
453 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
454 | |
455 | /* restore page register */ | |
793b883e | 456 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a SH |
457 | break; |
458 | ||
459 | default: | |
460 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
461 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
462 | /* turn off the Rx LED (LED_RX) */ | |
463 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
464 | } | |
465 | ||
466 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
467 | ||
468 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { | |
469 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
470 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
471 | } | |
472 | ||
473 | if (ledover) | |
474 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
475 | ||
d571b694 | 476 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
cd28ab6a SH |
477 | if (sky2->autoneg == AUTONEG_ENABLE) |
478 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
479 | else | |
480 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
481 | } | |
482 | ||
1b537565 SH |
483 | /* Force a renegotiation */ |
484 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
485 | { | |
486 | down(&sky2->phy_sema); | |
487 | sky2_phy_init(sky2->hw, sky2->port); | |
488 | up(&sky2->phy_sema); | |
489 | } | |
490 | ||
cd28ab6a SH |
491 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
492 | { | |
493 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
494 | u16 reg; | |
495 | int i; | |
496 | const u8 *addr = hw->dev[port]->dev_addr; | |
497 | ||
42eeea01 SH |
498 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
499 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); | |
cd28ab6a SH |
500 | |
501 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
502 | ||
793b883e | 503 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
504 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
505 | /* clear GMAC 1 Control reset */ | |
506 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
507 | do { | |
508 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
509 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
510 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
511 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
512 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
513 | } | |
514 | ||
cd28ab6a SH |
515 | if (sky2->autoneg == AUTONEG_DISABLE) { |
516 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
517 | reg |= GM_GPCR_AU_ALL_DIS; | |
518 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
519 | gma_read16(hw, port, GM_GP_CTRL); | |
520 | ||
cd28ab6a SH |
521 | switch (sky2->speed) { |
522 | case SPEED_1000: | |
6f4c56b2 | 523 | reg &= ~GM_GPCR_SPEED_100; |
cd28ab6a | 524 | reg |= GM_GPCR_SPEED_1000; |
6f4c56b2 | 525 | break; |
cd28ab6a | 526 | case SPEED_100: |
6f4c56b2 | 527 | reg &= ~GM_GPCR_SPEED_1000; |
cd28ab6a | 528 | reg |= GM_GPCR_SPEED_100; |
6f4c56b2 SH |
529 | break; |
530 | case SPEED_10: | |
531 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
532 | break; | |
cd28ab6a SH |
533 | } |
534 | ||
535 | if (sky2->duplex == DUPLEX_FULL) | |
536 | reg |= GM_GPCR_DUP_FULL; | |
537 | } else | |
538 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
539 | ||
540 | if (!sky2->tx_pause && !sky2->rx_pause) { | |
541 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e SH |
542 | reg |= |
543 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
544 | } else if (sky2->tx_pause && !sky2->rx_pause) { | |
cd28ab6a SH |
545 | /* disable Rx flow-control */ |
546 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
547 | } | |
548 | ||
549 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
550 | ||
793b883e | 551 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 552 | |
91c86df5 | 553 | down(&sky2->phy_sema); |
cd28ab6a | 554 | sky2_phy_init(hw, port); |
91c86df5 | 555 | up(&sky2->phy_sema); |
cd28ab6a SH |
556 | |
557 | /* MIB clear */ | |
558 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
559 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
560 | ||
561 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
793b883e | 562 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i); |
cd28ab6a SH |
563 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
564 | ||
565 | /* transmit control */ | |
566 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
567 | ||
568 | /* receive control reg: unicast + multicast + no FCS */ | |
569 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 570 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
571 | |
572 | /* transmit flow control */ | |
573 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
574 | ||
575 | /* transmit parameter */ | |
576 | gma_write16(hw, port, GM_TX_PARAM, | |
577 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
578 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
579 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
580 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
581 | ||
582 | /* serial mode register */ | |
583 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 584 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 585 | |
6b1a3aef | 586 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
587 | reg |= GM_SMOD_JUMBO_ENA; |
588 | ||
589 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
590 | ||
cd28ab6a SH |
591 | /* virtual address for data */ |
592 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
593 | ||
793b883e SH |
594 | /* physical address: used for pause frames */ |
595 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
596 | ||
597 | /* ignore counter overflows */ | |
cd28ab6a SH |
598 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
599 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
600 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
601 | ||
602 | /* Configure Rx MAC FIFO */ | |
603 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
793b883e | 604 | sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T), |
d1f13708 | 605 | GMF_RX_CTRL_DEF); |
cd28ab6a | 606 | |
d571b694 | 607 | /* Flush Rx MAC FIFO on any flow control or error */ |
42eeea01 | 608 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
cd28ab6a | 609 | |
793b883e SH |
610 | /* Set threshold to 0xa (64 bytes) |
611 | * ASF disabled so no need to do WA dev #4.30 | |
cd28ab6a SH |
612 | */ |
613 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
614 | ||
615 | /* Configure Tx MAC FIFO */ | |
616 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
617 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 SH |
618 | |
619 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
620 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); | |
621 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); | |
622 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | |
623 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
624 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); | |
625 | /* Disable Store & Forward mode for TX */ | |
626 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); | |
627 | } | |
628 | } | |
629 | ||
cd28ab6a SH |
630 | } |
631 | ||
1c28f6ba SH |
632 | /* Assign Ram Buffer allocation. |
633 | * start and end are in units of 4k bytes | |
634 | * ram registers are in units of 64bit words | |
635 | */ | |
636 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) | |
cd28ab6a | 637 | { |
1c28f6ba | 638 | u32 start, end; |
cd28ab6a | 639 | |
1c28f6ba SH |
640 | start = startk * 4096/8; |
641 | end = (endk * 4096/8) - 1; | |
793b883e | 642 | |
cd28ab6a SH |
643 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
644 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
645 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
646 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
647 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
648 | ||
649 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba SH |
650 | u32 space = (endk - startk) * 4096/8; |
651 | u32 tp = space - space/4; | |
793b883e | 652 | |
1c28f6ba SH |
653 | /* On receive queue's set the thresholds |
654 | * give receiver priority when > 3/4 full | |
655 | * send pause when down to 2K | |
656 | */ | |
657 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
658 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 659 | |
1c28f6ba SH |
660 | tp = space - 2048/8; |
661 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); | |
662 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
663 | } else { |
664 | /* Enable store & forward on Tx queue's because | |
665 | * Tx FIFO is only 1K on Yukon | |
666 | */ | |
667 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
668 | } | |
669 | ||
670 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 671 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
672 | } |
673 | ||
cd28ab6a | 674 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 675 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
676 | { |
677 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
678 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
679 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 680 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
681 | } |
682 | ||
cd28ab6a SH |
683 | /* Setup prefetch unit registers. This is the interface between |
684 | * hardware and driver list elements | |
685 | */ | |
8cc048e3 | 686 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
cd28ab6a SH |
687 | u64 addr, u32 last) |
688 | { | |
cd28ab6a SH |
689 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
690 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
691 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
692 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
693 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
694 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
695 | |
696 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
697 | } |
698 | ||
793b883e SH |
699 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
700 | { | |
701 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
702 | ||
703 | sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE; | |
704 | return le; | |
705 | } | |
cd28ab6a SH |
706 | |
707 | /* | |
d571b694 | 708 | * This is a workaround code taken from SysKonnect sk98lin driver |
793b883e | 709 | * to deal with chip bug on Yukon EC rev 0 in the wraparound case. |
cd28ab6a | 710 | */ |
28bd181a | 711 | static void sky2_put_idx(struct sky2_hw *hw, unsigned q, |
cd28ab6a | 712 | u16 idx, u16 *last, u16 size) |
cd28ab6a | 713 | { |
762c2de2 | 714 | wmb(); |
cd28ab6a SH |
715 | if (is_ec_a1(hw) && idx < *last) { |
716 | u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); | |
717 | ||
718 | if (hwget == 0) { | |
719 | /* Start prefetching again */ | |
793b883e | 720 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0); |
cd28ab6a SH |
721 | goto setnew; |
722 | } | |
723 | ||
793b883e | 724 | if (hwget == size - 1) { |
cd28ab6a SH |
725 | /* set watermark to one list element */ |
726 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8); | |
727 | ||
728 | /* set put index to first list element */ | |
729 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0); | |
793b883e SH |
730 | } else /* have hardware go to end of list */ |
731 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), | |
732 | size - 1); | |
cd28ab6a | 733 | } else { |
793b883e | 734 | setnew: |
cd28ab6a | 735 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
cd28ab6a | 736 | } |
bea86103 | 737 | *last = idx; |
762c2de2 | 738 | mmiowb(); |
cd28ab6a SH |
739 | } |
740 | ||
793b883e | 741 | |
cd28ab6a SH |
742 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
743 | { | |
744 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
745 | sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE; | |
746 | return le; | |
747 | } | |
748 | ||
a018e330 SH |
749 | /* Return high part of DMA address (could be 32 or 64 bit) */ |
750 | static inline u32 high32(dma_addr_t a) | |
751 | { | |
a036119f | 752 | return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0; |
a018e330 SH |
753 | } |
754 | ||
793b883e | 755 | /* Build description to hardware about buffer */ |
28bd181a | 756 | static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map) |
cd28ab6a SH |
757 | { |
758 | struct sky2_rx_le *le; | |
734d1868 SH |
759 | u32 hi = high32(map); |
760 | u16 len = sky2->rx_bufsize; | |
cd28ab6a | 761 | |
793b883e | 762 | if (sky2->rx_addr64 != hi) { |
cd28ab6a | 763 | le = sky2_next_rx(sky2); |
793b883e | 764 | le->addr = cpu_to_le32(hi); |
cd28ab6a SH |
765 | le->ctrl = 0; |
766 | le->opcode = OP_ADDR64 | HW_OWNER; | |
734d1868 | 767 | sky2->rx_addr64 = high32(map + len); |
cd28ab6a | 768 | } |
793b883e | 769 | |
cd28ab6a | 770 | le = sky2_next_rx(sky2); |
734d1868 SH |
771 | le->addr = cpu_to_le32((u32) map); |
772 | le->length = cpu_to_le16(len); | |
cd28ab6a SH |
773 | le->ctrl = 0; |
774 | le->opcode = OP_PACKET | HW_OWNER; | |
775 | } | |
776 | ||
793b883e | 777 | |
cd28ab6a SH |
778 | /* Tell chip where to start receive checksum. |
779 | * Actually has two checksums, but set both same to avoid possible byte | |
780 | * order problems. | |
781 | */ | |
793b883e | 782 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a SH |
783 | { |
784 | struct sky2_rx_le *le; | |
785 | ||
cd28ab6a | 786 | le = sky2_next_rx(sky2); |
793b883e | 787 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; |
cd28ab6a SH |
788 | le->ctrl = 0; |
789 | le->opcode = OP_TCPSTART | HW_OWNER; | |
793b883e | 790 | |
793b883e SH |
791 | sky2_write32(sky2->hw, |
792 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
793 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
794 | |
795 | } | |
796 | ||
6b1a3aef SH |
797 | /* |
798 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
799 | * reach the end of packet and since we can't make sure that we have | |
800 | * incoming data, we must reset the BMU while it is not doing a DMA | |
801 | * transfer. Since it is possible that the RX path is still active, | |
802 | * the RX RAM buffer will be stopped first, so any possible incoming | |
803 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
804 | * BMU is polled until any DMA in progress is ended and only then it | |
805 | * will be reset. | |
806 | */ | |
807 | static void sky2_rx_stop(struct sky2_port *sky2) | |
808 | { | |
809 | struct sky2_hw *hw = sky2->hw; | |
810 | unsigned rxq = rxqaddr[sky2->port]; | |
811 | int i; | |
812 | ||
813 | /* disable the RAM Buffer receive queue */ | |
814 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
815 | ||
816 | for (i = 0; i < 0xffff; i++) | |
817 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
818 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
819 | goto stopped; | |
820 | ||
821 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
822 | sky2->netdev->name); | |
823 | stopped: | |
824 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
825 | ||
826 | /* reset the Rx prefetch unit */ | |
827 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
828 | } | |
793b883e | 829 | |
d571b694 | 830 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
831 | static void sky2_rx_clean(struct sky2_port *sky2) |
832 | { | |
833 | unsigned i; | |
834 | ||
835 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 836 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a SH |
837 | struct ring_info *re = sky2->rx_ring + i; |
838 | ||
839 | if (re->skb) { | |
793b883e | 840 | pci_unmap_single(sky2->hw->pdev, |
734d1868 | 841 | re->mapaddr, sky2->rx_bufsize, |
cd28ab6a SH |
842 | PCI_DMA_FROMDEVICE); |
843 | kfree_skb(re->skb); | |
844 | re->skb = NULL; | |
845 | } | |
846 | } | |
847 | } | |
848 | ||
ef743d33 SH |
849 | /* Basic MII support */ |
850 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
851 | { | |
852 | struct mii_ioctl_data *data = if_mii(ifr); | |
853 | struct sky2_port *sky2 = netdev_priv(dev); | |
854 | struct sky2_hw *hw = sky2->hw; | |
855 | int err = -EOPNOTSUPP; | |
856 | ||
857 | if (!netif_running(dev)) | |
858 | return -ENODEV; /* Phy still in reset */ | |
859 | ||
860 | switch(cmd) { | |
861 | case SIOCGMIIPHY: | |
862 | data->phy_id = PHY_ADDR_MARV; | |
863 | ||
864 | /* fallthru */ | |
865 | case SIOCGMIIREG: { | |
866 | u16 val = 0; | |
91c86df5 SH |
867 | |
868 | down(&sky2->phy_sema); | |
ef743d33 | 869 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
91c86df5 SH |
870 | up(&sky2->phy_sema); |
871 | ||
ef743d33 SH |
872 | data->val_out = val; |
873 | break; | |
874 | } | |
875 | ||
876 | case SIOCSMIIREG: | |
877 | if (!capable(CAP_NET_ADMIN)) | |
878 | return -EPERM; | |
879 | ||
91c86df5 | 880 | down(&sky2->phy_sema); |
ef743d33 SH |
881 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
882 | data->val_in); | |
91c86df5 | 883 | up(&sky2->phy_sema); |
ef743d33 SH |
884 | break; |
885 | } | |
886 | return err; | |
887 | } | |
888 | ||
d1f13708 SH |
889 | #ifdef SKY2_VLAN_TAG_USED |
890 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
891 | { | |
892 | struct sky2_port *sky2 = netdev_priv(dev); | |
893 | struct sky2_hw *hw = sky2->hw; | |
894 | u16 port = sky2->port; | |
d1f13708 | 895 | |
302d1252 | 896 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 SH |
897 | |
898 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); | |
899 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); | |
900 | sky2->vlgrp = grp; | |
901 | ||
302d1252 | 902 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 SH |
903 | } |
904 | ||
905 | static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
906 | { | |
907 | struct sky2_port *sky2 = netdev_priv(dev); | |
908 | struct sky2_hw *hw = sky2->hw; | |
909 | u16 port = sky2->port; | |
d1f13708 | 910 | |
302d1252 | 911 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 SH |
912 | |
913 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); | |
914 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); | |
915 | if (sky2->vlgrp) | |
916 | sky2->vlgrp->vlan_devices[vid] = NULL; | |
917 | ||
302d1252 | 918 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 SH |
919 | } |
920 | #endif | |
921 | ||
82788c7a SH |
922 | /* |
923 | * It appears the hardware has a bug in the FIFO logic that | |
924 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
925 | * is not aligned. ALso alloc_skb() won't align properly if slab | |
926 | * debugging is enabled. | |
927 | */ | |
928 | static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask) | |
929 | { | |
930 | struct sk_buff *skb; | |
931 | ||
932 | skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask); | |
933 | if (likely(skb)) { | |
934 | unsigned long p = (unsigned long) skb->data; | |
935 | skb_reserve(skb, | |
936 | ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p); | |
937 | } | |
938 | ||
939 | return skb; | |
940 | } | |
941 | ||
cd28ab6a SH |
942 | /* |
943 | * Allocate and setup receiver buffer pool. | |
944 | * In case of 64 bit dma, there are 2X as many list elements | |
945 | * available as ring entries | |
946 | * and need to reserve one list element so we don't wrap around. | |
947 | */ | |
6b1a3aef | 948 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 949 | { |
6b1a3aef | 950 | struct sky2_hw *hw = sky2->hw; |
6b1a3aef SH |
951 | unsigned rxq = rxqaddr[sky2->port]; |
952 | int i; | |
cd28ab6a | 953 | |
6b1a3aef | 954 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 955 | sky2_qset(hw, rxq); |
6b1a3aef SH |
956 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
957 | ||
958 | rx_set_checksum(sky2); | |
793b883e | 959 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a | 960 | struct ring_info *re = sky2->rx_ring + i; |
cd28ab6a | 961 | |
82788c7a | 962 | re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL); |
cd28ab6a SH |
963 | if (!re->skb) |
964 | goto nomem; | |
965 | ||
6b1a3aef | 966 | re->mapaddr = pci_map_single(hw->pdev, re->skb->data, |
734d1868 SH |
967 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
968 | sky2_rx_add(sky2, re->mapaddr); | |
cd28ab6a SH |
969 | } |
970 | ||
6b1a3aef SH |
971 | /* Tell chip about available buffers */ |
972 | sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); | |
973 | sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX)); | |
cd28ab6a SH |
974 | return 0; |
975 | nomem: | |
976 | sky2_rx_clean(sky2); | |
977 | return -ENOMEM; | |
978 | } | |
979 | ||
980 | /* Bring up network interface. */ | |
981 | static int sky2_up(struct net_device *dev) | |
982 | { | |
983 | struct sky2_port *sky2 = netdev_priv(dev); | |
984 | struct sky2_hw *hw = sky2->hw; | |
985 | unsigned port = sky2->port; | |
986 | u32 ramsize, rxspace; | |
987 | int err = -ENOMEM; | |
988 | ||
989 | if (netif_msg_ifup(sky2)) | |
990 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
991 | ||
992 | /* must be power of 2 */ | |
993 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
994 | TX_RING_SIZE * |
995 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
996 | &sky2->tx_le_map); |
997 | if (!sky2->tx_le) | |
998 | goto err_out; | |
999 | ||
6cdbbdf3 | 1000 | sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), |
cd28ab6a SH |
1001 | GFP_KERNEL); |
1002 | if (!sky2->tx_ring) | |
1003 | goto err_out; | |
1004 | sky2->tx_prod = sky2->tx_cons = 0; | |
cd28ab6a SH |
1005 | |
1006 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
1007 | &sky2->rx_le_map); | |
1008 | if (!sky2->rx_le) | |
1009 | goto err_out; | |
1010 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1011 | ||
6cdbbdf3 | 1012 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info), |
cd28ab6a SH |
1013 | GFP_KERNEL); |
1014 | if (!sky2->rx_ring) | |
1015 | goto err_out; | |
1016 | ||
1017 | sky2_mac_init(hw, port); | |
1018 | ||
1c28f6ba SH |
1019 | /* Determine available ram buffer space (in 4K blocks). |
1020 | * Note: not sure about the FE setting below yet | |
1021 | */ | |
1022 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
1023 | ramsize = 4; | |
1024 | else | |
1025 | ramsize = sky2_read8(hw, B2_E_0); | |
1026 | ||
1027 | /* Give transmitter one third (rounded up) */ | |
1028 | rxspace = ramsize - (ramsize + 2) / 3; | |
cd28ab6a | 1029 | |
cd28ab6a | 1030 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1c28f6ba | 1031 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize); |
cd28ab6a | 1032 | |
793b883e SH |
1033 | /* Make sure SyncQ is disabled */ |
1034 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1035 | RB_RST_SET); | |
1036 | ||
af4ed7e6 | 1037 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 SH |
1038 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) |
1039 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | |
1040 | ||
1041 | ||
6b1a3aef SH |
1042 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1043 | TX_RING_SIZE - 1); | |
cd28ab6a | 1044 | |
6b1a3aef | 1045 | err = sky2_rx_start(sky2); |
cd28ab6a SH |
1046 | if (err) |
1047 | goto err_out; | |
1048 | ||
cd28ab6a SH |
1049 | /* Enable interrupts from phy/mac for port */ |
1050 | hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; | |
1051 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1052 | return 0; | |
1053 | ||
1054 | err_out: | |
1b537565 | 1055 | if (sky2->rx_le) { |
cd28ab6a SH |
1056 | pci_free_consistent(hw->pdev, RX_LE_BYTES, |
1057 | sky2->rx_le, sky2->rx_le_map); | |
1b537565 SH |
1058 | sky2->rx_le = NULL; |
1059 | } | |
1060 | if (sky2->tx_le) { | |
cd28ab6a SH |
1061 | pci_free_consistent(hw->pdev, |
1062 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1063 | sky2->tx_le, sky2->tx_le_map); | |
1b537565 SH |
1064 | sky2->tx_le = NULL; |
1065 | } | |
1066 | kfree(sky2->tx_ring); | |
1067 | kfree(sky2->rx_ring); | |
cd28ab6a | 1068 | |
1b537565 SH |
1069 | sky2->tx_ring = NULL; |
1070 | sky2->rx_ring = NULL; | |
cd28ab6a SH |
1071 | return err; |
1072 | } | |
1073 | ||
793b883e SH |
1074 | /* Modular subtraction in ring */ |
1075 | static inline int tx_dist(unsigned tail, unsigned head) | |
1076 | { | |
129372d0 | 1077 | return (head - tail) % TX_RING_SIZE; |
793b883e | 1078 | } |
cd28ab6a | 1079 | |
793b883e SH |
1080 | /* Number of list elements available for next tx */ |
1081 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1082 | { |
793b883e | 1083 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
1084 | } |
1085 | ||
793b883e | 1086 | /* Estimate of number of transmit list elements required */ |
28bd181a | 1087 | static unsigned tx_le_req(const struct sk_buff *skb) |
cd28ab6a | 1088 | { |
793b883e SH |
1089 | unsigned count; |
1090 | ||
1091 | count = sizeof(dma_addr_t) / sizeof(u32); | |
1092 | count += skb_shinfo(skb)->nr_frags * count; | |
1093 | ||
1094 | if (skb_shinfo(skb)->tso_size) | |
1095 | ++count; | |
1096 | ||
0e3ff6aa | 1097 | if (skb->ip_summed == CHECKSUM_HW) |
793b883e SH |
1098 | ++count; |
1099 | ||
1100 | return count; | |
cd28ab6a SH |
1101 | } |
1102 | ||
793b883e SH |
1103 | /* |
1104 | * Put one packet in ring for transmit. | |
1105 | * A single packet can generate multiple list elements, and | |
1106 | * the number of ring elements will probably be less than the number | |
1107 | * of list elements used. | |
f2e46561 SH |
1108 | * |
1109 | * No BH disabling for tx_lock here (like tg3) | |
793b883e | 1110 | */ |
cd28ab6a SH |
1111 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
1112 | { | |
1113 | struct sky2_port *sky2 = netdev_priv(dev); | |
1114 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1115 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1116 | struct tx_ring_info *re; |
cd28ab6a SH |
1117 | unsigned i, len; |
1118 | dma_addr_t mapping; | |
1119 | u32 addr64; | |
1120 | u16 mss; | |
1121 | u8 ctrl; | |
1122 | ||
302d1252 SH |
1123 | /* No BH disabling for tx_lock here. We are running in BH disabled |
1124 | * context and TX reclaim runs via poll inside of a software | |
1125 | * interrupt, and no related locks in IRQ processing. | |
1126 | */ | |
f2e46561 | 1127 | if (!spin_trylock(&sky2->tx_lock)) |
cd28ab6a SH |
1128 | return NETDEV_TX_LOCKED; |
1129 | ||
793b883e | 1130 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { |
8c463ef7 SH |
1131 | /* There is a known but harmless race with lockless tx |
1132 | * and netif_stop_queue. | |
1133 | */ | |
1134 | if (!netif_queue_stopped(dev)) { | |
1135 | netif_stop_queue(dev); | |
3be92a70 SH |
1136 | if (net_ratelimit()) |
1137 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
1138 | dev->name); | |
8c463ef7 | 1139 | } |
f2e46561 | 1140 | spin_unlock(&sky2->tx_lock); |
cd28ab6a | 1141 | |
cd28ab6a SH |
1142 | return NETDEV_TX_BUSY; |
1143 | } | |
1144 | ||
793b883e | 1145 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
1146 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
1147 | dev->name, sky2->tx_prod, skb->len); | |
1148 | ||
cd28ab6a SH |
1149 | len = skb_headlen(skb); |
1150 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
a018e330 | 1151 | addr64 = high32(mapping); |
793b883e SH |
1152 | |
1153 | re = sky2->tx_ring + sky2->tx_prod; | |
1154 | ||
a018e330 SH |
1155 | /* Send high bits if changed or crosses boundary */ |
1156 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { | |
793b883e SH |
1157 | le = get_tx_le(sky2); |
1158 | le->tx.addr = cpu_to_le32(addr64); | |
1159 | le->ctrl = 0; | |
1160 | le->opcode = OP_ADDR64 | HW_OWNER; | |
a018e330 | 1161 | sky2->tx_addr64 = high32(mapping + len); |
793b883e | 1162 | } |
cd28ab6a SH |
1163 | |
1164 | /* Check for TCP Segmentation Offload */ | |
1165 | mss = skb_shinfo(skb)->tso_size; | |
793b883e | 1166 | if (mss != 0) { |
cd28ab6a SH |
1167 | /* just drop the packet if non-linear expansion fails */ |
1168 | if (skb_header_cloned(skb) && | |
1169 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
793b883e SH |
1170 | dev_kfree_skb_any(skb); |
1171 | goto out_unlock; | |
cd28ab6a SH |
1172 | } |
1173 | ||
1174 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ | |
1175 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | |
1176 | mss += ETH_HLEN; | |
793b883e | 1177 | } |
cd28ab6a | 1178 | |
793b883e | 1179 | if (mss != sky2->tx_last_mss) { |
cd28ab6a SH |
1180 | le = get_tx_le(sky2); |
1181 | le->tx.tso.size = cpu_to_le16(mss); | |
793b883e | 1182 | le->tx.tso.rsvd = 0; |
cd28ab6a | 1183 | le->opcode = OP_LRGLEN | HW_OWNER; |
cd28ab6a | 1184 | le->ctrl = 0; |
793b883e | 1185 | sky2->tx_last_mss = mss; |
cd28ab6a SH |
1186 | } |
1187 | ||
cd28ab6a | 1188 | ctrl = 0; |
d1f13708 SH |
1189 | #ifdef SKY2_VLAN_TAG_USED |
1190 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ | |
1191 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | |
1192 | if (!le) { | |
1193 | le = get_tx_le(sky2); | |
1194 | le->tx.addr = 0; | |
1195 | le->opcode = OP_VLAN|HW_OWNER; | |
1196 | le->ctrl = 0; | |
1197 | } else | |
1198 | le->opcode |= OP_VLAN; | |
1199 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1200 | ctrl |= INS_VLAN; | |
1201 | } | |
1202 | #endif | |
1203 | ||
1204 | /* Handle TCP checksum offload */ | |
cd28ab6a | 1205 | if (skb->ip_summed == CHECKSUM_HW) { |
793b883e SH |
1206 | u16 hdr = skb->h.raw - skb->data; |
1207 | u16 offset = hdr + skb->csum; | |
cd28ab6a SH |
1208 | |
1209 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1210 | if (skb->nh.iph->protocol == IPPROTO_UDP) | |
1211 | ctrl |= UDPTCP; | |
1212 | ||
1213 | le = get_tx_le(sky2); | |
1214 | le->tx.csum.start = cpu_to_le16(hdr); | |
793b883e SH |
1215 | le->tx.csum.offset = cpu_to_le16(offset); |
1216 | le->length = 0; /* initial checksum value */ | |
cd28ab6a | 1217 | le->ctrl = 1; /* one packet */ |
793b883e | 1218 | le->opcode = OP_TCPLISW | HW_OWNER; |
cd28ab6a SH |
1219 | } |
1220 | ||
1221 | le = get_tx_le(sky2); | |
1222 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1223 | le->length = cpu_to_le16(len); | |
1224 | le->ctrl = ctrl; | |
793b883e | 1225 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1226 | |
793b883e | 1227 | /* Record the transmit mapping info */ |
cd28ab6a | 1228 | re->skb = skb; |
6cdbbdf3 | 1229 | pci_unmap_addr_set(re, mapaddr, mapping); |
cd28ab6a SH |
1230 | |
1231 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1232 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6cdbbdf3 | 1233 | struct tx_ring_info *fre; |
cd28ab6a SH |
1234 | |
1235 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1236 | frag->size, PCI_DMA_TODEVICE); | |
a036119f | 1237 | addr64 = high32(mapping); |
793b883e SH |
1238 | if (addr64 != sky2->tx_addr64) { |
1239 | le = get_tx_le(sky2); | |
1240 | le->tx.addr = cpu_to_le32(addr64); | |
1241 | le->ctrl = 0; | |
1242 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1243 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1244 | } |
1245 | ||
1246 | le = get_tx_le(sky2); | |
1247 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1248 | le->length = cpu_to_le16(frag->size); | |
1249 | le->ctrl = ctrl; | |
793b883e | 1250 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1251 | |
793b883e SH |
1252 | fre = sky2->tx_ring |
1253 | + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE; | |
6cdbbdf3 | 1254 | pci_unmap_addr_set(fre, mapaddr, mapping); |
cd28ab6a | 1255 | } |
6cdbbdf3 | 1256 | |
793b883e | 1257 | re->idx = sky2->tx_prod; |
cd28ab6a SH |
1258 | le->ctrl |= EOP; |
1259 | ||
724bca3c | 1260 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod, |
cd28ab6a SH |
1261 | &sky2->tx_last_put, TX_RING_SIZE); |
1262 | ||
0e3ff6aa | 1263 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
cd28ab6a | 1264 | netif_stop_queue(dev); |
793b883e SH |
1265 | |
1266 | out_unlock: | |
f2e46561 | 1267 | spin_unlock(&sky2->tx_lock); |
cd28ab6a SH |
1268 | |
1269 | dev->trans_start = jiffies; | |
1270 | return NETDEV_TX_OK; | |
1271 | } | |
1272 | ||
cd28ab6a | 1273 | /* |
793b883e SH |
1274 | * Free ring elements from starting at tx_cons until "done" |
1275 | * | |
1276 | * NB: the hardware will tell us about partial completion of multi-part | |
d571b694 | 1277 | * buffers; these are deferred until completion. |
cd28ab6a | 1278 | */ |
d11c13e7 | 1279 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1280 | { |
d11c13e7 | 1281 | struct net_device *dev = sky2->netdev; |
af2a58ac SH |
1282 | struct pci_dev *pdev = sky2->hw->pdev; |
1283 | u16 nxt, put; | |
793b883e | 1284 | unsigned i; |
cd28ab6a | 1285 | |
0e3ff6aa | 1286 | BUG_ON(done >= TX_RING_SIZE); |
2224795d | 1287 | |
d11c13e7 | 1288 | if (unlikely(netif_msg_tx_done(sky2))) |
d571b694 | 1289 | printk(KERN_DEBUG "%s: tx done, up to %u\n", |
d11c13e7 | 1290 | dev->name, done); |
cd28ab6a | 1291 | |
af2a58ac SH |
1292 | for (put = sky2->tx_cons; put != done; put = nxt) { |
1293 | struct tx_ring_info *re = sky2->tx_ring + put; | |
1294 | struct sk_buff *skb = re->skb; | |
cd28ab6a | 1295 | |
af2a58ac SH |
1296 | nxt = re->idx; |
1297 | BUG_ON(nxt >= TX_RING_SIZE); | |
d70cd51a | 1298 | prefetch(sky2->tx_ring + nxt); |
cd28ab6a | 1299 | |
793b883e | 1300 | /* Check for partial status */ |
af2a58ac SH |
1301 | if (tx_dist(put, done) < tx_dist(put, nxt)) |
1302 | break; | |
793b883e SH |
1303 | |
1304 | skb = re->skb; | |
af2a58ac | 1305 | pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), |
734d1868 | 1306 | skb_headlen(skb), PCI_DMA_TODEVICE); |
793b883e SH |
1307 | |
1308 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6cdbbdf3 | 1309 | struct tx_ring_info *fre; |
af2a58ac SH |
1310 | fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE; |
1311 | pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), | |
1312 | skb_shinfo(skb)->frags[i].size, | |
734d1868 | 1313 | PCI_DMA_TODEVICE); |
cd28ab6a SH |
1314 | } |
1315 | ||
cd28ab6a | 1316 | dev_kfree_skb_any(skb); |
793b883e | 1317 | } |
793b883e | 1318 | |
af2a58ac | 1319 | sky2->tx_cons = put; |
793b883e | 1320 | if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE) |
cd28ab6a | 1321 | netif_wake_queue(dev); |
cd28ab6a SH |
1322 | } |
1323 | ||
1324 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
13b97b74 | 1325 | static void sky2_tx_clean(struct sky2_port *sky2) |
cd28ab6a | 1326 | { |
302d1252 | 1327 | spin_lock_bh(&sky2->tx_lock); |
d11c13e7 | 1328 | sky2_tx_complete(sky2, sky2->tx_prod); |
302d1252 | 1329 | spin_unlock_bh(&sky2->tx_lock); |
cd28ab6a SH |
1330 | } |
1331 | ||
1332 | /* Network shutdown */ | |
1333 | static int sky2_down(struct net_device *dev) | |
1334 | { | |
1335 | struct sky2_port *sky2 = netdev_priv(dev); | |
1336 | struct sky2_hw *hw = sky2->hw; | |
1337 | unsigned port = sky2->port; | |
1338 | u16 ctrl; | |
cd28ab6a | 1339 | |
1b537565 SH |
1340 | /* Never really got started! */ |
1341 | if (!sky2->tx_le) | |
1342 | return 0; | |
1343 | ||
cd28ab6a SH |
1344 | if (netif_msg_ifdown(sky2)) |
1345 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1346 | ||
018d1c66 | 1347 | /* Stop more packets from being queued */ |
cd28ab6a SH |
1348 | netif_stop_queue(dev); |
1349 | ||
018d1c66 SH |
1350 | /* Disable port IRQ */ |
1351 | local_irq_disable(); | |
1352 | hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
1353 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1354 | local_irq_enable(); | |
1355 | ||
91c86df5 | 1356 | flush_scheduled_work(); |
018d1c66 | 1357 | |
793b883e SH |
1358 | sky2_phy_reset(hw, port); |
1359 | ||
cd28ab6a SH |
1360 | /* Stop transmitter */ |
1361 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1362 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1363 | ||
1364 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1365 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1366 | |
1367 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1368 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1369 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1370 | ||
1371 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1372 | ||
1373 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1374 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1375 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1376 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1377 | ||
1378 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1379 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1380 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1381 | ||
1382 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1383 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1384 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1385 | ||
1386 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1387 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1388 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1389 | |
1390 | /* Reset the Tx prefetch units */ | |
1391 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1392 | PREF_UNIT_RST_SET); | |
1393 | ||
1394 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1395 | ||
6b1a3aef | 1396 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1397 | |
1398 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1399 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1400 | ||
d571b694 | 1401 | /* turn off LED's */ |
cd28ab6a SH |
1402 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1403 | ||
018d1c66 SH |
1404 | synchronize_irq(hw->pdev->irq); |
1405 | ||
cd28ab6a SH |
1406 | sky2_tx_clean(sky2); |
1407 | sky2_rx_clean(sky2); | |
1408 | ||
1409 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1410 | sky2->rx_le, sky2->rx_le_map); | |
1411 | kfree(sky2->rx_ring); | |
1412 | ||
1413 | pci_free_consistent(hw->pdev, | |
1414 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1415 | sky2->tx_le, sky2->tx_le_map); | |
1416 | kfree(sky2->tx_ring); | |
1417 | ||
1b537565 SH |
1418 | sky2->tx_le = NULL; |
1419 | sky2->rx_le = NULL; | |
1420 | ||
1421 | sky2->rx_ring = NULL; | |
1422 | sky2->tx_ring = NULL; | |
1423 | ||
cd28ab6a SH |
1424 | return 0; |
1425 | } | |
1426 | ||
1427 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1428 | { | |
793b883e SH |
1429 | if (!hw->copper) |
1430 | return SPEED_1000; | |
1431 | ||
cd28ab6a SH |
1432 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1433 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1434 | ||
1435 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1436 | case PHY_M_PS_SPEED_1000: | |
1437 | return SPEED_1000; | |
1438 | case PHY_M_PS_SPEED_100: | |
1439 | return SPEED_100; | |
1440 | default: | |
1441 | return SPEED_10; | |
1442 | } | |
1443 | } | |
1444 | ||
1445 | static void sky2_link_up(struct sky2_port *sky2) | |
1446 | { | |
1447 | struct sky2_hw *hw = sky2->hw; | |
1448 | unsigned port = sky2->port; | |
1449 | u16 reg; | |
1450 | ||
1451 | /* Enable Transmit FIFO Underrun */ | |
793b883e | 1452 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
cd28ab6a SH |
1453 | |
1454 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
6f4c56b2 SH |
1455 | if (sky2->autoneg == AUTONEG_DISABLE) { |
1456 | reg |= GM_GPCR_AU_ALL_DIS; | |
1457 | ||
1458 | /* Is write/read necessary? Copied from sky2_mac_init */ | |
1459 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1460 | gma_read16(hw, port, GM_GP_CTRL); | |
1461 | ||
1462 | switch (sky2->speed) { | |
1463 | case SPEED_1000: | |
1464 | reg &= ~GM_GPCR_SPEED_100; | |
1465 | reg |= GM_GPCR_SPEED_1000; | |
1466 | break; | |
1467 | case SPEED_100: | |
1468 | reg &= ~GM_GPCR_SPEED_1000; | |
1469 | reg |= GM_GPCR_SPEED_100; | |
1470 | break; | |
1471 | case SPEED_10: | |
1472 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
1473 | break; | |
1474 | } | |
1475 | } else | |
1476 | reg &= ~GM_GPCR_AU_ALL_DIS; | |
1477 | ||
cd28ab6a SH |
1478 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) |
1479 | reg |= GM_GPCR_DUP_FULL; | |
1480 | ||
cd28ab6a SH |
1481 | /* enable Rx/Tx */ |
1482 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1483 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1484 | gma_read16(hw, port, GM_GP_CTRL); | |
1485 | ||
1486 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1487 | ||
1488 | netif_carrier_on(sky2->netdev); | |
1489 | netif_wake_queue(sky2->netdev); | |
1490 | ||
1491 | /* Turn on link LED */ | |
793b883e | 1492 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1493 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1494 | ||
793b883e SH |
1495 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
1496 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
1497 | ||
1498 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
1499 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
1500 | PHY_M_LEDC_INIT_CTRL(sky2->speed == | |
1501 | SPEED_10 ? 7 : 0) | | |
1502 | PHY_M_LEDC_STA1_CTRL(sky2->speed == | |
1503 | SPEED_100 ? 7 : 0) | | |
1504 | PHY_M_LEDC_STA0_CTRL(sky2->speed == | |
1505 | SPEED_1000 ? 7 : 0)); | |
1506 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
1507 | } | |
1508 | ||
cd28ab6a SH |
1509 | if (netif_msg_link(sky2)) |
1510 | printk(KERN_INFO PFX | |
d571b694 | 1511 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
cd28ab6a SH |
1512 | sky2->netdev->name, sky2->speed, |
1513 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
1514 | (sky2->tx_pause && sky2->rx_pause) ? "both" : | |
793b883e | 1515 | sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); |
cd28ab6a SH |
1516 | } |
1517 | ||
1518 | static void sky2_link_down(struct sky2_port *sky2) | |
1519 | { | |
1520 | struct sky2_hw *hw = sky2->hw; | |
1521 | unsigned port = sky2->port; | |
1522 | u16 reg; | |
1523 | ||
1524 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1525 | ||
1526 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1527 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1528 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1529 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | |
1530 | ||
1531 | if (sky2->rx_pause && !sky2->tx_pause) { | |
1532 | /* restore Asymmetric Pause bit */ | |
1533 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
793b883e SH |
1534 | gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) |
1535 | | PHY_M_AN_ASP); | |
cd28ab6a SH |
1536 | } |
1537 | ||
cd28ab6a SH |
1538 | netif_carrier_off(sky2->netdev); |
1539 | netif_stop_queue(sky2->netdev); | |
1540 | ||
1541 | /* Turn on link LED */ | |
1542 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1543 | ||
1544 | if (netif_msg_link(sky2)) | |
1545 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
1546 | sky2_phy_init(hw, port); | |
1547 | } | |
1548 | ||
793b883e SH |
1549 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1550 | { | |
1551 | struct sky2_hw *hw = sky2->hw; | |
1552 | unsigned port = sky2->port; | |
1553 | u16 lpa; | |
1554 | ||
1555 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); | |
1556 | ||
1557 | if (lpa & PHY_M_AN_RF) { | |
1558 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1559 | return -1; | |
1560 | } | |
1561 | ||
1562 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
1563 | gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { | |
1564 | printk(KERN_ERR PFX "%s: master/slave fault", | |
1565 | sky2->netdev->name); | |
1566 | return -1; | |
1567 | } | |
1568 | ||
1569 | if (!(aux & PHY_M_PS_SPDUP_RES)) { | |
1570 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1571 | sky2->netdev->name); | |
1572 | return -1; | |
1573 | } | |
1574 | ||
1575 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
1576 | ||
1577 | sky2->speed = sky2_phy_speed(hw, aux); | |
1578 | ||
1579 | /* Pause bits are offset (9..8) */ | |
1580 | if (hw->chip_id == CHIP_ID_YUKON_XL) | |
1581 | aux >>= 6; | |
1582 | ||
1583 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | |
1584 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | |
1585 | ||
1586 | if ((sky2->tx_pause || sky2->rx_pause) | |
1587 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | |
1588 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
1589 | else | |
1590 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1591 | ||
1592 | return 0; | |
1593 | } | |
cd28ab6a SH |
1594 | |
1595 | /* | |
91c86df5 | 1596 | * Interrupt from PHY are handled outside of interrupt context |
cd28ab6a SH |
1597 | * because accessing phy registers requires spin wait which might |
1598 | * cause excess interrupt latency. | |
1599 | */ | |
91c86df5 | 1600 | static void sky2_phy_task(void *arg) |
cd28ab6a | 1601 | { |
91c86df5 | 1602 | struct sky2_port *sky2 = arg; |
cd28ab6a | 1603 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a SH |
1604 | u16 istatus, phystat; |
1605 | ||
91c86df5 | 1606 | down(&sky2->phy_sema); |
793b883e SH |
1607 | istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT); |
1608 | phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT); | |
cd28ab6a SH |
1609 | |
1610 | if (netif_msg_intr(sky2)) | |
1611 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1612 | sky2->netdev->name, istatus, phystat); | |
1613 | ||
1614 | if (istatus & PHY_M_IS_AN_COMPL) { | |
793b883e SH |
1615 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1616 | sky2_link_up(sky2); | |
1617 | goto out; | |
1618 | } | |
cd28ab6a | 1619 | |
793b883e SH |
1620 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1621 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1622 | |
793b883e SH |
1623 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1624 | sky2->duplex = | |
1625 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1626 | |
793b883e SH |
1627 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1628 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1629 | sky2_link_up(sky2); |
793b883e SH |
1630 | else |
1631 | sky2_link_down(sky2); | |
cd28ab6a | 1632 | } |
793b883e | 1633 | out: |
91c86df5 | 1634 | up(&sky2->phy_sema); |
cd28ab6a SH |
1635 | |
1636 | local_irq_disable(); | |
793b883e | 1637 | hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2; |
cd28ab6a SH |
1638 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
1639 | local_irq_enable(); | |
1640 | } | |
1641 | ||
302d1252 SH |
1642 | |
1643 | /* Transmit timeout is only called if we are running, carries is up | |
1644 | * and tx queue is full (stopped). | |
1645 | */ | |
cd28ab6a SH |
1646 | static void sky2_tx_timeout(struct net_device *dev) |
1647 | { | |
1648 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 SH |
1649 | struct sky2_hw *hw = sky2->hw; |
1650 | unsigned txq = txqaddr[sky2->port]; | |
302d1252 SH |
1651 | u16 ridx; |
1652 | ||
1653 | /* Maybe we just missed an status interrupt */ | |
1654 | spin_lock(&sky2->tx_lock); | |
1655 | ridx = sky2_read16(hw, | |
1656 | sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX); | |
1657 | sky2_tx_complete(sky2, ridx); | |
1658 | spin_unlock(&sky2->tx_lock); | |
1659 | ||
1660 | if (!netif_queue_stopped(dev)) { | |
1661 | if (net_ratelimit()) | |
1662 | pr_info(PFX "transmit interrupt missed? recovered\n"); | |
1663 | return; | |
1664 | } | |
cd28ab6a SH |
1665 | |
1666 | if (netif_msg_timer(sky2)) | |
1667 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1668 | ||
8cc048e3 | 1669 | sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); |
8cc048e3 | 1670 | sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
cd28ab6a SH |
1671 | |
1672 | sky2_tx_clean(sky2); | |
8cc048e3 SH |
1673 | |
1674 | sky2_qset(hw, txq); | |
1675 | sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); | |
cd28ab6a SH |
1676 | } |
1677 | ||
734d1868 SH |
1678 | |
1679 | #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) | |
1680 | /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */ | |
1681 | static inline unsigned sky2_buf_size(int mtu) | |
1682 | { | |
1683 | return roundup(mtu + ETH_HLEN + 4, 8); | |
1684 | } | |
1685 | ||
cd28ab6a SH |
1686 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) |
1687 | { | |
6b1a3aef SH |
1688 | struct sky2_port *sky2 = netdev_priv(dev); |
1689 | struct sky2_hw *hw = sky2->hw; | |
1690 | int err; | |
1691 | u16 ctl, mode; | |
cd28ab6a SH |
1692 | |
1693 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
1694 | return -EINVAL; | |
1695 | ||
5a5b1ea0 SH |
1696 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) |
1697 | return -EINVAL; | |
1698 | ||
6b1a3aef SH |
1699 | if (!netif_running(dev)) { |
1700 | dev->mtu = new_mtu; | |
1701 | return 0; | |
1702 | } | |
1703 | ||
6b1a3aef SH |
1704 | sky2_write32(hw, B0_IMSK, 0); |
1705 | ||
018d1c66 SH |
1706 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1707 | netif_stop_queue(dev); | |
1708 | netif_poll_disable(hw->dev[0]); | |
1709 | ||
6b1a3aef SH |
1710 | ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); |
1711 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
1712 | sky2_rx_stop(sky2); | |
1713 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
1714 | |
1715 | dev->mtu = new_mtu; | |
734d1868 | 1716 | sky2->rx_bufsize = sky2_buf_size(new_mtu); |
6b1a3aef SH |
1717 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
1718 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1719 | ||
1720 | if (dev->mtu > ETH_DATA_LEN) | |
1721 | mode |= GM_SMOD_JUMBO_ENA; | |
1722 | ||
1723 | gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); | |
cd28ab6a | 1724 | |
6b1a3aef | 1725 | sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 1726 | |
6b1a3aef | 1727 | err = sky2_rx_start(sky2); |
6b1a3aef | 1728 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
018d1c66 | 1729 | |
1b537565 SH |
1730 | if (err) |
1731 | dev_close(dev); | |
1732 | else { | |
1733 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); | |
1734 | ||
1735 | netif_poll_enable(hw->dev[0]); | |
1736 | netif_wake_queue(dev); | |
1737 | } | |
1738 | ||
cd28ab6a SH |
1739 | return err; |
1740 | } | |
1741 | ||
1742 | /* | |
1743 | * Receive one packet. | |
1744 | * For small packets or errors, just reuse existing skb. | |
d571b694 | 1745 | * For larger packets, get new buffer. |
cd28ab6a | 1746 | */ |
d11c13e7 | 1747 | static struct sk_buff *sky2_receive(struct sky2_port *sky2, |
cd28ab6a SH |
1748 | u16 length, u32 status) |
1749 | { | |
cd28ab6a | 1750 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 1751 | struct sk_buff *skb = NULL; |
cd28ab6a SH |
1752 | |
1753 | if (unlikely(netif_msg_rx_status(sky2))) | |
1754 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
d11c13e7 | 1755 | sky2->netdev->name, sky2->rx_next, status, length); |
cd28ab6a | 1756 | |
793b883e | 1757 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 1758 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 1759 | |
42eeea01 | 1760 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
1761 | goto error; |
1762 | ||
42eeea01 SH |
1763 | if (!(status & GMR_FS_RX_OK)) |
1764 | goto resubmit; | |
1765 | ||
6e15b712 SH |
1766 | if ((status >> 16) != length || length > sky2->rx_bufsize) |
1767 | goto oversize; | |
1768 | ||
bdb5c58e | 1769 | if (length < copybreak) { |
79e57d32 SH |
1770 | skb = alloc_skb(length + 2, GFP_ATOMIC); |
1771 | if (!skb) | |
793b883e SH |
1772 | goto resubmit; |
1773 | ||
79e57d32 | 1774 | skb_reserve(skb, 2); |
793b883e SH |
1775 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, |
1776 | length, PCI_DMA_FROMDEVICE); | |
79e57d32 | 1777 | memcpy(skb->data, re->skb->data, length); |
d11c13e7 SH |
1778 | skb->ip_summed = re->skb->ip_summed; |
1779 | skb->csum = re->skb->csum; | |
793b883e SH |
1780 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, |
1781 | length, PCI_DMA_FROMDEVICE); | |
793b883e | 1782 | } else { |
79e57d32 SH |
1783 | struct sk_buff *nskb; |
1784 | ||
82788c7a | 1785 | nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC); |
793b883e SH |
1786 | if (!nskb) |
1787 | goto resubmit; | |
cd28ab6a | 1788 | |
793b883e | 1789 | skb = re->skb; |
79e57d32 | 1790 | re->skb = nskb; |
793b883e | 1791 | pci_unmap_single(sky2->hw->pdev, re->mapaddr, |
734d1868 | 1792 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1793 | prefetch(skb->data); |
cd28ab6a | 1794 | |
793b883e | 1795 | re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, |
734d1868 | 1796 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1797 | } |
cd28ab6a | 1798 | |
79e57d32 | 1799 | skb_put(skb, length); |
793b883e | 1800 | resubmit: |
d11c13e7 | 1801 | re->skb->ip_summed = CHECKSUM_NONE; |
734d1868 | 1802 | sky2_rx_add(sky2, re->mapaddr); |
79e57d32 | 1803 | |
bea86103 SH |
1804 | /* Tell receiver about new buffers. */ |
1805 | sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put, | |
1806 | &sky2->rx_last_put, RX_LE_SIZE); | |
1807 | ||
cd28ab6a SH |
1808 | return skb; |
1809 | ||
6e15b712 SH |
1810 | oversize: |
1811 | ++sky2->net_stats.rx_over_errors; | |
1812 | goto resubmit; | |
1813 | ||
cd28ab6a | 1814 | error: |
6e15b712 SH |
1815 | ++sky2->net_stats.rx_errors; |
1816 | ||
3be92a70 | 1817 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
cd28ab6a SH |
1818 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", |
1819 | sky2->netdev->name, status, length); | |
793b883e SH |
1820 | |
1821 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
cd28ab6a SH |
1822 | sky2->net_stats.rx_length_errors++; |
1823 | if (status & GMR_FS_FRAGMENT) | |
1824 | sky2->net_stats.rx_frame_errors++; | |
1825 | if (status & GMR_FS_CRC_ERR) | |
1826 | sky2->net_stats.rx_crc_errors++; | |
793b883e SH |
1827 | if (status & GMR_FS_RX_FF_OV) |
1828 | sky2->net_stats.rx_fifo_errors++; | |
79e57d32 | 1829 | |
793b883e | 1830 | goto resubmit; |
cd28ab6a SH |
1831 | } |
1832 | ||
2224795d SH |
1833 | /* |
1834 | * Check for transmit complete | |
793b883e | 1835 | */ |
13b97b74 | 1836 | #define TX_NO_STATUS 0xffff |
2224795d | 1837 | |
28bd181a | 1838 | static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last) |
13b97b74 SH |
1839 | { |
1840 | if (last != TX_NO_STATUS) { | |
1841 | struct net_device *dev = hw->dev[port]; | |
1842 | if (dev && netif_running(dev)) { | |
1843 | struct sky2_port *sky2 = netdev_priv(dev); | |
302d1252 SH |
1844 | |
1845 | spin_lock(&sky2->tx_lock); | |
13b97b74 | 1846 | sky2_tx_complete(sky2, last); |
302d1252 | 1847 | spin_unlock(&sky2->tx_lock); |
13b97b74 | 1848 | } |
2224795d | 1849 | } |
cd28ab6a SH |
1850 | } |
1851 | ||
1852 | /* | |
cd28ab6a SH |
1853 | * Both ports share the same status interrupt, therefore there is only |
1854 | * one poll routine. | |
cd28ab6a | 1855 | */ |
d11c13e7 | 1856 | static int sky2_poll(struct net_device *dev0, int *budget) |
cd28ab6a | 1857 | { |
d11c13e7 SH |
1858 | struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; |
1859 | unsigned int to_do = min(dev0->quota, *budget); | |
cd28ab6a | 1860 | unsigned int work_done = 0; |
793b883e | 1861 | u16 hwidx; |
13b97b74 | 1862 | u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS }; |
cd28ab6a | 1863 | |
f9a66c7f SH |
1864 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); |
1865 | ||
793b883e | 1866 | hwidx = sky2_read16(hw, STAT_PUT_IDX); |
79e57d32 | 1867 | BUG_ON(hwidx >= STATUS_RING_SIZE); |
af2a58ac | 1868 | rmb(); |
bea86103 | 1869 | |
13210ce5 SH |
1870 | while (hwidx != hw->st_idx) { |
1871 | struct sky2_status_le *le = hw->st_le + hw->st_idx; | |
1872 | struct net_device *dev; | |
d11c13e7 | 1873 | struct sky2_port *sky2; |
cd28ab6a | 1874 | struct sk_buff *skb; |
cd28ab6a SH |
1875 | u32 status; |
1876 | u16 length; | |
1877 | ||
13210ce5 | 1878 | le = hw->st_le + hw->st_idx; |
bea86103 | 1879 | hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE; |
13210ce5 | 1880 | prefetch(hw->st_le + hw->st_idx); |
bea86103 | 1881 | |
13210ce5 SH |
1882 | BUG_ON(le->link >= 2); |
1883 | dev = hw->dev[le->link]; | |
1884 | if (dev == NULL || !netif_running(dev)) | |
1885 | continue; | |
1886 | ||
1887 | sky2 = netdev_priv(dev); | |
cd28ab6a SH |
1888 | status = le32_to_cpu(le->status); |
1889 | length = le16_to_cpu(le->length); | |
cd28ab6a | 1890 | |
dc4d5ea2 | 1891 | switch (le->opcode & ~HW_OWNER) { |
cd28ab6a | 1892 | case OP_RXSTAT: |
d11c13e7 | 1893 | skb = sky2_receive(sky2, length, status); |
d1f13708 SH |
1894 | if (!skb) |
1895 | break; | |
13210ce5 SH |
1896 | |
1897 | skb->dev = dev; | |
1898 | skb->protocol = eth_type_trans(skb, dev); | |
1899 | dev->last_rx = jiffies; | |
1900 | ||
d1f13708 SH |
1901 | #ifdef SKY2_VLAN_TAG_USED |
1902 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { | |
1903 | vlan_hwaccel_receive_skb(skb, | |
1904 | sky2->vlgrp, | |
1905 | be16_to_cpu(sky2->rx_tag)); | |
1906 | } else | |
1907 | #endif | |
cd28ab6a | 1908 | netif_receive_skb(skb); |
13210ce5 SH |
1909 | |
1910 | if (++work_done >= to_do) | |
1911 | goto exit_loop; | |
cd28ab6a SH |
1912 | break; |
1913 | ||
d1f13708 SH |
1914 | #ifdef SKY2_VLAN_TAG_USED |
1915 | case OP_RXVLAN: | |
1916 | sky2->rx_tag = length; | |
1917 | break; | |
1918 | ||
1919 | case OP_RXCHKSVLAN: | |
1920 | sky2->rx_tag = length; | |
1921 | /* fall through */ | |
1922 | #endif | |
cd28ab6a | 1923 | case OP_RXCHKS: |
d11c13e7 SH |
1924 | skb = sky2->rx_ring[sky2->rx_next].skb; |
1925 | skb->ip_summed = CHECKSUM_HW; | |
1926 | skb->csum = le16_to_cpu(status); | |
cd28ab6a SH |
1927 | break; |
1928 | ||
1929 | case OP_TXINDEXLE: | |
13b97b74 SH |
1930 | /* TX index reports status for both ports */ |
1931 | tx_done[0] = status & 0xffff; | |
1932 | tx_done[1] = ((status >> 24) & 0xff) | |
1933 | | (u16)(length & 0xf) << 8; | |
cd28ab6a SH |
1934 | break; |
1935 | ||
cd28ab6a SH |
1936 | default: |
1937 | if (net_ratelimit()) | |
793b883e | 1938 | printk(KERN_WARNING PFX |
dc4d5ea2 | 1939 | "unknown status opcode 0x%x\n", le->opcode); |
cd28ab6a SH |
1940 | break; |
1941 | } | |
13210ce5 | 1942 | } |
cd28ab6a | 1943 | |
13210ce5 | 1944 | exit_loop: |
13b97b74 SH |
1945 | sky2_tx_check(hw, 0, tx_done[0]); |
1946 | sky2_tx_check(hw, 1, tx_done[1]); | |
1947 | ||
f9a66c7f | 1948 | if (likely(work_done < to_do)) { |
13b97b74 | 1949 | /* need to restart TX timer */ |
cd28ab6a SH |
1950 | if (is_ec_a1(hw)) { |
1951 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
1952 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
1953 | } | |
1954 | ||
bea86103 | 1955 | netif_rx_complete(dev0); |
cd28ab6a SH |
1956 | hw->intr_mask |= Y2_IS_STAT_BMU; |
1957 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
13210ce5 SH |
1958 | return 0; |
1959 | } else { | |
1960 | *budget -= work_done; | |
1961 | dev0->quota -= work_done; | |
1962 | return 1; | |
cd28ab6a | 1963 | } |
cd28ab6a SH |
1964 | } |
1965 | ||
1966 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
1967 | { | |
1968 | struct net_device *dev = hw->dev[port]; | |
1969 | ||
3be92a70 SH |
1970 | if (net_ratelimit()) |
1971 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
1972 | dev->name, status); | |
cd28ab6a SH |
1973 | |
1974 | if (status & Y2_IS_PAR_RD1) { | |
3be92a70 SH |
1975 | if (net_ratelimit()) |
1976 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
1977 | dev->name); | |
cd28ab6a SH |
1978 | /* Clear IRQ */ |
1979 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
1980 | } | |
1981 | ||
1982 | if (status & Y2_IS_PAR_WR1) { | |
3be92a70 SH |
1983 | if (net_ratelimit()) |
1984 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
1985 | dev->name); | |
cd28ab6a SH |
1986 | |
1987 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
1988 | } | |
1989 | ||
1990 | if (status & Y2_IS_PAR_MAC1) { | |
3be92a70 SH |
1991 | if (net_ratelimit()) |
1992 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
cd28ab6a SH |
1993 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
1994 | } | |
1995 | ||
1996 | if (status & Y2_IS_PAR_RX1) { | |
3be92a70 SH |
1997 | if (net_ratelimit()) |
1998 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
cd28ab6a SH |
1999 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
2000 | } | |
2001 | ||
2002 | if (status & Y2_IS_TCP_TXA1) { | |
3be92a70 SH |
2003 | if (net_ratelimit()) |
2004 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", | |
2005 | dev->name); | |
cd28ab6a SH |
2006 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
2007 | } | |
2008 | } | |
2009 | ||
2010 | static void sky2_hw_intr(struct sky2_hw *hw) | |
2011 | { | |
2012 | u32 status = sky2_read32(hw, B0_HWE_ISRC); | |
2013 | ||
793b883e | 2014 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 2015 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2016 | |
2017 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
2018 | u16 pci_err; |
2019 | ||
2020 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err); | |
3be92a70 SH |
2021 | if (net_ratelimit()) |
2022 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", | |
2023 | pci_name(hw->pdev), pci_err); | |
cd28ab6a SH |
2024 | |
2025 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
2026 | pci_write_config_word(hw->pdev, PCI_STATUS, |
2027 | pci_err | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
2028 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2029 | } | |
2030 | ||
2031 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 2032 | /* PCI-Express uncorrectable Error occurred */ |
793b883e SH |
2033 | u32 pex_err; |
2034 | ||
2035 | pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err); | |
cd28ab6a | 2036 | |
3be92a70 SH |
2037 | if (net_ratelimit()) |
2038 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", | |
2039 | pci_name(hw->pdev), pex_err); | |
cd28ab6a SH |
2040 | |
2041 | /* clear the interrupt */ | |
2042 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
2043 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, |
2044 | 0xffffffffUL); | |
cd28ab6a SH |
2045 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2046 | ||
2047 | if (pex_err & PEX_FATAL_ERRORS) { | |
2048 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); | |
2049 | hwmsk &= ~Y2_IS_PCI_EXP; | |
2050 | sky2_write32(hw, B0_HWE_IMSK, hwmsk); | |
2051 | } | |
2052 | } | |
2053 | ||
2054 | if (status & Y2_HWE_L1_MASK) | |
2055 | sky2_hw_error(hw, 0, status); | |
2056 | status >>= 8; | |
2057 | if (status & Y2_HWE_L1_MASK) | |
2058 | sky2_hw_error(hw, 1, status); | |
2059 | } | |
2060 | ||
2061 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2062 | { | |
2063 | struct net_device *dev = hw->dev[port]; | |
2064 | struct sky2_port *sky2 = netdev_priv(dev); | |
2065 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2066 | ||
2067 | if (netif_msg_intr(sky2)) | |
2068 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
2069 | dev->name, status); | |
2070 | ||
2071 | if (status & GM_IS_RX_FF_OR) { | |
2072 | ++sky2->net_stats.rx_fifo_errors; | |
2073 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); | |
2074 | } | |
2075 | ||
2076 | if (status & GM_IS_TX_FF_UR) { | |
2077 | ++sky2->net_stats.tx_fifo_errors; | |
2078 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); | |
2079 | } | |
cd28ab6a SH |
2080 | } |
2081 | ||
2082 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
2083 | { | |
2084 | struct net_device *dev = hw->dev[port]; | |
2085 | struct sky2_port *sky2 = netdev_priv(dev); | |
2086 | ||
2087 | hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
2088 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
91c86df5 | 2089 | schedule_work(&sky2->phy_task); |
cd28ab6a SH |
2090 | } |
2091 | ||
2092 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |
2093 | { | |
2094 | struct sky2_hw *hw = dev_id; | |
bea86103 | 2095 | struct net_device *dev0 = hw->dev[0]; |
cd28ab6a SH |
2096 | u32 status; |
2097 | ||
2098 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
793b883e | 2099 | if (status == 0 || status == ~0) |
cd28ab6a SH |
2100 | return IRQ_NONE; |
2101 | ||
2102 | if (status & Y2_IS_HW_ERR) | |
2103 | sky2_hw_intr(hw); | |
2104 | ||
793b883e | 2105 | /* Do NAPI for Rx and Tx status */ |
bea86103 | 2106 | if (status & Y2_IS_STAT_BMU) { |
cd28ab6a SH |
2107 | hw->intr_mask &= ~Y2_IS_STAT_BMU; |
2108 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
bea86103 | 2109 | |
0a122576 SH |
2110 | if (likely(__netif_rx_schedule_prep(dev0))) { |
2111 | prefetch(&hw->st_le[hw->st_idx]); | |
bea86103 | 2112 | __netif_rx_schedule(dev0); |
0a122576 | 2113 | } |
cd28ab6a SH |
2114 | } |
2115 | ||
793b883e | 2116 | if (status & Y2_IS_IRQ_PHY1) |
cd28ab6a SH |
2117 | sky2_phy_intr(hw, 0); |
2118 | ||
2119 | if (status & Y2_IS_IRQ_PHY2) | |
2120 | sky2_phy_intr(hw, 1); | |
2121 | ||
2122 | if (status & Y2_IS_IRQ_MAC1) | |
2123 | sky2_mac_intr(hw, 0); | |
2124 | ||
2125 | if (status & Y2_IS_IRQ_MAC2) | |
2126 | sky2_mac_intr(hw, 1); | |
2127 | ||
cd28ab6a | 2128 | sky2_write32(hw, B0_Y2_SP_ICR, 2); |
793b883e SH |
2129 | |
2130 | sky2_read32(hw, B0_IMSK); | |
2131 | ||
cd28ab6a SH |
2132 | return IRQ_HANDLED; |
2133 | } | |
2134 | ||
2135 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2136 | static void sky2_netpoll(struct net_device *dev) | |
2137 | { | |
2138 | struct sky2_port *sky2 = netdev_priv(dev); | |
2139 | ||
793b883e | 2140 | sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL); |
cd28ab6a SH |
2141 | } |
2142 | #endif | |
2143 | ||
2144 | /* Chip internal frequency for clock calculations */ | |
fb17358f | 2145 | static inline u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 2146 | { |
793b883e | 2147 | switch (hw->chip_id) { |
cd28ab6a | 2148 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2149 | case CHIP_ID_YUKON_EC_U: |
fb17358f | 2150 | return 125; /* 125 Mhz */ |
cd28ab6a | 2151 | case CHIP_ID_YUKON_FE: |
fb17358f | 2152 | return 100; /* 100 Mhz */ |
793b883e | 2153 | default: /* YUKON_XL */ |
fb17358f | 2154 | return 156; /* 156 Mhz */ |
cd28ab6a SH |
2155 | } |
2156 | } | |
2157 | ||
fb17358f | 2158 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 2159 | { |
fb17358f | 2160 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
2161 | } |
2162 | ||
fb17358f | 2163 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 2164 | { |
fb17358f | 2165 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
2166 | } |
2167 | ||
fb17358f | 2168 | |
cd28ab6a SH |
2169 | static int sky2_reset(struct sky2_hw *hw) |
2170 | { | |
cd28ab6a SH |
2171 | u16 status; |
2172 | u8 t8, pmd_type; | |
2d42d21f | 2173 | int i, err; |
cd28ab6a | 2174 | |
cd28ab6a | 2175 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
08c06d8a | 2176 | |
cd28ab6a SH |
2177 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
2178 | if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { | |
2179 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
2180 | pci_name(hw->pdev), hw->chip_id); | |
2181 | return -EOPNOTSUPP; | |
2182 | } | |
2183 | ||
2184 | /* disable ASF */ | |
2185 | if (hw->chip_id <= CHIP_ID_YUKON_EC) { | |
2186 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
2187 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
2188 | } | |
2189 | ||
2190 | /* do a SW reset */ | |
2191 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
2192 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2193 | ||
2194 | /* clear PCI errors, if any */ | |
2d42d21f SH |
2195 | err = pci_read_config_word(hw->pdev, PCI_STATUS, &status); |
2196 | if (err) | |
2197 | goto pci_err; | |
2198 | ||
cd28ab6a | 2199 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
2d42d21f SH |
2200 | err = pci_write_config_word(hw->pdev, PCI_STATUS, |
2201 | status | PCI_STATUS_ERROR_BITS); | |
2202 | if (err) | |
2203 | goto pci_err; | |
cd28ab6a SH |
2204 | |
2205 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
2206 | ||
2207 | /* clear any PEX errors */ | |
2d42d21f SH |
2208 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) { |
2209 | err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, | |
2210 | 0xffffffffUL); | |
2211 | if (err) | |
2212 | goto pci_err; | |
cd28ab6a SH |
2213 | } |
2214 | ||
2215 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | |
2216 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | |
2217 | ||
2218 | hw->ports = 1; | |
2219 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
2220 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
2221 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
2222 | ++hw->ports; | |
2223 | } | |
2224 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; | |
2225 | ||
5afa0a9c | 2226 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
2227 | |
2228 | for (i = 0; i < hw->ports; i++) { | |
2229 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
2230 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
2231 | } | |
2232 | ||
2233 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
2234 | ||
793b883e SH |
2235 | /* Clear I2C IRQ noise */ |
2236 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
2237 | |
2238 | /* turn off hardware timer (unused) */ | |
2239 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
2240 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 2241 | |
cd28ab6a SH |
2242 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
2243 | ||
69634ee7 SH |
2244 | /* Turn off descriptor polling */ |
2245 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
2246 | |
2247 | /* Turn off receive timestamp */ | |
2248 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 2249 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2250 | |
2251 | /* enable the Tx Arbiters */ | |
2252 | for (i = 0; i < hw->ports; i++) | |
2253 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
2254 | ||
2255 | /* Initialize ram interface */ | |
2256 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 2257 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
2258 | |
2259 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
2260 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
2261 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
2262 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
2263 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
2264 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
2265 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
2266 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
2267 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
2268 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
2269 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
2270 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
2271 | } | |
2272 | ||
cd28ab6a SH |
2273 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); |
2274 | ||
cd28ab6a SH |
2275 | for (i = 0; i < hw->ports; i++) |
2276 | sky2_phy_reset(hw, i); | |
cd28ab6a | 2277 | |
cd28ab6a SH |
2278 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2279 | hw->st_idx = 0; | |
2280 | ||
2281 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
2282 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
2283 | ||
2284 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 2285 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
2286 | |
2287 | /* Set the list last index */ | |
793b883e | 2288 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 2289 | |
793b883e | 2290 | /* These status setup values are copied from SysKonnect's driver */ |
cd28ab6a SH |
2291 | if (is_ec_a1(hw)) { |
2292 | /* WA for dev. #4.3 */ | |
793b883e | 2293 | sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */ |
cd28ab6a SH |
2294 | |
2295 | /* set Status-FIFO watermark */ | |
2296 | sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */ | |
2297 | ||
2298 | /* set Status-FIFO ISR watermark */ | |
793b883e | 2299 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */ |
69634ee7 | 2300 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000)); |
cd28ab6a | 2301 | } else { |
69634ee7 SH |
2302 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
2303 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a SH |
2304 | |
2305 | /* set Status-FIFO ISR watermark */ | |
2306 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
69634ee7 SH |
2307 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); |
2308 | else | |
2309 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 2310 | |
69634ee7 SH |
2311 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
2312 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
2313 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); | |
cd28ab6a SH |
2314 | } |
2315 | ||
793b883e | 2316 | /* enable status unit */ |
cd28ab6a SH |
2317 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2318 | ||
2319 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2320 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2321 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2322 | ||
2323 | return 0; | |
2d42d21f SH |
2324 | |
2325 | pci_err: | |
2326 | /* This is to catch a BIOS bug workaround where | |
2327 | * mmconfig table doesn't have other buses. | |
2328 | */ | |
2329 | printk(KERN_ERR PFX "%s: can't access PCI config space\n", | |
2330 | pci_name(hw->pdev)); | |
2331 | return err; | |
cd28ab6a SH |
2332 | } |
2333 | ||
28bd181a | 2334 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
cd28ab6a SH |
2335 | { |
2336 | u32 modes; | |
2337 | if (hw->copper) { | |
793b883e SH |
2338 | modes = SUPPORTED_10baseT_Half |
2339 | | SUPPORTED_10baseT_Full | |
2340 | | SUPPORTED_100baseT_Half | |
2341 | | SUPPORTED_100baseT_Full | |
2342 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2343 | |
2344 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
2345 | modes |= SUPPORTED_1000baseT_Half | |
793b883e | 2346 | | SUPPORTED_1000baseT_Full; |
cd28ab6a SH |
2347 | } else |
2348 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
793b883e | 2349 | | SUPPORTED_Autoneg; |
cd28ab6a SH |
2350 | return modes; |
2351 | } | |
2352 | ||
793b883e | 2353 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
2354 | { |
2355 | struct sky2_port *sky2 = netdev_priv(dev); | |
2356 | struct sky2_hw *hw = sky2->hw; | |
2357 | ||
2358 | ecmd->transceiver = XCVR_INTERNAL; | |
2359 | ecmd->supported = sky2_supported_modes(hw); | |
2360 | ecmd->phy_address = PHY_ADDR_MARV; | |
2361 | if (hw->copper) { | |
2362 | ecmd->supported = SUPPORTED_10baseT_Half | |
793b883e SH |
2363 | | SUPPORTED_10baseT_Full |
2364 | | SUPPORTED_100baseT_Half | |
2365 | | SUPPORTED_100baseT_Full | |
2366 | | SUPPORTED_1000baseT_Half | |
2367 | | SUPPORTED_1000baseT_Full | |
2368 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2369 | ecmd->port = PORT_TP; |
2370 | } else | |
2371 | ecmd->port = PORT_FIBRE; | |
2372 | ||
2373 | ecmd->advertising = sky2->advertising; | |
2374 | ecmd->autoneg = sky2->autoneg; | |
2375 | ecmd->speed = sky2->speed; | |
2376 | ecmd->duplex = sky2->duplex; | |
2377 | return 0; | |
2378 | } | |
2379 | ||
2380 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2381 | { | |
2382 | struct sky2_port *sky2 = netdev_priv(dev); | |
2383 | const struct sky2_hw *hw = sky2->hw; | |
2384 | u32 supported = sky2_supported_modes(hw); | |
2385 | ||
2386 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2387 | ecmd->advertising = supported; | |
2388 | sky2->duplex = -1; | |
2389 | sky2->speed = -1; | |
2390 | } else { | |
2391 | u32 setting; | |
2392 | ||
793b883e | 2393 | switch (ecmd->speed) { |
cd28ab6a SH |
2394 | case SPEED_1000: |
2395 | if (ecmd->duplex == DUPLEX_FULL) | |
2396 | setting = SUPPORTED_1000baseT_Full; | |
2397 | else if (ecmd->duplex == DUPLEX_HALF) | |
2398 | setting = SUPPORTED_1000baseT_Half; | |
2399 | else | |
2400 | return -EINVAL; | |
2401 | break; | |
2402 | case SPEED_100: | |
2403 | if (ecmd->duplex == DUPLEX_FULL) | |
2404 | setting = SUPPORTED_100baseT_Full; | |
2405 | else if (ecmd->duplex == DUPLEX_HALF) | |
2406 | setting = SUPPORTED_100baseT_Half; | |
2407 | else | |
2408 | return -EINVAL; | |
2409 | break; | |
2410 | ||
2411 | case SPEED_10: | |
2412 | if (ecmd->duplex == DUPLEX_FULL) | |
2413 | setting = SUPPORTED_10baseT_Full; | |
2414 | else if (ecmd->duplex == DUPLEX_HALF) | |
2415 | setting = SUPPORTED_10baseT_Half; | |
2416 | else | |
2417 | return -EINVAL; | |
2418 | break; | |
2419 | default: | |
2420 | return -EINVAL; | |
2421 | } | |
2422 | ||
2423 | if ((setting & supported) == 0) | |
2424 | return -EINVAL; | |
2425 | ||
2426 | sky2->speed = ecmd->speed; | |
2427 | sky2->duplex = ecmd->duplex; | |
2428 | } | |
2429 | ||
2430 | sky2->autoneg = ecmd->autoneg; | |
2431 | sky2->advertising = ecmd->advertising; | |
2432 | ||
1b537565 SH |
2433 | if (netif_running(dev)) |
2434 | sky2_phy_reinit(sky2); | |
cd28ab6a SH |
2435 | |
2436 | return 0; | |
2437 | } | |
2438 | ||
2439 | static void sky2_get_drvinfo(struct net_device *dev, | |
2440 | struct ethtool_drvinfo *info) | |
2441 | { | |
2442 | struct sky2_port *sky2 = netdev_priv(dev); | |
2443 | ||
2444 | strcpy(info->driver, DRV_NAME); | |
2445 | strcpy(info->version, DRV_VERSION); | |
2446 | strcpy(info->fw_version, "N/A"); | |
2447 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
2448 | } | |
2449 | ||
2450 | static const struct sky2_stat { | |
793b883e SH |
2451 | char name[ETH_GSTRING_LEN]; |
2452 | u16 offset; | |
cd28ab6a SH |
2453 | } sky2_stats[] = { |
2454 | { "tx_bytes", GM_TXO_OK_HI }, | |
2455 | { "rx_bytes", GM_RXO_OK_HI }, | |
2456 | { "tx_broadcast", GM_TXF_BC_OK }, | |
2457 | { "rx_broadcast", GM_RXF_BC_OK }, | |
2458 | { "tx_multicast", GM_TXF_MC_OK }, | |
2459 | { "rx_multicast", GM_RXF_MC_OK }, | |
2460 | { "tx_unicast", GM_TXF_UC_OK }, | |
2461 | { "rx_unicast", GM_RXF_UC_OK }, | |
2462 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
2463 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
2464 | { "collisions", GM_TXF_SNG_COL }, | |
2465 | { "late_collision",GM_TXF_LAT_COL }, | |
2466 | { "aborted", GM_TXF_ABO_COL }, | |
2467 | { "multi_collisions", GM_TXF_MUL_COL }, | |
2468 | { "fifo_underrun", GM_TXE_FIFO_UR }, | |
2469 | { "fifo_overflow", GM_RXE_FIFO_OV }, | |
2470 | { "rx_toolong", GM_RXF_LNG_ERR }, | |
2471 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
2472 | { "rx_runt", GM_RXE_FRAG }, | |
2473 | { "rx_too_long", GM_RXF_LNG_ERR }, | |
2474 | { "rx_fcs_error", GM_RXF_FCS_ERR }, | |
2475 | }; | |
2476 | ||
cd28ab6a SH |
2477 | static u32 sky2_get_rx_csum(struct net_device *dev) |
2478 | { | |
2479 | struct sky2_port *sky2 = netdev_priv(dev); | |
2480 | ||
2481 | return sky2->rx_csum; | |
2482 | } | |
2483 | ||
2484 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
2485 | { | |
2486 | struct sky2_port *sky2 = netdev_priv(dev); | |
2487 | ||
2488 | sky2->rx_csum = data; | |
793b883e | 2489 | |
cd28ab6a SH |
2490 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2491 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
2492 | ||
2493 | return 0; | |
2494 | } | |
2495 | ||
2496 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
2497 | { | |
2498 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2499 | return sky2->msg_enable; | |
2500 | } | |
2501 | ||
9a7ae0a9 SH |
2502 | static int sky2_nway_reset(struct net_device *dev) |
2503 | { | |
2504 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 SH |
2505 | |
2506 | if (sky2->autoneg != AUTONEG_ENABLE) | |
2507 | return -EINVAL; | |
2508 | ||
1b537565 | 2509 | sky2_phy_reinit(sky2); |
9a7ae0a9 SH |
2510 | |
2511 | return 0; | |
2512 | } | |
2513 | ||
793b883e | 2514 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
2515 | { |
2516 | struct sky2_hw *hw = sky2->hw; | |
2517 | unsigned port = sky2->port; | |
2518 | int i; | |
2519 | ||
2520 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 2521 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 2522 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 2523 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 2524 | |
793b883e | 2525 | for (i = 2; i < count; i++) |
cd28ab6a SH |
2526 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
2527 | } | |
2528 | ||
cd28ab6a SH |
2529 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
2530 | { | |
2531 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2532 | sky2->msg_enable = value; | |
2533 | } | |
2534 | ||
2535 | static int sky2_get_stats_count(struct net_device *dev) | |
2536 | { | |
2537 | return ARRAY_SIZE(sky2_stats); | |
2538 | } | |
2539 | ||
2540 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 2541 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
2542 | { |
2543 | struct sky2_port *sky2 = netdev_priv(dev); | |
2544 | ||
793b883e | 2545 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
2546 | } |
2547 | ||
793b883e | 2548 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
2549 | { |
2550 | int i; | |
2551 | ||
2552 | switch (stringset) { | |
2553 | case ETH_SS_STATS: | |
2554 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
2555 | memcpy(data + i * ETH_GSTRING_LEN, | |
2556 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
2557 | break; | |
2558 | } | |
2559 | } | |
2560 | ||
2561 | /* Use hardware MIB variables for critical path statistics and | |
2562 | * transmit feedback not reported at interrupt. | |
2563 | * Other errors are accounted for in interrupt handler. | |
2564 | */ | |
2565 | static struct net_device_stats *sky2_get_stats(struct net_device *dev) | |
2566 | { | |
2567 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2568 | u64 data[13]; |
cd28ab6a | 2569 | |
793b883e | 2570 | sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); |
cd28ab6a SH |
2571 | |
2572 | sky2->net_stats.tx_bytes = data[0]; | |
2573 | sky2->net_stats.rx_bytes = data[1]; | |
2574 | sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
2575 | sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
2576 | sky2->net_stats.multicast = data[5] + data[7]; | |
2577 | sky2->net_stats.collisions = data[10]; | |
2578 | sky2->net_stats.tx_aborted_errors = data[12]; | |
2579 | ||
2580 | return &sky2->net_stats; | |
2581 | } | |
2582 | ||
2583 | static int sky2_set_mac_address(struct net_device *dev, void *p) | |
2584 | { | |
2585 | struct sky2_port *sky2 = netdev_priv(dev); | |
a8ab1ec0 SH |
2586 | struct sky2_hw *hw = sky2->hw; |
2587 | unsigned port = sky2->port; | |
2588 | const struct sockaddr *addr = p; | |
cd28ab6a SH |
2589 | |
2590 | if (!is_valid_ether_addr(addr->sa_data)) | |
2591 | return -EADDRNOTAVAIL; | |
2592 | ||
cd28ab6a | 2593 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
a8ab1ec0 | 2594 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
cd28ab6a | 2595 | dev->dev_addr, ETH_ALEN); |
a8ab1ec0 | 2596 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
cd28ab6a | 2597 | dev->dev_addr, ETH_ALEN); |
1b537565 | 2598 | |
a8ab1ec0 SH |
2599 | /* virtual address for data */ |
2600 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
2601 | ||
2602 | /* physical address: used for pause frames */ | |
2603 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
1b537565 SH |
2604 | |
2605 | return 0; | |
cd28ab6a SH |
2606 | } |
2607 | ||
2608 | static void sky2_set_multicast(struct net_device *dev) | |
2609 | { | |
2610 | struct sky2_port *sky2 = netdev_priv(dev); | |
2611 | struct sky2_hw *hw = sky2->hw; | |
2612 | unsigned port = sky2->port; | |
2613 | struct dev_mc_list *list = dev->mc_list; | |
2614 | u16 reg; | |
2615 | u8 filter[8]; | |
2616 | ||
2617 | memset(filter, 0, sizeof(filter)); | |
2618 | ||
2619 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
2620 | reg |= GM_RXCR_UCF_ENA; | |
2621 | ||
d571b694 | 2622 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 2623 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
793b883e | 2624 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ |
cd28ab6a | 2625 | memset(filter, 0xff, sizeof(filter)); |
793b883e | 2626 | else if (dev->mc_count == 0) /* no multicast */ |
cd28ab6a SH |
2627 | reg &= ~GM_RXCR_MCF_ENA; |
2628 | else { | |
2629 | int i; | |
2630 | reg |= GM_RXCR_MCF_ENA; | |
2631 | ||
2632 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2633 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
793b883e | 2634 | filter[bit / 8] |= 1 << (bit % 8); |
cd28ab6a SH |
2635 | } |
2636 | } | |
2637 | ||
cd28ab6a | 2638 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 2639 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 2640 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 2641 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 2642 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 2643 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 2644 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 2645 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
2646 | |
2647 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
2648 | } | |
2649 | ||
2650 | /* Can have one global because blinking is controlled by | |
2651 | * ethtool and that is always under RTNL mutex | |
2652 | */ | |
91c86df5 | 2653 | static void sky2_led(struct sky2_hw *hw, unsigned port, int on) |
cd28ab6a | 2654 | { |
793b883e SH |
2655 | u16 pg; |
2656 | ||
793b883e SH |
2657 | switch (hw->chip_id) { |
2658 | case CHIP_ID_YUKON_XL: | |
2659 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2660 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2661 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
2662 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
2663 | PHY_M_LEDC_INIT_CTRL(7) | | |
2664 | PHY_M_LEDC_STA1_CTRL(7) | | |
2665 | PHY_M_LEDC_STA0_CTRL(7)) | |
2666 | : 0); | |
2667 | ||
2668 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2669 | break; | |
2670 | ||
2671 | default: | |
2672 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
cd28ab6a | 2673 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
793b883e SH |
2674 | on ? PHY_M_LED_MO_DUP(MO_LED_ON) | |
2675 | PHY_M_LED_MO_10(MO_LED_ON) | | |
2676 | PHY_M_LED_MO_100(MO_LED_ON) | | |
cd28ab6a | 2677 | PHY_M_LED_MO_1000(MO_LED_ON) | |
793b883e SH |
2678 | PHY_M_LED_MO_RX(MO_LED_ON) |
2679 | : PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
2680 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
2681 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
cd28ab6a SH |
2682 | PHY_M_LED_MO_1000(MO_LED_OFF) | |
2683 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
2684 | ||
793b883e | 2685 | } |
cd28ab6a SH |
2686 | } |
2687 | ||
2688 | /* blink LED's for finding board */ | |
2689 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
2690 | { | |
2691 | struct sky2_port *sky2 = netdev_priv(dev); | |
2692 | struct sky2_hw *hw = sky2->hw; | |
2693 | unsigned port = sky2->port; | |
793b883e | 2694 | u16 ledctrl, ledover = 0; |
cd28ab6a | 2695 | long ms; |
91c86df5 | 2696 | int interrupted; |
cd28ab6a SH |
2697 | int onoff = 1; |
2698 | ||
793b883e | 2699 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
2700 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
2701 | else | |
2702 | ms = data * 1000; | |
2703 | ||
2704 | /* save initial values */ | |
91c86df5 | 2705 | down(&sky2->phy_sema); |
793b883e SH |
2706 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2707 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2708 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2709 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2710 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2711 | } else { | |
2712 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
2713 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
2714 | } | |
cd28ab6a | 2715 | |
91c86df5 SH |
2716 | interrupted = 0; |
2717 | while (!interrupted && ms > 0) { | |
cd28ab6a SH |
2718 | sky2_led(hw, port, onoff); |
2719 | onoff = !onoff; | |
2720 | ||
91c86df5 SH |
2721 | up(&sky2->phy_sema); |
2722 | interrupted = msleep_interruptible(250); | |
2723 | down(&sky2->phy_sema); | |
2724 | ||
cd28ab6a SH |
2725 | ms -= 250; |
2726 | } | |
2727 | ||
2728 | /* resume regularly scheduled programming */ | |
793b883e SH |
2729 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2730 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2731 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2732 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
2733 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2734 | } else { | |
2735 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
2736 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
2737 | } | |
91c86df5 | 2738 | up(&sky2->phy_sema); |
cd28ab6a SH |
2739 | |
2740 | return 0; | |
2741 | } | |
2742 | ||
2743 | static void sky2_get_pauseparam(struct net_device *dev, | |
2744 | struct ethtool_pauseparam *ecmd) | |
2745 | { | |
2746 | struct sky2_port *sky2 = netdev_priv(dev); | |
2747 | ||
2748 | ecmd->tx_pause = sky2->tx_pause; | |
2749 | ecmd->rx_pause = sky2->rx_pause; | |
2750 | ecmd->autoneg = sky2->autoneg; | |
2751 | } | |
2752 | ||
2753 | static int sky2_set_pauseparam(struct net_device *dev, | |
2754 | struct ethtool_pauseparam *ecmd) | |
2755 | { | |
2756 | struct sky2_port *sky2 = netdev_priv(dev); | |
2757 | int err = 0; | |
2758 | ||
2759 | sky2->autoneg = ecmd->autoneg; | |
2760 | sky2->tx_pause = ecmd->tx_pause != 0; | |
2761 | sky2->rx_pause = ecmd->rx_pause != 0; | |
2762 | ||
1b537565 | 2763 | sky2_phy_reinit(sky2); |
cd28ab6a SH |
2764 | |
2765 | return err; | |
2766 | } | |
2767 | ||
2768 | #ifdef CONFIG_PM | |
2769 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2770 | { | |
2771 | struct sky2_port *sky2 = netdev_priv(dev); | |
2772 | ||
2773 | wol->supported = WAKE_MAGIC; | |
2774 | wol->wolopts = sky2->wol ? WAKE_MAGIC : 0; | |
2775 | } | |
2776 | ||
2777 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2778 | { | |
2779 | struct sky2_port *sky2 = netdev_priv(dev); | |
2780 | struct sky2_hw *hw = sky2->hw; | |
2781 | ||
2782 | if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) | |
2783 | return -EOPNOTSUPP; | |
2784 | ||
2785 | sky2->wol = wol->wolopts == WAKE_MAGIC; | |
2786 | ||
2787 | if (sky2->wol) { | |
2788 | memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN); | |
2789 | ||
2790 | sky2_write16(hw, WOL_CTRL_STAT, | |
2791 | WOL_CTL_ENA_PME_ON_MAGIC_PKT | | |
2792 | WOL_CTL_ENA_MAGIC_PKT_UNIT); | |
2793 | } else | |
2794 | sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT); | |
2795 | ||
2796 | return 0; | |
2797 | } | |
2798 | #endif | |
2799 | ||
fb17358f SH |
2800 | static int sky2_get_coalesce(struct net_device *dev, |
2801 | struct ethtool_coalesce *ecmd) | |
2802 | { | |
2803 | struct sky2_port *sky2 = netdev_priv(dev); | |
2804 | struct sky2_hw *hw = sky2->hw; | |
2805 | ||
2806 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
2807 | ecmd->tx_coalesce_usecs = 0; | |
2808 | else { | |
2809 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
2810 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2811 | } | |
2812 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
2813 | ||
2814 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
2815 | ecmd->rx_coalesce_usecs = 0; | |
2816 | else { | |
2817 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
2818 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2819 | } | |
2820 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
2821 | ||
2822 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
2823 | ecmd->rx_coalesce_usecs_irq = 0; | |
2824 | else { | |
2825 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
2826 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
2827 | } | |
2828 | ||
2829 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
2830 | ||
2831 | return 0; | |
2832 | } | |
2833 | ||
2834 | /* Note: this affect both ports */ | |
2835 | static int sky2_set_coalesce(struct net_device *dev, | |
2836 | struct ethtool_coalesce *ecmd) | |
2837 | { | |
2838 | struct sky2_port *sky2 = netdev_priv(dev); | |
2839 | struct sky2_hw *hw = sky2->hw; | |
2840 | const u32 tmin = sky2_clk2us(hw, 1); | |
2841 | const u32 tmax = 5000; | |
2842 | ||
2843 | if (ecmd->tx_coalesce_usecs != 0 && | |
2844 | (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax)) | |
2845 | return -EINVAL; | |
2846 | ||
2847 | if (ecmd->rx_coalesce_usecs != 0 && | |
2848 | (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax)) | |
2849 | return -EINVAL; | |
2850 | ||
2851 | if (ecmd->rx_coalesce_usecs_irq != 0 && | |
2852 | (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax)) | |
2853 | return -EINVAL; | |
2854 | ||
2855 | if (ecmd->tx_max_coalesced_frames > 0xffff) | |
2856 | return -EINVAL; | |
2857 | if (ecmd->rx_max_coalesced_frames > 0xff) | |
2858 | return -EINVAL; | |
2859 | if (ecmd->rx_max_coalesced_frames_irq > 0xff) | |
2860 | return -EINVAL; | |
2861 | ||
2862 | if (ecmd->tx_coalesce_usecs == 0) | |
2863 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
2864 | else { | |
2865 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
2866 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
2867 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2868 | } | |
2869 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
2870 | ||
2871 | if (ecmd->rx_coalesce_usecs == 0) | |
2872 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
2873 | else { | |
2874 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
2875 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
2876 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2877 | } | |
2878 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
2879 | ||
2880 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
2881 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
2882 | else { | |
d28d4870 | 2883 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
fb17358f SH |
2884 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
2885 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2886 | } | |
2887 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
2888 | return 0; | |
2889 | } | |
2890 | ||
793b883e SH |
2891 | static void sky2_get_ringparam(struct net_device *dev, |
2892 | struct ethtool_ringparam *ering) | |
2893 | { | |
2894 | struct sky2_port *sky2 = netdev_priv(dev); | |
2895 | ||
2896 | ering->rx_max_pending = RX_MAX_PENDING; | |
2897 | ering->rx_mini_max_pending = 0; | |
2898 | ering->rx_jumbo_max_pending = 0; | |
2899 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
2900 | ||
2901 | ering->rx_pending = sky2->rx_pending; | |
2902 | ering->rx_mini_pending = 0; | |
2903 | ering->rx_jumbo_pending = 0; | |
2904 | ering->tx_pending = sky2->tx_pending; | |
2905 | } | |
2906 | ||
2907 | static int sky2_set_ringparam(struct net_device *dev, | |
2908 | struct ethtool_ringparam *ering) | |
2909 | { | |
2910 | struct sky2_port *sky2 = netdev_priv(dev); | |
2911 | int err = 0; | |
2912 | ||
2913 | if (ering->rx_pending > RX_MAX_PENDING || | |
2914 | ering->rx_pending < 8 || | |
2915 | ering->tx_pending < MAX_SKB_TX_LE || | |
2916 | ering->tx_pending > TX_RING_SIZE - 1) | |
2917 | return -EINVAL; | |
2918 | ||
2919 | if (netif_running(dev)) | |
2920 | sky2_down(dev); | |
2921 | ||
2922 | sky2->rx_pending = ering->rx_pending; | |
2923 | sky2->tx_pending = ering->tx_pending; | |
2924 | ||
1b537565 | 2925 | if (netif_running(dev)) { |
793b883e | 2926 | err = sky2_up(dev); |
1b537565 SH |
2927 | if (err) |
2928 | dev_close(dev); | |
6ed995bb SH |
2929 | else |
2930 | sky2_set_multicast(dev); | |
1b537565 | 2931 | } |
793b883e SH |
2932 | |
2933 | return err; | |
2934 | } | |
2935 | ||
793b883e SH |
2936 | static int sky2_get_regs_len(struct net_device *dev) |
2937 | { | |
6e4cbb34 | 2938 | return 0x4000; |
793b883e SH |
2939 | } |
2940 | ||
2941 | /* | |
2942 | * Returns copy of control register region | |
6e4cbb34 | 2943 | * Note: access to the RAM address register set will cause timeouts. |
793b883e SH |
2944 | */ |
2945 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2946 | void *p) | |
2947 | { | |
2948 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2949 | const void __iomem *io = sky2->hw->regs; |
793b883e | 2950 | |
6e4cbb34 | 2951 | BUG_ON(regs->len < B3_RI_WTO_R1); |
793b883e | 2952 | regs->version = 1; |
6e4cbb34 | 2953 | memset(p, 0, regs->len); |
793b883e | 2954 | |
6e4cbb34 SH |
2955 | memcpy_fromio(p, io, B3_RAM_ADDR); |
2956 | ||
2957 | memcpy_fromio(p + B3_RI_WTO_R1, | |
2958 | io + B3_RI_WTO_R1, | |
2959 | regs->len - B3_RI_WTO_R1); | |
793b883e | 2960 | } |
cd28ab6a SH |
2961 | |
2962 | static struct ethtool_ops sky2_ethtool_ops = { | |
793b883e SH |
2963 | .get_settings = sky2_get_settings, |
2964 | .set_settings = sky2_set_settings, | |
2965 | .get_drvinfo = sky2_get_drvinfo, | |
2966 | .get_msglevel = sky2_get_msglevel, | |
2967 | .set_msglevel = sky2_set_msglevel, | |
9a7ae0a9 | 2968 | .nway_reset = sky2_nway_reset, |
793b883e SH |
2969 | .get_regs_len = sky2_get_regs_len, |
2970 | .get_regs = sky2_get_regs, | |
2971 | .get_link = ethtool_op_get_link, | |
2972 | .get_sg = ethtool_op_get_sg, | |
2973 | .set_sg = ethtool_op_set_sg, | |
2974 | .get_tx_csum = ethtool_op_get_tx_csum, | |
2975 | .set_tx_csum = ethtool_op_set_tx_csum, | |
2976 | .get_tso = ethtool_op_get_tso, | |
2977 | .set_tso = ethtool_op_set_tso, | |
2978 | .get_rx_csum = sky2_get_rx_csum, | |
2979 | .set_rx_csum = sky2_set_rx_csum, | |
2980 | .get_strings = sky2_get_strings, | |
fb17358f SH |
2981 | .get_coalesce = sky2_get_coalesce, |
2982 | .set_coalesce = sky2_set_coalesce, | |
793b883e SH |
2983 | .get_ringparam = sky2_get_ringparam, |
2984 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
2985 | .get_pauseparam = sky2_get_pauseparam, |
2986 | .set_pauseparam = sky2_set_pauseparam, | |
2987 | #ifdef CONFIG_PM | |
793b883e SH |
2988 | .get_wol = sky2_get_wol, |
2989 | .set_wol = sky2_set_wol, | |
cd28ab6a | 2990 | #endif |
793b883e | 2991 | .phys_id = sky2_phys_id, |
cd28ab6a SH |
2992 | .get_stats_count = sky2_get_stats_count, |
2993 | .get_ethtool_stats = sky2_get_ethtool_stats, | |
2995bfb7 | 2994 | .get_perm_addr = ethtool_op_get_perm_addr, |
cd28ab6a SH |
2995 | }; |
2996 | ||
2997 | /* Initialize network device */ | |
2998 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
2999 | unsigned port, int highmem) | |
3000 | { | |
3001 | struct sky2_port *sky2; | |
3002 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
3003 | ||
3004 | if (!dev) { | |
3005 | printk(KERN_ERR "sky2 etherdev alloc failed"); | |
3006 | return NULL; | |
3007 | } | |
3008 | ||
3009 | SET_MODULE_OWNER(dev); | |
3010 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
ef743d33 | 3011 | dev->irq = hw->pdev->irq; |
cd28ab6a SH |
3012 | dev->open = sky2_up; |
3013 | dev->stop = sky2_down; | |
ef743d33 | 3014 | dev->do_ioctl = sky2_ioctl; |
cd28ab6a SH |
3015 | dev->hard_start_xmit = sky2_xmit_frame; |
3016 | dev->get_stats = sky2_get_stats; | |
3017 | dev->set_multicast_list = sky2_set_multicast; | |
3018 | dev->set_mac_address = sky2_set_mac_address; | |
3019 | dev->change_mtu = sky2_change_mtu; | |
3020 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
3021 | dev->tx_timeout = sky2_tx_timeout; | |
3022 | dev->watchdog_timeo = TX_WATCHDOG; | |
3023 | if (port == 0) | |
3024 | dev->poll = sky2_poll; | |
3025 | dev->weight = NAPI_WEIGHT; | |
3026 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3027 | dev->poll_controller = sky2_netpoll; | |
3028 | #endif | |
cd28ab6a SH |
3029 | |
3030 | sky2 = netdev_priv(dev); | |
3031 | sky2->netdev = dev; | |
3032 | sky2->hw = hw; | |
3033 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
3034 | ||
3035 | spin_lock_init(&sky2->tx_lock); | |
3036 | /* Auto speed and flow control */ | |
3037 | sky2->autoneg = AUTONEG_ENABLE; | |
585b5601 | 3038 | sky2->tx_pause = 1; |
cd28ab6a SH |
3039 | sky2->rx_pause = 1; |
3040 | sky2->duplex = -1; | |
3041 | sky2->speed = -1; | |
3042 | sky2->advertising = sky2_supported_modes(hw); | |
75d070c5 SH |
3043 | |
3044 | /* Receive checksum disabled for Yukon XL | |
3045 | * because of observed problems with incorrect | |
3046 | * values when multiple packets are received in one interrupt | |
3047 | */ | |
3048 | sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL); | |
3049 | ||
91c86df5 SH |
3050 | INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2); |
3051 | init_MUTEX(&sky2->phy_sema); | |
793b883e SH |
3052 | sky2->tx_pending = TX_DEF_PENDING; |
3053 | sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING; | |
734d1868 | 3054 | sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN); |
cd28ab6a SH |
3055 | |
3056 | hw->dev[port] = dev; | |
3057 | ||
3058 | sky2->port = port; | |
3059 | ||
5a5b1ea0 SH |
3060 | dev->features |= NETIF_F_LLTX; |
3061 | if (hw->chip_id != CHIP_ID_YUKON_EC_U) | |
3062 | dev->features |= NETIF_F_TSO; | |
cd28ab6a SH |
3063 | if (highmem) |
3064 | dev->features |= NETIF_F_HIGHDMA; | |
793b883e | 3065 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a | 3066 | |
d1f13708 SH |
3067 | #ifdef SKY2_VLAN_TAG_USED |
3068 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
3069 | dev->vlan_rx_register = sky2_vlan_rx_register; | |
3070 | dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid; | |
3071 | #endif | |
3072 | ||
cd28ab6a | 3073 | /* read the mac address */ |
793b883e | 3074 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 3075 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a SH |
3076 | |
3077 | /* device is off until link detection */ | |
3078 | netif_carrier_off(dev); | |
3079 | netif_stop_queue(dev); | |
3080 | ||
3081 | return dev; | |
3082 | } | |
3083 | ||
28bd181a | 3084 | static void __devinit sky2_show_addr(struct net_device *dev) |
cd28ab6a SH |
3085 | { |
3086 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3087 | ||
3088 | if (netif_msg_probe(sky2)) | |
3089 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3090 | dev->name, | |
3091 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3092 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3093 | } | |
3094 | ||
4d52b48b SH |
3095 | /* Handle software interrupt used during MSI test */ |
3096 | static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id, | |
3097 | struct pt_regs *regs) | |
3098 | { | |
3099 | struct sky2_hw *hw = dev_id; | |
3100 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
3101 | ||
3102 | if (status == 0) | |
3103 | return IRQ_NONE; | |
3104 | ||
3105 | if (status & Y2_IS_IRQ_SW) { | |
3106 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3107 | hw->msi = 1; | |
3108 | } | |
3109 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
3110 | ||
3111 | sky2_read32(hw, B0_IMSK); | |
3112 | return IRQ_HANDLED; | |
3113 | } | |
3114 | ||
3115 | /* Test interrupt path by forcing a a software IRQ */ | |
3116 | static int __devinit sky2_test_msi(struct sky2_hw *hw) | |
3117 | { | |
3118 | struct pci_dev *pdev = hw->pdev; | |
3119 | int i, err; | |
3120 | ||
3121 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); | |
3122 | ||
3123 | err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw); | |
3124 | if (err) { | |
3125 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3126 | pci_name(pdev), pdev->irq); | |
3127 | return err; | |
3128 | } | |
3129 | ||
3130 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); | |
3131 | wmb(); | |
3132 | ||
3133 | for (i = 0; i < 10; i++) { | |
3134 | barrier(); | |
3135 | if (hw->msi) | |
3136 | goto found; | |
3137 | mdelay(1); | |
3138 | } | |
3139 | ||
3140 | err = -EOPNOTSUPP; | |
3141 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3142 | found: | |
3143 | sky2_write32(hw, B0_IMSK, 0); | |
3144 | ||
3145 | free_irq(pdev->irq, hw); | |
3146 | ||
3147 | return err; | |
3148 | } | |
3149 | ||
cd28ab6a SH |
3150 | static int __devinit sky2_probe(struct pci_dev *pdev, |
3151 | const struct pci_device_id *ent) | |
3152 | { | |
793b883e | 3153 | struct net_device *dev, *dev1 = NULL; |
cd28ab6a | 3154 | struct sky2_hw *hw; |
5afa0a9c | 3155 | int err, pm_cap, using_dac = 0; |
cd28ab6a | 3156 | |
793b883e SH |
3157 | err = pci_enable_device(pdev); |
3158 | if (err) { | |
cd28ab6a SH |
3159 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
3160 | pci_name(pdev)); | |
3161 | goto err_out; | |
3162 | } | |
3163 | ||
793b883e SH |
3164 | err = pci_request_regions(pdev, DRV_NAME); |
3165 | if (err) { | |
cd28ab6a SH |
3166 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
3167 | pci_name(pdev)); | |
793b883e | 3168 | goto err_out; |
cd28ab6a SH |
3169 | } |
3170 | ||
3171 | pci_set_master(pdev); | |
3172 | ||
5afa0a9c SH |
3173 | /* Find power-management capability. */ |
3174 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
3175 | if (pm_cap == 0) { | |
3176 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
3177 | "aborting.\n"); | |
3178 | err = -EIO; | |
3179 | goto err_out_free_regions; | |
3180 | } | |
3181 | ||
d1f3d4dd SH |
3182 | if (sizeof(dma_addr_t) > sizeof(u32) && |
3183 | !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { | |
3184 | using_dac = 1; | |
3185 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
3186 | if (err < 0) { | |
3187 | printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA " | |
3188 | "for consistent allocations\n", pci_name(pdev)); | |
3189 | goto err_out_free_regions; | |
3190 | } | |
cd28ab6a | 3191 | |
d1f3d4dd | 3192 | } else { |
cd28ab6a SH |
3193 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
3194 | if (err) { | |
3195 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3196 | pci_name(pdev)); | |
3197 | goto err_out_free_regions; | |
3198 | } | |
3199 | } | |
d1f3d4dd | 3200 | |
cd28ab6a | 3201 | #ifdef __BIG_ENDIAN |
d571b694 | 3202 | /* byte swap descriptors in hardware */ |
cd28ab6a SH |
3203 | { |
3204 | u32 reg; | |
3205 | ||
3206 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
3207 | reg |= PCI_REV_DESC; | |
3208 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
3209 | } | |
3210 | #endif | |
3211 | ||
3212 | err = -ENOMEM; | |
6aad85d6 | 3213 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
cd28ab6a SH |
3214 | if (!hw) { |
3215 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
3216 | pci_name(pdev)); | |
3217 | goto err_out_free_regions; | |
3218 | } | |
3219 | ||
cd28ab6a | 3220 | hw->pdev = pdev; |
cd28ab6a SH |
3221 | |
3222 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3223 | if (!hw->regs) { | |
3224 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
3225 | pci_name(pdev)); | |
3226 | goto err_out_free_hw; | |
3227 | } | |
5afa0a9c | 3228 | hw->pm_cap = pm_cap; |
cd28ab6a | 3229 | |
08c06d8a SH |
3230 | /* ring for status responses */ |
3231 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | |
3232 | &hw->st_dma); | |
3233 | if (!hw->st_le) | |
3234 | goto err_out_iounmap; | |
3235 | ||
cd28ab6a SH |
3236 | err = sky2_reset(hw); |
3237 | if (err) | |
793b883e | 3238 | goto err_out_iounmap; |
cd28ab6a | 3239 | |
5f4f9dc1 SH |
3240 | printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n", |
3241 | DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq, | |
92f965e8 | 3242 | yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], |
793b883e | 3243 | hw->chip_id, hw->chip_rev); |
cd28ab6a | 3244 | |
793b883e SH |
3245 | dev = sky2_init_netdev(hw, 0, using_dac); |
3246 | if (!dev) | |
cd28ab6a SH |
3247 | goto err_out_free_pci; |
3248 | ||
793b883e SH |
3249 | err = register_netdev(dev); |
3250 | if (err) { | |
cd28ab6a SH |
3251 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
3252 | pci_name(pdev)); | |
3253 | goto err_out_free_netdev; | |
3254 | } | |
3255 | ||
3256 | sky2_show_addr(dev); | |
3257 | ||
3258 | if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { | |
3259 | if (register_netdev(dev1) == 0) | |
3260 | sky2_show_addr(dev1); | |
3261 | else { | |
3262 | /* Failure to register second port need not be fatal */ | |
793b883e SH |
3263 | printk(KERN_WARNING PFX |
3264 | "register of second port failed\n"); | |
cd28ab6a SH |
3265 | hw->dev[1] = NULL; |
3266 | free_netdev(dev1); | |
3267 | } | |
3268 | } | |
3269 | ||
4d52b48b SH |
3270 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
3271 | err = sky2_test_msi(hw); | |
3272 | if (err == -EOPNOTSUPP) { | |
3273 | /* MSI test failed, go back to INTx mode */ | |
3274 | printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " | |
3275 | "switching to INTx mode. Please report this failure to " | |
3276 | "the PCI maintainer and include system chipset information.\n", | |
3277 | pci_name(pdev)); | |
3278 | pci_disable_msi(pdev); | |
3279 | } | |
3280 | else if (err) | |
3281 | goto err_out_unregister; | |
3282 | } | |
3283 | ||
db992c97 SH |
3284 | err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ | SA_SAMPLE_RANDOM, |
3285 | DRV_NAME, hw); | |
793b883e SH |
3286 | if (err) { |
3287 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3288 | pci_name(pdev), pdev->irq); | |
3289 | goto err_out_unregister; | |
3290 | } | |
3291 | ||
3292 | hw->intr_mask = Y2_IS_BASE; | |
3293 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
3294 | ||
3295 | pci_set_drvdata(pdev, hw); | |
3296 | ||
cd28ab6a SH |
3297 | return 0; |
3298 | ||
793b883e | 3299 | err_out_unregister: |
4d52b48b SH |
3300 | if (hw->msi) |
3301 | pci_disable_msi(pdev); | |
793b883e SH |
3302 | if (dev1) { |
3303 | unregister_netdev(dev1); | |
3304 | free_netdev(dev1); | |
3305 | } | |
3306 | unregister_netdev(dev); | |
cd28ab6a SH |
3307 | err_out_free_netdev: |
3308 | free_netdev(dev); | |
cd28ab6a | 3309 | err_out_free_pci: |
793b883e | 3310 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
3311 | pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
3312 | err_out_iounmap: | |
3313 | iounmap(hw->regs); | |
3314 | err_out_free_hw: | |
3315 | kfree(hw); | |
3316 | err_out_free_regions: | |
3317 | pci_release_regions(pdev); | |
cd28ab6a | 3318 | pci_disable_device(pdev); |
cd28ab6a SH |
3319 | err_out: |
3320 | return err; | |
3321 | } | |
3322 | ||
3323 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
3324 | { | |
793b883e | 3325 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3326 | struct net_device *dev0, *dev1; |
3327 | ||
793b883e | 3328 | if (!hw) |
cd28ab6a SH |
3329 | return; |
3330 | ||
cd28ab6a | 3331 | dev0 = hw->dev[0]; |
793b883e SH |
3332 | dev1 = hw->dev[1]; |
3333 | if (dev1) | |
3334 | unregister_netdev(dev1); | |
cd28ab6a SH |
3335 | unregister_netdev(dev0); |
3336 | ||
793b883e | 3337 | sky2_write32(hw, B0_IMSK, 0); |
5afa0a9c | 3338 | sky2_set_power_state(hw, PCI_D3hot); |
cd28ab6a | 3339 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 3340 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 3341 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
3342 | |
3343 | free_irq(pdev->irq, hw); | |
4d52b48b SH |
3344 | if (hw->msi) |
3345 | pci_disable_msi(pdev); | |
793b883e | 3346 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
3347 | pci_release_regions(pdev); |
3348 | pci_disable_device(pdev); | |
793b883e | 3349 | |
cd28ab6a SH |
3350 | if (dev1) |
3351 | free_netdev(dev1); | |
3352 | free_netdev(dev0); | |
3353 | iounmap(hw->regs); | |
3354 | kfree(hw); | |
5afa0a9c | 3355 | |
cd28ab6a SH |
3356 | pci_set_drvdata(pdev, NULL); |
3357 | } | |
3358 | ||
3359 | #ifdef CONFIG_PM | |
3360 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
3361 | { | |
793b883e | 3362 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
5afa0a9c | 3363 | int i; |
cd28ab6a SH |
3364 | |
3365 | for (i = 0; i < 2; i++) { | |
3366 | struct net_device *dev = hw->dev[i]; | |
3367 | ||
3368 | if (dev) { | |
5afa0a9c SH |
3369 | if (!netif_running(dev)) |
3370 | continue; | |
3371 | ||
3372 | sky2_down(dev); | |
cd28ab6a | 3373 | netif_device_detach(dev); |
cd28ab6a SH |
3374 | } |
3375 | } | |
3376 | ||
5afa0a9c | 3377 | return sky2_set_power_state(hw, pci_choose_state(pdev, state)); |
cd28ab6a SH |
3378 | } |
3379 | ||
3380 | static int sky2_resume(struct pci_dev *pdev) | |
3381 | { | |
793b883e | 3382 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
08c06d8a | 3383 | int i, err; |
cd28ab6a | 3384 | |
cd28ab6a SH |
3385 | pci_restore_state(pdev); |
3386 | pci_enable_wake(pdev, PCI_D0, 0); | |
08c06d8a SH |
3387 | err = sky2_set_power_state(hw, PCI_D0); |
3388 | if (err) | |
3389 | goto out; | |
cd28ab6a | 3390 | |
08c06d8a SH |
3391 | err = sky2_reset(hw); |
3392 | if (err) | |
3393 | goto out; | |
cd28ab6a SH |
3394 | |
3395 | for (i = 0; i < 2; i++) { | |
3396 | struct net_device *dev = hw->dev[i]; | |
08c06d8a SH |
3397 | if (dev && netif_running(dev)) { |
3398 | netif_device_attach(dev); | |
3399 | err = sky2_up(dev); | |
3400 | if (err) { | |
3401 | printk(KERN_ERR PFX "%s: could not up: %d\n", | |
3402 | dev->name, err); | |
3403 | dev_close(dev); | |
3404 | break; | |
5afa0a9c | 3405 | } |
cd28ab6a SH |
3406 | } |
3407 | } | |
08c06d8a SH |
3408 | out: |
3409 | return err; | |
cd28ab6a SH |
3410 | } |
3411 | #endif | |
3412 | ||
3413 | static struct pci_driver sky2_driver = { | |
793b883e SH |
3414 | .name = DRV_NAME, |
3415 | .id_table = sky2_id_table, | |
3416 | .probe = sky2_probe, | |
3417 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 3418 | #ifdef CONFIG_PM |
793b883e SH |
3419 | .suspend = sky2_suspend, |
3420 | .resume = sky2_resume, | |
cd28ab6a SH |
3421 | #endif |
3422 | }; | |
3423 | ||
3424 | static int __init sky2_init_module(void) | |
3425 | { | |
50241c4c | 3426 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
3427 | } |
3428 | ||
3429 | static void __exit sky2_cleanup_module(void) | |
3430 | { | |
3431 | pci_unregister_driver(&sky2_driver); | |
3432 | } | |
3433 | ||
3434 | module_init(sky2_init_module); | |
3435 | module_exit(sky2_cleanup_module); | |
3436 | ||
3437 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
3438 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
3439 | MODULE_LICENSE("GPL"); | |
5f4f9dc1 | 3440 | MODULE_VERSION(DRV_VERSION); |