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sky2: use upper/lower 32 bits
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
deeb16dc 53#define DRV_VERSION "1.24"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 66
67#define TX_RING_SIZE 512
e9c1be80 68#define TX_DEF_PENDING 128
b19666d9 69#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH		 78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33
SH		 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH		 259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH		 294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH		 319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
0ea065e5 324 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH		 337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH		 358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
0ea065e5 366 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH		 373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH		 380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH		 386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH		 402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a 410
0ea065e5 411 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
b89165f2
SH		 426 } else { /* special defines for FIBER (88E1040S only) */
427 if (sky2->advertising & ADVERTISED_1000baseT_Full)
428 adv |= PHY_M_AN_1000X_AFD;
429 if (sky2->advertising & ADVERTISED_1000baseT_Half)
430 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 431 }
cd28ab6a
SH		 432
433 /* Restart Auto-negotiation */
434 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
435 } else {
436 /* forced speed/duplex settings */
437 ct1000 = PHY_M_1000C_MSE;
438
0ea065e5
SH		 439 /* Disable auto update for duplex flow control and duplex */
440 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 441
442 switch (sky2->speed) {
443 case SPEED_1000:
444 ctrl |= PHY_CT_SP1000;
2eaba1a2 445 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 446 break;
447 case SPEED_100:
448 ctrl |= PHY_CT_SP100;
2eaba1a2 449 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 450 break;
451 }
452
2eaba1a2
SH		 453 if (sky2->duplex == DUPLEX_FULL) {
454 reg |= GM_GPCR_DUP_FULL;
455 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 456 } else if (sky2->speed < SPEED_1000)
457 sky2->flow_mode = FC_NONE;
0ea065e5 458 }
2eaba1a2 459
0ea065e5
SH		 460 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
461 if (sky2_is_copper(hw))
462 adv |= copper_fc_adv[sky2->flow_mode];
463 else
464 adv |= fiber_fc_adv[sky2->flow_mode];
465 } else {
466 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 467 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 468
469 /* Forward pause packets to GMAC? */
16ad91e1 470 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 471 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
472 else
473 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 474 }
475
2eaba1a2
SH		 476 gma_write16(hw, port, GM_GP_CTRL, reg);
477
05745c4a 478 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 479 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
480
481 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
482 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
483
484 /* Setup Phy LED's */
485 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
486 ledover = 0;
487
488 switch (hw->chip_id) {
489 case CHIP_ID_YUKON_FE:
490 /* on 88E3082 these bits are at 11..9 (shifted left) */
491 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
492
493 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
494
495 /* delete ACT LED control bits */
496 ctrl &= ~PHY_M_FELP_LED1_MSK;
497 /* change ACT LED control to blink mode */
498 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
499 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
500 break;
501
05745c4a
SH		 502 case CHIP_ID_YUKON_FE_P:
503 /* Enable Link Partner Next Page */
504 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
505 ctrl |= PHY_M_PC_ENA_LIP_NP;
506
507 /* disable Energy Detect and enable scrambler */
508 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
509 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
510
511 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
512 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
513 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
514 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
515
516 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
517 break;
518
cd28ab6a 519 case CHIP_ID_YUKON_XL:
793b883e 520 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 521
522 /* select page 3 to access LED control register */
523 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
524
525 /* set LED Function Control register */
ed6d32c7
SH		 526 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
527 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
528 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
529 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
530 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 531
532 /* set Polarity Control register */
533 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 534 (PHY_M_POLC_LS1_P_MIX(4) |
535 PHY_M_POLC_IS0_P_MIX(4) |
536 PHY_M_POLC_LOS_CTRL(2) |
537 PHY_M_POLC_INIT_CTRL(2) |
538 PHY_M_POLC_STA1_CTRL(2) |
539 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 540
541 /* restore page register */
793b883e 542 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 543 break;
93745494 544
ed6d32c7 545 case CHIP_ID_YUKON_EC_U:
93745494 546 case CHIP_ID_YUKON_EX:
ed4d4161 547 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 548 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
549
550 /* select page 3 to access LED control register */
551 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
552
553 /* set LED Function Control register */
554 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
555 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
556 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
557 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
558 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
559
560 /* set Blink Rate in LED Timer Control Register */
561 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
562 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
563 /* restore page register */
564 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
565 break;
cd28ab6a
SH		 566
567 default:
568 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
569 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 570
cd28ab6a 571 /* turn off the Rx LED (LED_RX) */
a84d0a3d 572 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 573 }
574
0ce8b98d 575 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 576 /* apply fixes in PHY AFE */
ed6d32c7
SH		 577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
578
977bdf06 579 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 580 gm_phy_write(hw, port, 0x18, 0xaa99);
581 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 582
0ce8b98d
SH		 583 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
584 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
585 gm_phy_write(hw, port, 0x18, 0xa204);
586 gm_phy_write(hw, port, 0x17, 0x2002);
587 }
977bdf06
SH		 588
589 /* set page register to 0 */
9467a8fc 590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 591 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
592 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
593 /* apply workaround for integrated resistors calibration */
594 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
595 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 596 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
597 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 598 /* no effect on Yukon-XL */
977bdf06 599 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 600
0ea065e5
SH		 601 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
602 || sky2->speed == SPEED_100) {
977bdf06 603 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 604 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 605 }
cd28ab6a 606
977bdf06
SH		 607 if (ledover)
608 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
609
610 }
2eaba1a2 611
d571b694 612 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 613 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
615 else
616 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
617}
618
b96936da
SH		 619static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
620static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
621
622static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 623{
624 u32 reg1;
d3bcfbeb 625
82637e80 626 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 627 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 628 reg1 &= ~phy_power[port];
d3bcfbeb 629
b96936da 630 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 631 reg1 |= coma_mode[port];
632
b32f40c4 633 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 634 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
635 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 636
637 if (hw->chip_id == CHIP_ID_YUKON_FE)
638 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
639 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
640 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 641}
167f53d0 642
b96936da
SH		 643static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
644{
645 u32 reg1;
db99b988
SH		 646 u16 ctrl;
647
648 /* release GPHY Control reset */
649 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
650
651 /* release GMAC reset */
652 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
653
654 if (hw->flags & SKY2_HW_NEWER_PHY) {
655 /* select page 2 to access MAC control register */
656 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
657
658 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
659 /* allow GMII Power Down */
660 ctrl &= ~PHY_M_MAC_GMIF_PUP;
661 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
662
663 /* set page register back to 0 */
664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
665 }
666
667 /* setup General Purpose Control Register */
668 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 669 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
670 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
671 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 672
673 if (hw->chip_id != CHIP_ID_YUKON_EC) {
674 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 675 /* select page 2 to access MAC control register */
676 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 677
e484d5f5 678 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 679 /* enable Power Down */
680 ctrl |= PHY_M_PC_POW_D_ENA;
681 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 682
683 /* set page register back to 0 */
684 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 685 }
686
687 /* set IEEE compatible Power Down Mode (dev. #4.99) */
688 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
689 }
b96936da
SH		 690
691 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
692 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 693 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 694 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
695 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 696}
697
1b537565
SH		 698/* Force a renegotiation */
699static void sky2_phy_reinit(struct sky2_port *sky2)
700{
e07b1aa8 701 spin_lock_bh(&sky2->phy_lock);
1b537565 702 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 703 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 704}
705
e3173832
SH		 706/* Put device in state to listen for Wake On Lan */
707static void sky2_wol_init(struct sky2_port *sky2)
708{
709 struct sky2_hw *hw = sky2->hw;
710 unsigned port = sky2->port;
711 enum flow_control save_mode;
712 u16 ctrl;
713 u32 reg1;
714
715 /* Bring hardware out of reset */
716 sky2_write16(hw, B0_CTST, CS_RST_CLR);
717 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
718
719 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
720 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
721
722 /* Force to 10/100
723 * sky2_reset will re-enable on resume
724 */
725 save_mode = sky2->flow_mode;
726 ctrl = sky2->advertising;
727
728 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
729 sky2->flow_mode = FC_NONE;
b96936da
SH		 730
731 spin_lock_bh(&sky2->phy_lock);
732 sky2_phy_power_up(hw, port);
733 sky2_phy_init(hw, port);
734 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 735
736 sky2->flow_mode = save_mode;
737 sky2->advertising = ctrl;
738
739 /* Set GMAC to no flow control and auto update for speed/duplex */
740 gma_write16(hw, port, GM_GP_CTRL,
741 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
742 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
743
744 /* Set WOL address */
745 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
746 sky2->netdev->dev_addr, ETH_ALEN);
747
748 /* Turn on appropriate WOL control bits */
749 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
750 ctrl = 0;
751 if (sky2->wol & WAKE_PHY)
752 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
753 else
754 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
755
756 if (sky2->wol & WAKE_MAGIC)
757 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
758 else
759 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
760
761 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
762 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
763
764 /* Turn on legacy PCI-Express PME mode */
b32f40c4 765 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 766 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 767 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 768
769 /* block receiver */
770 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
771
772}
773
69161611
SH		 774static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
775{
05745c4a
SH		 776 struct net_device *dev = hw->dev[port];
777
ed4d4161
SH		 778 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
779 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
780 hw->chip_id == CHIP_ID_YUKON_FE_P ||
781 hw->chip_id == CHIP_ID_YUKON_SUPR) {
782 /* Yukon-Extreme B0 and further Extreme devices */
783 /* enable Store & Forward mode for TX */
05745c4a 784
ed4d4161
SH		 785 if (dev->mtu <= ETH_DATA_LEN)
786 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
787 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 788
ed4d4161
SH		 789 else
790 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
791 TX_JUMBO_ENA| TX_STFW_ENA);
792 } else {
793 if (dev->mtu <= ETH_DATA_LEN)
794 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
795 else {
796 /* set Tx GMAC FIFO Almost Empty Threshold */
797 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
798 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 799
ed4d4161
SH		 800 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
801
802 /* Can't do offload because of lack of store/forward */
803 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
804 }
69161611
SH		 805 }
806}
807
cd28ab6a
SH		 808static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
809{
810 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
811 u16 reg;
25cccecc 812 u32 rx_reg;
cd28ab6a
SH		 813 int i;
814 const u8 *addr = hw->dev[port]->dev_addr;
815
f350339c
SH		 816 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
817 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 818
819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
820
793b883e 821 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 822 /* WA DEV_472 -- looks like crossed wires on port 2 */
823 /* clear GMAC 1 Control reset */
824 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
825 do {
826 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
827 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
828 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
829 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
830 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
831 }
832
793b883e 833 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 834
2eaba1a2
SH		 835 /* Enable Transmit FIFO Underrun */
836 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
837
e07b1aa8 838 spin_lock_bh(&sky2->phy_lock);
b96936da 839 sky2_phy_power_up(hw, port);
cd28ab6a 840 sky2_phy_init(hw, port);
e07b1aa8 841 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 842
843 /* MIB clear */
844 reg = gma_read16(hw, port, GM_PHY_ADDR);
845 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
846
43f2f104
SH		 847 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
848 gma_read16(hw, port, i);
cd28ab6a
SH		 849 gma_write16(hw, port, GM_PHY_ADDR, reg);
850
851 /* transmit control */
852 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
853
854 /* receive control reg: unicast + multicast + no FCS */
855 gma_write16(hw, port, GM_RX_CTRL,
793b883e 856 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 857
858 /* transmit flow control */
859 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
860
861 /* transmit parameter */
862 gma_write16(hw, port, GM_TX_PARAM,
863 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
864 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
865 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
866 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
867
868 /* serial mode register */
869 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 870 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 871
6b1a3aef 872 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 873 reg |= GM_SMOD_JUMBO_ENA;
874
875 gma_write16(hw, port, GM_SERIAL_MODE, reg);
876
cd28ab6a
SH		 877 /* virtual address for data */
878 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
879
793b883e
SH		 880 /* physical address: used for pause frames */
881 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
882
883 /* ignore counter overflows */
cd28ab6a
SH		 884 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
885 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
886 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
887
888 /* Configure Rx MAC FIFO */
889 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 890 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 891 if (hw->chip_id == CHIP_ID_YUKON_EX ||
892 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 893 rx_reg |= GMF_RX_OVER_ON;
69161611 894
25cccecc 895 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 896
798fdd07
SH		 897 if (hw->chip_id == CHIP_ID_YUKON_XL) {
898 /* Hardware errata - clear flush mask */
899 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
900 } else {
901 /* Flush Rx MAC FIFO on any flow control or error */
902 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
903 }
cd28ab6a 904
8df9a876 905 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 906 reg = RX_GMF_FL_THR_DEF + 1;
907 /* Another magic mystery workaround from sk98lin */
908 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
909 hw->chip_rev == CHIP_REV_YU_FE2_A0)
910 reg = 0x178;
911 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 912
913 /* Configure Tx MAC FIFO */
914 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
915 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 916
e0c28116 917 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 918 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 919 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 920 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 921
69161611 922 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 923 }
924
e970d1f8
SH		 925 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
926 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
927 /* disable dynamic watermark */
928 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
929 reg &= ~TX_DYN_WM_ENA;
930 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
931 }
cd28ab6a
SH		 932}
933
67712901
SH		 934/* Assign Ram Buffer allocation to queue */
935static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 936{
67712901
SH		 937 u32 end;
938
939 /* convert from K bytes to qwords used for hw register */
940 start *= 1024/8;
941 space *= 1024/8;
942 end = start + space - 1;
793b883e 943
cd28ab6a
SH		 944 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
945 sky2_write32(hw, RB_ADDR(q, RB_START), start);
946 sky2_write32(hw, RB_ADDR(q, RB_END), end);
947 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
948 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
949
950 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 951 u32 tp = space - space/4;
793b883e 952
1c28f6ba
SH		 953 /* On receive queue's set the thresholds
954 * give receiver priority when > 3/4 full
955 * send pause when down to 2K
956 */
957 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
958 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 959
1c28f6ba
SH		 960 tp = space - 2048/8;
961 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
962 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 963 } else {
964 /* Enable store & forward on Tx queue's because
965 * Tx FIFO is only 1K on Yukon
966 */
967 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
968 }
969
970 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 971 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 972}
973
cd28ab6a 974/* Setup Bus Memory Interface */
af4ed7e6 975static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 976{
977 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
978 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
979 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 980 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 981}
982
cd28ab6a
SH		 983/* Setup prefetch unit registers. This is the interface between
984 * hardware and driver list elements
985 */
8cc048e3 986static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 987 dma_addr_t addr, u32 last)
cd28ab6a 988{
cd28ab6a
SH		 989 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
990 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 991 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
992 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 993 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
994 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 995
996 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 997}
998
9b289c33 999static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1000{
9b289c33 1001 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1002
9b289c33 1003 *slot = RING_NEXT(*slot, TX_RING_SIZE);
291ea614 1004 le->ctrl = 0;
793b883e
SH		 1005 return le;
1006}
cd28ab6a 1007
88f5f0ca
SH		 1008static void tx_init(struct sky2_port *sky2)
1009{
1010 struct sky2_tx_le *le;
1011
1012 sky2->tx_prod = sky2->tx_cons = 0;
1013 sky2->tx_tcpsum = 0;
1014 sky2->tx_last_mss = 0;
1015
9b289c33 1016 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1017 le->addr = 0;
1018 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1019}
1020
291ea614
SH		 1021static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1022 struct sky2_tx_le *le)
1023{
1024 return sky2->tx_ring + (le - sky2->tx_le);
1025}
1026
290d4de5
SH		 1027/* Update chip's next pointer */
1028static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1029{
50432cb5 1030 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1031 wmb();
50432cb5
SH		 1032 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1033
1034 /* Synchronize I/O on since next processor may write to tail */
1035 mmiowb();
cd28ab6a
SH		 1036}
1037
793b883e 1038
cd28ab6a
SH		 1039static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1040{
1041 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1042 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1043 le->ctrl = 0;
cd28ab6a
SH		 1044 return le;
1045}
1046
14d0263f
SH		 1047/* Build description to hardware for one receive segment */
1048static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1049 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1050{
1051 struct sky2_rx_le *le;
1052
86c6887e 1053 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1054 le = sky2_next_rx(sky2);
86c6887e 1055 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1056 le->opcode = OP_ADDR64 | HW_OWNER;
1057 }
793b883e 1058
cd28ab6a 1059 le = sky2_next_rx(sky2);
d6e74b6b 1060 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1061 le->length = cpu_to_le16(len);
14d0263f 1062 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1063}
1064
14d0263f
SH		 1065/* Build description to hardware for one possibly fragmented skb */
1066static void sky2_rx_submit(struct sky2_port *sky2,
1067 const struct rx_ring_info *re)
1068{
1069 int i;
1070
1071 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1072
1073 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1074 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1075}
1076
1077
454e6cb6 1078static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1079 unsigned size)
1080{
1081 struct sk_buff *skb = re->skb;
1082 int i;
1083
1084 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1085 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1086 return -EIO;
1087
14d0263f
SH		 1088 pci_unmap_len_set(re, data_size, size);
1089
1090 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1091 re->frag_addr[i] = pci_map_page(pdev,
1092 skb_shinfo(skb)->frags[i].page,
1093 skb_shinfo(skb)->frags[i].page_offset,
1094 skb_shinfo(skb)->frags[i].size,
1095 PCI_DMA_FROMDEVICE);
454e6cb6 1096 return 0;
14d0263f
SH		 1097}
1098
1099static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1100{
1101 struct sk_buff *skb = re->skb;
1102 int i;
1103
1104 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1105 PCI_DMA_FROMDEVICE);
1106
1107 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1108 pci_unmap_page(pdev, re->frag_addr[i],
1109 skb_shinfo(skb)->frags[i].size,
1110 PCI_DMA_FROMDEVICE);
1111}
793b883e 1112
cd28ab6a
SH		 1113/* Tell chip where to start receive checksum.
1114 * Actually has two checksums, but set both same to avoid possible byte
1115 * order problems.
1116 */
793b883e 1117static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1118{
ea76e635 1119 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1120
ea76e635
SH		 1121 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1122 le->ctrl = 0;
1123 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1124
ea76e635
SH		 1125 sky2_write32(sky2->hw,
1126 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1127 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1128 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1129}
1130
6b1a3aef
SH		 1131/*
1132 * The RX Stop command will not work for Yukon-2 if the BMU does not
1133 * reach the end of packet and since we can't make sure that we have
1134 * incoming data, we must reset the BMU while it is not doing a DMA
1135 * transfer. Since it is possible that the RX path is still active,
1136 * the RX RAM buffer will be stopped first, so any possible incoming
1137 * data will not trigger a DMA. After the RAM buffer is stopped, the
1138 * BMU is polled until any DMA in progress is ended and only then it
1139 * will be reset.
1140 */
1141static void sky2_rx_stop(struct sky2_port *sky2)
1142{
1143 struct sky2_hw *hw = sky2->hw;
1144 unsigned rxq = rxqaddr[sky2->port];
1145 int i;
1146
1147 /* disable the RAM Buffer receive queue */
1148 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1149
1150 for (i = 0; i < 0xffff; i++)
1151 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1152 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1153 goto stopped;
1154
1155 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1156 sky2->netdev->name);
1157stopped:
1158 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1159
1160 /* reset the Rx prefetch unit */
1161 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1162 mmiowb();
6b1a3aef 1163}
793b883e 1164
d571b694 1165/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1166static void sky2_rx_clean(struct sky2_port *sky2)
1167{
1168 unsigned i;
1169
1170 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1171 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1172 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1173
1174 if (re->skb) {
14d0263f 1175 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1176 kfree_skb(re->skb);
1177 re->skb = NULL;
1178 }
1179 }
bd1c6869 1180 skb_queue_purge(&sky2->rx_recycle);
cd28ab6a
SH		 1181}
1182
ef743d33
SH		 1183/* Basic MII support */
1184static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1185{
1186 struct mii_ioctl_data *data = if_mii(ifr);
1187 struct sky2_port *sky2 = netdev_priv(dev);
1188 struct sky2_hw *hw = sky2->hw;
1189 int err = -EOPNOTSUPP;
1190
1191 if (!netif_running(dev))
1192 return -ENODEV; /* Phy still in reset */
1193
d89e1343 1194 switch (cmd) {
ef743d33
SH		 1195 case SIOCGMIIPHY:
1196 data->phy_id = PHY_ADDR_MARV;
1197
1198 /* fallthru */
1199 case SIOCGMIIREG: {
1200 u16 val = 0;
91c86df5 1201
e07b1aa8 1202 spin_lock_bh(&sky2->phy_lock);
ef743d33 1203 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1204 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1205
ef743d33
SH		 1206 data->val_out = val;
1207 break;
1208 }
1209
1210 case SIOCSMIIREG:
1211 if (!capable(CAP_NET_ADMIN))
1212 return -EPERM;
1213
e07b1aa8 1214 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1215 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1216 data->val_in);
e07b1aa8 1217 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1218 break;
1219 }
1220 return err;
1221}
1222
d1f13708 1223#ifdef SKY2_VLAN_TAG_USED
d494eacd 1224static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1225{
d494eacd 1226 if (onoff) {
3d4e66f5
SH		 1227 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1228 RX_VLAN_STRIP_ON);
1229 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1230 TX_VLAN_TAG_ON);
1231 } else {
1232 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1233 RX_VLAN_STRIP_OFF);
1234 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1235 TX_VLAN_TAG_OFF);
1236 }
d494eacd
SH		 1237}
1238
1239static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1240{
1241 struct sky2_port *sky2 = netdev_priv(dev);
1242 struct sky2_hw *hw = sky2->hw;
1243 u16 port = sky2->port;
1244
1245 netif_tx_lock_bh(dev);
1246 napi_disable(&hw->napi);
1247
1248 sky2->vlgrp = grp;
1249 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1250
d1d08d12 1251 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1252 napi_enable(&hw->napi);
2bb8c262 1253 netif_tx_unlock_bh(dev);
d1f13708
SH		 1254}
1255#endif
1256
bd1c6869
SH		 1257/* Amount of required worst case padding in rx buffer */
1258static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1259{
1260 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1261}
1262
82788c7a 1263/*
14d0263f
SH		 1264 * Allocate an skb for receiving. If the MTU is large enough
1265 * make the skb non-linear with a fragment list of pages.
82788c7a 1266 */
14d0263f 1267static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1268{
1269 struct sk_buff *skb;
14d0263f 1270 int i;
82788c7a 1271
bd1c6869
SH		 1272 skb = __skb_dequeue(&sky2->rx_recycle);
1273 if (!skb)
1274 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size
1275 + sky2_rx_pad(sky2->hw));
1276 if (!skb)
1277 goto nomem;
1278
39dbd958 1279 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1280 unsigned char *start;
1281 /*
1282 * Workaround for a bug in FIFO that cause hang
1283 * if the FIFO if the receive buffer is not 64 byte aligned.
1284 * The buffer returned from netdev_alloc_skb is
1285 * aligned except if slab debugging is enabled.
1286 */
f03b8654
SH		 1287 start = PTR_ALIGN(skb->data, 8);
1288 skb_reserve(skb, start - skb->data);
bd1c6869 1289 } else
f03b8654 1290 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1291
1292 for (i = 0; i < sky2->rx_nfrags; i++) {
1293 struct page *page = alloc_page(GFP_ATOMIC);
1294
1295 if (!page)
1296 goto free_partial;
1297 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1298 }
1299
1300 return skb;
14d0263f
SH		 1301free_partial:
1302 kfree_skb(skb);
1303nomem:
1304 return NULL;
82788c7a
SH		 1305}
1306
55c9dd35
SH		 1307static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1308{
1309 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1310}
1311
cd28ab6a
SH		 1312/*
1313 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1314 * Normal case this ends up creating one list element for skb
1315 * in the receive ring. Worst case if using large MTU and each
1316 * allocation falls on a different 64 bit region, that results
1317 * in 6 list elements per ring entry.
1318 * One element is used for checksum enable/disable, and one
1319 * extra to avoid wrap.
cd28ab6a 1320 */
6b1a3aef 1321static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1322{
6b1a3aef 1323 struct sky2_hw *hw = sky2->hw;
14d0263f 1324 struct rx_ring_info *re;
6b1a3aef 1325 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1326 unsigned i, size, thresh;
cd28ab6a 1327
6b1a3aef 1328 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1329 sky2_qset(hw, rxq);
977bdf06 1330
c3905bc4
SH		 1331 /* On PCI express lowering the watermark gives better performance */
1332 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1333 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1334
1335 /* These chips have no ram buffer?
1336 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1337 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1338 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1339 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1340 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1341
6b1a3aef
SH		 1342 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1343
ea76e635
SH		 1344 if (!(hw->flags & SKY2_HW_NEW_LE))
1345 rx_set_checksum(sky2);
14d0263f
SH		 1346
1347 /* Space needed for frame data + headers rounded up */
f957da2a 1348 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1349
1350 /* Stopping point for hardware truncation */
1351 thresh = (size - 8) / sizeof(u32);
1352
5f06eba4 1353 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1354 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1355
5f06eba4
SH		 1356 /* Compute residue after pages */
1357 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1358
5f06eba4
SH		 1359 /* Optimize to handle small packets and headers */
1360 if (size < copybreak)
1361 size = copybreak;
1362 if (size < ETH_HLEN)
1363 size = ETH_HLEN;
14d0263f 1364
14d0263f
SH		 1365 sky2->rx_data_size = size;
1366
bd1c6869
SH		 1367 skb_queue_head_init(&sky2->rx_recycle);
1368
14d0263f 1369 /* Fill Rx ring */
793b883e 1370 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1371 re = sky2->rx_ring + i;
cd28ab6a 1372
14d0263f 1373 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1374 if (!re->skb)
1375 goto nomem;
1376
454e6cb6
SH		 1377 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1378 dev_kfree_skb(re->skb);
1379 re->skb = NULL;
1380 goto nomem;
1381 }
1382
14d0263f 1383 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1384 }
1385
a1433ac4
SH		 1386 /*
1387 * The receiver hangs if it receives frames larger than the
1388 * packet buffer. As a workaround, truncate oversize frames, but
1389 * the register is limited to 9 bits, so if you do frames > 2052
1390 * you better get the MTU right!
1391 */
a1433ac4
SH		 1392 if (thresh > 0x1ff)
1393 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1394 else {
1395 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1396 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1397 }
1398
6b1a3aef 1399 /* Tell chip about available buffers */
55c9dd35 1400 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1401 return 0;
1402nomem:
1403 sky2_rx_clean(sky2);
1404 return -ENOMEM;
1405}
1406
1407/* Bring up network interface. */
1408static int sky2_up(struct net_device *dev)
1409{
1410 struct sky2_port *sky2 = netdev_priv(dev);
1411 struct sky2_hw *hw = sky2->hw;
1412 unsigned port = sky2->port;
e0c28116 1413 u32 imask, ramsize;
ee7abb04 1414 int cap, err = -ENOMEM;
843a46f4 1415 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1416
ee7abb04
SH		 1417 /*
1418 * On dual port PCI-X card, there is an problem where status
1419 * can be received out of order due to split transactions
843a46f4 1420 */
ee7abb04
SH		 1421 if (otherdev && netif_running(otherdev) &&
1422 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1423 u16 cmd;
1424
b32f40c4 1425 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1426 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1427 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1428
ee7abb04 1429 }
843a46f4 1430
55d7b4e6
SH		 1431 netif_carrier_off(dev);
1432
cd28ab6a
SH		 1433 /* must be power of 2 */
1434 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1435 TX_RING_SIZE *
1436 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1437 &sky2->tx_le_map);
1438 if (!sky2->tx_le)
1439 goto err_out;
1440
6cdbbdf3 1441 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1442 GFP_KERNEL);
1443 if (!sky2->tx_ring)
1444 goto err_out;
88f5f0ca
SH		 1445
1446 tx_init(sky2);
cd28ab6a
SH		 1447
1448 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1449 &sky2->rx_le_map);
1450 if (!sky2->rx_le)
1451 goto err_out;
1452 memset(sky2->rx_le, 0, RX_LE_BYTES);
1453
291ea614 1454 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1455 GFP_KERNEL);
1456 if (!sky2->rx_ring)
1457 goto err_out;
1458
1459 sky2_mac_init(hw, port);
1460
e0c28116
SH		 1461 /* Register is number of 4K blocks on internal RAM buffer. */
1462 ramsize = sky2_read8(hw, B2_E_0) * 4;
1463 if (ramsize > 0) {
67712901 1464 u32 rxspace;
cd28ab6a 1465
39dbd958 1466 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1467 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1468 if (ramsize < 16)
1469 rxspace = ramsize / 2;
1470 else
1471 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1472
67712901
SH		 1473 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1474 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1475
1476 /* Make sure SyncQ is disabled */
1477 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1478 RB_RST_SET);
1479 }
793b883e 1480
af4ed7e6 1481 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1482
69161611
SH		 1483 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1484 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1485 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1486
977bdf06 1487 /* Set almost empty threshold */
c2716fb4
SH		 1488 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1489 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1490 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1491
6b1a3aef
SH		 1492 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1493 TX_RING_SIZE - 1);
cd28ab6a 1494
d494eacd
SH		 1495#ifdef SKY2_VLAN_TAG_USED
1496 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1497#endif
1498
6b1a3aef 1499 err = sky2_rx_start(sky2);
6de16237 1500 if (err)
cd28ab6a
SH		 1501 goto err_out;
1502
cd28ab6a 1503 /* Enable interrupts from phy/mac for port */
e07b1aa8 1504 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1505 imask |= portirq_msk[port];
e07b1aa8 1506 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1507 sky2_read32(hw, B0_IMSK);
e07b1aa8 1508
a11da890
AD		 1509 if (netif_msg_ifup(sky2))
1510 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1511
cd28ab6a
SH		 1512 return 0;
1513
1514err_out:
1b537565 1515 if (sky2->rx_le) {
cd28ab6a
SH		 1516 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1517 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1518 sky2->rx_le = NULL;
1519 }
1520 if (sky2->tx_le) {
cd28ab6a
SH		 1521 pci_free_consistent(hw->pdev,
1522 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1523 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1524 sky2->tx_le = NULL;
1525 }
1526 kfree(sky2->tx_ring);
1527 kfree(sky2->rx_ring);
cd28ab6a 1528
1b537565
SH		 1529 sky2->tx_ring = NULL;
1530 sky2->rx_ring = NULL;
cd28ab6a
SH		 1531 return err;
1532}
1533
793b883e
SH		 1534/* Modular subtraction in ring */
1535static inline int tx_dist(unsigned tail, unsigned head)
1536{
cb5d9547 1537 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1538}
cd28ab6a 1539
793b883e
SH		 1540/* Number of list elements available for next tx */
1541static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1542{
793b883e 1543 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1544}
1545
793b883e 1546/* Estimate of number of transmit list elements required */
28bd181a 1547static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1548{
793b883e
SH		 1549 unsigned count;
1550
1551 count = sizeof(dma_addr_t) / sizeof(u32);
1552 count += skb_shinfo(skb)->nr_frags * count;
1553
89114afd 1554 if (skb_is_gso(skb))
793b883e
SH		 1555 ++count;
1556
84fa7933 1557 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1558 ++count;
1559
1560 return count;
cd28ab6a
SH		 1561}
1562
793b883e
SH		 1563/*
1564 * Put one packet in ring for transmit.
1565 * A single packet can generate multiple list elements, and
1566 * the number of ring elements will probably be less than the number
1567 * of list elements used.
1568 */
cd28ab6a
SH		 1569static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1570{
1571 struct sky2_port *sky2 = netdev_priv(dev);
1572 struct sky2_hw *hw = sky2->hw;
d1f13708 1573 struct sky2_tx_le *le = NULL;
6cdbbdf3 1574 struct tx_ring_info *re;
9b289c33
MM		 1575 unsigned i, len;
1576 u16 slot;
cd28ab6a 1577 dma_addr_t mapping;
cd28ab6a
SH		 1578 u16 mss;
1579 u8 ctrl;
1580
2bb8c262
SH		 1581 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1582 return NETDEV_TX_BUSY;
cd28ab6a 1583
cd28ab6a
SH		 1584 len = skb_headlen(skb);
1585 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1586
454e6cb6
SH		 1587 if (pci_dma_mapping_error(hw->pdev, mapping))
1588 goto mapping_error;
1589
9b289c33 1590 slot = sky2->tx_prod;
454e6cb6
SH		 1591 if (unlikely(netif_msg_tx_queued(sky2)))
1592 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1593 dev->name, slot, skb->len);
454e6cb6 1594
86c6887e
SH		 1595 /* Send high bits if needed */
1596 if (sizeof(dma_addr_t) > sizeof(u32)) {
9b289c33 1597 le = get_tx_le(sky2, &slot);
86c6887e 1598 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1599 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1600 }
cd28ab6a
SH		 1601
1602 /* Check for TCP Segmentation Offload */
7967168c 1603 mss = skb_shinfo(skb)->gso_size;
793b883e 1604 if (mss != 0) {
ea76e635
SH		 1605
1606 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1607 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1608
1609 if (mss != sky2->tx_last_mss) {
9b289c33 1610 le = get_tx_le(sky2, &slot);
69161611 1611 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1612
1613 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1614 le->opcode = OP_MSS | HW_OWNER;
1615 else
1616 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1617 sky2->tx_last_mss = mss;
1618 }
cd28ab6a
SH		 1619 }
1620
cd28ab6a 1621 ctrl = 0;
d1f13708
SH		 1622#ifdef SKY2_VLAN_TAG_USED
1623 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1624 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1625 if (!le) {
9b289c33 1626 le = get_tx_le(sky2, &slot);
f65b138c 1627 le->addr = 0;
d1f13708 1628 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1629 } else
1630 le->opcode |= OP_VLAN;
1631 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1632 ctrl |= INS_VLAN;
1633 }
1634#endif
1635
1636 /* Handle TCP checksum offload */
84fa7933 1637 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1638 /* On Yukon EX (some versions) encoding change. */
ea76e635 1639 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1640 ctrl |= CALSUM; /* auto checksum */
1641 else {
1642 const unsigned offset = skb_transport_offset(skb);
1643 u32 tcpsum;
1644
1645 tcpsum = offset << 16; /* sum start */
1646 tcpsum |= offset + skb->csum_offset; /* sum write */
1647
1648 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1649 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1650 ctrl |= UDPTCP;
1651
1652 if (tcpsum != sky2->tx_tcpsum) {
1653 sky2->tx_tcpsum = tcpsum;
1654
9b289c33 1655 le = get_tx_le(sky2, &slot);
69161611
SH		 1656 le->addr = cpu_to_le32(tcpsum);
1657 le->length = 0; /* initial checksum value */
1658 le->ctrl = 1; /* one packet */
1659 le->opcode = OP_TCPLISW | HW_OWNER;
1660 }
1d179332 1661 }
cd28ab6a
SH		 1662 }
1663
9b289c33 1664 le = get_tx_le(sky2, &slot);
d6e74b6b 1665 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1666 le->length = cpu_to_le16(len);
1667 le->ctrl = ctrl;
793b883e 1668 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1669
291ea614 1670 re = tx_le_re(sky2, le);
cd28ab6a 1671 re->skb = skb;
6cdbbdf3 1672 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1673 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1674
1675 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1676 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1677
1678 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1679 frag->size, PCI_DMA_TODEVICE);
86c6887e 1680
454e6cb6
SH		 1681 if (pci_dma_mapping_error(hw->pdev, mapping))
1682 goto mapping_unwind;
1683
86c6887e 1684 if (sizeof(dma_addr_t) > sizeof(u32)) {
9b289c33 1685 le = get_tx_le(sky2, &slot);
86c6887e 1686 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1687 le->ctrl = 0;
1688 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1689 }
1690
9b289c33 1691 le = get_tx_le(sky2, &slot);
d6e74b6b 1692 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1693 le->length = cpu_to_le16(frag->size);
1694 le->ctrl = ctrl;
793b883e 1695 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1696
291ea614
SH		 1697 re = tx_le_re(sky2, le);
1698 re->skb = skb;
1699 pci_unmap_addr_set(re, mapaddr, mapping);
1700 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1701 }
6cdbbdf3 1702
cd28ab6a
SH		 1703 le->ctrl |= EOP;
1704
9b289c33
MM		 1705 sky2->tx_prod = slot;
1706
97bda706
SH		 1707 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1708 netif_stop_queue(dev);
b19666d9 1709
290d4de5 1710 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1711
cd28ab6a 1712 return NETDEV_TX_OK;
454e6cb6
SH		 1713
1714mapping_unwind:
9b289c33 1715 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, TX_RING_SIZE)) {
454e6cb6
SH		 1716 le = sky2->tx_le + i;
1717 re = sky2->tx_ring + i;
1718
1719 switch(le->opcode & ~HW_OWNER) {
1720 case OP_LARGESEND:
1721 case OP_PACKET:
1722 pci_unmap_single(hw->pdev,
1723 pci_unmap_addr(re, mapaddr),
1724 pci_unmap_len(re, maplen),
1725 PCI_DMA_TODEVICE);
1726 break;
1727 case OP_BUFFER:
1728 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1729 pci_unmap_len(re, maplen),
1730 PCI_DMA_TODEVICE);
1731 break;
1732 }
1733 }
1734
454e6cb6
SH		 1735mapping_error:
1736 if (net_ratelimit())
1737 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1738 dev_kfree_skb(skb);
1739 return NETDEV_TX_OK;
cd28ab6a
SH		 1740}
1741
cd28ab6a 1742/*
793b883e
SH		 1743 * Free ring elements from starting at tx_cons until "done"
1744 *
481cea4a
SH		 1745 * NB:
1746 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1747 * buffers so make sure not to free skb to early.
481cea4a
SH		 1748 * 2. This may run in parallel start_xmit because the it only
1749 * looks at the tail of the queue of FIFO (tx_cons), not
1750 * the head (tx_prod)
cd28ab6a 1751 */
d11c13e7 1752static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1753{
d11c13e7 1754 struct net_device *dev = sky2->netdev;
af2a58ac 1755 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1756 unsigned idx;
cd28ab6a 1757
0e3ff6aa 1758 BUG_ON(done >= TX_RING_SIZE);
2224795d 1759
291ea614
SH		 1760 for (idx = sky2->tx_cons; idx != done;
1761 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1762 struct sky2_tx_le *le = sky2->tx_le + idx;
1763 struct tx_ring_info *re = sky2->tx_ring + idx;
1764
1765 switch(le->opcode & ~HW_OWNER) {
1766 case OP_LARGESEND:
1767 case OP_PACKET:
1768 pci_unmap_single(pdev,
1769 pci_unmap_addr(re, mapaddr),
1770 pci_unmap_len(re, maplen),
1771 PCI_DMA_TODEVICE);
af2a58ac 1772 break;
291ea614
SH		 1773 case OP_BUFFER:
1774 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1775 pci_unmap_len(re, maplen),
734d1868 1776 PCI_DMA_TODEVICE);
291ea614
SH		 1777 break;
1778 }
1779
1780 if (le->ctrl & EOP) {
bd1c6869
SH		 1781 struct sk_buff *skb = re->skb;
1782
291ea614
SH		 1783 if (unlikely(netif_msg_tx_done(sky2)))
1784 printk(KERN_DEBUG "%s: tx done %u\n",
1785 dev->name, idx);
3cf26753 1786
7138a0f5 1787 dev->stats.tx_packets++;
bd1c6869
SH		 1788 dev->stats.tx_bytes += skb->len;
1789
1790 if (skb_queue_len(&sky2->rx_recycle) < sky2->rx_pending
1791 && skb_recycle_check(skb, sky2->rx_data_size
1792 + sky2_rx_pad(sky2->hw)))
1793 __skb_queue_head(&sky2->rx_recycle, skb);
1794 else
1795 dev_kfree_skb_any(skb);
2bf56fe2 1796
3cf26753 1797 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1798 }
793b883e 1799 }
793b883e 1800
291ea614 1801 sky2->tx_cons = idx;
50432cb5
SH		 1802 smp_mb();
1803
22e11703 1804 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1805 netif_wake_queue(dev);
cd28ab6a
SH		 1806}
1807
264bb4fa 1808static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1809{
a510996b
MM		 1810 /* Disable Force Sync bit and Enable Alloc bit */
1811 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1812 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1813
1814 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1815 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1816 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1817
1818 /* Reset the PCI FIFO of the async Tx queue */
1819 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1820 BMU_RST_SET | BMU_FIFO_RST);
1821
1822 /* Reset the Tx prefetch units */
1823 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1824 PREF_UNIT_RST_SET);
1825
1826 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1827 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1828}
1829
cd28ab6a
SH		 1830/* Network shutdown */
1831static int sky2_down(struct net_device *dev)
1832{
1833 struct sky2_port *sky2 = netdev_priv(dev);
1834 struct sky2_hw *hw = sky2->hw;
1835 unsigned port = sky2->port;
1836 u16 ctrl;
e07b1aa8 1837 u32 imask;
cd28ab6a 1838
1b537565
SH		 1839 /* Never really got started! */
1840 if (!sky2->tx_le)
1841 return 0;
1842
cd28ab6a
SH		 1843 if (netif_msg_ifdown(sky2))
1844 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1845
d104acaf
SH		 1846 /* Force flow control off */
1847 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1848
cd28ab6a
SH		 1849 /* Stop transmitter */
1850 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1851 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1852
1853 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1854 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1855
1856 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1857 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1858 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1859
1860 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1861
1862 /* Workaround shared GMAC reset */
793b883e
SH		 1863 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1864 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1865 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1866
cd28ab6a 1867 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1868
6c83504f
SH		 1869 /* Force any delayed status interrrupt and NAPI */
1870 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1871 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1872 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1873 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1874
a947a39d
MM		 1875 sky2_rx_stop(sky2);
1876
1877 /* Disable port IRQ */
1878 imask = sky2_read32(hw, B0_IMSK);
1879 imask &= ~portirq_msk[port];
1880 sky2_write32(hw, B0_IMSK, imask);
1881 sky2_read32(hw, B0_IMSK);
1882
6c83504f
SH		 1883 synchronize_irq(hw->pdev->irq);
1884 napi_synchronize(&hw->napi);
1885
0da6d7b3 1886 spin_lock_bh(&sky2->phy_lock);
b96936da 1887 sky2_phy_power_down(hw, port);
0da6d7b3 1888 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1889
d571b694 1890 /* turn off LED's */
cd28ab6a
SH		 1891 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1892
264bb4fa
MM		 1893 sky2_tx_reset(hw, port);
1894
481cea4a
SH		 1895 /* Free any pending frames stuck in HW queue */
1896 sky2_tx_complete(sky2, sky2->tx_prod);
1897
cd28ab6a
SH		 1898 sky2_rx_clean(sky2);
1899
1900 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1901 sky2->rx_le, sky2->rx_le_map);
1902 kfree(sky2->rx_ring);
1903
1904 pci_free_consistent(hw->pdev,
1905 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1906 sky2->tx_le, sky2->tx_le_map);
1907 kfree(sky2->tx_ring);
1908
1b537565
SH		 1909 sky2->tx_le = NULL;
1910 sky2->rx_le = NULL;
1911
1912 sky2->rx_ring = NULL;
1913 sky2->tx_ring = NULL;
1914
cd28ab6a
SH		 1915 return 0;
1916}
1917
1918static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1919{
ea76e635 1920 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1921 return SPEED_1000;
1922
05745c4a
SH		 1923 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1924 if (aux & PHY_M_PS_SPEED_100)
1925 return SPEED_100;
1926 else
1927 return SPEED_10;
1928 }
cd28ab6a
SH		 1929
1930 switch (aux & PHY_M_PS_SPEED_MSK) {
1931 case PHY_M_PS_SPEED_1000:
1932 return SPEED_1000;
1933 case PHY_M_PS_SPEED_100:
1934 return SPEED_100;
1935 default:
1936 return SPEED_10;
1937 }
1938}
1939
1940static void sky2_link_up(struct sky2_port *sky2)
1941{
1942 struct sky2_hw *hw = sky2->hw;
1943 unsigned port = sky2->port;
1944 u16 reg;
16ad91e1
SH		 1945 static const char *fc_name[] = {
1946 [FC_NONE] = "none",
1947 [FC_TX] = "tx",
1948 [FC_RX] = "rx",
1949 [FC_BOTH] = "both",
1950 };
cd28ab6a 1951
cd28ab6a 1952 /* enable Rx/Tx */
2eaba1a2 1953 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1954 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1955 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1956
1957 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1958
1959 netif_carrier_on(sky2->netdev);
cd28ab6a 1960
75e80683 1961 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1962
cd28ab6a 1963 /* Turn on link LED */
793b883e 1964 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1965 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1966
1967 if (netif_msg_link(sky2))
1968 printk(KERN_INFO PFX
d571b694 1969 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1970 sky2->netdev->name, sky2->speed,
1971 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1972 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1973}
1974
1975static void sky2_link_down(struct sky2_port *sky2)
1976{
1977 struct sky2_hw *hw = sky2->hw;
1978 unsigned port = sky2->port;
1979 u16 reg;
1980
1981 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1982
1983 reg = gma_read16(hw, port, GM_GP_CTRL);
1984 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1985 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1986
cd28ab6a 1987 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1988
1989 /* Turn on link LED */
1990 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1991
1992 if (netif_msg_link(sky2))
1993 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1994
cd28ab6a
SH		 1995 sky2_phy_init(hw, port);
1996}
1997
16ad91e1
SH		 1998static enum flow_control sky2_flow(int rx, int tx)
1999{
2000 if (rx)
2001 return tx ? FC_BOTH : FC_RX;
2002 else
2003 return tx ? FC_TX : FC_NONE;
2004}
2005
793b883e
SH		 2006static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2007{
2008 struct sky2_hw *hw = sky2->hw;
2009 unsigned port = sky2->port;
da4c1ff4 2010 u16 advert, lpa;
793b883e 2011
da4c1ff4 2012 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2013 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2014 if (lpa & PHY_M_AN_RF) {
2015 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2016 return -1;
2017 }
2018
793b883e
SH		 2019 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2020 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2021 sky2->netdev->name);
2022 return -1;
2023 }
2024
793b883e 2025 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2026 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2027
da4c1ff4
SH		 2028 /* Since the pause result bits seem to in different positions on
2029 * different chips. look at registers.
2030 */
ea76e635 2031 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2032 /* Shift for bits in fiber PHY */
2033 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2034 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2035
2036 if (advert & ADVERTISE_1000XPAUSE)
2037 advert |= ADVERTISE_PAUSE_CAP;
2038 if (advert & ADVERTISE_1000XPSE_ASYM)
2039 advert |= ADVERTISE_PAUSE_ASYM;
2040 if (lpa & LPA_1000XPAUSE)
2041 lpa |= LPA_PAUSE_CAP;
2042 if (lpa & LPA_1000XPAUSE_ASYM)
2043 lpa |= LPA_PAUSE_ASYM;
2044 }
793b883e 2045
da4c1ff4
SH		 2046 sky2->flow_status = FC_NONE;
2047 if (advert & ADVERTISE_PAUSE_CAP) {
2048 if (lpa & LPA_PAUSE_CAP)
2049 sky2->flow_status = FC_BOTH;
2050 else if (advert & ADVERTISE_PAUSE_ASYM)
2051 sky2->flow_status = FC_RX;
2052 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2053 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2054 sky2->flow_status = FC_TX;
2055 }
793b883e 2056
16ad91e1 2057 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2058 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2059 sky2->flow_status = FC_NONE;
2eaba1a2 2060
da4c1ff4 2061 if (sky2->flow_status & FC_TX)
793b883e
SH		 2062 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2063 else
2064 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2065
2066 return 0;
2067}
cd28ab6a 2068
e07b1aa8
SH		 2069/* Interrupt from PHY */
2070static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2071{
e07b1aa8
SH		 2072 struct net_device *dev = hw->dev[port];
2073 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2074 u16 istatus, phystat;
2075
ebc646f6
SH		 2076 if (!netif_running(dev))
2077 return;
2078
e07b1aa8
SH		 2079 spin_lock(&sky2->phy_lock);
2080 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2081 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2082
cd28ab6a
SH		 2083 if (netif_msg_intr(sky2))
2084 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2085 sky2->netdev->name, istatus, phystat);
2086
0ea065e5 2087 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2088 if (sky2_autoneg_done(sky2, phystat) == 0)
2089 sky2_link_up(sky2);
2090 goto out;
2091 }
cd28ab6a 2092
793b883e
SH		 2093 if (istatus & PHY_M_IS_LSP_CHANGE)
2094 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2095
793b883e
SH		 2096 if (istatus & PHY_M_IS_DUP_CHANGE)
2097 sky2->duplex =
2098 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2099
793b883e
SH		 2100 if (istatus & PHY_M_IS_LST_CHANGE) {
2101 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2102 sky2_link_up(sky2);
793b883e
SH		 2103 else
2104 sky2_link_down(sky2);
cd28ab6a 2105 }
793b883e 2106out:
e07b1aa8 2107 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2108}
2109
62335ab0 2110/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2111 * and tx queue is full (stopped).
2112 */
cd28ab6a
SH		 2113static void sky2_tx_timeout(struct net_device *dev)
2114{
2115 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2116 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2117
2118 if (netif_msg_timer(sky2))
2119 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2120
8f24664d 2121 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2122 dev->name, sky2->tx_cons, sky2->tx_prod,
2123 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2124 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2125
81906791
SH		 2126 /* can't restart safely under softirq */
2127 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2128}
2129
2130static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2131{
6b1a3aef
SH		 2132 struct sky2_port *sky2 = netdev_priv(dev);
2133 struct sky2_hw *hw = sky2->hw;
b628ed98 2134 unsigned port = sky2->port;
6b1a3aef
SH		 2135 int err;
2136 u16 ctl, mode;
e07b1aa8 2137 u32 imask;
cd28ab6a
SH		 2138
2139 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2140 return -EINVAL;
2141
05745c4a
SH		 2142 if (new_mtu > ETH_DATA_LEN &&
2143 (hw->chip_id == CHIP_ID_YUKON_FE ||
2144 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2145 return -EINVAL;
2146
6b1a3aef
SH		 2147 if (!netif_running(dev)) {
2148 dev->mtu = new_mtu;
2149 return 0;
2150 }
2151
e07b1aa8 2152 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2153 sky2_write32(hw, B0_IMSK, 0);
2154
018d1c66
SH		 2155 dev->trans_start = jiffies; /* prevent tx timeout */
2156 netif_stop_queue(dev);
bea3348e 2157 napi_disable(&hw->napi);
018d1c66 2158
e07b1aa8
SH		 2159 synchronize_irq(hw->pdev->irq);
2160
39dbd958 2161 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2162 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2163
2164 ctl = gma_read16(hw, port, GM_GP_CTRL);
2165 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2166 sky2_rx_stop(sky2);
2167 sky2_rx_clean(sky2);
cd28ab6a
SH		 2168
2169 dev->mtu = new_mtu;
14d0263f 2170
6b1a3aef
SH		 2171 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2172 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2173
2174 if (dev->mtu > ETH_DATA_LEN)
2175 mode |= GM_SMOD_JUMBO_ENA;
2176
b628ed98 2177 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2178
b628ed98 2179 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2180
6b1a3aef 2181 err = sky2_rx_start(sky2);
e07b1aa8 2182 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2183
d1d08d12 2184 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2185 napi_enable(&hw->napi);
2186
1b537565
SH		 2187 if (err)
2188 dev_close(dev);
2189 else {
b628ed98 2190 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2191
1b537565
SH		 2192 netif_wake_queue(dev);
2193 }
2194
cd28ab6a
SH		 2195 return err;
2196}
2197
14d0263f
SH		 2198/* For small just reuse existing skb for next receive */
2199static struct sk_buff *receive_copy(struct sky2_port *sky2,
2200 const struct rx_ring_info *re,
2201 unsigned length)
2202{
2203 struct sk_buff *skb;
2204
2205 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2206 if (likely(skb)) {
2207 skb_reserve(skb, 2);
2208 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2209 length, PCI_DMA_FROMDEVICE);
d626f62b 2210 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2211 skb->ip_summed = re->skb->ip_summed;
2212 skb->csum = re->skb->csum;
2213 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2214 length, PCI_DMA_FROMDEVICE);
2215 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2216 skb_put(skb, length);
14d0263f
SH		 2217 }
2218 return skb;
2219}
2220
2221/* Adjust length of skb with fragments to match received data */
2222static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2223 unsigned int length)
2224{
2225 int i, num_frags;
2226 unsigned int size;
2227
2228 /* put header into skb */
2229 size = min(length, hdr_space);
2230 skb->tail += size;
2231 skb->len += size;
2232 length -= size;
2233
2234 num_frags = skb_shinfo(skb)->nr_frags;
2235 for (i = 0; i < num_frags; i++) {
2236 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2237
2238 if (length == 0) {
2239 /* don't need this page */
2240 __free_page(frag->page);
2241 --skb_shinfo(skb)->nr_frags;
2242 } else {
2243 size = min(length, (unsigned) PAGE_SIZE);
2244
2245 frag->size = size;
2246 skb->data_len += size;
2247 skb->truesize += size;
2248 skb->len += size;
2249 length -= size;
2250 }
2251 }
2252}
2253
2254/* Normal packet - take skb from ring element and put in a new one */
2255static struct sk_buff *receive_new(struct sky2_port *sky2,
2256 struct rx_ring_info *re,
2257 unsigned int length)
2258{
2259 struct sk_buff *skb, *nskb;
2260 unsigned hdr_space = sky2->rx_data_size;
2261
14d0263f
SH		 2262 /* Don't be tricky about reusing pages (yet) */
2263 nskb = sky2_rx_alloc(sky2);
2264 if (unlikely(!nskb))
2265 return NULL;
2266
2267 skb = re->skb;
2268 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2269
2270 prefetch(skb->data);
2271 re->skb = nskb;
454e6cb6
SH		 2272 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2273 dev_kfree_skb(nskb);
2274 re->skb = skb;
2275 return NULL;
2276 }
14d0263f
SH		 2277
2278 if (skb_shinfo(skb)->nr_frags)
2279 skb_put_frags(skb, hdr_space, length);
2280 else
489b10c1 2281 skb_put(skb, length);
14d0263f
SH		 2282 return skb;
2283}
2284
cd28ab6a
SH		 2285/*
2286 * Receive one packet.
d571b694 2287 * For larger packets, get new buffer.
cd28ab6a 2288 */
497d7c86 2289static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2290 u16 length, u32 status)
2291{
497d7c86 2292 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2293 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2294 struct sk_buff *skb = NULL;
d6532232
SH		 2295 u16 count = (status & GMR_FS_LEN) >> 16;
2296
2297#ifdef SKY2_VLAN_TAG_USED
2298 /* Account for vlan tag */
2299 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2300 count -= VLAN_HLEN;
2301#endif
cd28ab6a
SH		 2302
2303 if (unlikely(netif_msg_rx_status(sky2)))
2304 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2305 dev->name, sky2->rx_next, status, length);
cd28ab6a 2306
793b883e 2307 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2308 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2309
3b12e014
SH		 2310 /* This chip has hardware problems that generates bogus status.
2311 * So do only marginal checking and expect higher level protocols
2312 * to handle crap frames.
2313 */
2314 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2315 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2316 length != count)
2317 goto okay;
2318
42eeea01 2319 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2320 goto error;
2321
42eeea01
SH		 2322 if (!(status & GMR_FS_RX_OK))
2323 goto resubmit;
2324
d6532232
SH		 2325 /* if length reported by DMA does not match PHY, packet was truncated */
2326 if (length != count)
3b12e014 2327 goto len_error;
71749531 2328
3b12e014 2329okay:
14d0263f
SH		 2330 if (length < copybreak)
2331 skb = receive_copy(sky2, re, length);
2332 else
2333 skb = receive_new(sky2, re, length);
793b883e 2334resubmit:
14d0263f 2335 sky2_rx_submit(sky2, re);
79e57d32 2336
cd28ab6a
SH		 2337 return skb;
2338
3b12e014 2339len_error:
71749531
SH		 2340 /* Truncation of overlength packets
2341 causes PHY length to not match MAC length */
7138a0f5 2342 ++dev->stats.rx_length_errors;
d6532232 2343 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2344 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2345 dev->name, status, length);
d6532232 2346 goto resubmit;
71749531 2347
cd28ab6a 2348error:
7138a0f5 2349 ++dev->stats.rx_errors;
b6d77734 2350 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2351 dev->stats.rx_over_errors++;
b6d77734
SH		 2352 goto resubmit;
2353 }
6e15b712 2354
3be92a70 2355 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2356 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2357 dev->name, status, length);
793b883e
SH		 2358
2359 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2360 dev->stats.rx_length_errors++;
cd28ab6a 2361 if (status & GMR_FS_FRAGMENT)
7138a0f5 2362 dev->stats.rx_frame_errors++;
cd28ab6a 2363 if (status & GMR_FS_CRC_ERR)
7138a0f5 2364 dev->stats.rx_crc_errors++;
79e57d32 2365
793b883e 2366 goto resubmit;
cd28ab6a
SH		 2367}
2368
e07b1aa8
SH		 2369/* Transmit complete */
2370static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2371{
e07b1aa8 2372 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2373
49d4b8ba 2374 if (netif_running(dev))
e07b1aa8 2375 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2376}
2377
37e5a243
SH		 2378static inline void sky2_skb_rx(const struct sky2_port *sky2,
2379 u32 status, struct sk_buff *skb)
2380{
2381#ifdef SKY2_VLAN_TAG_USED
2382 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2383 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2384 if (skb->ip_summed == CHECKSUM_NONE)
2385 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2386 else
2387 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2388 vlan_tag, skb);
2389 return;
2390 }
2391#endif
2392 if (skb->ip_summed == CHECKSUM_NONE)
2393 netif_receive_skb(skb);
2394 else
2395 napi_gro_receive(&sky2->hw->napi, skb);
2396}
2397
bf15fe99
SH		 2398static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2399 unsigned packets, unsigned bytes)
2400{
2401 if (packets) {
2402 struct net_device *dev = hw->dev[port];
2403
2404 dev->stats.rx_packets += packets;
2405 dev->stats.rx_bytes += bytes;
2406 dev->last_rx = jiffies;
2407 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2408 }
2409}
2410
e07b1aa8 2411/* Process status response ring */
26691830 2412static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2413{
e07b1aa8 2414 int work_done = 0;
bf15fe99
SH		 2415 unsigned int total_bytes[2] = { 0 };
2416 unsigned int total_packets[2] = { 0 };
a8fd6266 2417
af2a58ac 2418 rmb();
26691830 2419 do {
55c9dd35 2420 struct sky2_port *sky2;
13210ce5 2421 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2422 unsigned port;
13210ce5 2423 struct net_device *dev;
cd28ab6a 2424 struct sk_buff *skb;
cd28ab6a
SH		 2425 u32 status;
2426 u16 length;
ab5adecb
SH		 2427 u8 opcode = le->opcode;
2428
2429 if (!(opcode & HW_OWNER))
2430 break;
cd28ab6a 2431
cb5d9547 2432 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2433
ab5adecb 2434 port = le->css & CSS_LINK_BIT;
69161611 2435 dev = hw->dev[port];
13210ce5 2436 sky2 = netdev_priv(dev);
f65b138c
SH		 2437 length = le16_to_cpu(le->length);
2438 status = le32_to_cpu(le->status);
cd28ab6a 2439
ab5adecb
SH		 2440 le->opcode = 0;
2441 switch (opcode & ~HW_OWNER) {
cd28ab6a 2442 case OP_RXSTAT:
bf15fe99
SH		 2443 total_packets[port]++;
2444 total_bytes[port] += length;
497d7c86 2445 skb = sky2_receive(dev, length, status);
3225b919 2446 if (unlikely(!skb)) {
7138a0f5 2447 dev->stats.rx_dropped++;
55c9dd35 2448 break;
3225b919 2449 }
13210ce5 2450
69161611 2451 /* This chip reports checksum status differently */
05745c4a 2452 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2453 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2454 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2455 (le->css & CSS_TCPUDPCSOK))
2456 skb->ip_summed = CHECKSUM_UNNECESSARY;
2457 else
2458 skb->ip_summed = CHECKSUM_NONE;
2459 }
2460
13210ce5 2461 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2462
37e5a243 2463 sky2_skb_rx(sky2, status, skb);
13210ce5 2464
22e11703 2465 /* Stop after net poll weight */
13210ce5
SH		 2466 if (++work_done >= to_do)
2467 goto exit_loop;
cd28ab6a
SH		 2468 break;
2469
d1f13708
SH		 2470#ifdef SKY2_VLAN_TAG_USED
2471 case OP_RXVLAN:
2472 sky2->rx_tag = length;
2473 break;
2474
2475 case OP_RXCHKSVLAN:
2476 sky2->rx_tag = length;
2477 /* fall through */
2478#endif
cd28ab6a 2479 case OP_RXCHKS:
0ea065e5 2480 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
87418307
SH		 2481 break;
2482
05745c4a
SH		 2483 /* If this happens then driver assuming wrong format */
2484 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2485 if (net_ratelimit())
2486 printk(KERN_NOTICE "%s: unexpected"
2487 " checksum status\n",
2488 dev->name);
69161611 2489 break;
05745c4a 2490 }
69161611 2491
87418307
SH		 2492 /* Both checksum counters are programmed to start at
2493 * the same offset, so unless there is a problem they
2494 * should match. This failure is an early indication that
2495 * hardware receive checksumming won't work.
2496 */
2497 if (likely(status >> 16 == (status & 0xffff))) {
2498 skb = sky2->rx_ring[sky2->rx_next].skb;
2499 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2500 skb->csum = le16_to_cpu(status);
87418307
SH		 2501 } else {
2502 printk(KERN_NOTICE PFX "%s: hardware receive "
2503 "checksum problem (status = %#x)\n",
2504 dev->name, status);
0ea065e5
SH		 2505 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2506
87418307 2507 sky2_write32(sky2->hw,
69161611 2508 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2509 BMU_DIS_RX_CHKSUM);
2510 }
cd28ab6a
SH		 2511 break;
2512
2513 case OP_TXINDEXLE:
13b97b74 2514 /* TX index reports status for both ports */
f55925d7
SH		 2515 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2516 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2517 if (hw->dev[1])
2518 sky2_tx_done(hw->dev[1],
2519 ((status >> 24) & 0xff)
2520 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2521 break;
2522
cd28ab6a
SH		 2523 default:
2524 if (net_ratelimit())
793b883e 2525 printk(KERN_WARNING PFX
ab5adecb 2526 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2527 }
26691830 2528 } while (hw->st_idx != idx);
cd28ab6a 2529
fe2a24df
SH		 2530 /* Fully processed status ring so clear irq */
2531 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2532
13210ce5 2533exit_loop:
bf15fe99
SH		 2534 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2535 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2536
e07b1aa8 2537 return work_done;
cd28ab6a
SH		 2538}
2539
2540static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2541{
2542 struct net_device *dev = hw->dev[port];
2543
3be92a70
SH		 2544 if (net_ratelimit())
2545 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2546 dev->name, status);
cd28ab6a
SH		 2547
2548 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2549 if (net_ratelimit())
2550 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2551 dev->name);
cd28ab6a
SH		 2552 /* Clear IRQ */
2553 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2554 }
2555
2556 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2557 if (net_ratelimit())
2558 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2559 dev->name);
cd28ab6a
SH		 2560
2561 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2562 }
2563
2564 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2565 if (net_ratelimit())
2566 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2567 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2568 }
2569
2570 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2571 if (net_ratelimit())
2572 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2573 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2574 }
2575
2576 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2577 if (net_ratelimit())
2578 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2579 dev->name);
cd28ab6a
SH		 2580 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2581 }
2582}
2583
2584static void sky2_hw_intr(struct sky2_hw *hw)
2585{
555382cb 2586 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2587 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2588 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2589
2590 status &= hwmsk;
cd28ab6a 2591
793b883e 2592 if (status & Y2_IS_TIST_OV)
cd28ab6a 2593 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2594
2595 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2596 u16 pci_err;
2597
82637e80 2598 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2599 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2600 if (net_ratelimit())
555382cb 2601 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2602 pci_err);
cd28ab6a 2603
b32f40c4 2604 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2605 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2606 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2607 }
2608
2609 if (status & Y2_IS_PCI_EXP) {
d571b694 2610 /* PCI-Express uncorrectable Error occurred */
555382cb 2611 u32 err;
cd28ab6a 2612
82637e80 2613 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2614 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2615 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2616 0xfffffffful);
3be92a70 2617 if (net_ratelimit())
555382cb 2618 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2619
7782c8c4 2620 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2622 }
2623
2624 if (status & Y2_HWE_L1_MASK)
2625 sky2_hw_error(hw, 0, status);
2626 status >>= 8;
2627 if (status & Y2_HWE_L1_MASK)
2628 sky2_hw_error(hw, 1, status);
2629}
2630
2631static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2632{
2633 struct net_device *dev = hw->dev[port];
2634 struct sky2_port *sky2 = netdev_priv(dev);
2635 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2636
2637 if (netif_msg_intr(sky2))
2638 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2639 dev->name, status);
2640
a3caeada
SH		 2641 if (status & GM_IS_RX_CO_OV)
2642 gma_read16(hw, port, GM_RX_IRQ_SRC);
2643
2644 if (status & GM_IS_TX_CO_OV)
2645 gma_read16(hw, port, GM_TX_IRQ_SRC);
2646
cd28ab6a 2647 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2648 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2649 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2650 }
2651
2652 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2653 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2654 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2655 }
cd28ab6a
SH		 2656}
2657
40b01727
SH		 2658/* This should never happen it is a bug. */
2659static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2660 u16 q, unsigned ring_size)
d257924e
SH		 2661{
2662 struct net_device *dev = hw->dev[port];
2663 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2664 unsigned idx;
2665 const u64 *le = (q == Q_R1 || q == Q_R2)
2666 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2667
40b01727
SH		 2668 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2669 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2670 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2671 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2672
40b01727 2673 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2674}
cd28ab6a 2675
75e80683
SH		 2676static int sky2_rx_hung(struct net_device *dev)
2677{
2678 struct sky2_port *sky2 = netdev_priv(dev);
2679 struct sky2_hw *hw = sky2->hw;
2680 unsigned port = sky2->port;
2681 unsigned rxq = rxqaddr[port];
2682 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2683 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2684 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2685 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2686
2687 /* If idle and MAC or PCI is stuck */
2688 if (sky2->check.last == dev->last_rx &&
2689 ((mac_rp == sky2->check.mac_rp &&
2690 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2691 /* Check if the PCI RX hang */
2692 (fifo_rp == sky2->check.fifo_rp &&
2693 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2694 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2695 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2696 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2697 return 1;
2698 } else {
2699 sky2->check.last = dev->last_rx;
2700 sky2->check.mac_rp = mac_rp;
2701 sky2->check.mac_lev = mac_lev;
2702 sky2->check.fifo_rp = fifo_rp;
2703 sky2->check.fifo_lev = fifo_lev;
2704 return 0;
2705 }
2706}
2707
32c2c300 2708static void sky2_watchdog(unsigned long arg)
d27ed387 2709{
01bd7564 2710 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2711
75e80683 2712 /* Check for lost IRQ once a second */
32c2c300 2713 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2714 napi_schedule(&hw->napi);
75e80683
SH		 2715 } else {
2716 int i, active = 0;
2717
2718 for (i = 0; i < hw->ports; i++) {
bea3348e 2719 struct net_device *dev = hw->dev[i];
75e80683
SH		 2720 if (!netif_running(dev))
2721 continue;
2722 ++active;
2723
2724 /* For chips with Rx FIFO, check if stuck */
39dbd958 2725 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2726 sky2_rx_hung(dev)) {
2727 pr_info(PFX "%s: receiver hang detected\n",
2728 dev->name);
2729 schedule_work(&hw->restart_work);
2730 return;
2731 }
2732 }
2733
2734 if (active == 0)
2735 return;
32c2c300 2736 }
01bd7564 2737
75e80683 2738 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2739}
2740
40b01727
SH		 2741/* Hardware/software error handling */
2742static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2743{
40b01727
SH		 2744 if (net_ratelimit())
2745 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2746
1e5f1283
SH		 2747 if (status & Y2_IS_HW_ERR)
2748 sky2_hw_intr(hw);
d257924e 2749
1e5f1283
SH		 2750 if (status & Y2_IS_IRQ_MAC1)
2751 sky2_mac_intr(hw, 0);
cd28ab6a 2752
1e5f1283
SH		 2753 if (status & Y2_IS_IRQ_MAC2)
2754 sky2_mac_intr(hw, 1);
cd28ab6a 2755
1e5f1283 2756 if (status & Y2_IS_CHK_RX1)
40b01727 2757 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2758
1e5f1283 2759 if (status & Y2_IS_CHK_RX2)
40b01727 2760 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2761
1e5f1283 2762 if (status & Y2_IS_CHK_TXA1)
40b01727 2763 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2764
1e5f1283 2765 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2766 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2767}
2768
bea3348e 2769static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2770{
bea3348e 2771 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2772 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2773 int work_done = 0;
26691830 2774 u16 idx;
40b01727
SH		 2775
2776 if (unlikely(status & Y2_IS_ERROR))
2777 sky2_err_intr(hw, status);
2778
2779 if (status & Y2_IS_IRQ_PHY1)
2780 sky2_phy_intr(hw, 0);
2781
2782 if (status & Y2_IS_IRQ_PHY2)
2783 sky2_phy_intr(hw, 1);
cd28ab6a 2784
26691830
SH		 2785 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2786 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2787
2788 if (work_done >= work_limit)
26691830
SH		 2789 goto done;
2790 }
6f535763 2791
26691830
SH		 2792 napi_complete(napi);
2793 sky2_read32(hw, B0_Y2_SP_LISR);
2794done:
6f535763 2795
bea3348e 2796 return work_done;
e07b1aa8
SH		 2797}
2798
7d12e780 2799static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2800{
2801 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2802 u32 status;
2803
2804 /* Reading this mask interrupts as side effect */
2805 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2806 if (status == 0 || status == ~0)
2807 return IRQ_NONE;
793b883e 2808
e07b1aa8 2809 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2810
2811 napi_schedule(&hw->napi);
793b883e 2812
cd28ab6a
SH		 2813 return IRQ_HANDLED;
2814}
2815
2816#ifdef CONFIG_NET_POLL_CONTROLLER
2817static void sky2_netpoll(struct net_device *dev)
2818{
2819 struct sky2_port *sky2 = netdev_priv(dev);
2820
bea3348e 2821 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2822}
2823#endif
2824
2825/* Chip internal frequency for clock calculations */
05745c4a 2826static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2827{
793b883e 2828 switch (hw->chip_id) {
cd28ab6a 2829 case CHIP_ID_YUKON_EC:
5a5b1ea0 2830 case CHIP_ID_YUKON_EC_U:
93745494 2831 case CHIP_ID_YUKON_EX:
ed4d4161 2832 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2833 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2834 return 125;
2835
cd28ab6a 2836 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2837 return 100;
2838
2839 case CHIP_ID_YUKON_FE_P:
2840 return 50;
2841
2842 case CHIP_ID_YUKON_XL:
2843 return 156;
2844
2845 default:
2846 BUG();
cd28ab6a
SH		 2847 }
2848}
2849
fb17358f 2850static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2851{
fb17358f 2852 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2853}
2854
fb17358f 2855static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2856{
fb17358f 2857 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2858}
2859
fb17358f 2860
e3173832 2861static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2862{
b89165f2 2863 u8 t8;
cd28ab6a 2864
167f53d0 2865 /* Enable all clocks and check for bad PCI access */
b32f40c4 2866 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2867
cd28ab6a 2868 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2869
cd28ab6a 2870 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2871 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2872
2873 switch(hw->chip_id) {
2874 case CHIP_ID_YUKON_XL:
39dbd958 2875 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2876 break;
2877
2878 case CHIP_ID_YUKON_EC_U:
2879 hw->flags = SKY2_HW_GIGABIT
2880 | SKY2_HW_NEWER_PHY
2881 | SKY2_HW_ADV_POWER_CTL;
2882 break;
2883
2884 case CHIP_ID_YUKON_EX:
2885 hw->flags = SKY2_HW_GIGABIT
2886 | SKY2_HW_NEWER_PHY
2887 | SKY2_HW_NEW_LE
2888 | SKY2_HW_ADV_POWER_CTL;
2889
2890 /* New transmit checksum */
2891 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2892 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2893 break;
2894
2895 case CHIP_ID_YUKON_EC:
2896 /* This rev is really old, and requires untested workarounds */
2897 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2898 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2899 return -EOPNOTSUPP;
2900 }
39dbd958 2901 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2902 break;
2903
2904 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2905 break;
2906
05745c4a
SH		 2907 case CHIP_ID_YUKON_FE_P:
2908 hw->flags = SKY2_HW_NEWER_PHY
2909 | SKY2_HW_NEW_LE
2910 | SKY2_HW_AUTO_TX_SUM
2911 | SKY2_HW_ADV_POWER_CTL;
2912 break;
ed4d4161
SH		 2913
2914 case CHIP_ID_YUKON_SUPR:
2915 hw->flags = SKY2_HW_GIGABIT
2916 | SKY2_HW_NEWER_PHY
2917 | SKY2_HW_NEW_LE
2918 | SKY2_HW_AUTO_TX_SUM
2919 | SKY2_HW_ADV_POWER_CTL;
2920 break;
2921
0ce8b98d
SH		 2922 case CHIP_ID_YUKON_UL_2:
2923 hw->flags = SKY2_HW_GIGABIT
2924 | SKY2_HW_ADV_POWER_CTL;
2925 break;
2926
ea76e635 2927 default:
b02a9258
SH		 2928 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2929 hw->chip_id);
cd28ab6a
SH		 2930 return -EOPNOTSUPP;
2931 }
2932
ea76e635
SH		 2933 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2934 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2935 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2936
e3173832
SH		 2937 hw->ports = 1;
2938 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2939 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2940 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2941 ++hw->ports;
2942 }
2943
2944 return 0;
2945}
2946
2947static void sky2_reset(struct sky2_hw *hw)
2948{
555382cb 2949 struct pci_dev *pdev = hw->pdev;
e3173832 2950 u16 status;
555382cb
SH		 2951 int i, cap;
2952 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2953
cd28ab6a 2954 /* disable ASF */
4f44d8ba
SH		 2955 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2956 status = sky2_read16(hw, HCU_CCSR);
2957 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2958 HCU_CCSR_UC_STATE_MSK);
2959 sky2_write16(hw, HCU_CCSR, status);
2960 } else
2961 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2962 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2963
2964 /* do a SW reset */
2965 sky2_write8(hw, B0_CTST, CS_RST_SET);
2966 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2967
ac93a394
SH		 2968 /* allow writes to PCI config */
2969 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2970
cd28ab6a 2971 /* clear PCI errors, if any */
b32f40c4 2972 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2973 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2974 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2975
2976 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2977
555382cb
SH		 2978 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2979 if (cap) {
7782c8c4
SH		 2980 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2981 0xfffffffful);
555382cb
SH		 2982
2983 /* If error bit is stuck on ignore it */
2984 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2985 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2986 else
555382cb
SH		 2987 hwe_mask |= Y2_IS_PCI_EXP;
2988 }
cd28ab6a 2989
ae306cca 2990 sky2_power_on(hw);
82637e80 2991 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2992
2993 for (i = 0; i < hw->ports; i++) {
2994 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2995 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2996
ed4d4161
SH		 2997 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2998 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2999 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3000 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3001 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 3002 }
3003
793b883e
SH		 3004 /* Clear I2C IRQ noise */
3005 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3006
3007 /* turn off hardware timer (unused) */
3008 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3009 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3010
cd28ab6a
SH		 3011 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3012
69634ee7
SH		 3013 /* Turn off descriptor polling */
3014 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3015
3016 /* Turn off receive timestamp */
3017 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3018 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3019
3020 /* enable the Tx Arbiters */
3021 for (i = 0; i < hw->ports; i++)
3022 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3023
3024 /* Initialize ram interface */
3025 for (i = 0; i < hw->ports; i++) {
793b883e 3026 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3027
3028 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3029 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3030 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3031 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3032 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3033 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3034 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3035 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3036 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3037 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3038 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3039 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3040 }
3041
555382cb 3042 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3043
cd28ab6a 3044 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3045 sky2_gmac_reset(hw, i);
cd28ab6a 3046
cd28ab6a
SH		 3047 memset(hw->st_le, 0, STATUS_LE_BYTES);
3048 hw->st_idx = 0;
3049
3050 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3051 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3052
3053 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3054 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3055
3056 /* Set the list last index */
793b883e 3057 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3058
290d4de5
SH		 3059 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3060 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3061
290d4de5
SH		 3062 /* set Status-FIFO ISR watermark */
3063 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3064 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3065 else
3066 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3067
290d4de5 3068 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3069 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3070 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3071
793b883e 3072 /* enable status unit */
cd28ab6a
SH		 3073 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3074
3075 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3076 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3077 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3078}
3079
af18d8b8
SH		 3080/* Take device down (offline).
3081 * Equivalent to doing dev_stop() but this does not
3082 * inform upper layers of the transistion.
3083 */
3084static void sky2_detach(struct net_device *dev)
3085{
3086 if (netif_running(dev)) {
3087 netif_device_detach(dev); /* stop txq */
3088 sky2_down(dev);
3089 }
3090}
3091
3092/* Bring device back after doing sky2_detach */
3093static int sky2_reattach(struct net_device *dev)
3094{
3095 int err = 0;
3096
3097 if (netif_running(dev)) {
3098 err = sky2_up(dev);
3099 if (err) {
3100 printk(KERN_INFO PFX "%s: could not restart %d\n",
3101 dev->name, err);
3102 dev_close(dev);
3103 } else {
3104 netif_device_attach(dev);
3105 sky2_set_multicast(dev);
3106 }
3107 }
3108
3109 return err;
3110}
3111
81906791
SH		 3112static void sky2_restart(struct work_struct *work)
3113{
3114 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3115 int i;
81906791 3116
81906791 3117 rtnl_lock();
af18d8b8
SH		 3118 for (i = 0; i < hw->ports; i++)
3119 sky2_detach(hw->dev[i]);
81906791 3120
8cfcbe99
SH		 3121 napi_disable(&hw->napi);
3122 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3123 sky2_reset(hw);
3124 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3125 napi_enable(&hw->napi);
81906791 3126
af18d8b8
SH		 3127 for (i = 0; i < hw->ports; i++)
3128 sky2_reattach(hw->dev[i]);
81906791 3129
81906791
SH		 3130 rtnl_unlock();
3131}
3132
e3173832
SH		 3133static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3134{
3135 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3136}
3137
3138static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3139{
3140 const struct sky2_port *sky2 = netdev_priv(dev);
3141
3142 wol->supported = sky2_wol_supported(sky2->hw);
3143 wol->wolopts = sky2->wol;
3144}
3145
3146static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3147{
3148 struct sky2_port *sky2 = netdev_priv(dev);
3149 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3150
9d731d77
RW		 3151 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3152 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3153 return -EOPNOTSUPP;
3154
3155 sky2->wol = wol->wolopts;
3156
05745c4a
SH		 3157 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3158 hw->chip_id == CHIP_ID_YUKON_EX ||
3159 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3160 sky2_write32(hw, B0_CTST, sky2->wol
3161 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3162
9d731d77
RW		 3163 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3164
e3173832
SH		 3165 if (!netif_running(dev))
3166 sky2_wol_init(sky2);
cd28ab6a
SH		 3167 return 0;
3168}
3169
28bd181a 3170static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3171{
b89165f2
SH		 3172 if (sky2_is_copper(hw)) {
3173 u32 modes = SUPPORTED_10baseT_Half
3174 | SUPPORTED_10baseT_Full
3175 | SUPPORTED_100baseT_Half
3176 | SUPPORTED_100baseT_Full
3177 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3178
ea76e635 3179 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3180 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3181 | SUPPORTED_1000baseT_Full;
3182 return modes;
cd28ab6a 3183 } else
b89165f2
SH		 3184 return SUPPORTED_1000baseT_Half
3185 | SUPPORTED_1000baseT_Full
3186 | SUPPORTED_Autoneg
3187 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3188}
3189
793b883e 3190static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3191{
3192 struct sky2_port *sky2 = netdev_priv(dev);
3193 struct sky2_hw *hw = sky2->hw;
3194
3195 ecmd->transceiver = XCVR_INTERNAL;
3196 ecmd->supported = sky2_supported_modes(hw);
3197 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3198 if (sky2_is_copper(hw)) {
cd28ab6a 3199 ecmd->port = PORT_TP;
b89165f2
SH		 3200 ecmd->speed = sky2->speed;
3201 } else {
3202 ecmd->speed = SPEED_1000;
cd28ab6a 3203 ecmd->port = PORT_FIBRE;
b89165f2 3204 }
cd28ab6a
SH		 3205
3206 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3207 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3208 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3209 ecmd->duplex = sky2->duplex;
3210 return 0;
3211}
3212
3213static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3214{
3215 struct sky2_port *sky2 = netdev_priv(dev);
3216 const struct sky2_hw *hw = sky2->hw;
3217 u32 supported = sky2_supported_modes(hw);
3218
3219 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3220 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3221 ecmd->advertising = supported;
3222 sky2->duplex = -1;
3223 sky2->speed = -1;
3224 } else {
3225 u32 setting;
3226
793b883e 3227 switch (ecmd->speed) {
cd28ab6a
SH		 3228 case SPEED_1000:
3229 if (ecmd->duplex == DUPLEX_FULL)
3230 setting = SUPPORTED_1000baseT_Full;
3231 else if (ecmd->duplex == DUPLEX_HALF)
3232 setting = SUPPORTED_1000baseT_Half;
3233 else
3234 return -EINVAL;
3235 break;
3236 case SPEED_100:
3237 if (ecmd->duplex == DUPLEX_FULL)
3238 setting = SUPPORTED_100baseT_Full;
3239 else if (ecmd->duplex == DUPLEX_HALF)
3240 setting = SUPPORTED_100baseT_Half;
3241 else
3242 return -EINVAL;
3243 break;
3244
3245 case SPEED_10:
3246 if (ecmd->duplex == DUPLEX_FULL)
3247 setting = SUPPORTED_10baseT_Full;
3248 else if (ecmd->duplex == DUPLEX_HALF)
3249 setting = SUPPORTED_10baseT_Half;
3250 else
3251 return -EINVAL;
3252 break;
3253 default:
3254 return -EINVAL;
3255 }
3256
3257 if ((setting & supported) == 0)
3258 return -EINVAL;
3259
3260 sky2->speed = ecmd->speed;
3261 sky2->duplex = ecmd->duplex;
0ea065e5 3262 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3263 }
3264
cd28ab6a
SH		 3265 sky2->advertising = ecmd->advertising;
3266
d1b139c0 3267 if (netif_running(dev)) {
1b537565 3268 sky2_phy_reinit(sky2);
d1b139c0
SH		 3269 sky2_set_multicast(dev);
3270 }
cd28ab6a
SH		 3271
3272 return 0;
3273}
3274
3275static void sky2_get_drvinfo(struct net_device *dev,
3276 struct ethtool_drvinfo *info)
3277{
3278 struct sky2_port *sky2 = netdev_priv(dev);
3279
3280 strcpy(info->driver, DRV_NAME);
3281 strcpy(info->version, DRV_VERSION);
3282 strcpy(info->fw_version, "N/A");
3283 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3284}
3285
3286static const struct sky2_stat {
793b883e
SH		 3287 char name[ETH_GSTRING_LEN];
3288 u16 offset;
cd28ab6a
SH		 3289} sky2_stats[] = {
3290 { "tx_bytes", GM_TXO_OK_HI },
3291 { "rx_bytes", GM_RXO_OK_HI },
3292 { "tx_broadcast", GM_TXF_BC_OK },
3293 { "rx_broadcast", GM_RXF_BC_OK },
3294 { "tx_multicast", GM_TXF_MC_OK },
3295 { "rx_multicast", GM_RXF_MC_OK },
3296 { "tx_unicast", GM_TXF_UC_OK },
3297 { "rx_unicast", GM_RXF_UC_OK },
3298 { "tx_mac_pause", GM_TXF_MPAUSE },
3299 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3300 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3301 { "late_collision",GM_TXF_LAT_COL },
3302 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3303 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3304 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3305
d2604540 3306 { "rx_short", GM_RXF_SHT },
cd28ab6a 3307 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3308 { "rx_64_byte_packets", GM_RXF_64B },
3309 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3310 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3311 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3312 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3313 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3314 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3315 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3316 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3317 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3318 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3319
3320 { "tx_64_byte_packets", GM_TXF_64B },
3321 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3322 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3323 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3324 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3325 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3326 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3327 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3328};
3329
cd28ab6a
SH		 3330static u32 sky2_get_rx_csum(struct net_device *dev)
3331{
3332 struct sky2_port *sky2 = netdev_priv(dev);
3333
0ea065e5 3334 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3335}
3336
3337static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3338{
3339 struct sky2_port *sky2 = netdev_priv(dev);
3340
0ea065e5
SH		 3341 if (data)
3342 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3343 else
3344 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3345
cd28ab6a
SH		 3346 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3347 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3348
3349 return 0;
3350}
3351
3352static u32 sky2_get_msglevel(struct net_device *netdev)
3353{
3354 struct sky2_port *sky2 = netdev_priv(netdev);
3355 return sky2->msg_enable;
3356}
3357
9a7ae0a9
SH		 3358static int sky2_nway_reset(struct net_device *dev)
3359{
3360 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3361
0ea065e5 3362 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3363 return -EINVAL;
3364
1b537565 3365 sky2_phy_reinit(sky2);
d1b139c0 3366 sky2_set_multicast(dev);
9a7ae0a9
SH		 3367
3368 return 0;
3369}
3370
793b883e 3371static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3372{
3373 struct sky2_hw *hw = sky2->hw;
3374 unsigned port = sky2->port;
3375 int i;
3376
3377 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3378 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3379 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3380 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3381
793b883e 3382 for (i = 2; i < count; i++)
cd28ab6a
SH		 3383 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3384}
3385
cd28ab6a
SH		 3386static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3387{
3388 struct sky2_port *sky2 = netdev_priv(netdev);
3389 sky2->msg_enable = value;
3390}
3391
b9f2c044 3392static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3393{
b9f2c044
JG		 3394 switch (sset) {
3395 case ETH_SS_STATS:
3396 return ARRAY_SIZE(sky2_stats);
3397 default:
3398 return -EOPNOTSUPP;
3399 }
cd28ab6a
SH		 3400}
3401
3402static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3403 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3404{
3405 struct sky2_port *sky2 = netdev_priv(dev);
3406
793b883e 3407 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3408}
3409
793b883e 3410static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3411{
3412 int i;
3413
3414 switch (stringset) {
3415 case ETH_SS_STATS:
3416 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3417 memcpy(data + i * ETH_GSTRING_LEN,
3418 sky2_stats[i].name, ETH_GSTRING_LEN);
3419 break;
3420 }
3421}
3422
cd28ab6a
SH		 3423static int sky2_set_mac_address(struct net_device *dev, void *p)
3424{
3425 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3426 struct sky2_hw *hw = sky2->hw;
3427 unsigned port = sky2->port;
3428 const struct sockaddr *addr = p;
cd28ab6a
SH		 3429
3430 if (!is_valid_ether_addr(addr->sa_data))
3431 return -EADDRNOTAVAIL;
3432
cd28ab6a 3433 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3434 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3435 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3436 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3437 dev->dev_addr, ETH_ALEN);
1b537565 3438
a8ab1ec0
SH		 3439 /* virtual address for data */
3440 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3441
3442 /* physical address: used for pause frames */
3443 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3444
3445 return 0;
cd28ab6a
SH		 3446}
3447
a052b52f
SH		 3448static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3449{
3450 u32 bit;
3451
3452 bit = ether_crc(ETH_ALEN, addr) & 63;
3453 filter[bit >> 3] |= 1 << (bit & 7);
3454}
3455
cd28ab6a
SH		 3456static void sky2_set_multicast(struct net_device *dev)
3457{
3458 struct sky2_port *sky2 = netdev_priv(dev);
3459 struct sky2_hw *hw = sky2->hw;
3460 unsigned port = sky2->port;
3461 struct dev_mc_list *list = dev->mc_list;
3462 u16 reg;
3463 u8 filter[8];
a052b52f
SH		 3464 int rx_pause;
3465 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3466
a052b52f 3467 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3468 memset(filter, 0, sizeof(filter));
3469
3470 reg = gma_read16(hw, port, GM_RX_CTRL);
3471 reg |= GM_RXCR_UCF_ENA;
3472
d571b694 3473 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3474 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3475 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3476 memset(filter, 0xff, sizeof(filter));
a052b52f 3477 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3478 reg &= ~GM_RXCR_MCF_ENA;
3479 else {
3480 int i;
3481 reg |= GM_RXCR_MCF_ENA;
3482
a052b52f
SH		 3483 if (rx_pause)
3484 sky2_add_filter(filter, pause_mc_addr);
3485
3486 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3487 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3488 }
3489
cd28ab6a 3490 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3491 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3492 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3493 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3494 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3495 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3496 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3497 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3498
3499 gma_write16(hw, port, GM_RX_CTRL, reg);
3500}
3501
3502/* Can have one global because blinking is controlled by
3503 * ethtool and that is always under RTNL mutex
3504 */
a84d0a3d 3505static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3506{
a84d0a3d
SH		 3507 struct sky2_hw *hw = sky2->hw;
3508 unsigned port = sky2->port;
793b883e 3509
a84d0a3d
SH		 3510 spin_lock_bh(&sky2->phy_lock);
3511 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3512 hw->chip_id == CHIP_ID_YUKON_EX ||
3513 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3514 u16 pg;
793b883e
SH		 3515 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3517
a84d0a3d
SH		 3518 switch (mode) {
3519 case MO_LED_OFF:
3520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3521 PHY_M_LEDC_LOS_CTRL(8) |
3522 PHY_M_LEDC_INIT_CTRL(8) |
3523 PHY_M_LEDC_STA1_CTRL(8) |
3524 PHY_M_LEDC_STA0_CTRL(8));
3525 break;
3526 case MO_LED_ON:
3527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3528 PHY_M_LEDC_LOS_CTRL(9) |
3529 PHY_M_LEDC_INIT_CTRL(9) |
3530 PHY_M_LEDC_STA1_CTRL(9) |
3531 PHY_M_LEDC_STA0_CTRL(9));
3532 break;
3533 case MO_LED_BLINK:
3534 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3535 PHY_M_LEDC_LOS_CTRL(0xa) |
3536 PHY_M_LEDC_INIT_CTRL(0xa) |
3537 PHY_M_LEDC_STA1_CTRL(0xa) |
3538 PHY_M_LEDC_STA0_CTRL(0xa));
3539 break;
3540 case MO_LED_NORM:
3541 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3542 PHY_M_LEDC_LOS_CTRL(1) |
3543 PHY_M_LEDC_INIT_CTRL(8) |
3544 PHY_M_LEDC_STA1_CTRL(7) |
3545 PHY_M_LEDC_STA0_CTRL(7));
3546 }
793b883e 3547
a84d0a3d
SH		 3548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3549 } else
7d2e3cb7 3550 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3551 PHY_M_LED_MO_DUP(mode) |
3552 PHY_M_LED_MO_10(mode) |
3553 PHY_M_LED_MO_100(mode) |
3554 PHY_M_LED_MO_1000(mode) |
3555 PHY_M_LED_MO_RX(mode) |
3556 PHY_M_LED_MO_TX(mode));
3557
3558 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3559}
3560
3561/* blink LED's for finding board */
3562static int sky2_phys_id(struct net_device *dev, u32 data)
3563{
3564 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3565 unsigned int i;
cd28ab6a 3566
a84d0a3d
SH		 3567 if (data == 0)
3568 data = UINT_MAX;
cd28ab6a 3569
a84d0a3d
SH		 3570 for (i = 0; i < data; i++) {
3571 sky2_led(sky2, MO_LED_ON);
3572 if (msleep_interruptible(500))
3573 break;
3574 sky2_led(sky2, MO_LED_OFF);
3575 if (msleep_interruptible(500))
3576 break;
793b883e 3577 }
a84d0a3d 3578 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3579
3580 return 0;
3581}
3582
3583static void sky2_get_pauseparam(struct net_device *dev,
3584 struct ethtool_pauseparam *ecmd)
3585{
3586 struct sky2_port *sky2 = netdev_priv(dev);
3587
16ad91e1
SH		 3588 switch (sky2->flow_mode) {
3589 case FC_NONE:
3590 ecmd->tx_pause = ecmd->rx_pause = 0;
3591 break;
3592 case FC_TX:
3593 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3594 break;
3595 case FC_RX:
3596 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3597 break;
3598 case FC_BOTH:
3599 ecmd->tx_pause = ecmd->rx_pause = 1;
3600 }
3601
0ea065e5
SH		 3602 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3603 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3604}
3605
3606static int sky2_set_pauseparam(struct net_device *dev,
3607 struct ethtool_pauseparam *ecmd)
3608{
3609 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3610
0ea065e5
SH		 3611 if (ecmd->autoneg == AUTONEG_ENABLE)
3612 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3613 else
3614 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3615
16ad91e1 3616 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3617
16ad91e1
SH		 3618 if (netif_running(dev))
3619 sky2_phy_reinit(sky2);
cd28ab6a 3620
2eaba1a2 3621 return 0;
cd28ab6a
SH		 3622}
3623
fb17358f
SH		 3624static int sky2_get_coalesce(struct net_device *dev,
3625 struct ethtool_coalesce *ecmd)
3626{
3627 struct sky2_port *sky2 = netdev_priv(dev);
3628 struct sky2_hw *hw = sky2->hw;
3629
3630 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3631 ecmd->tx_coalesce_usecs = 0;
3632 else {
3633 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3634 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3635 }
3636 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3637
3638 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3639 ecmd->rx_coalesce_usecs = 0;
3640 else {
3641 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3642 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3643 }
3644 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3645
3646 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3647 ecmd->rx_coalesce_usecs_irq = 0;
3648 else {
3649 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3650 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3651 }
3652
3653 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3654
3655 return 0;
3656}
3657
3658/* Note: this affect both ports */
3659static int sky2_set_coalesce(struct net_device *dev,
3660 struct ethtool_coalesce *ecmd)
3661{
3662 struct sky2_port *sky2 = netdev_priv(dev);
3663 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3664 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3665
77b3d6a2
SH		 3666 if (ecmd->tx_coalesce_usecs > tmax ||
3667 ecmd->rx_coalesce_usecs > tmax ||
3668 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3669 return -EINVAL;
3670
ff81fbbe 3671 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3672 return -EINVAL;
ff81fbbe 3673 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3674 return -EINVAL;
ff81fbbe 3675 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3676 return -EINVAL;
3677
3678 if (ecmd->tx_coalesce_usecs == 0)
3679 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3680 else {
3681 sky2_write32(hw, STAT_TX_TIMER_INI,
3682 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3683 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3684 }
3685 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3686
3687 if (ecmd->rx_coalesce_usecs == 0)
3688 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3689 else {
3690 sky2_write32(hw, STAT_LEV_TIMER_INI,
3691 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3692 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3693 }
3694 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3695
3696 if (ecmd->rx_coalesce_usecs_irq == 0)
3697 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3698 else {
d28d4870 3699 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3700 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3701 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3702 }
3703 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3704 return 0;
3705}
3706
793b883e
SH		 3707static void sky2_get_ringparam(struct net_device *dev,
3708 struct ethtool_ringparam *ering)
3709{
3710 struct sky2_port *sky2 = netdev_priv(dev);
3711
3712 ering->rx_max_pending = RX_MAX_PENDING;
3713 ering->rx_mini_max_pending = 0;
3714 ering->rx_jumbo_max_pending = 0;
3715 ering->tx_max_pending = TX_RING_SIZE - 1;
3716
3717 ering->rx_pending = sky2->rx_pending;
3718 ering->rx_mini_pending = 0;
3719 ering->rx_jumbo_pending = 0;
3720 ering->tx_pending = sky2->tx_pending;
3721}
3722
3723static int sky2_set_ringparam(struct net_device *dev,
3724 struct ethtool_ringparam *ering)
3725{
3726 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3727
3728 if (ering->rx_pending > RX_MAX_PENDING ||
3729 ering->rx_pending < 8 ||
3730 ering->tx_pending < MAX_SKB_TX_LE ||
3731 ering->tx_pending > TX_RING_SIZE - 1)
3732 return -EINVAL;
3733
af18d8b8 3734 sky2_detach(dev);
793b883e
SH		 3735
3736 sky2->rx_pending = ering->rx_pending;
3737 sky2->tx_pending = ering->tx_pending;
3738
af18d8b8 3739 return sky2_reattach(dev);
793b883e
SH		 3740}
3741
793b883e
SH		 3742static int sky2_get_regs_len(struct net_device *dev)
3743{
6e4cbb34 3744 return 0x4000;
793b883e
SH		 3745}
3746
3747/*
3748 * Returns copy of control register region
3ead5db7 3749 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3750 */
3751static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3752 void *p)
3753{
3754 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3755 const void __iomem *io = sky2->hw->regs;
295b54c4 3756 unsigned int b;
793b883e
SH		 3757
3758 regs->version = 1;
793b883e 3759
295b54c4
SH		 3760 for (b = 0; b < 128; b++) {
3761 /* This complicated switch statement is to make sure and
3762 * only access regions that are unreserved.
3763 * Some blocks are only valid on dual port cards.
3764 * and block 3 has some special diagnostic registers that
3765 * are poison.
3766 */
3767 switch (b) {
3768 case 3:
3769 /* skip diagnostic ram region */
3770 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3771 break;
3ead5db7 3772
295b54c4
SH		 3773 /* dual port cards only */
3774 case 5: /* Tx Arbiter 2 */
3775 case 9: /* RX2 */
3776 case 14 ... 15: /* TX2 */
3777 case 17: case 19: /* Ram Buffer 2 */
3778 case 22 ... 23: /* Tx Ram Buffer 2 */
3779 case 25: /* Rx MAC Fifo 1 */
3780 case 27: /* Tx MAC Fifo 2 */
3781 case 31: /* GPHY 2 */
3782 case 40 ... 47: /* Pattern Ram 2 */
3783 case 52: case 54: /* TCP Segmentation 2 */
3784 case 112 ... 116: /* GMAC 2 */
3785 if (sky2->hw->ports == 1)
3786 goto reserved;
3787 /* fall through */
3788 case 0: /* Control */
3789 case 2: /* Mac address */
3790 case 4: /* Tx Arbiter 1 */
3791 case 7: /* PCI express reg */
3792 case 8: /* RX1 */
3793 case 12 ... 13: /* TX1 */
3794 case 16: case 18:/* Rx Ram Buffer 1 */
3795 case 20 ... 21: /* Tx Ram Buffer 1 */
3796 case 24: /* Rx MAC Fifo 1 */
3797 case 26: /* Tx MAC Fifo 1 */
3798 case 28 ... 29: /* Descriptor and status unit */
3799 case 30: /* GPHY 1*/
3800 case 32 ... 39: /* Pattern Ram 1 */
3801 case 48: case 50: /* TCP Segmentation 1 */
3802 case 56 ... 60: /* PCI space */
3803 case 80 ... 84: /* GMAC 1 */
3804 memcpy_fromio(p, io, 128);
3805 break;
3806 default:
3807reserved:
3808 memset(p, 0, 128);
3809 }
3ead5db7 3810
295b54c4
SH		 3811 p += 128;
3812 io += 128;
3813 }
793b883e 3814}
cd28ab6a 3815
b628ed98
SH		 3816/* In order to do Jumbo packets on these chips, need to turn off the
3817 * transmit store/forward. Therefore checksum offload won't work.
3818 */
3819static int no_tx_offload(struct net_device *dev)
3820{
3821 const struct sky2_port *sky2 = netdev_priv(dev);
3822 const struct sky2_hw *hw = sky2->hw;
3823
69161611 3824 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3825}
3826
3827static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3828{
3829 if (data && no_tx_offload(dev))
3830 return -EINVAL;
3831
3832 return ethtool_op_set_tx_csum(dev, data);
3833}
3834
3835
3836static int sky2_set_tso(struct net_device *dev, u32 data)
3837{
3838 if (data && no_tx_offload(dev))
3839 return -EINVAL;
3840
3841 return ethtool_op_set_tso(dev, data);
3842}
3843
f4331a6d
SH		 3844static int sky2_get_eeprom_len(struct net_device *dev)
3845{
3846 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3847 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3848 u16 reg2;
3849
b32f40c4 3850 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3851 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3852}
3853
1413235c 3854static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3855{
1413235c 3856 unsigned long start = jiffies;
f4331a6d 3857
1413235c
SH		 3858 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3859 /* Can take up to 10.6 ms for write */
3860 if (time_after(jiffies, start + HZ/4)) {
3861 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3862 return -ETIMEDOUT;
3863 }
3864 mdelay(1);
3865 }
167f53d0 3866
1413235c
SH		 3867 return 0;
3868}
167f53d0 3869
1413235c
SH		 3870static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3871 u16 offset, size_t length)
3872{
3873 int rc = 0;
3874
3875 while (length > 0) {
3876 u32 val;
3877
3878 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3879 rc = sky2_vpd_wait(hw, cap, 0);
3880 if (rc)
3881 break;
3882
3883 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3884
3885 memcpy(data, &val, min(sizeof(val), length));
3886 offset += sizeof(u32);
3887 data += sizeof(u32);
3888 length -= sizeof(u32);
3889 }
3890
3891 return rc;
f4331a6d
SH		 3892}
3893
1413235c
SH		 3894static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3895 u16 offset, unsigned int length)
f4331a6d 3896{
1413235c
SH		 3897 unsigned int i;
3898 int rc = 0;
3899
3900 for (i = 0; i < length; i += sizeof(u32)) {
3901 u32 val = *(u32 *)(data + i);
3902
3903 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3904 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3905
3906 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3907 if (rc)
3908 break;
3909 }
3910 return rc;
f4331a6d
SH		 3911}
3912
3913static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3914 u8 *data)
3915{
3916 struct sky2_port *sky2 = netdev_priv(dev);
3917 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3918
3919 if (!cap)
3920 return -EINVAL;
3921
3922 eeprom->magic = SKY2_EEPROM_MAGIC;
3923
1413235c 3924 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3925}
3926
3927static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3928 u8 *data)
3929{
3930 struct sky2_port *sky2 = netdev_priv(dev);
3931 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3932
3933 if (!cap)
3934 return -EINVAL;
3935
3936 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3937 return -EINVAL;
3938
1413235c
SH		 3939 /* Partial writes not supported */
3940 if ((eeprom->offset & 3) || (eeprom->len & 3))
3941 return -EINVAL;
f4331a6d 3942
1413235c 3943 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3944}
3945
3946
7282d491 3947static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3948 .get_settings = sky2_get_settings,
3949 .set_settings = sky2_set_settings,
3950 .get_drvinfo = sky2_get_drvinfo,
3951 .get_wol = sky2_get_wol,
3952 .set_wol = sky2_set_wol,
3953 .get_msglevel = sky2_get_msglevel,
3954 .set_msglevel = sky2_set_msglevel,
3955 .nway_reset = sky2_nway_reset,
3956 .get_regs_len = sky2_get_regs_len,
3957 .get_regs = sky2_get_regs,
3958 .get_link = ethtool_op_get_link,
3959 .get_eeprom_len = sky2_get_eeprom_len,
3960 .get_eeprom = sky2_get_eeprom,
3961 .set_eeprom = sky2_set_eeprom,
f4331a6d 3962 .set_sg = ethtool_op_set_sg,
f4331a6d 3963 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3964 .set_tso = sky2_set_tso,
3965 .get_rx_csum = sky2_get_rx_csum,
3966 .set_rx_csum = sky2_set_rx_csum,
3967 .get_strings = sky2_get_strings,
3968 .get_coalesce = sky2_get_coalesce,
3969 .set_coalesce = sky2_set_coalesce,
3970 .get_ringparam = sky2_get_ringparam,
3971 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3972 .get_pauseparam = sky2_get_pauseparam,
3973 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3974 .phys_id = sky2_phys_id,
b9f2c044 3975 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3976 .get_ethtool_stats = sky2_get_ethtool_stats,
3977};
3978
3cf26753
SH		 3979#ifdef CONFIG_SKY2_DEBUG
3980
3981static struct dentry *sky2_debug;
3982
e4c2abe2
SH		 3983
3984/*
3985 * Read and parse the first part of Vital Product Data
3986 */
3987#define VPD_SIZE 128
3988#define VPD_MAGIC 0x82
3989
3990static const struct vpd_tag {
3991 char tag[2];
3992 char *label;
3993} vpd_tags[] = {
3994 { "PN", "Part Number" },
3995 { "EC", "Engineering Level" },
3996 { "MN", "Manufacturer" },
3997 { "SN", "Serial Number" },
3998 { "YA", "Asset Tag" },
3999 { "VL", "First Error Log Message" },
4000 { "VF", "Second Error Log Message" },
4001 { "VB", "Boot Agent ROM Configuration" },
4002 { "VE", "EFI UNDI Configuration" },
4003};
4004
4005static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4006{
4007 size_t vpd_size;
4008 loff_t offs;
4009 u8 len;
4010 unsigned char *buf;
4011 u16 reg2;
4012
4013 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4014 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4015
4016 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4017 buf = kmalloc(vpd_size, GFP_KERNEL);
4018 if (!buf) {
4019 seq_puts(seq, "no memory!\n");
4020 return;
4021 }
4022
4023 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4024 seq_puts(seq, "VPD read failed\n");
4025 goto out;
4026 }
4027
4028 if (buf[0] != VPD_MAGIC) {
4029 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4030 goto out;
4031 }
4032 len = buf[1];
4033 if (len == 0 || len > vpd_size - 4) {
4034 seq_printf(seq, "Invalid id length: %d\n", len);
4035 goto out;
4036 }
4037
4038 seq_printf(seq, "%.*s\n", len, buf + 3);
4039 offs = len + 3;
4040
4041 while (offs < vpd_size - 4) {
4042 int i;
4043
4044 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4045 break;
4046 len = buf[offs + 2];
4047 if (offs + len + 3 >= vpd_size)
4048 break;
4049
4050 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4051 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4052 seq_printf(seq, " %s: %.*s\n",
4053 vpd_tags[i].label, len, buf + offs + 3);
4054 break;
4055 }
4056 }
4057 offs += len + 3;
4058 }
4059out:
4060 kfree(buf);
4061}
4062
3cf26753
SH		 4063static int sky2_debug_show(struct seq_file *seq, void *v)
4064{
4065 struct net_device *dev = seq->private;
4066 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4067 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4068 unsigned port = sky2->port;
4069 unsigned idx, last;
4070 int sop;
4071
e4c2abe2 4072 sky2_show_vpd(seq, hw);
3cf26753 4073
e4c2abe2 4074 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4075 sky2_read32(hw, B0_ISRC),
4076 sky2_read32(hw, B0_IMSK),
4077 sky2_read32(hw, B0_Y2_SP_ICR));
4078
e4c2abe2
SH		 4079 if (!netif_running(dev)) {
4080 seq_printf(seq, "network not running\n");
4081 return 0;
4082 }
4083
bea3348e 4084 napi_disable(&hw->napi);
3cf26753
SH		 4085 last = sky2_read16(hw, STAT_PUT_IDX);
4086
4087 if (hw->st_idx == last)
4088 seq_puts(seq, "Status ring (empty)\n");
4089 else {
4090 seq_puts(seq, "Status ring\n");
4091 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4092 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4093 const struct sky2_status_le *le = hw->st_le + idx;
4094 seq_printf(seq, "[%d] %#x %d %#x\n",
4095 idx, le->opcode, le->length, le->status);
4096 }
4097 seq_puts(seq, "\n");
4098 }
4099
4100 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4101 sky2->tx_cons, sky2->tx_prod,
4102 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4103 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4104
4105 /* Dump contents of tx ring */
4106 sop = 1;
4107 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4108 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4109 const struct sky2_tx_le *le = sky2->tx_le + idx;
4110 u32 a = le32_to_cpu(le->addr);
4111
4112 if (sop)
4113 seq_printf(seq, "%u:", idx);
4114 sop = 0;
4115
4116 switch(le->opcode & ~HW_OWNER) {
4117 case OP_ADDR64:
4118 seq_printf(seq, " %#x:", a);
4119 break;
4120 case OP_LRGLEN:
4121 seq_printf(seq, " mtu=%d", a);
4122 break;
4123 case OP_VLAN:
4124 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4125 break;
4126 case OP_TCPLISW:
4127 seq_printf(seq, " csum=%#x", a);
4128 break;
4129 case OP_LARGESEND:
4130 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4131 break;
4132 case OP_PACKET:
4133 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4134 break;
4135 case OP_BUFFER:
4136 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4137 break;
4138 default:
4139 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4140 a, le16_to_cpu(le->length));
4141 }
4142
4143 if (le->ctrl & EOP) {
4144 seq_putc(seq, '\n');
4145 sop = 1;
4146 }
4147 }
4148
4149 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4150 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4151 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4152 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4153
d1d08d12 4154 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4155 napi_enable(&hw->napi);
3cf26753
SH		 4156 return 0;
4157}
4158
4159static int sky2_debug_open(struct inode *inode, struct file *file)
4160{
4161 return single_open(file, sky2_debug_show, inode->i_private);
4162}
4163
4164static const struct file_operations sky2_debug_fops = {
4165 .owner = THIS_MODULE,
4166 .open = sky2_debug_open,
4167 .read = seq_read,
4168 .llseek = seq_lseek,
4169 .release = single_release,
4170};
4171
4172/*
4173 * Use network device events to create/remove/rename
4174 * debugfs file entries
4175 */
4176static int sky2_device_event(struct notifier_block *unused,
4177 unsigned long event, void *ptr)
4178{
4179 struct net_device *dev = ptr;
5b296bc9 4180 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4181
1436b301 4182 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4183 return NOTIFY_DONE;
3cf26753 4184
5b296bc9
SH		 4185 switch(event) {
4186 case NETDEV_CHANGENAME:
4187 if (sky2->debugfs) {
4188 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4189 sky2_debug, dev->name);
4190 }
4191 break;
3cf26753 4192
5b296bc9
SH		 4193 case NETDEV_GOING_DOWN:
4194 if (sky2->debugfs) {
4195 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4196 dev->name);
4197 debugfs_remove(sky2->debugfs);
4198 sky2->debugfs = NULL;
3cf26753 4199 }
5b296bc9
SH		 4200 break;
4201
4202 case NETDEV_UP:
4203 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4204 sky2_debug, dev,
4205 &sky2_debug_fops);
4206 if (IS_ERR(sky2->debugfs))
4207 sky2->debugfs = NULL;
3cf26753
SH		 4208 }
4209
4210 return NOTIFY_DONE;
4211}
4212
4213static struct notifier_block sky2_notifier = {
4214 .notifier_call = sky2_device_event,
4215};
4216
4217
4218static __init void sky2_debug_init(void)
4219{
4220 struct dentry *ent;
4221
4222 ent = debugfs_create_dir("sky2", NULL);
4223 if (!ent || IS_ERR(ent))
4224 return;
4225
4226 sky2_debug = ent;
4227 register_netdevice_notifier(&sky2_notifier);
4228}
4229
4230static __exit void sky2_debug_cleanup(void)
4231{
4232 if (sky2_debug) {
4233 unregister_netdevice_notifier(&sky2_notifier);
4234 debugfs_remove(sky2_debug);
4235 sky2_debug = NULL;
4236 }
4237}
4238
4239#else
4240#define sky2_debug_init()
4241#define sky2_debug_cleanup()
4242#endif
4243
1436b301
SH		 4244/* Two copies of network device operations to handle special case of
4245 not allowing netpoll on second port */
4246static const struct net_device_ops sky2_netdev_ops[2] = {
4247 {
4248 .ndo_open = sky2_up,
4249 .ndo_stop = sky2_down,
00829823 4250 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4251 .ndo_do_ioctl = sky2_ioctl,
4252 .ndo_validate_addr = eth_validate_addr,
4253 .ndo_set_mac_address = sky2_set_mac_address,
4254 .ndo_set_multicast_list = sky2_set_multicast,
4255 .ndo_change_mtu = sky2_change_mtu,
4256 .ndo_tx_timeout = sky2_tx_timeout,
4257#ifdef SKY2_VLAN_TAG_USED
4258 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4259#endif
4260#ifdef CONFIG_NET_POLL_CONTROLLER
4261 .ndo_poll_controller = sky2_netpoll,
4262#endif
4263 },
4264 {
4265 .ndo_open = sky2_up,
4266 .ndo_stop = sky2_down,
00829823 4267 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4268 .ndo_do_ioctl = sky2_ioctl,
4269 .ndo_validate_addr = eth_validate_addr,
4270 .ndo_set_mac_address = sky2_set_mac_address,
4271 .ndo_set_multicast_list = sky2_set_multicast,
4272 .ndo_change_mtu = sky2_change_mtu,
4273 .ndo_tx_timeout = sky2_tx_timeout,
4274#ifdef SKY2_VLAN_TAG_USED
4275 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4276#endif
4277 },
4278};
3cf26753 4279
cd28ab6a
SH		 4280/* Initialize network device */
4281static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4282 unsigned port,
be63a21c 4283 int highmem, int wol)
cd28ab6a
SH		 4284{
4285 struct sky2_port *sky2;
4286 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4287
4288 if (!dev) {
898eb71c 4289 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4290 return NULL;
4291 }
4292
cd28ab6a 4293 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4294 dev->irq = hw->pdev->irq;
cd28ab6a 4295 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4296 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4297 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4298
4299 sky2 = netdev_priv(dev);
4300 sky2->netdev = dev;
4301 sky2->hw = hw;
4302 sky2->msg_enable = netif_msg_init(debug, default_msg);
4303
cd28ab6a 4304 /* Auto speed and flow control */
0ea065e5
SH		 4305 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4306 if (hw->chip_id != CHIP_ID_YUKON_XL)
4307 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4308
16ad91e1
SH		 4309 sky2->flow_mode = FC_BOTH;
4310
cd28ab6a
SH		 4311 sky2->duplex = -1;
4312 sky2->speed = -1;
4313 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4314 sky2->wol = wol;
75d070c5 4315
e07b1aa8 4316 spin_lock_init(&sky2->phy_lock);
793b883e 4317 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4318 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4319
4320 hw->dev[port] = dev;
4321
4322 sky2->port = port;
4323
4a50a876 4324 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4325 if (highmem)
4326 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4327
d1f13708 4328#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4329 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4330 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4331 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4332 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4333 }
d1f13708
SH		 4334#endif
4335
cd28ab6a 4336 /* read the mac address */
793b883e 4337 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4338 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4339
cd28ab6a
SH		 4340 return dev;
4341}
4342
28bd181a 4343static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4344{
4345 const struct sky2_port *sky2 = netdev_priv(dev);
4346
4347 if (netif_msg_probe(sky2))
e174961c
JB		 4348 printk(KERN_INFO PFX "%s: addr %pM\n",
4349 dev->name, dev->dev_addr);
cd28ab6a
SH		 4350}
4351
fb2690a9 4352/* Handle software interrupt used during MSI test */
7d12e780 4353static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4354{
4355 struct sky2_hw *hw = dev_id;
4356 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4357
4358 if (status == 0)
4359 return IRQ_NONE;
4360
4361 if (status & Y2_IS_IRQ_SW) {
ea76e635 4362 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4363 wake_up(&hw->msi_wait);
4364 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4365 }
4366 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4367
4368 return IRQ_HANDLED;
4369}
4370
4371/* Test interrupt path by forcing a a software IRQ */
4372static int __devinit sky2_test_msi(struct sky2_hw *hw)
4373{
4374 struct pci_dev *pdev = hw->pdev;
4375 int err;
4376
bb507fe1
SH		 4377 init_waitqueue_head (&hw->msi_wait);
4378
fb2690a9
SH		 4379 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4380
b0a20ded 4381 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4382 if (err) {
b02a9258 4383 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4384 return err;
4385 }
4386
fb2690a9 4387 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4388 sky2_read8(hw, B0_CTST);
fb2690a9 4389
ea76e635 4390 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4391
ea76e635 4392 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4393 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4394 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4395 "switching to INTx mode.\n");
fb2690a9
SH		 4396
4397 err = -EOPNOTSUPP;
4398 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4399 }
4400
4401 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4402 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4403
4404 free_irq(pdev->irq, hw);
4405
4406 return err;
4407}
4408
c7127a34
SH		 4409/* This driver supports yukon2 chipset only */
4410static const char *sky2_name(u8 chipid, char *buf, int sz)
4411{
4412 const char *name[] = {
4413 "XL", /* 0xb3 */
4414 "EC Ultra", /* 0xb4 */
4415 "Extreme", /* 0xb5 */
4416 "EC", /* 0xb6 */
4417 "FE", /* 0xb7 */
4418 "FE+", /* 0xb8 */
4419 "Supreme", /* 0xb9 */
0ce8b98d 4420 "UL 2", /* 0xba */
c7127a34
SH		 4421 };
4422
0ce8b98d 4423 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4424 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4425 else
4426 snprintf(buf, sz, "(chip %#x)", chipid);
4427 return buf;
4428}
4429
cd28ab6a
SH		 4430static int __devinit sky2_probe(struct pci_dev *pdev,
4431 const struct pci_device_id *ent)
4432{
7f60c64b 4433 struct net_device *dev;
cd28ab6a 4434 struct sky2_hw *hw;
be63a21c 4435 int err, using_dac = 0, wol_default;
3834507d 4436 u32 reg;
c7127a34 4437 char buf1[16];
cd28ab6a 4438
793b883e
SH		 4439 err = pci_enable_device(pdev);
4440 if (err) {
b02a9258 4441 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4442 goto err_out;
4443 }
4444
6cc90a5a
SH		 4445 /* Get configuration information
4446 * Note: only regular PCI config access once to test for HW issues
4447 * other PCI access through shared memory for speed and to
4448 * avoid MMCONFIG problems.
4449 */
4450 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4451 if (err) {
4452 dev_err(&pdev->dev, "PCI read config failed\n");
4453 goto err_out;
4454 }
4455
4456 if (~reg == 0) {
4457 dev_err(&pdev->dev, "PCI configuration read error\n");
4458 goto err_out;
4459 }
4460
793b883e
SH		 4461 err = pci_request_regions(pdev, DRV_NAME);
4462 if (err) {
b02a9258 4463 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4464 goto err_out_disable;
cd28ab6a
SH		 4465 }
4466
4467 pci_set_master(pdev);
4468
d1f3d4dd 4469 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4470 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4471 using_dac = 1;
6a35528a 4472 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4473 if (err < 0) {
b02a9258
SH		 4474 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4475 "for consistent allocations\n");
d1f3d4dd
SH		 4476 goto err_out_free_regions;
4477 }
d1f3d4dd 4478 } else {
284901a9 4479 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4480 if (err) {
b02a9258 4481 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4482 goto err_out_free_regions;
4483 }
4484 }
d1f3d4dd 4485
3834507d
SH		 4486
4487#ifdef __BIG_ENDIAN
4488 /* The sk98lin vendor driver uses hardware byte swapping but
4489 * this driver uses software swapping.
4490 */
4491 reg &= ~PCI_REV_DESC;
4492 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4493 if (err) {
4494 dev_err(&pdev->dev, "PCI write config failed\n");
4495 goto err_out_free_regions;
4496 }
4497#endif
4498
9d731d77 4499 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4500
cd28ab6a 4501 err = -ENOMEM;
6aad85d6 4502 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4503 if (!hw) {
b02a9258 4504 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4505 goto err_out_free_regions;
4506 }
4507
cd28ab6a 4508 hw->pdev = pdev;
cd28ab6a
SH		 4509
4510 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4511 if (!hw->regs) {
b02a9258 4512 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4513 goto err_out_free_hw;
4514 }
4515
08c06d8a 4516 /* ring for status responses */
167f53d0 4517 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4518 if (!hw->st_le)
4519 goto err_out_iounmap;
4520
e3173832 4521 err = sky2_init(hw);
cd28ab6a 4522 if (err)
793b883e 4523 goto err_out_iounmap;
cd28ab6a 4524
c844d483
SH		 4525 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4526 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4527
e3173832
SH		 4528 sky2_reset(hw);
4529
be63a21c 4530 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4531 if (!dev) {
4532 err = -ENOMEM;
cd28ab6a 4533 goto err_out_free_pci;
7f60c64b 4534 }
cd28ab6a 4535
9fa1b1f3
SH		 4536 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4537 err = sky2_test_msi(hw);
4538 if (err == -EOPNOTSUPP)
4539 pci_disable_msi(pdev);
4540 else if (err)
4541 goto err_out_free_netdev;
4542 }
4543
793b883e
SH		 4544 err = register_netdev(dev);
4545 if (err) {
b02a9258 4546 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4547 goto err_out_free_netdev;
4548 }
4549
6de16237
SH		 4550 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4551
ea76e635
SH		 4552 err = request_irq(pdev->irq, sky2_intr,
4553 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4554 dev->name, hw);
9fa1b1f3 4555 if (err) {
b02a9258 4556 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4557 goto err_out_unregister;
4558 }
4559 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4560 napi_enable(&hw->napi);
9fa1b1f3 4561
cd28ab6a
SH		 4562 sky2_show_addr(dev);
4563
7f60c64b 4564 if (hw->ports > 1) {
4565 struct net_device *dev1;
4566
be63a21c 4567 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4568 if (!dev1)
4569 dev_warn(&pdev->dev, "allocation for second device failed\n");
4570 else if ((err = register_netdev(dev1))) {
4571 dev_warn(&pdev->dev,
4572 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4573 hw->dev[1] = NULL;
4574 free_netdev(dev1);
b02a9258
SH		 4575 } else
4576 sky2_show_addr(dev1);
cd28ab6a
SH		 4577 }
4578
32c2c300 4579 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4580 INIT_WORK(&hw->restart_work, sky2_restart);
4581
793b883e
SH		 4582 pci_set_drvdata(pdev, hw);
4583
cd28ab6a
SH		 4584 return 0;
4585
793b883e 4586err_out_unregister:
ea76e635 4587 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4588 pci_disable_msi(pdev);
793b883e 4589 unregister_netdev(dev);
cd28ab6a
SH		 4590err_out_free_netdev:
4591 free_netdev(dev);
cd28ab6a 4592err_out_free_pci:
793b883e 4593 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4594 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4595err_out_iounmap:
4596 iounmap(hw->regs);
4597err_out_free_hw:
4598 kfree(hw);
4599err_out_free_regions:
4600 pci_release_regions(pdev);
44a1d2e5 4601err_out_disable:
cd28ab6a 4602 pci_disable_device(pdev);
cd28ab6a 4603err_out:
549a68c3 4604 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4605 return err;
4606}
4607
4608static void __devexit sky2_remove(struct pci_dev *pdev)
4609{
793b883e 4610 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4611 int i;
cd28ab6a 4612
793b883e 4613 if (!hw)
cd28ab6a
SH		 4614 return;
4615
32c2c300 4616 del_timer_sync(&hw->watchdog_timer);
6de16237 4617 cancel_work_sync(&hw->restart_work);
d27ed387 4618
b877fe28 4619 for (i = hw->ports-1; i >= 0; --i)
6de16237 4620 unregister_netdev(hw->dev[i]);
81906791 4621
d27ed387 4622 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4623
ae306cca
SH		 4624 sky2_power_aux(hw);
4625
cd28ab6a 4626 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4627 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4628 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4629
4630 free_irq(pdev->irq, hw);
ea76e635 4631 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4632 pci_disable_msi(pdev);
793b883e 4633 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4634 pci_release_regions(pdev);
4635 pci_disable_device(pdev);
793b883e 4636
b877fe28 4637 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4638 free_netdev(hw->dev[i]);
4639
cd28ab6a
SH		 4640 iounmap(hw->regs);
4641 kfree(hw);
5afa0a9c 4642
cd28ab6a
SH		 4643 pci_set_drvdata(pdev, NULL);
4644}
4645
4646#ifdef CONFIG_PM
4647static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4648{
793b883e 4649 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4650 int i, wol = 0;
cd28ab6a 4651
549a68c3
SH		 4652 if (!hw)
4653 return 0;
4654
063a0b38
SH		 4655 del_timer_sync(&hw->watchdog_timer);
4656 cancel_work_sync(&hw->restart_work);
4657
19720737 4658 rtnl_lock();
f05267e7 4659 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4660 struct net_device *dev = hw->dev[i];
e3173832 4661 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4662
af18d8b8 4663 sky2_detach(dev);
e3173832
SH		 4664
4665 if (sky2->wol)
4666 sky2_wol_init(sky2);
4667
4668 wol |= sky2->wol;
cd28ab6a
SH		 4669 }
4670
8ab8fca2 4671 sky2_write32(hw, B0_IMSK, 0);
6de16237 4672 napi_disable(&hw->napi);
ae306cca 4673 sky2_power_aux(hw);
19720737 4674 rtnl_unlock();
e3173832 4675
d374c1c1 4676 pci_save_state(pdev);
e3173832 4677 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4678 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4679
2ccc99b7 4680 return 0;
cd28ab6a
SH		 4681}
4682
4683static int sky2_resume(struct pci_dev *pdev)
4684{
793b883e 4685 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4686 int i, err;
cd28ab6a 4687
549a68c3
SH		 4688 if (!hw)
4689 return 0;
4690
f71eb1a2
SH		 4691 err = pci_set_power_state(pdev, PCI_D0);
4692 if (err)
4693 goto out;
ae306cca
SH		 4694
4695 err = pci_restore_state(pdev);
4696 if (err)
4697 goto out;
4698
cd28ab6a 4699 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4700
4701 /* Re-enable all clocks */
05745c4a
SH		 4702 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4703 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4704 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4705 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4706
e3173832 4707 sky2_reset(hw);
8ab8fca2 4708 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4709 napi_enable(&hw->napi);
8ab8fca2 4710
af18d8b8 4711 rtnl_lock();
f05267e7 4712 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4713 err = sky2_reattach(hw->dev[i]);
4714 if (err)
4715 goto out;
cd28ab6a 4716 }
af18d8b8 4717 rtnl_unlock();
eb35cf60 4718
ae306cca 4719 return 0;
08c06d8a 4720out:
af18d8b8
SH		 4721 rtnl_unlock();
4722
b02a9258 4723 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4724 pci_disable_device(pdev);
08c06d8a 4725 return err;
cd28ab6a
SH		 4726}
4727#endif
4728
e3173832
SH		 4729static void sky2_shutdown(struct pci_dev *pdev)
4730{
4731 struct sky2_hw *hw = pci_get_drvdata(pdev);
4732 int i, wol = 0;
4733
549a68c3
SH		 4734 if (!hw)
4735 return;
4736
19720737 4737 rtnl_lock();
5c0d6b34 4738 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4739
4740 for (i = 0; i < hw->ports; i++) {
4741 struct net_device *dev = hw->dev[i];
4742 struct sky2_port *sky2 = netdev_priv(dev);
4743
4744 if (sky2->wol) {
4745 wol = 1;
4746 sky2_wol_init(sky2);
4747 }
4748 }
4749
4750 if (wol)
4751 sky2_power_aux(hw);
19720737 4752 rtnl_unlock();
e3173832
SH		 4753
4754 pci_enable_wake(pdev, PCI_D3hot, wol);
4755 pci_enable_wake(pdev, PCI_D3cold, wol);
4756
4757 pci_disable_device(pdev);
f71eb1a2 4758 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4759}
4760
cd28ab6a 4761static struct pci_driver sky2_driver = {
793b883e
SH		 4762 .name = DRV_NAME,
4763 .id_table = sky2_id_table,
4764 .probe = sky2_probe,
4765 .remove = __devexit_p(sky2_remove),
cd28ab6a 4766#ifdef CONFIG_PM
793b883e
SH		 4767 .suspend = sky2_suspend,
4768 .resume = sky2_resume,
cd28ab6a 4769#endif
e3173832 4770 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4771};
4772
4773static int __init sky2_init_module(void)
4774{
c844d483
SH		 4775 pr_info(PFX "driver version " DRV_VERSION "\n");
4776
3cf26753 4777 sky2_debug_init();
50241c4c 4778 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4779}
4780
4781static void __exit sky2_cleanup_module(void)
4782{
4783 pci_unregister_driver(&sky2_driver);
3cf26753 4784 sky2_debug_cleanup();
cd28ab6a
SH		 4785}
4786
4787module_init(sky2_init_module);
4788module_exit(sky2_cleanup_module);
4789
4790MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4791MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4792MODULE_LICENSE("GPL");
5f4f9dc1 4793MODULE_VERSION(DRV_VERSION);
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