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sky2: reduce default transmit ring
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
743d32ad 53#define DRV_VERSION "1.22"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 66
67#define TX_RING_SIZE 512
e9c1be80 68#define TX_DEF_PENDING 128
b19666d9 69#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH		 78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33
SH		 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH		 259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH		 294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH		 319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
ea76e635
SH		 324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH		 337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH		 358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 366 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH		 373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH		 380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH		 386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH		 402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a
SH		 410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
16ad91e1 426 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 432
16ad91e1 433 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 434 }
cd28ab6a
SH		 435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
2eaba1a2
SH		 442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
2eaba1a2 448 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
2eaba1a2 452 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 453 break;
454 }
455
2eaba1a2
SH		 456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
2eaba1a2 461
2eaba1a2 462
16ad91e1 463 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 464
465 /* Forward pause packets to GMAC? */
16ad91e1 466 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 470 }
471
2eaba1a2
SH		 472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
05745c4a 474 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
05745c4a
SH		 498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
cd28ab6a 515 case CHIP_ID_YUKON_XL:
793b883e 516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 536
537 /* restore page register */
793b883e 538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 539 break;
93745494 540
ed6d32c7 541 case CHIP_ID_YUKON_EC_U:
93745494 542 case CHIP_ID_YUKON_EX:
ed4d4161 543 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
cd28ab6a
SH		 562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 566
cd28ab6a 567 /* turn off the Rx LED (LED_RX) */
a84d0a3d 568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 569 }
570
0ce8b98d 571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 572 /* apply fixes in PHY AFE */
ed6d32c7
SH		 573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
977bdf06 575 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 578
0ce8b98d
SH		 579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
977bdf06
SH		 584
585 /* set page register to 0 */
9467a8fc 586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 594 /* no effect on Yukon-XL */
977bdf06 595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 596
977bdf06
SH		 597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 600 }
cd28ab6a 601
977bdf06
SH		 602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
2eaba1a2 606
d571b694 607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612}
613
b96936da
SH		 614static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 618{
619 u32 reg1;
d3bcfbeb 620
82637e80 621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 623 reg1 &= ~phy_power[port];
d3bcfbeb 624
b96936da 625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 626 reg1 |= coma_mode[port];
627
b32f40c4 628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 636}
167f53d0 637
b96936da
SH		 638static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639{
640 u32 reg1;
db99b988
SH		 641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 670
e484d5f5 671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
b96936da
SH		 683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 689}
690
1b537565
SH		 691/* Force a renegotiation */
692static void sky2_phy_reinit(struct sky2_port *sky2)
693{
e07b1aa8 694 spin_lock_bh(&sky2->phy_lock);
1b537565 695 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 696 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 697}
698
e3173832
SH		 699/* Put device in state to listen for Wake On Lan */
700static void sky2_wol_init(struct sky2_port *sky2)
701{
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
b96936da
SH		 723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
b32f40c4 758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 759 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765}
766
69161611
SH		 767static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768{
05745c4a
SH		 769 struct net_device *dev = hw->dev[port];
770
ed4d4161
SH		 771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
05745c4a 777
ed4d4161
SH		 778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 781
ed4d4161
SH		 782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 792
ed4d4161
SH		 793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
69161611
SH		 798 }
799}
800
cd28ab6a
SH		 801static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802{
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
25cccecc 805 u32 rx_reg;
cd28ab6a
SH		 806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
f350339c
SH		 809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
793b883e 814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
793b883e 826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 827
2eaba1a2
SH		 828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
e07b1aa8 831 spin_lock_bh(&sky2->phy_lock);
b96936da 832 sky2_phy_power_up(hw, port);
cd28ab6a 833 sky2_phy_init(hw, port);
e07b1aa8 834 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
43f2f104
SH		 840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
cd28ab6a
SH		 842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
793b883e 849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 864
6b1a3aef 865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
cd28ab6a
SH		 870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
793b883e
SH		 873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
cd28ab6a
SH		 877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 886 rx_reg |= GMF_RX_OVER_ON;
69161611 887
25cccecc 888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 889
798fdd07
SH		 890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
cd28ab6a 897
8df9a876 898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 909
e0c28116 910 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 914
69161611 915 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 916 }
917
e970d1f8
SH		 918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
cd28ab6a
SH		 925}
926
67712901
SH		 927/* Assign Ram Buffer allocation to queue */
928static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 929{
67712901
SH		 930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
793b883e 936
cd28ab6a
SH		 937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 944 u32 tp = space - space/4;
793b883e 945
1c28f6ba
SH		 946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 952
1c28f6ba
SH		 953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 965}
966
cd28ab6a 967/* Setup Bus Memory Interface */
af4ed7e6 968static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 969{
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 974}
975
cd28ab6a
SH		 976/* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
8cc048e3 979static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 980 u64 addr, u32 last)
981{
cd28ab6a
SH		 982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 990}
991
793b883e
SH		 992static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993{
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
cb5d9547 996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 997 le->ctrl = 0;
793b883e
SH		 998 return le;
999}
cd28ab6a 1000
88f5f0ca
SH		 1001static void tx_init(struct sky2_port *sky2)
1002{
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1012}
1013
291ea614
SH		 1014static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016{
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018}
1019
290d4de5
SH		 1020/* Update chip's next pointer */
1021static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1022{
50432cb5 1023 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1024 wmb();
50432cb5
SH		 1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
cd28ab6a
SH		 1029}
1030
793b883e 1031
cd28ab6a
SH		 1032static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033{
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1036 le->ctrl = 0;
cd28ab6a
SH		 1037 return le;
1038}
1039
14d0263f
SH		 1040/* Build description to hardware for one receive segment */
1041static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1043{
1044 struct sky2_rx_le *le;
1045
86c6887e 1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1047 le = sky2_next_rx(sky2);
86c6887e 1048 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
793b883e 1051
cd28ab6a 1052 le = sky2_next_rx(sky2);
734d1868
SH		 1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
14d0263f 1055 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1056}
1057
14d0263f
SH		 1058/* Build description to hardware for one possibly fragmented skb */
1059static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061{
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068}
1069
1070
454e6cb6 1071static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1072 unsigned size)
1073{
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
14d0263f
SH		 1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
454e6cb6 1089 return 0;
14d0263f
SH		 1090}
1091
1092static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093{
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104}
793b883e 1105
cd28ab6a
SH		 1106/* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
793b883e 1110static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1111{
ea76e635 1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1113
ea76e635
SH		 1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1117
ea76e635
SH		 1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1121}
1122
6b1a3aef
SH		 1123/*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133static void sky2_rx_stop(struct sky2_port *sky2)
1134{
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
c0bad0f2
SH		 1154
1155 /* Reset the RAM Buffer receive queue */
1156 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);
1157
1158 /* Reset Rx MAC FIFO */
1159 sky2_write8(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), GMF_RST_SET);
1160
1161 sky2_read8(hw, B0_CTST);
6b1a3aef 1162}
793b883e 1163
d571b694 1164/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1165static void sky2_rx_clean(struct sky2_port *sky2)
1166{
1167 unsigned i;
1168
1169 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1170 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1171 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1172
1173 if (re->skb) {
14d0263f 1174 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1175 kfree_skb(re->skb);
1176 re->skb = NULL;
1177 }
1178 }
1179}
1180
ef743d33
SH		 1181/* Basic MII support */
1182static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1183{
1184 struct mii_ioctl_data *data = if_mii(ifr);
1185 struct sky2_port *sky2 = netdev_priv(dev);
1186 struct sky2_hw *hw = sky2->hw;
1187 int err = -EOPNOTSUPP;
1188
1189 if (!netif_running(dev))
1190 return -ENODEV; /* Phy still in reset */
1191
d89e1343 1192 switch (cmd) {
ef743d33
SH		 1193 case SIOCGMIIPHY:
1194 data->phy_id = PHY_ADDR_MARV;
1195
1196 /* fallthru */
1197 case SIOCGMIIREG: {
1198 u16 val = 0;
91c86df5 1199
e07b1aa8 1200 spin_lock_bh(&sky2->phy_lock);
ef743d33 1201 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1202 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1203
ef743d33
SH		 1204 data->val_out = val;
1205 break;
1206 }
1207
1208 case SIOCSMIIREG:
1209 if (!capable(CAP_NET_ADMIN))
1210 return -EPERM;
1211
e07b1aa8 1212 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1213 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1214 data->val_in);
e07b1aa8 1215 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1216 break;
1217 }
1218 return err;
1219}
1220
d1f13708 1221#ifdef SKY2_VLAN_TAG_USED
d494eacd 1222static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1223{
d494eacd 1224 if (onoff) {
3d4e66f5
SH		 1225 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1226 RX_VLAN_STRIP_ON);
1227 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1228 TX_VLAN_TAG_ON);
1229 } else {
1230 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1231 RX_VLAN_STRIP_OFF);
1232 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1233 TX_VLAN_TAG_OFF);
1234 }
d494eacd
SH		 1235}
1236
1237static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1238{
1239 struct sky2_port *sky2 = netdev_priv(dev);
1240 struct sky2_hw *hw = sky2->hw;
1241 u16 port = sky2->port;
1242
1243 netif_tx_lock_bh(dev);
1244 napi_disable(&hw->napi);
1245
1246 sky2->vlgrp = grp;
1247 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1248
d1d08d12 1249 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1250 napi_enable(&hw->napi);
2bb8c262 1251 netif_tx_unlock_bh(dev);
d1f13708
SH		 1252}
1253#endif
1254
82788c7a 1255/*
14d0263f
SH		 1256 * Allocate an skb for receiving. If the MTU is large enough
1257 * make the skb non-linear with a fragment list of pages.
82788c7a 1258 */
14d0263f 1259static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1260{
1261 struct sk_buff *skb;
14d0263f 1262 int i;
82788c7a 1263
39dbd958 1264 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1265 unsigned char *start;
1266 /*
1267 * Workaround for a bug in FIFO that cause hang
1268 * if the FIFO if the receive buffer is not 64 byte aligned.
1269 * The buffer returned from netdev_alloc_skb is
1270 * aligned except if slab debugging is enabled.
1271 */
1272 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1273 if (!skb)
1274 goto nomem;
1275 start = PTR_ALIGN(skb->data, 8);
1276 skb_reserve(skb, start - skb->data);
1277 } else {
1278 skb = netdev_alloc_skb(sky2->netdev,
1279 sky2->rx_data_size + NET_IP_ALIGN);
1280 if (!skb)
1281 goto nomem;
1282 skb_reserve(skb, NET_IP_ALIGN);
1283 }
14d0263f
SH		 1284
1285 for (i = 0; i < sky2->rx_nfrags; i++) {
1286 struct page *page = alloc_page(GFP_ATOMIC);
1287
1288 if (!page)
1289 goto free_partial;
1290 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1291 }
1292
1293 return skb;
14d0263f
SH		 1294free_partial:
1295 kfree_skb(skb);
1296nomem:
1297 return NULL;
82788c7a
SH		 1298}
1299
55c9dd35
SH		 1300static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1301{
1302 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1303}
1304
cd28ab6a
SH		 1305/*
1306 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1307 * Normal case this ends up creating one list element for skb
1308 * in the receive ring. Worst case if using large MTU and each
1309 * allocation falls on a different 64 bit region, that results
1310 * in 6 list elements per ring entry.
1311 * One element is used for checksum enable/disable, and one
1312 * extra to avoid wrap.
cd28ab6a 1313 */
6b1a3aef 1314static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1315{
6b1a3aef 1316 struct sky2_hw *hw = sky2->hw;
14d0263f 1317 struct rx_ring_info *re;
6b1a3aef 1318 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1319 unsigned i, size, thresh;
cd28ab6a 1320
6b1a3aef 1321 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1322 sky2_qset(hw, rxq);
977bdf06 1323
c3905bc4
SH		 1324 /* On PCI express lowering the watermark gives better performance */
1325 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1326 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1327
1328 /* These chips have no ram buffer?
1329 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1330 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1331 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1332 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1333 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1334
6b1a3aef
SH		 1335 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1336
ea76e635
SH		 1337 if (!(hw->flags & SKY2_HW_NEW_LE))
1338 rx_set_checksum(sky2);
14d0263f
SH		 1339
1340 /* Space needed for frame data + headers rounded up */
f957da2a 1341 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1342
1343 /* Stopping point for hardware truncation */
1344 thresh = (size - 8) / sizeof(u32);
1345
5f06eba4 1346 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1347 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1348
5f06eba4
SH		 1349 /* Compute residue after pages */
1350 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1351
5f06eba4
SH		 1352 /* Optimize to handle small packets and headers */
1353 if (size < copybreak)
1354 size = copybreak;
1355 if (size < ETH_HLEN)
1356 size = ETH_HLEN;
14d0263f 1357
14d0263f
SH		 1358 sky2->rx_data_size = size;
1359
1360 /* Fill Rx ring */
793b883e 1361 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1362 re = sky2->rx_ring + i;
cd28ab6a 1363
14d0263f 1364 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1365 if (!re->skb)
1366 goto nomem;
1367
454e6cb6
SH		 1368 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1369 dev_kfree_skb(re->skb);
1370 re->skb = NULL;
1371 goto nomem;
1372 }
1373
14d0263f 1374 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1375 }
1376
a1433ac4
SH		 1377 /*
1378 * The receiver hangs if it receives frames larger than the
1379 * packet buffer. As a workaround, truncate oversize frames, but
1380 * the register is limited to 9 bits, so if you do frames > 2052
1381 * you better get the MTU right!
1382 */
a1433ac4
SH		 1383 if (thresh > 0x1ff)
1384 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1385 else {
1386 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1387 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1388 }
1389
6b1a3aef 1390 /* Tell chip about available buffers */
55c9dd35 1391 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1392 return 0;
1393nomem:
1394 sky2_rx_clean(sky2);
1395 return -ENOMEM;
1396}
1397
1398/* Bring up network interface. */
1399static int sky2_up(struct net_device *dev)
1400{
1401 struct sky2_port *sky2 = netdev_priv(dev);
1402 struct sky2_hw *hw = sky2->hw;
1403 unsigned port = sky2->port;
e0c28116 1404 u32 imask, ramsize;
ee7abb04 1405 int cap, err = -ENOMEM;
843a46f4 1406 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1407
ee7abb04
SH		 1408 /*
1409 * On dual port PCI-X card, there is an problem where status
1410 * can be received out of order due to split transactions
843a46f4 1411 */
ee7abb04
SH		 1412 if (otherdev && netif_running(otherdev) &&
1413 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1414 u16 cmd;
1415
b32f40c4 1416 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1417 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1418 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1419
ee7abb04 1420 }
843a46f4 1421
55d7b4e6
SH		 1422 netif_carrier_off(dev);
1423
cd28ab6a
SH		 1424 /* must be power of 2 */
1425 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1426 TX_RING_SIZE *
1427 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1428 &sky2->tx_le_map);
1429 if (!sky2->tx_le)
1430 goto err_out;
1431
6cdbbdf3 1432 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1433 GFP_KERNEL);
1434 if (!sky2->tx_ring)
1435 goto err_out;
88f5f0ca
SH		 1436
1437 tx_init(sky2);
cd28ab6a
SH		 1438
1439 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1440 &sky2->rx_le_map);
1441 if (!sky2->rx_le)
1442 goto err_out;
1443 memset(sky2->rx_le, 0, RX_LE_BYTES);
1444
291ea614 1445 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1446 GFP_KERNEL);
1447 if (!sky2->rx_ring)
1448 goto err_out;
1449
1450 sky2_mac_init(hw, port);
1451
e0c28116
SH		 1452 /* Register is number of 4K blocks on internal RAM buffer. */
1453 ramsize = sky2_read8(hw, B2_E_0) * 4;
1454 if (ramsize > 0) {
67712901 1455 u32 rxspace;
cd28ab6a 1456
39dbd958 1457 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1458 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1459 if (ramsize < 16)
1460 rxspace = ramsize / 2;
1461 else
1462 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1463
67712901
SH		 1464 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1465 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1466
1467 /* Make sure SyncQ is disabled */
1468 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1469 RB_RST_SET);
1470 }
793b883e 1471
af4ed7e6 1472 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1473
69161611
SH		 1474 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1475 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1476 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1477
977bdf06 1478 /* Set almost empty threshold */
c2716fb4
SH		 1479 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1480 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1481 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1482
6b1a3aef
SH		 1483 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1484 TX_RING_SIZE - 1);
cd28ab6a 1485
d494eacd
SH		 1486#ifdef SKY2_VLAN_TAG_USED
1487 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1488#endif
1489
6b1a3aef 1490 err = sky2_rx_start(sky2);
6de16237 1491 if (err)
cd28ab6a
SH		 1492 goto err_out;
1493
cd28ab6a 1494 /* Enable interrupts from phy/mac for port */
e07b1aa8 1495 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1496 imask |= portirq_msk[port];
e07b1aa8 1497 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1498 sky2_read32(hw, B0_IMSK);
e07b1aa8 1499
a7bffe72 1500 sky2_set_multicast(dev);
a11da890
AD		 1501
1502 if (netif_msg_ifup(sky2))
1503 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
cd28ab6a
SH		 1504 return 0;
1505
1506err_out:
1b537565 1507 if (sky2->rx_le) {
cd28ab6a
SH		 1508 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1509 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1510 sky2->rx_le = NULL;
1511 }
1512 if (sky2->tx_le) {
cd28ab6a
SH		 1513 pci_free_consistent(hw->pdev,
1514 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1515 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1516 sky2->tx_le = NULL;
1517 }
1518 kfree(sky2->tx_ring);
1519 kfree(sky2->rx_ring);
cd28ab6a 1520
1b537565
SH		 1521 sky2->tx_ring = NULL;
1522 sky2->rx_ring = NULL;
cd28ab6a
SH		 1523 return err;
1524}
1525
793b883e
SH		 1526/* Modular subtraction in ring */
1527static inline int tx_dist(unsigned tail, unsigned head)
1528{
cb5d9547 1529 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1530}
cd28ab6a 1531
793b883e
SH		 1532/* Number of list elements available for next tx */
1533static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1534{
793b883e 1535 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1536}
1537
793b883e 1538/* Estimate of number of transmit list elements required */
28bd181a 1539static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1540{
793b883e
SH		 1541 unsigned count;
1542
1543 count = sizeof(dma_addr_t) / sizeof(u32);
1544 count += skb_shinfo(skb)->nr_frags * count;
1545
89114afd 1546 if (skb_is_gso(skb))
793b883e
SH		 1547 ++count;
1548
84fa7933 1549 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1550 ++count;
1551
1552 return count;
cd28ab6a
SH		 1553}
1554
793b883e
SH		 1555/*
1556 * Put one packet in ring for transmit.
1557 * A single packet can generate multiple list elements, and
1558 * the number of ring elements will probably be less than the number
1559 * of list elements used.
1560 */
cd28ab6a
SH		 1561static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1562{
1563 struct sky2_port *sky2 = netdev_priv(dev);
1564 struct sky2_hw *hw = sky2->hw;
d1f13708 1565 struct sky2_tx_le *le = NULL;
6cdbbdf3 1566 struct tx_ring_info *re;
454e6cb6 1567 unsigned i, len, first_slot;
cd28ab6a 1568 dma_addr_t mapping;
cd28ab6a
SH		 1569 u16 mss;
1570 u8 ctrl;
1571
2bb8c262
SH		 1572 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1573 return NETDEV_TX_BUSY;
cd28ab6a 1574
cd28ab6a
SH		 1575 len = skb_headlen(skb);
1576 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1577
454e6cb6
SH		 1578 if (pci_dma_mapping_error(hw->pdev, mapping))
1579 goto mapping_error;
1580
1581 first_slot = sky2->tx_prod;
1582 if (unlikely(netif_msg_tx_queued(sky2)))
1583 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1584 dev->name, first_slot, skb->len);
1585
86c6887e
SH		 1586 /* Send high bits if needed */
1587 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1588 le = get_tx_le(sky2);
86c6887e 1589 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1590 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1591 }
cd28ab6a
SH		 1592
1593 /* Check for TCP Segmentation Offload */
7967168c 1594 mss = skb_shinfo(skb)->gso_size;
793b883e 1595 if (mss != 0) {
ea76e635
SH		 1596
1597 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1598 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1599
1600 if (mss != sky2->tx_last_mss) {
1601 le = get_tx_le(sky2);
1602 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1603
1604 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1605 le->opcode = OP_MSS | HW_OWNER;
1606 else
1607 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1608 sky2->tx_last_mss = mss;
1609 }
cd28ab6a
SH		 1610 }
1611
cd28ab6a 1612 ctrl = 0;
d1f13708
SH		 1613#ifdef SKY2_VLAN_TAG_USED
1614 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1615 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1616 if (!le) {
1617 le = get_tx_le(sky2);
f65b138c 1618 le->addr = 0;
d1f13708 1619 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1620 } else
1621 le->opcode |= OP_VLAN;
1622 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1623 ctrl |= INS_VLAN;
1624 }
1625#endif
1626
1627 /* Handle TCP checksum offload */
84fa7933 1628 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1629 /* On Yukon EX (some versions) encoding change. */
ea76e635 1630 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1631 ctrl |= CALSUM; /* auto checksum */
1632 else {
1633 const unsigned offset = skb_transport_offset(skb);
1634 u32 tcpsum;
1635
1636 tcpsum = offset << 16; /* sum start */
1637 tcpsum |= offset + skb->csum_offset; /* sum write */
1638
1639 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1640 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1641 ctrl |= UDPTCP;
1642
1643 if (tcpsum != sky2->tx_tcpsum) {
1644 sky2->tx_tcpsum = tcpsum;
1645
1646 le = get_tx_le(sky2);
1647 le->addr = cpu_to_le32(tcpsum);
1648 le->length = 0; /* initial checksum value */
1649 le->ctrl = 1; /* one packet */
1650 le->opcode = OP_TCPLISW | HW_OWNER;
1651 }
1d179332 1652 }
cd28ab6a
SH		 1653 }
1654
1655 le = get_tx_le(sky2);
f65b138c 1656 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1657 le->length = cpu_to_le16(len);
1658 le->ctrl = ctrl;
793b883e 1659 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1660
291ea614 1661 re = tx_le_re(sky2, le);
cd28ab6a 1662 re->skb = skb;
6cdbbdf3 1663 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1664 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1665
1666 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1667 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1668
1669 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1670 frag->size, PCI_DMA_TODEVICE);
86c6887e 1671
454e6cb6
SH		 1672 if (pci_dma_mapping_error(hw->pdev, mapping))
1673 goto mapping_unwind;
1674
86c6887e 1675 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1676 le = get_tx_le(sky2);
86c6887e 1677 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1678 le->ctrl = 0;
1679 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1680 }
1681
1682 le = get_tx_le(sky2);
f65b138c 1683 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1684 le->length = cpu_to_le16(frag->size);
1685 le->ctrl = ctrl;
793b883e 1686 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1687
291ea614
SH		 1688 re = tx_le_re(sky2, le);
1689 re->skb = skb;
1690 pci_unmap_addr_set(re, mapaddr, mapping);
1691 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1692 }
6cdbbdf3 1693
cd28ab6a
SH		 1694 le->ctrl |= EOP;
1695
97bda706
SH		 1696 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1697 netif_stop_queue(dev);
b19666d9 1698
290d4de5 1699 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1700
cd28ab6a 1701 return NETDEV_TX_OK;
454e6cb6
SH		 1702
1703mapping_unwind:
1704 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1705 le = sky2->tx_le + i;
1706 re = sky2->tx_ring + i;
1707
1708 switch(le->opcode & ~HW_OWNER) {
1709 case OP_LARGESEND:
1710 case OP_PACKET:
1711 pci_unmap_single(hw->pdev,
1712 pci_unmap_addr(re, mapaddr),
1713 pci_unmap_len(re, maplen),
1714 PCI_DMA_TODEVICE);
1715 break;
1716 case OP_BUFFER:
1717 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1718 pci_unmap_len(re, maplen),
1719 PCI_DMA_TODEVICE);
1720 break;
1721 }
1722 }
1723
1724 sky2->tx_prod = first_slot;
1725mapping_error:
1726 if (net_ratelimit())
1727 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1728 dev_kfree_skb(skb);
1729 return NETDEV_TX_OK;
cd28ab6a
SH		 1730}
1731
cd28ab6a 1732/*
793b883e
SH		 1733 * Free ring elements from starting at tx_cons until "done"
1734 *
1735 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1736 * buffers so make sure not to free skb to early.
cd28ab6a 1737 */
d11c13e7 1738static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1739{
d11c13e7 1740 struct net_device *dev = sky2->netdev;
af2a58ac 1741 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1742 unsigned idx;
cd28ab6a 1743
0e3ff6aa 1744 BUG_ON(done >= TX_RING_SIZE);
2224795d 1745
291ea614
SH		 1746 for (idx = sky2->tx_cons; idx != done;
1747 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1748 struct sky2_tx_le *le = sky2->tx_le + idx;
1749 struct tx_ring_info *re = sky2->tx_ring + idx;
1750
1751 switch(le->opcode & ~HW_OWNER) {
1752 case OP_LARGESEND:
1753 case OP_PACKET:
1754 pci_unmap_single(pdev,
1755 pci_unmap_addr(re, mapaddr),
1756 pci_unmap_len(re, maplen),
1757 PCI_DMA_TODEVICE);
af2a58ac 1758 break;
291ea614
SH		 1759 case OP_BUFFER:
1760 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1761 pci_unmap_len(re, maplen),
734d1868 1762 PCI_DMA_TODEVICE);
291ea614
SH		 1763 break;
1764 }
1765
1766 if (le->ctrl & EOP) {
1767 if (unlikely(netif_msg_tx_done(sky2)))
1768 printk(KERN_DEBUG "%s: tx done %u\n",
1769 dev->name, idx);
3cf26753 1770
7138a0f5
SH		 1771 dev->stats.tx_packets++;
1772 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1773
794b2bd2 1774 dev_kfree_skb_any(re->skb);
3cf26753 1775 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1776 }
793b883e 1777 }
793b883e 1778
291ea614 1779 sky2->tx_cons = idx;
50432cb5
SH		 1780 smp_mb();
1781
22e11703 1782 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1783 netif_wake_queue(dev);
cd28ab6a
SH		 1784}
1785
1786/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1787static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1788{
2bb8c262
SH		 1789 struct sky2_port *sky2 = netdev_priv(dev);
1790
1791 netif_tx_lock_bh(dev);
d11c13e7 1792 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1793 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1794}
1795
1796/* Network shutdown */
1797static int sky2_down(struct net_device *dev)
1798{
1799 struct sky2_port *sky2 = netdev_priv(dev);
1800 struct sky2_hw *hw = sky2->hw;
1801 unsigned port = sky2->port;
1802 u16 ctrl;
e07b1aa8 1803 u32 imask;
cd28ab6a 1804
1b537565
SH		 1805 /* Never really got started! */
1806 if (!sky2->tx_le)
1807 return 0;
1808
cd28ab6a
SH		 1809 if (netif_msg_ifdown(sky2))
1810 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1811
ebc646f6
SH		 1812 /* Disable port IRQ */
1813 imask = sky2_read32(hw, B0_IMSK);
1814 imask &= ~portirq_msk[port];
1815 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1816 sky2_read32(hw, B0_IMSK);
ebc646f6 1817
d104acaf
SH		 1818 /* Force flow control off */
1819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1820
cd28ab6a
SH		 1821 /* Stop transmitter */
1822 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1823 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1824
1825 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1826 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1827
1828 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1829 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1830 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1831
1832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1833
1834 /* Workaround shared GMAC reset */
793b883e
SH		 1835 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1836 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1837 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1838
1839 /* Disable Force Sync bit and Enable Alloc bit */
1840 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1841 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1842
1843 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1844 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1845 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1846
1847 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1848 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1849 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1850
1851 /* Reset the Tx prefetch units */
1852 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1853 PREF_UNIT_RST_SET);
1854
1855 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1856
6b1a3aef 1857 sky2_rx_stop(sky2);
cd28ab6a
SH		 1858
1859 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1860 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1861
6c83504f
SH		 1862 /* Force any delayed status interrrupt and NAPI */
1863 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1864 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1865 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1866 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1867
1868 synchronize_irq(hw->pdev->irq);
1869 napi_synchronize(&hw->napi);
1870
b96936da 1871 sky2_phy_power_down(hw, port);
d3bcfbeb 1872
d571b694 1873 /* turn off LED's */
cd28ab6a
SH		 1874 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1875
2bb8c262 1876 sky2_tx_clean(dev);
cd28ab6a
SH		 1877 sky2_rx_clean(sky2);
1878
1879 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1880 sky2->rx_le, sky2->rx_le_map);
1881 kfree(sky2->rx_ring);
1882
1883 pci_free_consistent(hw->pdev,
1884 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1885 sky2->tx_le, sky2->tx_le_map);
1886 kfree(sky2->tx_ring);
1887
1b537565
SH		 1888 sky2->tx_le = NULL;
1889 sky2->rx_le = NULL;
1890
1891 sky2->rx_ring = NULL;
1892 sky2->tx_ring = NULL;
1893
cd28ab6a
SH		 1894 return 0;
1895}
1896
1897static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1898{
ea76e635 1899 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1900 return SPEED_1000;
1901
05745c4a
SH		 1902 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1903 if (aux & PHY_M_PS_SPEED_100)
1904 return SPEED_100;
1905 else
1906 return SPEED_10;
1907 }
cd28ab6a
SH		 1908
1909 switch (aux & PHY_M_PS_SPEED_MSK) {
1910 case PHY_M_PS_SPEED_1000:
1911 return SPEED_1000;
1912 case PHY_M_PS_SPEED_100:
1913 return SPEED_100;
1914 default:
1915 return SPEED_10;
1916 }
1917}
1918
1919static void sky2_link_up(struct sky2_port *sky2)
1920{
1921 struct sky2_hw *hw = sky2->hw;
1922 unsigned port = sky2->port;
1923 u16 reg;
16ad91e1
SH		 1924 static const char *fc_name[] = {
1925 [FC_NONE] = "none",
1926 [FC_TX] = "tx",
1927 [FC_RX] = "rx",
1928 [FC_BOTH] = "both",
1929 };
cd28ab6a 1930
cd28ab6a 1931 /* enable Rx/Tx */
2eaba1a2 1932 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1933 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1934 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1935
1936 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1937
1938 netif_carrier_on(sky2->netdev);
cd28ab6a 1939
75e80683 1940 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1941
cd28ab6a 1942 /* Turn on link LED */
793b883e 1943 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1944 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1945
1946 if (netif_msg_link(sky2))
1947 printk(KERN_INFO PFX
d571b694 1948 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1949 sky2->netdev->name, sky2->speed,
1950 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1951 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1952}
1953
1954static void sky2_link_down(struct sky2_port *sky2)
1955{
1956 struct sky2_hw *hw = sky2->hw;
1957 unsigned port = sky2->port;
1958 u16 reg;
1959
1960 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1961
1962 reg = gma_read16(hw, port, GM_GP_CTRL);
1963 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1964 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1965
cd28ab6a 1966 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1967
1968 /* Turn on link LED */
1969 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1970
1971 if (netif_msg_link(sky2))
1972 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1973
cd28ab6a
SH		 1974 sky2_phy_init(hw, port);
1975}
1976
16ad91e1
SH		 1977static enum flow_control sky2_flow(int rx, int tx)
1978{
1979 if (rx)
1980 return tx ? FC_BOTH : FC_RX;
1981 else
1982 return tx ? FC_TX : FC_NONE;
1983}
1984
793b883e
SH		 1985static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1986{
1987 struct sky2_hw *hw = sky2->hw;
1988 unsigned port = sky2->port;
da4c1ff4 1989 u16 advert, lpa;
793b883e 1990
da4c1ff4 1991 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1992 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1993 if (lpa & PHY_M_AN_RF) {
1994 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1995 return -1;
1996 }
1997
793b883e
SH		 1998 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1999 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2000 sky2->netdev->name);
2001 return -1;
2002 }
2003
793b883e 2004 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2005 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2006
da4c1ff4
SH		 2007 /* Since the pause result bits seem to in different positions on
2008 * different chips. look at registers.
2009 */
ea76e635 2010 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2011 /* Shift for bits in fiber PHY */
2012 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2013 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2014
2015 if (advert & ADVERTISE_1000XPAUSE)
2016 advert |= ADVERTISE_PAUSE_CAP;
2017 if (advert & ADVERTISE_1000XPSE_ASYM)
2018 advert |= ADVERTISE_PAUSE_ASYM;
2019 if (lpa & LPA_1000XPAUSE)
2020 lpa |= LPA_PAUSE_CAP;
2021 if (lpa & LPA_1000XPAUSE_ASYM)
2022 lpa |= LPA_PAUSE_ASYM;
2023 }
793b883e 2024
da4c1ff4
SH		 2025 sky2->flow_status = FC_NONE;
2026 if (advert & ADVERTISE_PAUSE_CAP) {
2027 if (lpa & LPA_PAUSE_CAP)
2028 sky2->flow_status = FC_BOTH;
2029 else if (advert & ADVERTISE_PAUSE_ASYM)
2030 sky2->flow_status = FC_RX;
2031 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2032 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2033 sky2->flow_status = FC_TX;
2034 }
793b883e 2035
16ad91e1 2036 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2037 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2038 sky2->flow_status = FC_NONE;
2eaba1a2 2039
da4c1ff4 2040 if (sky2->flow_status & FC_TX)
793b883e
SH		 2041 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2042 else
2043 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2044
2045 return 0;
2046}
cd28ab6a 2047
e07b1aa8
SH		 2048/* Interrupt from PHY */
2049static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2050{
e07b1aa8
SH		 2051 struct net_device *dev = hw->dev[port];
2052 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2053 u16 istatus, phystat;
2054
ebc646f6
SH		 2055 if (!netif_running(dev))
2056 return;
2057
e07b1aa8
SH		 2058 spin_lock(&sky2->phy_lock);
2059 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2060 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2061
cd28ab6a
SH		 2062 if (netif_msg_intr(sky2))
2063 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2064 sky2->netdev->name, istatus, phystat);
2065
2eaba1a2 2066 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2067 if (sky2_autoneg_done(sky2, phystat) == 0)
2068 sky2_link_up(sky2);
2069 goto out;
2070 }
cd28ab6a 2071
793b883e
SH		 2072 if (istatus & PHY_M_IS_LSP_CHANGE)
2073 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2074
793b883e
SH		 2075 if (istatus & PHY_M_IS_DUP_CHANGE)
2076 sky2->duplex =
2077 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2078
793b883e
SH		 2079 if (istatus & PHY_M_IS_LST_CHANGE) {
2080 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2081 sky2_link_up(sky2);
793b883e
SH		 2082 else
2083 sky2_link_down(sky2);
cd28ab6a 2084 }
793b883e 2085out:
e07b1aa8 2086 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2087}
2088
62335ab0 2089/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2090 * and tx queue is full (stopped).
2091 */
cd28ab6a
SH		 2092static void sky2_tx_timeout(struct net_device *dev)
2093{
2094 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2095 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2096
2097 if (netif_msg_timer(sky2))
2098 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2099
8f24664d 2100 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2101 dev->name, sky2->tx_cons, sky2->tx_prod,
2102 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2103 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2104
81906791
SH		 2105 /* can't restart safely under softirq */
2106 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2107}
2108
2109static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2110{
6b1a3aef
SH		 2111 struct sky2_port *sky2 = netdev_priv(dev);
2112 struct sky2_hw *hw = sky2->hw;
b628ed98 2113 unsigned port = sky2->port;
6b1a3aef
SH		 2114 int err;
2115 u16 ctl, mode;
e07b1aa8 2116 u32 imask;
cd28ab6a
SH		 2117
2118 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2119 return -EINVAL;
2120
05745c4a
SH		 2121 if (new_mtu > ETH_DATA_LEN &&
2122 (hw->chip_id == CHIP_ID_YUKON_FE ||
2123 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2124 return -EINVAL;
2125
6b1a3aef
SH		 2126 if (!netif_running(dev)) {
2127 dev->mtu = new_mtu;
2128 return 0;
2129 }
2130
e07b1aa8 2131 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2132 sky2_write32(hw, B0_IMSK, 0);
2133
018d1c66
SH		 2134 dev->trans_start = jiffies; /* prevent tx timeout */
2135 netif_stop_queue(dev);
bea3348e 2136 napi_disable(&hw->napi);
018d1c66 2137
e07b1aa8
SH		 2138 synchronize_irq(hw->pdev->irq);
2139
39dbd958 2140 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2141 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2142
2143 ctl = gma_read16(hw, port, GM_GP_CTRL);
2144 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2145 sky2_rx_stop(sky2);
2146 sky2_rx_clean(sky2);
cd28ab6a
SH		 2147
2148 dev->mtu = new_mtu;
14d0263f 2149
6b1a3aef
SH		 2150 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2151 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2152
2153 if (dev->mtu > ETH_DATA_LEN)
2154 mode |= GM_SMOD_JUMBO_ENA;
2155
b628ed98 2156 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2157
b628ed98 2158 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2159
6b1a3aef 2160 err = sky2_rx_start(sky2);
e07b1aa8 2161 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2162
d1d08d12 2163 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2164 napi_enable(&hw->napi);
2165
1b537565
SH		 2166 if (err)
2167 dev_close(dev);
2168 else {
b628ed98 2169 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2170
1b537565
SH		 2171 netif_wake_queue(dev);
2172 }
2173
cd28ab6a
SH		 2174 return err;
2175}
2176
14d0263f
SH		 2177/* For small just reuse existing skb for next receive */
2178static struct sk_buff *receive_copy(struct sky2_port *sky2,
2179 const struct rx_ring_info *re,
2180 unsigned length)
2181{
2182 struct sk_buff *skb;
2183
2184 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2185 if (likely(skb)) {
2186 skb_reserve(skb, 2);
2187 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2188 length, PCI_DMA_FROMDEVICE);
d626f62b 2189 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2190 skb->ip_summed = re->skb->ip_summed;
2191 skb->csum = re->skb->csum;
2192 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2193 length, PCI_DMA_FROMDEVICE);
2194 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2195 skb_put(skb, length);
14d0263f
SH		 2196 }
2197 return skb;
2198}
2199
2200/* Adjust length of skb with fragments to match received data */
2201static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2202 unsigned int length)
2203{
2204 int i, num_frags;
2205 unsigned int size;
2206
2207 /* put header into skb */
2208 size = min(length, hdr_space);
2209 skb->tail += size;
2210 skb->len += size;
2211 length -= size;
2212
2213 num_frags = skb_shinfo(skb)->nr_frags;
2214 for (i = 0; i < num_frags; i++) {
2215 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2216
2217 if (length == 0) {
2218 /* don't need this page */
2219 __free_page(frag->page);
2220 --skb_shinfo(skb)->nr_frags;
2221 } else {
2222 size = min(length, (unsigned) PAGE_SIZE);
2223
2224 frag->size = size;
2225 skb->data_len += size;
2226 skb->truesize += size;
2227 skb->len += size;
2228 length -= size;
2229 }
2230 }
2231}
2232
2233/* Normal packet - take skb from ring element and put in a new one */
2234static struct sk_buff *receive_new(struct sky2_port *sky2,
2235 struct rx_ring_info *re,
2236 unsigned int length)
2237{
2238 struct sk_buff *skb, *nskb;
2239 unsigned hdr_space = sky2->rx_data_size;
2240
14d0263f
SH		 2241 /* Don't be tricky about reusing pages (yet) */
2242 nskb = sky2_rx_alloc(sky2);
2243 if (unlikely(!nskb))
2244 return NULL;
2245
2246 skb = re->skb;
2247 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2248
2249 prefetch(skb->data);
2250 re->skb = nskb;
454e6cb6
SH		 2251 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2252 dev_kfree_skb(nskb);
2253 re->skb = skb;
2254 return NULL;
2255 }
14d0263f
SH		 2256
2257 if (skb_shinfo(skb)->nr_frags)
2258 skb_put_frags(skb, hdr_space, length);
2259 else
489b10c1 2260 skb_put(skb, length);
14d0263f
SH		 2261 return skb;
2262}
2263
cd28ab6a
SH		 2264/*
2265 * Receive one packet.
d571b694 2266 * For larger packets, get new buffer.
cd28ab6a 2267 */
497d7c86 2268static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2269 u16 length, u32 status)
2270{
497d7c86 2271 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2272 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2273 struct sk_buff *skb = NULL;
d6532232
SH		 2274 u16 count = (status & GMR_FS_LEN) >> 16;
2275
2276#ifdef SKY2_VLAN_TAG_USED
2277 /* Account for vlan tag */
2278 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2279 count -= VLAN_HLEN;
2280#endif
cd28ab6a
SH		 2281
2282 if (unlikely(netif_msg_rx_status(sky2)))
2283 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2284 dev->name, sky2->rx_next, status, length);
cd28ab6a 2285
793b883e 2286 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2287 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2288
3b12e014
SH		 2289 /* This chip has hardware problems that generates bogus status.
2290 * So do only marginal checking and expect higher level protocols
2291 * to handle crap frames.
2292 */
2293 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2294 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2295 length != count)
2296 goto okay;
2297
42eeea01 2298 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2299 goto error;
2300
42eeea01
SH		 2301 if (!(status & GMR_FS_RX_OK))
2302 goto resubmit;
2303
d6532232
SH		 2304 /* if length reported by DMA does not match PHY, packet was truncated */
2305 if (length != count)
3b12e014 2306 goto len_error;
71749531 2307
3b12e014 2308okay:
14d0263f
SH		 2309 if (length < copybreak)
2310 skb = receive_copy(sky2, re, length);
2311 else
2312 skb = receive_new(sky2, re, length);
793b883e 2313resubmit:
14d0263f 2314 sky2_rx_submit(sky2, re);
79e57d32 2315
cd28ab6a
SH		 2316 return skb;
2317
3b12e014 2318len_error:
71749531
SH		 2319 /* Truncation of overlength packets
2320 causes PHY length to not match MAC length */
7138a0f5 2321 ++dev->stats.rx_length_errors;
d6532232 2322 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2323 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2324 dev->name, status, length);
d6532232 2325 goto resubmit;
71749531 2326
cd28ab6a 2327error:
7138a0f5 2328 ++dev->stats.rx_errors;
b6d77734 2329 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2330 dev->stats.rx_over_errors++;
b6d77734
SH		 2331 goto resubmit;
2332 }
6e15b712 2333
3be92a70 2334 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2335 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2336 dev->name, status, length);
793b883e
SH		 2337
2338 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2339 dev->stats.rx_length_errors++;
cd28ab6a 2340 if (status & GMR_FS_FRAGMENT)
7138a0f5 2341 dev->stats.rx_frame_errors++;
cd28ab6a 2342 if (status & GMR_FS_CRC_ERR)
7138a0f5 2343 dev->stats.rx_crc_errors++;
79e57d32 2344
793b883e 2345 goto resubmit;
cd28ab6a
SH		 2346}
2347
e07b1aa8
SH		 2348/* Transmit complete */
2349static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2350{
e07b1aa8 2351 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2352
e07b1aa8 2353 if (netif_running(dev)) {
2bb8c262 2354 netif_tx_lock(dev);
e07b1aa8 2355 sky2_tx_complete(sky2, last);
2bb8c262 2356 netif_tx_unlock(dev);
2224795d 2357 }
cd28ab6a
SH		 2358}
2359
bf15fe99
SH		 2360static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2361 unsigned packets, unsigned bytes)
2362{
2363 if (packets) {
2364 struct net_device *dev = hw->dev[port];
2365
2366 dev->stats.rx_packets += packets;
2367 dev->stats.rx_bytes += bytes;
2368 dev->last_rx = jiffies;
2369 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2370 }
2371}
2372
e07b1aa8 2373/* Process status response ring */
26691830 2374static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2375{
e07b1aa8 2376 int work_done = 0;
bf15fe99
SH		 2377 unsigned int total_bytes[2] = { 0 };
2378 unsigned int total_packets[2] = { 0 };
a8fd6266 2379
af2a58ac 2380 rmb();
26691830 2381 do {
55c9dd35 2382 struct sky2_port *sky2;
13210ce5 2383 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2384 unsigned port;
13210ce5 2385 struct net_device *dev;
cd28ab6a 2386 struct sk_buff *skb;
cd28ab6a
SH		 2387 u32 status;
2388 u16 length;
ab5adecb
SH		 2389 u8 opcode = le->opcode;
2390
2391 if (!(opcode & HW_OWNER))
2392 break;
cd28ab6a 2393
cb5d9547 2394 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2395
ab5adecb 2396 port = le->css & CSS_LINK_BIT;
69161611 2397 dev = hw->dev[port];
13210ce5 2398 sky2 = netdev_priv(dev);
f65b138c
SH		 2399 length = le16_to_cpu(le->length);
2400 status = le32_to_cpu(le->status);
cd28ab6a 2401
ab5adecb
SH		 2402 le->opcode = 0;
2403 switch (opcode & ~HW_OWNER) {
cd28ab6a 2404 case OP_RXSTAT:
bf15fe99
SH		 2405 total_packets[port]++;
2406 total_bytes[port] += length;
497d7c86 2407 skb = sky2_receive(dev, length, status);
3225b919 2408 if (unlikely(!skb)) {
7138a0f5 2409 dev->stats.rx_dropped++;
55c9dd35 2410 break;
3225b919 2411 }
13210ce5 2412
69161611 2413 /* This chip reports checksum status differently */
05745c4a 2414 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2415 if (sky2->rx_csum &&
2416 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2417 (le->css & CSS_TCPUDPCSOK))
2418 skb->ip_summed = CHECKSUM_UNNECESSARY;
2419 else
2420 skb->ip_summed = CHECKSUM_NONE;
2421 }
2422
13210ce5 2423 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2424
d1f13708
SH		 2425#ifdef SKY2_VLAN_TAG_USED
2426 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2427 vlan_hwaccel_receive_skb(skb,
2428 sky2->vlgrp,
2429 be16_to_cpu(sky2->rx_tag));
2430 } else
2431#endif
cd28ab6a 2432 netif_receive_skb(skb);
13210ce5 2433
22e11703 2434 /* Stop after net poll weight */
13210ce5
SH		 2435 if (++work_done >= to_do)
2436 goto exit_loop;
cd28ab6a
SH		 2437 break;
2438
d1f13708
SH		 2439#ifdef SKY2_VLAN_TAG_USED
2440 case OP_RXVLAN:
2441 sky2->rx_tag = length;
2442 break;
2443
2444 case OP_RXCHKSVLAN:
2445 sky2->rx_tag = length;
2446 /* fall through */
2447#endif
cd28ab6a 2448 case OP_RXCHKS:
87418307
SH		 2449 if (!sky2->rx_csum)
2450 break;
2451
05745c4a
SH		 2452 /* If this happens then driver assuming wrong format */
2453 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2454 if (net_ratelimit())
2455 printk(KERN_NOTICE "%s: unexpected"
2456 " checksum status\n",
2457 dev->name);
69161611 2458 break;
05745c4a 2459 }
69161611 2460
87418307
SH		 2461 /* Both checksum counters are programmed to start at
2462 * the same offset, so unless there is a problem they
2463 * should match. This failure is an early indication that
2464 * hardware receive checksumming won't work.
2465 */
2466 if (likely(status >> 16 == (status & 0xffff))) {
2467 skb = sky2->rx_ring[sky2->rx_next].skb;
2468 skb->ip_summed = CHECKSUM_COMPLETE;
2469 skb->csum = status & 0xffff;
2470 } else {
2471 printk(KERN_NOTICE PFX "%s: hardware receive "
2472 "checksum problem (status = %#x)\n",
2473 dev->name, status);
2474 sky2->rx_csum = 0;
2475 sky2_write32(sky2->hw,
69161611 2476 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2477 BMU_DIS_RX_CHKSUM);
2478 }
cd28ab6a
SH		 2479 break;
2480
2481 case OP_TXINDEXLE:
13b97b74 2482 /* TX index reports status for both ports */
f55925d7
SH		 2483 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2484 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2485 if (hw->dev[1])
2486 sky2_tx_done(hw->dev[1],
2487 ((status >> 24) & 0xff)
2488 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2489 break;
2490
cd28ab6a
SH		 2491 default:
2492 if (net_ratelimit())
793b883e 2493 printk(KERN_WARNING PFX
ab5adecb 2494 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2495 }
26691830 2496 } while (hw->st_idx != idx);
cd28ab6a 2497
fe2a24df
SH		 2498 /* Fully processed status ring so clear irq */
2499 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2500
13210ce5 2501exit_loop:
bf15fe99
SH		 2502 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2503 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2504
e07b1aa8 2505 return work_done;
cd28ab6a
SH		 2506}
2507
2508static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2509{
2510 struct net_device *dev = hw->dev[port];
2511
3be92a70
SH		 2512 if (net_ratelimit())
2513 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2514 dev->name, status);
cd28ab6a
SH		 2515
2516 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2517 if (net_ratelimit())
2518 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2519 dev->name);
cd28ab6a
SH		 2520 /* Clear IRQ */
2521 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2522 }
2523
2524 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2525 if (net_ratelimit())
2526 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2527 dev->name);
cd28ab6a
SH		 2528
2529 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2530 }
2531
2532 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2533 if (net_ratelimit())
2534 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2535 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2536 }
2537
2538 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2539 if (net_ratelimit())
2540 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2541 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2542 }
2543
2544 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2545 if (net_ratelimit())
2546 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2547 dev->name);
cd28ab6a
SH		 2548 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2549 }
2550}
2551
2552static void sky2_hw_intr(struct sky2_hw *hw)
2553{
555382cb 2554 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2555 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2556 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2557
2558 status &= hwmsk;
cd28ab6a 2559
793b883e 2560 if (status & Y2_IS_TIST_OV)
cd28ab6a 2561 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2562
2563 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2564 u16 pci_err;
2565
82637e80 2566 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2567 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2568 if (net_ratelimit())
555382cb 2569 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2570 pci_err);
cd28ab6a 2571
b32f40c4 2572 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2573 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2574 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2575 }
2576
2577 if (status & Y2_IS_PCI_EXP) {
d571b694 2578 /* PCI-Express uncorrectable Error occurred */
555382cb 2579 u32 err;
cd28ab6a 2580
82637e80 2581 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2582 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2583 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2584 0xfffffffful);
3be92a70 2585 if (net_ratelimit())
555382cb 2586 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2587
7782c8c4 2588 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2589 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2590 }
2591
2592 if (status & Y2_HWE_L1_MASK)
2593 sky2_hw_error(hw, 0, status);
2594 status >>= 8;
2595 if (status & Y2_HWE_L1_MASK)
2596 sky2_hw_error(hw, 1, status);
2597}
2598
2599static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2600{
2601 struct net_device *dev = hw->dev[port];
2602 struct sky2_port *sky2 = netdev_priv(dev);
2603 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2604
2605 if (netif_msg_intr(sky2))
2606 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2607 dev->name, status);
2608
a3caeada
SH		 2609 if (status & GM_IS_RX_CO_OV)
2610 gma_read16(hw, port, GM_RX_IRQ_SRC);
2611
2612 if (status & GM_IS_TX_CO_OV)
2613 gma_read16(hw, port, GM_TX_IRQ_SRC);
2614
cd28ab6a 2615 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2616 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2617 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2618 }
2619
2620 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2621 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2622 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2623 }
cd28ab6a
SH		 2624}
2625
40b01727
SH		 2626/* This should never happen it is a bug. */
2627static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2628 u16 q, unsigned ring_size)
d257924e
SH		 2629{
2630 struct net_device *dev = hw->dev[port];
2631 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2632 unsigned idx;
2633 const u64 *le = (q == Q_R1 || q == Q_R2)
2634 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2635
40b01727
SH		 2636 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2637 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2638 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2639 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2640
40b01727 2641 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2642}
cd28ab6a 2643
75e80683
SH		 2644static int sky2_rx_hung(struct net_device *dev)
2645{
2646 struct sky2_port *sky2 = netdev_priv(dev);
2647 struct sky2_hw *hw = sky2->hw;
2648 unsigned port = sky2->port;
2649 unsigned rxq = rxqaddr[port];
2650 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2651 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2652 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2653 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2654
2655 /* If idle and MAC or PCI is stuck */
2656 if (sky2->check.last == dev->last_rx &&
2657 ((mac_rp == sky2->check.mac_rp &&
2658 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2659 /* Check if the PCI RX hang */
2660 (fifo_rp == sky2->check.fifo_rp &&
2661 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2662 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2663 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2664 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2665 return 1;
2666 } else {
2667 sky2->check.last = dev->last_rx;
2668 sky2->check.mac_rp = mac_rp;
2669 sky2->check.mac_lev = mac_lev;
2670 sky2->check.fifo_rp = fifo_rp;
2671 sky2->check.fifo_lev = fifo_lev;
2672 return 0;
2673 }
2674}
2675
32c2c300 2676static void sky2_watchdog(unsigned long arg)
d27ed387 2677{
01bd7564 2678 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2679
75e80683 2680 /* Check for lost IRQ once a second */
32c2c300 2681 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2682 napi_schedule(&hw->napi);
75e80683
SH		 2683 } else {
2684 int i, active = 0;
2685
2686 for (i = 0; i < hw->ports; i++) {
bea3348e 2687 struct net_device *dev = hw->dev[i];
75e80683
SH		 2688 if (!netif_running(dev))
2689 continue;
2690 ++active;
2691
2692 /* For chips with Rx FIFO, check if stuck */
39dbd958 2693 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2694 sky2_rx_hung(dev)) {
2695 pr_info(PFX "%s: receiver hang detected\n",
2696 dev->name);
2697 schedule_work(&hw->restart_work);
2698 return;
2699 }
2700 }
2701
2702 if (active == 0)
2703 return;
32c2c300 2704 }
01bd7564 2705
75e80683 2706 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2707}
2708
40b01727
SH		 2709/* Hardware/software error handling */
2710static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2711{
40b01727
SH		 2712 if (net_ratelimit())
2713 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2714
1e5f1283
SH		 2715 if (status & Y2_IS_HW_ERR)
2716 sky2_hw_intr(hw);
d257924e 2717
1e5f1283
SH		 2718 if (status & Y2_IS_IRQ_MAC1)
2719 sky2_mac_intr(hw, 0);
cd28ab6a 2720
1e5f1283
SH		 2721 if (status & Y2_IS_IRQ_MAC2)
2722 sky2_mac_intr(hw, 1);
cd28ab6a 2723
1e5f1283 2724 if (status & Y2_IS_CHK_RX1)
40b01727 2725 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2726
1e5f1283 2727 if (status & Y2_IS_CHK_RX2)
40b01727 2728 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2729
1e5f1283 2730 if (status & Y2_IS_CHK_TXA1)
40b01727 2731 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2732
1e5f1283 2733 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2734 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2735}
2736
bea3348e 2737static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2738{
bea3348e 2739 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2740 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2741 int work_done = 0;
26691830 2742 u16 idx;
40b01727
SH		 2743
2744 if (unlikely(status & Y2_IS_ERROR))
2745 sky2_err_intr(hw, status);
2746
2747 if (status & Y2_IS_IRQ_PHY1)
2748 sky2_phy_intr(hw, 0);
2749
2750 if (status & Y2_IS_IRQ_PHY2)
2751 sky2_phy_intr(hw, 1);
cd28ab6a 2752
26691830
SH		 2753 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2754 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2755
2756 if (work_done >= work_limit)
26691830
SH		 2757 goto done;
2758 }
6f535763 2759
26691830
SH		 2760 napi_complete(napi);
2761 sky2_read32(hw, B0_Y2_SP_LISR);
2762done:
6f535763 2763
bea3348e 2764 return work_done;
e07b1aa8
SH		 2765}
2766
7d12e780 2767static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2768{
2769 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2770 u32 status;
2771
2772 /* Reading this mask interrupts as side effect */
2773 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2774 if (status == 0 || status == ~0)
2775 return IRQ_NONE;
793b883e 2776
e07b1aa8 2777 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2778
2779 napi_schedule(&hw->napi);
793b883e 2780
cd28ab6a
SH		 2781 return IRQ_HANDLED;
2782}
2783
2784#ifdef CONFIG_NET_POLL_CONTROLLER
2785static void sky2_netpoll(struct net_device *dev)
2786{
2787 struct sky2_port *sky2 = netdev_priv(dev);
2788
bea3348e 2789 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2790}
2791#endif
2792
2793/* Chip internal frequency for clock calculations */
05745c4a 2794static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2795{
793b883e 2796 switch (hw->chip_id) {
cd28ab6a 2797 case CHIP_ID_YUKON_EC:
5a5b1ea0 2798 case CHIP_ID_YUKON_EC_U:
93745494 2799 case CHIP_ID_YUKON_EX:
ed4d4161 2800 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2801 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2802 return 125;
2803
cd28ab6a 2804 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2805 return 100;
2806
2807 case CHIP_ID_YUKON_FE_P:
2808 return 50;
2809
2810 case CHIP_ID_YUKON_XL:
2811 return 156;
2812
2813 default:
2814 BUG();
cd28ab6a
SH		 2815 }
2816}
2817
fb17358f 2818static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2819{
fb17358f 2820 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2821}
2822
fb17358f 2823static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2824{
fb17358f 2825 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2826}
2827
fb17358f 2828
e3173832 2829static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2830{
b89165f2 2831 u8 t8;
cd28ab6a 2832
167f53d0 2833 /* Enable all clocks and check for bad PCI access */
b32f40c4 2834 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2835
cd28ab6a 2836 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2837
cd28ab6a 2838 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2839 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2840
2841 switch(hw->chip_id) {
2842 case CHIP_ID_YUKON_XL:
39dbd958 2843 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2844 break;
2845
2846 case CHIP_ID_YUKON_EC_U:
2847 hw->flags = SKY2_HW_GIGABIT
2848 | SKY2_HW_NEWER_PHY
2849 | SKY2_HW_ADV_POWER_CTL;
2850 break;
2851
2852 case CHIP_ID_YUKON_EX:
2853 hw->flags = SKY2_HW_GIGABIT
2854 | SKY2_HW_NEWER_PHY
2855 | SKY2_HW_NEW_LE
2856 | SKY2_HW_ADV_POWER_CTL;
2857
2858 /* New transmit checksum */
2859 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2860 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2861 break;
2862
2863 case CHIP_ID_YUKON_EC:
2864 /* This rev is really old, and requires untested workarounds */
2865 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2866 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2867 return -EOPNOTSUPP;
2868 }
39dbd958 2869 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2870 break;
2871
2872 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2873 break;
2874
05745c4a
SH		 2875 case CHIP_ID_YUKON_FE_P:
2876 hw->flags = SKY2_HW_NEWER_PHY
2877 | SKY2_HW_NEW_LE
2878 | SKY2_HW_AUTO_TX_SUM
2879 | SKY2_HW_ADV_POWER_CTL;
2880 break;
ed4d4161
SH		 2881
2882 case CHIP_ID_YUKON_SUPR:
2883 hw->flags = SKY2_HW_GIGABIT
2884 | SKY2_HW_NEWER_PHY
2885 | SKY2_HW_NEW_LE
2886 | SKY2_HW_AUTO_TX_SUM
2887 | SKY2_HW_ADV_POWER_CTL;
2888 break;
2889
0ce8b98d
SH		 2890 case CHIP_ID_YUKON_UL_2:
2891 hw->flags = SKY2_HW_GIGABIT
2892 | SKY2_HW_ADV_POWER_CTL;
2893 break;
2894
ea76e635 2895 default:
b02a9258
SH		 2896 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2897 hw->chip_id);
cd28ab6a
SH		 2898 return -EOPNOTSUPP;
2899 }
2900
ea76e635
SH		 2901 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2902 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2903 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2904
e3173832
SH		 2905 hw->ports = 1;
2906 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2907 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2908 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2909 ++hw->ports;
2910 }
2911
2912 return 0;
2913}
2914
2915static void sky2_reset(struct sky2_hw *hw)
2916{
555382cb 2917 struct pci_dev *pdev = hw->pdev;
e3173832 2918 u16 status;
555382cb
SH		 2919 int i, cap;
2920 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2921
cd28ab6a 2922 /* disable ASF */
4f44d8ba
SH		 2923 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2924 status = sky2_read16(hw, HCU_CCSR);
2925 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2926 HCU_CCSR_UC_STATE_MSK);
2927 sky2_write16(hw, HCU_CCSR, status);
2928 } else
2929 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2930 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2931
2932 /* do a SW reset */
2933 sky2_write8(hw, B0_CTST, CS_RST_SET);
2934 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2935
ac93a394
SH		 2936 /* allow writes to PCI config */
2937 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2938
cd28ab6a 2939 /* clear PCI errors, if any */
b32f40c4 2940 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2941 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2942 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2943
2944 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2945
555382cb
SH		 2946 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2947 if (cap) {
7782c8c4
SH		 2948 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2949 0xfffffffful);
555382cb
SH		 2950
2951 /* If error bit is stuck on ignore it */
2952 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2953 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2954 else
555382cb
SH		 2955 hwe_mask |= Y2_IS_PCI_EXP;
2956 }
cd28ab6a 2957
ae306cca 2958 sky2_power_on(hw);
82637e80 2959 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2960
2961 for (i = 0; i < hw->ports; i++) {
2962 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2963 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2964
ed4d4161
SH		 2965 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2966 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2967 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2968 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2969 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2970 }
2971
793b883e
SH		 2972 /* Clear I2C IRQ noise */
2973 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2974
2975 /* turn off hardware timer (unused) */
2976 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2977 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2978
cd28ab6a
SH		 2979 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2980
69634ee7
SH		 2981 /* Turn off descriptor polling */
2982 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2983
2984 /* Turn off receive timestamp */
2985 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2986 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2987
2988 /* enable the Tx Arbiters */
2989 for (i = 0; i < hw->ports; i++)
2990 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2991
2992 /* Initialize ram interface */
2993 for (i = 0; i < hw->ports; i++) {
793b883e 2994 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2995
2996 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2997 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2998 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2999 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3000 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3001 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3002 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3003 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3004 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3005 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3006 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3007 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3008 }
3009
555382cb 3010 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3011
cd28ab6a 3012 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3013 sky2_gmac_reset(hw, i);
cd28ab6a 3014
cd28ab6a
SH		 3015 memset(hw->st_le, 0, STATUS_LE_BYTES);
3016 hw->st_idx = 0;
3017
3018 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3019 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3020
3021 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3022 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3023
3024 /* Set the list last index */
793b883e 3025 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3026
290d4de5
SH		 3027 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3028 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3029
290d4de5
SH		 3030 /* set Status-FIFO ISR watermark */
3031 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3032 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3033 else
3034 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3035
290d4de5 3036 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3037 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3038 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3039
793b883e 3040 /* enable status unit */
cd28ab6a
SH		 3041 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3042
3043 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3044 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3045 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3046}
3047
81906791
SH		 3048static void sky2_restart(struct work_struct *work)
3049{
3050 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3051 struct net_device *dev;
3052 int i, err;
3053
81906791 3054 rtnl_lock();
81906791
SH		 3055 for (i = 0; i < hw->ports; i++) {
3056 dev = hw->dev[i];
3057 if (netif_running(dev))
3058 sky2_down(dev);
3059 }
3060
8cfcbe99
SH		 3061 napi_disable(&hw->napi);
3062 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3063 sky2_reset(hw);
3064 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3065 napi_enable(&hw->napi);
81906791
SH		 3066
3067 for (i = 0; i < hw->ports; i++) {
3068 dev = hw->dev[i];
3069 if (netif_running(dev)) {
3070 err = sky2_up(dev);
3071 if (err) {
3072 printk(KERN_INFO PFX "%s: could not restart %d\n",
3073 dev->name, err);
3074 dev_close(dev);
3075 }
3076 }
3077 }
3078
81906791
SH		 3079 rtnl_unlock();
3080}
3081
e3173832
SH		 3082static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3083{
3084 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3085}
3086
3087static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3088{
3089 const struct sky2_port *sky2 = netdev_priv(dev);
3090
3091 wol->supported = sky2_wol_supported(sky2->hw);
3092 wol->wolopts = sky2->wol;
3093}
3094
3095static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3096{
3097 struct sky2_port *sky2 = netdev_priv(dev);
3098 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3099
9d731d77
RW		 3100 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3101 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3102 return -EOPNOTSUPP;
3103
3104 sky2->wol = wol->wolopts;
3105
05745c4a
SH		 3106 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3107 hw->chip_id == CHIP_ID_YUKON_EX ||
3108 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3109 sky2_write32(hw, B0_CTST, sky2->wol
3110 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3111
9d731d77
RW		 3112 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3113
e3173832
SH		 3114 if (!netif_running(dev))
3115 sky2_wol_init(sky2);
cd28ab6a
SH		 3116 return 0;
3117}
3118
28bd181a 3119static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3120{
b89165f2
SH		 3121 if (sky2_is_copper(hw)) {
3122 u32 modes = SUPPORTED_10baseT_Half
3123 | SUPPORTED_10baseT_Full
3124 | SUPPORTED_100baseT_Half
3125 | SUPPORTED_100baseT_Full
3126 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3127
ea76e635 3128 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3129 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3130 | SUPPORTED_1000baseT_Full;
3131 return modes;
cd28ab6a 3132 } else
b89165f2
SH		 3133 return SUPPORTED_1000baseT_Half
3134 | SUPPORTED_1000baseT_Full
3135 | SUPPORTED_Autoneg
3136 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3137}
3138
793b883e 3139static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3140{
3141 struct sky2_port *sky2 = netdev_priv(dev);
3142 struct sky2_hw *hw = sky2->hw;
3143
3144 ecmd->transceiver = XCVR_INTERNAL;
3145 ecmd->supported = sky2_supported_modes(hw);
3146 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3147 if (sky2_is_copper(hw)) {
cd28ab6a 3148 ecmd->port = PORT_TP;
b89165f2
SH		 3149 ecmd->speed = sky2->speed;
3150 } else {
3151 ecmd->speed = SPEED_1000;
cd28ab6a 3152 ecmd->port = PORT_FIBRE;
b89165f2 3153 }
cd28ab6a
SH		 3154
3155 ecmd->advertising = sky2->advertising;
3156 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3157 ecmd->duplex = sky2->duplex;
3158 return 0;
3159}
3160
3161static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3162{
3163 struct sky2_port *sky2 = netdev_priv(dev);
3164 const struct sky2_hw *hw = sky2->hw;
3165 u32 supported = sky2_supported_modes(hw);
3166
3167 if (ecmd->autoneg == AUTONEG_ENABLE) {
3168 ecmd->advertising = supported;
3169 sky2->duplex = -1;
3170 sky2->speed = -1;
3171 } else {
3172 u32 setting;
3173
793b883e 3174 switch (ecmd->speed) {
cd28ab6a
SH		 3175 case SPEED_1000:
3176 if (ecmd->duplex == DUPLEX_FULL)
3177 setting = SUPPORTED_1000baseT_Full;
3178 else if (ecmd->duplex == DUPLEX_HALF)
3179 setting = SUPPORTED_1000baseT_Half;
3180 else
3181 return -EINVAL;
3182 break;
3183 case SPEED_100:
3184 if (ecmd->duplex == DUPLEX_FULL)
3185 setting = SUPPORTED_100baseT_Full;
3186 else if (ecmd->duplex == DUPLEX_HALF)
3187 setting = SUPPORTED_100baseT_Half;
3188 else
3189 return -EINVAL;
3190 break;
3191
3192 case SPEED_10:
3193 if (ecmd->duplex == DUPLEX_FULL)
3194 setting = SUPPORTED_10baseT_Full;
3195 else if (ecmd->duplex == DUPLEX_HALF)
3196 setting = SUPPORTED_10baseT_Half;
3197 else
3198 return -EINVAL;
3199 break;
3200 default:
3201 return -EINVAL;
3202 }
3203
3204 if ((setting & supported) == 0)
3205 return -EINVAL;
3206
3207 sky2->speed = ecmd->speed;
3208 sky2->duplex = ecmd->duplex;
3209 }
3210
3211 sky2->autoneg = ecmd->autoneg;
3212 sky2->advertising = ecmd->advertising;
3213
d1b139c0 3214 if (netif_running(dev)) {
1b537565 3215 sky2_phy_reinit(sky2);
d1b139c0
SH		 3216 sky2_set_multicast(dev);
3217 }
cd28ab6a
SH		 3218
3219 return 0;
3220}
3221
3222static void sky2_get_drvinfo(struct net_device *dev,
3223 struct ethtool_drvinfo *info)
3224{
3225 struct sky2_port *sky2 = netdev_priv(dev);
3226
3227 strcpy(info->driver, DRV_NAME);
3228 strcpy(info->version, DRV_VERSION);
3229 strcpy(info->fw_version, "N/A");
3230 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3231}
3232
3233static const struct sky2_stat {
793b883e
SH		 3234 char name[ETH_GSTRING_LEN];
3235 u16 offset;
cd28ab6a
SH		 3236} sky2_stats[] = {
3237 { "tx_bytes", GM_TXO_OK_HI },
3238 { "rx_bytes", GM_RXO_OK_HI },
3239 { "tx_broadcast", GM_TXF_BC_OK },
3240 { "rx_broadcast", GM_RXF_BC_OK },
3241 { "tx_multicast", GM_TXF_MC_OK },
3242 { "rx_multicast", GM_RXF_MC_OK },
3243 { "tx_unicast", GM_TXF_UC_OK },
3244 { "rx_unicast", GM_RXF_UC_OK },
3245 { "tx_mac_pause", GM_TXF_MPAUSE },
3246 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3247 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3248 { "late_collision",GM_TXF_LAT_COL },
3249 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3250 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3251 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3252
d2604540 3253 { "rx_short", GM_RXF_SHT },
cd28ab6a 3254 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3255 { "rx_64_byte_packets", GM_RXF_64B },
3256 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3257 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3258 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3259 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3260 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3261 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3262 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3263 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3264 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3265 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3266
3267 { "tx_64_byte_packets", GM_TXF_64B },
3268 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3269 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3270 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3271 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3272 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3273 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3274 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3275};
3276
cd28ab6a
SH		 3277static u32 sky2_get_rx_csum(struct net_device *dev)
3278{
3279 struct sky2_port *sky2 = netdev_priv(dev);
3280
3281 return sky2->rx_csum;
3282}
3283
3284static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3285{
3286 struct sky2_port *sky2 = netdev_priv(dev);
3287
3288 sky2->rx_csum = data;
793b883e 3289
cd28ab6a
SH		 3290 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3291 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3292
3293 return 0;
3294}
3295
3296static u32 sky2_get_msglevel(struct net_device *netdev)
3297{
3298 struct sky2_port *sky2 = netdev_priv(netdev);
3299 return sky2->msg_enable;
3300}
3301
9a7ae0a9
SH		 3302static int sky2_nway_reset(struct net_device *dev)
3303{
3304 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3305
16ad91e1 3306 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3307 return -EINVAL;
3308
1b537565 3309 sky2_phy_reinit(sky2);
d1b139c0 3310 sky2_set_multicast(dev);
9a7ae0a9
SH		 3311
3312 return 0;
3313}
3314
793b883e 3315static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3316{
3317 struct sky2_hw *hw = sky2->hw;
3318 unsigned port = sky2->port;
3319 int i;
3320
3321 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3322 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3323 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3324 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3325
793b883e 3326 for (i = 2; i < count; i++)
cd28ab6a
SH		 3327 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3328}
3329
cd28ab6a
SH		 3330static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3331{
3332 struct sky2_port *sky2 = netdev_priv(netdev);
3333 sky2->msg_enable = value;
3334}
3335
b9f2c044 3336static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3337{
b9f2c044
JG		 3338 switch (sset) {
3339 case ETH_SS_STATS:
3340 return ARRAY_SIZE(sky2_stats);
3341 default:
3342 return -EOPNOTSUPP;
3343 }
cd28ab6a
SH		 3344}
3345
3346static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3347 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3348{
3349 struct sky2_port *sky2 = netdev_priv(dev);
3350
793b883e 3351 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3352}
3353
793b883e 3354static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3355{
3356 int i;
3357
3358 switch (stringset) {
3359 case ETH_SS_STATS:
3360 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3361 memcpy(data + i * ETH_GSTRING_LEN,
3362 sky2_stats[i].name, ETH_GSTRING_LEN);
3363 break;
3364 }
3365}
3366
cd28ab6a
SH		 3367static int sky2_set_mac_address(struct net_device *dev, void *p)
3368{
3369 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3370 struct sky2_hw *hw = sky2->hw;
3371 unsigned port = sky2->port;
3372 const struct sockaddr *addr = p;
cd28ab6a
SH		 3373
3374 if (!is_valid_ether_addr(addr->sa_data))
3375 return -EADDRNOTAVAIL;
3376
cd28ab6a 3377 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3378 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3379 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3380 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3381 dev->dev_addr, ETH_ALEN);
1b537565 3382
a8ab1ec0
SH		 3383 /* virtual address for data */
3384 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3385
3386 /* physical address: used for pause frames */
3387 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3388
3389 return 0;
cd28ab6a
SH		 3390}
3391
a052b52f
SH		 3392static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3393{
3394 u32 bit;
3395
3396 bit = ether_crc(ETH_ALEN, addr) & 63;
3397 filter[bit >> 3] |= 1 << (bit & 7);
3398}
3399
cd28ab6a
SH		 3400static void sky2_set_multicast(struct net_device *dev)
3401{
3402 struct sky2_port *sky2 = netdev_priv(dev);
3403 struct sky2_hw *hw = sky2->hw;
3404 unsigned port = sky2->port;
3405 struct dev_mc_list *list = dev->mc_list;
3406 u16 reg;
3407 u8 filter[8];
a052b52f
SH		 3408 int rx_pause;
3409 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3410
a052b52f 3411 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3412 memset(filter, 0, sizeof(filter));
3413
3414 reg = gma_read16(hw, port, GM_RX_CTRL);
3415 reg |= GM_RXCR_UCF_ENA;
3416
d571b694 3417 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3418 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3419 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3420 memset(filter, 0xff, sizeof(filter));
a052b52f 3421 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3422 reg &= ~GM_RXCR_MCF_ENA;
3423 else {
3424 int i;
3425 reg |= GM_RXCR_MCF_ENA;
3426
a052b52f
SH		 3427 if (rx_pause)
3428 sky2_add_filter(filter, pause_mc_addr);
3429
3430 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3431 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3432 }
3433
cd28ab6a 3434 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3435 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3436 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3437 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3438 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3439 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3440 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3441 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3442
3443 gma_write16(hw, port, GM_RX_CTRL, reg);
3444}
3445
3446/* Can have one global because blinking is controlled by
3447 * ethtool and that is always under RTNL mutex
3448 */
a84d0a3d 3449static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3450{
a84d0a3d
SH		 3451 struct sky2_hw *hw = sky2->hw;
3452 unsigned port = sky2->port;
793b883e 3453
a84d0a3d
SH		 3454 spin_lock_bh(&sky2->phy_lock);
3455 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3456 hw->chip_id == CHIP_ID_YUKON_EX ||
3457 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3458 u16 pg;
793b883e
SH		 3459 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3460 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3461
a84d0a3d
SH		 3462 switch (mode) {
3463 case MO_LED_OFF:
3464 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3465 PHY_M_LEDC_LOS_CTRL(8) |
3466 PHY_M_LEDC_INIT_CTRL(8) |
3467 PHY_M_LEDC_STA1_CTRL(8) |
3468 PHY_M_LEDC_STA0_CTRL(8));
3469 break;
3470 case MO_LED_ON:
3471 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3472 PHY_M_LEDC_LOS_CTRL(9) |
3473 PHY_M_LEDC_INIT_CTRL(9) |
3474 PHY_M_LEDC_STA1_CTRL(9) |
3475 PHY_M_LEDC_STA0_CTRL(9));
3476 break;
3477 case MO_LED_BLINK:
3478 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3479 PHY_M_LEDC_LOS_CTRL(0xa) |
3480 PHY_M_LEDC_INIT_CTRL(0xa) |
3481 PHY_M_LEDC_STA1_CTRL(0xa) |
3482 PHY_M_LEDC_STA0_CTRL(0xa));
3483 break;
3484 case MO_LED_NORM:
3485 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3486 PHY_M_LEDC_LOS_CTRL(1) |
3487 PHY_M_LEDC_INIT_CTRL(8) |
3488 PHY_M_LEDC_STA1_CTRL(7) |
3489 PHY_M_LEDC_STA0_CTRL(7));
3490 }
793b883e 3491
a84d0a3d
SH		 3492 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3493 } else
7d2e3cb7 3494 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3495 PHY_M_LED_MO_DUP(mode) |
3496 PHY_M_LED_MO_10(mode) |
3497 PHY_M_LED_MO_100(mode) |
3498 PHY_M_LED_MO_1000(mode) |
3499 PHY_M_LED_MO_RX(mode) |
3500 PHY_M_LED_MO_TX(mode));
3501
3502 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3503}
3504
3505/* blink LED's for finding board */
3506static int sky2_phys_id(struct net_device *dev, u32 data)
3507{
3508 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3509 unsigned int i;
cd28ab6a 3510
a84d0a3d
SH		 3511 if (data == 0)
3512 data = UINT_MAX;
cd28ab6a 3513
a84d0a3d
SH		 3514 for (i = 0; i < data; i++) {
3515 sky2_led(sky2, MO_LED_ON);
3516 if (msleep_interruptible(500))
3517 break;
3518 sky2_led(sky2, MO_LED_OFF);
3519 if (msleep_interruptible(500))
3520 break;
793b883e 3521 }
a84d0a3d 3522 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3523
3524 return 0;
3525}
3526
3527static void sky2_get_pauseparam(struct net_device *dev,
3528 struct ethtool_pauseparam *ecmd)
3529{
3530 struct sky2_port *sky2 = netdev_priv(dev);
3531
16ad91e1
SH		 3532 switch (sky2->flow_mode) {
3533 case FC_NONE:
3534 ecmd->tx_pause = ecmd->rx_pause = 0;
3535 break;
3536 case FC_TX:
3537 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3538 break;
3539 case FC_RX:
3540 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3541 break;
3542 case FC_BOTH:
3543 ecmd->tx_pause = ecmd->rx_pause = 1;
3544 }
3545
cd28ab6a
SH		 3546 ecmd->autoneg = sky2->autoneg;
3547}
3548
3549static int sky2_set_pauseparam(struct net_device *dev,
3550 struct ethtool_pauseparam *ecmd)
3551{
3552 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3553
3554 sky2->autoneg = ecmd->autoneg;
16ad91e1 3555 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3556
16ad91e1
SH		 3557 if (netif_running(dev))
3558 sky2_phy_reinit(sky2);
cd28ab6a 3559
2eaba1a2 3560 return 0;
cd28ab6a
SH		 3561}
3562
fb17358f
SH		 3563static int sky2_get_coalesce(struct net_device *dev,
3564 struct ethtool_coalesce *ecmd)
3565{
3566 struct sky2_port *sky2 = netdev_priv(dev);
3567 struct sky2_hw *hw = sky2->hw;
3568
3569 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3570 ecmd->tx_coalesce_usecs = 0;
3571 else {
3572 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3573 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3574 }
3575 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3576
3577 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3578 ecmd->rx_coalesce_usecs = 0;
3579 else {
3580 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3581 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3582 }
3583 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3584
3585 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3586 ecmd->rx_coalesce_usecs_irq = 0;
3587 else {
3588 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3589 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3590 }
3591
3592 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3593
3594 return 0;
3595}
3596
3597/* Note: this affect both ports */
3598static int sky2_set_coalesce(struct net_device *dev,
3599 struct ethtool_coalesce *ecmd)
3600{
3601 struct sky2_port *sky2 = netdev_priv(dev);
3602 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3603 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3604
77b3d6a2
SH		 3605 if (ecmd->tx_coalesce_usecs > tmax ||
3606 ecmd->rx_coalesce_usecs > tmax ||
3607 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3608 return -EINVAL;
3609
ff81fbbe 3610 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3611 return -EINVAL;
ff81fbbe 3612 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3613 return -EINVAL;
ff81fbbe 3614 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3615 return -EINVAL;
3616
3617 if (ecmd->tx_coalesce_usecs == 0)
3618 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3619 else {
3620 sky2_write32(hw, STAT_TX_TIMER_INI,
3621 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3622 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3623 }
3624 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3625
3626 if (ecmd->rx_coalesce_usecs == 0)
3627 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3628 else {
3629 sky2_write32(hw, STAT_LEV_TIMER_INI,
3630 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3631 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3632 }
3633 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3634
3635 if (ecmd->rx_coalesce_usecs_irq == 0)
3636 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3637 else {
d28d4870 3638 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3639 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3640 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3641 }
3642 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3643 return 0;
3644}
3645
793b883e
SH		 3646static void sky2_get_ringparam(struct net_device *dev,
3647 struct ethtool_ringparam *ering)
3648{
3649 struct sky2_port *sky2 = netdev_priv(dev);
3650
3651 ering->rx_max_pending = RX_MAX_PENDING;
3652 ering->rx_mini_max_pending = 0;
3653 ering->rx_jumbo_max_pending = 0;
3654 ering->tx_max_pending = TX_RING_SIZE - 1;
3655
3656 ering->rx_pending = sky2->rx_pending;
3657 ering->rx_mini_pending = 0;
3658 ering->rx_jumbo_pending = 0;
3659 ering->tx_pending = sky2->tx_pending;
3660}
3661
3662static int sky2_set_ringparam(struct net_device *dev,
3663 struct ethtool_ringparam *ering)
3664{
3665 struct sky2_port *sky2 = netdev_priv(dev);
3666 int err = 0;
3667
3668 if (ering->rx_pending > RX_MAX_PENDING ||
3669 ering->rx_pending < 8 ||
3670 ering->tx_pending < MAX_SKB_TX_LE ||
3671 ering->tx_pending > TX_RING_SIZE - 1)
3672 return -EINVAL;
3673
3674 if (netif_running(dev))
3675 sky2_down(dev);
3676
3677 sky2->rx_pending = ering->rx_pending;
3678 sky2->tx_pending = ering->tx_pending;
3679
1b537565 3680 if (netif_running(dev)) {
793b883e 3681 err = sky2_up(dev);
1b537565
SH		 3682 if (err)
3683 dev_close(dev);
3684 }
793b883e
SH		 3685
3686 return err;
3687}
3688
793b883e
SH		 3689static int sky2_get_regs_len(struct net_device *dev)
3690{
6e4cbb34 3691 return 0x4000;
793b883e
SH		 3692}
3693
3694/*
3695 * Returns copy of control register region
3ead5db7 3696 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3697 */
3698static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3699 void *p)
3700{
3701 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3702 const void __iomem *io = sky2->hw->regs;
295b54c4 3703 unsigned int b;
793b883e
SH		 3704
3705 regs->version = 1;
793b883e 3706
295b54c4
SH		 3707 for (b = 0; b < 128; b++) {
3708 /* This complicated switch statement is to make sure and
3709 * only access regions that are unreserved.
3710 * Some blocks are only valid on dual port cards.
3711 * and block 3 has some special diagnostic registers that
3712 * are poison.
3713 */
3714 switch (b) {
3715 case 3:
3716 /* skip diagnostic ram region */
3717 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3718 break;
3ead5db7 3719
295b54c4
SH		 3720 /* dual port cards only */
3721 case 5: /* Tx Arbiter 2 */
3722 case 9: /* RX2 */
3723 case 14 ... 15: /* TX2 */
3724 case 17: case 19: /* Ram Buffer 2 */
3725 case 22 ... 23: /* Tx Ram Buffer 2 */
3726 case 25: /* Rx MAC Fifo 1 */
3727 case 27: /* Tx MAC Fifo 2 */
3728 case 31: /* GPHY 2 */
3729 case 40 ... 47: /* Pattern Ram 2 */
3730 case 52: case 54: /* TCP Segmentation 2 */
3731 case 112 ... 116: /* GMAC 2 */
3732 if (sky2->hw->ports == 1)
3733 goto reserved;
3734 /* fall through */
3735 case 0: /* Control */
3736 case 2: /* Mac address */
3737 case 4: /* Tx Arbiter 1 */
3738 case 7: /* PCI express reg */
3739 case 8: /* RX1 */
3740 case 12 ... 13: /* TX1 */
3741 case 16: case 18:/* Rx Ram Buffer 1 */
3742 case 20 ... 21: /* Tx Ram Buffer 1 */
3743 case 24: /* Rx MAC Fifo 1 */
3744 case 26: /* Tx MAC Fifo 1 */
3745 case 28 ... 29: /* Descriptor and status unit */
3746 case 30: /* GPHY 1*/
3747 case 32 ... 39: /* Pattern Ram 1 */
3748 case 48: case 50: /* TCP Segmentation 1 */
3749 case 56 ... 60: /* PCI space */
3750 case 80 ... 84: /* GMAC 1 */
3751 memcpy_fromio(p, io, 128);
3752 break;
3753 default:
3754reserved:
3755 memset(p, 0, 128);
3756 }
3ead5db7 3757
295b54c4
SH		 3758 p += 128;
3759 io += 128;
3760 }
793b883e 3761}
cd28ab6a 3762
b628ed98
SH		 3763/* In order to do Jumbo packets on these chips, need to turn off the
3764 * transmit store/forward. Therefore checksum offload won't work.
3765 */
3766static int no_tx_offload(struct net_device *dev)
3767{
3768 const struct sky2_port *sky2 = netdev_priv(dev);
3769 const struct sky2_hw *hw = sky2->hw;
3770
69161611 3771 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3772}
3773
3774static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3775{
3776 if (data && no_tx_offload(dev))
3777 return -EINVAL;
3778
3779 return ethtool_op_set_tx_csum(dev, data);
3780}
3781
3782
3783static int sky2_set_tso(struct net_device *dev, u32 data)
3784{
3785 if (data && no_tx_offload(dev))
3786 return -EINVAL;
3787
3788 return ethtool_op_set_tso(dev, data);
3789}
3790
f4331a6d
SH		 3791static int sky2_get_eeprom_len(struct net_device *dev)
3792{
3793 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3794 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3795 u16 reg2;
3796
b32f40c4 3797 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3798 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3799}
3800
1413235c 3801static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3802{
1413235c 3803 unsigned long start = jiffies;
f4331a6d 3804
1413235c
SH		 3805 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3806 /* Can take up to 10.6 ms for write */
3807 if (time_after(jiffies, start + HZ/4)) {
3808 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3809 return -ETIMEDOUT;
3810 }
3811 mdelay(1);
3812 }
167f53d0 3813
1413235c
SH		 3814 return 0;
3815}
167f53d0 3816
1413235c
SH		 3817static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3818 u16 offset, size_t length)
3819{
3820 int rc = 0;
3821
3822 while (length > 0) {
3823 u32 val;
3824
3825 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3826 rc = sky2_vpd_wait(hw, cap, 0);
3827 if (rc)
3828 break;
3829
3830 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3831
3832 memcpy(data, &val, min(sizeof(val), length));
3833 offset += sizeof(u32);
3834 data += sizeof(u32);
3835 length -= sizeof(u32);
3836 }
3837
3838 return rc;
f4331a6d
SH		 3839}
3840
1413235c
SH		 3841static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3842 u16 offset, unsigned int length)
f4331a6d 3843{
1413235c
SH		 3844 unsigned int i;
3845 int rc = 0;
3846
3847 for (i = 0; i < length; i += sizeof(u32)) {
3848 u32 val = *(u32 *)(data + i);
3849
3850 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3851 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3852
3853 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3854 if (rc)
3855 break;
3856 }
3857 return rc;
f4331a6d
SH		 3858}
3859
3860static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3861 u8 *data)
3862{
3863 struct sky2_port *sky2 = netdev_priv(dev);
3864 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3865
3866 if (!cap)
3867 return -EINVAL;
3868
3869 eeprom->magic = SKY2_EEPROM_MAGIC;
3870
1413235c 3871 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3872}
3873
3874static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3875 u8 *data)
3876{
3877 struct sky2_port *sky2 = netdev_priv(dev);
3878 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3879
3880 if (!cap)
3881 return -EINVAL;
3882
3883 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3884 return -EINVAL;
3885
1413235c
SH		 3886 /* Partial writes not supported */
3887 if ((eeprom->offset & 3) || (eeprom->len & 3))
3888 return -EINVAL;
f4331a6d 3889
1413235c 3890 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3891}
3892
3893
7282d491 3894static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3895 .get_settings = sky2_get_settings,
3896 .set_settings = sky2_set_settings,
3897 .get_drvinfo = sky2_get_drvinfo,
3898 .get_wol = sky2_get_wol,
3899 .set_wol = sky2_set_wol,
3900 .get_msglevel = sky2_get_msglevel,
3901 .set_msglevel = sky2_set_msglevel,
3902 .nway_reset = sky2_nway_reset,
3903 .get_regs_len = sky2_get_regs_len,
3904 .get_regs = sky2_get_regs,
3905 .get_link = ethtool_op_get_link,
3906 .get_eeprom_len = sky2_get_eeprom_len,
3907 .get_eeprom = sky2_get_eeprom,
3908 .set_eeprom = sky2_set_eeprom,
f4331a6d 3909 .set_sg = ethtool_op_set_sg,
f4331a6d 3910 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3911 .set_tso = sky2_set_tso,
3912 .get_rx_csum = sky2_get_rx_csum,
3913 .set_rx_csum = sky2_set_rx_csum,
3914 .get_strings = sky2_get_strings,
3915 .get_coalesce = sky2_get_coalesce,
3916 .set_coalesce = sky2_set_coalesce,
3917 .get_ringparam = sky2_get_ringparam,
3918 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3919 .get_pauseparam = sky2_get_pauseparam,
3920 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3921 .phys_id = sky2_phys_id,
b9f2c044 3922 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3923 .get_ethtool_stats = sky2_get_ethtool_stats,
3924};
3925
3cf26753
SH		 3926#ifdef CONFIG_SKY2_DEBUG
3927
3928static struct dentry *sky2_debug;
3929
e4c2abe2
SH		 3930
3931/*
3932 * Read and parse the first part of Vital Product Data
3933 */
3934#define VPD_SIZE 128
3935#define VPD_MAGIC 0x82
3936
3937static const struct vpd_tag {
3938 char tag[2];
3939 char *label;
3940} vpd_tags[] = {
3941 { "PN", "Part Number" },
3942 { "EC", "Engineering Level" },
3943 { "MN", "Manufacturer" },
3944 { "SN", "Serial Number" },
3945 { "YA", "Asset Tag" },
3946 { "VL", "First Error Log Message" },
3947 { "VF", "Second Error Log Message" },
3948 { "VB", "Boot Agent ROM Configuration" },
3949 { "VE", "EFI UNDI Configuration" },
3950};
3951
3952static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3953{
3954 size_t vpd_size;
3955 loff_t offs;
3956 u8 len;
3957 unsigned char *buf;
3958 u16 reg2;
3959
3960 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3961 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3962
3963 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3964 buf = kmalloc(vpd_size, GFP_KERNEL);
3965 if (!buf) {
3966 seq_puts(seq, "no memory!\n");
3967 return;
3968 }
3969
3970 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
3971 seq_puts(seq, "VPD read failed\n");
3972 goto out;
3973 }
3974
3975 if (buf[0] != VPD_MAGIC) {
3976 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
3977 goto out;
3978 }
3979 len = buf[1];
3980 if (len == 0 || len > vpd_size - 4) {
3981 seq_printf(seq, "Invalid id length: %d\n", len);
3982 goto out;
3983 }
3984
3985 seq_printf(seq, "%.*s\n", len, buf + 3);
3986 offs = len + 3;
3987
3988 while (offs < vpd_size - 4) {
3989 int i;
3990
3991 if (!memcmp("RW", buf + offs, 2)) /* end marker */
3992 break;
3993 len = buf[offs + 2];
3994 if (offs + len + 3 >= vpd_size)
3995 break;
3996
3997 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
3998 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
3999 seq_printf(seq, " %s: %.*s\n",
4000 vpd_tags[i].label, len, buf + offs + 3);
4001 break;
4002 }
4003 }
4004 offs += len + 3;
4005 }
4006out:
4007 kfree(buf);
4008}
4009
3cf26753
SH		 4010static int sky2_debug_show(struct seq_file *seq, void *v)
4011{
4012 struct net_device *dev = seq->private;
4013 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4014 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4015 unsigned port = sky2->port;
4016 unsigned idx, last;
4017 int sop;
4018
e4c2abe2 4019 sky2_show_vpd(seq, hw);
3cf26753 4020
e4c2abe2 4021 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4022 sky2_read32(hw, B0_ISRC),
4023 sky2_read32(hw, B0_IMSK),
4024 sky2_read32(hw, B0_Y2_SP_ICR));
4025
e4c2abe2
SH		 4026 if (!netif_running(dev)) {
4027 seq_printf(seq, "network not running\n");
4028 return 0;
4029 }
4030
bea3348e 4031 napi_disable(&hw->napi);
3cf26753
SH		 4032 last = sky2_read16(hw, STAT_PUT_IDX);
4033
4034 if (hw->st_idx == last)
4035 seq_puts(seq, "Status ring (empty)\n");
4036 else {
4037 seq_puts(seq, "Status ring\n");
4038 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4039 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4040 const struct sky2_status_le *le = hw->st_le + idx;
4041 seq_printf(seq, "[%d] %#x %d %#x\n",
4042 idx, le->opcode, le->length, le->status);
4043 }
4044 seq_puts(seq, "\n");
4045 }
4046
4047 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4048 sky2->tx_cons, sky2->tx_prod,
4049 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4050 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4051
4052 /* Dump contents of tx ring */
4053 sop = 1;
4054 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4055 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4056 const struct sky2_tx_le *le = sky2->tx_le + idx;
4057 u32 a = le32_to_cpu(le->addr);
4058
4059 if (sop)
4060 seq_printf(seq, "%u:", idx);
4061 sop = 0;
4062
4063 switch(le->opcode & ~HW_OWNER) {
4064 case OP_ADDR64:
4065 seq_printf(seq, " %#x:", a);
4066 break;
4067 case OP_LRGLEN:
4068 seq_printf(seq, " mtu=%d", a);
4069 break;
4070 case OP_VLAN:
4071 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4072 break;
4073 case OP_TCPLISW:
4074 seq_printf(seq, " csum=%#x", a);
4075 break;
4076 case OP_LARGESEND:
4077 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4078 break;
4079 case OP_PACKET:
4080 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4081 break;
4082 case OP_BUFFER:
4083 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4084 break;
4085 default:
4086 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4087 a, le16_to_cpu(le->length));
4088 }
4089
4090 if (le->ctrl & EOP) {
4091 seq_putc(seq, '\n');
4092 sop = 1;
4093 }
4094 }
4095
4096 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4097 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4098 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4099 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4100
d1d08d12 4101 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4102 napi_enable(&hw->napi);
3cf26753
SH		 4103 return 0;
4104}
4105
4106static int sky2_debug_open(struct inode *inode, struct file *file)
4107{
4108 return single_open(file, sky2_debug_show, inode->i_private);
4109}
4110
4111static const struct file_operations sky2_debug_fops = {
4112 .owner = THIS_MODULE,
4113 .open = sky2_debug_open,
4114 .read = seq_read,
4115 .llseek = seq_lseek,
4116 .release = single_release,
4117};
4118
4119/*
4120 * Use network device events to create/remove/rename
4121 * debugfs file entries
4122 */
4123static int sky2_device_event(struct notifier_block *unused,
4124 unsigned long event, void *ptr)
4125{
4126 struct net_device *dev = ptr;
5b296bc9 4127 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4128
1436b301 4129 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4130 return NOTIFY_DONE;
3cf26753 4131
5b296bc9
SH		 4132 switch(event) {
4133 case NETDEV_CHANGENAME:
4134 if (sky2->debugfs) {
4135 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4136 sky2_debug, dev->name);
4137 }
4138 break;
3cf26753 4139
5b296bc9
SH		 4140 case NETDEV_GOING_DOWN:
4141 if (sky2->debugfs) {
4142 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4143 dev->name);
4144 debugfs_remove(sky2->debugfs);
4145 sky2->debugfs = NULL;
3cf26753 4146 }
5b296bc9
SH		 4147 break;
4148
4149 case NETDEV_UP:
4150 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4151 sky2_debug, dev,
4152 &sky2_debug_fops);
4153 if (IS_ERR(sky2->debugfs))
4154 sky2->debugfs = NULL;
3cf26753
SH		 4155 }
4156
4157 return NOTIFY_DONE;
4158}
4159
4160static struct notifier_block sky2_notifier = {
4161 .notifier_call = sky2_device_event,
4162};
4163
4164
4165static __init void sky2_debug_init(void)
4166{
4167 struct dentry *ent;
4168
4169 ent = debugfs_create_dir("sky2", NULL);
4170 if (!ent || IS_ERR(ent))
4171 return;
4172
4173 sky2_debug = ent;
4174 register_netdevice_notifier(&sky2_notifier);
4175}
4176
4177static __exit void sky2_debug_cleanup(void)
4178{
4179 if (sky2_debug) {
4180 unregister_netdevice_notifier(&sky2_notifier);
4181 debugfs_remove(sky2_debug);
4182 sky2_debug = NULL;
4183 }
4184}
4185
4186#else
4187#define sky2_debug_init()
4188#define sky2_debug_cleanup()
4189#endif
4190
1436b301
SH		 4191/* Two copies of network device operations to handle special case of
4192 not allowing netpoll on second port */
4193static const struct net_device_ops sky2_netdev_ops[2] = {
4194 {
4195 .ndo_open = sky2_up,
4196 .ndo_stop = sky2_down,
00829823 4197 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4198 .ndo_do_ioctl = sky2_ioctl,
4199 .ndo_validate_addr = eth_validate_addr,
4200 .ndo_set_mac_address = sky2_set_mac_address,
4201 .ndo_set_multicast_list = sky2_set_multicast,
4202 .ndo_change_mtu = sky2_change_mtu,
4203 .ndo_tx_timeout = sky2_tx_timeout,
4204#ifdef SKY2_VLAN_TAG_USED
4205 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4206#endif
4207#ifdef CONFIG_NET_POLL_CONTROLLER
4208 .ndo_poll_controller = sky2_netpoll,
4209#endif
4210 },
4211 {
4212 .ndo_open = sky2_up,
4213 .ndo_stop = sky2_down,
00829823 4214 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4215 .ndo_do_ioctl = sky2_ioctl,
4216 .ndo_validate_addr = eth_validate_addr,
4217 .ndo_set_mac_address = sky2_set_mac_address,
4218 .ndo_set_multicast_list = sky2_set_multicast,
4219 .ndo_change_mtu = sky2_change_mtu,
4220 .ndo_tx_timeout = sky2_tx_timeout,
4221#ifdef SKY2_VLAN_TAG_USED
4222 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4223#endif
4224 },
4225};
3cf26753 4226
cd28ab6a
SH		 4227/* Initialize network device */
4228static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4229 unsigned port,
be63a21c 4230 int highmem, int wol)
cd28ab6a
SH		 4231{
4232 struct sky2_port *sky2;
4233 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4234
4235 if (!dev) {
898eb71c 4236 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4237 return NULL;
4238 }
4239
cd28ab6a 4240 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4241 dev->irq = hw->pdev->irq;
cd28ab6a 4242 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4243 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4244 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4245
4246 sky2 = netdev_priv(dev);
4247 sky2->netdev = dev;
4248 sky2->hw = hw;
4249 sky2->msg_enable = netif_msg_init(debug, default_msg);
4250
cd28ab6a
SH		 4251 /* Auto speed and flow control */
4252 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4253 sky2->flow_mode = FC_BOTH;
4254
cd28ab6a
SH		 4255 sky2->duplex = -1;
4256 sky2->speed = -1;
4257 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4258 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4259 sky2->wol = wol;
75d070c5 4260
e07b1aa8 4261 spin_lock_init(&sky2->phy_lock);
793b883e 4262 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4263 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4264
4265 hw->dev[port] = dev;
4266
4267 sky2->port = port;
4268
4a50a876 4269 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4270 if (highmem)
4271 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4272
d1f13708 4273#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4274 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4275 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4276 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4277 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4278 }
d1f13708
SH		 4279#endif
4280
cd28ab6a 4281 /* read the mac address */
793b883e 4282 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4283 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4284
cd28ab6a
SH		 4285 return dev;
4286}
4287
28bd181a 4288static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4289{
4290 const struct sky2_port *sky2 = netdev_priv(dev);
4291
4292 if (netif_msg_probe(sky2))
e174961c
JB		 4293 printk(KERN_INFO PFX "%s: addr %pM\n",
4294 dev->name, dev->dev_addr);
cd28ab6a
SH		 4295}
4296
fb2690a9 4297/* Handle software interrupt used during MSI test */
7d12e780 4298static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4299{
4300 struct sky2_hw *hw = dev_id;
4301 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4302
4303 if (status == 0)
4304 return IRQ_NONE;
4305
4306 if (status & Y2_IS_IRQ_SW) {
ea76e635 4307 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4308 wake_up(&hw->msi_wait);
4309 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4310 }
4311 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4312
4313 return IRQ_HANDLED;
4314}
4315
4316/* Test interrupt path by forcing a a software IRQ */
4317static int __devinit sky2_test_msi(struct sky2_hw *hw)
4318{
4319 struct pci_dev *pdev = hw->pdev;
4320 int err;
4321
bb507fe1
SH		 4322 init_waitqueue_head (&hw->msi_wait);
4323
fb2690a9
SH		 4324 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4325
b0a20ded 4326 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4327 if (err) {
b02a9258 4328 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4329 return err;
4330 }
4331
fb2690a9 4332 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4333 sky2_read8(hw, B0_CTST);
fb2690a9 4334
ea76e635 4335 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4336
ea76e635 4337 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4338 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4339 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4340 "switching to INTx mode.\n");
fb2690a9
SH		 4341
4342 err = -EOPNOTSUPP;
4343 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4344 }
4345
4346 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4347 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4348
4349 free_irq(pdev->irq, hw);
4350
4351 return err;
4352}
4353
c7127a34
SH		 4354/* This driver supports yukon2 chipset only */
4355static const char *sky2_name(u8 chipid, char *buf, int sz)
4356{
4357 const char *name[] = {
4358 "XL", /* 0xb3 */
4359 "EC Ultra", /* 0xb4 */
4360 "Extreme", /* 0xb5 */
4361 "EC", /* 0xb6 */
4362 "FE", /* 0xb7 */
4363 "FE+", /* 0xb8 */
4364 "Supreme", /* 0xb9 */
0ce8b98d 4365 "UL 2", /* 0xba */
c7127a34
SH		 4366 };
4367
0ce8b98d 4368 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4369 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4370 else
4371 snprintf(buf, sz, "(chip %#x)", chipid);
4372 return buf;
4373}
4374
cd28ab6a
SH		 4375static int __devinit sky2_probe(struct pci_dev *pdev,
4376 const struct pci_device_id *ent)
4377{
7f60c64b 4378 struct net_device *dev;
cd28ab6a 4379 struct sky2_hw *hw;
be63a21c 4380 int err, using_dac = 0, wol_default;
3834507d 4381 u32 reg;
c7127a34 4382 char buf1[16];
cd28ab6a 4383
793b883e
SH		 4384 err = pci_enable_device(pdev);
4385 if (err) {
b02a9258 4386 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4387 goto err_out;
4388 }
4389
6cc90a5a
SH		 4390 /* Get configuration information
4391 * Note: only regular PCI config access once to test for HW issues
4392 * other PCI access through shared memory for speed and to
4393 * avoid MMCONFIG problems.
4394 */
4395 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4396 if (err) {
4397 dev_err(&pdev->dev, "PCI read config failed\n");
4398 goto err_out;
4399 }
4400
4401 if (~reg == 0) {
4402 dev_err(&pdev->dev, "PCI configuration read error\n");
4403 goto err_out;
4404 }
4405
793b883e
SH		 4406 err = pci_request_regions(pdev, DRV_NAME);
4407 if (err) {
b02a9258 4408 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4409 goto err_out_disable;
cd28ab6a
SH		 4410 }
4411
4412 pci_set_master(pdev);
4413
d1f3d4dd 4414 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4415 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4416 using_dac = 1;
6a35528a 4417 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4418 if (err < 0) {
b02a9258
SH		 4419 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4420 "for consistent allocations\n");
d1f3d4dd
SH		 4421 goto err_out_free_regions;
4422 }
d1f3d4dd 4423 } else {
284901a9 4424 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4425 if (err) {
b02a9258 4426 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4427 goto err_out_free_regions;
4428 }
4429 }
d1f3d4dd 4430
3834507d
SH		 4431
4432#ifdef __BIG_ENDIAN
4433 /* The sk98lin vendor driver uses hardware byte swapping but
4434 * this driver uses software swapping.
4435 */
4436 reg &= ~PCI_REV_DESC;
4437 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4438 if (err) {
4439 dev_err(&pdev->dev, "PCI write config failed\n");
4440 goto err_out_free_regions;
4441 }
4442#endif
4443
9d731d77 4444 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4445
cd28ab6a 4446 err = -ENOMEM;
6aad85d6 4447 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4448 if (!hw) {
b02a9258 4449 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4450 goto err_out_free_regions;
4451 }
4452
cd28ab6a 4453 hw->pdev = pdev;
cd28ab6a
SH		 4454
4455 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4456 if (!hw->regs) {
b02a9258 4457 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4458 goto err_out_free_hw;
4459 }
4460
08c06d8a 4461 /* ring for status responses */
167f53d0 4462 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4463 if (!hw->st_le)
4464 goto err_out_iounmap;
4465
e3173832 4466 err = sky2_init(hw);
cd28ab6a 4467 if (err)
793b883e 4468 goto err_out_iounmap;
cd28ab6a 4469
c844d483
SH		 4470 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4471 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4472
e3173832
SH		 4473 sky2_reset(hw);
4474
be63a21c 4475 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4476 if (!dev) {
4477 err = -ENOMEM;
cd28ab6a 4478 goto err_out_free_pci;
7f60c64b 4479 }
cd28ab6a 4480
9fa1b1f3
SH		 4481 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4482 err = sky2_test_msi(hw);
4483 if (err == -EOPNOTSUPP)
4484 pci_disable_msi(pdev);
4485 else if (err)
4486 goto err_out_free_netdev;
4487 }
4488
793b883e
SH		 4489 err = register_netdev(dev);
4490 if (err) {
b02a9258 4491 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4492 goto err_out_free_netdev;
4493 }
4494
6de16237
SH		 4495 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4496
ea76e635
SH		 4497 err = request_irq(pdev->irq, sky2_intr,
4498 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4499 dev->name, hw);
9fa1b1f3 4500 if (err) {
b02a9258 4501 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4502 goto err_out_unregister;
4503 }
4504 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4505 napi_enable(&hw->napi);
9fa1b1f3 4506
cd28ab6a
SH		 4507 sky2_show_addr(dev);
4508
7f60c64b 4509 if (hw->ports > 1) {
4510 struct net_device *dev1;
4511
be63a21c 4512 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4513 if (!dev1)
4514 dev_warn(&pdev->dev, "allocation for second device failed\n");
4515 else if ((err = register_netdev(dev1))) {
4516 dev_warn(&pdev->dev,
4517 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4518 hw->dev[1] = NULL;
4519 free_netdev(dev1);
b02a9258
SH		 4520 } else
4521 sky2_show_addr(dev1);
cd28ab6a
SH		 4522 }
4523
32c2c300 4524 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4525 INIT_WORK(&hw->restart_work, sky2_restart);
4526
793b883e
SH		 4527 pci_set_drvdata(pdev, hw);
4528
cd28ab6a
SH		 4529 return 0;
4530
793b883e 4531err_out_unregister:
ea76e635 4532 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4533 pci_disable_msi(pdev);
793b883e 4534 unregister_netdev(dev);
cd28ab6a
SH		 4535err_out_free_netdev:
4536 free_netdev(dev);
cd28ab6a 4537err_out_free_pci:
793b883e 4538 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4539 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4540err_out_iounmap:
4541 iounmap(hw->regs);
4542err_out_free_hw:
4543 kfree(hw);
4544err_out_free_regions:
4545 pci_release_regions(pdev);
44a1d2e5 4546err_out_disable:
cd28ab6a 4547 pci_disable_device(pdev);
cd28ab6a 4548err_out:
549a68c3 4549 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4550 return err;
4551}
4552
4553static void __devexit sky2_remove(struct pci_dev *pdev)
4554{
793b883e 4555 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4556 int i;
cd28ab6a 4557
793b883e 4558 if (!hw)
cd28ab6a
SH		 4559 return;
4560
32c2c300 4561 del_timer_sync(&hw->watchdog_timer);
6de16237 4562 cancel_work_sync(&hw->restart_work);
d27ed387 4563
b877fe28 4564 for (i = hw->ports-1; i >= 0; --i)
6de16237 4565 unregister_netdev(hw->dev[i]);
81906791 4566
d27ed387 4567 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4568
ae306cca
SH		 4569 sky2_power_aux(hw);
4570
cd28ab6a 4571 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4572 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4573 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4574
4575 free_irq(pdev->irq, hw);
ea76e635 4576 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4577 pci_disable_msi(pdev);
793b883e 4578 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4579 pci_release_regions(pdev);
4580 pci_disable_device(pdev);
793b883e 4581
b877fe28 4582 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4583 free_netdev(hw->dev[i]);
4584
cd28ab6a
SH		 4585 iounmap(hw->regs);
4586 kfree(hw);
5afa0a9c 4587
cd28ab6a
SH		 4588 pci_set_drvdata(pdev, NULL);
4589}
4590
4591#ifdef CONFIG_PM
4592static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4593{
793b883e 4594 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4595 int i, wol = 0;
cd28ab6a 4596
549a68c3
SH		 4597 if (!hw)
4598 return 0;
4599
063a0b38
SH		 4600 del_timer_sync(&hw->watchdog_timer);
4601 cancel_work_sync(&hw->restart_work);
4602
f05267e7 4603 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4604 struct net_device *dev = hw->dev[i];
e3173832 4605 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4606
063a0b38 4607 netif_device_detach(dev);
e3173832 4608 if (netif_running(dev))
5afa0a9c 4609 sky2_down(dev);
e3173832
SH		 4610
4611 if (sky2->wol)
4612 sky2_wol_init(sky2);
4613
4614 wol |= sky2->wol;
cd28ab6a
SH		 4615 }
4616
8ab8fca2 4617 sky2_write32(hw, B0_IMSK, 0);
6de16237 4618 napi_disable(&hw->napi);
ae306cca 4619 sky2_power_aux(hw);
e3173832 4620
d374c1c1 4621 pci_save_state(pdev);
e3173832 4622 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4623 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4624
2ccc99b7 4625 return 0;
cd28ab6a
SH		 4626}
4627
4628static int sky2_resume(struct pci_dev *pdev)
4629{
793b883e 4630 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4631 int i, err;
cd28ab6a 4632
549a68c3
SH		 4633 if (!hw)
4634 return 0;
4635
f71eb1a2
SH		 4636 err = pci_set_power_state(pdev, PCI_D0);
4637 if (err)
4638 goto out;
ae306cca
SH		 4639
4640 err = pci_restore_state(pdev);
4641 if (err)
4642 goto out;
4643
cd28ab6a 4644 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4645
4646 /* Re-enable all clocks */
05745c4a
SH		 4647 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4648 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4649 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4650 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4651
e3173832 4652 sky2_reset(hw);
8ab8fca2 4653 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4654 napi_enable(&hw->napi);
8ab8fca2 4655
f05267e7 4656 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4657 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4658
4659 netif_device_attach(dev);
6a5706b9 4660 if (netif_running(dev)) {
08c06d8a
SH		 4661 err = sky2_up(dev);
4662 if (err) {
4663 printk(KERN_ERR PFX "%s: could not up: %d\n",
4664 dev->name, err);
68c28898 4665 rtnl_lock();
08c06d8a 4666 dev_close(dev);
68c28898 4667 rtnl_unlock();
eb35cf60 4668 goto out;
5afa0a9c 4669 }
cd28ab6a
SH		 4670 }
4671 }
eb35cf60 4672
ae306cca 4673 return 0;
08c06d8a 4674out:
b02a9258 4675 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4676 pci_disable_device(pdev);
08c06d8a 4677 return err;
cd28ab6a
SH		 4678}
4679#endif
4680
e3173832
SH		 4681static void sky2_shutdown(struct pci_dev *pdev)
4682{
4683 struct sky2_hw *hw = pci_get_drvdata(pdev);
4684 int i, wol = 0;
4685
549a68c3
SH		 4686 if (!hw)
4687 return;
4688
5c0d6b34 4689 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4690
4691 for (i = 0; i < hw->ports; i++) {
4692 struct net_device *dev = hw->dev[i];
4693 struct sky2_port *sky2 = netdev_priv(dev);
4694
4695 if (sky2->wol) {
4696 wol = 1;
4697 sky2_wol_init(sky2);
4698 }
4699 }
4700
4701 if (wol)
4702 sky2_power_aux(hw);
4703
4704 pci_enable_wake(pdev, PCI_D3hot, wol);
4705 pci_enable_wake(pdev, PCI_D3cold, wol);
4706
4707 pci_disable_device(pdev);
f71eb1a2 4708 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4709}
4710
cd28ab6a 4711static struct pci_driver sky2_driver = {
793b883e
SH		 4712 .name = DRV_NAME,
4713 .id_table = sky2_id_table,
4714 .probe = sky2_probe,
4715 .remove = __devexit_p(sky2_remove),
cd28ab6a 4716#ifdef CONFIG_PM
793b883e
SH		 4717 .suspend = sky2_suspend,
4718 .resume = sky2_resume,
cd28ab6a 4719#endif
e3173832 4720 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4721};
4722
4723static int __init sky2_init_module(void)
4724{
c844d483
SH		 4725 pr_info(PFX "driver version " DRV_VERSION "\n");
4726
3cf26753 4727 sky2_debug_init();
50241c4c 4728 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4729}
4730
4731static void __exit sky2_cleanup_module(void)
4732{
4733 pci_unregister_driver(&sky2_driver);
3cf26753 4734 sky2_debug_cleanup();
cd28ab6a
SH		 4735}
4736
4737module_init(sky2_init_module);
4738module_exit(sky2_cleanup_module);
4739
4740MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4741MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4742MODULE_LICENSE("GPL");
5f4f9dc1 4743MODULE_VERSION(DRV_VERSION);
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