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Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
cd28ab6a | 26 | #include <linux/config.h> |
793b883e | 27 | #include <linux/crc32.h> |
cd28ab6a SH |
28 | #include <linux/kernel.h> |
29 | #include <linux/version.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/netdevice.h> | |
d0bbccfa | 32 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
33 | #include <linux/etherdevice.h> |
34 | #include <linux/ethtool.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/ip.h> | |
37 | #include <linux/tcp.h> | |
38 | #include <linux/in.h> | |
39 | #include <linux/delay.h> | |
91c86df5 | 40 | #include <linux/workqueue.h> |
d1f13708 | 41 | #include <linux/if_vlan.h> |
d70cd51a | 42 | #include <linux/prefetch.h> |
ef743d33 | 43 | #include <linux/mii.h> |
cd28ab6a SH |
44 | |
45 | #include <asm/irq.h> | |
46 | ||
d1f13708 SH |
47 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
48 | #define SKY2_VLAN_TAG_USED 1 | |
49 | #endif | |
50 | ||
cd28ab6a SH |
51 | #include "sky2.h" |
52 | ||
53 | #define DRV_NAME "sky2" | |
bdf9c27d | 54 | #define DRV_VERSION "1.2" |
cd28ab6a SH |
55 | #define PFX DRV_NAME " " |
56 | ||
57 | /* | |
58 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
59 | * that are organized into three (receive, transmit, status) different rings | |
60 | * similar to Tigon3. A transmit can require several elements; | |
61 | * a receive requires one (or two if using 64 bit dma). | |
62 | */ | |
63 | ||
13210ce5 | 64 | #define RX_LE_SIZE 512 |
cd28ab6a | 65 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
bea86103 | 66 | #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) |
13210ce5 | 67 | #define RX_DEF_PENDING RX_MAX_PENDING |
82788c7a | 68 | #define RX_SKB_ALIGN 8 |
793b883e SH |
69 | |
70 | #define TX_RING_SIZE 512 | |
71 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
72 | #define TX_MIN_PENDING 64 | |
b19666d9 | 73 | #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS) |
cd28ab6a | 74 | |
793b883e | 75 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a SH |
76 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
77 | #define ETH_JUMBO_MTU 9000 | |
78 | #define TX_WATCHDOG (5 * HZ) | |
79 | #define NAPI_WEIGHT 64 | |
80 | #define PHY_RETRIES 1000 | |
81 | ||
82 | static const u32 default_msg = | |
793b883e SH |
83 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
84 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
3be92a70 | 85 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
cd28ab6a | 86 | |
793b883e | 87 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
88 | module_param(debug, int, 0); |
89 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
90 | ||
bdb5c58e SH |
91 | static int copybreak __read_mostly = 256; |
92 | module_param(copybreak, int, 0); | |
93 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
94 | ||
fb2690a9 SH |
95 | static int disable_msi = 0; |
96 | module_param(disable_msi, int, 0); | |
97 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
98 | ||
cd28ab6a | 99 | static const struct pci_device_id sky2_id_table[] = { |
793b883e | 100 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
cd28ab6a | 101 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
cd28ab6a SH |
102 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, |
103 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | |
104 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | |
105 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, | |
106 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, | |
107 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, | |
108 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | |
5a5b1ea0 | 112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, |
cd28ab6a SH |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | |
5a5b1ea0 | 116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, |
cd28ab6a SH |
117 | { 0 } |
118 | }; | |
793b883e | 119 | |
cd28ab6a SH |
120 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
121 | ||
122 | /* Avoid conditionals by using array */ | |
123 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
124 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
125 | ||
92f965e8 SH |
126 | /* This driver supports yukon2 chipset only */ |
127 | static const char *yukon2_name[] = { | |
128 | "XL", /* 0xb3 */ | |
129 | "EC Ultra", /* 0xb4 */ | |
130 | "UNKNOWN", /* 0xb5 */ | |
131 | "EC", /* 0xb6 */ | |
132 | "FE", /* 0xb7 */ | |
793b883e SH |
133 | }; |
134 | ||
793b883e | 135 | /* Access to external PHY */ |
ef743d33 | 136 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
137 | { |
138 | int i; | |
139 | ||
140 | gma_write16(hw, port, GM_SMI_DATA, val); | |
141 | gma_write16(hw, port, GM_SMI_CTRL, | |
142 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
143 | ||
144 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 145 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
ef743d33 | 146 | return 0; |
793b883e | 147 | udelay(1); |
cd28ab6a | 148 | } |
ef743d33 | 149 | |
793b883e | 150 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 151 | return -ETIMEDOUT; |
cd28ab6a SH |
152 | } |
153 | ||
ef743d33 | 154 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
155 | { |
156 | int i; | |
157 | ||
793b883e | 158 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
159 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
160 | ||
161 | for (i = 0; i < PHY_RETRIES; i++) { | |
ef743d33 SH |
162 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { |
163 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
164 | return 0; | |
165 | } | |
166 | ||
793b883e | 167 | udelay(1); |
cd28ab6a SH |
168 | } |
169 | ||
ef743d33 SH |
170 | return -ETIMEDOUT; |
171 | } | |
172 | ||
173 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
174 | { | |
175 | u16 v; | |
176 | ||
177 | if (__gm_phy_read(hw, port, reg, &v) != 0) | |
178 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); | |
179 | return v; | |
cd28ab6a SH |
180 | } |
181 | ||
5afa0a9c SH |
182 | static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) |
183 | { | |
184 | u16 power_control; | |
185 | u32 reg1; | |
186 | int vaux; | |
187 | int ret = 0; | |
188 | ||
189 | pr_debug("sky2_set_power_state %d\n", state); | |
190 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
191 | ||
56a645cc | 192 | power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC); |
08c06d8a | 193 | vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && |
5afa0a9c SH |
194 | (power_control & PCI_PM_CAP_PME_D3cold); |
195 | ||
56a645cc | 196 | power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL); |
5afa0a9c SH |
197 | |
198 | power_control |= PCI_PM_CTRL_PME_STATUS; | |
199 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); | |
200 | ||
201 | switch (state) { | |
202 | case PCI_D0: | |
203 | /* switch power to VCC (WA for VAUX problem) */ | |
204 | sky2_write8(hw, B0_POWER_CTRL, | |
205 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
206 | ||
207 | /* disable Core Clock Division, */ | |
208 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
209 | ||
210 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
211 | /* enable bits are inverted */ | |
212 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
213 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
214 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
215 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
216 | else | |
217 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
218 | ||
219 | /* Turn off phy power saving */ | |
56a645cc | 220 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
5afa0a9c SH |
221 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); |
222 | ||
d571b694 | 223 | /* looks like this XL is back asswards .. */ |
5afa0a9c SH |
224 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { |
225 | reg1 |= PCI_Y2_PHY1_COMA; | |
226 | if (hw->ports > 1) | |
227 | reg1 |= PCI_Y2_PHY2_COMA; | |
228 | } | |
977bdf06 SH |
229 | |
230 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
56a645cc SH |
231 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
232 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); | |
977bdf06 | 233 | reg1 &= P_ASPM_CONTROL_MSK; |
56a645cc SH |
234 | sky2_pci_write32(hw, PCI_DEV_REG4, reg1); |
235 | sky2_pci_write32(hw, PCI_DEV_REG5, 0); | |
977bdf06 SH |
236 | } |
237 | ||
56a645cc | 238 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
977bdf06 | 239 | |
5afa0a9c SH |
240 | break; |
241 | ||
242 | case PCI_D3hot: | |
243 | case PCI_D3cold: | |
244 | /* Turn on phy power saving */ | |
56a645cc | 245 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
5afa0a9c SH |
246 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
247 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
248 | else | |
249 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
56a645cc | 250 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
5afa0a9c SH |
251 | |
252 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
253 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
254 | else | |
255 | /* enable bits are inverted */ | |
256 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
257 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
258 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
259 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
260 | ||
261 | /* switch power to VAUX */ | |
262 | if (vaux && state != PCI_D3cold) | |
263 | sky2_write8(hw, B0_POWER_CTRL, | |
264 | (PC_VAUX_ENA | PC_VCC_ENA | | |
265 | PC_VAUX_ON | PC_VCC_OFF)); | |
266 | break; | |
267 | default: | |
268 | printk(KERN_ERR PFX "Unknown power state %d\n", state); | |
269 | ret = -1; | |
270 | } | |
271 | ||
56a645cc | 272 | sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control); |
5afa0a9c SH |
273 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
274 | return ret; | |
275 | } | |
276 | ||
cd28ab6a SH |
277 | static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) |
278 | { | |
279 | u16 reg; | |
280 | ||
281 | /* disable all GMAC IRQ's */ | |
282 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
283 | /* disable PHY IRQs */ | |
284 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 285 | |
cd28ab6a SH |
286 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
287 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
288 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
289 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
290 | ||
291 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
292 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
293 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
294 | } | |
295 | ||
296 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |
297 | { | |
298 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
793b883e | 299 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; |
cd28ab6a | 300 | |
793b883e | 301 | if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) { |
cd28ab6a SH |
302 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
303 | ||
304 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 305 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
306 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
307 | ||
308 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
309 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; | |
310 | else | |
311 | ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); | |
312 | ||
313 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
314 | } | |
315 | ||
316 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
317 | if (hw->copper) { | |
318 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
319 | /* enable automatic crossover */ | |
320 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
321 | } else { | |
322 | /* disable energy detect */ | |
323 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
324 | ||
325 | /* enable automatic crossover */ | |
326 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
327 | ||
328 | if (sky2->autoneg == AUTONEG_ENABLE && | |
329 | hw->chip_id == CHIP_ID_YUKON_XL) { | |
330 | ctrl &= ~PHY_M_PC_DSC_MSK; | |
331 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
332 | } | |
333 | } | |
334 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
335 | } else { | |
336 | /* workaround for deviation #4.88 (CRC errors) */ | |
337 | /* disable Automatic Crossover */ | |
338 | ||
339 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
340 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
341 | ||
342 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | |
343 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | |
344 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
345 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
346 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
347 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
348 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
349 | ||
350 | /* select page 1 to access Fiber registers */ | |
351 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
352 | } | |
cd28ab6a SH |
353 | } |
354 | ||
355 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
356 | if (sky2->autoneg == AUTONEG_DISABLE) | |
357 | ctrl &= ~PHY_CT_ANE; | |
358 | else | |
359 | ctrl |= PHY_CT_ANE; | |
360 | ||
361 | ctrl |= PHY_CT_RESET; | |
362 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
363 | ||
364 | ctrl = 0; | |
365 | ct1000 = 0; | |
366 | adv = PHY_AN_CSMA; | |
367 | ||
368 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
369 | if (hw->copper) { | |
370 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
371 | ct1000 |= PHY_M_1000C_AFD; | |
372 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
373 | ct1000 |= PHY_M_1000C_AHD; | |
374 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
375 | adv |= PHY_M_AN_100_FD; | |
376 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
377 | adv |= PHY_M_AN_100_HD; | |
378 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
379 | adv |= PHY_M_AN_10_FD; | |
380 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
381 | adv |= PHY_M_AN_10_HD; | |
793b883e | 382 | } else /* special defines for FIBER (88E1011S only) */ |
cd28ab6a SH |
383 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
384 | ||
385 | /* Set Flow-control capabilities */ | |
386 | if (sky2->tx_pause && sky2->rx_pause) | |
793b883e | 387 | adv |= PHY_AN_PAUSE_CAP; /* symmetric */ |
cd28ab6a | 388 | else if (sky2->rx_pause && !sky2->tx_pause) |
793b883e | 389 | adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; |
cd28ab6a SH |
390 | else if (!sky2->rx_pause && sky2->tx_pause) |
391 | adv |= PHY_AN_PAUSE_ASYM; /* local */ | |
392 | ||
393 | /* Restart Auto-negotiation */ | |
394 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
395 | } else { | |
396 | /* forced speed/duplex settings */ | |
397 | ct1000 = PHY_M_1000C_MSE; | |
398 | ||
399 | if (sky2->duplex == DUPLEX_FULL) | |
400 | ctrl |= PHY_CT_DUP_MD; | |
401 | ||
402 | switch (sky2->speed) { | |
403 | case SPEED_1000: | |
404 | ctrl |= PHY_CT_SP1000; | |
405 | break; | |
406 | case SPEED_100: | |
407 | ctrl |= PHY_CT_SP100; | |
408 | break; | |
409 | } | |
410 | ||
411 | ctrl |= PHY_CT_RESET; | |
412 | } | |
413 | ||
414 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
415 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
416 | ||
417 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
418 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
419 | ||
420 | /* Setup Phy LED's */ | |
421 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
422 | ledover = 0; | |
423 | ||
424 | switch (hw->chip_id) { | |
425 | case CHIP_ID_YUKON_FE: | |
426 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
427 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
428 | ||
429 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
430 | ||
431 | /* delete ACT LED control bits */ | |
432 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
433 | /* change ACT LED control to blink mode */ | |
434 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
435 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
436 | break; | |
437 | ||
438 | case CHIP_ID_YUKON_XL: | |
793b883e | 439 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
440 | |
441 | /* select page 3 to access LED control register */ | |
442 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
443 | ||
444 | /* set LED Function Control register */ | |
793b883e SH |
445 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ |
446 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
447 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
448 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
449 | |
450 | /* set Polarity Control register */ | |
451 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
452 | (PHY_M_POLC_LS1_P_MIX(4) | |
453 | PHY_M_POLC_IS0_P_MIX(4) | | |
454 | PHY_M_POLC_LOS_CTRL(2) | | |
455 | PHY_M_POLC_INIT_CTRL(2) | | |
456 | PHY_M_POLC_STA1_CTRL(2) | | |
457 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
458 | |
459 | /* restore page register */ | |
793b883e | 460 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a SH |
461 | break; |
462 | ||
463 | default: | |
464 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
465 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
466 | /* turn off the Rx LED (LED_RX) */ | |
467 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
468 | } | |
469 | ||
977bdf06 SH |
470 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { |
471 | /* apply fixes in PHY AFE */ | |
472 | gm_phy_write(hw, port, 22, 255); | |
473 | /* increase differential signal amplitude in 10BASE-T */ | |
474 | gm_phy_write(hw, port, 24, 0xaa99); | |
475 | gm_phy_write(hw, port, 23, 0x2011); | |
cd28ab6a | 476 | |
977bdf06 SH |
477 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ |
478 | gm_phy_write(hw, port, 24, 0xa204); | |
479 | gm_phy_write(hw, port, 23, 0x2002); | |
480 | ||
481 | /* set page register to 0 */ | |
482 | gm_phy_write(hw, port, 22, 0); | |
483 | } else { | |
484 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
cd28ab6a | 485 | |
977bdf06 SH |
486 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { |
487 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
488 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
489 | } | |
cd28ab6a | 490 | |
977bdf06 SH |
491 | if (ledover) |
492 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
493 | ||
494 | } | |
d571b694 | 495 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
cd28ab6a SH |
496 | if (sky2->autoneg == AUTONEG_ENABLE) |
497 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
498 | else | |
499 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
500 | } | |
501 | ||
1b537565 SH |
502 | /* Force a renegotiation */ |
503 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
504 | { | |
e07b1aa8 | 505 | spin_lock_bh(&sky2->phy_lock); |
1b537565 | 506 | sky2_phy_init(sky2->hw, sky2->port); |
e07b1aa8 | 507 | spin_unlock_bh(&sky2->phy_lock); |
1b537565 SH |
508 | } |
509 | ||
cd28ab6a SH |
510 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
511 | { | |
512 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
513 | u16 reg; | |
514 | int i; | |
515 | const u8 *addr = hw->dev[port]->dev_addr; | |
516 | ||
42eeea01 SH |
517 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
518 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); | |
cd28ab6a SH |
519 | |
520 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
521 | ||
793b883e | 522 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
523 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
524 | /* clear GMAC 1 Control reset */ | |
525 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
526 | do { | |
527 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
528 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
529 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
530 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
531 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
532 | } | |
533 | ||
cd28ab6a SH |
534 | if (sky2->autoneg == AUTONEG_DISABLE) { |
535 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
536 | reg |= GM_GPCR_AU_ALL_DIS; | |
537 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
538 | gma_read16(hw, port, GM_GP_CTRL); | |
539 | ||
cd28ab6a SH |
540 | switch (sky2->speed) { |
541 | case SPEED_1000: | |
6f4c56b2 | 542 | reg &= ~GM_GPCR_SPEED_100; |
cd28ab6a | 543 | reg |= GM_GPCR_SPEED_1000; |
6f4c56b2 | 544 | break; |
cd28ab6a | 545 | case SPEED_100: |
6f4c56b2 | 546 | reg &= ~GM_GPCR_SPEED_1000; |
cd28ab6a | 547 | reg |= GM_GPCR_SPEED_100; |
6f4c56b2 SH |
548 | break; |
549 | case SPEED_10: | |
550 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
551 | break; | |
cd28ab6a SH |
552 | } |
553 | ||
554 | if (sky2->duplex == DUPLEX_FULL) | |
555 | reg |= GM_GPCR_DUP_FULL; | |
556 | } else | |
557 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
558 | ||
559 | if (!sky2->tx_pause && !sky2->rx_pause) { | |
560 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e SH |
561 | reg |= |
562 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
563 | } else if (sky2->tx_pause && !sky2->rx_pause) { | |
cd28ab6a SH |
564 | /* disable Rx flow-control */ |
565 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
566 | } | |
567 | ||
568 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
569 | ||
793b883e | 570 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 571 | |
e07b1aa8 | 572 | spin_lock_bh(&sky2->phy_lock); |
cd28ab6a | 573 | sky2_phy_init(hw, port); |
e07b1aa8 | 574 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
575 | |
576 | /* MIB clear */ | |
577 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
578 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
579 | ||
43f2f104 SH |
580 | for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) |
581 | gma_read16(hw, port, i); | |
cd28ab6a SH |
582 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
583 | ||
584 | /* transmit control */ | |
585 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
586 | ||
587 | /* receive control reg: unicast + multicast + no FCS */ | |
588 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 589 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
590 | |
591 | /* transmit flow control */ | |
592 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
593 | ||
594 | /* transmit parameter */ | |
595 | gma_write16(hw, port, GM_TX_PARAM, | |
596 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
597 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
598 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
599 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
600 | ||
601 | /* serial mode register */ | |
602 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 603 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 604 | |
6b1a3aef | 605 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
606 | reg |= GM_SMOD_JUMBO_ENA; |
607 | ||
608 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
609 | ||
cd28ab6a SH |
610 | /* virtual address for data */ |
611 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
612 | ||
793b883e SH |
613 | /* physical address: used for pause frames */ |
614 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
615 | ||
616 | /* ignore counter overflows */ | |
cd28ab6a SH |
617 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
618 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
619 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
620 | ||
621 | /* Configure Rx MAC FIFO */ | |
622 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
70f1be48 SH |
623 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), |
624 | GMF_OPER_ON | GMF_RX_F_FL_ON); | |
cd28ab6a | 625 | |
d571b694 | 626 | /* Flush Rx MAC FIFO on any flow control or error */ |
42eeea01 | 627 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
cd28ab6a | 628 | |
793b883e SH |
629 | /* Set threshold to 0xa (64 bytes) |
630 | * ASF disabled so no need to do WA dev #4.30 | |
cd28ab6a SH |
631 | */ |
632 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
633 | ||
634 | /* Configure Tx MAC FIFO */ | |
635 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
636 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 SH |
637 | |
638 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
639 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); | |
640 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); | |
641 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | |
642 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
643 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); | |
644 | /* Disable Store & Forward mode for TX */ | |
645 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); | |
646 | } | |
647 | } | |
648 | ||
cd28ab6a SH |
649 | } |
650 | ||
1c28f6ba SH |
651 | /* Assign Ram Buffer allocation. |
652 | * start and end are in units of 4k bytes | |
653 | * ram registers are in units of 64bit words | |
654 | */ | |
655 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) | |
cd28ab6a | 656 | { |
1c28f6ba | 657 | u32 start, end; |
cd28ab6a | 658 | |
1c28f6ba SH |
659 | start = startk * 4096/8; |
660 | end = (endk * 4096/8) - 1; | |
793b883e | 661 | |
cd28ab6a SH |
662 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
663 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
664 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
665 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
666 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
667 | ||
668 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba SH |
669 | u32 space = (endk - startk) * 4096/8; |
670 | u32 tp = space - space/4; | |
793b883e | 671 | |
1c28f6ba SH |
672 | /* On receive queue's set the thresholds |
673 | * give receiver priority when > 3/4 full | |
674 | * send pause when down to 2K | |
675 | */ | |
676 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
677 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 678 | |
1c28f6ba SH |
679 | tp = space - 2048/8; |
680 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); | |
681 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
682 | } else { |
683 | /* Enable store & forward on Tx queue's because | |
684 | * Tx FIFO is only 1K on Yukon | |
685 | */ | |
686 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
687 | } | |
688 | ||
689 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 690 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
691 | } |
692 | ||
cd28ab6a | 693 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 694 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
695 | { |
696 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
697 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
698 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 699 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
700 | } |
701 | ||
cd28ab6a SH |
702 | /* Setup prefetch unit registers. This is the interface between |
703 | * hardware and driver list elements | |
704 | */ | |
8cc048e3 | 705 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
cd28ab6a SH |
706 | u64 addr, u32 last) |
707 | { | |
cd28ab6a SH |
708 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
709 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
710 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
711 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
712 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
713 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
714 | |
715 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
716 | } |
717 | ||
793b883e SH |
718 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
719 | { | |
720 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
721 | ||
722 | sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE; | |
723 | return le; | |
724 | } | |
cd28ab6a | 725 | |
290d4de5 SH |
726 | /* Update chip's next pointer */ |
727 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) | |
cd28ab6a | 728 | { |
762c2de2 | 729 | wmb(); |
290d4de5 | 730 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
762c2de2 | 731 | mmiowb(); |
cd28ab6a SH |
732 | } |
733 | ||
793b883e | 734 | |
cd28ab6a SH |
735 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
736 | { | |
737 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
738 | sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE; | |
739 | return le; | |
740 | } | |
741 | ||
a018e330 SH |
742 | /* Return high part of DMA address (could be 32 or 64 bit) */ |
743 | static inline u32 high32(dma_addr_t a) | |
744 | { | |
a036119f | 745 | return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0; |
a018e330 SH |
746 | } |
747 | ||
793b883e | 748 | /* Build description to hardware about buffer */ |
28bd181a | 749 | static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map) |
cd28ab6a SH |
750 | { |
751 | struct sky2_rx_le *le; | |
734d1868 SH |
752 | u32 hi = high32(map); |
753 | u16 len = sky2->rx_bufsize; | |
cd28ab6a | 754 | |
793b883e | 755 | if (sky2->rx_addr64 != hi) { |
cd28ab6a | 756 | le = sky2_next_rx(sky2); |
793b883e | 757 | le->addr = cpu_to_le32(hi); |
cd28ab6a SH |
758 | le->ctrl = 0; |
759 | le->opcode = OP_ADDR64 | HW_OWNER; | |
734d1868 | 760 | sky2->rx_addr64 = high32(map + len); |
cd28ab6a | 761 | } |
793b883e | 762 | |
cd28ab6a | 763 | le = sky2_next_rx(sky2); |
734d1868 SH |
764 | le->addr = cpu_to_le32((u32) map); |
765 | le->length = cpu_to_le16(len); | |
cd28ab6a SH |
766 | le->ctrl = 0; |
767 | le->opcode = OP_PACKET | HW_OWNER; | |
768 | } | |
769 | ||
793b883e | 770 | |
cd28ab6a SH |
771 | /* Tell chip where to start receive checksum. |
772 | * Actually has two checksums, but set both same to avoid possible byte | |
773 | * order problems. | |
774 | */ | |
793b883e | 775 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a SH |
776 | { |
777 | struct sky2_rx_le *le; | |
778 | ||
cd28ab6a | 779 | le = sky2_next_rx(sky2); |
793b883e | 780 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; |
cd28ab6a SH |
781 | le->ctrl = 0; |
782 | le->opcode = OP_TCPSTART | HW_OWNER; | |
793b883e | 783 | |
793b883e SH |
784 | sky2_write32(sky2->hw, |
785 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
786 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
787 | |
788 | } | |
789 | ||
6b1a3aef SH |
790 | /* |
791 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
792 | * reach the end of packet and since we can't make sure that we have | |
793 | * incoming data, we must reset the BMU while it is not doing a DMA | |
794 | * transfer. Since it is possible that the RX path is still active, | |
795 | * the RX RAM buffer will be stopped first, so any possible incoming | |
796 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
797 | * BMU is polled until any DMA in progress is ended and only then it | |
798 | * will be reset. | |
799 | */ | |
800 | static void sky2_rx_stop(struct sky2_port *sky2) | |
801 | { | |
802 | struct sky2_hw *hw = sky2->hw; | |
803 | unsigned rxq = rxqaddr[sky2->port]; | |
804 | int i; | |
805 | ||
806 | /* disable the RAM Buffer receive queue */ | |
807 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
808 | ||
809 | for (i = 0; i < 0xffff; i++) | |
810 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
811 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
812 | goto stopped; | |
813 | ||
814 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
815 | sky2->netdev->name); | |
816 | stopped: | |
817 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
818 | ||
819 | /* reset the Rx prefetch unit */ | |
820 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
821 | } | |
793b883e | 822 | |
d571b694 | 823 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
824 | static void sky2_rx_clean(struct sky2_port *sky2) |
825 | { | |
826 | unsigned i; | |
827 | ||
828 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 829 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a SH |
830 | struct ring_info *re = sky2->rx_ring + i; |
831 | ||
832 | if (re->skb) { | |
793b883e | 833 | pci_unmap_single(sky2->hw->pdev, |
734d1868 | 834 | re->mapaddr, sky2->rx_bufsize, |
cd28ab6a SH |
835 | PCI_DMA_FROMDEVICE); |
836 | kfree_skb(re->skb); | |
837 | re->skb = NULL; | |
838 | } | |
839 | } | |
840 | } | |
841 | ||
ef743d33 SH |
842 | /* Basic MII support */ |
843 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
844 | { | |
845 | struct mii_ioctl_data *data = if_mii(ifr); | |
846 | struct sky2_port *sky2 = netdev_priv(dev); | |
847 | struct sky2_hw *hw = sky2->hw; | |
848 | int err = -EOPNOTSUPP; | |
849 | ||
850 | if (!netif_running(dev)) | |
851 | return -ENODEV; /* Phy still in reset */ | |
852 | ||
d89e1343 | 853 | switch (cmd) { |
ef743d33 SH |
854 | case SIOCGMIIPHY: |
855 | data->phy_id = PHY_ADDR_MARV; | |
856 | ||
857 | /* fallthru */ | |
858 | case SIOCGMIIREG: { | |
859 | u16 val = 0; | |
91c86df5 | 860 | |
e07b1aa8 | 861 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 | 862 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
e07b1aa8 | 863 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 864 | |
ef743d33 SH |
865 | data->val_out = val; |
866 | break; | |
867 | } | |
868 | ||
869 | case SIOCSMIIREG: | |
870 | if (!capable(CAP_NET_ADMIN)) | |
871 | return -EPERM; | |
872 | ||
e07b1aa8 | 873 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 SH |
874 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
875 | data->val_in); | |
e07b1aa8 | 876 | spin_unlock_bh(&sky2->phy_lock); |
ef743d33 SH |
877 | break; |
878 | } | |
879 | return err; | |
880 | } | |
881 | ||
d1f13708 SH |
882 | #ifdef SKY2_VLAN_TAG_USED |
883 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
884 | { | |
885 | struct sky2_port *sky2 = netdev_priv(dev); | |
886 | struct sky2_hw *hw = sky2->hw; | |
887 | u16 port = sky2->port; | |
d1f13708 | 888 | |
302d1252 | 889 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 SH |
890 | |
891 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); | |
892 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); | |
893 | sky2->vlgrp = grp; | |
894 | ||
302d1252 | 895 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 SH |
896 | } |
897 | ||
898 | static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
899 | { | |
900 | struct sky2_port *sky2 = netdev_priv(dev); | |
901 | struct sky2_hw *hw = sky2->hw; | |
902 | u16 port = sky2->port; | |
d1f13708 | 903 | |
302d1252 | 904 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 SH |
905 | |
906 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); | |
907 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); | |
908 | if (sky2->vlgrp) | |
909 | sky2->vlgrp->vlan_devices[vid] = NULL; | |
910 | ||
302d1252 | 911 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 SH |
912 | } |
913 | #endif | |
914 | ||
82788c7a SH |
915 | /* |
916 | * It appears the hardware has a bug in the FIFO logic that | |
917 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
918 | * is not aligned. ALso alloc_skb() won't align properly if slab | |
919 | * debugging is enabled. | |
920 | */ | |
921 | static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask) | |
922 | { | |
923 | struct sk_buff *skb; | |
924 | ||
925 | skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask); | |
926 | if (likely(skb)) { | |
927 | unsigned long p = (unsigned long) skb->data; | |
4a15d56f | 928 | skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); |
82788c7a SH |
929 | } |
930 | ||
931 | return skb; | |
932 | } | |
933 | ||
cd28ab6a SH |
934 | /* |
935 | * Allocate and setup receiver buffer pool. | |
936 | * In case of 64 bit dma, there are 2X as many list elements | |
937 | * available as ring entries | |
938 | * and need to reserve one list element so we don't wrap around. | |
939 | */ | |
6b1a3aef | 940 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 941 | { |
6b1a3aef | 942 | struct sky2_hw *hw = sky2->hw; |
6b1a3aef SH |
943 | unsigned rxq = rxqaddr[sky2->port]; |
944 | int i; | |
cd28ab6a | 945 | |
6b1a3aef | 946 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 947 | sky2_qset(hw, rxq); |
977bdf06 SH |
948 | |
949 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { | |
950 | /* MAC Rx RAM Read is controlled by hardware */ | |
951 | sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); | |
952 | } | |
953 | ||
6b1a3aef SH |
954 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
955 | ||
956 | rx_set_checksum(sky2); | |
793b883e | 957 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a | 958 | struct ring_info *re = sky2->rx_ring + i; |
cd28ab6a | 959 | |
82788c7a | 960 | re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL); |
cd28ab6a SH |
961 | if (!re->skb) |
962 | goto nomem; | |
963 | ||
6b1a3aef | 964 | re->mapaddr = pci_map_single(hw->pdev, re->skb->data, |
734d1868 SH |
965 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
966 | sky2_rx_add(sky2, re->mapaddr); | |
cd28ab6a SH |
967 | } |
968 | ||
70f1be48 SH |
969 | /* Truncate oversize frames */ |
970 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8); | |
971 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); | |
972 | ||
6b1a3aef SH |
973 | /* Tell chip about available buffers */ |
974 | sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); | |
cd28ab6a SH |
975 | return 0; |
976 | nomem: | |
977 | sky2_rx_clean(sky2); | |
978 | return -ENOMEM; | |
979 | } | |
980 | ||
981 | /* Bring up network interface. */ | |
982 | static int sky2_up(struct net_device *dev) | |
983 | { | |
984 | struct sky2_port *sky2 = netdev_priv(dev); | |
985 | struct sky2_hw *hw = sky2->hw; | |
986 | unsigned port = sky2->port; | |
e07b1aa8 | 987 | u32 ramsize, rxspace, imask; |
cd28ab6a SH |
988 | int err = -ENOMEM; |
989 | ||
990 | if (netif_msg_ifup(sky2)) | |
991 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
992 | ||
993 | /* must be power of 2 */ | |
994 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
995 | TX_RING_SIZE * |
996 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
997 | &sky2->tx_le_map); |
998 | if (!sky2->tx_le) | |
999 | goto err_out; | |
1000 | ||
6cdbbdf3 | 1001 | sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), |
cd28ab6a SH |
1002 | GFP_KERNEL); |
1003 | if (!sky2->tx_ring) | |
1004 | goto err_out; | |
1005 | sky2->tx_prod = sky2->tx_cons = 0; | |
cd28ab6a SH |
1006 | |
1007 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
1008 | &sky2->rx_le_map); | |
1009 | if (!sky2->rx_le) | |
1010 | goto err_out; | |
1011 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1012 | ||
6cdbbdf3 | 1013 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info), |
cd28ab6a SH |
1014 | GFP_KERNEL); |
1015 | if (!sky2->rx_ring) | |
1016 | goto err_out; | |
1017 | ||
1018 | sky2_mac_init(hw, port); | |
1019 | ||
1c28f6ba SH |
1020 | /* Determine available ram buffer space (in 4K blocks). |
1021 | * Note: not sure about the FE setting below yet | |
1022 | */ | |
1023 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
1024 | ramsize = 4; | |
1025 | else | |
1026 | ramsize = sky2_read8(hw, B2_E_0); | |
1027 | ||
1028 | /* Give transmitter one third (rounded up) */ | |
1029 | rxspace = ramsize - (ramsize + 2) / 3; | |
cd28ab6a | 1030 | |
cd28ab6a | 1031 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1c28f6ba | 1032 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize); |
cd28ab6a | 1033 | |
793b883e SH |
1034 | /* Make sure SyncQ is disabled */ |
1035 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1036 | RB_RST_SET); | |
1037 | ||
af4ed7e6 | 1038 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 | 1039 | |
977bdf06 SH |
1040 | /* Set almost empty threshold */ |
1041 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1) | |
1042 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | |
5a5b1ea0 | 1043 | |
6b1a3aef SH |
1044 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1045 | TX_RING_SIZE - 1); | |
cd28ab6a | 1046 | |
6b1a3aef | 1047 | err = sky2_rx_start(sky2); |
cd28ab6a SH |
1048 | if (err) |
1049 | goto err_out; | |
1050 | ||
cd28ab6a | 1051 | /* Enable interrupts from phy/mac for port */ |
e07b1aa8 SH |
1052 | imask = sky2_read32(hw, B0_IMSK); |
1053 | imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; | |
1054 | sky2_write32(hw, B0_IMSK, imask); | |
1055 | ||
cd28ab6a SH |
1056 | return 0; |
1057 | ||
1058 | err_out: | |
1b537565 | 1059 | if (sky2->rx_le) { |
cd28ab6a SH |
1060 | pci_free_consistent(hw->pdev, RX_LE_BYTES, |
1061 | sky2->rx_le, sky2->rx_le_map); | |
1b537565 SH |
1062 | sky2->rx_le = NULL; |
1063 | } | |
1064 | if (sky2->tx_le) { | |
cd28ab6a SH |
1065 | pci_free_consistent(hw->pdev, |
1066 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1067 | sky2->tx_le, sky2->tx_le_map); | |
1b537565 SH |
1068 | sky2->tx_le = NULL; |
1069 | } | |
1070 | kfree(sky2->tx_ring); | |
1071 | kfree(sky2->rx_ring); | |
cd28ab6a | 1072 | |
1b537565 SH |
1073 | sky2->tx_ring = NULL; |
1074 | sky2->rx_ring = NULL; | |
cd28ab6a SH |
1075 | return err; |
1076 | } | |
1077 | ||
793b883e SH |
1078 | /* Modular subtraction in ring */ |
1079 | static inline int tx_dist(unsigned tail, unsigned head) | |
1080 | { | |
129372d0 | 1081 | return (head - tail) % TX_RING_SIZE; |
793b883e | 1082 | } |
cd28ab6a | 1083 | |
793b883e SH |
1084 | /* Number of list elements available for next tx */ |
1085 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1086 | { |
793b883e | 1087 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
1088 | } |
1089 | ||
793b883e | 1090 | /* Estimate of number of transmit list elements required */ |
28bd181a | 1091 | static unsigned tx_le_req(const struct sk_buff *skb) |
cd28ab6a | 1092 | { |
793b883e SH |
1093 | unsigned count; |
1094 | ||
1095 | count = sizeof(dma_addr_t) / sizeof(u32); | |
1096 | count += skb_shinfo(skb)->nr_frags * count; | |
1097 | ||
1098 | if (skb_shinfo(skb)->tso_size) | |
1099 | ++count; | |
1100 | ||
0e3ff6aa | 1101 | if (skb->ip_summed == CHECKSUM_HW) |
793b883e SH |
1102 | ++count; |
1103 | ||
1104 | return count; | |
cd28ab6a SH |
1105 | } |
1106 | ||
793b883e SH |
1107 | /* |
1108 | * Put one packet in ring for transmit. | |
1109 | * A single packet can generate multiple list elements, and | |
1110 | * the number of ring elements will probably be less than the number | |
1111 | * of list elements used. | |
f2e46561 SH |
1112 | * |
1113 | * No BH disabling for tx_lock here (like tg3) | |
793b883e | 1114 | */ |
cd28ab6a SH |
1115 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
1116 | { | |
1117 | struct sky2_port *sky2 = netdev_priv(dev); | |
1118 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1119 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1120 | struct tx_ring_info *re; |
cd28ab6a | 1121 | unsigned i, len; |
b19666d9 | 1122 | int avail; |
cd28ab6a SH |
1123 | dma_addr_t mapping; |
1124 | u32 addr64; | |
1125 | u16 mss; | |
1126 | u8 ctrl; | |
1127 | ||
302d1252 SH |
1128 | /* No BH disabling for tx_lock here. We are running in BH disabled |
1129 | * context and TX reclaim runs via poll inside of a software | |
1130 | * interrupt, and no related locks in IRQ processing. | |
1131 | */ | |
f2e46561 | 1132 | if (!spin_trylock(&sky2->tx_lock)) |
cd28ab6a SH |
1133 | return NETDEV_TX_LOCKED; |
1134 | ||
793b883e | 1135 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { |
8c463ef7 SH |
1136 | /* There is a known but harmless race with lockless tx |
1137 | * and netif_stop_queue. | |
1138 | */ | |
1139 | if (!netif_queue_stopped(dev)) { | |
1140 | netif_stop_queue(dev); | |
3be92a70 SH |
1141 | if (net_ratelimit()) |
1142 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
1143 | dev->name); | |
8c463ef7 | 1144 | } |
f2e46561 | 1145 | spin_unlock(&sky2->tx_lock); |
cd28ab6a | 1146 | |
cd28ab6a SH |
1147 | return NETDEV_TX_BUSY; |
1148 | } | |
1149 | ||
793b883e | 1150 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
1151 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
1152 | dev->name, sky2->tx_prod, skb->len); | |
1153 | ||
cd28ab6a SH |
1154 | len = skb_headlen(skb); |
1155 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
a018e330 | 1156 | addr64 = high32(mapping); |
793b883e SH |
1157 | |
1158 | re = sky2->tx_ring + sky2->tx_prod; | |
1159 | ||
a018e330 SH |
1160 | /* Send high bits if changed or crosses boundary */ |
1161 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { | |
793b883e SH |
1162 | le = get_tx_le(sky2); |
1163 | le->tx.addr = cpu_to_le32(addr64); | |
1164 | le->ctrl = 0; | |
1165 | le->opcode = OP_ADDR64 | HW_OWNER; | |
a018e330 | 1166 | sky2->tx_addr64 = high32(mapping + len); |
793b883e | 1167 | } |
cd28ab6a SH |
1168 | |
1169 | /* Check for TCP Segmentation Offload */ | |
1170 | mss = skb_shinfo(skb)->tso_size; | |
793b883e | 1171 | if (mss != 0) { |
cd28ab6a SH |
1172 | /* just drop the packet if non-linear expansion fails */ |
1173 | if (skb_header_cloned(skb) && | |
1174 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
15240072 | 1175 | dev_kfree_skb(skb); |
793b883e | 1176 | goto out_unlock; |
cd28ab6a SH |
1177 | } |
1178 | ||
1179 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ | |
1180 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | |
1181 | mss += ETH_HLEN; | |
793b883e | 1182 | } |
cd28ab6a | 1183 | |
793b883e | 1184 | if (mss != sky2->tx_last_mss) { |
cd28ab6a SH |
1185 | le = get_tx_le(sky2); |
1186 | le->tx.tso.size = cpu_to_le16(mss); | |
793b883e | 1187 | le->tx.tso.rsvd = 0; |
cd28ab6a | 1188 | le->opcode = OP_LRGLEN | HW_OWNER; |
cd28ab6a | 1189 | le->ctrl = 0; |
793b883e | 1190 | sky2->tx_last_mss = mss; |
cd28ab6a SH |
1191 | } |
1192 | ||
cd28ab6a | 1193 | ctrl = 0; |
d1f13708 SH |
1194 | #ifdef SKY2_VLAN_TAG_USED |
1195 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ | |
1196 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | |
1197 | if (!le) { | |
1198 | le = get_tx_le(sky2); | |
1199 | le->tx.addr = 0; | |
1200 | le->opcode = OP_VLAN|HW_OWNER; | |
1201 | le->ctrl = 0; | |
1202 | } else | |
1203 | le->opcode |= OP_VLAN; | |
1204 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1205 | ctrl |= INS_VLAN; | |
1206 | } | |
1207 | #endif | |
1208 | ||
1209 | /* Handle TCP checksum offload */ | |
cd28ab6a | 1210 | if (skb->ip_summed == CHECKSUM_HW) { |
793b883e SH |
1211 | u16 hdr = skb->h.raw - skb->data; |
1212 | u16 offset = hdr + skb->csum; | |
cd28ab6a SH |
1213 | |
1214 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1215 | if (skb->nh.iph->protocol == IPPROTO_UDP) | |
1216 | ctrl |= UDPTCP; | |
1217 | ||
1218 | le = get_tx_le(sky2); | |
1219 | le->tx.csum.start = cpu_to_le16(hdr); | |
793b883e SH |
1220 | le->tx.csum.offset = cpu_to_le16(offset); |
1221 | le->length = 0; /* initial checksum value */ | |
cd28ab6a | 1222 | le->ctrl = 1; /* one packet */ |
793b883e | 1223 | le->opcode = OP_TCPLISW | HW_OWNER; |
cd28ab6a SH |
1224 | } |
1225 | ||
1226 | le = get_tx_le(sky2); | |
1227 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1228 | le->length = cpu_to_le16(len); | |
1229 | le->ctrl = ctrl; | |
793b883e | 1230 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1231 | |
793b883e | 1232 | /* Record the transmit mapping info */ |
cd28ab6a | 1233 | re->skb = skb; |
6cdbbdf3 | 1234 | pci_unmap_addr_set(re, mapaddr, mapping); |
cd28ab6a SH |
1235 | |
1236 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1237 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6cdbbdf3 | 1238 | struct tx_ring_info *fre; |
cd28ab6a SH |
1239 | |
1240 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1241 | frag->size, PCI_DMA_TODEVICE); | |
a036119f | 1242 | addr64 = high32(mapping); |
793b883e SH |
1243 | if (addr64 != sky2->tx_addr64) { |
1244 | le = get_tx_le(sky2); | |
1245 | le->tx.addr = cpu_to_le32(addr64); | |
1246 | le->ctrl = 0; | |
1247 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1248 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1249 | } |
1250 | ||
1251 | le = get_tx_le(sky2); | |
1252 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1253 | le->length = cpu_to_le16(frag->size); | |
1254 | le->ctrl = ctrl; | |
793b883e | 1255 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1256 | |
793b883e SH |
1257 | fre = sky2->tx_ring |
1258 | + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE; | |
6cdbbdf3 | 1259 | pci_unmap_addr_set(fre, mapaddr, mapping); |
cd28ab6a | 1260 | } |
6cdbbdf3 | 1261 | |
793b883e | 1262 | re->idx = sky2->tx_prod; |
cd28ab6a SH |
1263 | le->ctrl |= EOP; |
1264 | ||
b19666d9 SH |
1265 | avail = tx_avail(sky2); |
1266 | if (mss != 0 || avail < TX_MIN_PENDING) { | |
1267 | le->ctrl |= FRC_STAT; | |
1268 | if (avail <= MAX_SKB_TX_LE) | |
1269 | netif_stop_queue(dev); | |
1270 | } | |
1271 | ||
290d4de5 | 1272 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); |
cd28ab6a | 1273 | |
793b883e | 1274 | out_unlock: |
f2e46561 | 1275 | spin_unlock(&sky2->tx_lock); |
cd28ab6a SH |
1276 | |
1277 | dev->trans_start = jiffies; | |
1278 | return NETDEV_TX_OK; | |
1279 | } | |
1280 | ||
cd28ab6a | 1281 | /* |
793b883e SH |
1282 | * Free ring elements from starting at tx_cons until "done" |
1283 | * | |
1284 | * NB: the hardware will tell us about partial completion of multi-part | |
d571b694 | 1285 | * buffers; these are deferred until completion. |
cd28ab6a | 1286 | */ |
d11c13e7 | 1287 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1288 | { |
d11c13e7 | 1289 | struct net_device *dev = sky2->netdev; |
af2a58ac SH |
1290 | struct pci_dev *pdev = sky2->hw->pdev; |
1291 | u16 nxt, put; | |
793b883e | 1292 | unsigned i; |
cd28ab6a | 1293 | |
0e3ff6aa | 1294 | BUG_ON(done >= TX_RING_SIZE); |
2224795d | 1295 | |
d11c13e7 | 1296 | if (unlikely(netif_msg_tx_done(sky2))) |
d571b694 | 1297 | printk(KERN_DEBUG "%s: tx done, up to %u\n", |
d11c13e7 | 1298 | dev->name, done); |
cd28ab6a | 1299 | |
af2a58ac SH |
1300 | for (put = sky2->tx_cons; put != done; put = nxt) { |
1301 | struct tx_ring_info *re = sky2->tx_ring + put; | |
1302 | struct sk_buff *skb = re->skb; | |
cd28ab6a | 1303 | |
d89e1343 | 1304 | nxt = re->idx; |
af2a58ac | 1305 | BUG_ON(nxt >= TX_RING_SIZE); |
d70cd51a | 1306 | prefetch(sky2->tx_ring + nxt); |
cd28ab6a | 1307 | |
793b883e | 1308 | /* Check for partial status */ |
af2a58ac SH |
1309 | if (tx_dist(put, done) < tx_dist(put, nxt)) |
1310 | break; | |
793b883e SH |
1311 | |
1312 | skb = re->skb; | |
af2a58ac | 1313 | pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), |
734d1868 | 1314 | skb_headlen(skb), PCI_DMA_TODEVICE); |
793b883e SH |
1315 | |
1316 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6cdbbdf3 | 1317 | struct tx_ring_info *fre; |
af2a58ac SH |
1318 | fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE; |
1319 | pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), | |
d89e1343 | 1320 | skb_shinfo(skb)->frags[i].size, |
734d1868 | 1321 | PCI_DMA_TODEVICE); |
cd28ab6a SH |
1322 | } |
1323 | ||
15240072 | 1324 | dev_kfree_skb(skb); |
793b883e | 1325 | } |
793b883e | 1326 | |
af2a58ac | 1327 | sky2->tx_cons = put; |
8f24664d | 1328 | if (tx_avail(sky2) > MAX_SKB_TX_LE) |
cd28ab6a | 1329 | netif_wake_queue(dev); |
cd28ab6a SH |
1330 | } |
1331 | ||
1332 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
13b97b74 | 1333 | static void sky2_tx_clean(struct sky2_port *sky2) |
cd28ab6a | 1334 | { |
302d1252 | 1335 | spin_lock_bh(&sky2->tx_lock); |
d11c13e7 | 1336 | sky2_tx_complete(sky2, sky2->tx_prod); |
302d1252 | 1337 | spin_unlock_bh(&sky2->tx_lock); |
cd28ab6a SH |
1338 | } |
1339 | ||
1340 | /* Network shutdown */ | |
1341 | static int sky2_down(struct net_device *dev) | |
1342 | { | |
1343 | struct sky2_port *sky2 = netdev_priv(dev); | |
1344 | struct sky2_hw *hw = sky2->hw; | |
1345 | unsigned port = sky2->port; | |
1346 | u16 ctrl; | |
e07b1aa8 | 1347 | u32 imask; |
cd28ab6a | 1348 | |
1b537565 SH |
1349 | /* Never really got started! */ |
1350 | if (!sky2->tx_le) | |
1351 | return 0; | |
1352 | ||
cd28ab6a SH |
1353 | if (netif_msg_ifdown(sky2)) |
1354 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1355 | ||
018d1c66 | 1356 | /* Stop more packets from being queued */ |
cd28ab6a SH |
1357 | netif_stop_queue(dev); |
1358 | ||
793b883e SH |
1359 | sky2_phy_reset(hw, port); |
1360 | ||
cd28ab6a SH |
1361 | /* Stop transmitter */ |
1362 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1363 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1364 | ||
1365 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1366 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1367 | |
1368 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1369 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1370 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1371 | ||
1372 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1373 | ||
1374 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1375 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1376 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1377 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1378 | ||
1379 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1380 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1381 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1382 | ||
1383 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1384 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1385 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1386 | ||
1387 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1388 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1389 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1390 | |
1391 | /* Reset the Tx prefetch units */ | |
1392 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1393 | PREF_UNIT_RST_SET); | |
1394 | ||
1395 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1396 | ||
6b1a3aef | 1397 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1398 | |
1399 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1400 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1401 | ||
e07b1aa8 SH |
1402 | /* Disable port IRQ */ |
1403 | imask = sky2_read32(hw, B0_IMSK); | |
1404 | imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; | |
1405 | sky2_write32(hw, B0_IMSK, imask); | |
1406 | ||
d571b694 | 1407 | /* turn off LED's */ |
cd28ab6a SH |
1408 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1409 | ||
018d1c66 SH |
1410 | synchronize_irq(hw->pdev->irq); |
1411 | ||
cd28ab6a SH |
1412 | sky2_tx_clean(sky2); |
1413 | sky2_rx_clean(sky2); | |
1414 | ||
1415 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1416 | sky2->rx_le, sky2->rx_le_map); | |
1417 | kfree(sky2->rx_ring); | |
1418 | ||
1419 | pci_free_consistent(hw->pdev, | |
1420 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1421 | sky2->tx_le, sky2->tx_le_map); | |
1422 | kfree(sky2->tx_ring); | |
1423 | ||
1b537565 SH |
1424 | sky2->tx_le = NULL; |
1425 | sky2->rx_le = NULL; | |
1426 | ||
1427 | sky2->rx_ring = NULL; | |
1428 | sky2->tx_ring = NULL; | |
1429 | ||
cd28ab6a SH |
1430 | return 0; |
1431 | } | |
1432 | ||
1433 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1434 | { | |
793b883e SH |
1435 | if (!hw->copper) |
1436 | return SPEED_1000; | |
1437 | ||
cd28ab6a SH |
1438 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1439 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1440 | ||
1441 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1442 | case PHY_M_PS_SPEED_1000: | |
1443 | return SPEED_1000; | |
1444 | case PHY_M_PS_SPEED_100: | |
1445 | return SPEED_100; | |
1446 | default: | |
1447 | return SPEED_10; | |
1448 | } | |
1449 | } | |
1450 | ||
1451 | static void sky2_link_up(struct sky2_port *sky2) | |
1452 | { | |
1453 | struct sky2_hw *hw = sky2->hw; | |
1454 | unsigned port = sky2->port; | |
1455 | u16 reg; | |
1456 | ||
1457 | /* Enable Transmit FIFO Underrun */ | |
793b883e | 1458 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
cd28ab6a SH |
1459 | |
1460 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
6f4c56b2 SH |
1461 | if (sky2->autoneg == AUTONEG_DISABLE) { |
1462 | reg |= GM_GPCR_AU_ALL_DIS; | |
1463 | ||
1464 | /* Is write/read necessary? Copied from sky2_mac_init */ | |
1465 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1466 | gma_read16(hw, port, GM_GP_CTRL); | |
1467 | ||
1468 | switch (sky2->speed) { | |
1469 | case SPEED_1000: | |
1470 | reg &= ~GM_GPCR_SPEED_100; | |
1471 | reg |= GM_GPCR_SPEED_1000; | |
1472 | break; | |
1473 | case SPEED_100: | |
1474 | reg &= ~GM_GPCR_SPEED_1000; | |
1475 | reg |= GM_GPCR_SPEED_100; | |
1476 | break; | |
1477 | case SPEED_10: | |
1478 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
1479 | break; | |
1480 | } | |
1481 | } else | |
1482 | reg &= ~GM_GPCR_AU_ALL_DIS; | |
1483 | ||
cd28ab6a SH |
1484 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) |
1485 | reg |= GM_GPCR_DUP_FULL; | |
1486 | ||
cd28ab6a SH |
1487 | /* enable Rx/Tx */ |
1488 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1489 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1490 | gma_read16(hw, port, GM_GP_CTRL); | |
1491 | ||
1492 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1493 | ||
1494 | netif_carrier_on(sky2->netdev); | |
1495 | netif_wake_queue(sky2->netdev); | |
1496 | ||
1497 | /* Turn on link LED */ | |
793b883e | 1498 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1499 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1500 | ||
793b883e SH |
1501 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
1502 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
1503 | ||
1504 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
1505 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
1506 | PHY_M_LEDC_INIT_CTRL(sky2->speed == | |
1507 | SPEED_10 ? 7 : 0) | | |
1508 | PHY_M_LEDC_STA1_CTRL(sky2->speed == | |
1509 | SPEED_100 ? 7 : 0) | | |
1510 | PHY_M_LEDC_STA0_CTRL(sky2->speed == | |
1511 | SPEED_1000 ? 7 : 0)); | |
1512 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
1513 | } | |
1514 | ||
cd28ab6a SH |
1515 | if (netif_msg_link(sky2)) |
1516 | printk(KERN_INFO PFX | |
d571b694 | 1517 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
cd28ab6a SH |
1518 | sky2->netdev->name, sky2->speed, |
1519 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
1520 | (sky2->tx_pause && sky2->rx_pause) ? "both" : | |
793b883e | 1521 | sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); |
cd28ab6a SH |
1522 | } |
1523 | ||
1524 | static void sky2_link_down(struct sky2_port *sky2) | |
1525 | { | |
1526 | struct sky2_hw *hw = sky2->hw; | |
1527 | unsigned port = sky2->port; | |
1528 | u16 reg; | |
1529 | ||
1530 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1531 | ||
1532 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1533 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1534 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1535 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | |
1536 | ||
1537 | if (sky2->rx_pause && !sky2->tx_pause) { | |
1538 | /* restore Asymmetric Pause bit */ | |
1539 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
793b883e SH |
1540 | gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) |
1541 | | PHY_M_AN_ASP); | |
cd28ab6a SH |
1542 | } |
1543 | ||
cd28ab6a SH |
1544 | netif_carrier_off(sky2->netdev); |
1545 | netif_stop_queue(sky2->netdev); | |
1546 | ||
1547 | /* Turn on link LED */ | |
1548 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1549 | ||
1550 | if (netif_msg_link(sky2)) | |
1551 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
1552 | sky2_phy_init(hw, port); | |
1553 | } | |
1554 | ||
793b883e SH |
1555 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1556 | { | |
1557 | struct sky2_hw *hw = sky2->hw; | |
1558 | unsigned port = sky2->port; | |
1559 | u16 lpa; | |
1560 | ||
1561 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); | |
1562 | ||
1563 | if (lpa & PHY_M_AN_RF) { | |
1564 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1565 | return -1; | |
1566 | } | |
1567 | ||
1568 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
1569 | gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { | |
1570 | printk(KERN_ERR PFX "%s: master/slave fault", | |
1571 | sky2->netdev->name); | |
1572 | return -1; | |
1573 | } | |
1574 | ||
1575 | if (!(aux & PHY_M_PS_SPDUP_RES)) { | |
1576 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1577 | sky2->netdev->name); | |
1578 | return -1; | |
1579 | } | |
1580 | ||
1581 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
1582 | ||
1583 | sky2->speed = sky2_phy_speed(hw, aux); | |
1584 | ||
1585 | /* Pause bits are offset (9..8) */ | |
1586 | if (hw->chip_id == CHIP_ID_YUKON_XL) | |
1587 | aux >>= 6; | |
1588 | ||
1589 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | |
1590 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | |
1591 | ||
1592 | if ((sky2->tx_pause || sky2->rx_pause) | |
1593 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | |
1594 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
1595 | else | |
1596 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1597 | ||
1598 | return 0; | |
1599 | } | |
cd28ab6a | 1600 | |
e07b1aa8 SH |
1601 | /* Interrupt from PHY */ |
1602 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
cd28ab6a | 1603 | { |
e07b1aa8 SH |
1604 | struct net_device *dev = hw->dev[port]; |
1605 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a SH |
1606 | u16 istatus, phystat; |
1607 | ||
e07b1aa8 SH |
1608 | spin_lock(&sky2->phy_lock); |
1609 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); | |
1610 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
1611 | ||
1612 | if (!netif_running(dev)) | |
1613 | goto out; | |
cd28ab6a SH |
1614 | |
1615 | if (netif_msg_intr(sky2)) | |
1616 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1617 | sky2->netdev->name, istatus, phystat); | |
1618 | ||
1619 | if (istatus & PHY_M_IS_AN_COMPL) { | |
793b883e SH |
1620 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1621 | sky2_link_up(sky2); | |
1622 | goto out; | |
1623 | } | |
cd28ab6a | 1624 | |
793b883e SH |
1625 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1626 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1627 | |
793b883e SH |
1628 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1629 | sky2->duplex = | |
1630 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1631 | |
793b883e SH |
1632 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1633 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1634 | sky2_link_up(sky2); |
793b883e SH |
1635 | else |
1636 | sky2_link_down(sky2); | |
cd28ab6a | 1637 | } |
793b883e | 1638 | out: |
e07b1aa8 | 1639 | spin_unlock(&sky2->phy_lock); |
cd28ab6a SH |
1640 | } |
1641 | ||
302d1252 SH |
1642 | |
1643 | /* Transmit timeout is only called if we are running, carries is up | |
1644 | * and tx queue is full (stopped). | |
1645 | */ | |
cd28ab6a SH |
1646 | static void sky2_tx_timeout(struct net_device *dev) |
1647 | { | |
1648 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 SH |
1649 | struct sky2_hw *hw = sky2->hw; |
1650 | unsigned txq = txqaddr[sky2->port]; | |
8f24664d | 1651 | u16 report, done; |
cd28ab6a SH |
1652 | |
1653 | if (netif_msg_timer(sky2)) | |
1654 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1655 | ||
8f24664d SH |
1656 | report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX); |
1657 | done = sky2_read16(hw, Q_ADDR(txq, Q_DONE)); | |
cd28ab6a | 1658 | |
8f24664d SH |
1659 | printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n", |
1660 | dev->name, | |
1661 | sky2->tx_cons, sky2->tx_prod, report, done); | |
1662 | ||
1663 | if (report != done) { | |
1664 | printk(KERN_INFO PFX "status burst pending (irq moderation?)\n"); | |
1665 | ||
1666 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
1667 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
1668 | } else if (report != sky2->tx_cons) { | |
1669 | printk(KERN_INFO PFX "status report lost?\n"); | |
1670 | ||
1671 | spin_lock_bh(&sky2->tx_lock); | |
1672 | sky2_tx_complete(sky2, report); | |
1673 | spin_unlock_bh(&sky2->tx_lock); | |
1674 | } else { | |
1675 | printk(KERN_INFO PFX "hardware hung? flushing\n"); | |
8cc048e3 | 1676 | |
8f24664d SH |
1677 | sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); |
1678 | sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
1679 | ||
1680 | sky2_tx_clean(sky2); | |
1681 | ||
1682 | sky2_qset(hw, txq); | |
1683 | sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); | |
1684 | } | |
cd28ab6a SH |
1685 | } |
1686 | ||
734d1868 | 1687 | |
70f1be48 SH |
1688 | /* Want receive buffer size to be multiple of 64 bits |
1689 | * and incl room for vlan and truncation | |
1690 | */ | |
734d1868 SH |
1691 | static inline unsigned sky2_buf_size(int mtu) |
1692 | { | |
4a15d56f | 1693 | return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8; |
734d1868 SH |
1694 | } |
1695 | ||
cd28ab6a SH |
1696 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) |
1697 | { | |
6b1a3aef SH |
1698 | struct sky2_port *sky2 = netdev_priv(dev); |
1699 | struct sky2_hw *hw = sky2->hw; | |
1700 | int err; | |
1701 | u16 ctl, mode; | |
e07b1aa8 | 1702 | u32 imask; |
cd28ab6a SH |
1703 | |
1704 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
1705 | return -EINVAL; | |
1706 | ||
5a5b1ea0 SH |
1707 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) |
1708 | return -EINVAL; | |
1709 | ||
6b1a3aef SH |
1710 | if (!netif_running(dev)) { |
1711 | dev->mtu = new_mtu; | |
1712 | return 0; | |
1713 | } | |
1714 | ||
e07b1aa8 | 1715 | imask = sky2_read32(hw, B0_IMSK); |
6b1a3aef SH |
1716 | sky2_write32(hw, B0_IMSK, 0); |
1717 | ||
018d1c66 SH |
1718 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1719 | netif_stop_queue(dev); | |
1720 | netif_poll_disable(hw->dev[0]); | |
1721 | ||
e07b1aa8 SH |
1722 | synchronize_irq(hw->pdev->irq); |
1723 | ||
6b1a3aef SH |
1724 | ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); |
1725 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
1726 | sky2_rx_stop(sky2); | |
1727 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
1728 | |
1729 | dev->mtu = new_mtu; | |
734d1868 | 1730 | sky2->rx_bufsize = sky2_buf_size(new_mtu); |
6b1a3aef SH |
1731 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
1732 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1733 | ||
1734 | if (dev->mtu > ETH_DATA_LEN) | |
1735 | mode |= GM_SMOD_JUMBO_ENA; | |
1736 | ||
1737 | gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); | |
cd28ab6a | 1738 | |
6b1a3aef | 1739 | sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 1740 | |
6b1a3aef | 1741 | err = sky2_rx_start(sky2); |
e07b1aa8 | 1742 | sky2_write32(hw, B0_IMSK, imask); |
018d1c66 | 1743 | |
1b537565 SH |
1744 | if (err) |
1745 | dev_close(dev); | |
1746 | else { | |
1747 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); | |
1748 | ||
1749 | netif_poll_enable(hw->dev[0]); | |
1750 | netif_wake_queue(dev); | |
1751 | } | |
1752 | ||
cd28ab6a SH |
1753 | return err; |
1754 | } | |
1755 | ||
1756 | /* | |
1757 | * Receive one packet. | |
1758 | * For small packets or errors, just reuse existing skb. | |
d571b694 | 1759 | * For larger packets, get new buffer. |
cd28ab6a | 1760 | */ |
d11c13e7 | 1761 | static struct sk_buff *sky2_receive(struct sky2_port *sky2, |
cd28ab6a SH |
1762 | u16 length, u32 status) |
1763 | { | |
cd28ab6a | 1764 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 1765 | struct sk_buff *skb = NULL; |
cd28ab6a SH |
1766 | |
1767 | if (unlikely(netif_msg_rx_status(sky2))) | |
1768 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
d11c13e7 | 1769 | sky2->netdev->name, sky2->rx_next, status, length); |
cd28ab6a | 1770 | |
793b883e | 1771 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 1772 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 1773 | |
42eeea01 | 1774 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
1775 | goto error; |
1776 | ||
42eeea01 SH |
1777 | if (!(status & GMR_FS_RX_OK)) |
1778 | goto resubmit; | |
1779 | ||
70f1be48 | 1780 | if (length > sky2->netdev->mtu + ETH_HLEN) |
6e15b712 SH |
1781 | goto oversize; |
1782 | ||
bdb5c58e | 1783 | if (length < copybreak) { |
79e57d32 SH |
1784 | skb = alloc_skb(length + 2, GFP_ATOMIC); |
1785 | if (!skb) | |
793b883e SH |
1786 | goto resubmit; |
1787 | ||
79e57d32 | 1788 | skb_reserve(skb, 2); |
793b883e SH |
1789 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, |
1790 | length, PCI_DMA_FROMDEVICE); | |
79e57d32 | 1791 | memcpy(skb->data, re->skb->data, length); |
d11c13e7 SH |
1792 | skb->ip_summed = re->skb->ip_summed; |
1793 | skb->csum = re->skb->csum; | |
793b883e SH |
1794 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, |
1795 | length, PCI_DMA_FROMDEVICE); | |
793b883e | 1796 | } else { |
79e57d32 SH |
1797 | struct sk_buff *nskb; |
1798 | ||
82788c7a | 1799 | nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC); |
793b883e SH |
1800 | if (!nskb) |
1801 | goto resubmit; | |
cd28ab6a | 1802 | |
793b883e | 1803 | skb = re->skb; |
79e57d32 | 1804 | re->skb = nskb; |
793b883e | 1805 | pci_unmap_single(sky2->hw->pdev, re->mapaddr, |
734d1868 | 1806 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1807 | prefetch(skb->data); |
cd28ab6a | 1808 | |
793b883e | 1809 | re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, |
734d1868 | 1810 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1811 | } |
cd28ab6a | 1812 | |
79e57d32 | 1813 | skb_put(skb, length); |
793b883e | 1814 | resubmit: |
d11c13e7 | 1815 | re->skb->ip_summed = CHECKSUM_NONE; |
734d1868 | 1816 | sky2_rx_add(sky2, re->mapaddr); |
79e57d32 | 1817 | |
bea86103 | 1818 | /* Tell receiver about new buffers. */ |
290d4de5 | 1819 | sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put); |
bea86103 | 1820 | |
cd28ab6a SH |
1821 | return skb; |
1822 | ||
6e15b712 SH |
1823 | oversize: |
1824 | ++sky2->net_stats.rx_over_errors; | |
1825 | goto resubmit; | |
1826 | ||
cd28ab6a | 1827 | error: |
6e15b712 SH |
1828 | ++sky2->net_stats.rx_errors; |
1829 | ||
3be92a70 | 1830 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
cd28ab6a SH |
1831 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", |
1832 | sky2->netdev->name, status, length); | |
793b883e SH |
1833 | |
1834 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
cd28ab6a SH |
1835 | sky2->net_stats.rx_length_errors++; |
1836 | if (status & GMR_FS_FRAGMENT) | |
1837 | sky2->net_stats.rx_frame_errors++; | |
1838 | if (status & GMR_FS_CRC_ERR) | |
1839 | sky2->net_stats.rx_crc_errors++; | |
793b883e SH |
1840 | if (status & GMR_FS_RX_FF_OV) |
1841 | sky2->net_stats.rx_fifo_errors++; | |
79e57d32 | 1842 | |
793b883e | 1843 | goto resubmit; |
cd28ab6a SH |
1844 | } |
1845 | ||
e07b1aa8 SH |
1846 | /* Transmit complete */ |
1847 | static inline void sky2_tx_done(struct net_device *dev, u16 last) | |
13b97b74 | 1848 | { |
e07b1aa8 | 1849 | struct sky2_port *sky2 = netdev_priv(dev); |
302d1252 | 1850 | |
e07b1aa8 SH |
1851 | if (netif_running(dev)) { |
1852 | spin_lock(&sky2->tx_lock); | |
1853 | sky2_tx_complete(sky2, last); | |
1854 | spin_unlock(&sky2->tx_lock); | |
2224795d | 1855 | } |
cd28ab6a SH |
1856 | } |
1857 | ||
e07b1aa8 SH |
1858 | /* Process status response ring */ |
1859 | static int sky2_status_intr(struct sky2_hw *hw, int to_do) | |
cd28ab6a | 1860 | { |
e07b1aa8 | 1861 | int work_done = 0; |
a8fd6266 | 1862 | |
af2a58ac | 1863 | rmb(); |
bea86103 | 1864 | |
e07b1aa8 | 1865 | for(;;) { |
13210ce5 SH |
1866 | struct sky2_status_le *le = hw->st_le + hw->st_idx; |
1867 | struct net_device *dev; | |
d11c13e7 | 1868 | struct sky2_port *sky2; |
cd28ab6a | 1869 | struct sk_buff *skb; |
cd28ab6a SH |
1870 | u32 status; |
1871 | u16 length; | |
e07b1aa8 SH |
1872 | u8 link, opcode; |
1873 | ||
1874 | opcode = le->opcode; | |
1875 | if (!opcode) | |
1876 | break; | |
1877 | opcode &= ~HW_OWNER; | |
cd28ab6a | 1878 | |
bea86103 | 1879 | hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE; |
e07b1aa8 | 1880 | le->opcode = 0; |
bea86103 | 1881 | |
e07b1aa8 SH |
1882 | link = le->link; |
1883 | BUG_ON(link >= 2); | |
1884 | dev = hw->dev[link]; | |
13210ce5 SH |
1885 | |
1886 | sky2 = netdev_priv(dev); | |
e07b1aa8 SH |
1887 | length = le->length; |
1888 | status = le->status; | |
cd28ab6a | 1889 | |
e07b1aa8 | 1890 | switch (opcode) { |
cd28ab6a | 1891 | case OP_RXSTAT: |
d11c13e7 | 1892 | skb = sky2_receive(sky2, length, status); |
d1f13708 SH |
1893 | if (!skb) |
1894 | break; | |
13210ce5 SH |
1895 | |
1896 | skb->dev = dev; | |
1897 | skb->protocol = eth_type_trans(skb, dev); | |
1898 | dev->last_rx = jiffies; | |
1899 | ||
d1f13708 SH |
1900 | #ifdef SKY2_VLAN_TAG_USED |
1901 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { | |
1902 | vlan_hwaccel_receive_skb(skb, | |
1903 | sky2->vlgrp, | |
1904 | be16_to_cpu(sky2->rx_tag)); | |
1905 | } else | |
1906 | #endif | |
cd28ab6a | 1907 | netif_receive_skb(skb); |
13210ce5 SH |
1908 | |
1909 | if (++work_done >= to_do) | |
1910 | goto exit_loop; | |
cd28ab6a SH |
1911 | break; |
1912 | ||
d1f13708 SH |
1913 | #ifdef SKY2_VLAN_TAG_USED |
1914 | case OP_RXVLAN: | |
1915 | sky2->rx_tag = length; | |
1916 | break; | |
1917 | ||
1918 | case OP_RXCHKSVLAN: | |
1919 | sky2->rx_tag = length; | |
1920 | /* fall through */ | |
1921 | #endif | |
cd28ab6a | 1922 | case OP_RXCHKS: |
d11c13e7 SH |
1923 | skb = sky2->rx_ring[sky2->rx_next].skb; |
1924 | skb->ip_summed = CHECKSUM_HW; | |
1925 | skb->csum = le16_to_cpu(status); | |
cd28ab6a SH |
1926 | break; |
1927 | ||
1928 | case OP_TXINDEXLE: | |
13b97b74 | 1929 | /* TX index reports status for both ports */ |
f55925d7 SH |
1930 | BUILD_BUG_ON(TX_RING_SIZE > 0x1000); |
1931 | sky2_tx_done(hw->dev[0], status & 0xfff); | |
e07b1aa8 SH |
1932 | if (hw->dev[1]) |
1933 | sky2_tx_done(hw->dev[1], | |
1934 | ((status >> 24) & 0xff) | |
1935 | | (u16)(length & 0xf) << 8); | |
cd28ab6a SH |
1936 | break; |
1937 | ||
cd28ab6a SH |
1938 | default: |
1939 | if (net_ratelimit()) | |
793b883e | 1940 | printk(KERN_WARNING PFX |
e07b1aa8 | 1941 | "unknown status opcode 0x%x\n", opcode); |
cd28ab6a SH |
1942 | break; |
1943 | } | |
13210ce5 | 1944 | } |
cd28ab6a | 1945 | |
13210ce5 | 1946 | exit_loop: |
e07b1aa8 | 1947 | return work_done; |
cd28ab6a SH |
1948 | } |
1949 | ||
1950 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
1951 | { | |
1952 | struct net_device *dev = hw->dev[port]; | |
1953 | ||
3be92a70 SH |
1954 | if (net_ratelimit()) |
1955 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
1956 | dev->name, status); | |
cd28ab6a SH |
1957 | |
1958 | if (status & Y2_IS_PAR_RD1) { | |
3be92a70 SH |
1959 | if (net_ratelimit()) |
1960 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
1961 | dev->name); | |
cd28ab6a SH |
1962 | /* Clear IRQ */ |
1963 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
1964 | } | |
1965 | ||
1966 | if (status & Y2_IS_PAR_WR1) { | |
3be92a70 SH |
1967 | if (net_ratelimit()) |
1968 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
1969 | dev->name); | |
cd28ab6a SH |
1970 | |
1971 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
1972 | } | |
1973 | ||
1974 | if (status & Y2_IS_PAR_MAC1) { | |
3be92a70 SH |
1975 | if (net_ratelimit()) |
1976 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
cd28ab6a SH |
1977 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
1978 | } | |
1979 | ||
1980 | if (status & Y2_IS_PAR_RX1) { | |
3be92a70 SH |
1981 | if (net_ratelimit()) |
1982 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
cd28ab6a SH |
1983 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
1984 | } | |
1985 | ||
1986 | if (status & Y2_IS_TCP_TXA1) { | |
3be92a70 SH |
1987 | if (net_ratelimit()) |
1988 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", | |
1989 | dev->name); | |
cd28ab6a SH |
1990 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
1991 | } | |
1992 | } | |
1993 | ||
1994 | static void sky2_hw_intr(struct sky2_hw *hw) | |
1995 | { | |
1996 | u32 status = sky2_read32(hw, B0_HWE_ISRC); | |
1997 | ||
793b883e | 1998 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 1999 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2000 | |
2001 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
2002 | u16 pci_err; |
2003 | ||
56a645cc | 2004 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
3be92a70 SH |
2005 | if (net_ratelimit()) |
2006 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", | |
2007 | pci_name(hw->pdev), pci_err); | |
cd28ab6a SH |
2008 | |
2009 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
56a645cc | 2010 | sky2_pci_write16(hw, PCI_STATUS, |
793b883e | 2011 | pci_err | PCI_STATUS_ERROR_BITS); |
cd28ab6a SH |
2012 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2013 | } | |
2014 | ||
2015 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 2016 | /* PCI-Express uncorrectable Error occurred */ |
793b883e SH |
2017 | u32 pex_err; |
2018 | ||
56a645cc | 2019 | pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT); |
cd28ab6a | 2020 | |
3be92a70 SH |
2021 | if (net_ratelimit()) |
2022 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", | |
2023 | pci_name(hw->pdev), pex_err); | |
cd28ab6a SH |
2024 | |
2025 | /* clear the interrupt */ | |
2026 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
56a645cc | 2027 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, |
793b883e | 2028 | 0xffffffffUL); |
cd28ab6a SH |
2029 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2030 | ||
2031 | if (pex_err & PEX_FATAL_ERRORS) { | |
2032 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); | |
2033 | hwmsk &= ~Y2_IS_PCI_EXP; | |
2034 | sky2_write32(hw, B0_HWE_IMSK, hwmsk); | |
2035 | } | |
2036 | } | |
2037 | ||
2038 | if (status & Y2_HWE_L1_MASK) | |
2039 | sky2_hw_error(hw, 0, status); | |
2040 | status >>= 8; | |
2041 | if (status & Y2_HWE_L1_MASK) | |
2042 | sky2_hw_error(hw, 1, status); | |
2043 | } | |
2044 | ||
2045 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2046 | { | |
2047 | struct net_device *dev = hw->dev[port]; | |
2048 | struct sky2_port *sky2 = netdev_priv(dev); | |
2049 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2050 | ||
2051 | if (netif_msg_intr(sky2)) | |
2052 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
2053 | dev->name, status); | |
2054 | ||
2055 | if (status & GM_IS_RX_FF_OR) { | |
2056 | ++sky2->net_stats.rx_fifo_errors; | |
2057 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); | |
2058 | } | |
2059 | ||
2060 | if (status & GM_IS_TX_FF_UR) { | |
2061 | ++sky2->net_stats.tx_fifo_errors; | |
2062 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); | |
2063 | } | |
cd28ab6a SH |
2064 | } |
2065 | ||
d257924e SH |
2066 | /* This should never happen it is a fatal situation */ |
2067 | static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port, | |
2068 | const char *rxtx, u32 mask) | |
2069 | { | |
2070 | struct net_device *dev = hw->dev[port]; | |
2071 | struct sky2_port *sky2 = netdev_priv(dev); | |
2072 | u32 imask; | |
2073 | ||
2074 | printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n", | |
2075 | dev ? dev->name : "<not registered>", rxtx); | |
2076 | ||
2077 | imask = sky2_read32(hw, B0_IMSK); | |
2078 | imask &= ~mask; | |
2079 | sky2_write32(hw, B0_IMSK, imask); | |
2080 | ||
2081 | if (dev) { | |
2082 | spin_lock(&sky2->phy_lock); | |
2083 | sky2_link_down(sky2); | |
2084 | spin_unlock(&sky2->phy_lock); | |
2085 | } | |
2086 | } | |
cd28ab6a | 2087 | |
d27ed387 SH |
2088 | /* If idle then force a fake soft NAPI poll once a second |
2089 | * to work around cases where sharing an edge triggered interrupt. | |
2090 | */ | |
2091 | static void sky2_idle(unsigned long arg) | |
2092 | { | |
2093 | struct net_device *dev = (struct net_device *) arg; | |
2094 | ||
2095 | local_irq_disable(); | |
2096 | if (__netif_rx_schedule_prep(dev)) | |
2097 | __netif_rx_schedule(dev); | |
2098 | local_irq_enable(); | |
2099 | } | |
2100 | ||
2101 | ||
e07b1aa8 | 2102 | static int sky2_poll(struct net_device *dev0, int *budget) |
cd28ab6a | 2103 | { |
e07b1aa8 SH |
2104 | struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; |
2105 | int work_limit = min(dev0->quota, *budget); | |
2106 | int work_done = 0; | |
fb2690a9 | 2107 | u32 status = sky2_read32(hw, B0_Y2_SP_EISR); |
cd28ab6a | 2108 | |
1e5f1283 SH |
2109 | if (status & Y2_IS_HW_ERR) |
2110 | sky2_hw_intr(hw); | |
d257924e | 2111 | |
1e5f1283 SH |
2112 | if (status & Y2_IS_IRQ_PHY1) |
2113 | sky2_phy_intr(hw, 0); | |
cd28ab6a | 2114 | |
1e5f1283 SH |
2115 | if (status & Y2_IS_IRQ_PHY2) |
2116 | sky2_phy_intr(hw, 1); | |
cd28ab6a | 2117 | |
1e5f1283 SH |
2118 | if (status & Y2_IS_IRQ_MAC1) |
2119 | sky2_mac_intr(hw, 0); | |
cd28ab6a | 2120 | |
1e5f1283 SH |
2121 | if (status & Y2_IS_IRQ_MAC2) |
2122 | sky2_mac_intr(hw, 1); | |
cd28ab6a | 2123 | |
1e5f1283 SH |
2124 | if (status & Y2_IS_CHK_RX1) |
2125 | sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1); | |
d257924e | 2126 | |
1e5f1283 SH |
2127 | if (status & Y2_IS_CHK_RX2) |
2128 | sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2); | |
d257924e | 2129 | |
1e5f1283 SH |
2130 | if (status & Y2_IS_CHK_TXA1) |
2131 | sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1); | |
d257924e | 2132 | |
1e5f1283 SH |
2133 | if (status & Y2_IS_CHK_TXA2) |
2134 | sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); | |
cd28ab6a | 2135 | |
1e5f1283 SH |
2136 | if (status & Y2_IS_STAT_BMU) |
2137 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | |
e07b1aa8 | 2138 | |
1e5f1283 SH |
2139 | work_done = sky2_status_intr(hw, work_limit); |
2140 | *budget -= work_done; | |
2141 | dev0->quota -= work_done; | |
e07b1aa8 | 2142 | |
1e5f1283 SH |
2143 | if (work_done >= work_limit) |
2144 | return 1; | |
e07b1aa8 | 2145 | |
d27ed387 SH |
2146 | mod_timer(&hw->idle_timer, jiffies + HZ); |
2147 | ||
d3240312 | 2148 | netif_rx_complete(dev0); |
e07b1aa8 | 2149 | |
fb2690a9 | 2150 | status = sky2_read32(hw, B0_Y2_SP_LISR); |
e07b1aa8 SH |
2151 | return 0; |
2152 | } | |
2153 | ||
2154 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |
2155 | { | |
2156 | struct sky2_hw *hw = dev_id; | |
2157 | struct net_device *dev0 = hw->dev[0]; | |
2158 | u32 status; | |
2159 | ||
2160 | /* Reading this mask interrupts as side effect */ | |
2161 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
2162 | if (status == 0 || status == ~0) | |
2163 | return IRQ_NONE; | |
793b883e | 2164 | |
e07b1aa8 SH |
2165 | prefetch(&hw->st_le[hw->st_idx]); |
2166 | if (likely(__netif_rx_schedule_prep(dev0))) | |
2167 | __netif_rx_schedule(dev0); | |
d3240312 SH |
2168 | else |
2169 | printk(KERN_DEBUG PFX "irq race detected\n"); | |
793b883e | 2170 | |
cd28ab6a SH |
2171 | return IRQ_HANDLED; |
2172 | } | |
2173 | ||
2174 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2175 | static void sky2_netpoll(struct net_device *dev) | |
2176 | { | |
2177 | struct sky2_port *sky2 = netdev_priv(dev); | |
2178 | ||
793b883e | 2179 | sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL); |
cd28ab6a SH |
2180 | } |
2181 | #endif | |
2182 | ||
2183 | /* Chip internal frequency for clock calculations */ | |
fb17358f | 2184 | static inline u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 2185 | { |
793b883e | 2186 | switch (hw->chip_id) { |
cd28ab6a | 2187 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2188 | case CHIP_ID_YUKON_EC_U: |
fb17358f | 2189 | return 125; /* 125 Mhz */ |
cd28ab6a | 2190 | case CHIP_ID_YUKON_FE: |
fb17358f | 2191 | return 100; /* 100 Mhz */ |
793b883e | 2192 | default: /* YUKON_XL */ |
fb17358f | 2193 | return 156; /* 156 Mhz */ |
cd28ab6a SH |
2194 | } |
2195 | } | |
2196 | ||
fb17358f | 2197 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 2198 | { |
fb17358f | 2199 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
2200 | } |
2201 | ||
fb17358f | 2202 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 2203 | { |
fb17358f | 2204 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
2205 | } |
2206 | ||
fb17358f | 2207 | |
98712e5e | 2208 | static int __devinit sky2_reset(struct sky2_hw *hw) |
cd28ab6a | 2209 | { |
cd28ab6a SH |
2210 | u16 status; |
2211 | u8 t8, pmd_type; | |
56a645cc | 2212 | int i; |
cd28ab6a | 2213 | |
cd28ab6a | 2214 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
08c06d8a | 2215 | |
cd28ab6a SH |
2216 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
2217 | if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { | |
2218 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
2219 | pci_name(hw->pdev), hw->chip_id); | |
2220 | return -EOPNOTSUPP; | |
2221 | } | |
2222 | ||
290d4de5 SH |
2223 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; |
2224 | ||
2225 | /* This rev is really old, and requires untested workarounds */ | |
2226 | if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) { | |
2227 | printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n", | |
2228 | pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], | |
2229 | hw->chip_id, hw->chip_rev); | |
2230 | return -EOPNOTSUPP; | |
2231 | } | |
2232 | ||
2233 | /* This chip is new and not tested yet */ | |
2234 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
2235 | pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n", | |
2236 | pci_name(hw->pdev)); | |
2237 | pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n"); | |
2238 | } | |
2239 | ||
cd28ab6a SH |
2240 | /* disable ASF */ |
2241 | if (hw->chip_id <= CHIP_ID_YUKON_EC) { | |
2242 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
2243 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
2244 | } | |
2245 | ||
2246 | /* do a SW reset */ | |
2247 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
2248 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2249 | ||
2250 | /* clear PCI errors, if any */ | |
56a645cc | 2251 | status = sky2_pci_read16(hw, PCI_STATUS); |
2d42d21f | 2252 | |
cd28ab6a | 2253 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
56a645cc SH |
2254 | sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS); |
2255 | ||
cd28ab6a SH |
2256 | |
2257 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
2258 | ||
2259 | /* clear any PEX errors */ | |
d89e1343 | 2260 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) |
56a645cc SH |
2261 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); |
2262 | ||
cd28ab6a SH |
2263 | |
2264 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | |
2265 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | |
2266 | ||
2267 | hw->ports = 1; | |
2268 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
2269 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
2270 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
2271 | ++hw->ports; | |
2272 | } | |
cd28ab6a | 2273 | |
5afa0a9c | 2274 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
2275 | |
2276 | for (i = 0; i < hw->ports; i++) { | |
2277 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
2278 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
2279 | } | |
2280 | ||
2281 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
2282 | ||
793b883e SH |
2283 | /* Clear I2C IRQ noise */ |
2284 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
2285 | |
2286 | /* turn off hardware timer (unused) */ | |
2287 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
2288 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 2289 | |
cd28ab6a SH |
2290 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
2291 | ||
69634ee7 SH |
2292 | /* Turn off descriptor polling */ |
2293 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
2294 | |
2295 | /* Turn off receive timestamp */ | |
2296 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 2297 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2298 | |
2299 | /* enable the Tx Arbiters */ | |
2300 | for (i = 0; i < hw->ports; i++) | |
2301 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
2302 | ||
2303 | /* Initialize ram interface */ | |
2304 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 2305 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
2306 | |
2307 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
2308 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
2309 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
2310 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
2311 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
2312 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
2313 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
2314 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
2315 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
2316 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
2317 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
2318 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
2319 | } | |
2320 | ||
cd28ab6a SH |
2321 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); |
2322 | ||
cd28ab6a SH |
2323 | for (i = 0; i < hw->ports; i++) |
2324 | sky2_phy_reset(hw, i); | |
cd28ab6a | 2325 | |
cd28ab6a SH |
2326 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2327 | hw->st_idx = 0; | |
2328 | ||
2329 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
2330 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
2331 | ||
2332 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 2333 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
2334 | |
2335 | /* Set the list last index */ | |
793b883e | 2336 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 2337 | |
290d4de5 SH |
2338 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
2339 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a | 2340 | |
290d4de5 SH |
2341 | /* set Status-FIFO ISR watermark */ |
2342 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
2343 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); | |
2344 | else | |
2345 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 2346 | |
290d4de5 | 2347 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
77b3d6a2 SH |
2348 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); |
2349 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
cd28ab6a | 2350 | |
793b883e | 2351 | /* enable status unit */ |
cd28ab6a SH |
2352 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2353 | ||
2354 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2355 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2356 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2357 | ||
2358 | return 0; | |
2359 | } | |
2360 | ||
28bd181a | 2361 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
cd28ab6a SH |
2362 | { |
2363 | u32 modes; | |
2364 | if (hw->copper) { | |
793b883e SH |
2365 | modes = SUPPORTED_10baseT_Half |
2366 | | SUPPORTED_10baseT_Full | |
2367 | | SUPPORTED_100baseT_Half | |
2368 | | SUPPORTED_100baseT_Full | |
2369 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2370 | |
2371 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
2372 | modes |= SUPPORTED_1000baseT_Half | |
793b883e | 2373 | | SUPPORTED_1000baseT_Full; |
cd28ab6a SH |
2374 | } else |
2375 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
793b883e | 2376 | | SUPPORTED_Autoneg; |
cd28ab6a SH |
2377 | return modes; |
2378 | } | |
2379 | ||
793b883e | 2380 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
2381 | { |
2382 | struct sky2_port *sky2 = netdev_priv(dev); | |
2383 | struct sky2_hw *hw = sky2->hw; | |
2384 | ||
2385 | ecmd->transceiver = XCVR_INTERNAL; | |
2386 | ecmd->supported = sky2_supported_modes(hw); | |
2387 | ecmd->phy_address = PHY_ADDR_MARV; | |
2388 | if (hw->copper) { | |
2389 | ecmd->supported = SUPPORTED_10baseT_Half | |
793b883e SH |
2390 | | SUPPORTED_10baseT_Full |
2391 | | SUPPORTED_100baseT_Half | |
2392 | | SUPPORTED_100baseT_Full | |
2393 | | SUPPORTED_1000baseT_Half | |
2394 | | SUPPORTED_1000baseT_Full | |
2395 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2396 | ecmd->port = PORT_TP; |
2397 | } else | |
2398 | ecmd->port = PORT_FIBRE; | |
2399 | ||
2400 | ecmd->advertising = sky2->advertising; | |
2401 | ecmd->autoneg = sky2->autoneg; | |
2402 | ecmd->speed = sky2->speed; | |
2403 | ecmd->duplex = sky2->duplex; | |
2404 | return 0; | |
2405 | } | |
2406 | ||
2407 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2408 | { | |
2409 | struct sky2_port *sky2 = netdev_priv(dev); | |
2410 | const struct sky2_hw *hw = sky2->hw; | |
2411 | u32 supported = sky2_supported_modes(hw); | |
2412 | ||
2413 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2414 | ecmd->advertising = supported; | |
2415 | sky2->duplex = -1; | |
2416 | sky2->speed = -1; | |
2417 | } else { | |
2418 | u32 setting; | |
2419 | ||
793b883e | 2420 | switch (ecmd->speed) { |
cd28ab6a SH |
2421 | case SPEED_1000: |
2422 | if (ecmd->duplex == DUPLEX_FULL) | |
2423 | setting = SUPPORTED_1000baseT_Full; | |
2424 | else if (ecmd->duplex == DUPLEX_HALF) | |
2425 | setting = SUPPORTED_1000baseT_Half; | |
2426 | else | |
2427 | return -EINVAL; | |
2428 | break; | |
2429 | case SPEED_100: | |
2430 | if (ecmd->duplex == DUPLEX_FULL) | |
2431 | setting = SUPPORTED_100baseT_Full; | |
2432 | else if (ecmd->duplex == DUPLEX_HALF) | |
2433 | setting = SUPPORTED_100baseT_Half; | |
2434 | else | |
2435 | return -EINVAL; | |
2436 | break; | |
2437 | ||
2438 | case SPEED_10: | |
2439 | if (ecmd->duplex == DUPLEX_FULL) | |
2440 | setting = SUPPORTED_10baseT_Full; | |
2441 | else if (ecmd->duplex == DUPLEX_HALF) | |
2442 | setting = SUPPORTED_10baseT_Half; | |
2443 | else | |
2444 | return -EINVAL; | |
2445 | break; | |
2446 | default: | |
2447 | return -EINVAL; | |
2448 | } | |
2449 | ||
2450 | if ((setting & supported) == 0) | |
2451 | return -EINVAL; | |
2452 | ||
2453 | sky2->speed = ecmd->speed; | |
2454 | sky2->duplex = ecmd->duplex; | |
2455 | } | |
2456 | ||
2457 | sky2->autoneg = ecmd->autoneg; | |
2458 | sky2->advertising = ecmd->advertising; | |
2459 | ||
1b537565 SH |
2460 | if (netif_running(dev)) |
2461 | sky2_phy_reinit(sky2); | |
cd28ab6a SH |
2462 | |
2463 | return 0; | |
2464 | } | |
2465 | ||
2466 | static void sky2_get_drvinfo(struct net_device *dev, | |
2467 | struct ethtool_drvinfo *info) | |
2468 | { | |
2469 | struct sky2_port *sky2 = netdev_priv(dev); | |
2470 | ||
2471 | strcpy(info->driver, DRV_NAME); | |
2472 | strcpy(info->version, DRV_VERSION); | |
2473 | strcpy(info->fw_version, "N/A"); | |
2474 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
2475 | } | |
2476 | ||
2477 | static const struct sky2_stat { | |
793b883e SH |
2478 | char name[ETH_GSTRING_LEN]; |
2479 | u16 offset; | |
cd28ab6a SH |
2480 | } sky2_stats[] = { |
2481 | { "tx_bytes", GM_TXO_OK_HI }, | |
2482 | { "rx_bytes", GM_RXO_OK_HI }, | |
2483 | { "tx_broadcast", GM_TXF_BC_OK }, | |
2484 | { "rx_broadcast", GM_RXF_BC_OK }, | |
2485 | { "tx_multicast", GM_TXF_MC_OK }, | |
2486 | { "rx_multicast", GM_RXF_MC_OK }, | |
2487 | { "tx_unicast", GM_TXF_UC_OK }, | |
2488 | { "rx_unicast", GM_RXF_UC_OK }, | |
2489 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
2490 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
eadfa7dd | 2491 | { "collisions", GM_TXF_COL }, |
cd28ab6a SH |
2492 | { "late_collision",GM_TXF_LAT_COL }, |
2493 | { "aborted", GM_TXF_ABO_COL }, | |
eadfa7dd | 2494 | { "single_collisions", GM_TXF_SNG_COL }, |
cd28ab6a | 2495 | { "multi_collisions", GM_TXF_MUL_COL }, |
eadfa7dd | 2496 | |
d2604540 | 2497 | { "rx_short", GM_RXF_SHT }, |
cd28ab6a | 2498 | { "rx_runt", GM_RXE_FRAG }, |
eadfa7dd SH |
2499 | { "rx_64_byte_packets", GM_RXF_64B }, |
2500 | { "rx_65_to_127_byte_packets", GM_RXF_127B }, | |
2501 | { "rx_128_to_255_byte_packets", GM_RXF_255B }, | |
2502 | { "rx_256_to_511_byte_packets", GM_RXF_511B }, | |
2503 | { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, | |
2504 | { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, | |
2505 | { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, | |
cd28ab6a | 2506 | { "rx_too_long", GM_RXF_LNG_ERR }, |
eadfa7dd SH |
2507 | { "rx_fifo_overflow", GM_RXE_FIFO_OV }, |
2508 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
cd28ab6a | 2509 | { "rx_fcs_error", GM_RXF_FCS_ERR }, |
eadfa7dd SH |
2510 | |
2511 | { "tx_64_byte_packets", GM_TXF_64B }, | |
2512 | { "tx_65_to_127_byte_packets", GM_TXF_127B }, | |
2513 | { "tx_128_to_255_byte_packets", GM_TXF_255B }, | |
2514 | { "tx_256_to_511_byte_packets", GM_TXF_511B }, | |
2515 | { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, | |
2516 | { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, | |
2517 | { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, | |
2518 | { "tx_fifo_underrun", GM_TXE_FIFO_UR }, | |
cd28ab6a SH |
2519 | }; |
2520 | ||
cd28ab6a SH |
2521 | static u32 sky2_get_rx_csum(struct net_device *dev) |
2522 | { | |
2523 | struct sky2_port *sky2 = netdev_priv(dev); | |
2524 | ||
2525 | return sky2->rx_csum; | |
2526 | } | |
2527 | ||
2528 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
2529 | { | |
2530 | struct sky2_port *sky2 = netdev_priv(dev); | |
2531 | ||
2532 | sky2->rx_csum = data; | |
793b883e | 2533 | |
cd28ab6a SH |
2534 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2535 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
2536 | ||
2537 | return 0; | |
2538 | } | |
2539 | ||
2540 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
2541 | { | |
2542 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2543 | return sky2->msg_enable; | |
2544 | } | |
2545 | ||
9a7ae0a9 SH |
2546 | static int sky2_nway_reset(struct net_device *dev) |
2547 | { | |
2548 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 SH |
2549 | |
2550 | if (sky2->autoneg != AUTONEG_ENABLE) | |
2551 | return -EINVAL; | |
2552 | ||
1b537565 | 2553 | sky2_phy_reinit(sky2); |
9a7ae0a9 SH |
2554 | |
2555 | return 0; | |
2556 | } | |
2557 | ||
793b883e | 2558 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
2559 | { |
2560 | struct sky2_hw *hw = sky2->hw; | |
2561 | unsigned port = sky2->port; | |
2562 | int i; | |
2563 | ||
2564 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 2565 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 2566 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 2567 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 2568 | |
793b883e | 2569 | for (i = 2; i < count; i++) |
cd28ab6a SH |
2570 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
2571 | } | |
2572 | ||
cd28ab6a SH |
2573 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
2574 | { | |
2575 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2576 | sky2->msg_enable = value; | |
2577 | } | |
2578 | ||
2579 | static int sky2_get_stats_count(struct net_device *dev) | |
2580 | { | |
2581 | return ARRAY_SIZE(sky2_stats); | |
2582 | } | |
2583 | ||
2584 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 2585 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
2586 | { |
2587 | struct sky2_port *sky2 = netdev_priv(dev); | |
2588 | ||
793b883e | 2589 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
2590 | } |
2591 | ||
793b883e | 2592 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
2593 | { |
2594 | int i; | |
2595 | ||
2596 | switch (stringset) { | |
2597 | case ETH_SS_STATS: | |
2598 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
2599 | memcpy(data + i * ETH_GSTRING_LEN, | |
2600 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
2601 | break; | |
2602 | } | |
2603 | } | |
2604 | ||
2605 | /* Use hardware MIB variables for critical path statistics and | |
2606 | * transmit feedback not reported at interrupt. | |
2607 | * Other errors are accounted for in interrupt handler. | |
2608 | */ | |
2609 | static struct net_device_stats *sky2_get_stats(struct net_device *dev) | |
2610 | { | |
2611 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2612 | u64 data[13]; |
cd28ab6a | 2613 | |
793b883e | 2614 | sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); |
cd28ab6a SH |
2615 | |
2616 | sky2->net_stats.tx_bytes = data[0]; | |
2617 | sky2->net_stats.rx_bytes = data[1]; | |
2618 | sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
2619 | sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
050ff180 | 2620 | sky2->net_stats.multicast = data[3] + data[5]; |
cd28ab6a SH |
2621 | sky2->net_stats.collisions = data[10]; |
2622 | sky2->net_stats.tx_aborted_errors = data[12]; | |
2623 | ||
2624 | return &sky2->net_stats; | |
2625 | } | |
2626 | ||
2627 | static int sky2_set_mac_address(struct net_device *dev, void *p) | |
2628 | { | |
2629 | struct sky2_port *sky2 = netdev_priv(dev); | |
a8ab1ec0 SH |
2630 | struct sky2_hw *hw = sky2->hw; |
2631 | unsigned port = sky2->port; | |
2632 | const struct sockaddr *addr = p; | |
cd28ab6a SH |
2633 | |
2634 | if (!is_valid_ether_addr(addr->sa_data)) | |
2635 | return -EADDRNOTAVAIL; | |
2636 | ||
cd28ab6a | 2637 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
a8ab1ec0 | 2638 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
cd28ab6a | 2639 | dev->dev_addr, ETH_ALEN); |
a8ab1ec0 | 2640 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
cd28ab6a | 2641 | dev->dev_addr, ETH_ALEN); |
1b537565 | 2642 | |
a8ab1ec0 SH |
2643 | /* virtual address for data */ |
2644 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
2645 | ||
2646 | /* physical address: used for pause frames */ | |
2647 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
1b537565 SH |
2648 | |
2649 | return 0; | |
cd28ab6a SH |
2650 | } |
2651 | ||
2652 | static void sky2_set_multicast(struct net_device *dev) | |
2653 | { | |
2654 | struct sky2_port *sky2 = netdev_priv(dev); | |
2655 | struct sky2_hw *hw = sky2->hw; | |
2656 | unsigned port = sky2->port; | |
2657 | struct dev_mc_list *list = dev->mc_list; | |
2658 | u16 reg; | |
2659 | u8 filter[8]; | |
2660 | ||
2661 | memset(filter, 0, sizeof(filter)); | |
2662 | ||
2663 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
2664 | reg |= GM_RXCR_UCF_ENA; | |
2665 | ||
d571b694 | 2666 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 2667 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
793b883e | 2668 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ |
cd28ab6a | 2669 | memset(filter, 0xff, sizeof(filter)); |
793b883e | 2670 | else if (dev->mc_count == 0) /* no multicast */ |
cd28ab6a SH |
2671 | reg &= ~GM_RXCR_MCF_ENA; |
2672 | else { | |
2673 | int i; | |
2674 | reg |= GM_RXCR_MCF_ENA; | |
2675 | ||
2676 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2677 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
793b883e | 2678 | filter[bit / 8] |= 1 << (bit % 8); |
cd28ab6a SH |
2679 | } |
2680 | } | |
2681 | ||
cd28ab6a | 2682 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 2683 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 2684 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 2685 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 2686 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 2687 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 2688 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 2689 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
2690 | |
2691 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
2692 | } | |
2693 | ||
2694 | /* Can have one global because blinking is controlled by | |
2695 | * ethtool and that is always under RTNL mutex | |
2696 | */ | |
91c86df5 | 2697 | static void sky2_led(struct sky2_hw *hw, unsigned port, int on) |
cd28ab6a | 2698 | { |
793b883e SH |
2699 | u16 pg; |
2700 | ||
793b883e SH |
2701 | switch (hw->chip_id) { |
2702 | case CHIP_ID_YUKON_XL: | |
2703 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2704 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2705 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
2706 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
2707 | PHY_M_LEDC_INIT_CTRL(7) | | |
2708 | PHY_M_LEDC_STA1_CTRL(7) | | |
2709 | PHY_M_LEDC_STA0_CTRL(7)) | |
2710 | : 0); | |
2711 | ||
2712 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2713 | break; | |
2714 | ||
2715 | default: | |
2716 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
cd28ab6a | 2717 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
793b883e SH |
2718 | on ? PHY_M_LED_MO_DUP(MO_LED_ON) | |
2719 | PHY_M_LED_MO_10(MO_LED_ON) | | |
2720 | PHY_M_LED_MO_100(MO_LED_ON) | | |
cd28ab6a | 2721 | PHY_M_LED_MO_1000(MO_LED_ON) | |
793b883e SH |
2722 | PHY_M_LED_MO_RX(MO_LED_ON) |
2723 | : PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
2724 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
2725 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
cd28ab6a SH |
2726 | PHY_M_LED_MO_1000(MO_LED_OFF) | |
2727 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
2728 | ||
793b883e | 2729 | } |
cd28ab6a SH |
2730 | } |
2731 | ||
2732 | /* blink LED's for finding board */ | |
2733 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
2734 | { | |
2735 | struct sky2_port *sky2 = netdev_priv(dev); | |
2736 | struct sky2_hw *hw = sky2->hw; | |
2737 | unsigned port = sky2->port; | |
793b883e | 2738 | u16 ledctrl, ledover = 0; |
cd28ab6a | 2739 | long ms; |
91c86df5 | 2740 | int interrupted; |
cd28ab6a SH |
2741 | int onoff = 1; |
2742 | ||
793b883e | 2743 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
2744 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
2745 | else | |
2746 | ms = data * 1000; | |
2747 | ||
2748 | /* save initial values */ | |
e07b1aa8 | 2749 | spin_lock_bh(&sky2->phy_lock); |
793b883e SH |
2750 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2751 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2752 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2753 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2754 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2755 | } else { | |
2756 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
2757 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
2758 | } | |
cd28ab6a | 2759 | |
91c86df5 SH |
2760 | interrupted = 0; |
2761 | while (!interrupted && ms > 0) { | |
cd28ab6a SH |
2762 | sky2_led(hw, port, onoff); |
2763 | onoff = !onoff; | |
2764 | ||
e07b1aa8 | 2765 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 2766 | interrupted = msleep_interruptible(250); |
e07b1aa8 | 2767 | spin_lock_bh(&sky2->phy_lock); |
91c86df5 | 2768 | |
cd28ab6a SH |
2769 | ms -= 250; |
2770 | } | |
2771 | ||
2772 | /* resume regularly scheduled programming */ | |
793b883e SH |
2773 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2774 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2775 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2776 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
2777 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2778 | } else { | |
2779 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
2780 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
2781 | } | |
e07b1aa8 | 2782 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
2783 | |
2784 | return 0; | |
2785 | } | |
2786 | ||
2787 | static void sky2_get_pauseparam(struct net_device *dev, | |
2788 | struct ethtool_pauseparam *ecmd) | |
2789 | { | |
2790 | struct sky2_port *sky2 = netdev_priv(dev); | |
2791 | ||
2792 | ecmd->tx_pause = sky2->tx_pause; | |
2793 | ecmd->rx_pause = sky2->rx_pause; | |
2794 | ecmd->autoneg = sky2->autoneg; | |
2795 | } | |
2796 | ||
2797 | static int sky2_set_pauseparam(struct net_device *dev, | |
2798 | struct ethtool_pauseparam *ecmd) | |
2799 | { | |
2800 | struct sky2_port *sky2 = netdev_priv(dev); | |
2801 | int err = 0; | |
2802 | ||
2803 | sky2->autoneg = ecmd->autoneg; | |
2804 | sky2->tx_pause = ecmd->tx_pause != 0; | |
2805 | sky2->rx_pause = ecmd->rx_pause != 0; | |
2806 | ||
1b537565 | 2807 | sky2_phy_reinit(sky2); |
cd28ab6a SH |
2808 | |
2809 | return err; | |
2810 | } | |
2811 | ||
fb17358f SH |
2812 | static int sky2_get_coalesce(struct net_device *dev, |
2813 | struct ethtool_coalesce *ecmd) | |
2814 | { | |
2815 | struct sky2_port *sky2 = netdev_priv(dev); | |
2816 | struct sky2_hw *hw = sky2->hw; | |
2817 | ||
2818 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
2819 | ecmd->tx_coalesce_usecs = 0; | |
2820 | else { | |
2821 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
2822 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2823 | } | |
2824 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
2825 | ||
2826 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
2827 | ecmd->rx_coalesce_usecs = 0; | |
2828 | else { | |
2829 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
2830 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2831 | } | |
2832 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
2833 | ||
2834 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
2835 | ecmd->rx_coalesce_usecs_irq = 0; | |
2836 | else { | |
2837 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
2838 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
2839 | } | |
2840 | ||
2841 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
2842 | ||
2843 | return 0; | |
2844 | } | |
2845 | ||
2846 | /* Note: this affect both ports */ | |
2847 | static int sky2_set_coalesce(struct net_device *dev, | |
2848 | struct ethtool_coalesce *ecmd) | |
2849 | { | |
2850 | struct sky2_port *sky2 = netdev_priv(dev); | |
2851 | struct sky2_hw *hw = sky2->hw; | |
77b3d6a2 | 2852 | const u32 tmax = sky2_clk2us(hw, 0x0ffffff); |
fb17358f | 2853 | |
77b3d6a2 SH |
2854 | if (ecmd->tx_coalesce_usecs > tmax || |
2855 | ecmd->rx_coalesce_usecs > tmax || | |
2856 | ecmd->rx_coalesce_usecs_irq > tmax) | |
fb17358f SH |
2857 | return -EINVAL; |
2858 | ||
ff81fbbe | 2859 | if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1) |
fb17358f | 2860 | return -EINVAL; |
ff81fbbe | 2861 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
fb17358f | 2862 | return -EINVAL; |
ff81fbbe | 2863 | if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING) |
fb17358f SH |
2864 | return -EINVAL; |
2865 | ||
2866 | if (ecmd->tx_coalesce_usecs == 0) | |
2867 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
2868 | else { | |
2869 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
2870 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
2871 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2872 | } | |
2873 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
2874 | ||
2875 | if (ecmd->rx_coalesce_usecs == 0) | |
2876 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
2877 | else { | |
2878 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
2879 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
2880 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2881 | } | |
2882 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
2883 | ||
2884 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
2885 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
2886 | else { | |
d28d4870 | 2887 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
fb17358f SH |
2888 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
2889 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2890 | } | |
2891 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
2892 | return 0; | |
2893 | } | |
2894 | ||
793b883e SH |
2895 | static void sky2_get_ringparam(struct net_device *dev, |
2896 | struct ethtool_ringparam *ering) | |
2897 | { | |
2898 | struct sky2_port *sky2 = netdev_priv(dev); | |
2899 | ||
2900 | ering->rx_max_pending = RX_MAX_PENDING; | |
2901 | ering->rx_mini_max_pending = 0; | |
2902 | ering->rx_jumbo_max_pending = 0; | |
2903 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
2904 | ||
2905 | ering->rx_pending = sky2->rx_pending; | |
2906 | ering->rx_mini_pending = 0; | |
2907 | ering->rx_jumbo_pending = 0; | |
2908 | ering->tx_pending = sky2->tx_pending; | |
2909 | } | |
2910 | ||
2911 | static int sky2_set_ringparam(struct net_device *dev, | |
2912 | struct ethtool_ringparam *ering) | |
2913 | { | |
2914 | struct sky2_port *sky2 = netdev_priv(dev); | |
2915 | int err = 0; | |
2916 | ||
2917 | if (ering->rx_pending > RX_MAX_PENDING || | |
2918 | ering->rx_pending < 8 || | |
2919 | ering->tx_pending < MAX_SKB_TX_LE || | |
2920 | ering->tx_pending > TX_RING_SIZE - 1) | |
2921 | return -EINVAL; | |
2922 | ||
2923 | if (netif_running(dev)) | |
2924 | sky2_down(dev); | |
2925 | ||
2926 | sky2->rx_pending = ering->rx_pending; | |
2927 | sky2->tx_pending = ering->tx_pending; | |
2928 | ||
1b537565 | 2929 | if (netif_running(dev)) { |
793b883e | 2930 | err = sky2_up(dev); |
1b537565 SH |
2931 | if (err) |
2932 | dev_close(dev); | |
6ed995bb SH |
2933 | else |
2934 | sky2_set_multicast(dev); | |
1b537565 | 2935 | } |
793b883e SH |
2936 | |
2937 | return err; | |
2938 | } | |
2939 | ||
793b883e SH |
2940 | static int sky2_get_regs_len(struct net_device *dev) |
2941 | { | |
6e4cbb34 | 2942 | return 0x4000; |
793b883e SH |
2943 | } |
2944 | ||
2945 | /* | |
2946 | * Returns copy of control register region | |
6e4cbb34 | 2947 | * Note: access to the RAM address register set will cause timeouts. |
793b883e SH |
2948 | */ |
2949 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2950 | void *p) | |
2951 | { | |
2952 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2953 | const void __iomem *io = sky2->hw->regs; |
793b883e | 2954 | |
6e4cbb34 | 2955 | BUG_ON(regs->len < B3_RI_WTO_R1); |
793b883e | 2956 | regs->version = 1; |
6e4cbb34 | 2957 | memset(p, 0, regs->len); |
793b883e | 2958 | |
6e4cbb34 SH |
2959 | memcpy_fromio(p, io, B3_RAM_ADDR); |
2960 | ||
2961 | memcpy_fromio(p + B3_RI_WTO_R1, | |
2962 | io + B3_RI_WTO_R1, | |
2963 | regs->len - B3_RI_WTO_R1); | |
793b883e | 2964 | } |
cd28ab6a SH |
2965 | |
2966 | static struct ethtool_ops sky2_ethtool_ops = { | |
793b883e SH |
2967 | .get_settings = sky2_get_settings, |
2968 | .set_settings = sky2_set_settings, | |
2969 | .get_drvinfo = sky2_get_drvinfo, | |
2970 | .get_msglevel = sky2_get_msglevel, | |
2971 | .set_msglevel = sky2_set_msglevel, | |
9a7ae0a9 | 2972 | .nway_reset = sky2_nway_reset, |
793b883e SH |
2973 | .get_regs_len = sky2_get_regs_len, |
2974 | .get_regs = sky2_get_regs, | |
2975 | .get_link = ethtool_op_get_link, | |
2976 | .get_sg = ethtool_op_get_sg, | |
2977 | .set_sg = ethtool_op_set_sg, | |
2978 | .get_tx_csum = ethtool_op_get_tx_csum, | |
2979 | .set_tx_csum = ethtool_op_set_tx_csum, | |
2980 | .get_tso = ethtool_op_get_tso, | |
2981 | .set_tso = ethtool_op_set_tso, | |
2982 | .get_rx_csum = sky2_get_rx_csum, | |
2983 | .set_rx_csum = sky2_set_rx_csum, | |
2984 | .get_strings = sky2_get_strings, | |
fb17358f SH |
2985 | .get_coalesce = sky2_get_coalesce, |
2986 | .set_coalesce = sky2_set_coalesce, | |
793b883e SH |
2987 | .get_ringparam = sky2_get_ringparam, |
2988 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
2989 | .get_pauseparam = sky2_get_pauseparam, |
2990 | .set_pauseparam = sky2_set_pauseparam, | |
793b883e | 2991 | .phys_id = sky2_phys_id, |
cd28ab6a SH |
2992 | .get_stats_count = sky2_get_stats_count, |
2993 | .get_ethtool_stats = sky2_get_ethtool_stats, | |
2995bfb7 | 2994 | .get_perm_addr = ethtool_op_get_perm_addr, |
cd28ab6a SH |
2995 | }; |
2996 | ||
2997 | /* Initialize network device */ | |
2998 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
2999 | unsigned port, int highmem) | |
3000 | { | |
3001 | struct sky2_port *sky2; | |
3002 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
3003 | ||
3004 | if (!dev) { | |
3005 | printk(KERN_ERR "sky2 etherdev alloc failed"); | |
3006 | return NULL; | |
3007 | } | |
3008 | ||
3009 | SET_MODULE_OWNER(dev); | |
3010 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
ef743d33 | 3011 | dev->irq = hw->pdev->irq; |
cd28ab6a SH |
3012 | dev->open = sky2_up; |
3013 | dev->stop = sky2_down; | |
ef743d33 | 3014 | dev->do_ioctl = sky2_ioctl; |
cd28ab6a SH |
3015 | dev->hard_start_xmit = sky2_xmit_frame; |
3016 | dev->get_stats = sky2_get_stats; | |
3017 | dev->set_multicast_list = sky2_set_multicast; | |
3018 | dev->set_mac_address = sky2_set_mac_address; | |
3019 | dev->change_mtu = sky2_change_mtu; | |
3020 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
3021 | dev->tx_timeout = sky2_tx_timeout; | |
3022 | dev->watchdog_timeo = TX_WATCHDOG; | |
3023 | if (port == 0) | |
3024 | dev->poll = sky2_poll; | |
3025 | dev->weight = NAPI_WEIGHT; | |
3026 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3027 | dev->poll_controller = sky2_netpoll; | |
3028 | #endif | |
cd28ab6a SH |
3029 | |
3030 | sky2 = netdev_priv(dev); | |
3031 | sky2->netdev = dev; | |
3032 | sky2->hw = hw; | |
3033 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
3034 | ||
3035 | spin_lock_init(&sky2->tx_lock); | |
3036 | /* Auto speed and flow control */ | |
3037 | sky2->autoneg = AUTONEG_ENABLE; | |
585b5601 | 3038 | sky2->tx_pause = 1; |
cd28ab6a SH |
3039 | sky2->rx_pause = 1; |
3040 | sky2->duplex = -1; | |
3041 | sky2->speed = -1; | |
3042 | sky2->advertising = sky2_supported_modes(hw); | |
75d070c5 | 3043 | |
d89e1343 | 3044 | /* Receive checksum disabled for Yukon XL |
75d070c5 SH |
3045 | * because of observed problems with incorrect |
3046 | * values when multiple packets are received in one interrupt | |
3047 | */ | |
3048 | sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL); | |
3049 | ||
e07b1aa8 | 3050 | spin_lock_init(&sky2->phy_lock); |
793b883e | 3051 | sky2->tx_pending = TX_DEF_PENDING; |
290d4de5 | 3052 | sky2->rx_pending = RX_DEF_PENDING; |
734d1868 | 3053 | sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN); |
cd28ab6a SH |
3054 | |
3055 | hw->dev[port] = dev; | |
3056 | ||
3057 | sky2->port = port; | |
3058 | ||
5a5b1ea0 SH |
3059 | dev->features |= NETIF_F_LLTX; |
3060 | if (hw->chip_id != CHIP_ID_YUKON_EC_U) | |
3061 | dev->features |= NETIF_F_TSO; | |
cd28ab6a SH |
3062 | if (highmem) |
3063 | dev->features |= NETIF_F_HIGHDMA; | |
793b883e | 3064 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a | 3065 | |
d1f13708 SH |
3066 | #ifdef SKY2_VLAN_TAG_USED |
3067 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
3068 | dev->vlan_rx_register = sky2_vlan_rx_register; | |
3069 | dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid; | |
3070 | #endif | |
3071 | ||
cd28ab6a | 3072 | /* read the mac address */ |
793b883e | 3073 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 3074 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a SH |
3075 | |
3076 | /* device is off until link detection */ | |
3077 | netif_carrier_off(dev); | |
3078 | netif_stop_queue(dev); | |
3079 | ||
3080 | return dev; | |
3081 | } | |
3082 | ||
28bd181a | 3083 | static void __devinit sky2_show_addr(struct net_device *dev) |
cd28ab6a SH |
3084 | { |
3085 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3086 | ||
3087 | if (netif_msg_probe(sky2)) | |
3088 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3089 | dev->name, | |
3090 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3091 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3092 | } | |
3093 | ||
fb2690a9 SH |
3094 | /* Handle software interrupt used during MSI test */ |
3095 | static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id, | |
3096 | struct pt_regs *regs) | |
3097 | { | |
3098 | struct sky2_hw *hw = dev_id; | |
3099 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
3100 | ||
3101 | if (status == 0) | |
3102 | return IRQ_NONE; | |
3103 | ||
3104 | if (status & Y2_IS_IRQ_SW) { | |
3105 | hw->msi_detected = 1; | |
3106 | wake_up(&hw->msi_wait); | |
3107 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3108 | } | |
3109 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
3110 | ||
3111 | return IRQ_HANDLED; | |
3112 | } | |
3113 | ||
3114 | /* Test interrupt path by forcing a a software IRQ */ | |
3115 | static int __devinit sky2_test_msi(struct sky2_hw *hw) | |
3116 | { | |
3117 | struct pci_dev *pdev = hw->pdev; | |
3118 | int err; | |
3119 | ||
3120 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); | |
3121 | ||
3122 | err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw); | |
3123 | if (err) { | |
3124 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3125 | pci_name(pdev), pdev->irq); | |
3126 | return err; | |
3127 | } | |
3128 | ||
3129 | init_waitqueue_head (&hw->msi_wait); | |
3130 | ||
3131 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); | |
3132 | wmb(); | |
3133 | ||
3134 | wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10); | |
3135 | ||
3136 | if (!hw->msi_detected) { | |
3137 | /* MSI test failed, go back to INTx mode */ | |
3138 | printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " | |
3139 | "switching to INTx mode. Please report this failure to " | |
3140 | "the PCI maintainer and include system chipset information.\n", | |
3141 | pci_name(pdev)); | |
3142 | ||
3143 | err = -EOPNOTSUPP; | |
3144 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3145 | } | |
3146 | ||
3147 | sky2_write32(hw, B0_IMSK, 0); | |
3148 | ||
3149 | free_irq(pdev->irq, hw); | |
3150 | ||
3151 | return err; | |
3152 | } | |
3153 | ||
cd28ab6a SH |
3154 | static int __devinit sky2_probe(struct pci_dev *pdev, |
3155 | const struct pci_device_id *ent) | |
3156 | { | |
793b883e | 3157 | struct net_device *dev, *dev1 = NULL; |
cd28ab6a | 3158 | struct sky2_hw *hw; |
5afa0a9c | 3159 | int err, pm_cap, using_dac = 0; |
cd28ab6a | 3160 | |
793b883e SH |
3161 | err = pci_enable_device(pdev); |
3162 | if (err) { | |
cd28ab6a SH |
3163 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
3164 | pci_name(pdev)); | |
3165 | goto err_out; | |
3166 | } | |
3167 | ||
793b883e SH |
3168 | err = pci_request_regions(pdev, DRV_NAME); |
3169 | if (err) { | |
cd28ab6a SH |
3170 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
3171 | pci_name(pdev)); | |
793b883e | 3172 | goto err_out; |
cd28ab6a SH |
3173 | } |
3174 | ||
3175 | pci_set_master(pdev); | |
3176 | ||
5afa0a9c SH |
3177 | /* Find power-management capability. */ |
3178 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
3179 | if (pm_cap == 0) { | |
3180 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
3181 | "aborting.\n"); | |
3182 | err = -EIO; | |
3183 | goto err_out_free_regions; | |
3184 | } | |
3185 | ||
d1f3d4dd SH |
3186 | if (sizeof(dma_addr_t) > sizeof(u32) && |
3187 | !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { | |
3188 | using_dac = 1; | |
3189 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
3190 | if (err < 0) { | |
3191 | printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA " | |
3192 | "for consistent allocations\n", pci_name(pdev)); | |
3193 | goto err_out_free_regions; | |
3194 | } | |
cd28ab6a | 3195 | |
d1f3d4dd | 3196 | } else { |
cd28ab6a SH |
3197 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
3198 | if (err) { | |
3199 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3200 | pci_name(pdev)); | |
3201 | goto err_out_free_regions; | |
3202 | } | |
3203 | } | |
d1f3d4dd | 3204 | |
cd28ab6a | 3205 | err = -ENOMEM; |
6aad85d6 | 3206 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
cd28ab6a SH |
3207 | if (!hw) { |
3208 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
3209 | pci_name(pdev)); | |
3210 | goto err_out_free_regions; | |
3211 | } | |
3212 | ||
cd28ab6a | 3213 | hw->pdev = pdev; |
cd28ab6a SH |
3214 | |
3215 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3216 | if (!hw->regs) { | |
3217 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
3218 | pci_name(pdev)); | |
3219 | goto err_out_free_hw; | |
3220 | } | |
5afa0a9c | 3221 | hw->pm_cap = pm_cap; |
cd28ab6a | 3222 | |
56a645cc SH |
3223 | #ifdef __BIG_ENDIAN |
3224 | /* byte swap descriptors in hardware */ | |
3225 | { | |
3226 | u32 reg; | |
3227 | ||
3228 | reg = sky2_pci_read32(hw, PCI_DEV_REG2); | |
3229 | reg |= PCI_REV_DESC; | |
3230 | sky2_pci_write32(hw, PCI_DEV_REG2, reg); | |
3231 | } | |
3232 | #endif | |
3233 | ||
08c06d8a SH |
3234 | /* ring for status responses */ |
3235 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | |
3236 | &hw->st_dma); | |
3237 | if (!hw->st_le) | |
3238 | goto err_out_iounmap; | |
3239 | ||
cd28ab6a SH |
3240 | err = sky2_reset(hw); |
3241 | if (err) | |
793b883e | 3242 | goto err_out_iounmap; |
cd28ab6a | 3243 | |
5f4f9dc1 SH |
3244 | printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n", |
3245 | DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq, | |
92f965e8 | 3246 | yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], |
793b883e | 3247 | hw->chip_id, hw->chip_rev); |
cd28ab6a | 3248 | |
793b883e SH |
3249 | dev = sky2_init_netdev(hw, 0, using_dac); |
3250 | if (!dev) | |
cd28ab6a SH |
3251 | goto err_out_free_pci; |
3252 | ||
793b883e SH |
3253 | err = register_netdev(dev); |
3254 | if (err) { | |
cd28ab6a SH |
3255 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
3256 | pci_name(pdev)); | |
3257 | goto err_out_free_netdev; | |
3258 | } | |
3259 | ||
3260 | sky2_show_addr(dev); | |
3261 | ||
3262 | if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { | |
3263 | if (register_netdev(dev1) == 0) | |
3264 | sky2_show_addr(dev1); | |
3265 | else { | |
3266 | /* Failure to register second port need not be fatal */ | |
793b883e SH |
3267 | printk(KERN_WARNING PFX |
3268 | "register of second port failed\n"); | |
cd28ab6a SH |
3269 | hw->dev[1] = NULL; |
3270 | free_netdev(dev1); | |
3271 | } | |
3272 | } | |
3273 | ||
fb2690a9 SH |
3274 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
3275 | err = sky2_test_msi(hw); | |
3276 | if (err == -EOPNOTSUPP) | |
3277 | pci_disable_msi(pdev); | |
3278 | else if (err) | |
3279 | goto err_out_unregister; | |
3280 | } | |
3281 | ||
3282 | err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw); | |
793b883e SH |
3283 | if (err) { |
3284 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3285 | pci_name(pdev), pdev->irq); | |
3286 | goto err_out_unregister; | |
3287 | } | |
3288 | ||
e07b1aa8 | 3289 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |
793b883e | 3290 | |
d27ed387 SH |
3291 | setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) dev); |
3292 | ||
793b883e SH |
3293 | pci_set_drvdata(pdev, hw); |
3294 | ||
cd28ab6a SH |
3295 | return 0; |
3296 | ||
793b883e | 3297 | err_out_unregister: |
fb2690a9 | 3298 | pci_disable_msi(pdev); |
793b883e SH |
3299 | if (dev1) { |
3300 | unregister_netdev(dev1); | |
3301 | free_netdev(dev1); | |
3302 | } | |
3303 | unregister_netdev(dev); | |
cd28ab6a SH |
3304 | err_out_free_netdev: |
3305 | free_netdev(dev); | |
cd28ab6a | 3306 | err_out_free_pci: |
793b883e | 3307 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
3308 | pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
3309 | err_out_iounmap: | |
3310 | iounmap(hw->regs); | |
3311 | err_out_free_hw: | |
3312 | kfree(hw); | |
3313 | err_out_free_regions: | |
3314 | pci_release_regions(pdev); | |
cd28ab6a | 3315 | pci_disable_device(pdev); |
cd28ab6a SH |
3316 | err_out: |
3317 | return err; | |
3318 | } | |
3319 | ||
3320 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
3321 | { | |
793b883e | 3322 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3323 | struct net_device *dev0, *dev1; |
3324 | ||
793b883e | 3325 | if (!hw) |
cd28ab6a SH |
3326 | return; |
3327 | ||
d27ed387 SH |
3328 | del_timer_sync(&hw->idle_timer); |
3329 | ||
3330 | sky2_write32(hw, B0_IMSK, 0); | |
cd28ab6a | 3331 | dev0 = hw->dev[0]; |
793b883e SH |
3332 | dev1 = hw->dev[1]; |
3333 | if (dev1) | |
3334 | unregister_netdev(dev1); | |
cd28ab6a SH |
3335 | unregister_netdev(dev0); |
3336 | ||
5afa0a9c | 3337 | sky2_set_power_state(hw, PCI_D3hot); |
cd28ab6a | 3338 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 3339 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 3340 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
3341 | |
3342 | free_irq(pdev->irq, hw); | |
fb2690a9 | 3343 | pci_disable_msi(pdev); |
793b883e | 3344 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
3345 | pci_release_regions(pdev); |
3346 | pci_disable_device(pdev); | |
793b883e | 3347 | |
cd28ab6a SH |
3348 | if (dev1) |
3349 | free_netdev(dev1); | |
3350 | free_netdev(dev0); | |
3351 | iounmap(hw->regs); | |
3352 | kfree(hw); | |
5afa0a9c | 3353 | |
cd28ab6a SH |
3354 | pci_set_drvdata(pdev, NULL); |
3355 | } | |
3356 | ||
3357 | #ifdef CONFIG_PM | |
3358 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
3359 | { | |
793b883e | 3360 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
5afa0a9c | 3361 | int i; |
cd28ab6a SH |
3362 | |
3363 | for (i = 0; i < 2; i++) { | |
3364 | struct net_device *dev = hw->dev[i]; | |
3365 | ||
3366 | if (dev) { | |
5afa0a9c SH |
3367 | if (!netif_running(dev)) |
3368 | continue; | |
3369 | ||
3370 | sky2_down(dev); | |
cd28ab6a | 3371 | netif_device_detach(dev); |
cd28ab6a SH |
3372 | } |
3373 | } | |
3374 | ||
5afa0a9c | 3375 | return sky2_set_power_state(hw, pci_choose_state(pdev, state)); |
cd28ab6a SH |
3376 | } |
3377 | ||
3378 | static int sky2_resume(struct pci_dev *pdev) | |
3379 | { | |
793b883e | 3380 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
08c06d8a | 3381 | int i, err; |
cd28ab6a | 3382 | |
cd28ab6a SH |
3383 | pci_restore_state(pdev); |
3384 | pci_enable_wake(pdev, PCI_D0, 0); | |
08c06d8a SH |
3385 | err = sky2_set_power_state(hw, PCI_D0); |
3386 | if (err) | |
3387 | goto out; | |
cd28ab6a | 3388 | |
08c06d8a SH |
3389 | err = sky2_reset(hw); |
3390 | if (err) | |
3391 | goto out; | |
cd28ab6a SH |
3392 | |
3393 | for (i = 0; i < 2; i++) { | |
3394 | struct net_device *dev = hw->dev[i]; | |
08c06d8a SH |
3395 | if (dev && netif_running(dev)) { |
3396 | netif_device_attach(dev); | |
3397 | err = sky2_up(dev); | |
3398 | if (err) { | |
3399 | printk(KERN_ERR PFX "%s: could not up: %d\n", | |
3400 | dev->name, err); | |
3401 | dev_close(dev); | |
3402 | break; | |
5afa0a9c | 3403 | } |
cd28ab6a SH |
3404 | } |
3405 | } | |
08c06d8a SH |
3406 | out: |
3407 | return err; | |
cd28ab6a SH |
3408 | } |
3409 | #endif | |
3410 | ||
3411 | static struct pci_driver sky2_driver = { | |
793b883e SH |
3412 | .name = DRV_NAME, |
3413 | .id_table = sky2_id_table, | |
3414 | .probe = sky2_probe, | |
3415 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 3416 | #ifdef CONFIG_PM |
793b883e SH |
3417 | .suspend = sky2_suspend, |
3418 | .resume = sky2_resume, | |
cd28ab6a SH |
3419 | #endif |
3420 | }; | |
3421 | ||
3422 | static int __init sky2_init_module(void) | |
3423 | { | |
50241c4c | 3424 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
3425 | } |
3426 | ||
3427 | static void __exit sky2_cleanup_module(void) | |
3428 | { | |
3429 | pci_unregister_driver(&sky2_driver); | |
3430 | } | |
3431 | ||
3432 | module_init(sky2_init_module); | |
3433 | module_exit(sky2_cleanup_module); | |
3434 | ||
3435 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
3436 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
3437 | MODULE_LICENSE("GPL"); | |
5f4f9dc1 | 3438 | MODULE_VERSION(DRV_VERSION); |