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sky2: fix PM related regressions
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
743d32ad 54#define DRV_VERSION "1.22"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
f4331a6d
SH		 79#define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
e6cac9ba 101static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 141 { 0 }
142};
793b883e 143
cd28ab6a
SH		 144MODULE_DEVICE_TABLE(pci, sky2_id_table);
145
146/* Avoid conditionals by using array */
147static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
148static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 149static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 150
d1b139c0
SH		 151static void sky2_set_multicast(struct net_device *dev);
152
af043aa5 153/* Access to PHY via serial interconnect */
ef743d33 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 155{
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 163 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
164 if (ctrl == 0xffff)
165 goto io_error;
166
167 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 168 return 0;
af043aa5
SH		 169
170 udelay(10);
cd28ab6a 171 }
ef743d33 172
af043aa5 173 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 174 return -ETIMEDOUT;
af043aa5
SH		 175
176io_error:
177 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
178 return -EIO;
cd28ab6a
SH		 179}
180
ef743d33 181static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 182{
183 int i;
184
793b883e 185 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 186 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187
188 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 189 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
190 if (ctrl == 0xffff)
191 goto io_error;
192
193 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 194 *val = gma_read16(hw, port, GM_SMI_DATA);
195 return 0;
196 }
197
af043aa5 198 udelay(10);
cd28ab6a
SH		 199 }
200
af043aa5 201 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 202 return -ETIMEDOUT;
af043aa5
SH		 203io_error:
204 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
205 return -EIO;
ef743d33
SH		 206}
207
af043aa5 208static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 209{
210 u16 v;
af043aa5 211 __gm_phy_read(hw, port, reg, &v);
ef743d33 212 return v;
cd28ab6a
SH		 213}
214
5afa0a9c 215
ae306cca
SH		 216static void sky2_power_on(struct sky2_hw *hw)
217{
218 /* switch power to VCC (WA for VAUX problem) */
219 sky2_write8(hw, B0_POWER_CTRL,
220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 221
ae306cca
SH		 222 /* disable Core Clock Division, */
223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 224
ae306cca
SH		 225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
226 /* enable bits are inverted */
227 sky2_write8(hw, B2_Y2_CLK_GATE,
228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 else
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 233
ea76e635 234 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 235 u32 reg;
5afa0a9c 236
b32f40c4 237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 238
b32f40c4 239 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 240 /* set all bits to 0 except bits 15..12 and 8 */
241 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 242 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 243
b32f40c4 244 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 245 /* set all bits to 0 except bits 28 & 27 */
246 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 247 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 248
b32f40c4 249 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 250
251 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
252 reg = sky2_read32(hw, B2_GP_IO);
253 reg |= GLB_GPIO_STAT_RACE_DIS;
254 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 255
256 sky2_read32(hw, B2_GP_IO);
5afa0a9c 257 }
ae306cca 258}
5afa0a9c 259
ae306cca
SH		 260static void sky2_power_aux(struct sky2_hw *hw)
261{
262 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
263 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
264 else
265 /* enable bits are inverted */
266 sky2_write8(hw, B2_Y2_CLK_GATE,
267 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
268 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
269 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
270
271 /* switch power to VAUX */
272 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
273 sky2_write8(hw, B0_POWER_CTRL,
274 (PC_VAUX_ENA | PC_VCC_ENA |
275 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 276}
277
d3bcfbeb 278static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 279{
280 u16 reg;
281
282 /* disable all GMAC IRQ's */
283 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 284
cd28ab6a
SH		 285 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
286 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
288 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
289
290 reg = gma_read16(hw, port, GM_RX_CTRL);
291 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
292 gma_write16(hw, port, GM_RX_CTRL, reg);
293}
294
16ad91e1
SH		 295/* flow control to advertise bits */
296static const u16 copper_fc_adv[] = {
297 [FC_NONE] = 0,
298 [FC_TX] = PHY_M_AN_ASP,
299 [FC_RX] = PHY_M_AN_PC,
300 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
301};
302
303/* flow control to advertise bits when using 1000BaseX */
304static const u16 fiber_fc_adv[] = {
df3fe1f3 305 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 306 [FC_TX] = PHY_M_P_ASYM_MD_X,
307 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 308 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 309};
310
311/* flow control to GMA disable bits */
312static const u16 gm_fc_disable[] = {
313 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
314 [FC_TX] = GM_GPCR_FC_RX_DIS,
315 [FC_RX] = GM_GPCR_FC_TX_DIS,
316 [FC_BOTH] = 0,
317};
318
319
cd28ab6a
SH		 320static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
321{
322 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 323 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 324
ea76e635
SH		 325 if (sky2->autoneg == AUTONEG_ENABLE &&
326 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 327 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
328
329 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 330 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 331 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
332
53419c68 333 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 334 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 335 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 336 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
337 else
53419c68
SH		 338 /* set master & slave downshift counter to 1x */
339 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 340
341 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
342 }
343
344 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 345 if (sky2_is_copper(hw)) {
05745c4a 346 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 347 /* enable automatic crossover */
348 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 349
350 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
351 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
352 u16 spec;
353
354 /* Enable Class A driver for FE+ A0 */
355 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
356 spec |= PHY_M_FESC_SEL_CL_A;
357 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
358 }
cd28ab6a
SH		 359 } else {
360 /* disable energy detect */
361 ctrl &= ~PHY_M_PC_EN_DET_MSK;
362
363 /* enable automatic crossover */
364 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
365
53419c68 366 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 367 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 368 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 369 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 370 ctrl &= ~PHY_M_PC_DSC_MSK;
371 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
372 }
373 }
cd28ab6a
SH		 374 } else {
375 /* workaround for deviation #4.88 (CRC errors) */
376 /* disable Automatic Crossover */
377
378 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 379 }
cd28ab6a 380
b89165f2
SH		 381 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
382
383 /* special setup for PHY 88E1112 Fiber */
ea76e635 384 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 385 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 386
b89165f2
SH		 387 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
389 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
390 ctrl &= ~PHY_M_MAC_MD_MSK;
391 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
392 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393
394 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 395 /* select page 1 to access Fiber registers */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 397
398 /* for SFP-module set SIGDET polarity to low */
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 402 }
b89165f2
SH		 403
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 405 }
406
7800fddc 407 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 408 ct1000 = 0;
409 adv = PHY_AN_CSMA;
2eaba1a2 410 reg = 0;
cd28ab6a
SH		 411
412 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 413 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 414 if (sky2->advertising & ADVERTISED_1000baseT_Full)
415 ct1000 |= PHY_M_1000C_AFD;
416 if (sky2->advertising & ADVERTISED_1000baseT_Half)
417 ct1000 |= PHY_M_1000C_AHD;
418 if (sky2->advertising & ADVERTISED_100baseT_Full)
419 adv |= PHY_M_AN_100_FD;
420 if (sky2->advertising & ADVERTISED_100baseT_Half)
421 adv |= PHY_M_AN_100_HD;
422 if (sky2->advertising & ADVERTISED_10baseT_Full)
423 adv |= PHY_M_AN_10_FD;
424 if (sky2->advertising & ADVERTISED_10baseT_Half)
425 adv |= PHY_M_AN_10_HD;
709c6e7b 426
16ad91e1 427 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 428 } else { /* special defines for FIBER (88E1040S only) */
429 if (sky2->advertising & ADVERTISED_1000baseT_Full)
430 adv |= PHY_M_AN_1000X_AFD;
431 if (sky2->advertising & ADVERTISED_1000baseT_Half)
432 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 433
16ad91e1 434 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 435 }
cd28ab6a
SH		 436
437 /* Restart Auto-negotiation */
438 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
439 } else {
440 /* forced speed/duplex settings */
441 ct1000 = PHY_M_1000C_MSE;
442
2eaba1a2
SH		 443 /* Disable auto update for duplex flow control and speed */
444 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 445
446 switch (sky2->speed) {
447 case SPEED_1000:
448 ctrl |= PHY_CT_SP1000;
2eaba1a2 449 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 450 break;
451 case SPEED_100:
452 ctrl |= PHY_CT_SP100;
2eaba1a2 453 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 454 break;
455 }
456
2eaba1a2
SH		 457 if (sky2->duplex == DUPLEX_FULL) {
458 reg |= GM_GPCR_DUP_FULL;
459 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 460 } else if (sky2->speed < SPEED_1000)
461 sky2->flow_mode = FC_NONE;
2eaba1a2 462
2eaba1a2 463
16ad91e1 464 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 465
466 /* Forward pause packets to GMAC? */
16ad91e1 467 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 468 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
469 else
470 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 471 }
472
2eaba1a2
SH		 473 gma_write16(hw, port, GM_GP_CTRL, reg);
474
05745c4a 475 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 476 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
477
478 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
479 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
480
481 /* Setup Phy LED's */
482 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
483 ledover = 0;
484
485 switch (hw->chip_id) {
486 case CHIP_ID_YUKON_FE:
487 /* on 88E3082 these bits are at 11..9 (shifted left) */
488 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
489
490 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
491
492 /* delete ACT LED control bits */
493 ctrl &= ~PHY_M_FELP_LED1_MSK;
494 /* change ACT LED control to blink mode */
495 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
496 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
497 break;
498
05745c4a
SH		 499 case CHIP_ID_YUKON_FE_P:
500 /* Enable Link Partner Next Page */
501 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
502 ctrl |= PHY_M_PC_ENA_LIP_NP;
503
504 /* disable Energy Detect and enable scrambler */
505 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
507
508 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
509 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
510 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
511 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
512
513 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
514 break;
515
cd28ab6a 516 case CHIP_ID_YUKON_XL:
793b883e 517 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 518
519 /* select page 3 to access LED control register */
520 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
521
522 /* set LED Function Control register */
ed6d32c7
SH		 523 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
524 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
525 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
526 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
527 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 528
529 /* set Polarity Control register */
530 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 531 (PHY_M_POLC_LS1_P_MIX(4) |
532 PHY_M_POLC_IS0_P_MIX(4) |
533 PHY_M_POLC_LOS_CTRL(2) |
534 PHY_M_POLC_INIT_CTRL(2) |
535 PHY_M_POLC_STA1_CTRL(2) |
536 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 537
538 /* restore page register */
793b883e 539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 540 break;
93745494 541
ed6d32c7 542 case CHIP_ID_YUKON_EC_U:
93745494 543 case CHIP_ID_YUKON_EX:
ed4d4161 544 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 545 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
546
547 /* select page 3 to access LED control register */
548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
549
550 /* set LED Function Control register */
551 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
552 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
553 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
554 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
555 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
556
557 /* set Blink Rate in LED Timer Control Register */
558 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
559 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
560 /* restore page register */
561 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
562 break;
cd28ab6a
SH		 563
564 default:
565 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
566 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 567
cd28ab6a 568 /* turn off the Rx LED (LED_RX) */
a84d0a3d 569 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 570 }
571
0ce8b98d 572 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 573 /* apply fixes in PHY AFE */
ed6d32c7
SH		 574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
575
977bdf06 576 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 577 gm_phy_write(hw, port, 0x18, 0xaa99);
578 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 579
0ce8b98d
SH		 580 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
581 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
582 gm_phy_write(hw, port, 0x18, 0xa204);
583 gm_phy_write(hw, port, 0x17, 0x2002);
584 }
977bdf06
SH		 585
586 /* set page register to 0 */
9467a8fc 587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 588 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
589 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
590 /* apply workaround for integrated resistors calibration */
591 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
592 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 593 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
594 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 595 /* no effect on Yukon-XL */
977bdf06 596 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 597
977bdf06
SH		 598 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
599 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 600 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 601 }
cd28ab6a 602
977bdf06
SH		 603 if (ledover)
604 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
605
606 }
2eaba1a2 607
d571b694 608 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 609 if (sky2->autoneg == AUTONEG_ENABLE)
610 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
611 else
612 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
613}
614
b96936da
SH		 615static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
616static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
617
618static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 619{
620 u32 reg1;
d3bcfbeb 621
82637e80 622 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 623 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 624 reg1 &= ~phy_power[port];
d3bcfbeb 625
b96936da 626 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 627 reg1 |= coma_mode[port];
628
b32f40c4 629 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 630 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
631 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 632
633 if (hw->chip_id == CHIP_ID_YUKON_FE)
634 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
635 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
636 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 637}
167f53d0 638
b96936da
SH		 639static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
640{
641 u32 reg1;
db99b988
SH		 642 u16 ctrl;
643
644 /* release GPHY Control reset */
645 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
646
647 /* release GMAC reset */
648 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
649
650 if (hw->flags & SKY2_HW_NEWER_PHY) {
651 /* select page 2 to access MAC control register */
652 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
653
654 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
655 /* allow GMII Power Down */
656 ctrl &= ~PHY_M_MAC_GMIF_PUP;
657 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
658
659 /* set page register back to 0 */
660 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
661 }
662
663 /* setup General Purpose Control Register */
664 gma_write16(hw, port, GM_GP_CTRL,
665 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
666
667 if (hw->chip_id != CHIP_ID_YUKON_EC) {
668 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
669 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
670
671 /* enable Power Down */
672 ctrl |= PHY_M_PC_POW_D_ENA;
673 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
674 }
675
676 /* set IEEE compatible Power Down Mode (dev. #4.99) */
677 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
678 }
b96936da
SH		 679
680 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
681 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 682 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 683 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 685}
686
1b537565
SH		 687/* Force a renegotiation */
688static void sky2_phy_reinit(struct sky2_port *sky2)
689{
e07b1aa8 690 spin_lock_bh(&sky2->phy_lock);
1b537565 691 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 692 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 693}
694
e3173832
SH		 695/* Put device in state to listen for Wake On Lan */
696static void sky2_wol_init(struct sky2_port *sky2)
697{
698 struct sky2_hw *hw = sky2->hw;
699 unsigned port = sky2->port;
700 enum flow_control save_mode;
701 u16 ctrl;
702 u32 reg1;
703
704 /* Bring hardware out of reset */
705 sky2_write16(hw, B0_CTST, CS_RST_CLR);
706 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
707
708 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
709 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
710
711 /* Force to 10/100
712 * sky2_reset will re-enable on resume
713 */
714 save_mode = sky2->flow_mode;
715 ctrl = sky2->advertising;
716
717 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
718 sky2->flow_mode = FC_NONE;
b96936da
SH		 719
720 spin_lock_bh(&sky2->phy_lock);
721 sky2_phy_power_up(hw, port);
722 sky2_phy_init(hw, port);
723 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 724
725 sky2->flow_mode = save_mode;
726 sky2->advertising = ctrl;
727
728 /* Set GMAC to no flow control and auto update for speed/duplex */
729 gma_write16(hw, port, GM_GP_CTRL,
730 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
731 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
732
733 /* Set WOL address */
734 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
735 sky2->netdev->dev_addr, ETH_ALEN);
736
737 /* Turn on appropriate WOL control bits */
738 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
739 ctrl = 0;
740 if (sky2->wol & WAKE_PHY)
741 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
742 else
743 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
744
745 if (sky2->wol & WAKE_MAGIC)
746 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
747 else
748 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
749
750 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
751 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
752
753 /* Turn on legacy PCI-Express PME mode */
b32f40c4 754 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 755 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 756 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 757
758 /* block receiver */
759 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
760
761}
762
69161611
SH		 763static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
764{
05745c4a
SH		 765 struct net_device *dev = hw->dev[port];
766
ed4d4161
SH		 767 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
768 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
769 hw->chip_id == CHIP_ID_YUKON_FE_P ||
770 hw->chip_id == CHIP_ID_YUKON_SUPR) {
771 /* Yukon-Extreme B0 and further Extreme devices */
772 /* enable Store & Forward mode for TX */
05745c4a 773
ed4d4161
SH		 774 if (dev->mtu <= ETH_DATA_LEN)
775 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
776 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 777
ed4d4161
SH		 778 else
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_ENA| TX_STFW_ENA);
781 } else {
782 if (dev->mtu <= ETH_DATA_LEN)
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
784 else {
785 /* set Tx GMAC FIFO Almost Empty Threshold */
786 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
787 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 788
ed4d4161
SH		 789 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
790
791 /* Can't do offload because of lack of store/forward */
792 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
793 }
69161611
SH		 794 }
795}
796
cd28ab6a
SH		 797static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
798{
799 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
800 u16 reg;
25cccecc 801 u32 rx_reg;
cd28ab6a
SH		 802 int i;
803 const u8 *addr = hw->dev[port]->dev_addr;
804
f350339c
SH		 805 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
806 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 807
808 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
809
793b883e 810 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 811 /* WA DEV_472 -- looks like crossed wires on port 2 */
812 /* clear GMAC 1 Control reset */
813 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
814 do {
815 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
816 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
817 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
818 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
819 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
820 }
821
793b883e 822 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 823
2eaba1a2
SH		 824 /* Enable Transmit FIFO Underrun */
825 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
826
e07b1aa8 827 spin_lock_bh(&sky2->phy_lock);
b96936da 828 sky2_phy_power_up(hw, port);
cd28ab6a 829 sky2_phy_init(hw, port);
e07b1aa8 830 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 831
832 /* MIB clear */
833 reg = gma_read16(hw, port, GM_PHY_ADDR);
834 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
835
43f2f104
SH		 836 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
837 gma_read16(hw, port, i);
cd28ab6a
SH		 838 gma_write16(hw, port, GM_PHY_ADDR, reg);
839
840 /* transmit control */
841 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
842
843 /* receive control reg: unicast + multicast + no FCS */
844 gma_write16(hw, port, GM_RX_CTRL,
793b883e 845 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 846
847 /* transmit flow control */
848 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
849
850 /* transmit parameter */
851 gma_write16(hw, port, GM_TX_PARAM,
852 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
853 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
854 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
855 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
856
857 /* serial mode register */
858 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 859 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 860
6b1a3aef 861 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 862 reg |= GM_SMOD_JUMBO_ENA;
863
864 gma_write16(hw, port, GM_SERIAL_MODE, reg);
865
cd28ab6a
SH		 866 /* virtual address for data */
867 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
868
793b883e
SH		 869 /* physical address: used for pause frames */
870 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
871
872 /* ignore counter overflows */
cd28ab6a
SH		 873 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
874 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
875 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
876
877 /* Configure Rx MAC FIFO */
878 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 879 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 880 if (hw->chip_id == CHIP_ID_YUKON_EX ||
881 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 882 rx_reg |= GMF_RX_OVER_ON;
69161611 883
25cccecc 884 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 885
798fdd07
SH		 886 if (hw->chip_id == CHIP_ID_YUKON_XL) {
887 /* Hardware errata - clear flush mask */
888 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
889 } else {
890 /* Flush Rx MAC FIFO on any flow control or error */
891 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
892 }
cd28ab6a 893
8df9a876 894 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 895 reg = RX_GMF_FL_THR_DEF + 1;
896 /* Another magic mystery workaround from sk98lin */
897 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
898 hw->chip_rev == CHIP_REV_YU_FE2_A0)
899 reg = 0x178;
900 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 901
902 /* Configure Tx MAC FIFO */
903 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
904 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 905
e0c28116 906 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 907 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 908 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 909 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 910
69161611 911 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 912 }
913
e970d1f8
SH		 914 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
915 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
916 /* disable dynamic watermark */
917 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
918 reg &= ~TX_DYN_WM_ENA;
919 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
920 }
cd28ab6a
SH		 921}
922
67712901
SH		 923/* Assign Ram Buffer allocation to queue */
924static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 925{
67712901
SH		 926 u32 end;
927
928 /* convert from K bytes to qwords used for hw register */
929 start *= 1024/8;
930 space *= 1024/8;
931 end = start + space - 1;
793b883e 932
cd28ab6a
SH		 933 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
934 sky2_write32(hw, RB_ADDR(q, RB_START), start);
935 sky2_write32(hw, RB_ADDR(q, RB_END), end);
936 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
937 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
938
939 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 940 u32 tp = space - space/4;
793b883e 941
1c28f6ba
SH		 942 /* On receive queue's set the thresholds
943 * give receiver priority when > 3/4 full
944 * send pause when down to 2K
945 */
946 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
947 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 948
1c28f6ba
SH		 949 tp = space - 2048/8;
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 952 } else {
953 /* Enable store & forward on Tx queue's because
954 * Tx FIFO is only 1K on Yukon
955 */
956 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
957 }
958
959 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 960 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 961}
962
cd28ab6a 963/* Setup Bus Memory Interface */
af4ed7e6 964static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 965{
966 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
967 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
968 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 969 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 970}
971
cd28ab6a
SH		 972/* Setup prefetch unit registers. This is the interface between
973 * hardware and driver list elements
974 */
8cc048e3 975static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 976 u64 addr, u32 last)
977{
cd28ab6a
SH		 978 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
979 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
980 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
981 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
982 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 984
985 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 986}
987
793b883e
SH		 988static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
989{
990 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
991
cb5d9547 992 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 993 le->ctrl = 0;
793b883e
SH		 994 return le;
995}
cd28ab6a 996
88f5f0ca
SH		 997static void tx_init(struct sky2_port *sky2)
998{
999 struct sky2_tx_le *le;
1000
1001 sky2->tx_prod = sky2->tx_cons = 0;
1002 sky2->tx_tcpsum = 0;
1003 sky2->tx_last_mss = 0;
1004
1005 le = get_tx_le(sky2);
1006 le->addr = 0;
1007 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1008}
1009
291ea614
SH		 1010static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1011 struct sky2_tx_le *le)
1012{
1013 return sky2->tx_ring + (le - sky2->tx_le);
1014}
1015
290d4de5
SH		 1016/* Update chip's next pointer */
1017static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1018{
50432cb5 1019 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1020 wmb();
50432cb5
SH		 1021 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1022
1023 /* Synchronize I/O on since next processor may write to tail */
1024 mmiowb();
cd28ab6a
SH		 1025}
1026
793b883e 1027
cd28ab6a
SH		 1028static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1029{
1030 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1031 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1032 le->ctrl = 0;
cd28ab6a
SH		 1033 return le;
1034}
1035
14d0263f
SH		 1036/* Build description to hardware for one receive segment */
1037static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1038 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1039{
1040 struct sky2_rx_le *le;
1041
86c6887e 1042 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1043 le = sky2_next_rx(sky2);
86c6887e 1044 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1045 le->opcode = OP_ADDR64 | HW_OWNER;
1046 }
793b883e 1047
cd28ab6a 1048 le = sky2_next_rx(sky2);
734d1868
SH		 1049 le->addr = cpu_to_le32((u32) map);
1050 le->length = cpu_to_le16(len);
14d0263f 1051 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1052}
1053
14d0263f
SH		 1054/* Build description to hardware for one possibly fragmented skb */
1055static void sky2_rx_submit(struct sky2_port *sky2,
1056 const struct rx_ring_info *re)
1057{
1058 int i;
1059
1060 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1061
1062 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1063 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1064}
1065
1066
1067static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1068 unsigned size)
1069{
1070 struct sk_buff *skb = re->skb;
1071 int i;
1072
1073 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1074 pci_unmap_len_set(re, data_size, size);
1075
1076 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1077 re->frag_addr[i] = pci_map_page(pdev,
1078 skb_shinfo(skb)->frags[i].page,
1079 skb_shinfo(skb)->frags[i].page_offset,
1080 skb_shinfo(skb)->frags[i].size,
1081 PCI_DMA_FROMDEVICE);
1082}
1083
1084static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1085{
1086 struct sk_buff *skb = re->skb;
1087 int i;
1088
1089 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1090 PCI_DMA_FROMDEVICE);
1091
1092 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1093 pci_unmap_page(pdev, re->frag_addr[i],
1094 skb_shinfo(skb)->frags[i].size,
1095 PCI_DMA_FROMDEVICE);
1096}
793b883e 1097
cd28ab6a
SH		 1098/* Tell chip where to start receive checksum.
1099 * Actually has two checksums, but set both same to avoid possible byte
1100 * order problems.
1101 */
793b883e 1102static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1103{
ea76e635 1104 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1105
ea76e635
SH		 1106 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1107 le->ctrl = 0;
1108 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1109
ea76e635
SH		 1110 sky2_write32(sky2->hw,
1111 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1112 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1113}
1114
6b1a3aef
SH		 1115/*
1116 * The RX Stop command will not work for Yukon-2 if the BMU does not
1117 * reach the end of packet and since we can't make sure that we have
1118 * incoming data, we must reset the BMU while it is not doing a DMA
1119 * transfer. Since it is possible that the RX path is still active,
1120 * the RX RAM buffer will be stopped first, so any possible incoming
1121 * data will not trigger a DMA. After the RAM buffer is stopped, the
1122 * BMU is polled until any DMA in progress is ended and only then it
1123 * will be reset.
1124 */
1125static void sky2_rx_stop(struct sky2_port *sky2)
1126{
1127 struct sky2_hw *hw = sky2->hw;
1128 unsigned rxq = rxqaddr[sky2->port];
1129 int i;
1130
1131 /* disable the RAM Buffer receive queue */
1132 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1133
1134 for (i = 0; i < 0xffff; i++)
1135 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1136 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1137 goto stopped;
1138
1139 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1140 sky2->netdev->name);
1141stopped:
1142 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1143
1144 /* reset the Rx prefetch unit */
1145 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1146 mmiowb();
6b1a3aef 1147}
793b883e 1148
d571b694 1149/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1150static void sky2_rx_clean(struct sky2_port *sky2)
1151{
1152 unsigned i;
1153
1154 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1155 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1156 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1157
1158 if (re->skb) {
14d0263f 1159 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1160 kfree_skb(re->skb);
1161 re->skb = NULL;
1162 }
1163 }
1164}
1165
ef743d33
SH		 1166/* Basic MII support */
1167static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1168{
1169 struct mii_ioctl_data *data = if_mii(ifr);
1170 struct sky2_port *sky2 = netdev_priv(dev);
1171 struct sky2_hw *hw = sky2->hw;
1172 int err = -EOPNOTSUPP;
1173
1174 if (!netif_running(dev))
1175 return -ENODEV; /* Phy still in reset */
1176
d89e1343 1177 switch (cmd) {
ef743d33
SH		 1178 case SIOCGMIIPHY:
1179 data->phy_id = PHY_ADDR_MARV;
1180
1181 /* fallthru */
1182 case SIOCGMIIREG: {
1183 u16 val = 0;
91c86df5 1184
e07b1aa8 1185 spin_lock_bh(&sky2->phy_lock);
ef743d33 1186 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1187 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1188
ef743d33
SH		 1189 data->val_out = val;
1190 break;
1191 }
1192
1193 case SIOCSMIIREG:
1194 if (!capable(CAP_NET_ADMIN))
1195 return -EPERM;
1196
e07b1aa8 1197 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1198 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1199 data->val_in);
e07b1aa8 1200 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1201 break;
1202 }
1203 return err;
1204}
1205
d1f13708 1206#ifdef SKY2_VLAN_TAG_USED
d494eacd 1207static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1208{
d494eacd 1209 if (onoff) {
3d4e66f5
SH		 1210 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1211 RX_VLAN_STRIP_ON);
1212 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1213 TX_VLAN_TAG_ON);
1214 } else {
1215 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1216 RX_VLAN_STRIP_OFF);
1217 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1218 TX_VLAN_TAG_OFF);
1219 }
d494eacd
SH		 1220}
1221
1222static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1223{
1224 struct sky2_port *sky2 = netdev_priv(dev);
1225 struct sky2_hw *hw = sky2->hw;
1226 u16 port = sky2->port;
1227
1228 netif_tx_lock_bh(dev);
1229 napi_disable(&hw->napi);
1230
1231 sky2->vlgrp = grp;
1232 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1233
d1d08d12 1234 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1235 napi_enable(&hw->napi);
2bb8c262 1236 netif_tx_unlock_bh(dev);
d1f13708
SH		 1237}
1238#endif
1239
82788c7a 1240/*
14d0263f
SH		 1241 * Allocate an skb for receiving. If the MTU is large enough
1242 * make the skb non-linear with a fragment list of pages.
82788c7a 1243 */
14d0263f 1244static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1245{
1246 struct sk_buff *skb;
14d0263f 1247 int i;
82788c7a 1248
39dbd958 1249 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1250 unsigned char *start;
1251 /*
1252 * Workaround for a bug in FIFO that cause hang
1253 * if the FIFO if the receive buffer is not 64 byte aligned.
1254 * The buffer returned from netdev_alloc_skb is
1255 * aligned except if slab debugging is enabled.
1256 */
1257 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1258 if (!skb)
1259 goto nomem;
1260 start = PTR_ALIGN(skb->data, 8);
1261 skb_reserve(skb, start - skb->data);
1262 } else {
1263 skb = netdev_alloc_skb(sky2->netdev,
1264 sky2->rx_data_size + NET_IP_ALIGN);
1265 if (!skb)
1266 goto nomem;
1267 skb_reserve(skb, NET_IP_ALIGN);
1268 }
14d0263f
SH		 1269
1270 for (i = 0; i < sky2->rx_nfrags; i++) {
1271 struct page *page = alloc_page(GFP_ATOMIC);
1272
1273 if (!page)
1274 goto free_partial;
1275 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1276 }
1277
1278 return skb;
14d0263f
SH		 1279free_partial:
1280 kfree_skb(skb);
1281nomem:
1282 return NULL;
82788c7a
SH		 1283}
1284
55c9dd35
SH		 1285static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1286{
1287 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1288}
1289
cd28ab6a
SH		 1290/*
1291 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1292 * Normal case this ends up creating one list element for skb
1293 * in the receive ring. Worst case if using large MTU and each
1294 * allocation falls on a different 64 bit region, that results
1295 * in 6 list elements per ring entry.
1296 * One element is used for checksum enable/disable, and one
1297 * extra to avoid wrap.
cd28ab6a 1298 */
6b1a3aef 1299static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1300{
6b1a3aef 1301 struct sky2_hw *hw = sky2->hw;
14d0263f 1302 struct rx_ring_info *re;
6b1a3aef 1303 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1304 unsigned i, size, thresh;
cd28ab6a 1305
6b1a3aef 1306 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1307 sky2_qset(hw, rxq);
977bdf06 1308
c3905bc4
SH		 1309 /* On PCI express lowering the watermark gives better performance */
1310 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1311 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1312
1313 /* These chips have no ram buffer?
1314 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1315 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1316 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1317 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1318 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1319
6b1a3aef
SH		 1320 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1321
ea76e635
SH		 1322 if (!(hw->flags & SKY2_HW_NEW_LE))
1323 rx_set_checksum(sky2);
14d0263f
SH		 1324
1325 /* Space needed for frame data + headers rounded up */
f957da2a 1326 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1327
1328 /* Stopping point for hardware truncation */
1329 thresh = (size - 8) / sizeof(u32);
1330
5f06eba4 1331 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1332 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1333
5f06eba4
SH		 1334 /* Compute residue after pages */
1335 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1336
5f06eba4
SH		 1337 /* Optimize to handle small packets and headers */
1338 if (size < copybreak)
1339 size = copybreak;
1340 if (size < ETH_HLEN)
1341 size = ETH_HLEN;
14d0263f 1342
14d0263f
SH		 1343 sky2->rx_data_size = size;
1344
1345 /* Fill Rx ring */
793b883e 1346 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1347 re = sky2->rx_ring + i;
cd28ab6a 1348
14d0263f 1349 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1350 if (!re->skb)
1351 goto nomem;
1352
14d0263f
SH		 1353 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1354 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1355 }
1356
a1433ac4
SH		 1357 /*
1358 * The receiver hangs if it receives frames larger than the
1359 * packet buffer. As a workaround, truncate oversize frames, but
1360 * the register is limited to 9 bits, so if you do frames > 2052
1361 * you better get the MTU right!
1362 */
a1433ac4
SH		 1363 if (thresh > 0x1ff)
1364 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1365 else {
1366 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1367 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1368 }
1369
6b1a3aef 1370 /* Tell chip about available buffers */
55c9dd35 1371 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1372 return 0;
1373nomem:
1374 sky2_rx_clean(sky2);
1375 return -ENOMEM;
1376}
1377
1378/* Bring up network interface. */
1379static int sky2_up(struct net_device *dev)
1380{
1381 struct sky2_port *sky2 = netdev_priv(dev);
1382 struct sky2_hw *hw = sky2->hw;
1383 unsigned port = sky2->port;
e0c28116 1384 u32 imask, ramsize;
ee7abb04 1385 int cap, err = -ENOMEM;
843a46f4 1386 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1387
ee7abb04
SH		 1388 /*
1389 * On dual port PCI-X card, there is an problem where status
1390 * can be received out of order due to split transactions
843a46f4 1391 */
ee7abb04
SH		 1392 if (otherdev && netif_running(otherdev) &&
1393 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1394 u16 cmd;
1395
b32f40c4 1396 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1397 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1398 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1399
ee7abb04 1400 }
843a46f4 1401
cd28ab6a
SH		 1402 if (netif_msg_ifup(sky2))
1403 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1404
55d7b4e6
SH		 1405 netif_carrier_off(dev);
1406
cd28ab6a
SH		 1407 /* must be power of 2 */
1408 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1409 TX_RING_SIZE *
1410 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1411 &sky2->tx_le_map);
1412 if (!sky2->tx_le)
1413 goto err_out;
1414
6cdbbdf3 1415 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1416 GFP_KERNEL);
1417 if (!sky2->tx_ring)
1418 goto err_out;
88f5f0ca
SH		 1419
1420 tx_init(sky2);
cd28ab6a
SH		 1421
1422 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1423 &sky2->rx_le_map);
1424 if (!sky2->rx_le)
1425 goto err_out;
1426 memset(sky2->rx_le, 0, RX_LE_BYTES);
1427
291ea614 1428 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1429 GFP_KERNEL);
1430 if (!sky2->rx_ring)
1431 goto err_out;
1432
1433 sky2_mac_init(hw, port);
1434
e0c28116
SH		 1435 /* Register is number of 4K blocks on internal RAM buffer. */
1436 ramsize = sky2_read8(hw, B2_E_0) * 4;
1437 if (ramsize > 0) {
67712901 1438 u32 rxspace;
cd28ab6a 1439
39dbd958 1440 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1441 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1442 if (ramsize < 16)
1443 rxspace = ramsize / 2;
1444 else
1445 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1446
67712901
SH		 1447 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1448 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1449
1450 /* Make sure SyncQ is disabled */
1451 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1452 RB_RST_SET);
1453 }
793b883e 1454
af4ed7e6 1455 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1456
69161611
SH		 1457 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1458 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1459 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1460
977bdf06 1461 /* Set almost empty threshold */
c2716fb4
SH		 1462 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1463 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1464 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1465
6b1a3aef
SH		 1466 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1467 TX_RING_SIZE - 1);
cd28ab6a 1468
d494eacd
SH		 1469#ifdef SKY2_VLAN_TAG_USED
1470 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1471#endif
1472
6b1a3aef 1473 err = sky2_rx_start(sky2);
6de16237 1474 if (err)
cd28ab6a
SH		 1475 goto err_out;
1476
cd28ab6a 1477 /* Enable interrupts from phy/mac for port */
e07b1aa8 1478 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1479 imask |= portirq_msk[port];
e07b1aa8
SH		 1480 sky2_write32(hw, B0_IMSK, imask);
1481
a7bffe72 1482 sky2_set_multicast(dev);
cd28ab6a
SH		 1483 return 0;
1484
1485err_out:
1b537565 1486 if (sky2->rx_le) {
cd28ab6a
SH		 1487 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1488 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1489 sky2->rx_le = NULL;
1490 }
1491 if (sky2->tx_le) {
cd28ab6a
SH		 1492 pci_free_consistent(hw->pdev,
1493 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1494 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1495 sky2->tx_le = NULL;
1496 }
1497 kfree(sky2->tx_ring);
1498 kfree(sky2->rx_ring);
cd28ab6a 1499
1b537565
SH		 1500 sky2->tx_ring = NULL;
1501 sky2->rx_ring = NULL;
cd28ab6a
SH		 1502 return err;
1503}
1504
793b883e
SH		 1505/* Modular subtraction in ring */
1506static inline int tx_dist(unsigned tail, unsigned head)
1507{
cb5d9547 1508 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1509}
cd28ab6a 1510
793b883e
SH		 1511/* Number of list elements available for next tx */
1512static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1513{
793b883e 1514 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1515}
1516
793b883e 1517/* Estimate of number of transmit list elements required */
28bd181a 1518static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1519{
793b883e
SH		 1520 unsigned count;
1521
1522 count = sizeof(dma_addr_t) / sizeof(u32);
1523 count += skb_shinfo(skb)->nr_frags * count;
1524
89114afd 1525 if (skb_is_gso(skb))
793b883e
SH		 1526 ++count;
1527
84fa7933 1528 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1529 ++count;
1530
1531 return count;
cd28ab6a
SH		 1532}
1533
793b883e
SH		 1534/*
1535 * Put one packet in ring for transmit.
1536 * A single packet can generate multiple list elements, and
1537 * the number of ring elements will probably be less than the number
1538 * of list elements used.
1539 */
cd28ab6a
SH		 1540static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1541{
1542 struct sky2_port *sky2 = netdev_priv(dev);
1543 struct sky2_hw *hw = sky2->hw;
d1f13708 1544 struct sky2_tx_le *le = NULL;
6cdbbdf3 1545 struct tx_ring_info *re;
cd28ab6a
SH		 1546 unsigned i, len;
1547 dma_addr_t mapping;
cd28ab6a
SH		 1548 u16 mss;
1549 u8 ctrl;
1550
2bb8c262
SH		 1551 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1552 return NETDEV_TX_BUSY;
cd28ab6a 1553
793b883e 1554 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1555 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1556 dev->name, sky2->tx_prod, skb->len);
1557
cd28ab6a
SH		 1558 len = skb_headlen(skb);
1559 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1560
86c6887e
SH		 1561 /* Send high bits if needed */
1562 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1563 le = get_tx_le(sky2);
86c6887e 1564 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1565 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1566 }
cd28ab6a
SH		 1567
1568 /* Check for TCP Segmentation Offload */
7967168c 1569 mss = skb_shinfo(skb)->gso_size;
793b883e 1570 if (mss != 0) {
ea76e635
SH		 1571
1572 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1573 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1574
1575 if (mss != sky2->tx_last_mss) {
1576 le = get_tx_le(sky2);
1577 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1578
1579 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1580 le->opcode = OP_MSS | HW_OWNER;
1581 else
1582 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1583 sky2->tx_last_mss = mss;
1584 }
cd28ab6a
SH		 1585 }
1586
cd28ab6a 1587 ctrl = 0;
d1f13708
SH		 1588#ifdef SKY2_VLAN_TAG_USED
1589 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1590 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1591 if (!le) {
1592 le = get_tx_le(sky2);
f65b138c 1593 le->addr = 0;
d1f13708 1594 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1595 } else
1596 le->opcode |= OP_VLAN;
1597 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1598 ctrl |= INS_VLAN;
1599 }
1600#endif
1601
1602 /* Handle TCP checksum offload */
84fa7933 1603 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1604 /* On Yukon EX (some versions) encoding change. */
ea76e635 1605 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1606 ctrl |= CALSUM; /* auto checksum */
1607 else {
1608 const unsigned offset = skb_transport_offset(skb);
1609 u32 tcpsum;
1610
1611 tcpsum = offset << 16; /* sum start */
1612 tcpsum |= offset + skb->csum_offset; /* sum write */
1613
1614 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1615 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1616 ctrl |= UDPTCP;
1617
1618 if (tcpsum != sky2->tx_tcpsum) {
1619 sky2->tx_tcpsum = tcpsum;
1620
1621 le = get_tx_le(sky2);
1622 le->addr = cpu_to_le32(tcpsum);
1623 le->length = 0; /* initial checksum value */
1624 le->ctrl = 1; /* one packet */
1625 le->opcode = OP_TCPLISW | HW_OWNER;
1626 }
1d179332 1627 }
cd28ab6a
SH		 1628 }
1629
1630 le = get_tx_le(sky2);
f65b138c 1631 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1632 le->length = cpu_to_le16(len);
1633 le->ctrl = ctrl;
793b883e 1634 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1635
291ea614 1636 re = tx_le_re(sky2, le);
cd28ab6a 1637 re->skb = skb;
6cdbbdf3 1638 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1639 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1640
1641 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1642 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1643
1644 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1645 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1646
1647 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1648 le = get_tx_le(sky2);
86c6887e 1649 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1650 le->ctrl = 0;
1651 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1652 }
1653
1654 le = get_tx_le(sky2);
f65b138c 1655 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1656 le->length = cpu_to_le16(frag->size);
1657 le->ctrl = ctrl;
793b883e 1658 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1659
291ea614
SH		 1660 re = tx_le_re(sky2, le);
1661 re->skb = skb;
1662 pci_unmap_addr_set(re, mapaddr, mapping);
1663 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1664 }
6cdbbdf3 1665
cd28ab6a
SH		 1666 le->ctrl |= EOP;
1667
97bda706
SH		 1668 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1669 netif_stop_queue(dev);
b19666d9 1670
290d4de5 1671 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1672
cd28ab6a
SH		 1673 dev->trans_start = jiffies;
1674 return NETDEV_TX_OK;
1675}
1676
cd28ab6a 1677/*
793b883e
SH		 1678 * Free ring elements from starting at tx_cons until "done"
1679 *
1680 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1681 * buffers so make sure not to free skb to early.
cd28ab6a 1682 */
d11c13e7 1683static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1684{
d11c13e7 1685 struct net_device *dev = sky2->netdev;
af2a58ac 1686 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1687 unsigned idx;
cd28ab6a 1688
0e3ff6aa 1689 BUG_ON(done >= TX_RING_SIZE);
2224795d 1690
291ea614
SH		 1691 for (idx = sky2->tx_cons; idx != done;
1692 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1693 struct sky2_tx_le *le = sky2->tx_le + idx;
1694 struct tx_ring_info *re = sky2->tx_ring + idx;
1695
1696 switch(le->opcode & ~HW_OWNER) {
1697 case OP_LARGESEND:
1698 case OP_PACKET:
1699 pci_unmap_single(pdev,
1700 pci_unmap_addr(re, mapaddr),
1701 pci_unmap_len(re, maplen),
1702 PCI_DMA_TODEVICE);
af2a58ac 1703 break;
291ea614
SH		 1704 case OP_BUFFER:
1705 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1706 pci_unmap_len(re, maplen),
734d1868 1707 PCI_DMA_TODEVICE);
291ea614
SH		 1708 break;
1709 }
1710
1711 if (le->ctrl & EOP) {
1712 if (unlikely(netif_msg_tx_done(sky2)))
1713 printk(KERN_DEBUG "%s: tx done %u\n",
1714 dev->name, idx);
3cf26753 1715
7138a0f5
SH		 1716 dev->stats.tx_packets++;
1717 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1718
794b2bd2 1719 dev_kfree_skb_any(re->skb);
3cf26753 1720 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1721 }
793b883e 1722 }
793b883e 1723
291ea614 1724 sky2->tx_cons = idx;
50432cb5
SH		 1725 smp_mb();
1726
22e11703 1727 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1728 netif_wake_queue(dev);
cd28ab6a
SH		 1729}
1730
1731/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1732static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1733{
2bb8c262
SH		 1734 struct sky2_port *sky2 = netdev_priv(dev);
1735
1736 netif_tx_lock_bh(dev);
d11c13e7 1737 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1738 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1739}
1740
1741/* Network shutdown */
1742static int sky2_down(struct net_device *dev)
1743{
1744 struct sky2_port *sky2 = netdev_priv(dev);
1745 struct sky2_hw *hw = sky2->hw;
1746 unsigned port = sky2->port;
1747 u16 ctrl;
e07b1aa8 1748 u32 imask;
cd28ab6a 1749
1b537565
SH		 1750 /* Never really got started! */
1751 if (!sky2->tx_le)
1752 return 0;
1753
cd28ab6a
SH		 1754 if (netif_msg_ifdown(sky2))
1755 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1756
ebc646f6
SH		 1757 /* Disable port IRQ */
1758 imask = sky2_read32(hw, B0_IMSK);
1759 imask &= ~portirq_msk[port];
1760 sky2_write32(hw, B0_IMSK, imask);
1761
6de16237
SH		 1762 synchronize_irq(hw->pdev->irq);
1763
d3bcfbeb 1764 sky2_gmac_reset(hw, port);
793b883e 1765
cd28ab6a
SH		 1766 /* Stop transmitter */
1767 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1768 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1769
1770 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1771 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1772
1773 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1774 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1775 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1776
6de16237
SH		 1777 /* Make sure no packets are pending */
1778 napi_synchronize(&hw->napi);
1779
cd28ab6a
SH		 1780 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1781
1782 /* Workaround shared GMAC reset */
793b883e
SH		 1783 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1784 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1785 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1786
1787 /* Disable Force Sync bit and Enable Alloc bit */
1788 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1789 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1790
1791 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1792 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1793 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1794
1795 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1796 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1797 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1798
1799 /* Reset the Tx prefetch units */
1800 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1801 PREF_UNIT_RST_SET);
1802
1803 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1804
6b1a3aef 1805 sky2_rx_stop(sky2);
cd28ab6a
SH		 1806
1807 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1808 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1809
b96936da 1810 sky2_phy_power_down(hw, port);
d3bcfbeb 1811
d571b694 1812 /* turn off LED's */
cd28ab6a
SH		 1813 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1814
2bb8c262 1815 sky2_tx_clean(dev);
cd28ab6a
SH		 1816 sky2_rx_clean(sky2);
1817
1818 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1819 sky2->rx_le, sky2->rx_le_map);
1820 kfree(sky2->rx_ring);
1821
1822 pci_free_consistent(hw->pdev,
1823 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1824 sky2->tx_le, sky2->tx_le_map);
1825 kfree(sky2->tx_ring);
1826
1b537565
SH		 1827 sky2->tx_le = NULL;
1828 sky2->rx_le = NULL;
1829
1830 sky2->rx_ring = NULL;
1831 sky2->tx_ring = NULL;
1832
cd28ab6a
SH		 1833 return 0;
1834}
1835
1836static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1837{
ea76e635 1838 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1839 return SPEED_1000;
1840
05745c4a
SH		 1841 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1842 if (aux & PHY_M_PS_SPEED_100)
1843 return SPEED_100;
1844 else
1845 return SPEED_10;
1846 }
cd28ab6a
SH		 1847
1848 switch (aux & PHY_M_PS_SPEED_MSK) {
1849 case PHY_M_PS_SPEED_1000:
1850 return SPEED_1000;
1851 case PHY_M_PS_SPEED_100:
1852 return SPEED_100;
1853 default:
1854 return SPEED_10;
1855 }
1856}
1857
1858static void sky2_link_up(struct sky2_port *sky2)
1859{
1860 struct sky2_hw *hw = sky2->hw;
1861 unsigned port = sky2->port;
1862 u16 reg;
16ad91e1
SH		 1863 static const char *fc_name[] = {
1864 [FC_NONE] = "none",
1865 [FC_TX] = "tx",
1866 [FC_RX] = "rx",
1867 [FC_BOTH] = "both",
1868 };
cd28ab6a 1869
cd28ab6a 1870 /* enable Rx/Tx */
2eaba1a2 1871 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1872 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1873 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1874
1875 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1876
1877 netif_carrier_on(sky2->netdev);
cd28ab6a 1878
75e80683 1879 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1880
cd28ab6a 1881 /* Turn on link LED */
793b883e 1882 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1883 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1884
1885 if (netif_msg_link(sky2))
1886 printk(KERN_INFO PFX
d571b694 1887 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1888 sky2->netdev->name, sky2->speed,
1889 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1890 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1891}
1892
1893static void sky2_link_down(struct sky2_port *sky2)
1894{
1895 struct sky2_hw *hw = sky2->hw;
1896 unsigned port = sky2->port;
1897 u16 reg;
1898
1899 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1900
1901 reg = gma_read16(hw, port, GM_GP_CTRL);
1902 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1903 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1904
cd28ab6a 1905 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1906
1907 /* Turn on link LED */
1908 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1909
1910 if (netif_msg_link(sky2))
1911 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1912
cd28ab6a
SH		 1913 sky2_phy_init(hw, port);
1914}
1915
16ad91e1
SH		 1916static enum flow_control sky2_flow(int rx, int tx)
1917{
1918 if (rx)
1919 return tx ? FC_BOTH : FC_RX;
1920 else
1921 return tx ? FC_TX : FC_NONE;
1922}
1923
793b883e
SH		 1924static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1925{
1926 struct sky2_hw *hw = sky2->hw;
1927 unsigned port = sky2->port;
da4c1ff4 1928 u16 advert, lpa;
793b883e 1929
da4c1ff4 1930 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1931 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1932 if (lpa & PHY_M_AN_RF) {
1933 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1934 return -1;
1935 }
1936
793b883e
SH		 1937 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1938 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1939 sky2->netdev->name);
1940 return -1;
1941 }
1942
793b883e 1943 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1944 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1945
da4c1ff4
SH		 1946 /* Since the pause result bits seem to in different positions on
1947 * different chips. look at registers.
1948 */
ea76e635 1949 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1950 /* Shift for bits in fiber PHY */
1951 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1952 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1953
1954 if (advert & ADVERTISE_1000XPAUSE)
1955 advert |= ADVERTISE_PAUSE_CAP;
1956 if (advert & ADVERTISE_1000XPSE_ASYM)
1957 advert |= ADVERTISE_PAUSE_ASYM;
1958 if (lpa & LPA_1000XPAUSE)
1959 lpa |= LPA_PAUSE_CAP;
1960 if (lpa & LPA_1000XPAUSE_ASYM)
1961 lpa |= LPA_PAUSE_ASYM;
1962 }
793b883e 1963
da4c1ff4
SH		 1964 sky2->flow_status = FC_NONE;
1965 if (advert & ADVERTISE_PAUSE_CAP) {
1966 if (lpa & LPA_PAUSE_CAP)
1967 sky2->flow_status = FC_BOTH;
1968 else if (advert & ADVERTISE_PAUSE_ASYM)
1969 sky2->flow_status = FC_RX;
1970 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1971 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1972 sky2->flow_status = FC_TX;
1973 }
793b883e 1974
16ad91e1 1975 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1976 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1977 sky2->flow_status = FC_NONE;
2eaba1a2 1978
da4c1ff4 1979 if (sky2->flow_status & FC_TX)
793b883e
SH		 1980 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1981 else
1982 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1983
1984 return 0;
1985}
cd28ab6a 1986
e07b1aa8
SH		 1987/* Interrupt from PHY */
1988static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1989{
e07b1aa8
SH		 1990 struct net_device *dev = hw->dev[port];
1991 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1992 u16 istatus, phystat;
1993
ebc646f6
SH		 1994 if (!netif_running(dev))
1995 return;
1996
e07b1aa8
SH		 1997 spin_lock(&sky2->phy_lock);
1998 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1999 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2000
cd28ab6a
SH		 2001 if (netif_msg_intr(sky2))
2002 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2003 sky2->netdev->name, istatus, phystat);
2004
2eaba1a2 2005 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2006 if (sky2_autoneg_done(sky2, phystat) == 0)
2007 sky2_link_up(sky2);
2008 goto out;
2009 }
cd28ab6a 2010
793b883e
SH		 2011 if (istatus & PHY_M_IS_LSP_CHANGE)
2012 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2013
793b883e
SH		 2014 if (istatus & PHY_M_IS_DUP_CHANGE)
2015 sky2->duplex =
2016 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2017
793b883e
SH		 2018 if (istatus & PHY_M_IS_LST_CHANGE) {
2019 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2020 sky2_link_up(sky2);
793b883e
SH		 2021 else
2022 sky2_link_down(sky2);
cd28ab6a 2023 }
793b883e 2024out:
e07b1aa8 2025 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2026}
2027
62335ab0 2028/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2029 * and tx queue is full (stopped).
2030 */
cd28ab6a
SH		 2031static void sky2_tx_timeout(struct net_device *dev)
2032{
2033 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2034 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2035
2036 if (netif_msg_timer(sky2))
2037 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2038
8f24664d 2039 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2040 dev->name, sky2->tx_cons, sky2->tx_prod,
2041 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2042 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2043
81906791
SH		 2044 /* can't restart safely under softirq */
2045 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2046}
2047
2048static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2049{
6b1a3aef
SH		 2050 struct sky2_port *sky2 = netdev_priv(dev);
2051 struct sky2_hw *hw = sky2->hw;
b628ed98 2052 unsigned port = sky2->port;
6b1a3aef
SH		 2053 int err;
2054 u16 ctl, mode;
e07b1aa8 2055 u32 imask;
cd28ab6a
SH		 2056
2057 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2058 return -EINVAL;
2059
05745c4a
SH		 2060 if (new_mtu > ETH_DATA_LEN &&
2061 (hw->chip_id == CHIP_ID_YUKON_FE ||
2062 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2063 return -EINVAL;
2064
6b1a3aef
SH		 2065 if (!netif_running(dev)) {
2066 dev->mtu = new_mtu;
2067 return 0;
2068 }
2069
e07b1aa8 2070 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2071 sky2_write32(hw, B0_IMSK, 0);
2072
018d1c66
SH		 2073 dev->trans_start = jiffies; /* prevent tx timeout */
2074 netif_stop_queue(dev);
bea3348e 2075 napi_disable(&hw->napi);
018d1c66 2076
e07b1aa8
SH		 2077 synchronize_irq(hw->pdev->irq);
2078
39dbd958 2079 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2080 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2081
2082 ctl = gma_read16(hw, port, GM_GP_CTRL);
2083 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2084 sky2_rx_stop(sky2);
2085 sky2_rx_clean(sky2);
cd28ab6a
SH		 2086
2087 dev->mtu = new_mtu;
14d0263f 2088
6b1a3aef
SH		 2089 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2090 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2091
2092 if (dev->mtu > ETH_DATA_LEN)
2093 mode |= GM_SMOD_JUMBO_ENA;
2094
b628ed98 2095 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2096
b628ed98 2097 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2098
6b1a3aef 2099 err = sky2_rx_start(sky2);
e07b1aa8 2100 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2101
d1d08d12 2102 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2103 napi_enable(&hw->napi);
2104
1b537565
SH		 2105 if (err)
2106 dev_close(dev);
2107 else {
b628ed98 2108 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2109
1b537565
SH		 2110 netif_wake_queue(dev);
2111 }
2112
cd28ab6a
SH		 2113 return err;
2114}
2115
14d0263f
SH		 2116/* For small just reuse existing skb for next receive */
2117static struct sk_buff *receive_copy(struct sky2_port *sky2,
2118 const struct rx_ring_info *re,
2119 unsigned length)
2120{
2121 struct sk_buff *skb;
2122
2123 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2124 if (likely(skb)) {
2125 skb_reserve(skb, 2);
2126 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2127 length, PCI_DMA_FROMDEVICE);
d626f62b 2128 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2129 skb->ip_summed = re->skb->ip_summed;
2130 skb->csum = re->skb->csum;
2131 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2132 length, PCI_DMA_FROMDEVICE);
2133 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2134 skb_put(skb, length);
14d0263f
SH		 2135 }
2136 return skb;
2137}
2138
2139/* Adjust length of skb with fragments to match received data */
2140static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2141 unsigned int length)
2142{
2143 int i, num_frags;
2144 unsigned int size;
2145
2146 /* put header into skb */
2147 size = min(length, hdr_space);
2148 skb->tail += size;
2149 skb->len += size;
2150 length -= size;
2151
2152 num_frags = skb_shinfo(skb)->nr_frags;
2153 for (i = 0; i < num_frags; i++) {
2154 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2155
2156 if (length == 0) {
2157 /* don't need this page */
2158 __free_page(frag->page);
2159 --skb_shinfo(skb)->nr_frags;
2160 } else {
2161 size = min(length, (unsigned) PAGE_SIZE);
2162
2163 frag->size = size;
2164 skb->data_len += size;
2165 skb->truesize += size;
2166 skb->len += size;
2167 length -= size;
2168 }
2169 }
2170}
2171
2172/* Normal packet - take skb from ring element and put in a new one */
2173static struct sk_buff *receive_new(struct sky2_port *sky2,
2174 struct rx_ring_info *re,
2175 unsigned int length)
2176{
2177 struct sk_buff *skb, *nskb;
2178 unsigned hdr_space = sky2->rx_data_size;
2179
14d0263f
SH		 2180 /* Don't be tricky about reusing pages (yet) */
2181 nskb = sky2_rx_alloc(sky2);
2182 if (unlikely(!nskb))
2183 return NULL;
2184
2185 skb = re->skb;
2186 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2187
2188 prefetch(skb->data);
2189 re->skb = nskb;
2190 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2191
2192 if (skb_shinfo(skb)->nr_frags)
2193 skb_put_frags(skb, hdr_space, length);
2194 else
489b10c1 2195 skb_put(skb, length);
14d0263f
SH		 2196 return skb;
2197}
2198
cd28ab6a
SH		 2199/*
2200 * Receive one packet.
d571b694 2201 * For larger packets, get new buffer.
cd28ab6a 2202 */
497d7c86 2203static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2204 u16 length, u32 status)
2205{
497d7c86 2206 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2207 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2208 struct sk_buff *skb = NULL;
d6532232
SH		 2209 u16 count = (status & GMR_FS_LEN) >> 16;
2210
2211#ifdef SKY2_VLAN_TAG_USED
2212 /* Account for vlan tag */
2213 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2214 count -= VLAN_HLEN;
2215#endif
cd28ab6a
SH		 2216
2217 if (unlikely(netif_msg_rx_status(sky2)))
2218 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2219 dev->name, sky2->rx_next, status, length);
cd28ab6a 2220
793b883e 2221 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2222 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2223
3b12e014
SH		 2224 /* This chip has hardware problems that generates bogus status.
2225 * So do only marginal checking and expect higher level protocols
2226 * to handle crap frames.
2227 */
2228 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2229 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2230 length != count)
2231 goto okay;
2232
42eeea01 2233 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2234 goto error;
2235
42eeea01
SH		 2236 if (!(status & GMR_FS_RX_OK))
2237 goto resubmit;
2238
d6532232
SH		 2239 /* if length reported by DMA does not match PHY, packet was truncated */
2240 if (length != count)
3b12e014 2241 goto len_error;
71749531 2242
3b12e014 2243okay:
14d0263f
SH		 2244 if (length < copybreak)
2245 skb = receive_copy(sky2, re, length);
2246 else
2247 skb = receive_new(sky2, re, length);
793b883e 2248resubmit:
14d0263f 2249 sky2_rx_submit(sky2, re);
79e57d32 2250
cd28ab6a
SH		 2251 return skb;
2252
3b12e014 2253len_error:
71749531
SH		 2254 /* Truncation of overlength packets
2255 causes PHY length to not match MAC length */
7138a0f5 2256 ++dev->stats.rx_length_errors;
d6532232 2257 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2258 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2259 dev->name, status, length);
d6532232 2260 goto resubmit;
71749531 2261
cd28ab6a 2262error:
7138a0f5 2263 ++dev->stats.rx_errors;
b6d77734 2264 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2265 dev->stats.rx_over_errors++;
b6d77734
SH		 2266 goto resubmit;
2267 }
6e15b712 2268
3be92a70 2269 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2270 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2271 dev->name, status, length);
793b883e
SH		 2272
2273 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2274 dev->stats.rx_length_errors++;
cd28ab6a 2275 if (status & GMR_FS_FRAGMENT)
7138a0f5 2276 dev->stats.rx_frame_errors++;
cd28ab6a 2277 if (status & GMR_FS_CRC_ERR)
7138a0f5 2278 dev->stats.rx_crc_errors++;
79e57d32 2279
793b883e 2280 goto resubmit;
cd28ab6a
SH		 2281}
2282
e07b1aa8
SH		 2283/* Transmit complete */
2284static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2285{
e07b1aa8 2286 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2287
e07b1aa8 2288 if (netif_running(dev)) {
2bb8c262 2289 netif_tx_lock(dev);
e07b1aa8 2290 sky2_tx_complete(sky2, last);
2bb8c262 2291 netif_tx_unlock(dev);
2224795d 2292 }
cd28ab6a
SH		 2293}
2294
e07b1aa8 2295/* Process status response ring */
26691830 2296static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2297{
e07b1aa8 2298 int work_done = 0;
55c9dd35 2299 unsigned rx[2] = { 0, 0 };
a8fd6266 2300
af2a58ac 2301 rmb();
26691830 2302 do {
55c9dd35 2303 struct sky2_port *sky2;
13210ce5 2304 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2305 unsigned port;
13210ce5 2306 struct net_device *dev;
cd28ab6a 2307 struct sk_buff *skb;
cd28ab6a
SH		 2308 u32 status;
2309 u16 length;
ab5adecb
SH		 2310 u8 opcode = le->opcode;
2311
2312 if (!(opcode & HW_OWNER))
2313 break;
cd28ab6a 2314
cb5d9547 2315 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2316
ab5adecb 2317 port = le->css & CSS_LINK_BIT;
69161611 2318 dev = hw->dev[port];
13210ce5 2319 sky2 = netdev_priv(dev);
f65b138c
SH		 2320 length = le16_to_cpu(le->length);
2321 status = le32_to_cpu(le->status);
cd28ab6a 2322
ab5adecb
SH		 2323 le->opcode = 0;
2324 switch (opcode & ~HW_OWNER) {
cd28ab6a 2325 case OP_RXSTAT:
55c9dd35 2326 ++rx[port];
497d7c86 2327 skb = sky2_receive(dev, length, status);
3225b919 2328 if (unlikely(!skb)) {
7138a0f5 2329 dev->stats.rx_dropped++;
55c9dd35 2330 break;
3225b919 2331 }
13210ce5 2332
69161611 2333 /* This chip reports checksum status differently */
05745c4a 2334 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2335 if (sky2->rx_csum &&
2336 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2337 (le->css & CSS_TCPUDPCSOK))
2338 skb->ip_summed = CHECKSUM_UNNECESSARY;
2339 else
2340 skb->ip_summed = CHECKSUM_NONE;
2341 }
2342
13210ce5 2343 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2344 dev->stats.rx_packets++;
2345 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2346 dev->last_rx = jiffies;
2347
d1f13708
SH		 2348#ifdef SKY2_VLAN_TAG_USED
2349 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2350 vlan_hwaccel_receive_skb(skb,
2351 sky2->vlgrp,
2352 be16_to_cpu(sky2->rx_tag));
2353 } else
2354#endif
cd28ab6a 2355 netif_receive_skb(skb);
13210ce5 2356
22e11703 2357 /* Stop after net poll weight */
13210ce5
SH		 2358 if (++work_done >= to_do)
2359 goto exit_loop;
cd28ab6a
SH		 2360 break;
2361
d1f13708
SH		 2362#ifdef SKY2_VLAN_TAG_USED
2363 case OP_RXVLAN:
2364 sky2->rx_tag = length;
2365 break;
2366
2367 case OP_RXCHKSVLAN:
2368 sky2->rx_tag = length;
2369 /* fall through */
2370#endif
cd28ab6a 2371 case OP_RXCHKS:
87418307
SH		 2372 if (!sky2->rx_csum)
2373 break;
2374
05745c4a
SH		 2375 /* If this happens then driver assuming wrong format */
2376 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2377 if (net_ratelimit())
2378 printk(KERN_NOTICE "%s: unexpected"
2379 " checksum status\n",
2380 dev->name);
69161611 2381 break;
05745c4a 2382 }
69161611 2383
87418307
SH		 2384 /* Both checksum counters are programmed to start at
2385 * the same offset, so unless there is a problem they
2386 * should match. This failure is an early indication that
2387 * hardware receive checksumming won't work.
2388 */
2389 if (likely(status >> 16 == (status & 0xffff))) {
2390 skb = sky2->rx_ring[sky2->rx_next].skb;
2391 skb->ip_summed = CHECKSUM_COMPLETE;
2392 skb->csum = status & 0xffff;
2393 } else {
2394 printk(KERN_NOTICE PFX "%s: hardware receive "
2395 "checksum problem (status = %#x)\n",
2396 dev->name, status);
2397 sky2->rx_csum = 0;
2398 sky2_write32(sky2->hw,
69161611 2399 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2400 BMU_DIS_RX_CHKSUM);
2401 }
cd28ab6a
SH		 2402 break;
2403
2404 case OP_TXINDEXLE:
13b97b74 2405 /* TX index reports status for both ports */
f55925d7
SH		 2406 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2407 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2408 if (hw->dev[1])
2409 sky2_tx_done(hw->dev[1],
2410 ((status >> 24) & 0xff)
2411 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2412 break;
2413
cd28ab6a
SH		 2414 default:
2415 if (net_ratelimit())
793b883e 2416 printk(KERN_WARNING PFX
ab5adecb 2417 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2418 }
26691830 2419 } while (hw->st_idx != idx);
cd28ab6a 2420
fe2a24df
SH		 2421 /* Fully processed status ring so clear irq */
2422 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2423
13210ce5 2424exit_loop:
55c9dd35
SH		 2425 if (rx[0])
2426 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2427
55c9dd35
SH		 2428 if (rx[1])
2429 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2430
e07b1aa8 2431 return work_done;
cd28ab6a
SH		 2432}
2433
2434static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2435{
2436 struct net_device *dev = hw->dev[port];
2437
3be92a70
SH		 2438 if (net_ratelimit())
2439 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2440 dev->name, status);
cd28ab6a
SH		 2441
2442 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2443 if (net_ratelimit())
2444 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2445 dev->name);
cd28ab6a
SH		 2446 /* Clear IRQ */
2447 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2448 }
2449
2450 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2451 if (net_ratelimit())
2452 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2453 dev->name);
cd28ab6a
SH		 2454
2455 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2456 }
2457
2458 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2459 if (net_ratelimit())
2460 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2461 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2462 }
2463
2464 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2465 if (net_ratelimit())
2466 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2467 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2468 }
2469
2470 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2471 if (net_ratelimit())
2472 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2473 dev->name);
cd28ab6a
SH		 2474 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2475 }
2476}
2477
2478static void sky2_hw_intr(struct sky2_hw *hw)
2479{
555382cb 2480 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2481 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2482 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2483
2484 status &= hwmsk;
cd28ab6a 2485
793b883e 2486 if (status & Y2_IS_TIST_OV)
cd28ab6a 2487 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2488
2489 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2490 u16 pci_err;
2491
82637e80 2492 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2493 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2494 if (net_ratelimit())
555382cb 2495 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2496 pci_err);
cd28ab6a 2497
b32f40c4 2498 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2499 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2500 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2501 }
2502
2503 if (status & Y2_IS_PCI_EXP) {
d571b694 2504 /* PCI-Express uncorrectable Error occurred */
555382cb 2505 u32 err;
cd28ab6a 2506
82637e80 2507 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2508 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2509 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2510 0xfffffffful);
3be92a70 2511 if (net_ratelimit())
555382cb 2512 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2513
7782c8c4 2514 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2515 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2516 }
2517
2518 if (status & Y2_HWE_L1_MASK)
2519 sky2_hw_error(hw, 0, status);
2520 status >>= 8;
2521 if (status & Y2_HWE_L1_MASK)
2522 sky2_hw_error(hw, 1, status);
2523}
2524
2525static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2526{
2527 struct net_device *dev = hw->dev[port];
2528 struct sky2_port *sky2 = netdev_priv(dev);
2529 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2530
2531 if (netif_msg_intr(sky2))
2532 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2533 dev->name, status);
2534
a3caeada
SH		 2535 if (status & GM_IS_RX_CO_OV)
2536 gma_read16(hw, port, GM_RX_IRQ_SRC);
2537
2538 if (status & GM_IS_TX_CO_OV)
2539 gma_read16(hw, port, GM_TX_IRQ_SRC);
2540
cd28ab6a 2541 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2542 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2543 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2544 }
2545
2546 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2547 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2548 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2549 }
cd28ab6a
SH		 2550}
2551
40b01727
SH		 2552/* This should never happen it is a bug. */
2553static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2554 u16 q, unsigned ring_size)
d257924e
SH		 2555{
2556 struct net_device *dev = hw->dev[port];
2557 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2558 unsigned idx;
2559 const u64 *le = (q == Q_R1 || q == Q_R2)
2560 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2561
40b01727
SH		 2562 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2563 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2564 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2565 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2566
40b01727 2567 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2568}
cd28ab6a 2569
75e80683
SH		 2570static int sky2_rx_hung(struct net_device *dev)
2571{
2572 struct sky2_port *sky2 = netdev_priv(dev);
2573 struct sky2_hw *hw = sky2->hw;
2574 unsigned port = sky2->port;
2575 unsigned rxq = rxqaddr[port];
2576 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2577 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2578 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2579 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2580
2581 /* If idle and MAC or PCI is stuck */
2582 if (sky2->check.last == dev->last_rx &&
2583 ((mac_rp == sky2->check.mac_rp &&
2584 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2585 /* Check if the PCI RX hang */
2586 (fifo_rp == sky2->check.fifo_rp &&
2587 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2588 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2589 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2590 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2591 return 1;
2592 } else {
2593 sky2->check.last = dev->last_rx;
2594 sky2->check.mac_rp = mac_rp;
2595 sky2->check.mac_lev = mac_lev;
2596 sky2->check.fifo_rp = fifo_rp;
2597 sky2->check.fifo_lev = fifo_lev;
2598 return 0;
2599 }
2600}
2601
32c2c300 2602static void sky2_watchdog(unsigned long arg)
d27ed387 2603{
01bd7564 2604 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2605
75e80683 2606 /* Check for lost IRQ once a second */
32c2c300 2607 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2608 napi_schedule(&hw->napi);
75e80683
SH		 2609 } else {
2610 int i, active = 0;
2611
2612 for (i = 0; i < hw->ports; i++) {
bea3348e 2613 struct net_device *dev = hw->dev[i];
75e80683
SH		 2614 if (!netif_running(dev))
2615 continue;
2616 ++active;
2617
2618 /* For chips with Rx FIFO, check if stuck */
39dbd958 2619 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2620 sky2_rx_hung(dev)) {
2621 pr_info(PFX "%s: receiver hang detected\n",
2622 dev->name);
2623 schedule_work(&hw->restart_work);
2624 return;
2625 }
2626 }
2627
2628 if (active == 0)
2629 return;
32c2c300 2630 }
01bd7564 2631
75e80683 2632 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2633}
2634
40b01727
SH		 2635/* Hardware/software error handling */
2636static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2637{
40b01727
SH		 2638 if (net_ratelimit())
2639 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2640
1e5f1283
SH		 2641 if (status & Y2_IS_HW_ERR)
2642 sky2_hw_intr(hw);
d257924e 2643
1e5f1283
SH		 2644 if (status & Y2_IS_IRQ_MAC1)
2645 sky2_mac_intr(hw, 0);
cd28ab6a 2646
1e5f1283
SH		 2647 if (status & Y2_IS_IRQ_MAC2)
2648 sky2_mac_intr(hw, 1);
cd28ab6a 2649
1e5f1283 2650 if (status & Y2_IS_CHK_RX1)
40b01727 2651 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2652
1e5f1283 2653 if (status & Y2_IS_CHK_RX2)
40b01727 2654 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2655
1e5f1283 2656 if (status & Y2_IS_CHK_TXA1)
40b01727 2657 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2658
1e5f1283 2659 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2660 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2661}
2662
bea3348e 2663static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2664{
bea3348e 2665 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2666 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2667 int work_done = 0;
26691830 2668 u16 idx;
40b01727
SH		 2669
2670 if (unlikely(status & Y2_IS_ERROR))
2671 sky2_err_intr(hw, status);
2672
2673 if (status & Y2_IS_IRQ_PHY1)
2674 sky2_phy_intr(hw, 0);
2675
2676 if (status & Y2_IS_IRQ_PHY2)
2677 sky2_phy_intr(hw, 1);
cd28ab6a 2678
26691830
SH		 2679 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2680 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2681
2682 if (work_done >= work_limit)
26691830
SH		 2683 goto done;
2684 }
6f535763 2685
26691830
SH		 2686 /* Bug/Errata workaround?
2687 * Need to kick the TX irq moderation timer.
2688 */
2689 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2690 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2691 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2692 }
26691830
SH		 2693 napi_complete(napi);
2694 sky2_read32(hw, B0_Y2_SP_LISR);
2695done:
6f535763 2696
bea3348e 2697 return work_done;
e07b1aa8
SH		 2698}
2699
7d12e780 2700static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2701{
2702 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2703 u32 status;
2704
2705 /* Reading this mask interrupts as side effect */
2706 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2707 if (status == 0 || status == ~0)
2708 return IRQ_NONE;
793b883e 2709
e07b1aa8 2710 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2711
2712 napi_schedule(&hw->napi);
793b883e 2713
cd28ab6a
SH		 2714 return IRQ_HANDLED;
2715}
2716
2717#ifdef CONFIG_NET_POLL_CONTROLLER
2718static void sky2_netpoll(struct net_device *dev)
2719{
2720 struct sky2_port *sky2 = netdev_priv(dev);
2721
bea3348e 2722 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2723}
2724#endif
2725
2726/* Chip internal frequency for clock calculations */
05745c4a 2727static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2728{
793b883e 2729 switch (hw->chip_id) {
cd28ab6a 2730 case CHIP_ID_YUKON_EC:
5a5b1ea0 2731 case CHIP_ID_YUKON_EC_U:
93745494 2732 case CHIP_ID_YUKON_EX:
ed4d4161 2733 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2734 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2735 return 125;
2736
cd28ab6a 2737 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2738 return 100;
2739
2740 case CHIP_ID_YUKON_FE_P:
2741 return 50;
2742
2743 case CHIP_ID_YUKON_XL:
2744 return 156;
2745
2746 default:
2747 BUG();
cd28ab6a
SH		 2748 }
2749}
2750
fb17358f 2751static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2752{
fb17358f 2753 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2754}
2755
fb17358f 2756static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2757{
fb17358f 2758 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2759}
2760
fb17358f 2761
e3173832 2762static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2763{
b89165f2 2764 u8 t8;
cd28ab6a 2765
167f53d0 2766 /* Enable all clocks and check for bad PCI access */
b32f40c4 2767 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2768
cd28ab6a 2769 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2770
cd28ab6a 2771 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2772 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2773
2774 switch(hw->chip_id) {
2775 case CHIP_ID_YUKON_XL:
39dbd958 2776 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2777 break;
2778
2779 case CHIP_ID_YUKON_EC_U:
2780 hw->flags = SKY2_HW_GIGABIT
2781 | SKY2_HW_NEWER_PHY
2782 | SKY2_HW_ADV_POWER_CTL;
2783 break;
2784
2785 case CHIP_ID_YUKON_EX:
2786 hw->flags = SKY2_HW_GIGABIT
2787 | SKY2_HW_NEWER_PHY
2788 | SKY2_HW_NEW_LE
2789 | SKY2_HW_ADV_POWER_CTL;
2790
2791 /* New transmit checksum */
2792 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2793 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2794 break;
2795
2796 case CHIP_ID_YUKON_EC:
2797 /* This rev is really old, and requires untested workarounds */
2798 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2799 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2800 return -EOPNOTSUPP;
2801 }
39dbd958 2802 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2803 break;
2804
2805 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2806 break;
2807
05745c4a
SH		 2808 case CHIP_ID_YUKON_FE_P:
2809 hw->flags = SKY2_HW_NEWER_PHY
2810 | SKY2_HW_NEW_LE
2811 | SKY2_HW_AUTO_TX_SUM
2812 | SKY2_HW_ADV_POWER_CTL;
2813 break;
ed4d4161
SH		 2814
2815 case CHIP_ID_YUKON_SUPR:
2816 hw->flags = SKY2_HW_GIGABIT
2817 | SKY2_HW_NEWER_PHY
2818 | SKY2_HW_NEW_LE
2819 | SKY2_HW_AUTO_TX_SUM
2820 | SKY2_HW_ADV_POWER_CTL;
2821 break;
2822
0ce8b98d
SH		 2823 case CHIP_ID_YUKON_UL_2:
2824 hw->flags = SKY2_HW_GIGABIT
2825 | SKY2_HW_ADV_POWER_CTL;
2826 break;
2827
ea76e635 2828 default:
b02a9258
SH		 2829 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2830 hw->chip_id);
cd28ab6a
SH		 2831 return -EOPNOTSUPP;
2832 }
2833
ea76e635
SH		 2834 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2835 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2836 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2837
e3173832
SH		 2838 hw->ports = 1;
2839 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2840 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2841 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2842 ++hw->ports;
2843 }
2844
2845 return 0;
2846}
2847
2848static void sky2_reset(struct sky2_hw *hw)
2849{
555382cb 2850 struct pci_dev *pdev = hw->pdev;
e3173832 2851 u16 status;
555382cb
SH		 2852 int i, cap;
2853 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2854
cd28ab6a 2855 /* disable ASF */
4f44d8ba
SH		 2856 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2857 status = sky2_read16(hw, HCU_CCSR);
2858 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2859 HCU_CCSR_UC_STATE_MSK);
2860 sky2_write16(hw, HCU_CCSR, status);
2861 } else
2862 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2863 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2864
2865 /* do a SW reset */
2866 sky2_write8(hw, B0_CTST, CS_RST_SET);
2867 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2868
ac93a394
SH		 2869 /* allow writes to PCI config */
2870 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2871
cd28ab6a 2872 /* clear PCI errors, if any */
b32f40c4 2873 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2874 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2875 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2876
2877 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2878
555382cb
SH		 2879 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2880 if (cap) {
7782c8c4
SH		 2881 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2882 0xfffffffful);
555382cb
SH		 2883
2884 /* If error bit is stuck on ignore it */
2885 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2886 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2887 else
555382cb
SH		 2888 hwe_mask |= Y2_IS_PCI_EXP;
2889 }
cd28ab6a 2890
ae306cca 2891 sky2_power_on(hw);
82637e80 2892 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2893
2894 for (i = 0; i < hw->ports; i++) {
2895 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2896 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2897
ed4d4161
SH		 2898 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2899 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2900 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2901 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2902 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2903 }
2904
793b883e
SH		 2905 /* Clear I2C IRQ noise */
2906 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2907
2908 /* turn off hardware timer (unused) */
2909 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2910 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2911
cd28ab6a
SH		 2912 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2913
69634ee7
SH		 2914 /* Turn off descriptor polling */
2915 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2916
2917 /* Turn off receive timestamp */
2918 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2919 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2920
2921 /* enable the Tx Arbiters */
2922 for (i = 0; i < hw->ports; i++)
2923 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2924
2925 /* Initialize ram interface */
2926 for (i = 0; i < hw->ports; i++) {
793b883e 2927 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2928
2929 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2930 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2931 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2932 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2933 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2934 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2935 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2936 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2937 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2938 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2939 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2940 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2941 }
2942
555382cb 2943 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2944
cd28ab6a 2945 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2946 sky2_gmac_reset(hw, i);
cd28ab6a 2947
cd28ab6a
SH		 2948 memset(hw->st_le, 0, STATUS_LE_BYTES);
2949 hw->st_idx = 0;
2950
2951 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2952 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2953
2954 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2955 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2956
2957 /* Set the list last index */
793b883e 2958 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2959
290d4de5
SH		 2960 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2961 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2962
290d4de5
SH		 2963 /* set Status-FIFO ISR watermark */
2964 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2965 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2966 else
2967 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2968
290d4de5 2969 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2970 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2971 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2972
793b883e 2973 /* enable status unit */
cd28ab6a
SH		 2974 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2975
2976 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2977 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2978 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2979}
2980
81906791
SH		 2981static void sky2_restart(struct work_struct *work)
2982{
2983 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2984 struct net_device *dev;
2985 int i, err;
2986
81906791 2987 rtnl_lock();
81906791
SH		 2988 for (i = 0; i < hw->ports; i++) {
2989 dev = hw->dev[i];
2990 if (netif_running(dev))
2991 sky2_down(dev);
2992 }
2993
8cfcbe99
SH		 2994 napi_disable(&hw->napi);
2995 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 2996 sky2_reset(hw);
2997 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2998 napi_enable(&hw->napi);
81906791
SH		 2999
3000 for (i = 0; i < hw->ports; i++) {
3001 dev = hw->dev[i];
3002 if (netif_running(dev)) {
3003 err = sky2_up(dev);
3004 if (err) {
3005 printk(KERN_INFO PFX "%s: could not restart %d\n",
3006 dev->name, err);
3007 dev_close(dev);
3008 }
3009 }
3010 }
3011
81906791
SH		 3012 rtnl_unlock();
3013}
3014
e3173832
SH		 3015static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3016{
3017 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3018}
3019
3020static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3021{
3022 const struct sky2_port *sky2 = netdev_priv(dev);
3023
3024 wol->supported = sky2_wol_supported(sky2->hw);
3025 wol->wolopts = sky2->wol;
3026}
3027
3028static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3029{
3030 struct sky2_port *sky2 = netdev_priv(dev);
3031 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3032
e3173832
SH		 3033 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3034 return -EOPNOTSUPP;
3035
3036 sky2->wol = wol->wolopts;
3037
05745c4a
SH		 3038 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3039 hw->chip_id == CHIP_ID_YUKON_EX ||
3040 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3041 sky2_write32(hw, B0_CTST, sky2->wol
3042 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3043
3044 if (!netif_running(dev))
3045 sky2_wol_init(sky2);
cd28ab6a
SH		 3046 return 0;
3047}
3048
28bd181a 3049static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3050{
b89165f2
SH		 3051 if (sky2_is_copper(hw)) {
3052 u32 modes = SUPPORTED_10baseT_Half
3053 | SUPPORTED_10baseT_Full
3054 | SUPPORTED_100baseT_Half
3055 | SUPPORTED_100baseT_Full
3056 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3057
ea76e635 3058 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3059 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3060 | SUPPORTED_1000baseT_Full;
3061 return modes;
cd28ab6a 3062 } else
b89165f2
SH		 3063 return SUPPORTED_1000baseT_Half
3064 | SUPPORTED_1000baseT_Full
3065 | SUPPORTED_Autoneg
3066 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3067}
3068
793b883e 3069static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3070{
3071 struct sky2_port *sky2 = netdev_priv(dev);
3072 struct sky2_hw *hw = sky2->hw;
3073
3074 ecmd->transceiver = XCVR_INTERNAL;
3075 ecmd->supported = sky2_supported_modes(hw);
3076 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3077 if (sky2_is_copper(hw)) {
cd28ab6a 3078 ecmd->port = PORT_TP;
b89165f2
SH		 3079 ecmd->speed = sky2->speed;
3080 } else {
3081 ecmd->speed = SPEED_1000;
cd28ab6a 3082 ecmd->port = PORT_FIBRE;
b89165f2 3083 }
cd28ab6a
SH		 3084
3085 ecmd->advertising = sky2->advertising;
3086 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3087 ecmd->duplex = sky2->duplex;
3088 return 0;
3089}
3090
3091static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3092{
3093 struct sky2_port *sky2 = netdev_priv(dev);
3094 const struct sky2_hw *hw = sky2->hw;
3095 u32 supported = sky2_supported_modes(hw);
3096
3097 if (ecmd->autoneg == AUTONEG_ENABLE) {
3098 ecmd->advertising = supported;
3099 sky2->duplex = -1;
3100 sky2->speed = -1;
3101 } else {
3102 u32 setting;
3103
793b883e 3104 switch (ecmd->speed) {
cd28ab6a
SH		 3105 case SPEED_1000:
3106 if (ecmd->duplex == DUPLEX_FULL)
3107 setting = SUPPORTED_1000baseT_Full;
3108 else if (ecmd->duplex == DUPLEX_HALF)
3109 setting = SUPPORTED_1000baseT_Half;
3110 else
3111 return -EINVAL;
3112 break;
3113 case SPEED_100:
3114 if (ecmd->duplex == DUPLEX_FULL)
3115 setting = SUPPORTED_100baseT_Full;
3116 else if (ecmd->duplex == DUPLEX_HALF)
3117 setting = SUPPORTED_100baseT_Half;
3118 else
3119 return -EINVAL;
3120 break;
3121
3122 case SPEED_10:
3123 if (ecmd->duplex == DUPLEX_FULL)
3124 setting = SUPPORTED_10baseT_Full;
3125 else if (ecmd->duplex == DUPLEX_HALF)
3126 setting = SUPPORTED_10baseT_Half;
3127 else
3128 return -EINVAL;
3129 break;
3130 default:
3131 return -EINVAL;
3132 }
3133
3134 if ((setting & supported) == 0)
3135 return -EINVAL;
3136
3137 sky2->speed = ecmd->speed;
3138 sky2->duplex = ecmd->duplex;
3139 }
3140
3141 sky2->autoneg = ecmd->autoneg;
3142 sky2->advertising = ecmd->advertising;
3143
d1b139c0 3144 if (netif_running(dev)) {
1b537565 3145 sky2_phy_reinit(sky2);
d1b139c0
SH		 3146 sky2_set_multicast(dev);
3147 }
cd28ab6a
SH		 3148
3149 return 0;
3150}
3151
3152static void sky2_get_drvinfo(struct net_device *dev,
3153 struct ethtool_drvinfo *info)
3154{
3155 struct sky2_port *sky2 = netdev_priv(dev);
3156
3157 strcpy(info->driver, DRV_NAME);
3158 strcpy(info->version, DRV_VERSION);
3159 strcpy(info->fw_version, "N/A");
3160 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3161}
3162
3163static const struct sky2_stat {
793b883e
SH		 3164 char name[ETH_GSTRING_LEN];
3165 u16 offset;
cd28ab6a
SH		 3166} sky2_stats[] = {
3167 { "tx_bytes", GM_TXO_OK_HI },
3168 { "rx_bytes", GM_RXO_OK_HI },
3169 { "tx_broadcast", GM_TXF_BC_OK },
3170 { "rx_broadcast", GM_RXF_BC_OK },
3171 { "tx_multicast", GM_TXF_MC_OK },
3172 { "rx_multicast", GM_RXF_MC_OK },
3173 { "tx_unicast", GM_TXF_UC_OK },
3174 { "rx_unicast", GM_RXF_UC_OK },
3175 { "tx_mac_pause", GM_TXF_MPAUSE },
3176 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3177 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3178 { "late_collision",GM_TXF_LAT_COL },
3179 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3180 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3181 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3182
d2604540 3183 { "rx_short", GM_RXF_SHT },
cd28ab6a 3184 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3185 { "rx_64_byte_packets", GM_RXF_64B },
3186 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3187 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3188 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3189 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3190 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3191 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3192 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3193 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3194 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3195 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3196
3197 { "tx_64_byte_packets", GM_TXF_64B },
3198 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3199 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3200 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3201 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3202 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3203 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3204 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3205};
3206
cd28ab6a
SH		 3207static u32 sky2_get_rx_csum(struct net_device *dev)
3208{
3209 struct sky2_port *sky2 = netdev_priv(dev);
3210
3211 return sky2->rx_csum;
3212}
3213
3214static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3215{
3216 struct sky2_port *sky2 = netdev_priv(dev);
3217
3218 sky2->rx_csum = data;
793b883e 3219
cd28ab6a
SH		 3220 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3221 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3222
3223 return 0;
3224}
3225
3226static u32 sky2_get_msglevel(struct net_device *netdev)
3227{
3228 struct sky2_port *sky2 = netdev_priv(netdev);
3229 return sky2->msg_enable;
3230}
3231
9a7ae0a9
SH		 3232static int sky2_nway_reset(struct net_device *dev)
3233{
3234 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3235
16ad91e1 3236 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3237 return -EINVAL;
3238
1b537565 3239 sky2_phy_reinit(sky2);
d1b139c0 3240 sky2_set_multicast(dev);
9a7ae0a9
SH		 3241
3242 return 0;
3243}
3244
793b883e 3245static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3246{
3247 struct sky2_hw *hw = sky2->hw;
3248 unsigned port = sky2->port;
3249 int i;
3250
3251 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3252 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3253 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3254 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3255
793b883e 3256 for (i = 2; i < count; i++)
cd28ab6a
SH		 3257 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3258}
3259
cd28ab6a
SH		 3260static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3261{
3262 struct sky2_port *sky2 = netdev_priv(netdev);
3263 sky2->msg_enable = value;
3264}
3265
b9f2c044 3266static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3267{
b9f2c044
JG		 3268 switch (sset) {
3269 case ETH_SS_STATS:
3270 return ARRAY_SIZE(sky2_stats);
3271 default:
3272 return -EOPNOTSUPP;
3273 }
cd28ab6a
SH		 3274}
3275
3276static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3277 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3278{
3279 struct sky2_port *sky2 = netdev_priv(dev);
3280
793b883e 3281 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3282}
3283
793b883e 3284static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3285{
3286 int i;
3287
3288 switch (stringset) {
3289 case ETH_SS_STATS:
3290 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3291 memcpy(data + i * ETH_GSTRING_LEN,
3292 sky2_stats[i].name, ETH_GSTRING_LEN);
3293 break;
3294 }
3295}
3296
cd28ab6a
SH		 3297static int sky2_set_mac_address(struct net_device *dev, void *p)
3298{
3299 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3300 struct sky2_hw *hw = sky2->hw;
3301 unsigned port = sky2->port;
3302 const struct sockaddr *addr = p;
cd28ab6a
SH		 3303
3304 if (!is_valid_ether_addr(addr->sa_data))
3305 return -EADDRNOTAVAIL;
3306
cd28ab6a 3307 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3308 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3309 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3310 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3311 dev->dev_addr, ETH_ALEN);
1b537565 3312
a8ab1ec0
SH		 3313 /* virtual address for data */
3314 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3315
3316 /* physical address: used for pause frames */
3317 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3318
3319 return 0;
cd28ab6a
SH		 3320}
3321
a052b52f
SH		 3322static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3323{
3324 u32 bit;
3325
3326 bit = ether_crc(ETH_ALEN, addr) & 63;
3327 filter[bit >> 3] |= 1 << (bit & 7);
3328}
3329
cd28ab6a
SH		 3330static void sky2_set_multicast(struct net_device *dev)
3331{
3332 struct sky2_port *sky2 = netdev_priv(dev);
3333 struct sky2_hw *hw = sky2->hw;
3334 unsigned port = sky2->port;
3335 struct dev_mc_list *list = dev->mc_list;
3336 u16 reg;
3337 u8 filter[8];
a052b52f
SH		 3338 int rx_pause;
3339 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3340
a052b52f 3341 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3342 memset(filter, 0, sizeof(filter));
3343
3344 reg = gma_read16(hw, port, GM_RX_CTRL);
3345 reg |= GM_RXCR_UCF_ENA;
3346
d571b694 3347 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3348 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3349 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3350 memset(filter, 0xff, sizeof(filter));
a052b52f 3351 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3352 reg &= ~GM_RXCR_MCF_ENA;
3353 else {
3354 int i;
3355 reg |= GM_RXCR_MCF_ENA;
3356
a052b52f
SH		 3357 if (rx_pause)
3358 sky2_add_filter(filter, pause_mc_addr);
3359
3360 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3361 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3362 }
3363
cd28ab6a 3364 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3365 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3366 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3367 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3368 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3369 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3370 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3371 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3372
3373 gma_write16(hw, port, GM_RX_CTRL, reg);
3374}
3375
3376/* Can have one global because blinking is controlled by
3377 * ethtool and that is always under RTNL mutex
3378 */
a84d0a3d 3379static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3380{
a84d0a3d
SH		 3381 struct sky2_hw *hw = sky2->hw;
3382 unsigned port = sky2->port;
793b883e 3383
a84d0a3d
SH		 3384 spin_lock_bh(&sky2->phy_lock);
3385 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3386 hw->chip_id == CHIP_ID_YUKON_EX ||
3387 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3388 u16 pg;
793b883e
SH		 3389 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3390 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3391
a84d0a3d
SH		 3392 switch (mode) {
3393 case MO_LED_OFF:
3394 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3395 PHY_M_LEDC_LOS_CTRL(8) |
3396 PHY_M_LEDC_INIT_CTRL(8) |
3397 PHY_M_LEDC_STA1_CTRL(8) |
3398 PHY_M_LEDC_STA0_CTRL(8));
3399 break;
3400 case MO_LED_ON:
3401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3402 PHY_M_LEDC_LOS_CTRL(9) |
3403 PHY_M_LEDC_INIT_CTRL(9) |
3404 PHY_M_LEDC_STA1_CTRL(9) |
3405 PHY_M_LEDC_STA0_CTRL(9));
3406 break;
3407 case MO_LED_BLINK:
3408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3409 PHY_M_LEDC_LOS_CTRL(0xa) |
3410 PHY_M_LEDC_INIT_CTRL(0xa) |
3411 PHY_M_LEDC_STA1_CTRL(0xa) |
3412 PHY_M_LEDC_STA0_CTRL(0xa));
3413 break;
3414 case MO_LED_NORM:
3415 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3416 PHY_M_LEDC_LOS_CTRL(1) |
3417 PHY_M_LEDC_INIT_CTRL(8) |
3418 PHY_M_LEDC_STA1_CTRL(7) |
3419 PHY_M_LEDC_STA0_CTRL(7));
3420 }
793b883e 3421
a84d0a3d
SH		 3422 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3423 } else
7d2e3cb7 3424 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3425 PHY_M_LED_MO_DUP(mode) |
3426 PHY_M_LED_MO_10(mode) |
3427 PHY_M_LED_MO_100(mode) |
3428 PHY_M_LED_MO_1000(mode) |
3429 PHY_M_LED_MO_RX(mode) |
3430 PHY_M_LED_MO_TX(mode));
3431
3432 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3433}
3434
3435/* blink LED's for finding board */
3436static int sky2_phys_id(struct net_device *dev, u32 data)
3437{
3438 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3439 unsigned int i;
cd28ab6a 3440
a84d0a3d
SH		 3441 if (data == 0)
3442 data = UINT_MAX;
cd28ab6a 3443
a84d0a3d
SH		 3444 for (i = 0; i < data; i++) {
3445 sky2_led(sky2, MO_LED_ON);
3446 if (msleep_interruptible(500))
3447 break;
3448 sky2_led(sky2, MO_LED_OFF);
3449 if (msleep_interruptible(500))
3450 break;
793b883e 3451 }
a84d0a3d 3452 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3453
3454 return 0;
3455}
3456
3457static void sky2_get_pauseparam(struct net_device *dev,
3458 struct ethtool_pauseparam *ecmd)
3459{
3460 struct sky2_port *sky2 = netdev_priv(dev);
3461
16ad91e1
SH		 3462 switch (sky2->flow_mode) {
3463 case FC_NONE:
3464 ecmd->tx_pause = ecmd->rx_pause = 0;
3465 break;
3466 case FC_TX:
3467 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3468 break;
3469 case FC_RX:
3470 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3471 break;
3472 case FC_BOTH:
3473 ecmd->tx_pause = ecmd->rx_pause = 1;
3474 }
3475
cd28ab6a
SH		 3476 ecmd->autoneg = sky2->autoneg;
3477}
3478
3479static int sky2_set_pauseparam(struct net_device *dev,
3480 struct ethtool_pauseparam *ecmd)
3481{
3482 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3483
3484 sky2->autoneg = ecmd->autoneg;
16ad91e1 3485 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3486
16ad91e1
SH		 3487 if (netif_running(dev))
3488 sky2_phy_reinit(sky2);
cd28ab6a 3489
2eaba1a2 3490 return 0;
cd28ab6a
SH		 3491}
3492
fb17358f
SH		 3493static int sky2_get_coalesce(struct net_device *dev,
3494 struct ethtool_coalesce *ecmd)
3495{
3496 struct sky2_port *sky2 = netdev_priv(dev);
3497 struct sky2_hw *hw = sky2->hw;
3498
3499 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3500 ecmd->tx_coalesce_usecs = 0;
3501 else {
3502 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3503 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3504 }
3505 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3506
3507 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3508 ecmd->rx_coalesce_usecs = 0;
3509 else {
3510 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3511 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3512 }
3513 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3514
3515 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3516 ecmd->rx_coalesce_usecs_irq = 0;
3517 else {
3518 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3519 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3520 }
3521
3522 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3523
3524 return 0;
3525}
3526
3527/* Note: this affect both ports */
3528static int sky2_set_coalesce(struct net_device *dev,
3529 struct ethtool_coalesce *ecmd)
3530{
3531 struct sky2_port *sky2 = netdev_priv(dev);
3532 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3533 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3534
77b3d6a2
SH		 3535 if (ecmd->tx_coalesce_usecs > tmax ||
3536 ecmd->rx_coalesce_usecs > tmax ||
3537 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3538 return -EINVAL;
3539
ff81fbbe 3540 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3541 return -EINVAL;
ff81fbbe 3542 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3543 return -EINVAL;
ff81fbbe 3544 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3545 return -EINVAL;
3546
3547 if (ecmd->tx_coalesce_usecs == 0)
3548 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3549 else {
3550 sky2_write32(hw, STAT_TX_TIMER_INI,
3551 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3552 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3553 }
3554 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3555
3556 if (ecmd->rx_coalesce_usecs == 0)
3557 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3558 else {
3559 sky2_write32(hw, STAT_LEV_TIMER_INI,
3560 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3561 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3562 }
3563 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3564
3565 if (ecmd->rx_coalesce_usecs_irq == 0)
3566 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3567 else {
d28d4870 3568 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3569 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3570 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3571 }
3572 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3573 return 0;
3574}
3575
793b883e
SH		 3576static void sky2_get_ringparam(struct net_device *dev,
3577 struct ethtool_ringparam *ering)
3578{
3579 struct sky2_port *sky2 = netdev_priv(dev);
3580
3581 ering->rx_max_pending = RX_MAX_PENDING;
3582 ering->rx_mini_max_pending = 0;
3583 ering->rx_jumbo_max_pending = 0;
3584 ering->tx_max_pending = TX_RING_SIZE - 1;
3585
3586 ering->rx_pending = sky2->rx_pending;
3587 ering->rx_mini_pending = 0;
3588 ering->rx_jumbo_pending = 0;
3589 ering->tx_pending = sky2->tx_pending;
3590}
3591
3592static int sky2_set_ringparam(struct net_device *dev,
3593 struct ethtool_ringparam *ering)
3594{
3595 struct sky2_port *sky2 = netdev_priv(dev);
3596 int err = 0;
3597
3598 if (ering->rx_pending > RX_MAX_PENDING ||
3599 ering->rx_pending < 8 ||
3600 ering->tx_pending < MAX_SKB_TX_LE ||
3601 ering->tx_pending > TX_RING_SIZE - 1)
3602 return -EINVAL;
3603
3604 if (netif_running(dev))
3605 sky2_down(dev);
3606
3607 sky2->rx_pending = ering->rx_pending;
3608 sky2->tx_pending = ering->tx_pending;
3609
1b537565 3610 if (netif_running(dev)) {
793b883e 3611 err = sky2_up(dev);
1b537565
SH		 3612 if (err)
3613 dev_close(dev);
3614 }
793b883e
SH		 3615
3616 return err;
3617}
3618
793b883e
SH		 3619static int sky2_get_regs_len(struct net_device *dev)
3620{
6e4cbb34 3621 return 0x4000;
793b883e
SH		 3622}
3623
3624/*
3625 * Returns copy of control register region
3ead5db7 3626 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3627 */
3628static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3629 void *p)
3630{
3631 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3632 const void __iomem *io = sky2->hw->regs;
295b54c4 3633 unsigned int b;
793b883e
SH		 3634
3635 regs->version = 1;
793b883e 3636
295b54c4
SH		 3637 for (b = 0; b < 128; b++) {
3638 /* This complicated switch statement is to make sure and
3639 * only access regions that are unreserved.
3640 * Some blocks are only valid on dual port cards.
3641 * and block 3 has some special diagnostic registers that
3642 * are poison.
3643 */
3644 switch (b) {
3645 case 3:
3646 /* skip diagnostic ram region */
3647 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3648 break;
3ead5db7 3649
295b54c4
SH		 3650 /* dual port cards only */
3651 case 5: /* Tx Arbiter 2 */
3652 case 9: /* RX2 */
3653 case 14 ... 15: /* TX2 */
3654 case 17: case 19: /* Ram Buffer 2 */
3655 case 22 ... 23: /* Tx Ram Buffer 2 */
3656 case 25: /* Rx MAC Fifo 1 */
3657 case 27: /* Tx MAC Fifo 2 */
3658 case 31: /* GPHY 2 */
3659 case 40 ... 47: /* Pattern Ram 2 */
3660 case 52: case 54: /* TCP Segmentation 2 */
3661 case 112 ... 116: /* GMAC 2 */
3662 if (sky2->hw->ports == 1)
3663 goto reserved;
3664 /* fall through */
3665 case 0: /* Control */
3666 case 2: /* Mac address */
3667 case 4: /* Tx Arbiter 1 */
3668 case 7: /* PCI express reg */
3669 case 8: /* RX1 */
3670 case 12 ... 13: /* TX1 */
3671 case 16: case 18:/* Rx Ram Buffer 1 */
3672 case 20 ... 21: /* Tx Ram Buffer 1 */
3673 case 24: /* Rx MAC Fifo 1 */
3674 case 26: /* Tx MAC Fifo 1 */
3675 case 28 ... 29: /* Descriptor and status unit */
3676 case 30: /* GPHY 1*/
3677 case 32 ... 39: /* Pattern Ram 1 */
3678 case 48: case 50: /* TCP Segmentation 1 */
3679 case 56 ... 60: /* PCI space */
3680 case 80 ... 84: /* GMAC 1 */
3681 memcpy_fromio(p, io, 128);
3682 break;
3683 default:
3684reserved:
3685 memset(p, 0, 128);
3686 }
3ead5db7 3687
295b54c4
SH		 3688 p += 128;
3689 io += 128;
3690 }
793b883e 3691}
cd28ab6a 3692
b628ed98
SH		 3693/* In order to do Jumbo packets on these chips, need to turn off the
3694 * transmit store/forward. Therefore checksum offload won't work.
3695 */
3696static int no_tx_offload(struct net_device *dev)
3697{
3698 const struct sky2_port *sky2 = netdev_priv(dev);
3699 const struct sky2_hw *hw = sky2->hw;
3700
69161611 3701 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3702}
3703
3704static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3705{
3706 if (data && no_tx_offload(dev))
3707 return -EINVAL;
3708
3709 return ethtool_op_set_tx_csum(dev, data);
3710}
3711
3712
3713static int sky2_set_tso(struct net_device *dev, u32 data)
3714{
3715 if (data && no_tx_offload(dev))
3716 return -EINVAL;
3717
3718 return ethtool_op_set_tso(dev, data);
3719}
3720
f4331a6d
SH		 3721static int sky2_get_eeprom_len(struct net_device *dev)
3722{
3723 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3724 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3725 u16 reg2;
3726
b32f40c4 3727 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3728 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3729}
3730
b32f40c4 3731static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3732{
167f53d0 3733 u32 val;
f4331a6d 3734
b32f40c4 3735 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3736
3737 do {
b32f40c4 3738 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3739 } while (!(offset & PCI_VPD_ADDR_F));
3740
b32f40c4 3741 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3742 return val;
f4331a6d
SH		 3743}
3744
b32f40c4 3745static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3746{
b32f40c4
SH		 3747 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3748 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3749 do {
b32f40c4 3750 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3751 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3752}
3753
3754static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3755 u8 *data)
3756{
3757 struct sky2_port *sky2 = netdev_priv(dev);
3758 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3759 int length = eeprom->len;
3760 u16 offset = eeprom->offset;
3761
3762 if (!cap)
3763 return -EINVAL;
3764
3765 eeprom->magic = SKY2_EEPROM_MAGIC;
3766
3767 while (length > 0) {
b32f40c4 3768 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3769 int n = min_t(int, length, sizeof(val));
3770
3771 memcpy(data, &val, n);
3772 length -= n;
3773 data += n;
3774 offset += n;
3775 }
3776 return 0;
3777}
3778
3779static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3780 u8 *data)
3781{
3782 struct sky2_port *sky2 = netdev_priv(dev);
3783 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3784 int length = eeprom->len;
3785 u16 offset = eeprom->offset;
3786
3787 if (!cap)
3788 return -EINVAL;
3789
3790 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3791 return -EINVAL;
3792
3793 while (length > 0) {
3794 u32 val;
3795 int n = min_t(int, length, sizeof(val));
3796
3797 if (n < sizeof(val))
b32f40c4 3798 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3799 memcpy(&val, data, n);
3800
b32f40c4 3801 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3802
3803 length -= n;
3804 data += n;
3805 offset += n;
3806 }
3807 return 0;
3808}
3809
3810
7282d491 3811static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3812 .get_settings = sky2_get_settings,
3813 .set_settings = sky2_set_settings,
3814 .get_drvinfo = sky2_get_drvinfo,
3815 .get_wol = sky2_get_wol,
3816 .set_wol = sky2_set_wol,
3817 .get_msglevel = sky2_get_msglevel,
3818 .set_msglevel = sky2_set_msglevel,
3819 .nway_reset = sky2_nway_reset,
3820 .get_regs_len = sky2_get_regs_len,
3821 .get_regs = sky2_get_regs,
3822 .get_link = ethtool_op_get_link,
3823 .get_eeprom_len = sky2_get_eeprom_len,
3824 .get_eeprom = sky2_get_eeprom,
3825 .set_eeprom = sky2_set_eeprom,
f4331a6d 3826 .set_sg = ethtool_op_set_sg,
f4331a6d 3827 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3828 .set_tso = sky2_set_tso,
3829 .get_rx_csum = sky2_get_rx_csum,
3830 .set_rx_csum = sky2_set_rx_csum,
3831 .get_strings = sky2_get_strings,
3832 .get_coalesce = sky2_get_coalesce,
3833 .set_coalesce = sky2_set_coalesce,
3834 .get_ringparam = sky2_get_ringparam,
3835 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3836 .get_pauseparam = sky2_get_pauseparam,
3837 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3838 .phys_id = sky2_phys_id,
b9f2c044 3839 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3840 .get_ethtool_stats = sky2_get_ethtool_stats,
3841};
3842
3cf26753
SH		 3843#ifdef CONFIG_SKY2_DEBUG
3844
3845static struct dentry *sky2_debug;
3846
3847static int sky2_debug_show(struct seq_file *seq, void *v)
3848{
3849 struct net_device *dev = seq->private;
3850 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3851 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3852 unsigned port = sky2->port;
3853 unsigned idx, last;
3854 int sop;
3855
3856 if (!netif_running(dev))
3857 return -ENETDOWN;
3858
3859 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3860 sky2_read32(hw, B0_ISRC),
3861 sky2_read32(hw, B0_IMSK),
3862 sky2_read32(hw, B0_Y2_SP_ICR));
3863
bea3348e 3864 napi_disable(&hw->napi);
3cf26753
SH		 3865 last = sky2_read16(hw, STAT_PUT_IDX);
3866
3867 if (hw->st_idx == last)
3868 seq_puts(seq, "Status ring (empty)\n");
3869 else {
3870 seq_puts(seq, "Status ring\n");
3871 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3872 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3873 const struct sky2_status_le *le = hw->st_le + idx;
3874 seq_printf(seq, "[%d] %#x %d %#x\n",
3875 idx, le->opcode, le->length, le->status);
3876 }
3877 seq_puts(seq, "\n");
3878 }
3879
3880 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3881 sky2->tx_cons, sky2->tx_prod,
3882 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3883 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3884
3885 /* Dump contents of tx ring */
3886 sop = 1;
3887 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3888 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3889 const struct sky2_tx_le *le = sky2->tx_le + idx;
3890 u32 a = le32_to_cpu(le->addr);
3891
3892 if (sop)
3893 seq_printf(seq, "%u:", idx);
3894 sop = 0;
3895
3896 switch(le->opcode & ~HW_OWNER) {
3897 case OP_ADDR64:
3898 seq_printf(seq, " %#x:", a);
3899 break;
3900 case OP_LRGLEN:
3901 seq_printf(seq, " mtu=%d", a);
3902 break;
3903 case OP_VLAN:
3904 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3905 break;
3906 case OP_TCPLISW:
3907 seq_printf(seq, " csum=%#x", a);
3908 break;
3909 case OP_LARGESEND:
3910 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3911 break;
3912 case OP_PACKET:
3913 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3914 break;
3915 case OP_BUFFER:
3916 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3917 break;
3918 default:
3919 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3920 a, le16_to_cpu(le->length));
3921 }
3922
3923 if (le->ctrl & EOP) {
3924 seq_putc(seq, '\n');
3925 sop = 1;
3926 }
3927 }
3928
3929 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3930 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3931 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3932 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3933
d1d08d12 3934 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 3935 napi_enable(&hw->napi);
3cf26753
SH		 3936 return 0;
3937}
3938
3939static int sky2_debug_open(struct inode *inode, struct file *file)
3940{
3941 return single_open(file, sky2_debug_show, inode->i_private);
3942}
3943
3944static const struct file_operations sky2_debug_fops = {
3945 .owner = THIS_MODULE,
3946 .open = sky2_debug_open,
3947 .read = seq_read,
3948 .llseek = seq_lseek,
3949 .release = single_release,
3950};
3951
3952/*
3953 * Use network device events to create/remove/rename
3954 * debugfs file entries
3955 */
3956static int sky2_device_event(struct notifier_block *unused,
3957 unsigned long event, void *ptr)
3958{
3959 struct net_device *dev = ptr;
5b296bc9 3960 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3961
5b296bc9
SH		 3962 if (dev->open != sky2_up || !sky2_debug)
3963 return NOTIFY_DONE;
3cf26753 3964
5b296bc9
SH		 3965 switch(event) {
3966 case NETDEV_CHANGENAME:
3967 if (sky2->debugfs) {
3968 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3969 sky2_debug, dev->name);
3970 }
3971 break;
3cf26753 3972
5b296bc9
SH		 3973 case NETDEV_GOING_DOWN:
3974 if (sky2->debugfs) {
3975 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3976 dev->name);
3977 debugfs_remove(sky2->debugfs);
3978 sky2->debugfs = NULL;
3cf26753 3979 }
5b296bc9
SH		 3980 break;
3981
3982 case NETDEV_UP:
3983 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3984 sky2_debug, dev,
3985 &sky2_debug_fops);
3986 if (IS_ERR(sky2->debugfs))
3987 sky2->debugfs = NULL;
3cf26753
SH		 3988 }
3989
3990 return NOTIFY_DONE;
3991}
3992
3993static struct notifier_block sky2_notifier = {
3994 .notifier_call = sky2_device_event,
3995};
3996
3997
3998static __init void sky2_debug_init(void)
3999{
4000 struct dentry *ent;
4001
4002 ent = debugfs_create_dir("sky2", NULL);
4003 if (!ent || IS_ERR(ent))
4004 return;
4005
4006 sky2_debug = ent;
4007 register_netdevice_notifier(&sky2_notifier);
4008}
4009
4010static __exit void sky2_debug_cleanup(void)
4011{
4012 if (sky2_debug) {
4013 unregister_netdevice_notifier(&sky2_notifier);
4014 debugfs_remove(sky2_debug);
4015 sky2_debug = NULL;
4016 }
4017}
4018
4019#else
4020#define sky2_debug_init()
4021#define sky2_debug_cleanup()
4022#endif
4023
4024
cd28ab6a
SH		 4025/* Initialize network device */
4026static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4027 unsigned port,
be63a21c 4028 int highmem, int wol)
cd28ab6a
SH		 4029{
4030 struct sky2_port *sky2;
4031 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4032
4033 if (!dev) {
898eb71c 4034 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4035 return NULL;
4036 }
4037
cd28ab6a 4038 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4039 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 4040 dev->open = sky2_up;
4041 dev->stop = sky2_down;
ef743d33 4042 dev->do_ioctl = sky2_ioctl;
cd28ab6a 4043 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 4044 dev->set_multicast_list = sky2_set_multicast;
4045 dev->set_mac_address = sky2_set_mac_address;
4046 dev->change_mtu = sky2_change_mtu;
4047 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4048 dev->tx_timeout = sky2_tx_timeout;
4049 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 4050#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 4051 if (port == 0)
4052 dev->poll_controller = sky2_netpoll;
cd28ab6a 4053#endif
cd28ab6a
SH		 4054
4055 sky2 = netdev_priv(dev);
4056 sky2->netdev = dev;
4057 sky2->hw = hw;
4058 sky2->msg_enable = netif_msg_init(debug, default_msg);
4059
cd28ab6a
SH		 4060 /* Auto speed and flow control */
4061 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4062 sky2->flow_mode = FC_BOTH;
4063
cd28ab6a
SH		 4064 sky2->duplex = -1;
4065 sky2->speed = -1;
4066 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4067 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4068 sky2->wol = wol;
75d070c5 4069
e07b1aa8 4070 spin_lock_init(&sky2->phy_lock);
793b883e 4071 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4072 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4073
4074 hw->dev[port] = dev;
4075
4076 sky2->port = port;
4077
4a50a876 4078 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4079 if (highmem)
4080 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4081
d1f13708 4082#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4083 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4084 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4085 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4086 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4087 dev->vlan_rx_register = sky2_vlan_rx_register;
4088 }
d1f13708
SH		 4089#endif
4090
cd28ab6a 4091 /* read the mac address */
793b883e 4092 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4093 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4094
cd28ab6a
SH		 4095 return dev;
4096}
4097
28bd181a 4098static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4099{
4100 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4101 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4102
4103 if (netif_msg_probe(sky2))
0795af57
JP		 4104 printk(KERN_INFO PFX "%s: addr %s\n",
4105 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4106}
4107
fb2690a9 4108/* Handle software interrupt used during MSI test */
7d12e780 4109static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4110{
4111 struct sky2_hw *hw = dev_id;
4112 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4113
4114 if (status == 0)
4115 return IRQ_NONE;
4116
4117 if (status & Y2_IS_IRQ_SW) {
ea76e635 4118 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4119 wake_up(&hw->msi_wait);
4120 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4121 }
4122 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4123
4124 return IRQ_HANDLED;
4125}
4126
4127/* Test interrupt path by forcing a a software IRQ */
4128static int __devinit sky2_test_msi(struct sky2_hw *hw)
4129{
4130 struct pci_dev *pdev = hw->pdev;
4131 int err;
4132
bb507fe1
SH		 4133 init_waitqueue_head (&hw->msi_wait);
4134
fb2690a9
SH		 4135 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4136
b0a20ded 4137 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4138 if (err) {
b02a9258 4139 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4140 return err;
4141 }
4142
fb2690a9 4143 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4144 sky2_read8(hw, B0_CTST);
fb2690a9 4145
ea76e635 4146 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4147
ea76e635 4148 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4149 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4150 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4151 "switching to INTx mode.\n");
fb2690a9
SH		 4152
4153 err = -EOPNOTSUPP;
4154 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4155 }
4156
4157 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4158 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4159
4160 free_irq(pdev->irq, hw);
4161
4162 return err;
4163}
4164
be63a21c
SH		 4165static int __devinit pci_wake_enabled(struct pci_dev *dev)
4166{
4167 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4168 u16 value;
4169
4170 if (!pm)
4171 return 0;
4172 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4173 return 0;
4174 return value & PCI_PM_CTRL_PME_ENABLE;
4175}
4176
c7127a34
SH		 4177/* This driver supports yukon2 chipset only */
4178static const char *sky2_name(u8 chipid, char *buf, int sz)
4179{
4180 const char *name[] = {
4181 "XL", /* 0xb3 */
4182 "EC Ultra", /* 0xb4 */
4183 "Extreme", /* 0xb5 */
4184 "EC", /* 0xb6 */
4185 "FE", /* 0xb7 */
4186 "FE+", /* 0xb8 */
4187 "Supreme", /* 0xb9 */
0ce8b98d 4188 "UL 2", /* 0xba */
c7127a34
SH		 4189 };
4190
0ce8b98d 4191 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4192 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4193 else
4194 snprintf(buf, sz, "(chip %#x)", chipid);
4195 return buf;
4196}
4197
cd28ab6a
SH		 4198static int __devinit sky2_probe(struct pci_dev *pdev,
4199 const struct pci_device_id *ent)
4200{
7f60c64b 4201 struct net_device *dev;
cd28ab6a 4202 struct sky2_hw *hw;
be63a21c 4203 int err, using_dac = 0, wol_default;
c7127a34 4204 char buf1[16];
cd28ab6a 4205
793b883e
SH		 4206 err = pci_enable_device(pdev);
4207 if (err) {
b02a9258 4208 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4209 goto err_out;
4210 }
4211
793b883e
SH		 4212 err = pci_request_regions(pdev, DRV_NAME);
4213 if (err) {
b02a9258 4214 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4215 goto err_out_disable;
cd28ab6a
SH		 4216 }
4217
4218 pci_set_master(pdev);
4219
d1f3d4dd
SH		 4220 if (sizeof(dma_addr_t) > sizeof(u32) &&
4221 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4222 using_dac = 1;
4223 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4224 if (err < 0) {
b02a9258
SH		 4225 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4226 "for consistent allocations\n");
d1f3d4dd
SH		 4227 goto err_out_free_regions;
4228 }
d1f3d4dd 4229 } else {
cd28ab6a
SH		 4230 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4231 if (err) {
b02a9258 4232 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4233 goto err_out_free_regions;
4234 }
4235 }
d1f3d4dd 4236
be63a21c
SH		 4237 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4238
cd28ab6a 4239 err = -ENOMEM;
6aad85d6 4240 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4241 if (!hw) {
b02a9258 4242 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4243 goto err_out_free_regions;
4244 }
4245
cd28ab6a 4246 hw->pdev = pdev;
cd28ab6a
SH		 4247
4248 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4249 if (!hw->regs) {
b02a9258 4250 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4251 goto err_out_free_hw;
4252 }
4253
56a645cc 4254#ifdef __BIG_ENDIAN
f65b138c
SH		 4255 /* The sk98lin vendor driver uses hardware byte swapping but
4256 * this driver uses software swapping.
4257 */
56a645cc
SH		 4258 {
4259 u32 reg;
b32f40c4 4260 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4261 reg &= ~PCI_REV_DESC;
b32f40c4 4262 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4263 }
4264#endif
4265
08c06d8a 4266 /* ring for status responses */
167f53d0 4267 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4268 if (!hw->st_le)
4269 goto err_out_iounmap;
4270
e3173832 4271 err = sky2_init(hw);
cd28ab6a 4272 if (err)
793b883e 4273 goto err_out_iounmap;
cd28ab6a 4274
c7127a34
SH		 4275 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-2 %s rev %d\n",
4276 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4277 pdev->irq, sky2_name(hw->chip_id, buf1, sizeof(buf1)),
4278 hw->chip_rev);
cd28ab6a 4279
e3173832
SH		 4280 sky2_reset(hw);
4281
be63a21c 4282 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4283 if (!dev) {
4284 err = -ENOMEM;
cd28ab6a 4285 goto err_out_free_pci;
7f60c64b 4286 }
cd28ab6a 4287
9fa1b1f3
SH		 4288 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4289 err = sky2_test_msi(hw);
4290 if (err == -EOPNOTSUPP)
4291 pci_disable_msi(pdev);
4292 else if (err)
4293 goto err_out_free_netdev;
4294 }
4295
793b883e
SH		 4296 err = register_netdev(dev);
4297 if (err) {
b02a9258 4298 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4299 goto err_out_free_netdev;
4300 }
4301
6de16237
SH		 4302 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4303
ea76e635
SH		 4304 err = request_irq(pdev->irq, sky2_intr,
4305 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4306 dev->name, hw);
9fa1b1f3 4307 if (err) {
b02a9258 4308 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4309 goto err_out_unregister;
4310 }
4311 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4312 napi_enable(&hw->napi);
9fa1b1f3 4313
cd28ab6a
SH		 4314 sky2_show_addr(dev);
4315
7f60c64b 4316 if (hw->ports > 1) {
4317 struct net_device *dev1;
4318
be63a21c 4319 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4320 if (!dev1)
4321 dev_warn(&pdev->dev, "allocation for second device failed\n");
4322 else if ((err = register_netdev(dev1))) {
4323 dev_warn(&pdev->dev,
4324 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4325 hw->dev[1] = NULL;
4326 free_netdev(dev1);
b02a9258
SH		 4327 } else
4328 sky2_show_addr(dev1);
cd28ab6a
SH		 4329 }
4330
32c2c300 4331 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4332 INIT_WORK(&hw->restart_work, sky2_restart);
4333
793b883e
SH		 4334 pci_set_drvdata(pdev, hw);
4335
cd28ab6a
SH		 4336 return 0;
4337
793b883e 4338err_out_unregister:
ea76e635 4339 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4340 pci_disable_msi(pdev);
793b883e 4341 unregister_netdev(dev);
cd28ab6a
SH		 4342err_out_free_netdev:
4343 free_netdev(dev);
cd28ab6a 4344err_out_free_pci:
793b883e 4345 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4346 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4347err_out_iounmap:
4348 iounmap(hw->regs);
4349err_out_free_hw:
4350 kfree(hw);
4351err_out_free_regions:
4352 pci_release_regions(pdev);
44a1d2e5 4353err_out_disable:
cd28ab6a 4354 pci_disable_device(pdev);
cd28ab6a 4355err_out:
549a68c3 4356 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4357 return err;
4358}
4359
4360static void __devexit sky2_remove(struct pci_dev *pdev)
4361{
793b883e 4362 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4363 int i;
cd28ab6a 4364
793b883e 4365 if (!hw)
cd28ab6a
SH		 4366 return;
4367
32c2c300 4368 del_timer_sync(&hw->watchdog_timer);
6de16237 4369 cancel_work_sync(&hw->restart_work);
d27ed387 4370
b877fe28 4371 for (i = hw->ports-1; i >= 0; --i)
6de16237 4372 unregister_netdev(hw->dev[i]);
81906791 4373
d27ed387 4374 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4375
ae306cca
SH		 4376 sky2_power_aux(hw);
4377
cd28ab6a 4378 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4379 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4380 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4381
4382 free_irq(pdev->irq, hw);
ea76e635 4383 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4384 pci_disable_msi(pdev);
793b883e 4385 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4386 pci_release_regions(pdev);
4387 pci_disable_device(pdev);
793b883e 4388
b877fe28 4389 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4390 free_netdev(hw->dev[i]);
4391
cd28ab6a
SH		 4392 iounmap(hw->regs);
4393 kfree(hw);
5afa0a9c 4394
cd28ab6a
SH		 4395 pci_set_drvdata(pdev, NULL);
4396}
4397
4398#ifdef CONFIG_PM
4399static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4400{
793b883e 4401 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4402 int i, wol = 0;
cd28ab6a 4403
549a68c3
SH		 4404 if (!hw)
4405 return 0;
4406
063a0b38
SH		 4407 del_timer_sync(&hw->watchdog_timer);
4408 cancel_work_sync(&hw->restart_work);
4409
f05267e7 4410 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4411 struct net_device *dev = hw->dev[i];
e3173832 4412 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4413
063a0b38 4414 netif_device_detach(dev);
e3173832 4415 if (netif_running(dev))
5afa0a9c 4416 sky2_down(dev);
e3173832
SH		 4417
4418 if (sky2->wol)
4419 sky2_wol_init(sky2);
4420
4421 wol |= sky2->wol;
cd28ab6a
SH		 4422 }
4423
8ab8fca2 4424 sky2_write32(hw, B0_IMSK, 0);
6de16237 4425 napi_disable(&hw->napi);
ae306cca 4426 sky2_power_aux(hw);
e3173832 4427
d374c1c1 4428 pci_save_state(pdev);
e3173832 4429 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4430 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4431
2ccc99b7 4432 return 0;
cd28ab6a
SH		 4433}
4434
4435static int sky2_resume(struct pci_dev *pdev)
4436{
793b883e 4437 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4438 int i, err;
cd28ab6a 4439
549a68c3
SH		 4440 if (!hw)
4441 return 0;
4442
f71eb1a2
SH		 4443 err = pci_set_power_state(pdev, PCI_D0);
4444 if (err)
4445 goto out;
ae306cca
SH		 4446
4447 err = pci_restore_state(pdev);
4448 if (err)
4449 goto out;
4450
cd28ab6a 4451 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4452
4453 /* Re-enable all clocks */
05745c4a
SH		 4454 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4455 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4456 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4457 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4458
e3173832 4459 sky2_reset(hw);
8ab8fca2 4460 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4461 napi_enable(&hw->napi);
8ab8fca2 4462
f05267e7 4463 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4464 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4465
4466 netif_device_attach(dev);
6a5706b9 4467 if (netif_running(dev)) {
08c06d8a
SH		 4468 err = sky2_up(dev);
4469 if (err) {
4470 printk(KERN_ERR PFX "%s: could not up: %d\n",
4471 dev->name, err);
68c28898 4472 rtnl_lock();
08c06d8a 4473 dev_close(dev);
68c28898 4474 rtnl_unlock();
eb35cf60 4475 goto out;
5afa0a9c 4476 }
cd28ab6a
SH		 4477 }
4478 }
eb35cf60 4479
ae306cca 4480 return 0;
08c06d8a 4481out:
b02a9258 4482 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4483 pci_disable_device(pdev);
08c06d8a 4484 return err;
cd28ab6a
SH		 4485}
4486#endif
4487
e3173832
SH		 4488static void sky2_shutdown(struct pci_dev *pdev)
4489{
4490 struct sky2_hw *hw = pci_get_drvdata(pdev);
4491 int i, wol = 0;
4492
549a68c3
SH		 4493 if (!hw)
4494 return;
4495
5c0d6b34 4496 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4497
4498 for (i = 0; i < hw->ports; i++) {
4499 struct net_device *dev = hw->dev[i];
4500 struct sky2_port *sky2 = netdev_priv(dev);
4501
4502 if (sky2->wol) {
4503 wol = 1;
4504 sky2_wol_init(sky2);
4505 }
4506 }
4507
4508 if (wol)
4509 sky2_power_aux(hw);
4510
4511 pci_enable_wake(pdev, PCI_D3hot, wol);
4512 pci_enable_wake(pdev, PCI_D3cold, wol);
4513
4514 pci_disable_device(pdev);
f71eb1a2 4515 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4516}
4517
cd28ab6a 4518static struct pci_driver sky2_driver = {
793b883e
SH		 4519 .name = DRV_NAME,
4520 .id_table = sky2_id_table,
4521 .probe = sky2_probe,
4522 .remove = __devexit_p(sky2_remove),
cd28ab6a 4523#ifdef CONFIG_PM
793b883e
SH		 4524 .suspend = sky2_suspend,
4525 .resume = sky2_resume,
cd28ab6a 4526#endif
e3173832 4527 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4528};
4529
4530static int __init sky2_init_module(void)
4531{
3cf26753 4532 sky2_debug_init();
50241c4c 4533 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4534}
4535
4536static void __exit sky2_cleanup_module(void)
4537{
4538 pci_unregister_driver(&sky2_driver);
3cf26753 4539 sky2_debug_cleanup();
cd28ab6a
SH		 4540}
4541
4542module_init(sky2_init_module);
4543module_exit(sky2_cleanup_module);
4544
4545MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4546MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4547MODULE_LICENSE("GPL");
5f4f9dc1 4548MODULE_VERSION(DRV_VERSION);
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