projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /*------------------------------------------------------------------------ |
| 2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. | |
| 3 | . | |
| 4 | . Copyright (C) 1996 by Erik Stahlman | |
| 5 | . Copyright (C) 2001 Standard Microsystems Corporation | |
| 6 | . Developed by Simple Network Magic Corporation | |
| 7 | . Copyright (C) 2003 Monta Vista Software, Inc. | |
| 8 | . Unified SMC91x driver by Nicolas Pitre | |
| 9 | . | |
| 10 | . This program is free software; you can redistribute it and/or modify | |
| 11 | . it under the terms of the GNU General Public License as published by | |
| 12 | . the Free Software Foundation; either version 2 of the License, or | |
| 13 | . (at your option) any later version. | |
| 14 | . | |
| 15 | . This program is distributed in the hope that it will be useful, | |
| 16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | . GNU General Public License for more details. | |
| 19 | . | |
| 20 | . You should have received a copy of the GNU General Public License | |
| 21 | . along with this program; if not, write to the Free Software | |
| 22 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 23 | . | |
| 24 | . Information contained in this file was obtained from the LAN91C111 | |
| 25 | . manual from SMC. To get a copy, if you really want one, you can find | |
| 26 | . information under www.smsc.com. | |
| 27 | . | |
| 28 | . Authors | |
| 29 | . Erik Stahlman <erik@vt.edu> | |
| 30 | . Daris A Nevil <dnevil@snmc.com> | |
| 31 | . Nicolas Pitre <nico@cam.org> | |
| 32 | . | |
| 33 | ---------------------------------------------------------------------------*/ | |
| 34 | #ifndef _SMC91X_H_ | |
| 35 | #define _SMC91X_H_ | |
| 36 | ||
| 37 | ||
| 38 | /* | |
| 39 | * Define your architecture specific bus configuration parameters here. | |
| 40 | */ | |
| 41 | ||
| 42 | #if defined(CONFIG_ARCH_LUBBOCK) | |
| 43 | ||
| 44 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
| 45 | #define SMC_CAN_USE_8BIT 0 | |
| 46 | #define SMC_CAN_USE_16BIT 1 | |
| 47 | #define SMC_CAN_USE_32BIT 0 | |
| 48 | #define SMC_NOWAIT 1 | |
| 49 | ||
| 50 | /* The first two address lines aren't connected... */ | |
| 51 | #define SMC_IO_SHIFT 2 | |
| 52 | ||
| 53 | #define SMC_inw(a, r) readw((a) + (r)) | |
| 54 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
| 55 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
| 56 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
| 57 | ||
| 0851a284 WB |
58 | #elif defined(CONFIG_BFIN) |
| 59 | ||
| 60 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH | |
| 61 | ||
| 62 | # if defined (CONFIG_BFIN561_EZKIT) | |
| 63 | #define SMC_CAN_USE_8BIT 0 | |
| 64 | #define SMC_CAN_USE_16BIT 1 | |
| 65 | #define SMC_CAN_USE_32BIT 1 | |
| 66 | #define SMC_IO_SHIFT 0 | |
| 67 | #define SMC_NOWAIT 1 | |
| 68 | #define SMC_USE_BFIN_DMA 0 | |
| 69 | ||
| 70 | ||
| 71 | #define SMC_inw(a, r) readw((a) + (r)) | |
| 72 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
| 73 | #define SMC_inl(a, r) readl((a) + (r)) | |
| 74 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
| 75 | #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l) | |
| 76 | #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l) | |
| 77 | # else | |
| 78 | #define SMC_CAN_USE_8BIT 0 | |
| 79 | #define SMC_CAN_USE_16BIT 1 | |
| 80 | #define SMC_CAN_USE_32BIT 0 | |
| 81 | #define SMC_IO_SHIFT 0 | |
| 82 | #define SMC_NOWAIT 1 | |
| 83 | #define SMC_USE_BFIN_DMA 0 | |
| 84 | ||
| 85 | ||
| 86 | #define SMC_inw(a, r) readw((a) + (r)) | |
| 87 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
| 88 | #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l) | |
| 89 | #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l) | |
| 90 | # endif | |
| 91 | /* check if the mac in reg is valid */ | |
| 92 | #define SMC_GET_MAC_ADDR(addr) \ | |
| 93 | do { \ | |
| 94 | unsigned int __v; \ | |
| 95 | __v = SMC_inw(ioaddr, ADDR0_REG); \ | |
| 96 | addr[0] = __v; addr[1] = __v >> 8; \ | |
| 97 | __v = SMC_inw(ioaddr, ADDR1_REG); \ | |
| 98 | addr[2] = __v; addr[3] = __v >> 8; \ | |
| 99 | __v = SMC_inw(ioaddr, ADDR2_REG); \ | |
| 100 | addr[4] = __v; addr[5] = __v >> 8; \ | |
| 101 | if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \ | |
| 102 | random_ether_addr(addr); \ | |
| 103 | } \ | |
| 104 | } while (0) | |
| 1da177e4 LT |
105 | #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) |
| 106 | ||
| 107 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
| 108 | #define SMC_CAN_USE_8BIT 0 | |
| 109 | #define SMC_CAN_USE_16BIT 1 | |
| 110 | #define SMC_CAN_USE_32BIT 0 | |
| 111 | #define SMC_NOWAIT 1 | |
| 112 | ||
| 113 | #define SMC_IO_SHIFT 0 | |
| 114 | ||
| 115 | #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) | |
| 116 | #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) | |
| 117 | #define SMC_insw(a, r, p, l) \ | |
| 118 | do { \ | |
| 119 | unsigned long __port = (a) + (r); \ | |
| 120 | u16 *__p = (u16 *)(p); \ | |
| 121 | int __l = (l); \ | |
| 122 | insw(__port, __p, __l); \ | |
| 123 | while (__l > 0) { \ | |
| 124 | *__p = swab16(*__p); \ | |
| 125 | __p++; \ | |
| 126 | __l--; \ | |
| 127 | } \ | |
| 128 | } while (0) | |
| 129 | #define SMC_outsw(a, r, p, l) \ | |
| 130 | do { \ | |
| 131 | unsigned long __port = (a) + (r); \ | |
| 132 | u16 *__p = (u16 *)(p); \ | |
| 133 | int __l = (l); \ | |
| 134 | while (__l > 0) { \ | |
| 135 | /* Believe it or not, the swab isn't needed. */ \ | |
| 136 | outw( /* swab16 */ (*__p++), __port); \ | |
| 137 | __l--; \ | |
| 138 | } \ | |
| 139 | } while (0) | |
| 9ded96f2 | 140 | #define SMC_IRQ_FLAGS (0) |
| 1da177e4 LT |
141 | |
| 142 | #elif defined(CONFIG_SA1100_PLEB) | |
| 143 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
| 144 | #define SMC_CAN_USE_8BIT 1 | |
| 145 | #define SMC_CAN_USE_16BIT 1 | |
| 146 | #define SMC_CAN_USE_32BIT 0 | |
| 147 | #define SMC_IO_SHIFT 0 | |
| 148 | #define SMC_NOWAIT 1 | |
| 149 | ||
| 1cf99be5 RK |
150 | #define SMC_inb(a, r) readb((a) + (r)) |
| 151 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
| 152 | #define SMC_inw(a, r) readw((a) + (r)) | |
| 153 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
| 154 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
| 155 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
| 156 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
| 157 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
| 1da177e4 | 158 | |
| 9ded96f2 | 159 | #define SMC_IRQ_FLAGS (0) |
| 1da177e4 LT |
160 | |
| 161 | #elif defined(CONFIG_SA1100_ASSABET) | |
| 162 | ||
| 163 | #include <asm/arch/neponset.h> | |
| 164 | ||
| 165 | /* We can only do 8-bit reads and writes in the static memory space. */ | |
| 166 | #define SMC_CAN_USE_8BIT 1 | |
| 167 | #define SMC_CAN_USE_16BIT 0 | |
| 168 | #define SMC_CAN_USE_32BIT 0 | |
| 169 | #define SMC_NOWAIT 1 | |
| 170 | ||
| 171 | /* The first two address lines aren't connected... */ | |
| 172 | #define SMC_IO_SHIFT 2 | |
| 173 | ||
| 174 | #define SMC_inb(a, r) readb((a) + (r)) | |
| 175 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
| 176 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
| 177 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
| 178 | ||
| b0348b90 LB |
179 | #elif defined(CONFIG_MACH_LOGICPD_PXA270) |
| 180 | ||
| 181 | #define SMC_CAN_USE_8BIT 0 | |
| 182 | #define SMC_CAN_USE_16BIT 1 | |
| 183 | #define SMC_CAN_USE_32BIT 0 | |
| 184 | #define SMC_IO_SHIFT 0 | |
| 185 | #define SMC_NOWAIT 1 | |
| b0348b90 | 186 | |
| b0348b90 | 187 | #define SMC_inw(a, r) readw((a) + (r)) |
| b0348b90 | 188 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) |
| b0348b90 LB |
189 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
| 190 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
| 191 | ||
| 1da177e4 LT |
192 | #elif defined(CONFIG_ARCH_INNOKOM) || \ |
| 193 | defined(CONFIG_MACH_MAINSTONE) || \ | |
| 194 | defined(CONFIG_ARCH_PXA_IDP) || \ | |
| 195 | defined(CONFIG_ARCH_RAMSES) | |
| 196 | ||
| 197 | #define SMC_CAN_USE_8BIT 1 | |
| 198 | #define SMC_CAN_USE_16BIT 1 | |
| 199 | #define SMC_CAN_USE_32BIT 1 | |
| 200 | #define SMC_IO_SHIFT 0 | |
| 201 | #define SMC_NOWAIT 1 | |
| 202 | #define SMC_USE_PXA_DMA 1 | |
| 203 | ||
| 204 | #define SMC_inb(a, r) readb((a) + (r)) | |
| 205 | #define SMC_inw(a, r) readw((a) + (r)) | |
| 206 | #define SMC_inl(a, r) readl((a) + (r)) | |
| 207 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
| 208 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
| 209 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
| 210 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
| 211 | ||
| 212 | /* We actually can't write halfwords properly if not word aligned */ | |
| 213 | static inline void | |
| eb1d6988 | 214 | SMC_outw(u16 val, void __iomem *ioaddr, int reg) |
| 1da177e4 LT |
215 | { |
| 216 | if (reg & 2) { | |
| 217 | unsigned int v = val << 16; | |
| 218 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
| 219 | writel(v, ioaddr + (reg & ~2)); | |
| 220 | } else { | |
| 221 | writew(val, ioaddr + reg); | |
| 222 | } | |
| 223 | } | |
| 224 | ||
| 225 | #elif defined(CONFIG_ARCH_OMAP) | |
| 226 | ||
| 227 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
| 228 | #define SMC_CAN_USE_8BIT 0 | |
| 229 | #define SMC_CAN_USE_16BIT 1 | |
| 230 | #define SMC_CAN_USE_32BIT 0 | |
| 231 | #define SMC_IO_SHIFT 0 | |
| 232 | #define SMC_NOWAIT 1 | |
| 233 | ||
| 1da177e4 LT |
234 | #define SMC_inw(a, r) readw((a) + (r)) |
| 235 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
| 236 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
| 237 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
| 1da177e4 | 238 | |
| 5f13e7ec DB |
239 | #include <asm/mach-types.h> |
| 240 | #include <asm/arch/cpu.h> | |
| 241 | ||
| 9ded96f2 | 242 | #define SMC_IRQ_FLAGS (( \ |
| 5f13e7ec DB |
243 | machine_is_omap_h2() \ |
| 244 | || machine_is_omap_h3() \ | |
| f1b7c5f4 | 245 | || machine_is_omap_h4() \ |
| af44f5bf | 246 | || (machine_is_omap_innovator() && !cpu_is_omap1510()) \ |
| 1fb9df5d | 247 | ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING) |
| 5f13e7ec DB |
248 | |
| 249 | ||
| 1da177e4 LT |
250 | #elif defined(CONFIG_SH_SH4202_MICRODEV) |
| 251 | ||
| 252 | #define SMC_CAN_USE_8BIT 0 | |
| 253 | #define SMC_CAN_USE_16BIT 1 | |
| 254 | #define SMC_CAN_USE_32BIT 0 | |
| 255 | ||
| 256 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
| 257 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
| 258 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) | |
| 259 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
| 260 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) | |
| 261 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) | |
| 262 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) | |
| 263 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) | |
| 264 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
| 265 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
| 266 | ||
| 9ded96f2 | 267 | #define SMC_IRQ_FLAGS (0) |
| 1da177e4 LT |
268 | |
| 269 | #elif defined(CONFIG_ISA) | |
| 270 | ||
| 271 | #define SMC_CAN_USE_8BIT 1 | |
| 272 | #define SMC_CAN_USE_16BIT 1 | |
| 273 | #define SMC_CAN_USE_32BIT 0 | |
| 274 | ||
| 275 | #define SMC_inb(a, r) inb((a) + (r)) | |
| 276 | #define SMC_inw(a, r) inw((a) + (r)) | |
| 277 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
| 278 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
| 279 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
| 280 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
| 281 | ||
| 5125ed91 NI |
282 | #elif defined(CONFIG_SUPERH) |
| 283 | ||
| 6026ee67 | 284 | #ifdef CONFIG_SOLUTION_ENGINE |
| 5125ed91 NI |
285 | #define SMC_CAN_USE_8BIT 0 |
| 286 | #define SMC_CAN_USE_16BIT 1 | |
| 287 | #define SMC_CAN_USE_32BIT 0 | |
| 288 | #define SMC_IO_SHIFT 0 | |
| 289 | #define SMC_NOWAIT 1 | |
| 290 | ||
| 5125ed91 | 291 | #define SMC_inw(a, r) inw((a) + (r)) |
| 5125ed91 NI |
292 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) |
| 293 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
| 294 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
| 295 | ||
| 296 | #else /* BOARDS */ | |
| 297 | ||
| 298 | #define SMC_CAN_USE_8BIT 1 | |
| 299 | #define SMC_CAN_USE_16BIT 1 | |
| 300 | #define SMC_CAN_USE_32BIT 1 | |
| 301 | ||
| 302 | #define SMC_inb(a, r) inb((a) + (r)) | |
| 303 | #define SMC_inw(a, r) inw((a) + (r)) | |
| 304 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
| 305 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
| 306 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
| 307 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
| 308 | ||
| 309 | #endif /* BOARDS */ | |
| 310 | ||
| 311 | #define set_irq_type(irq, type) do {} while (0) | |
| 312 | ||
| 1da177e4 LT |
313 | #elif defined(CONFIG_M32R) |
| 314 | ||
| 315 | #define SMC_CAN_USE_8BIT 0 | |
| 316 | #define SMC_CAN_USE_16BIT 1 | |
| 317 | #define SMC_CAN_USE_32BIT 0 | |
| 318 | ||
| 59dc76a4 | 319 | #define SMC_inb(a, r) inb(((u32)a) + (r)) |
| f3ac9fbf HT |
320 | #define SMC_inw(a, r) inw(((u32)a) + (r)) |
| 321 | #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) | |
| 322 | #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) | |
| 323 | #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) | |
| 324 | #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) | |
| 1da177e4 | 325 | |
| 9ded96f2 | 326 | #define SMC_IRQ_FLAGS (0) |
| 1da177e4 LT |
327 | |
| 328 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
| 329 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
| 330 | ||
| d4adcffb MS |
331 | #elif defined(CONFIG_MACH_LPD79520) \ |
| 332 | || defined(CONFIG_MACH_LPD7A400) \ | |
| 333 | || defined(CONFIG_MACH_LPD7A404) | |
| 1da177e4 | 334 | |
| d4adcffb MS |
335 | /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the |
| 336 | * way that the CPU handles chip selects and the way that the SMC chip | |
| 337 | * expects the chip select to operate. Refer to | |
| 1da177e4 | 338 | * Documentation/arm/Sharp-LH/IOBarrier for details. The read from |
| d4adcffb MS |
339 | * IOBARRIER is a byte, in order that we read the least-common |
| 340 | * denominator. It would be wasteful to read 32 bits from an 8-bit | |
| 341 | * accessible region. | |
| 1da177e4 LT |
342 | * |
| 343 | * There is no explicit protection against interrupts intervening | |
| 344 | * between the writew and the IOBARRIER. In SMC ISR there is a | |
| 345 | * preamble that performs an IOBARRIER in the extremely unlikely event | |
| 346 | * that the driver interrupts itself between a writew to the chip an | |
| 347 | * the IOBARRIER that follows *and* the cache is large enough that the | |
| 348 | * first off-chip access while handing the interrupt is to the SMC | |
| 349 | * chip. Other devices in the same address space as the SMC chip must | |
| 350 | * be aware of the potential for trouble and perform a similar | |
| 351 | * IOBARRIER on entry to their ISR. | |
| 352 | */ | |
| 353 | ||
| 354 | #include <asm/arch/constants.h> /* IOBARRIER_VIRT */ | |
| 355 | ||
| 356 | #define SMC_CAN_USE_8BIT 0 | |
| 357 | #define SMC_CAN_USE_16BIT 1 | |
| 358 | #define SMC_CAN_USE_32BIT 0 | |
| 359 | #define SMC_NOWAIT 0 | |
| d4adcffb | 360 | #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT) |
| 1da177e4 | 361 | |
| d4adcffb MS |
362 | #define SMC_inw(a,r)\ |
| 363 | ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; }) | |
| 364 | #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; }) | |
| 1da177e4 | 365 | |
| d4adcffb MS |
366 | #define SMC_insw LPD7_SMC_insw |
| 367 | static inline void LPD7_SMC_insw (unsigned char* a, int r, | |
| 368 | unsigned char* p, int l) | |
| 369 | { | |
| 370 | unsigned short* ps = (unsigned short*) p; | |
| 371 | while (l-- > 0) { | |
| 372 | *ps++ = readw (a + r); | |
| 373 | LPD7X_IOBARRIER; | |
| 374 | } | |
| 375 | } | |
| 09779c6d | 376 | |
| d4adcffb MS |
377 | #define SMC_outsw LPD7_SMC_outsw |
| 378 | static inline void LPD7_SMC_outsw (unsigned char* a, int r, | |
| 379 | unsigned char* p, int l) | |
| 1da177e4 LT |
380 | { |
| 381 | unsigned short* ps = (unsigned short*) p; | |
| 382 | while (l-- > 0) { | |
| 383 | writew (*ps++, a + r); | |
| d4adcffb | 384 | LPD7X_IOBARRIER; |
| 1da177e4 LT |
385 | } |
| 386 | } | |
| 387 | ||
| d4adcffb | 388 | #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER |
| 1da177e4 LT |
389 | |
| 390 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
| 391 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
| 392 | ||
| 55793455 PP |
393 | #elif defined(CONFIG_SOC_AU1X00) |
| 394 | ||
| 395 | #include <au1xxx.h> | |
| 396 | ||
| 397 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
| 398 | #define SMC_CAN_USE_8BIT 0 | |
| 399 | #define SMC_CAN_USE_16BIT 1 | |
| 400 | #define SMC_CAN_USE_32BIT 0 | |
| 401 | #define SMC_IO_SHIFT 0 | |
| 402 | #define SMC_NOWAIT 1 | |
| 403 | ||
| 404 | #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r))) | |
| 405 | #define SMC_insw(a, r, p, l) \ | |
| 406 | do { \ | |
| 407 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
| 408 | int _l = (l); \ | |
| 409 | u16 *_p = (u16 *)(p); \ | |
| 410 | while (_l-- > 0) \ | |
| 411 | *_p++ = au_readw(_a); \ | |
| 412 | } while(0) | |
| 413 | #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r))) | |
| 414 | #define SMC_outsw(a, r, p, l) \ | |
| 415 | do { \ | |
| 416 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
| 417 | int _l = (l); \ | |
| 418 | const u16 *_p = (const u16 *)(p); \ | |
| 419 | while (_l-- > 0) \ | |
| 420 | au_writew(*_p++ , _a); \ | |
| 421 | } while(0) | |
| 422 | ||
| 9ded96f2 | 423 | #define SMC_IRQ_FLAGS (0) |
| 33fee56a DS |
424 | |
| 425 | #elif defined(CONFIG_ARCH_VERSATILE) | |
| 426 | ||
| 427 | #define SMC_CAN_USE_8BIT 1 | |
| 428 | #define SMC_CAN_USE_16BIT 1 | |
| 429 | #define SMC_CAN_USE_32BIT 1 | |
| 430 | #define SMC_NOWAIT 1 | |
| 431 | ||
| 432 | #define SMC_inb(a, r) readb((a) + (r)) | |
| 433 | #define SMC_inw(a, r) readw((a) + (r)) | |
| 434 | #define SMC_inl(a, r) readl((a) + (r)) | |
| 435 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
| 436 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
| 437 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
| 438 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
| 439 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
| 440 | ||
| 441 | #define SMC_IRQ_FLAGS (0) | |
| 55793455 | 442 | |
| 1da177e4 LT |
443 | #else |
| 444 | ||
| 445 | #define SMC_CAN_USE_8BIT 1 | |
| 446 | #define SMC_CAN_USE_16BIT 1 | |
| 447 | #define SMC_CAN_USE_32BIT 1 | |
| 448 | #define SMC_NOWAIT 1 | |
| 449 | ||
| 450 | #define SMC_inb(a, r) readb((a) + (r)) | |
| 451 | #define SMC_inw(a, r) readw((a) + (r)) | |
| 452 | #define SMC_inl(a, r) readl((a) + (r)) | |
| 453 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
| 454 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
| 455 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
| 456 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
| 457 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
| 458 | ||
| 459 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
| 460 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
| 461 | ||
| 462 | #endif | |
| 463 | ||
| 1da177e4 LT |
464 | #ifdef SMC_USE_PXA_DMA |
| 465 | /* | |
| 466 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is | |
| 467 | * always happening in irq context so no need to worry about races. TX is | |
| 468 | * different and probably not worth it for that reason, and not as critical | |
| 469 | * as RX which can overrun memory and lose packets. | |
| 470 | */ | |
| 471 | #include <linux/dma-mapping.h> | |
| 472 | #include <asm/dma.h> | |
| 473 | #include <asm/arch/pxa-regs.h> | |
| 474 | ||
| 475 | #ifdef SMC_insl | |
| 476 | #undef SMC_insl | |
| 477 | #define SMC_insl(a, r, p, l) \ | |
| 478 | smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) | |
| 479 | static inline void | |
| eb1d6988 | 480 | smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, |
| 1da177e4 LT |
481 | u_char *buf, int len) |
| 482 | { | |
| 483 | dma_addr_t dmabuf; | |
| 484 | ||
| 485 | /* fallback if no DMA available */ | |
| 486 | if (dma == (unsigned char)-1) { | |
| 487 | readsl(ioaddr + reg, buf, len); | |
| 488 | return; | |
| 489 | } | |
| 490 | ||
| 491 | /* 64 bit alignment is required for memory to memory DMA */ | |
| 492 | if ((long)buf & 4) { | |
| 493 | *((u32 *)buf) = SMC_inl(ioaddr, reg); | |
| 494 | buf += 4; | |
| 495 | len--; | |
| 496 | } | |
| 497 | ||
| 498 | len *= 4; | |
| 499 | dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); | |
| 500 | DCSR(dma) = DCSR_NODESC; | |
| 501 | DTADR(dma) = dmabuf; | |
| 502 | DSADR(dma) = physaddr + reg; | |
| 503 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
| 504 | DCMD_WIDTH4 | (DCMD_LENGTH & len)); | |
| 505 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
| 506 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
| 507 | cpu_relax(); | |
| 508 | DCSR(dma) = 0; | |
| 509 | dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); | |
| 510 | } | |
| 511 | #endif | |
| 512 | ||
| 513 | #ifdef SMC_insw | |
| 514 | #undef SMC_insw | |
| 515 | #define SMC_insw(a, r, p, l) \ | |
| 516 | smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) | |
| 517 | static inline void | |
| eb1d6988 | 518 | smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, |
| 1da177e4 LT |
519 | u_char *buf, int len) |
| 520 | { | |
| 521 | dma_addr_t dmabuf; | |
| 522 | ||
| 523 | /* fallback if no DMA available */ | |
| 524 | if (dma == (unsigned char)-1) { | |
| 525 | readsw(ioaddr + reg, buf, len); | |
| 526 | return; | |
| 527 | } | |
| 528 | ||
| 529 | /* 64 bit alignment is required for memory to memory DMA */ | |
| 530 | while ((long)buf & 6) { | |
| 531 | *((u16 *)buf) = SMC_inw(ioaddr, reg); | |
| 532 | buf += 2; | |
| 533 | len--; | |
| 534 | } | |
| 535 | ||
| 536 | len *= 2; | |
| 537 | dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); | |
| 538 | DCSR(dma) = DCSR_NODESC; | |
| 539 | DTADR(dma) = dmabuf; | |
| 540 | DSADR(dma) = physaddr + reg; | |
| 541 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
| 542 | DCMD_WIDTH2 | (DCMD_LENGTH & len)); | |
| 543 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
| 544 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
| 545 | cpu_relax(); | |
| 546 | DCSR(dma) = 0; | |
| 547 | dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); | |
| 548 | } | |
| 549 | #endif | |
| 550 | ||
| 551 | static void | |
| 7d12e780 | 552 | smc_pxa_dma_irq(int dma, void *dummy) |
| 1da177e4 LT |
553 | { |
| 554 | DCSR(dma) = 0; | |
| 555 | } | |
| 556 | #endif /* SMC_USE_PXA_DMA */ | |
| 557 | ||
| 558 | ||
| 09779c6d NP |
559 | /* |
| 560 | * Everything a particular hardware setup needs should have been defined | |
| 561 | * at this point. Add stubs for the undefined cases, mainly to avoid | |
| 562 | * compilation warnings since they'll be optimized away, or to prevent buggy | |
| 563 | * use of them. | |
| 564 | */ | |
| 565 | ||
| 566 | #if ! SMC_CAN_USE_32BIT | |
| 567 | #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) | |
| 568 | #define SMC_outl(x, ioaddr, reg) BUG() | |
| 569 | #define SMC_insl(a, r, p, l) BUG() | |
| 570 | #define SMC_outsl(a, r, p, l) BUG() | |
| 571 | #endif | |
| 572 | ||
| 573 | #if !defined(SMC_insl) || !defined(SMC_outsl) | |
| 574 | #define SMC_insl(a, r, p, l) BUG() | |
| 575 | #define SMC_outsl(a, r, p, l) BUG() | |
| 576 | #endif | |
| 577 | ||
| 578 | #if ! SMC_CAN_USE_16BIT | |
| 579 | ||
| 580 | /* | |
| 581 | * Any 16-bit access is performed with two 8-bit accesses if the hardware | |
| 582 | * can't do it directly. Most registers are 16-bit so those are mandatory. | |
| 583 | */ | |
| 584 | #define SMC_outw(x, ioaddr, reg) \ | |
| 585 | do { \ | |
| 586 | unsigned int __val16 = (x); \ | |
| 587 | SMC_outb( __val16, ioaddr, reg ); \ | |
| 588 | SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ | |
| 589 | } while (0) | |
| 590 | #define SMC_inw(ioaddr, reg) \ | |
| 591 | ({ \ | |
| 592 | unsigned int __val16; \ | |
| 593 | __val16 = SMC_inb( ioaddr, reg ); \ | |
| 594 | __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ | |
| 595 | __val16; \ | |
| 596 | }) | |
| 597 | ||
| 598 | #define SMC_insw(a, r, p, l) BUG() | |
| 599 | #define SMC_outsw(a, r, p, l) BUG() | |
| 600 | ||
| 601 | #endif | |
| 602 | ||
| 603 | #if !defined(SMC_insw) || !defined(SMC_outsw) | |
| 604 | #define SMC_insw(a, r, p, l) BUG() | |
| 605 | #define SMC_outsw(a, r, p, l) BUG() | |
| 606 | #endif | |
| 607 | ||
| 608 | #if ! SMC_CAN_USE_8BIT | |
| 609 | #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) | |
| 610 | #define SMC_outb(x, ioaddr, reg) BUG() | |
| 611 | #define SMC_insb(a, r, p, l) BUG() | |
| 612 | #define SMC_outsb(a, r, p, l) BUG() | |
| 613 | #endif | |
| 614 | ||
| 615 | #if !defined(SMC_insb) || !defined(SMC_outsb) | |
| 616 | #define SMC_insb(a, r, p, l) BUG() | |
| 617 | #define SMC_outsb(a, r, p, l) BUG() | |
| 618 | #endif | |
| 619 | ||
| 620 | #ifndef SMC_CAN_USE_DATACS | |
| 621 | #define SMC_CAN_USE_DATACS 0 | |
| 622 | #endif | |
| 623 | ||
| 1da177e4 LT |
624 | #ifndef SMC_IO_SHIFT |
| 625 | #define SMC_IO_SHIFT 0 | |
| 626 | #endif | |
| 09779c6d NP |
627 | |
| 628 | #ifndef SMC_IRQ_FLAGS | |
| 1fb9df5d | 629 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING |
| 09779c6d NP |
630 | #endif |
| 631 | ||
| 632 | #ifndef SMC_INTERRUPT_PREAMBLE | |
| 633 | #define SMC_INTERRUPT_PREAMBLE | |
| 634 | #endif | |
| 635 | ||
| 636 | ||
| 637 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ | |
| 1da177e4 LT |
638 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) |
| 639 | #define SMC_DATA_EXTENT (4) | |
| 640 | ||
| 641 | /* | |
| 642 | . Bank Select Register: | |
| 643 | . | |
| 644 | . yyyy yyyy 0000 00xx | |
| 645 | . xx = bank number | |
| 646 | . yyyy yyyy = 0x33, for identification purposes. | |
| 647 | */ | |
| 648 | #define BANK_SELECT (14 << SMC_IO_SHIFT) | |
| 649 | ||
| 650 | ||
| 651 | // Transmit Control Register | |
| 652 | /* BANK 0 */ | |
| 653 | #define TCR_REG SMC_REG(0x0000, 0) | |
| 654 | #define TCR_ENABLE 0x0001 // When 1 we can transmit | |
| 655 | #define TCR_LOOP 0x0002 // Controls output pin LBK | |
| 656 | #define TCR_FORCOL 0x0004 // When 1 will force a collision | |
| 657 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 | |
| 658 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames | |
| 659 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier | |
| 660 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation | |
| 661 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error | |
| 662 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback | |
| 663 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode | |
| 664 | ||
| 665 | #define TCR_CLEAR 0 /* do NOTHING */ | |
| 666 | /* the default settings for the TCR register : */ | |
| 667 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) | |
| 668 | ||
| 669 | ||
| 670 | // EPH Status Register | |
| 671 | /* BANK 0 */ | |
| 672 | #define EPH_STATUS_REG SMC_REG(0x0002, 0) | |
| 673 | #define ES_TX_SUC 0x0001 // Last TX was successful | |
| 674 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx | |
| 675 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx | |
| 676 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast | |
| 677 | #define ES_16COL 0x0010 // 16 Collisions Reached | |
| 678 | #define ES_SQET 0x0020 // Signal Quality Error Test | |
| 679 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast | |
| 680 | #define ES_TXDEFR 0x0080 // Transmit Deferred | |
| 681 | #define ES_LATCOL 0x0200 // Late collision detected on last tx | |
| 682 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense | |
| 683 | #define ES_EXC_DEF 0x0800 // Excessive Deferral | |
| 684 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication | |
| 685 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin | |
| 686 | #define ES_TXUNRN 0x8000 // Tx Underrun | |
| 687 | ||
| 688 | ||
| 689 | // Receive Control Register | |
| 690 | /* BANK 0 */ | |
| 691 | #define RCR_REG SMC_REG(0x0004, 0) | |
| 692 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted | |
| 693 | #define RCR_PRMS 0x0002 // Enable promiscuous mode | |
| 694 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames | |
| 695 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets | |
| 696 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets | |
| 697 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision | |
| 698 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier | |
| 699 | #define RCR_SOFTRST 0x8000 // resets the chip | |
| 700 | ||
| 701 | /* the normal settings for the RCR register : */ | |
| 702 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
| 703 | #define RCR_CLEAR 0x0 // set it to a base state | |
| 704 | ||
| 705 | ||
| 706 | // Counter Register | |
| 707 | /* BANK 0 */ | |
| 708 | #define COUNTER_REG SMC_REG(0x0006, 0) | |
| 709 | ||
| 710 | ||
| 711 | // Memory Information Register | |
| 712 | /* BANK 0 */ | |
| 713 | #define MIR_REG SMC_REG(0x0008, 0) | |
| 714 | ||
| 715 | ||
| 716 | // Receive/Phy Control Register | |
| 717 | /* BANK 0 */ | |
| 718 | #define RPC_REG SMC_REG(0x000A, 0) | |
| 719 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. | |
| 720 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode | |
| 721 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode | |
| 722 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb | |
| 723 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb | |
| 724 | #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect | |
| 725 | #define RPC_LED_RES (0x01) // LED = Reserved | |
| 726 | #define RPC_LED_10 (0x02) // LED = 10Mbps link detect | |
| 727 | #define RPC_LED_FD (0x03) // LED = Full Duplex Mode | |
| 728 | #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred | |
| 729 | #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect | |
| 730 | #define RPC_LED_TX (0x06) // LED = TX packet occurred | |
| 731 | #define RPC_LED_RX (0x07) // LED = RX packet occurred | |
| 732 | ||
| 733 | #ifndef RPC_LSA_DEFAULT | |
| 734 | #define RPC_LSA_DEFAULT RPC_LED_100 | |
| 735 | #endif | |
| 736 | #ifndef RPC_LSB_DEFAULT | |
| 737 | #define RPC_LSB_DEFAULT RPC_LED_FD | |
| 738 | #endif | |
| 739 | ||
| 740 | #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) | |
| 741 | ||
| 742 | ||
| 743 | /* Bank 0 0x0C is reserved */ | |
| 744 | ||
| 745 | // Bank Select Register | |
| 746 | /* All Banks */ | |
| 747 | #define BSR_REG 0x000E | |
| 748 | ||
| 749 | ||
| 750 | // Configuration Reg | |
| 751 | /* BANK 1 */ | |
| 752 | #define CONFIG_REG SMC_REG(0x0000, 1) | |
| 753 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy | |
| 754 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL | |
| 755 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus | |
| 756 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. | |
| 757 | ||
| 758 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
| 759 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
| 760 | ||
| 761 | ||
| 762 | // Base Address Register | |
| 763 | /* BANK 1 */ | |
| 764 | #define BASE_REG SMC_REG(0x0002, 1) | |
| 765 | ||
| 766 | ||
| 767 | // Individual Address Registers | |
| 768 | /* BANK 1 */ | |
| 769 | #define ADDR0_REG SMC_REG(0x0004, 1) | |
| 770 | #define ADDR1_REG SMC_REG(0x0006, 1) | |
| 771 | #define ADDR2_REG SMC_REG(0x0008, 1) | |
| 772 | ||
| 773 | ||
| 774 | // General Purpose Register | |
| 775 | /* BANK 1 */ | |
| 776 | #define GP_REG SMC_REG(0x000A, 1) | |
| 777 | ||
| 778 | ||
| 779 | // Control Register | |
| 780 | /* BANK 1 */ | |
| 781 | #define CTL_REG SMC_REG(0x000C, 1) | |
| 782 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received | |
| 783 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically | |
| 784 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt | |
| 785 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt | |
| 786 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt | |
| 787 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store | |
| 788 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers | |
| 789 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM | |
| 790 | ||
| 791 | ||
| 792 | // MMU Command Register | |
| 793 | /* BANK 2 */ | |
| 794 | #define MMU_CMD_REG SMC_REG(0x0000, 2) | |
| 795 | #define MC_BUSY 1 // When 1 the last release has not completed | |
| 796 | #define MC_NOP (0<<5) // No Op | |
| 797 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets | |
| 798 | #define MC_RESET (2<<5) // Reset MMU to initial state | |
| 799 | #define MC_REMOVE (3<<5) // Remove the current rx packet | |
| 800 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet | |
| 801 | #define MC_FREEPKT (5<<5) // Release packet in PNR register | |
| 802 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit | |
| 803 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs | |
| 804 | ||
| 805 | ||
| 806 | // Packet Number Register | |
| 807 | /* BANK 2 */ | |
| 808 | #define PN_REG SMC_REG(0x0002, 2) | |
| 809 | ||
| 810 | ||
| 811 | // Allocation Result Register | |
| 812 | /* BANK 2 */ | |
| 813 | #define AR_REG SMC_REG(0x0003, 2) | |
| 814 | #define AR_FAILED 0x80 // Alocation Failed | |
| 815 | ||
| 816 | ||
| 817 | // TX FIFO Ports Register | |
| 818 | /* BANK 2 */ | |
| 819 | #define TXFIFO_REG SMC_REG(0x0004, 2) | |
| 820 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty | |
| 821 | ||
| 822 | // RX FIFO Ports Register | |
| 823 | /* BANK 2 */ | |
| 824 | #define RXFIFO_REG SMC_REG(0x0005, 2) | |
| 825 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty | |
| 826 | ||
| 827 | #define FIFO_REG SMC_REG(0x0004, 2) | |
| 828 | ||
| 829 | // Pointer Register | |
| 830 | /* BANK 2 */ | |
| 831 | #define PTR_REG SMC_REG(0x0006, 2) | |
| 832 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area | |
| 833 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access | |
| 834 | #define PTR_READ 0x2000 // When 1 the operation is a read | |
| 835 | ||
| 836 | ||
| 837 | // Data Register | |
| 838 | /* BANK 2 */ | |
| 839 | #define DATA_REG SMC_REG(0x0008, 2) | |
| 840 | ||
| 841 | ||
| 842 | // Interrupt Status/Acknowledge Register | |
| 843 | /* BANK 2 */ | |
| 844 | #define INT_REG SMC_REG(0x000C, 2) | |
| 845 | ||
| 846 | ||
| 847 | // Interrupt Mask Register | |
| 848 | /* BANK 2 */ | |
| 849 | #define IM_REG SMC_REG(0x000D, 2) | |
| 850 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt | |
| 851 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt | |
| 852 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section | |
| 853 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns | |
| 854 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed | |
| 855 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty | |
| 856 | #define IM_TX_INT 0x02 // Transmit Interrupt | |
| 857 | #define IM_RCV_INT 0x01 // Receive Interrupt | |
| 858 | ||
| 859 | ||
| 860 | // Multicast Table Registers | |
| 861 | /* BANK 3 */ | |
| 862 | #define MCAST_REG1 SMC_REG(0x0000, 3) | |
| 863 | #define MCAST_REG2 SMC_REG(0x0002, 3) | |
| 864 | #define MCAST_REG3 SMC_REG(0x0004, 3) | |
| 865 | #define MCAST_REG4 SMC_REG(0x0006, 3) | |
| 866 | ||
| 867 | ||
| 868 | // Management Interface Register (MII) | |
| 869 | /* BANK 3 */ | |
| 870 | #define MII_REG SMC_REG(0x0008, 3) | |
| 871 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup | |
| 872 | #define MII_MDOE 0x0008 // MII Output Enable | |
| 873 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK | |
| 874 | #define MII_MDI 0x0002 // MII Input, pin MDI | |
| 875 | #define MII_MDO 0x0001 // MII Output, pin MDO | |
| 876 | ||
| 877 | ||
| 878 | // Revision Register | |
| 879 | /* BANK 3 */ | |
| 880 | /* ( hi: chip id low: rev # ) */ | |
| 881 | #define REV_REG SMC_REG(0x000A, 3) | |
| 882 | ||
| 883 | ||
| 884 | // Early RCV Register | |
| 885 | /* BANK 3 */ | |
| 886 | /* this is NOT on SMC9192 */ | |
| 887 | #define ERCV_REG SMC_REG(0x000C, 3) | |
| 888 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received | |
| 889 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask | |
| 890 | ||
| 891 | ||
| 892 | // External Register | |
| 893 | /* BANK 7 */ | |
| 894 | #define EXT_REG SMC_REG(0x0000, 7) | |
| 895 | ||
| 896 | ||
| 897 | #define CHIP_9192 3 | |
| 898 | #define CHIP_9194 4 | |
| 899 | #define CHIP_9195 5 | |
| 900 | #define CHIP_9196 6 | |
| 901 | #define CHIP_91100 7 | |
| 902 | #define CHIP_91100FD 8 | |
| 903 | #define CHIP_91111FD 9 | |
| 904 | ||
| 905 | static const char * chip_ids[ 16 ] = { | |
| 906 | NULL, NULL, NULL, | |
| 907 | /* 3 */ "SMC91C90/91C92", | |
| 908 | /* 4 */ "SMC91C94", | |
| 909 | /* 5 */ "SMC91C95", | |
| 910 | /* 6 */ "SMC91C96", | |
| 911 | /* 7 */ "SMC91C100", | |
| 912 | /* 8 */ "SMC91C100FD", | |
| 913 | /* 9 */ "SMC91C11xFD", | |
| 914 | NULL, NULL, NULL, | |
| 915 | NULL, NULL, NULL}; | |
| 916 | ||
| 917 | ||
| 1da177e4 LT |
918 | /* |
| 919 | . Receive status bits | |
| 920 | */ | |
| 921 | #define RS_ALGNERR 0x8000 | |
| 922 | #define RS_BRODCAST 0x4000 | |
| 923 | #define RS_BADCRC 0x2000 | |
| 924 | #define RS_ODDFRAME 0x1000 | |
| 925 | #define RS_TOOLONG 0x0800 | |
| 926 | #define RS_TOOSHORT 0x0400 | |
| 927 | #define RS_MULTICAST 0x0001 | |
| 928 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
| 929 | ||
| 930 | ||
| 931 | /* | |
| 932 | * PHY IDs | |
| 933 | * LAN83C183 == LAN91C111 Internal PHY | |
| 934 | */ | |
| 935 | #define PHY_LAN83C183 0x0016f840 | |
| 936 | #define PHY_LAN83C180 0x02821c50 | |
| 937 | ||
| 938 | /* | |
| 939 | * PHY Register Addresses (LAN91C111 Internal PHY) | |
| 940 | * | |
| 941 | * Generic PHY registers can be found in <linux/mii.h> | |
| 942 | * | |
| 943 | * These phy registers are specific to our on-board phy. | |
| 944 | */ | |
| 945 | ||
| 946 | // PHY Configuration Register 1 | |
| 947 | #define PHY_CFG1_REG 0x10 | |
| 948 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled | |
| 949 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled | |
| 950 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down | |
| 951 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler | |
| 952 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable | |
| 953 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled | |
| 954 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) | |
| 955 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db | |
| 956 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust | |
| 957 | #define PHY_CFG1_TLVL_MASK 0x003C | |
| 958 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time | |
| 959 | ||
| 960 | ||
| 961 | // PHY Configuration Register 2 | |
| 962 | #define PHY_CFG2_REG 0x11 | |
| 963 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled | |
| 964 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled | |
| 965 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) | |
| 966 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo | |
| 967 | ||
| 968 | // PHY Status Output (and Interrupt status) Register | |
| 969 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) | |
| 970 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read | |
| 971 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected | |
| 972 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync | |
| 973 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx | |
| 974 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx | |
| 975 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx | |
| 976 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected | |
| 977 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected | |
| 978 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode | |
| 979 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex | |
| 980 | ||
| 981 | // PHY Interrupt/Status Mask Register | |
| 982 | #define PHY_MASK_REG 0x13 // Interrupt Mask | |
| 983 | // Uses the same bit definitions as PHY_INT_REG | |
| 984 | ||
| 985 | ||
| 986 | /* | |
| 987 | * SMC91C96 ethernet config and status registers. | |
| 988 | * These are in the "attribute" space. | |
| 989 | */ | |
| 990 | #define ECOR 0x8000 | |
| 991 | #define ECOR_RESET 0x80 | |
| 992 | #define ECOR_LEVEL_IRQ 0x40 | |
| 993 | #define ECOR_WR_ATTRIB 0x04 | |
| 994 | #define ECOR_ENABLE 0x01 | |
| 995 | ||
| 996 | #define ECSR 0x8002 | |
| 997 | #define ECSR_IOIS8 0x20 | |
| 998 | #define ECSR_PWRDWN 0x04 | |
| 999 | #define ECSR_INT 0x02 | |
| 1000 | ||
| 1001 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) | |
| 1002 | ||
| 1003 | ||
| 1004 | /* | |
| 1005 | * Macros to abstract register access according to the data bus | |
| 1006 | * capabilities. Please use those and not the in/out primitives. | |
| 1007 | * Note: the following macros do *not* select the bank -- this must | |
| 1008 | * be done separately as needed in the main code. The SMC_REG() macro | |
| 1009 | * only uses the bank argument for debugging purposes (when enabled). | |
| 09779c6d NP |
1010 | * |
| 1011 | * Note: despite inline functions being safer, everything leading to this | |
| 1012 | * should preferably be macros to let BUG() display the line number in | |
| 1013 | * the core source code since we're interested in the top call site | |
| 1014 | * not in any inline function location. | |
| 1da177e4 LT |
1015 | */ |
| 1016 | ||
| 1017 | #if SMC_DEBUG > 0 | |
| 1018 | #define SMC_REG(reg, bank) \ | |
| 1019 | ({ \ | |
| 1020 | int __b = SMC_CURRENT_BANK(); \ | |
| 1021 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ | |
| 1022 | printk( "%s: bank reg screwed (0x%04x)\n", \ | |
| 1023 | CARDNAME, __b ); \ | |
| 1024 | BUG(); \ | |
| 1025 | } \ | |
| 1026 | reg<<SMC_IO_SHIFT; \ | |
| 1027 | }) | |
| 1028 | #else | |
| 1029 | #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) | |
| 1030 | #endif | |
| 1031 | ||
| 09779c6d NP |
1032 | /* |
| 1033 | * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not | |
| 1034 | * aligned to a 32 bit boundary. I tell you that does exist! | |
| 1035 | * Fortunately the affected register accesses can be easily worked around | |
| 1036 | * since we can write zeroes to the preceeding 16 bits without adverse | |
| 1037 | * effects and use a 32-bit access. | |
| 1038 | * | |
| 1039 | * Enforce it on any 32-bit capable setup for now. | |
| 1040 | */ | |
| 1041 | #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT | |
| 1042 | ||
| 1043 | #define SMC_GET_PN() \ | |
| 1044 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \ | |
| 1045 | : (SMC_inw(ioaddr, PN_REG) & 0xFF) ) | |
| 1046 | ||
| 1047 | #define SMC_SET_PN(x) \ | |
| 1048 | do { \ | |
| 1049 | if (SMC_MUST_ALIGN_WRITE) \ | |
| 1050 | SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \ | |
| 1051 | else if (SMC_CAN_USE_8BIT) \ | |
| 1052 | SMC_outb(x, ioaddr, PN_REG); \ | |
| 1053 | else \ | |
| 1054 | SMC_outw(x, ioaddr, PN_REG); \ | |
| 1055 | } while (0) | |
| 1056 | ||
| 1057 | #define SMC_GET_AR() \ | |
| 1058 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \ | |
| 1059 | : (SMC_inw(ioaddr, PN_REG) >> 8) ) | |
| 1060 | ||
| 1061 | #define SMC_GET_TXFIFO() \ | |
| 1062 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \ | |
| 1063 | : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) ) | |
| 1064 | ||
| 1065 | #define SMC_GET_RXFIFO() \ | |
| 1066 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \ | |
| 1067 | : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) ) | |
| 1068 | ||
| 1069 | #define SMC_GET_INT() \ | |
| 1070 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \ | |
| 1071 | : (SMC_inw(ioaddr, INT_REG) & 0xFF) ) | |
| 1072 | ||
| 1da177e4 LT |
1073 | #define SMC_ACK_INT(x) \ |
| 1074 | do { \ | |
| 09779c6d NP |
1075 | if (SMC_CAN_USE_8BIT) \ |
| 1076 | SMC_outb(x, ioaddr, INT_REG); \ | |
| 1077 | else { \ | |
| 1078 | unsigned long __flags; \ | |
| 1079 | int __mask; \ | |
| 1080 | local_irq_save(__flags); \ | |
| 1081 | __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ | |
| 1082 | SMC_outw( __mask | (x), ioaddr, INT_REG ); \ | |
| 1083 | local_irq_restore(__flags); \ | |
| 1084 | } \ | |
| 1085 | } while (0) | |
| 1086 | ||
| 1087 | #define SMC_GET_INT_MASK() \ | |
| 1088 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \ | |
| 1089 | : (SMC_inw( ioaddr, INT_REG ) >> 8) ) | |
| 1090 | ||
| 1091 | #define SMC_SET_INT_MASK(x) \ | |
| 1092 | do { \ | |
| 1093 | if (SMC_CAN_USE_8BIT) \ | |
| 1094 | SMC_outb(x, ioaddr, IM_REG); \ | |
| 1095 | else \ | |
| 1096 | SMC_outw((x) << 8, ioaddr, INT_REG); \ | |
| 1097 | } while (0) | |
| 1098 | ||
| 1099 | #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT) | |
| 1100 | ||
| 1101 | #define SMC_SELECT_BANK(x) \ | |
| 1102 | do { \ | |
| 1103 | if (SMC_MUST_ALIGN_WRITE) \ | |
| 1104 | SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ | |
| 1105 | else \ | |
| 1106 | SMC_outw(x, ioaddr, BANK_SELECT); \ | |
| 1107 | } while (0) | |
| 1108 | ||
| 1109 | #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG) | |
| 1110 | ||
| 1111 | #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG) | |
| 1112 | ||
| 1113 | #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG) | |
| 1114 | ||
| 1115 | #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG) | |
| 1116 | ||
| 1117 | #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG) | |
| 1118 | ||
| 1119 | #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG) | |
| 1120 | ||
| 1121 | #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG) | |
| 1122 | ||
| 1123 | #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG) | |
| 1124 | ||
| 1125 | #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG) | |
| 1126 | ||
| 1127 | #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG) | |
| 1128 | ||
| 1129 | #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG) | |
| 1130 | ||
| 1131 | #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG) | |
| 1132 | ||
| 1133 | #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG) | |
| 1134 | ||
| 1135 | #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG) | |
| 1136 | ||
| 1137 | #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG) | |
| 1138 | ||
| 1139 | #define SMC_SET_PTR(x) \ | |
| 1140 | do { \ | |
| 1141 | if (SMC_MUST_ALIGN_WRITE) \ | |
| 1142 | SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \ | |
| 1143 | else \ | |
| 1144 | SMC_outw(x, ioaddr, PTR_REG); \ | |
| 1da177e4 | 1145 | } while (0) |
| 1da177e4 | 1146 | |
| 09779c6d NP |
1147 | #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG) |
| 1148 | ||
| 1149 | #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG) | |
| 1150 | ||
| 1151 | #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG) | |
| 1152 | ||
| 1153 | #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG) | |
| 1154 | ||
| 1155 | #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG) | |
| 1156 | ||
| 1157 | #define SMC_SET_RPC(x) \ | |
| 1158 | do { \ | |
| 1159 | if (SMC_MUST_ALIGN_WRITE) \ | |
| 1160 | SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \ | |
| 1161 | else \ | |
| 1162 | SMC_outw(x, ioaddr, RPC_REG); \ | |
| 1163 | } while (0) | |
| 1164 | ||
| 1165 | #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG) | |
| 1166 | ||
| 1167 | #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG) | |
| 1da177e4 LT |
1168 | |
| 1169 | #ifndef SMC_GET_MAC_ADDR | |
| 1170 | #define SMC_GET_MAC_ADDR(addr) \ | |
| 1171 | do { \ | |
| 1172 | unsigned int __v; \ | |
| 1173 | __v = SMC_inw( ioaddr, ADDR0_REG ); \ | |
| 1174 | addr[0] = __v; addr[1] = __v >> 8; \ | |
| 1175 | __v = SMC_inw( ioaddr, ADDR1_REG ); \ | |
| 1176 | addr[2] = __v; addr[3] = __v >> 8; \ | |
| 1177 | __v = SMC_inw( ioaddr, ADDR2_REG ); \ | |
| 1178 | addr[4] = __v; addr[5] = __v >> 8; \ | |
| 1179 | } while (0) | |
| 1180 | #endif | |
| 1181 | ||
| 1182 | #define SMC_SET_MAC_ADDR(addr) \ | |
| 1183 | do { \ | |
| 1184 | SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ | |
| 1185 | SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ | |
| 1186 | SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ | |
| 1187 | } while (0) | |
| 1188 | ||
| 1189 | #define SMC_SET_MCAST(x) \ | |
| 1190 | do { \ | |
| 1191 | const unsigned char *mt = (x); \ | |
| 1192 | SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ | |
| 1193 | SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ | |
| 1194 | SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ | |
| 1195 | SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ | |
| 1196 | } while (0) | |
| 1197 | ||
| 1da177e4 LT |
1198 | #define SMC_PUT_PKT_HDR(status, length) \ |
| 1199 | do { \ | |
| 09779c6d NP |
1200 | if (SMC_CAN_USE_32BIT) \ |
| 1201 | SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \ | |
| 1202 | else { \ | |
| 1203 | SMC_outw(status, ioaddr, DATA_REG); \ | |
| 1204 | SMC_outw(length, ioaddr, DATA_REG); \ | |
| 1205 | } \ | |
| 1da177e4 | 1206 | } while (0) |
| 1da177e4 | 1207 | |
| 09779c6d | 1208 | #define SMC_GET_PKT_HDR(status, length) \ |
| 1da177e4 | 1209 | do { \ |
| 09779c6d NP |
1210 | if (SMC_CAN_USE_32BIT) { \ |
| 1211 | unsigned int __val = SMC_inl(ioaddr, DATA_REG); \ | |
| 1212 | (status) = __val & 0xffff; \ | |
| 1213 | (length) = __val >> 16; \ | |
| 1214 | } else { \ | |
| 1215 | (status) = SMC_inw(ioaddr, DATA_REG); \ | |
| 1216 | (length) = SMC_inw(ioaddr, DATA_REG); \ | |
| 1da177e4 LT |
1217 | } \ |
| 1218 | } while (0) | |
| 1da177e4 | 1219 | |
| 09779c6d | 1220 | #define SMC_PUSH_DATA(p, l) \ |
| 1da177e4 | 1221 | do { \ |
| 09779c6d NP |
1222 | if (SMC_CAN_USE_32BIT) { \ |
| 1223 | void *__ptr = (p); \ | |
| 1224 | int __len = (l); \ | |
| fbd81976 | 1225 | void __iomem *__ioaddr = ioaddr; \ |
| 09779c6d NP |
1226 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ |
| 1227 | __len -= 2; \ | |
| 1228 | SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ | |
| 1229 | __ptr += 2; \ | |
| 1230 | } \ | |
| 1231 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
| 1232 | __ioaddr = lp->datacs; \ | |
| 1233 | SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \ | |
| 1234 | if (__len & 2) { \ | |
| 1235 | __ptr += (__len & ~3); \ | |
| 1236 | SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \ | |
| 1237 | } \ | |
| 1238 | } else if (SMC_CAN_USE_16BIT) \ | |
| 1239 | SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \ | |
| 1240 | else if (SMC_CAN_USE_8BIT) \ | |
| 1241 | SMC_outsb(ioaddr, DATA_REG, p, l); \ | |
| 1da177e4 | 1242 | } while (0) |
| 1da177e4 LT |
1243 | |
| 1244 | #define SMC_PULL_DATA(p, l) \ | |
| 09779c6d NP |
1245 | do { \ |
| 1246 | if (SMC_CAN_USE_32BIT) { \ | |
| 1247 | void *__ptr = (p); \ | |
| 1248 | int __len = (l); \ | |
| fbd81976 | 1249 | void __iomem *__ioaddr = ioaddr; \ |
| 09779c6d NP |
1250 | if ((unsigned long)__ptr & 2) { \ |
| 1251 | /* \ | |
| 1252 | * We want 32bit alignment here. \ | |
| 1253 | * Since some buses perform a full \ | |
| 1254 | * 32bit fetch even for 16bit data \ | |
| 1255 | * we can't use SMC_inw() here. \ | |
| 1256 | * Back both source (on-chip) and \ | |
| 1257 | * destination pointers of 2 bytes. \ | |
| 1258 | * This is possible since the call to \ | |
| 1259 | * SMC_GET_PKT_HDR() already advanced \ | |
| 1260 | * the source pointer of 4 bytes, and \ | |
| 1261 | * the skb_reserve(skb, 2) advanced \ | |
| 1262 | * the destination pointer of 2 bytes. \ | |
| 1263 | */ \ | |
| 1264 | __ptr -= 2; \ | |
| 1265 | __len += 2; \ | |
| 1266 | SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ | |
| 1267 | } \ | |
| 1268 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
| 1269 | __ioaddr = lp->datacs; \ | |
| 1da177e4 | 1270 | __len += 2; \ |
| 09779c6d NP |
1271 | SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \ |
| 1272 | } else if (SMC_CAN_USE_16BIT) \ | |
| 1273 | SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \ | |
| 1274 | else if (SMC_CAN_USE_8BIT) \ | |
| 1275 | SMC_insb(ioaddr, DATA_REG, p, l); \ | |
| 1276 | } while (0) | |
| 1da177e4 LT |
1277 | |
| 1278 | #endif /* _SMC91X_H_ */ |