]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/net/smsc911x.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
atl1c: disable L1/L0s when link detected
[mirror_ubuntu-zesty-kernel.git] / drivers / net / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
32#include <linux/crc32.h>
33#include <linux/delay.h>
34#include <linux/errno.h>
35#include <linux/etherdevice.h>
36#include <linux/ethtool.h>
37#include <linux/init.h>
38#include <linux/ioport.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/netdevice.h>
42#include <linux/platform_device.h>
43#include <linux/sched.h>
44#include <linux/slab.h>
45#include <linux/timer.h>
fd9abb3d
SG		 46#include <linux/bug.h>
47#include <linux/bitops.h>
48#include <linux/irq.h>
49#include <linux/io.h>
50#include <linux/phy.h>
51#include <linux/smsc911x.h>
52#include "smsc911x.h"
53
54#define SMSC_CHIPNAME "smsc911x"
55#define SMSC_MDIONAME "smsc911x-mdio"
56#define SMSC_DRV_VERSION "2008-10-21"
57
58MODULE_LICENSE("GPL");
59MODULE_VERSION(SMSC_DRV_VERSION);
60
61#if USE_DEBUG > 0
62static int debug = 16;
63#else
64static int debug = 3;
65#endif
66
67module_param(debug, int, 0);
68MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70struct smsc911x_data {
71 void __iomem *ioaddr;
72
73 unsigned int idrev;
74
75 /* used to decide which workarounds apply */
76 unsigned int generation;
77
78 /* device configuration (copied from platform_data during probe) */
2107fb8b 79 struct smsc911x_platform_config config;
fd9abb3d
SG		 80
81 /* This needs to be acquired before calling any of below:
82 * smsc911x_mac_read(), smsc911x_mac_write()
83 */
84 spinlock_t mac_lock;
85
2107fb8b
SG		 86 /* spinlock to ensure 16-bit accesses are serialised.
87 * unused with a 32-bit bus */
fd9abb3d 88 spinlock_t dev_lock;
fd9abb3d
SG		 89
90 struct phy_device *phy_dev;
91 struct mii_bus *mii_bus;
92 int phy_irq[PHY_MAX_ADDR];
93 unsigned int using_extphy;
94 int last_duplex;
95 int last_carrier;
96
97 u32 msg_enable;
98 unsigned int gpio_setting;
99 unsigned int gpio_orig_setting;
100 struct net_device *dev;
101 struct napi_struct napi;
102
103 unsigned int software_irq_signal;
104
105#ifdef USE_PHY_WORK_AROUND
106#define MIN_PACKET_SIZE (64)
107 char loopback_tx_pkt[MIN_PACKET_SIZE];
108 char loopback_rx_pkt[MIN_PACKET_SIZE];
109 unsigned int resetcount;
110#endif
111
112 /* Members for Multicast filter workaround */
113 unsigned int multicast_update_pending;
114 unsigned int set_bits_mask;
115 unsigned int clear_bits_mask;
116 unsigned int hashhi;
117 unsigned int hashlo;
118};
119
2107fb8b 120/* The 16-bit access functions are significantly slower, due to the locking
fd9abb3d
SG		 121 * necessary. If your bus hardware can be configured to do this for you
122 * (in response to a single 32-bit operation from software), you should use
123 * the 32-bit access functions instead. */
124
125static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
126{
2107fb8b
SG		 127 if (pdata->config.flags & SMSC911X_USE_32BIT)
128 return readl(pdata->ioaddr + reg);
129
130 if (pdata->config.flags & SMSC911X_USE_16BIT) {
131 u32 data;
132 unsigned long flags;
133
134 /* these two 16-bit reads must be performed consecutively, so
135 * must not be interrupted by our own ISR (which would start
136 * another read operation) */
137 spin_lock_irqsave(&pdata->dev_lock, flags);
138 data = ((readw(pdata->ioaddr + reg) & 0xFFFF) |
139 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
140 spin_unlock_irqrestore(&pdata->dev_lock, flags);
141
142 return data;
143 }
fd9abb3d 144
2107fb8b 145 BUG();
702403af 146 return 0;
fd9abb3d
SG		 147}
148
149static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
150 u32 val)
151{
2107fb8b
SG		 152 if (pdata->config.flags & SMSC911X_USE_32BIT) {
153 writel(val, pdata->ioaddr + reg);
154 return;
155 }
156
157 if (pdata->config.flags & SMSC911X_USE_16BIT) {
158 unsigned long flags;
159
160 /* these two 16-bit writes must be performed consecutively, so
161 * must not be interrupted by our own ISR (which would start
162 * another read operation) */
163 spin_lock_irqsave(&pdata->dev_lock, flags);
164 writew(val & 0xFFFF, pdata->ioaddr + reg);
165 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
166 spin_unlock_irqrestore(&pdata->dev_lock, flags);
167 return;
168 }
fd9abb3d 169
2107fb8b 170 BUG();
fd9abb3d
SG		 171}
172
173/* Writes a packet to the TX_DATA_FIFO */
174static inline void
175smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
176 unsigned int wordcount)
177{
2107fb8b
SG		 178 if (pdata->config.flags & SMSC911X_USE_32BIT) {
179 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
180 return;
181 }
182
183 if (pdata->config.flags & SMSC911X_USE_16BIT) {
184 while (wordcount--)
185 smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
186 return;
187 }
188
189 BUG();
fd9abb3d
SG		 190}
191
192/* Reads a packet out of the RX_DATA_FIFO */
193static inline void
194smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
195 unsigned int wordcount)
196{
2107fb8b
SG		 197 if (pdata->config.flags & SMSC911X_USE_32BIT) {
198 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
199 return;
200 }
fd9abb3d 201
2107fb8b
SG		 202 if (pdata->config.flags & SMSC911X_USE_16BIT) {
203 while (wordcount--)
204 *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO);
205 return;
206 }
207
208 BUG();
209}
fd9abb3d
SG		 210
211/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
212 * and smsc911x_mac_write, so assumes mac_lock is held */
213static int smsc911x_mac_complete(struct smsc911x_data *pdata)
214{
215 int i;
216 u32 val;
217
218 SMSC_ASSERT_MAC_LOCK(pdata);
219
220 for (i = 0; i < 40; i++) {
221 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
222 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
223 return 0;
224 }
225 SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
226 "MAC_CSR_CMD: 0x%08X", val);
227 return -EIO;
228}
229
230/* Fetches a MAC register value. Assumes mac_lock is acquired */
231static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
232{
233 unsigned int temp;
234
235 SMSC_ASSERT_MAC_LOCK(pdata);
236
237 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
238 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
239 SMSC_WARNING(HW, "MAC busy at entry");
240 return 0xFFFFFFFF;
241 }
242
243 /* Send the MAC cmd */
244 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
245 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
246
247 /* Workaround for hardware read-after-write restriction */
248 temp = smsc911x_reg_read(pdata, BYTE_TEST);
249
250 /* Wait for the read to complete */
251 if (likely(smsc911x_mac_complete(pdata) == 0))
252 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
253
254 SMSC_WARNING(HW, "MAC busy after read");
255 return 0xFFFFFFFF;
256}
257
258/* Set a mac register, mac_lock must be acquired before calling */
259static void smsc911x_mac_write(struct smsc911x_data *pdata,
260 unsigned int offset, u32 val)
261{
262 unsigned int temp;
263
264 SMSC_ASSERT_MAC_LOCK(pdata);
265
266 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
267 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
268 SMSC_WARNING(HW,
269 "smsc911x_mac_write failed, MAC busy at entry");
270 return;
271 }
272
273 /* Send data to write */
274 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
275
276 /* Write the actual data */
277 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
278 MAC_CSR_CMD_CSR_BUSY_));
279
280 /* Workaround for hardware read-after-write restriction */
281 temp = smsc911x_reg_read(pdata, BYTE_TEST);
282
283 /* Wait for the write to complete */
284 if (likely(smsc911x_mac_complete(pdata) == 0))
285 return;
286
287 SMSC_WARNING(HW,
288 "smsc911x_mac_write failed, MAC busy after write");
289}
290
291/* Get a phy register */
292static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
293{
294 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
295 unsigned long flags;
296 unsigned int addr;
297 int i, reg;
298
299 spin_lock_irqsave(&pdata->mac_lock, flags);
300
301 /* Confirm MII not busy */
302 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
303 SMSC_WARNING(HW,
304 "MII is busy in smsc911x_mii_read???");
305 reg = -EIO;
306 goto out;
307 }
308
309 /* Set the address, index & direction (read from PHY) */
310 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
311 smsc911x_mac_write(pdata, MII_ACC, addr);
312
313 /* Wait for read to complete w/ timeout */
314 for (i = 0; i < 100; i++)
315 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
316 reg = smsc911x_mac_read(pdata, MII_DATA);
317 goto out;
318 }
319
150899d2 320 SMSC_WARNING(HW, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 321 reg = -EIO;
322
323out:
324 spin_unlock_irqrestore(&pdata->mac_lock, flags);
325 return reg;
326}
327
328/* Set a phy register */
329static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
330 u16 val)
331{
332 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
333 unsigned long flags;
334 unsigned int addr;
335 int i, reg;
336
337 spin_lock_irqsave(&pdata->mac_lock, flags);
338
339 /* Confirm MII not busy */
340 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
341 SMSC_WARNING(HW,
342 "MII is busy in smsc911x_mii_write???");
343 reg = -EIO;
344 goto out;
345 }
346
347 /* Put the data to write in the MAC */
348 smsc911x_mac_write(pdata, MII_DATA, val);
349
350 /* Set the address, index & direction (write to PHY) */
351 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
352 MII_ACC_MII_WRITE_;
353 smsc911x_mac_write(pdata, MII_ACC, addr);
354
355 /* Wait for write to complete w/ timeout */
356 for (i = 0; i < 100; i++)
357 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
358 reg = 0;
359 goto out;
360 }
361
362 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
363 reg = -EIO;
364
365out:
366 spin_unlock_irqrestore(&pdata->mac_lock, flags);
367 return reg;
368}
369
d23f028a
SG		 370/* Switch to external phy. Assumes tx and rx are stopped. */
371static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 372{
373 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
374
d23f028a
SG		 375 /* Disable phy clocks to the MAC */
376 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
377 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
378 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
379 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 380
d23f028a
SG		 381 /* Switch to external phy */
382 hwcfg |= HW_CFG_EXT_PHY_EN_;
383 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 384
d23f028a
SG		 385 /* Enable phy clocks to the MAC */
386 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
387 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
388 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
389 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 390
d23f028a
SG		 391 hwcfg |= HW_CFG_SMI_SEL_;
392 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
393}
fd9abb3d 394
d23f028a
SG		 395/* Autodetects and enables external phy if present on supported chips.
396 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
397 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
398static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
399{
400 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 401
d23f028a
SG		 402 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
403 SMSC_TRACE(HW, "Forcing internal PHY");
404 pdata->using_extphy = 0;
405 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
406 SMSC_TRACE(HW, "Forcing external PHY");
407 smsc911x_phy_enable_external(pdata);
408 pdata->using_extphy = 1;
409 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
410 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
411 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 412 pdata->using_extphy = 1;
413 } else {
d23f028a
SG		 414 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
415 pdata->using_extphy = 0;
fd9abb3d 416 }
fd9abb3d
SG		 417}
418
419/* Fetches a tx status out of the status fifo */
420static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
421{
422 unsigned int result =
423 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
424
425 if (result != 0)
426 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
427
428 return result;
429}
430
431/* Fetches the next rx status */
432static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
433{
434 unsigned int result =
435 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
436
437 if (result != 0)
438 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
439
440 return result;
441}
442
443#ifdef USE_PHY_WORK_AROUND
444static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
445{
446 unsigned int tries;
447 u32 wrsz;
448 u32 rdsz;
449 ulong bufp;
450
451 for (tries = 0; tries < 10; tries++) {
452 unsigned int txcmd_a;
453 unsigned int txcmd_b;
454 unsigned int status;
455 unsigned int pktlength;
456 unsigned int i;
457
458 /* Zero-out rx packet memory */
459 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
460
461 /* Write tx packet to 118 */
462 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
463 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
464 txcmd_a |= MIN_PACKET_SIZE;
465
466 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
467
468 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
469 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
470
471 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
472 wrsz = MIN_PACKET_SIZE + 3;
473 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
474 wrsz >>= 2;
475
476 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
477
478 /* Wait till transmit is done */
479 i = 60;
480 do {
481 udelay(5);
482 status = smsc911x_tx_get_txstatus(pdata);
483 } while ((i--) && (!status));
484
485 if (!status) {
486 SMSC_WARNING(HW, "Failed to transmit "
487 "during loopback test");
488 continue;
489 }
490 if (status & TX_STS_ES_) {
491 SMSC_WARNING(HW, "Transmit encountered "
492 "errors during loopback test");
493 continue;
494 }
495
496 /* Wait till receive is done */
497 i = 60;
498 do {
499 udelay(5);
500 status = smsc911x_rx_get_rxstatus(pdata);
501 } while ((i--) && (!status));
502
503 if (!status) {
504 SMSC_WARNING(HW,
505 "Failed to receive during loopback test");
506 continue;
507 }
508 if (status & RX_STS_ES_) {
509 SMSC_WARNING(HW, "Receive encountered "
510 "errors during loopback test");
511 continue;
512 }
513
514 pktlength = ((status & 0x3FFF0000UL) >> 16);
515 bufp = (ulong)pdata->loopback_rx_pkt;
516 rdsz = pktlength + 3;
517 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
518 rdsz >>= 2;
519
520 smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
521
522 if (pktlength != (MIN_PACKET_SIZE + 4)) {
523 SMSC_WARNING(HW, "Unexpected packet size "
524 "during loop back test, size=%d, will retry",
525 pktlength);
526 } else {
527 unsigned int j;
528 int mismatch = 0;
529 for (j = 0; j < MIN_PACKET_SIZE; j++) {
530 if (pdata->loopback_tx_pkt[j]
531 != pdata->loopback_rx_pkt[j]) {
532 mismatch = 1;
533 break;
534 }
535 }
536 if (!mismatch) {
537 SMSC_TRACE(HW, "Successfully verified "
538 "loopback packet");
539 return 0;
540 } else {
541 SMSC_WARNING(HW, "Data mismatch "
542 "during loop back test, will retry");
543 }
544 }
545 }
546
547 return -EIO;
548}
549
550static int smsc911x_phy_reset(struct smsc911x_data *pdata)
551{
552 struct phy_device *phy_dev = pdata->phy_dev;
553 unsigned int temp;
554 unsigned int i = 100000;
555
556 BUG_ON(!phy_dev);
557 BUG_ON(!phy_dev->bus);
558
559 SMSC_TRACE(HW, "Performing PHY BCR Reset");
560 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
561 do {
562 msleep(1);
563 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
564 MII_BMCR);
565 } while ((i--) && (temp & BMCR_RESET));
566
567 if (temp & BMCR_RESET) {
568 SMSC_WARNING(HW, "PHY reset failed to complete.");
569 return -EIO;
570 }
571 /* Extra delay required because the phy may not be completed with
572 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
573 * enough delay but using 1ms here to be safe */
574 msleep(1);
575
576 return 0;
577}
578
579static int smsc911x_phy_loopbacktest(struct net_device *dev)
580{
581 struct smsc911x_data *pdata = netdev_priv(dev);
582 struct phy_device *phy_dev = pdata->phy_dev;
583 int result = -EIO;
584 unsigned int i, val;
585 unsigned long flags;
586
587 /* Initialise tx packet using broadcast destination address */
588 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
589
590 /* Use incrementing source address */
591 for (i = 6; i < 12; i++)
592 pdata->loopback_tx_pkt[i] = (char)i;
593
594 /* Set length type field */
595 pdata->loopback_tx_pkt[12] = 0x00;
596 pdata->loopback_tx_pkt[13] = 0x00;
597
598 for (i = 14; i < MIN_PACKET_SIZE; i++)
599 pdata->loopback_tx_pkt[i] = (char)i;
600
601 val = smsc911x_reg_read(pdata, HW_CFG);
602 val &= HW_CFG_TX_FIF_SZ_;
603 val |= HW_CFG_SF_;
604 smsc911x_reg_write(pdata, HW_CFG, val);
605
606 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
607 smsc911x_reg_write(pdata, RX_CFG,
608 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
609
610 for (i = 0; i < 10; i++) {
611 /* Set PHY to 10/FD, no ANEG, and loopback mode */
612 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
613 BMCR_LOOPBACK | BMCR_FULLDPLX);
614
615 /* Enable MAC tx/rx, FD */
616 spin_lock_irqsave(&pdata->mac_lock, flags);
617 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
618 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
619 spin_unlock_irqrestore(&pdata->mac_lock, flags);
620
621 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
622 result = 0;
623 break;
624 }
625 pdata->resetcount++;
626
627 /* Disable MAC rx */
628 spin_lock_irqsave(&pdata->mac_lock, flags);
629 smsc911x_mac_write(pdata, MAC_CR, 0);
630 spin_unlock_irqrestore(&pdata->mac_lock, flags);
631
632 smsc911x_phy_reset(pdata);
633 }
634
635 /* Disable MAC */
636 spin_lock_irqsave(&pdata->mac_lock, flags);
637 smsc911x_mac_write(pdata, MAC_CR, 0);
638 spin_unlock_irqrestore(&pdata->mac_lock, flags);
639
640 /* Cancel PHY loopback mode */
641 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
642
643 smsc911x_reg_write(pdata, TX_CFG, 0);
644 smsc911x_reg_write(pdata, RX_CFG, 0);
645
646 return result;
647}
648#endif /* USE_PHY_WORK_AROUND */
649
fd9abb3d
SG		 650static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
651{
652 struct phy_device *phy_dev = pdata->phy_dev;
653 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
654 u32 flow;
655 unsigned long flags;
656
657 if (phy_dev->duplex == DUPLEX_FULL) {
658 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
659 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 660 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 661
662 if (cap & FLOW_CTRL_RX)
663 flow = 0xFFFF0002;
664 else
665 flow = 0;
666
667 if (cap & FLOW_CTRL_TX)
668 afc |= 0xF;
669 else
670 afc &= ~0xF;
671
672 SMSC_TRACE(HW, "rx pause %s, tx pause %s",
673 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
674 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
675 } else {
676 SMSC_TRACE(HW, "half duplex");
677 flow = 0;
678 afc |= 0xF;
679 }
680
681 spin_lock_irqsave(&pdata->mac_lock, flags);
682 smsc911x_mac_write(pdata, FLOW, flow);
683 spin_unlock_irqrestore(&pdata->mac_lock, flags);
684
685 smsc911x_reg_write(pdata, AFC_CFG, afc);
686}
687
688/* Update link mode if anything has changed. Called periodically when the
689 * PHY is in polling mode, even if nothing has changed. */
690static void smsc911x_phy_adjust_link(struct net_device *dev)
691{
692 struct smsc911x_data *pdata = netdev_priv(dev);
693 struct phy_device *phy_dev = pdata->phy_dev;
694 unsigned long flags;
695 int carrier;
696
697 if (phy_dev->duplex != pdata->last_duplex) {
698 unsigned int mac_cr;
699 SMSC_TRACE(HW, "duplex state has changed");
700
701 spin_lock_irqsave(&pdata->mac_lock, flags);
702 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
703 if (phy_dev->duplex) {
704 SMSC_TRACE(HW,
705 "configuring for full duplex mode");
706 mac_cr |= MAC_CR_FDPX_;
707 } else {
708 SMSC_TRACE(HW,
709 "configuring for half duplex mode");
710 mac_cr &= ~MAC_CR_FDPX_;
711 }
712 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
713 spin_unlock_irqrestore(&pdata->mac_lock, flags);
714
715 smsc911x_phy_update_flowcontrol(pdata);
716 pdata->last_duplex = phy_dev->duplex;
717 }
718
719 carrier = netif_carrier_ok(dev);
720 if (carrier != pdata->last_carrier) {
721 SMSC_TRACE(HW, "carrier state has changed");
722 if (carrier) {
723 SMSC_TRACE(HW, "configuring for carrier OK");
724 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
725 (!pdata->using_extphy)) {
726 /* Restore orginal GPIO configuration */
727 pdata->gpio_setting = pdata->gpio_orig_setting;
728 smsc911x_reg_write(pdata, GPIO_CFG,
729 pdata->gpio_setting);
730 }
731 } else {
732 SMSC_TRACE(HW, "configuring for no carrier");
733 /* Check global setting that LED1
734 * usage is 10/100 indicator */
735 pdata->gpio_setting = smsc911x_reg_read(pdata,
736 GPIO_CFG);
737 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_)
738 && (!pdata->using_extphy)) {
739 /* Force 10/100 LED off, after saving
740 * orginal GPIO configuration */
741 pdata->gpio_orig_setting = pdata->gpio_setting;
742
743 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
744 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
745 | GPIO_CFG_GPIODIR0_
746 | GPIO_CFG_GPIOD0_);
747 smsc911x_reg_write(pdata, GPIO_CFG,
748 pdata->gpio_setting);
749 }
750 }
751 pdata->last_carrier = carrier;
752 }
753}
754
755static int smsc911x_mii_probe(struct net_device *dev)
756{
757 struct smsc911x_data *pdata = netdev_priv(dev);
758 struct phy_device *phydev = NULL;
759 int phy_addr;
760
761 /* find the first phy */
762 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
763 if (pdata->mii_bus->phy_map[phy_addr]) {
764 phydev = pdata->mii_bus->phy_map[phy_addr];
765 SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
766 phy_addr, phydev->addr, phydev->phy_id);
767 break;
768 }
769 }
770
771 if (!phydev) {
772 pr_err("%s: no PHY found\n", dev->name);
773 return -ENODEV;
774 }
775
db1d7bf7 776 phydev = phy_connect(dev, dev_name(&phydev->dev),
2107fb8b 777 &smsc911x_phy_adjust_link, 0, pdata->config.phy_interface);
fd9abb3d
SG		 778
779 if (IS_ERR(phydev)) {
780 pr_err("%s: Could not attach to PHY\n", dev->name);
781 return PTR_ERR(phydev);
782 }
783
784 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7
KS		 785 dev->name, phydev->drv->name,
786 dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 787
788 /* mask with MAC supported features */
789 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
790 SUPPORTED_Asym_Pause);
791 phydev->advertising = phydev->supported;
792
793 pdata->phy_dev = phydev;
794 pdata->last_duplex = -1;
795 pdata->last_carrier = -1;
796
797#ifdef USE_PHY_WORK_AROUND
798 if (smsc911x_phy_loopbacktest(dev) < 0) {
799 SMSC_WARNING(HW, "Failed Loop Back Test");
800 return -ENODEV;
801 }
802 SMSC_TRACE(HW, "Passed Loop Back Test");
803#endif /* USE_PHY_WORK_AROUND */
804
805 SMSC_TRACE(HW, "phy initialised succesfully");
806 return 0;
807}
808
809static int __devinit smsc911x_mii_init(struct platform_device *pdev,
810 struct net_device *dev)
811{
812 struct smsc911x_data *pdata = netdev_priv(dev);
813 int err = -ENXIO, i;
814
815 pdata->mii_bus = mdiobus_alloc();
816 if (!pdata->mii_bus) {
817 err = -ENOMEM;
818 goto err_out_1;
819 }
820
821 pdata->mii_bus->name = SMSC_MDIONAME;
822 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
823 pdata->mii_bus->priv = pdata;
824 pdata->mii_bus->read = smsc911x_mii_read;
825 pdata->mii_bus->write = smsc911x_mii_write;
826 pdata->mii_bus->irq = pdata->phy_irq;
827 for (i = 0; i < PHY_MAX_ADDR; ++i)
828 pdata->mii_bus->irq[i] = PHY_POLL;
829
830 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 831
fd9abb3d
SG		 832 switch (pdata->idrev & 0xFFFF0000) {
833 case 0x01170000:
834 case 0x01150000:
835 case 0x117A0000:
836 case 0x115A0000:
837 /* External PHY supported, try to autodetect */
d23f028a 838 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 839 break;
840 default:
841 SMSC_TRACE(HW, "External PHY is not supported, "
842 "using internal PHY");
d23f028a 843 pdata->using_extphy = 0;
fd9abb3d
SG		 844 break;
845 }
846
847 if (!pdata->using_extphy) {
848 /* Mask all PHYs except ID 1 (internal) */
849 pdata->mii_bus->phy_mask = ~(1 << 1);
850 }
851
852 if (mdiobus_register(pdata->mii_bus)) {
853 SMSC_WARNING(PROBE, "Error registering mii bus");
854 goto err_out_free_bus_2;
855 }
856
857 if (smsc911x_mii_probe(dev) < 0) {
858 SMSC_WARNING(PROBE, "Error registering mii bus");
859 goto err_out_unregister_bus_3;
860 }
861
862 return 0;
863
864err_out_unregister_bus_3:
865 mdiobus_unregister(pdata->mii_bus);
866err_out_free_bus_2:
867 mdiobus_free(pdata->mii_bus);
868err_out_1:
869 return err;
870}
871
872/* Gets the number of tx statuses in the fifo */
873static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
874{
875 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
876 & TX_FIFO_INF_TSUSED_) >> 16;
877}
878
879/* Reads tx statuses and increments counters where necessary */
880static void smsc911x_tx_update_txcounters(struct net_device *dev)
881{
882 struct smsc911x_data *pdata = netdev_priv(dev);
883 unsigned int tx_stat;
884
885 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
886 if (unlikely(tx_stat & 0x80000000)) {
887 /* In this driver the packet tag is used as the packet
888 * length. Since a packet length can never reach the
889 * size of 0x8000, this bit is reserved. It is worth
890 * noting that the "reserved bit" in the warning above
891 * does not reference a hardware defined reserved bit
892 * but rather a driver defined one.
893 */
894 SMSC_WARNING(HW,
895 "Packet tag reserved bit is high");
896 } else {
785b6f97 897 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 898 dev->stats.tx_errors++;
899 } else {
900 dev->stats.tx_packets++;
901 dev->stats.tx_bytes += (tx_stat >> 16);
902 }
785b6f97 903 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 904 dev->stats.collisions += 16;
905 dev->stats.tx_aborted_errors += 1;
906 } else {
907 dev->stats.collisions +=
908 ((tx_stat >> 3) & 0xF);
909 }
785b6f97 910 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 911 dev->stats.tx_carrier_errors += 1;
785b6f97 912 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 913 dev->stats.collisions++;
914 dev->stats.tx_aborted_errors++;
915 }
916 }
917 }
918}
919
920/* Increments the Rx error counters */
921static void
922smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
923{
924 int crc_err = 0;
925
785b6f97 926 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 927 dev->stats.rx_errors++;
785b6f97 928 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 929 dev->stats.rx_crc_errors++;
930 crc_err = 1;
931 }
932 }
933 if (likely(!crc_err)) {
785b6f97
SG		 934 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
935 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 936 dev->stats.rx_length_errors++;
fd9abb3d
SG		 937 if (rxstat & RX_STS_MCAST_)
938 dev->stats.multicast++;
939 }
940}
941
942/* Quickly dumps bad packets */
943static void
944smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
945{
946 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
947
948 if (likely(pktwords >= 4)) {
949 unsigned int timeout = 500;
950 unsigned int val;
951 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
952 do {
953 udelay(1);
954 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 955 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 956
957 if (unlikely(timeout == 0))
958 SMSC_WARNING(HW, "Timed out waiting for "
959 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
960 } else {
961 unsigned int temp;
962 while (pktwords--)
963 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
964 }
965}
966
967/* NAPI poll function */
968static int smsc911x_poll(struct napi_struct *napi, int budget)
969{
970 struct smsc911x_data *pdata =
971 container_of(napi, struct smsc911x_data, napi);
972 struct net_device *dev = pdata->dev;
973 int npackets = 0;
974
975 while (likely(netif_running(dev)) && (npackets < budget)) {
976 unsigned int pktlength;
977 unsigned int pktwords;
978 struct sk_buff *skb;
979 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
980
981 if (!rxstat) {
982 unsigned int temp;
983 /* We processed all packets available. Tell NAPI it can
984 * stop polling then re-enable rx interrupts */
985 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 986 napi_complete(napi);
fd9abb3d
SG		 987 temp = smsc911x_reg_read(pdata, INT_EN);
988 temp |= INT_EN_RSFL_EN_;
989 smsc911x_reg_write(pdata, INT_EN, temp);
990 break;
991 }
992
993 /* Count packet for NAPI scheduling, even if it has an error.
994 * Error packets still require cycles to discard */
995 npackets++;
996
997 pktlength = ((rxstat & 0x3FFF0000) >> 16);
998 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
999 smsc911x_rx_counterrors(dev, rxstat);
1000
1001 if (unlikely(rxstat & RX_STS_ES_)) {
1002 SMSC_WARNING(RX_ERR,
1003 "Discarding packet with error bit set");
1004 /* Packet has an error, discard it and continue with
1005 * the next */
1006 smsc911x_rx_fastforward(pdata, pktwords);
1007 dev->stats.rx_dropped++;
1008 continue;
1009 }
1010
1011 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1012 if (unlikely(!skb)) {
1013 SMSC_WARNING(RX_ERR,
1014 "Unable to allocate skb for rx packet");
1015 /* Drop the packet and stop this polling iteration */
1016 smsc911x_rx_fastforward(pdata, pktwords);
1017 dev->stats.rx_dropped++;
1018 break;
1019 }
1020
1021 skb->data = skb->head;
1022 skb_reset_tail_pointer(skb);
1023
1024 /* Align IP on 16B boundary */
1025 skb_reserve(skb, NET_IP_ALIGN);
1026 skb_put(skb, pktlength - 4);
1027 smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
1028 pktwords);
1029 skb->protocol = eth_type_trans(skb, dev);
1030 skb->ip_summed = CHECKSUM_NONE;
1031 netif_receive_skb(skb);
1032
1033 /* Update counters */
1034 dev->stats.rx_packets++;
1035 dev->stats.rx_bytes += (pktlength - 4);
1036 dev->last_rx = jiffies;
1037 }
1038
1039 /* Return total received packets */
1040 return npackets;
1041}
1042
1043/* Returns hash bit number for given MAC address
1044 * Example:
1045 * 01 00 5E 00 00 01 -> returns bit number 31 */
1046static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1047{
1048 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1049}
1050
1051static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1052{
1053 /* Performs the multicast & mac_cr update. This is called when
1054 * safe on the current hardware, and with the mac_lock held */
1055 unsigned int mac_cr;
1056
1057 SMSC_ASSERT_MAC_LOCK(pdata);
1058
1059 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1060 mac_cr |= pdata->set_bits_mask;
1061 mac_cr &= ~(pdata->clear_bits_mask);
1062 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1063 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1064 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
1065 SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1066 mac_cr, pdata->hashhi, pdata->hashlo);
1067}
1068
1069static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1070{
1071 unsigned int mac_cr;
1072
1073 /* This function is only called for older LAN911x devices
1074 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1075 * be modified during Rx - newer devices immediately update the
1076 * registers.
1077 *
1078 * This is called from interrupt context */
1079
1080 spin_lock(&pdata->mac_lock);
1081
1082 /* Check Rx has stopped */
1083 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
1084 SMSC_WARNING(DRV, "Rx not stopped");
1085
1086 /* Perform the update - safe to do now Rx has stopped */
1087 smsc911x_rx_multicast_update(pdata);
1088
1089 /* Re-enable Rx */
1090 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1091 mac_cr |= MAC_CR_RXEN_;
1092 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1093
1094 pdata->multicast_update_pending = 0;
1095
1096 spin_unlock(&pdata->mac_lock);
1097}
1098
1099static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1100{
1101 unsigned int timeout;
1102 unsigned int temp;
1103
1104 /* Reset the LAN911x */
1105 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1106 timeout = 10;
1107 do {
1108 udelay(10);
1109 temp = smsc911x_reg_read(pdata, HW_CFG);
1110 } while ((--timeout) && (temp & HW_CFG_SRST_));
1111
1112 if (unlikely(temp & HW_CFG_SRST_)) {
1113 SMSC_WARNING(DRV, "Failed to complete reset");
1114 return -EIO;
1115 }
1116 return 0;
1117}
1118
1119/* Sets the device MAC address to dev_addr, called with mac_lock held */
1120static void
225ddf49 1121smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1122{
1123 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1124 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1125 (dev_addr[1] << 8) | dev_addr[0];
1126
1127 SMSC_ASSERT_MAC_LOCK(pdata);
1128
1129 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1130 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1131}
1132
1133static int smsc911x_open(struct net_device *dev)
1134{
1135 struct smsc911x_data *pdata = netdev_priv(dev);
1136 unsigned int timeout;
1137 unsigned int temp;
1138 unsigned int intcfg;
1139
1140 /* if the phy is not yet registered, retry later*/
1141 if (!pdata->phy_dev) {
1142 SMSC_WARNING(HW, "phy_dev is NULL");
1143 return -EAGAIN;
1144 }
1145
1146 if (!is_valid_ether_addr(dev->dev_addr)) {
1147 SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
1148 return -EADDRNOTAVAIL;
1149 }
1150
1151 /* Reset the LAN911x */
1152 if (smsc911x_soft_reset(pdata)) {
1153 SMSC_WARNING(HW, "soft reset failed");
1154 return -EIO;
1155 }
1156
1157 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1158 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1159
1160 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1161 timeout = 50;
f7efb6cc
SG		 1162 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1163 --timeout) {
fd9abb3d
SG		 1164 udelay(10);
1165 }
1166
1167 if (unlikely(timeout == 0))
1168 SMSC_WARNING(IFUP,
1169 "Timed out waiting for EEPROM busy bit to clear");
1170
1171 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1172
1173 /* The soft reset above cleared the device's MAC address,
1174 * restore it from local copy (set in probe) */
1175 spin_lock_irq(&pdata->mac_lock);
225ddf49 1176 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1177 spin_unlock_irq(&pdata->mac_lock);
1178
1179 /* Initialise irqs, but leave all sources disabled */
1180 smsc911x_reg_write(pdata, INT_EN, 0);
1181 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1182
1183 /* Set interrupt deassertion to 100uS */
1184 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1185
2107fb8b 1186 if (pdata->config.irq_polarity) {
fd9abb3d
SG		 1187 SMSC_TRACE(IFUP, "irq polarity: active high");
1188 intcfg |= INT_CFG_IRQ_POL_;
1189 } else {
1190 SMSC_TRACE(IFUP, "irq polarity: active low");
1191 }
1192
2107fb8b 1193 if (pdata->config.irq_type) {
fd9abb3d
SG		 1194 SMSC_TRACE(IFUP, "irq type: push-pull");
1195 intcfg |= INT_CFG_IRQ_TYPE_;
1196 } else {
1197 SMSC_TRACE(IFUP, "irq type: open drain");
1198 }
1199
1200 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1201
1202 SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
1203 pdata->software_irq_signal = 0;
1204 smp_wmb();
1205
1206 temp = smsc911x_reg_read(pdata, INT_EN);
1207 temp |= INT_EN_SW_INT_EN_;
1208 smsc911x_reg_write(pdata, INT_EN, temp);
1209
1210 timeout = 1000;
1211 while (timeout--) {
1212 if (pdata->software_irq_signal)
1213 break;
1214 msleep(1);
1215 }
1216
1217 if (!pdata->software_irq_signal) {
1218 dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
1219 dev->irq);
1220 return -ENODEV;
1221 }
1222 SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
1223
1224 dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1225 (unsigned long)pdata->ioaddr, dev->irq);
1226
44c1d6f9
SG		 1227 /* Reset the last known duplex and carrier */
1228 pdata->last_duplex = -1;
1229 pdata->last_carrier = -1;
1230
fd9abb3d
SG		 1231 /* Bring the PHY up */
1232 phy_start(pdata->phy_dev);
1233
1234 temp = smsc911x_reg_read(pdata, HW_CFG);
1235 /* Preserve TX FIFO size and external PHY configuration */
1236 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1237 temp |= HW_CFG_SF_;
1238 smsc911x_reg_write(pdata, HW_CFG, temp);
1239
1240 temp = smsc911x_reg_read(pdata, FIFO_INT);
1241 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1242 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1243 smsc911x_reg_write(pdata, FIFO_INT, temp);
1244
1245 /* set RX Data offset to 2 bytes for alignment */
1246 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1247
1248 /* enable NAPI polling before enabling RX interrupts */
1249 napi_enable(&pdata->napi);
1250
1251 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1252 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1253 smsc911x_reg_write(pdata, INT_EN, temp);
1254
1255 spin_lock_irq(&pdata->mac_lock);
1256 temp = smsc911x_mac_read(pdata, MAC_CR);
1257 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1258 smsc911x_mac_write(pdata, MAC_CR, temp);
1259 spin_unlock_irq(&pdata->mac_lock);
1260
1261 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1262
1263 netif_start_queue(dev);
1264 return 0;
1265}
1266
1267/* Entry point for stopping the interface */
1268static int smsc911x_stop(struct net_device *dev)
1269{
1270 struct smsc911x_data *pdata = netdev_priv(dev);
1271 unsigned int temp;
1272
fd9abb3d
SG		 1273 /* Disable all device interrupts */
1274 temp = smsc911x_reg_read(pdata, INT_CFG);
1275 temp &= ~INT_CFG_IRQ_EN_;
1276 smsc911x_reg_write(pdata, INT_CFG, temp);
1277
1278 /* Stop Tx and Rx polling */
1279 netif_stop_queue(dev);
1280 napi_disable(&pdata->napi);
1281
1282 /* At this point all Rx and Tx activity is stopped */
1283 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1284 smsc911x_tx_update_txcounters(dev);
1285
1286 /* Bring the PHY down */
dd045193
SG		 1287 if (pdata->phy_dev)
1288 phy_stop(pdata->phy_dev);
fd9abb3d
SG		 1289
1290 SMSC_TRACE(IFDOWN, "Interface stopped");
1291 return 0;
1292}
1293
1294/* Entry point for transmitting a packet */
1295static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1296{
1297 struct smsc911x_data *pdata = netdev_priv(dev);
1298 unsigned int freespace;
1299 unsigned int tx_cmd_a;
1300 unsigned int tx_cmd_b;
1301 unsigned int temp;
1302 u32 wrsz;
1303 ulong bufp;
1304
1305 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1306
1307 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
1308 SMSC_WARNING(TX_ERR,
1309 "Tx data fifo low, space available: %d", freespace);
1310
1311 /* Word alignment adjustment */
1312 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1313 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1314 tx_cmd_a |= (unsigned int)skb->len;
1315
1316 tx_cmd_b = ((unsigned int)skb->len) << 16;
1317 tx_cmd_b |= (unsigned int)skb->len;
1318
1319 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1320 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1321
1322 bufp = (ulong)skb->data & (~0x3);
1323 wrsz = (u32)skb->len + 3;
1324 wrsz += (u32)((ulong)skb->data & 0x3);
1325 wrsz >>= 2;
1326
1327 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
1328 freespace -= (skb->len + 32);
1329 dev_kfree_skb(skb);
1330 dev->trans_start = jiffies;
1331
1332 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1333 smsc911x_tx_update_txcounters(dev);
1334
1335 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1336 netif_stop_queue(dev);
1337 temp = smsc911x_reg_read(pdata, FIFO_INT);
1338 temp &= 0x00FFFFFF;
1339 temp |= 0x32000000;
1340 smsc911x_reg_write(pdata, FIFO_INT, temp);
1341 }
1342
1343 return NETDEV_TX_OK;
1344}
1345
1346/* Entry point for getting status counters */
1347static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1348{
1349 struct smsc911x_data *pdata = netdev_priv(dev);
1350 smsc911x_tx_update_txcounters(dev);
1351 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1352 return &dev->stats;
1353}
1354
1355/* Entry point for setting addressing modes */
1356static void smsc911x_set_multicast_list(struct net_device *dev)
1357{
1358 struct smsc911x_data *pdata = netdev_priv(dev);
1359 unsigned long flags;
1360
1361 if (dev->flags & IFF_PROMISC) {
1362 /* Enabling promiscuous mode */
1363 pdata->set_bits_mask = MAC_CR_PRMS_;
1364 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1365 pdata->hashhi = 0;
1366 pdata->hashlo = 0;
1367 } else if (dev->flags & IFF_ALLMULTI) {
1368 /* Enabling all multicast mode */
1369 pdata->set_bits_mask = MAC_CR_MCPAS_;
1370 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1371 pdata->hashhi = 0;
1372 pdata->hashlo = 0;
1373 } else if (dev->mc_count > 0) {
1374 /* Enabling specific multicast addresses */
1375 unsigned int hash_high = 0;
1376 unsigned int hash_low = 0;
1377 unsigned int count = 0;
1378 struct dev_mc_list *mc_list = dev->mc_list;
1379
1380 pdata->set_bits_mask = MAC_CR_HPFILT_;
1381 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1382
1383 while (mc_list) {
1384 count++;
1385 if ((mc_list->dmi_addrlen) == ETH_ALEN) {
1386 unsigned int bitnum =
1387 smsc911x_hash(mc_list->dmi_addr);
1388 unsigned int mask = 0x01 << (bitnum & 0x1F);
1389 if (bitnum & 0x20)
1390 hash_high |= mask;
1391 else
1392 hash_low |= mask;
1393 } else {
1394 SMSC_WARNING(DRV, "dmi_addrlen != 6");
1395 }
1396 mc_list = mc_list->next;
1397 }
1398 if (count != (unsigned int)dev->mc_count)
1399 SMSC_WARNING(DRV, "mc_count != dev->mc_count");
1400
1401 pdata->hashhi = hash_high;
1402 pdata->hashlo = hash_low;
1403 } else {
1404 /* Enabling local MAC address only */
1405 pdata->set_bits_mask = 0;
1406 pdata->clear_bits_mask =
1407 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1408 pdata->hashhi = 0;
1409 pdata->hashlo = 0;
1410 }
1411
1412 spin_lock_irqsave(&pdata->mac_lock, flags);
1413
1414 if (pdata->generation <= 1) {
1415 /* Older hardware revision - cannot change these flags while
1416 * receiving data */
1417 if (!pdata->multicast_update_pending) {
1418 unsigned int temp;
1419 SMSC_TRACE(HW, "scheduling mcast update");
1420 pdata->multicast_update_pending = 1;
1421
1422 /* Request the hardware to stop, then perform the
1423 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1424 temp = smsc911x_mac_read(pdata, MAC_CR);
1425 temp &= ~(MAC_CR_RXEN_);
1426 smsc911x_mac_write(pdata, MAC_CR, temp);
1427 } else {
1428 /* There is another update pending, this should now
1429 * use the newer values */
1430 }
1431 } else {
1432 /* Newer hardware revision - can write immediately */
1433 smsc911x_rx_multicast_update(pdata);
1434 }
1435
1436 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1437}
1438
1439static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1440{
1441 struct net_device *dev = dev_id;
1442 struct smsc911x_data *pdata = netdev_priv(dev);
1443 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1444 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1445 int serviced = IRQ_NONE;
1446 u32 temp;
1447
1448 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1449 temp = smsc911x_reg_read(pdata, INT_EN);
1450 temp &= (~INT_EN_SW_INT_EN_);
1451 smsc911x_reg_write(pdata, INT_EN, temp);
1452 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1453 pdata->software_irq_signal = 1;
1454 smp_wmb();
1455 serviced = IRQ_HANDLED;
1456 }
1457
1458 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1459 /* Called when there is a multicast update scheduled and
1460 * it is now safe to complete the update */
1461 SMSC_TRACE(INTR, "RX Stop interrupt");
fd9abb3d 1462 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1463 if (pdata->multicast_update_pending)
1464 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1465 serviced = IRQ_HANDLED;
1466 }
1467
1468 if (intsts & inten & INT_STS_TDFA_) {
1469 temp = smsc911x_reg_read(pdata, FIFO_INT);
1470 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1471 smsc911x_reg_write(pdata, FIFO_INT, temp);
1472 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1473 netif_wake_queue(dev);
1474 serviced = IRQ_HANDLED;
1475 }
1476
1477 if (unlikely(intsts & inten & INT_STS_RXE_)) {
1478 SMSC_TRACE(INTR, "RX Error interrupt");
1479 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1480 serviced = IRQ_HANDLED;
1481 }
1482
1483 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1484 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1485 /* Disable Rx interrupts */
1486 temp = smsc911x_reg_read(pdata, INT_EN);
1487 temp &= (~INT_EN_RSFL_EN_);
1488 smsc911x_reg_write(pdata, INT_EN, temp);
1489 /* Schedule a NAPI poll */
288379f0 1490 __napi_schedule(&pdata->napi);
fd9abb3d
SG		 1491 } else {
1492 SMSC_WARNING(RX_ERR,
288379f0 1493 "napi_schedule_prep failed");
fd9abb3d
SG		 1494 }
1495 serviced = IRQ_HANDLED;
1496 }
1497
1498 return serviced;
1499}
1500
1501#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1502static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1503{
1504 disable_irq(dev->irq);
1505 smsc911x_irqhandler(0, dev);
1506 enable_irq(dev->irq);
1507}
1508#endif /* CONFIG_NET_POLL_CONTROLLER */
1509
225ddf49
SG		 1510static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1511{
1512 struct smsc911x_data *pdata = netdev_priv(dev);
1513 struct sockaddr *addr = p;
1514
1515 /* On older hardware revisions we cannot change the mac address
1516 * registers while receiving data. Newer devices can safely change
1517 * this at any time. */
1518 if (pdata->generation <= 1 && netif_running(dev))
1519 return -EBUSY;
1520
1521 if (!is_valid_ether_addr(addr->sa_data))
1522 return -EADDRNOTAVAIL;
1523
1524 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1525
1526 spin_lock_irq(&pdata->mac_lock);
1527 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1528 spin_unlock_irq(&pdata->mac_lock);
1529
1530 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1531
1532 return 0;
1533}
1534
fd9abb3d
SG		 1535/* Standard ioctls for mii-tool */
1536static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1537{
1538 struct smsc911x_data *pdata = netdev_priv(dev);
1539
1540 if (!netif_running(dev) || !pdata->phy_dev)
1541 return -EINVAL;
1542
1543 return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
1544}
1545
1546static int
1547smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1548{
1549 struct smsc911x_data *pdata = netdev_priv(dev);
1550
1551 cmd->maxtxpkt = 1;
1552 cmd->maxrxpkt = 1;
1553 return phy_ethtool_gset(pdata->phy_dev, cmd);
1554}
1555
1556static int
1557smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1558{
1559 struct smsc911x_data *pdata = netdev_priv(dev);
1560
1561 return phy_ethtool_sset(pdata->phy_dev, cmd);
1562}
1563
1564static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1565 struct ethtool_drvinfo *info)
1566{
1567 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1568 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1569 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1570 sizeof(info->bus_info));
1571}
1572
1573static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1574{
1575 struct smsc911x_data *pdata = netdev_priv(dev);
1576
1577 return phy_start_aneg(pdata->phy_dev);
1578}
1579
1580static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1581{
1582 struct smsc911x_data *pdata = netdev_priv(dev);
1583 return pdata->msg_enable;
1584}
1585
1586static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1587{
1588 struct smsc911x_data *pdata = netdev_priv(dev);
1589 pdata->msg_enable = level;
1590}
1591
1592static int smsc911x_ethtool_getregslen(struct net_device *dev)
1593{
1594 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1595 sizeof(u32);
1596}
1597
1598static void
1599smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1600 void *buf)
1601{
1602 struct smsc911x_data *pdata = netdev_priv(dev);
1603 struct phy_device *phy_dev = pdata->phy_dev;
1604 unsigned long flags;
1605 unsigned int i;
1606 unsigned int j = 0;
1607 u32 *data = buf;
1608
1609 regs->version = pdata->idrev;
1610 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1611 data[j++] = smsc911x_reg_read(pdata, i);
1612
1613 for (i = MAC_CR; i <= WUCSR; i++) {
1614 spin_lock_irqsave(&pdata->mac_lock, flags);
1615 data[j++] = smsc911x_mac_read(pdata, i);
1616 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1617 }
1618
1619 for (i = 0; i <= 31; i++)
1620 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1621}
1622
1623static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1624{
1625 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1626 temp &= ~GPIO_CFG_EEPR_EN_;
1627 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1628 msleep(1);
1629}
1630
1631static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1632{
1633 int timeout = 100;
1634 u32 e2cmd;
1635
1636 SMSC_TRACE(DRV, "op 0x%08x", op);
1637 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
1638 SMSC_WARNING(DRV, "Busy at start");
1639 return -EBUSY;
1640 }
1641
1642 e2cmd = op | E2P_CMD_EPC_BUSY_;
1643 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1644
1645 do {
1646 msleep(1);
1647 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1648 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1649
1650 if (!timeout) {
1651 SMSC_TRACE(DRV, "TIMED OUT");
1652 return -EAGAIN;
1653 }
1654
1655 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1656 SMSC_TRACE(DRV, "Error occured during eeprom operation");
1657 return -EINVAL;
1658 }
1659
1660 return 0;
1661}
1662
1663static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1664 u8 address, u8 *data)
1665{
1666 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1667 int ret;
1668
1669 SMSC_TRACE(DRV, "address 0x%x", address);
1670 ret = smsc911x_eeprom_send_cmd(pdata, op);
1671
1672 if (!ret)
1673 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1674
1675 return ret;
1676}
1677
1678static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1679 u8 address, u8 data)
1680{
1681 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 1682 u32 temp;
fd9abb3d
SG		 1683 int ret;
1684
1685 SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
1686 ret = smsc911x_eeprom_send_cmd(pdata, op);
1687
1688 if (!ret) {
1689 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1690 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 1691
1692 /* Workaround for hardware read-after-write restriction */
1693 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1694
fd9abb3d
SG		 1695 ret = smsc911x_eeprom_send_cmd(pdata, op);
1696 }
1697
1698 return ret;
1699}
1700
1701static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1702{
1703 return SMSC911X_EEPROM_SIZE;
1704}
1705
1706static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1707 struct ethtool_eeprom *eeprom, u8 *data)
1708{
1709 struct smsc911x_data *pdata = netdev_priv(dev);
1710 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1711 int len;
1712 int i;
1713
1714 smsc911x_eeprom_enable_access(pdata);
1715
1716 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1717 for (i = 0; i < len; i++) {
1718 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1719 if (ret < 0) {
1720 eeprom->len = 0;
1721 return ret;
1722 }
1723 }
1724
1725 memcpy(data, &eeprom_data[eeprom->offset], len);
1726 eeprom->len = len;
1727 return 0;
1728}
1729
1730static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1731 struct ethtool_eeprom *eeprom, u8 *data)
1732{
1733 int ret;
1734 struct smsc911x_data *pdata = netdev_priv(dev);
1735
1736 smsc911x_eeprom_enable_access(pdata);
1737 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1738 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1739 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1740
1741 /* Single byte write, according to man page */
1742 eeprom->len = 1;
1743
1744 return ret;
1745}
1746
cb5b04fe 1747static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 1748 .get_settings = smsc911x_ethtool_getsettings,
1749 .set_settings = smsc911x_ethtool_setsettings,
1750 .get_link = ethtool_op_get_link,
1751 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1752 .nway_reset = smsc911x_ethtool_nwayreset,
1753 .get_msglevel = smsc911x_ethtool_getmsglevel,
1754 .set_msglevel = smsc911x_ethtool_setmsglevel,
1755 .get_regs_len = smsc911x_ethtool_getregslen,
1756 .get_regs = smsc911x_ethtool_getregs,
1757 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1758 .get_eeprom = smsc911x_ethtool_get_eeprom,
1759 .set_eeprom = smsc911x_ethtool_set_eeprom,
1760};
1761
631b7568
SG		 1762static const struct net_device_ops smsc911x_netdev_ops = {
1763 .ndo_open = smsc911x_open,
1764 .ndo_stop = smsc911x_stop,
1765 .ndo_start_xmit = smsc911x_hard_start_xmit,
1766 .ndo_get_stats = smsc911x_get_stats,
1767 .ndo_set_multicast_list = smsc911x_set_multicast_list,
1768 .ndo_do_ioctl = smsc911x_do_ioctl,
1769 .ndo_validate_addr = eth_validate_addr,
225ddf49 1770 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 1771#ifdef CONFIG_NET_POLL_CONTROLLER
1772 .ndo_poll_controller = smsc911x_poll_controller,
1773#endif
1774};
1775
31f45747
SG		 1776/* copies the current mac address from hardware to dev->dev_addr */
1777static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1778{
1779 struct smsc911x_data *pdata = netdev_priv(dev);
1780 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1781 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1782
1783 dev->dev_addr[0] = (u8)(mac_low32);
1784 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1785 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1786 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1787 dev->dev_addr[4] = (u8)(mac_high16);
1788 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1789}
1790
fd9abb3d
SG		 1791/* Initializing private device structures, only called from probe */
1792static int __devinit smsc911x_init(struct net_device *dev)
1793{
1794 struct smsc911x_data *pdata = netdev_priv(dev);
1795 unsigned int byte_test;
1796
1797 SMSC_TRACE(PROBE, "Driver Parameters:");
1798 SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
1799 (unsigned long)pdata->ioaddr);
1800 SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
1801 SMSC_TRACE(PROBE, "PHY will be autodetected.");
1802
fd9abb3d 1803 spin_lock_init(&pdata->dev_lock);
fd9abb3d
SG		 1804
1805 if (pdata->ioaddr == 0) {
1806 SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
1807 return -ENODEV;
1808 }
1809
1810 /* Check byte ordering */
1811 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1812 SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
1813 if (byte_test == 0x43218765) {
1814 SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
1815 "applying WORD_SWAP");
1816 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1817
1818 /* 1 dummy read of BYTE_TEST is needed after a write to
1819 * WORD_SWAP before its contents are valid */
1820 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1821
1822 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1823 }
1824
1825 if (byte_test != 0x87654321) {
1826 SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
1827 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
1828 SMSC_WARNING(PROBE,
1829 "top 16 bits equal to bottom 16 bits");
1830 SMSC_TRACE(PROBE, "This may mean the chip is set "
1831 "for 32 bit while the bus is reading 16 bit");
1832 }
1833 return -ENODEV;
1834 }
1835
1836 /* Default generation to zero (all workarounds apply) */
1837 pdata->generation = 0;
1838
1839 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1840 switch (pdata->idrev & 0xFFFF0000) {
1841 case 0x01180000:
1842 case 0x01170000:
1843 case 0x01160000:
1844 case 0x01150000:
1845 /* LAN911[5678] family */
1846 pdata->generation = pdata->idrev & 0x0000FFFF;
1847 break;
1848
1849 case 0x118A0000:
1850 case 0x117A0000:
1851 case 0x116A0000:
1852 case 0x115A0000:
1853 /* LAN921[5678] family */
1854 pdata->generation = 3;
1855 break;
1856
1857 case 0x92100000:
1858 case 0x92110000:
1859 case 0x92200000:
1860 case 0x92210000:
1861 /* LAN9210/LAN9211/LAN9220/LAN9221 */
1862 pdata->generation = 4;
1863 break;
1864
1865 default:
1866 SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
1867 pdata->idrev);
1868 return -ENODEV;
1869 }
1870
1871 SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
1872 pdata->idrev, pdata->generation);
1873
1874 if (pdata->generation == 0)
1875 SMSC_WARNING(PROBE,
1876 "This driver is not intended for this chip revision");
1877
31f45747
SG		 1878 /* workaround for platforms without an eeprom, where the mac address
1879 * is stored elsewhere and set by the bootloader. This saves the
1880 * mac address before resetting the device */
1881 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS)
1882 smsc911x_read_mac_address(dev);
1883
fd9abb3d
SG		 1884 /* Reset the LAN911x */
1885 if (smsc911x_soft_reset(pdata))
1886 return -ENODEV;
1887
1888 /* Disable all interrupt sources until we bring the device up */
1889 smsc911x_reg_write(pdata, INT_EN, 0);
1890
1891 ether_setup(dev);
fd9abb3d 1892 dev->flags |= IFF_MULTICAST;
fd9abb3d 1893 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 1894 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 1895 dev->ethtool_ops = &smsc911x_ethtool_ops;
1896
fd9abb3d
SG		 1897 return 0;
1898}
1899
1900static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
1901{
1902 struct net_device *dev;
1903 struct smsc911x_data *pdata;
1904 struct resource *res;
1905
1906 dev = platform_get_drvdata(pdev);
1907 BUG_ON(!dev);
1908 pdata = netdev_priv(dev);
1909 BUG_ON(!pdata);
1910 BUG_ON(!pdata->ioaddr);
1911 BUG_ON(!pdata->phy_dev);
1912
1913 SMSC_TRACE(IFDOWN, "Stopping driver.");
1914
1915 phy_disconnect(pdata->phy_dev);
1916 pdata->phy_dev = NULL;
1917 mdiobus_unregister(pdata->mii_bus);
1918 mdiobus_free(pdata->mii_bus);
1919
1920 platform_set_drvdata(pdev, NULL);
1921 unregister_netdev(dev);
1922 free_irq(dev->irq, dev);
1923 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1924 "smsc911x-memory");
1925 if (!res)
d4522739 1926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d
SG		 1927
1928 release_mem_region(res->start, res->end - res->start);
1929
1930 iounmap(pdata->ioaddr);
1931
1932 free_netdev(dev);
1933
1934 return 0;
1935}
1936
1937static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
1938{
1939 struct net_device *dev;
1940 struct smsc911x_data *pdata;
2107fb8b 1941 struct smsc911x_platform_config *config = pdev->dev.platform_data;
61307ed8 1942 struct resource *res, *irq_res;
fd9abb3d 1943 unsigned int intcfg = 0;
61307ed8 1944 int res_size, irq_flags;
fd9abb3d 1945 int retval;
fd9abb3d
SG		 1946
1947 pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
1948
2107fb8b
SG		 1949 /* platform data specifies irq & dynamic bus configuration */
1950 if (!pdev->dev.platform_data) {
1951 pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
1952 retval = -ENODEV;
1953 goto out_0;
1954 }
1955
fd9abb3d
SG		 1956 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1957 "smsc911x-memory");
1958 if (!res)
1959 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1960 if (!res) {
1961 pr_warning("%s: Could not allocate resource.\n",
1962 SMSC_CHIPNAME);
1963 retval = -ENODEV;
1964 goto out_0;
1965 }
1966 res_size = res->end - res->start;
1967
61307ed8
SG		 1968 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1969 if (!irq_res) {
1970 pr_warning("%s: Could not allocate irq resource.\n",
1971 SMSC_CHIPNAME);
1972 retval = -ENODEV;
1973 goto out_0;
1974 }
1975
fd9abb3d
SG		 1976 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
1977 retval = -EBUSY;
1978 goto out_0;
1979 }
1980
1981 dev = alloc_etherdev(sizeof(struct smsc911x_data));
1982 if (!dev) {
1983 pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
1984 retval = -ENOMEM;
1985 goto out_release_io_1;
1986 }
1987
1988 SET_NETDEV_DEV(dev, &pdev->dev);
1989
1990 pdata = netdev_priv(dev);
1991
61307ed8
SG		 1992 dev->irq = irq_res->start;
1993 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 1994 pdata->ioaddr = ioremap_nocache(res->start, res_size);
1995
2107fb8b
SG		 1996 /* copy config parameters across to pdata */
1997 memcpy(&pdata->config, config, sizeof(pdata->config));
fd9abb3d
SG		 1998
1999 pdata->dev = dev;
2000 pdata->msg_enable = ((1 << debug) - 1);
2001
2002 if (pdata->ioaddr == NULL) {
2003 SMSC_WARNING(PROBE,
2004 "Error smsc911x base address invalid");
2005 retval = -ENOMEM;
2006 goto out_free_netdev_2;
2007 }
2008
2009 retval = smsc911x_init(dev);
2010 if (retval < 0)
2011 goto out_unmap_io_3;
2012
2013 /* configure irq polarity and type before connecting isr */
2107fb8b 2014 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2015 intcfg |= INT_CFG_IRQ_POL_;
2016
2107fb8b 2017 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2018 intcfg |= INT_CFG_IRQ_TYPE_;
2019
2020 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2021
2022 /* Ensure interrupts are globally disabled before connecting ISR */
2023 smsc911x_reg_write(pdata, INT_EN, 0);
2024 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2025
61307ed8 2026 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2027 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d
SG		 2028 if (retval) {
2029 SMSC_WARNING(PROBE,
2030 "Unable to claim requested irq: %d", dev->irq);
2031 goto out_unmap_io_3;
2032 }
2033
2034 platform_set_drvdata(pdev, dev);
2035
2036 retval = register_netdev(dev);
2037 if (retval) {
2038 SMSC_WARNING(PROBE,
2039 "Error %i registering device", retval);
2040 goto out_unset_drvdata_4;
2041 } else {
2042 SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
2043 }
2044
2045 spin_lock_init(&pdata->mac_lock);
2046
2047 retval = smsc911x_mii_init(pdev, dev);
2048 if (retval) {
2049 SMSC_WARNING(PROBE,
2050 "Error %i initialising mii", retval);
2051 goto out_unregister_netdev_5;
2052 }
2053
2054 spin_lock_irq(&pdata->mac_lock);
2055
2056 /* Check if mac address has been specified when bringing interface up */
2057 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2058 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 2059 SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
2060 } else {
2061 /* Try reading mac address from device. if EEPROM is present
2062 * it will already have been set */
31f45747 2063 smsc911x_read_mac_address(dev);
fd9abb3d
SG		 2064
2065 if (is_valid_ether_addr(dev->dev_addr)) {
2066 /* eeprom values are valid so use them */
2067 SMSC_TRACE(PROBE,
2068 "Mac Address is read from LAN911x EEPROM");
2069 } else {
2070 /* eeprom values are invalid, generate random MAC */
2071 random_ether_addr(dev->dev_addr);
225ddf49 2072 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 2073 SMSC_TRACE(PROBE,
2074 "MAC Address is set to random_ether_addr");
2075 }
2076 }
2077
2078 spin_unlock_irq(&pdata->mac_lock);
2079
63a2ebb0 2080 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2081
2082 return 0;
2083
2084out_unregister_netdev_5:
2085 unregister_netdev(dev);
2086out_unset_drvdata_4:
2087 platform_set_drvdata(pdev, NULL);
2088 free_irq(dev->irq, dev);
2089out_unmap_io_3:
2090 iounmap(pdata->ioaddr);
2091out_free_netdev_2:
2092 free_netdev(dev);
2093out_release_io_1:
2094 release_mem_region(res->start, res->end - res->start);
2095out_0:
2096 return retval;
2097}
2098
2099static struct platform_driver smsc911x_driver = {
2100 .probe = smsc911x_drv_probe,
2101 .remove = smsc911x_drv_remove,
2102 .driver = {
2103 .name = SMSC_CHIPNAME,
2104 },
2105};
2106
2107/* Entry point for loading the module */
2108static int __init smsc911x_init_module(void)
2109{
2110 return platform_driver_register(&smsc911x_driver);
2111}
2112
2113/* entry point for unloading the module */
2114static void __exit smsc911x_cleanup_module(void)
2115{
2116 platform_driver_unregister(&smsc911x_driver);
2117}
2118
2119module_init(smsc911x_init_module);
2120module_exit(smsc911x_cleanup_module);
ubuntu-zesty-kernel mirror