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[mirror_ubuntu-bionic-kernel.git] / drivers / net / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
32#include <linux/crc32.h>
33#include <linux/delay.h>
34#include <linux/errno.h>
35#include <linux/etherdevice.h>
36#include <linux/ethtool.h>
37#include <linux/init.h>
38#include <linux/ioport.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/netdevice.h>
42#include <linux/platform_device.h>
43#include <linux/sched.h>
44#include <linux/slab.h>
45#include <linux/timer.h>
fd9abb3d
SG		 46#include <linux/bug.h>
47#include <linux/bitops.h>
48#include <linux/irq.h>
49#include <linux/io.h>
833cc67c 50#include <linux/swab.h>
fd9abb3d
SG		 51#include <linux/phy.h>
52#include <linux/smsc911x.h>
53#include "smsc911x.h"
54
55#define SMSC_CHIPNAME "smsc911x"
56#define SMSC_MDIONAME "smsc911x-mdio"
57#define SMSC_DRV_VERSION "2008-10-21"
58
59MODULE_LICENSE("GPL");
60MODULE_VERSION(SMSC_DRV_VERSION);
61
62#if USE_DEBUG > 0
63static int debug = 16;
64#else
65static int debug = 3;
66#endif
67
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71struct smsc911x_data {
72 void __iomem *ioaddr;
73
74 unsigned int idrev;
75
76 /* used to decide which workarounds apply */
77 unsigned int generation;
78
79 /* device configuration (copied from platform_data during probe) */
2107fb8b 80 struct smsc911x_platform_config config;
fd9abb3d
SG		 81
82 /* This needs to be acquired before calling any of below:
83 * smsc911x_mac_read(), smsc911x_mac_write()
84 */
85 spinlock_t mac_lock;
86
2107fb8b
SG		 87 /* spinlock to ensure 16-bit accesses are serialised.
88 * unused with a 32-bit bus */
fd9abb3d 89 spinlock_t dev_lock;
fd9abb3d
SG		 90
91 struct phy_device *phy_dev;
92 struct mii_bus *mii_bus;
93 int phy_irq[PHY_MAX_ADDR];
94 unsigned int using_extphy;
95 int last_duplex;
96 int last_carrier;
97
98 u32 msg_enable;
99 unsigned int gpio_setting;
100 unsigned int gpio_orig_setting;
101 struct net_device *dev;
102 struct napi_struct napi;
103
104 unsigned int software_irq_signal;
105
106#ifdef USE_PHY_WORK_AROUND
107#define MIN_PACKET_SIZE (64)
108 char loopback_tx_pkt[MIN_PACKET_SIZE];
109 char loopback_rx_pkt[MIN_PACKET_SIZE];
110 unsigned int resetcount;
111#endif
112
113 /* Members for Multicast filter workaround */
114 unsigned int multicast_update_pending;
115 unsigned int set_bits_mask;
116 unsigned int clear_bits_mask;
117 unsigned int hashhi;
118 unsigned int hashlo;
119};
120
2107fb8b 121/* The 16-bit access functions are significantly slower, due to the locking
fd9abb3d
SG		 122 * necessary. If your bus hardware can be configured to do this for you
123 * (in response to a single 32-bit operation from software), you should use
124 * the 32-bit access functions instead. */
125
126static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
127{
2107fb8b
SG		 128 if (pdata->config.flags & SMSC911X_USE_32BIT)
129 return readl(pdata->ioaddr + reg);
130
131 if (pdata->config.flags & SMSC911X_USE_16BIT) {
132 u32 data;
133 unsigned long flags;
134
135 /* these two 16-bit reads must be performed consecutively, so
136 * must not be interrupted by our own ISR (which would start
137 * another read operation) */
138 spin_lock_irqsave(&pdata->dev_lock, flags);
139 data = ((readw(pdata->ioaddr + reg) & 0xFFFF) |
140 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
141 spin_unlock_irqrestore(&pdata->dev_lock, flags);
142
143 return data;
144 }
fd9abb3d 145
2107fb8b 146 BUG();
702403af 147 return 0;
fd9abb3d
SG		 148}
149
150static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
151 u32 val)
152{
2107fb8b
SG		 153 if (pdata->config.flags & SMSC911X_USE_32BIT) {
154 writel(val, pdata->ioaddr + reg);
155 return;
156 }
157
158 if (pdata->config.flags & SMSC911X_USE_16BIT) {
159 unsigned long flags;
160
161 /* these two 16-bit writes must be performed consecutively, so
162 * must not be interrupted by our own ISR (which would start
163 * another read operation) */
164 spin_lock_irqsave(&pdata->dev_lock, flags);
165 writew(val & 0xFFFF, pdata->ioaddr + reg);
166 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
167 spin_unlock_irqrestore(&pdata->dev_lock, flags);
168 return;
169 }
fd9abb3d 170
2107fb8b 171 BUG();
fd9abb3d
SG		 172}
173
174/* Writes a packet to the TX_DATA_FIFO */
175static inline void
176smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
177 unsigned int wordcount)
178{
833cc67c
MD		 179 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
180 while (wordcount--)
181 smsc911x_reg_write(pdata, TX_DATA_FIFO, swab32(*buf++));
182 return;
183 }
184
2107fb8b
SG		 185 if (pdata->config.flags & SMSC911X_USE_32BIT) {
186 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
187 return;
188 }
189
190 if (pdata->config.flags & SMSC911X_USE_16BIT) {
191 while (wordcount--)
192 smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
193 return;
194 }
195
196 BUG();
fd9abb3d
SG		 197}
198
199/* Reads a packet out of the RX_DATA_FIFO */
200static inline void
201smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
202 unsigned int wordcount)
203{
833cc67c
MD		 204 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
205 while (wordcount--)
206 *buf++ = swab32(smsc911x_reg_read(pdata, RX_DATA_FIFO));
207 return;
208 }
209
2107fb8b
SG		 210 if (pdata->config.flags & SMSC911X_USE_32BIT) {
211 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
212 return;
213 }
fd9abb3d 214
2107fb8b
SG		 215 if (pdata->config.flags & SMSC911X_USE_16BIT) {
216 while (wordcount--)
217 *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO);
218 return;
219 }
220
221 BUG();
222}
fd9abb3d
SG		 223
224/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
225 * and smsc911x_mac_write, so assumes mac_lock is held */
226static int smsc911x_mac_complete(struct smsc911x_data *pdata)
227{
228 int i;
229 u32 val;
230
231 SMSC_ASSERT_MAC_LOCK(pdata);
232
233 for (i = 0; i < 40; i++) {
234 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
235 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
236 return 0;
237 }
238 SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
239 "MAC_CSR_CMD: 0x%08X", val);
240 return -EIO;
241}
242
243/* Fetches a MAC register value. Assumes mac_lock is acquired */
244static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
245{
246 unsigned int temp;
247
248 SMSC_ASSERT_MAC_LOCK(pdata);
249
250 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
251 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
252 SMSC_WARNING(HW, "MAC busy at entry");
253 return 0xFFFFFFFF;
254 }
255
256 /* Send the MAC cmd */
257 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
258 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
259
260 /* Workaround for hardware read-after-write restriction */
261 temp = smsc911x_reg_read(pdata, BYTE_TEST);
262
263 /* Wait for the read to complete */
264 if (likely(smsc911x_mac_complete(pdata) == 0))
265 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
266
267 SMSC_WARNING(HW, "MAC busy after read");
268 return 0xFFFFFFFF;
269}
270
271/* Set a mac register, mac_lock must be acquired before calling */
272static void smsc911x_mac_write(struct smsc911x_data *pdata,
273 unsigned int offset, u32 val)
274{
275 unsigned int temp;
276
277 SMSC_ASSERT_MAC_LOCK(pdata);
278
279 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
280 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
281 SMSC_WARNING(HW,
282 "smsc911x_mac_write failed, MAC busy at entry");
283 return;
284 }
285
286 /* Send data to write */
287 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
288
289 /* Write the actual data */
290 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
291 MAC_CSR_CMD_CSR_BUSY_));
292
293 /* Workaround for hardware read-after-write restriction */
294 temp = smsc911x_reg_read(pdata, BYTE_TEST);
295
296 /* Wait for the write to complete */
297 if (likely(smsc911x_mac_complete(pdata) == 0))
298 return;
299
300 SMSC_WARNING(HW,
301 "smsc911x_mac_write failed, MAC busy after write");
302}
303
304/* Get a phy register */
305static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
306{
307 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
308 unsigned long flags;
309 unsigned int addr;
310 int i, reg;
311
312 spin_lock_irqsave(&pdata->mac_lock, flags);
313
314 /* Confirm MII not busy */
315 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
316 SMSC_WARNING(HW,
317 "MII is busy in smsc911x_mii_read???");
318 reg = -EIO;
319 goto out;
320 }
321
322 /* Set the address, index & direction (read from PHY) */
323 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
324 smsc911x_mac_write(pdata, MII_ACC, addr);
325
326 /* Wait for read to complete w/ timeout */
327 for (i = 0; i < 100; i++)
328 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
329 reg = smsc911x_mac_read(pdata, MII_DATA);
330 goto out;
331 }
332
150899d2 333 SMSC_WARNING(HW, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 334 reg = -EIO;
335
336out:
337 spin_unlock_irqrestore(&pdata->mac_lock, flags);
338 return reg;
339}
340
341/* Set a phy register */
342static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
343 u16 val)
344{
345 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
346 unsigned long flags;
347 unsigned int addr;
348 int i, reg;
349
350 spin_lock_irqsave(&pdata->mac_lock, flags);
351
352 /* Confirm MII not busy */
353 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
354 SMSC_WARNING(HW,
355 "MII is busy in smsc911x_mii_write???");
356 reg = -EIO;
357 goto out;
358 }
359
360 /* Put the data to write in the MAC */
361 smsc911x_mac_write(pdata, MII_DATA, val);
362
363 /* Set the address, index & direction (write to PHY) */
364 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
365 MII_ACC_MII_WRITE_;
366 smsc911x_mac_write(pdata, MII_ACC, addr);
367
368 /* Wait for write to complete w/ timeout */
369 for (i = 0; i < 100; i++)
370 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
371 reg = 0;
372 goto out;
373 }
374
375 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
376 reg = -EIO;
377
378out:
379 spin_unlock_irqrestore(&pdata->mac_lock, flags);
380 return reg;
381}
382
d23f028a
SG		 383/* Switch to external phy. Assumes tx and rx are stopped. */
384static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 385{
386 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
387
d23f028a
SG		 388 /* Disable phy clocks to the MAC */
389 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
390 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
391 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
392 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 393
d23f028a
SG		 394 /* Switch to external phy */
395 hwcfg |= HW_CFG_EXT_PHY_EN_;
396 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 397
d23f028a
SG		 398 /* Enable phy clocks to the MAC */
399 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
400 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
401 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
402 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 403
d23f028a
SG		 404 hwcfg |= HW_CFG_SMI_SEL_;
405 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
406}
fd9abb3d 407
d23f028a
SG		 408/* Autodetects and enables external phy if present on supported chips.
409 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
410 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
411static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
412{
413 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 414
d23f028a
SG		 415 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
416 SMSC_TRACE(HW, "Forcing internal PHY");
417 pdata->using_extphy = 0;
418 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
419 SMSC_TRACE(HW, "Forcing external PHY");
420 smsc911x_phy_enable_external(pdata);
421 pdata->using_extphy = 1;
422 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
423 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
424 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 425 pdata->using_extphy = 1;
426 } else {
d23f028a
SG		 427 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
428 pdata->using_extphy = 0;
fd9abb3d 429 }
fd9abb3d
SG		 430}
431
432/* Fetches a tx status out of the status fifo */
433static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
434{
435 unsigned int result =
436 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
437
438 if (result != 0)
439 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
440
441 return result;
442}
443
444/* Fetches the next rx status */
445static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
446{
447 unsigned int result =
448 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
449
450 if (result != 0)
451 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
452
453 return result;
454}
455
456#ifdef USE_PHY_WORK_AROUND
457static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
458{
459 unsigned int tries;
460 u32 wrsz;
461 u32 rdsz;
462 ulong bufp;
463
464 for (tries = 0; tries < 10; tries++) {
465 unsigned int txcmd_a;
466 unsigned int txcmd_b;
467 unsigned int status;
468 unsigned int pktlength;
469 unsigned int i;
470
471 /* Zero-out rx packet memory */
472 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
473
474 /* Write tx packet to 118 */
475 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
476 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
477 txcmd_a |= MIN_PACKET_SIZE;
478
479 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
480
481 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
482 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
483
484 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
485 wrsz = MIN_PACKET_SIZE + 3;
486 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
487 wrsz >>= 2;
488
489 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
490
491 /* Wait till transmit is done */
492 i = 60;
493 do {
494 udelay(5);
495 status = smsc911x_tx_get_txstatus(pdata);
496 } while ((i--) && (!status));
497
498 if (!status) {
499 SMSC_WARNING(HW, "Failed to transmit "
500 "during loopback test");
501 continue;
502 }
503 if (status & TX_STS_ES_) {
504 SMSC_WARNING(HW, "Transmit encountered "
505 "errors during loopback test");
506 continue;
507 }
508
509 /* Wait till receive is done */
510 i = 60;
511 do {
512 udelay(5);
513 status = smsc911x_rx_get_rxstatus(pdata);
514 } while ((i--) && (!status));
515
516 if (!status) {
517 SMSC_WARNING(HW,
518 "Failed to receive during loopback test");
519 continue;
520 }
521 if (status & RX_STS_ES_) {
522 SMSC_WARNING(HW, "Receive encountered "
523 "errors during loopback test");
524 continue;
525 }
526
527 pktlength = ((status & 0x3FFF0000UL) >> 16);
528 bufp = (ulong)pdata->loopback_rx_pkt;
529 rdsz = pktlength + 3;
530 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
531 rdsz >>= 2;
532
533 smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
534
535 if (pktlength != (MIN_PACKET_SIZE + 4)) {
536 SMSC_WARNING(HW, "Unexpected packet size "
537 "during loop back test, size=%d, will retry",
538 pktlength);
539 } else {
540 unsigned int j;
541 int mismatch = 0;
542 for (j = 0; j < MIN_PACKET_SIZE; j++) {
543 if (pdata->loopback_tx_pkt[j]
544 != pdata->loopback_rx_pkt[j]) {
545 mismatch = 1;
546 break;
547 }
548 }
549 if (!mismatch) {
550 SMSC_TRACE(HW, "Successfully verified "
551 "loopback packet");
552 return 0;
553 } else {
554 SMSC_WARNING(HW, "Data mismatch "
555 "during loop back test, will retry");
556 }
557 }
558 }
559
560 return -EIO;
561}
562
563static int smsc911x_phy_reset(struct smsc911x_data *pdata)
564{
565 struct phy_device *phy_dev = pdata->phy_dev;
566 unsigned int temp;
567 unsigned int i = 100000;
568
569 BUG_ON(!phy_dev);
570 BUG_ON(!phy_dev->bus);
571
572 SMSC_TRACE(HW, "Performing PHY BCR Reset");
573 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
574 do {
575 msleep(1);
576 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
577 MII_BMCR);
578 } while ((i--) && (temp & BMCR_RESET));
579
580 if (temp & BMCR_RESET) {
581 SMSC_WARNING(HW, "PHY reset failed to complete.");
582 return -EIO;
583 }
584 /* Extra delay required because the phy may not be completed with
585 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
586 * enough delay but using 1ms here to be safe */
587 msleep(1);
588
589 return 0;
590}
591
592static int smsc911x_phy_loopbacktest(struct net_device *dev)
593{
594 struct smsc911x_data *pdata = netdev_priv(dev);
595 struct phy_device *phy_dev = pdata->phy_dev;
596 int result = -EIO;
597 unsigned int i, val;
598 unsigned long flags;
599
600 /* Initialise tx packet using broadcast destination address */
601 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
602
603 /* Use incrementing source address */
604 for (i = 6; i < 12; i++)
605 pdata->loopback_tx_pkt[i] = (char)i;
606
607 /* Set length type field */
608 pdata->loopback_tx_pkt[12] = 0x00;
609 pdata->loopback_tx_pkt[13] = 0x00;
610
611 for (i = 14; i < MIN_PACKET_SIZE; i++)
612 pdata->loopback_tx_pkt[i] = (char)i;
613
614 val = smsc911x_reg_read(pdata, HW_CFG);
615 val &= HW_CFG_TX_FIF_SZ_;
616 val |= HW_CFG_SF_;
617 smsc911x_reg_write(pdata, HW_CFG, val);
618
619 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
620 smsc911x_reg_write(pdata, RX_CFG,
621 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
622
623 for (i = 0; i < 10; i++) {
624 /* Set PHY to 10/FD, no ANEG, and loopback mode */
625 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
626 BMCR_LOOPBACK | BMCR_FULLDPLX);
627
628 /* Enable MAC tx/rx, FD */
629 spin_lock_irqsave(&pdata->mac_lock, flags);
630 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
631 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
632 spin_unlock_irqrestore(&pdata->mac_lock, flags);
633
634 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
635 result = 0;
636 break;
637 }
638 pdata->resetcount++;
639
640 /* Disable MAC rx */
641 spin_lock_irqsave(&pdata->mac_lock, flags);
642 smsc911x_mac_write(pdata, MAC_CR, 0);
643 spin_unlock_irqrestore(&pdata->mac_lock, flags);
644
645 smsc911x_phy_reset(pdata);
646 }
647
648 /* Disable MAC */
649 spin_lock_irqsave(&pdata->mac_lock, flags);
650 smsc911x_mac_write(pdata, MAC_CR, 0);
651 spin_unlock_irqrestore(&pdata->mac_lock, flags);
652
653 /* Cancel PHY loopback mode */
654 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
655
656 smsc911x_reg_write(pdata, TX_CFG, 0);
657 smsc911x_reg_write(pdata, RX_CFG, 0);
658
659 return result;
660}
661#endif /* USE_PHY_WORK_AROUND */
662
fd9abb3d
SG		 663static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
664{
665 struct phy_device *phy_dev = pdata->phy_dev;
666 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
667 u32 flow;
668 unsigned long flags;
669
670 if (phy_dev->duplex == DUPLEX_FULL) {
671 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
672 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 673 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 674
675 if (cap & FLOW_CTRL_RX)
676 flow = 0xFFFF0002;
677 else
678 flow = 0;
679
680 if (cap & FLOW_CTRL_TX)
681 afc |= 0xF;
682 else
683 afc &= ~0xF;
684
685 SMSC_TRACE(HW, "rx pause %s, tx pause %s",
686 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
687 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
688 } else {
689 SMSC_TRACE(HW, "half duplex");
690 flow = 0;
691 afc |= 0xF;
692 }
693
694 spin_lock_irqsave(&pdata->mac_lock, flags);
695 smsc911x_mac_write(pdata, FLOW, flow);
696 spin_unlock_irqrestore(&pdata->mac_lock, flags);
697
698 smsc911x_reg_write(pdata, AFC_CFG, afc);
699}
700
701/* Update link mode if anything has changed. Called periodically when the
702 * PHY is in polling mode, even if nothing has changed. */
703static void smsc911x_phy_adjust_link(struct net_device *dev)
704{
705 struct smsc911x_data *pdata = netdev_priv(dev);
706 struct phy_device *phy_dev = pdata->phy_dev;
707 unsigned long flags;
708 int carrier;
709
710 if (phy_dev->duplex != pdata->last_duplex) {
711 unsigned int mac_cr;
712 SMSC_TRACE(HW, "duplex state has changed");
713
714 spin_lock_irqsave(&pdata->mac_lock, flags);
715 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
716 if (phy_dev->duplex) {
717 SMSC_TRACE(HW,
718 "configuring for full duplex mode");
719 mac_cr |= MAC_CR_FDPX_;
720 } else {
721 SMSC_TRACE(HW,
722 "configuring for half duplex mode");
723 mac_cr &= ~MAC_CR_FDPX_;
724 }
725 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
726 spin_unlock_irqrestore(&pdata->mac_lock, flags);
727
728 smsc911x_phy_update_flowcontrol(pdata);
729 pdata->last_duplex = phy_dev->duplex;
730 }
731
732 carrier = netif_carrier_ok(dev);
733 if (carrier != pdata->last_carrier) {
734 SMSC_TRACE(HW, "carrier state has changed");
735 if (carrier) {
736 SMSC_TRACE(HW, "configuring for carrier OK");
737 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
738 (!pdata->using_extphy)) {
739 /* Restore orginal GPIO configuration */
740 pdata->gpio_setting = pdata->gpio_orig_setting;
741 smsc911x_reg_write(pdata, GPIO_CFG,
742 pdata->gpio_setting);
743 }
744 } else {
745 SMSC_TRACE(HW, "configuring for no carrier");
746 /* Check global setting that LED1
747 * usage is 10/100 indicator */
748 pdata->gpio_setting = smsc911x_reg_read(pdata,
749 GPIO_CFG);
750 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_)
751 && (!pdata->using_extphy)) {
752 /* Force 10/100 LED off, after saving
753 * orginal GPIO configuration */
754 pdata->gpio_orig_setting = pdata->gpio_setting;
755
756 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
757 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
758 | GPIO_CFG_GPIODIR0_
759 | GPIO_CFG_GPIOD0_);
760 smsc911x_reg_write(pdata, GPIO_CFG,
761 pdata->gpio_setting);
762 }
763 }
764 pdata->last_carrier = carrier;
765 }
766}
767
768static int smsc911x_mii_probe(struct net_device *dev)
769{
770 struct smsc911x_data *pdata = netdev_priv(dev);
771 struct phy_device *phydev = NULL;
772 int phy_addr;
773
774 /* find the first phy */
775 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
776 if (pdata->mii_bus->phy_map[phy_addr]) {
777 phydev = pdata->mii_bus->phy_map[phy_addr];
778 SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
779 phy_addr, phydev->addr, phydev->phy_id);
780 break;
781 }
782 }
783
784 if (!phydev) {
785 pr_err("%s: no PHY found\n", dev->name);
786 return -ENODEV;
787 }
788
db1d7bf7 789 phydev = phy_connect(dev, dev_name(&phydev->dev),
2107fb8b 790 &smsc911x_phy_adjust_link, 0, pdata->config.phy_interface);
fd9abb3d
SG		 791
792 if (IS_ERR(phydev)) {
793 pr_err("%s: Could not attach to PHY\n", dev->name);
794 return PTR_ERR(phydev);
795 }
796
797 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7
KS		 798 dev->name, phydev->drv->name,
799 dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 800
801 /* mask with MAC supported features */
802 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
803 SUPPORTED_Asym_Pause);
804 phydev->advertising = phydev->supported;
805
806 pdata->phy_dev = phydev;
807 pdata->last_duplex = -1;
808 pdata->last_carrier = -1;
809
810#ifdef USE_PHY_WORK_AROUND
811 if (smsc911x_phy_loopbacktest(dev) < 0) {
812 SMSC_WARNING(HW, "Failed Loop Back Test");
813 return -ENODEV;
814 }
815 SMSC_TRACE(HW, "Passed Loop Back Test");
816#endif /* USE_PHY_WORK_AROUND */
817
818 SMSC_TRACE(HW, "phy initialised succesfully");
819 return 0;
820}
821
822static int __devinit smsc911x_mii_init(struct platform_device *pdev,
823 struct net_device *dev)
824{
825 struct smsc911x_data *pdata = netdev_priv(dev);
826 int err = -ENXIO, i;
827
828 pdata->mii_bus = mdiobus_alloc();
829 if (!pdata->mii_bus) {
830 err = -ENOMEM;
831 goto err_out_1;
832 }
833
834 pdata->mii_bus->name = SMSC_MDIONAME;
835 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
836 pdata->mii_bus->priv = pdata;
837 pdata->mii_bus->read = smsc911x_mii_read;
838 pdata->mii_bus->write = smsc911x_mii_write;
839 pdata->mii_bus->irq = pdata->phy_irq;
840 for (i = 0; i < PHY_MAX_ADDR; ++i)
841 pdata->mii_bus->irq[i] = PHY_POLL;
842
843 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 844
fd9abb3d
SG		 845 switch (pdata->idrev & 0xFFFF0000) {
846 case 0x01170000:
847 case 0x01150000:
848 case 0x117A0000:
849 case 0x115A0000:
850 /* External PHY supported, try to autodetect */
d23f028a 851 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 852 break;
853 default:
854 SMSC_TRACE(HW, "External PHY is not supported, "
855 "using internal PHY");
d23f028a 856 pdata->using_extphy = 0;
fd9abb3d
SG		 857 break;
858 }
859
860 if (!pdata->using_extphy) {
861 /* Mask all PHYs except ID 1 (internal) */
862 pdata->mii_bus->phy_mask = ~(1 << 1);
863 }
864
865 if (mdiobus_register(pdata->mii_bus)) {
866 SMSC_WARNING(PROBE, "Error registering mii bus");
867 goto err_out_free_bus_2;
868 }
869
870 if (smsc911x_mii_probe(dev) < 0) {
871 SMSC_WARNING(PROBE, "Error registering mii bus");
872 goto err_out_unregister_bus_3;
873 }
874
875 return 0;
876
877err_out_unregister_bus_3:
878 mdiobus_unregister(pdata->mii_bus);
879err_out_free_bus_2:
880 mdiobus_free(pdata->mii_bus);
881err_out_1:
882 return err;
883}
884
885/* Gets the number of tx statuses in the fifo */
886static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
887{
888 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
889 & TX_FIFO_INF_TSUSED_) >> 16;
890}
891
892/* Reads tx statuses and increments counters where necessary */
893static void smsc911x_tx_update_txcounters(struct net_device *dev)
894{
895 struct smsc911x_data *pdata = netdev_priv(dev);
896 unsigned int tx_stat;
897
898 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
899 if (unlikely(tx_stat & 0x80000000)) {
900 /* In this driver the packet tag is used as the packet
901 * length. Since a packet length can never reach the
902 * size of 0x8000, this bit is reserved. It is worth
903 * noting that the "reserved bit" in the warning above
904 * does not reference a hardware defined reserved bit
905 * but rather a driver defined one.
906 */
907 SMSC_WARNING(HW,
908 "Packet tag reserved bit is high");
909 } else {
785b6f97 910 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 911 dev->stats.tx_errors++;
912 } else {
913 dev->stats.tx_packets++;
914 dev->stats.tx_bytes += (tx_stat >> 16);
915 }
785b6f97 916 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 917 dev->stats.collisions += 16;
918 dev->stats.tx_aborted_errors += 1;
919 } else {
920 dev->stats.collisions +=
921 ((tx_stat >> 3) & 0xF);
922 }
785b6f97 923 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 924 dev->stats.tx_carrier_errors += 1;
785b6f97 925 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 926 dev->stats.collisions++;
927 dev->stats.tx_aborted_errors++;
928 }
929 }
930 }
931}
932
933/* Increments the Rx error counters */
934static void
935smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
936{
937 int crc_err = 0;
938
785b6f97 939 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 940 dev->stats.rx_errors++;
785b6f97 941 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 942 dev->stats.rx_crc_errors++;
943 crc_err = 1;
944 }
945 }
946 if (likely(!crc_err)) {
785b6f97
SG		 947 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
948 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 949 dev->stats.rx_length_errors++;
fd9abb3d
SG		 950 if (rxstat & RX_STS_MCAST_)
951 dev->stats.multicast++;
952 }
953}
954
955/* Quickly dumps bad packets */
956static void
957smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
958{
959 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
960
961 if (likely(pktwords >= 4)) {
962 unsigned int timeout = 500;
963 unsigned int val;
964 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
965 do {
966 udelay(1);
967 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 968 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 969
970 if (unlikely(timeout == 0))
971 SMSC_WARNING(HW, "Timed out waiting for "
972 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
973 } else {
974 unsigned int temp;
975 while (pktwords--)
976 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
977 }
978}
979
980/* NAPI poll function */
981static int smsc911x_poll(struct napi_struct *napi, int budget)
982{
983 struct smsc911x_data *pdata =
984 container_of(napi, struct smsc911x_data, napi);
985 struct net_device *dev = pdata->dev;
986 int npackets = 0;
987
988 while (likely(netif_running(dev)) && (npackets < budget)) {
989 unsigned int pktlength;
990 unsigned int pktwords;
991 struct sk_buff *skb;
992 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
993
994 if (!rxstat) {
995 unsigned int temp;
996 /* We processed all packets available. Tell NAPI it can
997 * stop polling then re-enable rx interrupts */
998 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 999 napi_complete(napi);
fd9abb3d
SG		 1000 temp = smsc911x_reg_read(pdata, INT_EN);
1001 temp |= INT_EN_RSFL_EN_;
1002 smsc911x_reg_write(pdata, INT_EN, temp);
1003 break;
1004 }
1005
1006 /* Count packet for NAPI scheduling, even if it has an error.
1007 * Error packets still require cycles to discard */
1008 npackets++;
1009
1010 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1011 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1012 smsc911x_rx_counterrors(dev, rxstat);
1013
1014 if (unlikely(rxstat & RX_STS_ES_)) {
1015 SMSC_WARNING(RX_ERR,
1016 "Discarding packet with error bit set");
1017 /* Packet has an error, discard it and continue with
1018 * the next */
1019 smsc911x_rx_fastforward(pdata, pktwords);
1020 dev->stats.rx_dropped++;
1021 continue;
1022 }
1023
1024 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1025 if (unlikely(!skb)) {
1026 SMSC_WARNING(RX_ERR,
1027 "Unable to allocate skb for rx packet");
1028 /* Drop the packet and stop this polling iteration */
1029 smsc911x_rx_fastforward(pdata, pktwords);
1030 dev->stats.rx_dropped++;
1031 break;
1032 }
1033
1034 skb->data = skb->head;
1035 skb_reset_tail_pointer(skb);
1036
1037 /* Align IP on 16B boundary */
1038 skb_reserve(skb, NET_IP_ALIGN);
1039 skb_put(skb, pktlength - 4);
1040 smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
1041 pktwords);
1042 skb->protocol = eth_type_trans(skb, dev);
1043 skb->ip_summed = CHECKSUM_NONE;
1044 netif_receive_skb(skb);
1045
1046 /* Update counters */
1047 dev->stats.rx_packets++;
1048 dev->stats.rx_bytes += (pktlength - 4);
1049 dev->last_rx = jiffies;
1050 }
1051
1052 /* Return total received packets */
1053 return npackets;
1054}
1055
1056/* Returns hash bit number for given MAC address
1057 * Example:
1058 * 01 00 5E 00 00 01 -> returns bit number 31 */
1059static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1060{
1061 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1062}
1063
1064static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1065{
1066 /* Performs the multicast & mac_cr update. This is called when
1067 * safe on the current hardware, and with the mac_lock held */
1068 unsigned int mac_cr;
1069
1070 SMSC_ASSERT_MAC_LOCK(pdata);
1071
1072 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1073 mac_cr |= pdata->set_bits_mask;
1074 mac_cr &= ~(pdata->clear_bits_mask);
1075 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1076 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1077 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
1078 SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1079 mac_cr, pdata->hashhi, pdata->hashlo);
1080}
1081
1082static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1083{
1084 unsigned int mac_cr;
1085
1086 /* This function is only called for older LAN911x devices
1087 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1088 * be modified during Rx - newer devices immediately update the
1089 * registers.
1090 *
1091 * This is called from interrupt context */
1092
1093 spin_lock(&pdata->mac_lock);
1094
1095 /* Check Rx has stopped */
1096 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
1097 SMSC_WARNING(DRV, "Rx not stopped");
1098
1099 /* Perform the update - safe to do now Rx has stopped */
1100 smsc911x_rx_multicast_update(pdata);
1101
1102 /* Re-enable Rx */
1103 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1104 mac_cr |= MAC_CR_RXEN_;
1105 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1106
1107 pdata->multicast_update_pending = 0;
1108
1109 spin_unlock(&pdata->mac_lock);
1110}
1111
1112static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1113{
1114 unsigned int timeout;
1115 unsigned int temp;
1116
1117 /* Reset the LAN911x */
1118 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1119 timeout = 10;
1120 do {
1121 udelay(10);
1122 temp = smsc911x_reg_read(pdata, HW_CFG);
1123 } while ((--timeout) && (temp & HW_CFG_SRST_));
1124
1125 if (unlikely(temp & HW_CFG_SRST_)) {
1126 SMSC_WARNING(DRV, "Failed to complete reset");
1127 return -EIO;
1128 }
1129 return 0;
1130}
1131
1132/* Sets the device MAC address to dev_addr, called with mac_lock held */
1133static void
225ddf49 1134smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1135{
1136 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1137 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1138 (dev_addr[1] << 8) | dev_addr[0];
1139
1140 SMSC_ASSERT_MAC_LOCK(pdata);
1141
1142 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1143 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1144}
1145
1146static int smsc911x_open(struct net_device *dev)
1147{
1148 struct smsc911x_data *pdata = netdev_priv(dev);
1149 unsigned int timeout;
1150 unsigned int temp;
1151 unsigned int intcfg;
1152
1153 /* if the phy is not yet registered, retry later*/
1154 if (!pdata->phy_dev) {
1155 SMSC_WARNING(HW, "phy_dev is NULL");
1156 return -EAGAIN;
1157 }
1158
1159 if (!is_valid_ether_addr(dev->dev_addr)) {
1160 SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
1161 return -EADDRNOTAVAIL;
1162 }
1163
1164 /* Reset the LAN911x */
1165 if (smsc911x_soft_reset(pdata)) {
1166 SMSC_WARNING(HW, "soft reset failed");
1167 return -EIO;
1168 }
1169
1170 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1171 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1172
1173 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1174 timeout = 50;
f7efb6cc
SG		 1175 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1176 --timeout) {
fd9abb3d
SG		 1177 udelay(10);
1178 }
1179
1180 if (unlikely(timeout == 0))
1181 SMSC_WARNING(IFUP,
1182 "Timed out waiting for EEPROM busy bit to clear");
1183
1184 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1185
1186 /* The soft reset above cleared the device's MAC address,
1187 * restore it from local copy (set in probe) */
1188 spin_lock_irq(&pdata->mac_lock);
225ddf49 1189 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1190 spin_unlock_irq(&pdata->mac_lock);
1191
1192 /* Initialise irqs, but leave all sources disabled */
1193 smsc911x_reg_write(pdata, INT_EN, 0);
1194 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1195
1196 /* Set interrupt deassertion to 100uS */
1197 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1198
2107fb8b 1199 if (pdata->config.irq_polarity) {
fd9abb3d
SG		 1200 SMSC_TRACE(IFUP, "irq polarity: active high");
1201 intcfg |= INT_CFG_IRQ_POL_;
1202 } else {
1203 SMSC_TRACE(IFUP, "irq polarity: active low");
1204 }
1205
2107fb8b 1206 if (pdata->config.irq_type) {
fd9abb3d
SG		 1207 SMSC_TRACE(IFUP, "irq type: push-pull");
1208 intcfg |= INT_CFG_IRQ_TYPE_;
1209 } else {
1210 SMSC_TRACE(IFUP, "irq type: open drain");
1211 }
1212
1213 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1214
1215 SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
1216 pdata->software_irq_signal = 0;
1217 smp_wmb();
1218
1219 temp = smsc911x_reg_read(pdata, INT_EN);
1220 temp |= INT_EN_SW_INT_EN_;
1221 smsc911x_reg_write(pdata, INT_EN, temp);
1222
1223 timeout = 1000;
1224 while (timeout--) {
1225 if (pdata->software_irq_signal)
1226 break;
1227 msleep(1);
1228 }
1229
1230 if (!pdata->software_irq_signal) {
1231 dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
1232 dev->irq);
1233 return -ENODEV;
1234 }
1235 SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
1236
1237 dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1238 (unsigned long)pdata->ioaddr, dev->irq);
1239
44c1d6f9
SG		 1240 /* Reset the last known duplex and carrier */
1241 pdata->last_duplex = -1;
1242 pdata->last_carrier = -1;
1243
fd9abb3d
SG		 1244 /* Bring the PHY up */
1245 phy_start(pdata->phy_dev);
1246
1247 temp = smsc911x_reg_read(pdata, HW_CFG);
1248 /* Preserve TX FIFO size and external PHY configuration */
1249 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1250 temp |= HW_CFG_SF_;
1251 smsc911x_reg_write(pdata, HW_CFG, temp);
1252
1253 temp = smsc911x_reg_read(pdata, FIFO_INT);
1254 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1255 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1256 smsc911x_reg_write(pdata, FIFO_INT, temp);
1257
1258 /* set RX Data offset to 2 bytes for alignment */
1259 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1260
1261 /* enable NAPI polling before enabling RX interrupts */
1262 napi_enable(&pdata->napi);
1263
1264 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1265 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1266 smsc911x_reg_write(pdata, INT_EN, temp);
1267
1268 spin_lock_irq(&pdata->mac_lock);
1269 temp = smsc911x_mac_read(pdata, MAC_CR);
1270 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1271 smsc911x_mac_write(pdata, MAC_CR, temp);
1272 spin_unlock_irq(&pdata->mac_lock);
1273
1274 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1275
1276 netif_start_queue(dev);
1277 return 0;
1278}
1279
1280/* Entry point for stopping the interface */
1281static int smsc911x_stop(struct net_device *dev)
1282{
1283 struct smsc911x_data *pdata = netdev_priv(dev);
1284 unsigned int temp;
1285
fd9abb3d
SG		 1286 /* Disable all device interrupts */
1287 temp = smsc911x_reg_read(pdata, INT_CFG);
1288 temp &= ~INT_CFG_IRQ_EN_;
1289 smsc911x_reg_write(pdata, INT_CFG, temp);
1290
1291 /* Stop Tx and Rx polling */
1292 netif_stop_queue(dev);
1293 napi_disable(&pdata->napi);
1294
1295 /* At this point all Rx and Tx activity is stopped */
1296 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1297 smsc911x_tx_update_txcounters(dev);
1298
1299 /* Bring the PHY down */
dd045193
SG		 1300 if (pdata->phy_dev)
1301 phy_stop(pdata->phy_dev);
fd9abb3d
SG		 1302
1303 SMSC_TRACE(IFDOWN, "Interface stopped");
1304 return 0;
1305}
1306
1307/* Entry point for transmitting a packet */
1308static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1309{
1310 struct smsc911x_data *pdata = netdev_priv(dev);
1311 unsigned int freespace;
1312 unsigned int tx_cmd_a;
1313 unsigned int tx_cmd_b;
1314 unsigned int temp;
1315 u32 wrsz;
1316 ulong bufp;
1317
1318 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1319
1320 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
1321 SMSC_WARNING(TX_ERR,
1322 "Tx data fifo low, space available: %d", freespace);
1323
1324 /* Word alignment adjustment */
1325 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1326 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1327 tx_cmd_a |= (unsigned int)skb->len;
1328
1329 tx_cmd_b = ((unsigned int)skb->len) << 16;
1330 tx_cmd_b |= (unsigned int)skb->len;
1331
1332 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1333 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1334
1335 bufp = (ulong)skb->data & (~0x3);
1336 wrsz = (u32)skb->len + 3;
1337 wrsz += (u32)((ulong)skb->data & 0x3);
1338 wrsz >>= 2;
1339
1340 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
1341 freespace -= (skb->len + 32);
1342 dev_kfree_skb(skb);
1343 dev->trans_start = jiffies;
1344
1345 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1346 smsc911x_tx_update_txcounters(dev);
1347
1348 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1349 netif_stop_queue(dev);
1350 temp = smsc911x_reg_read(pdata, FIFO_INT);
1351 temp &= 0x00FFFFFF;
1352 temp |= 0x32000000;
1353 smsc911x_reg_write(pdata, FIFO_INT, temp);
1354 }
1355
1356 return NETDEV_TX_OK;
1357}
1358
1359/* Entry point for getting status counters */
1360static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1361{
1362 struct smsc911x_data *pdata = netdev_priv(dev);
1363 smsc911x_tx_update_txcounters(dev);
1364 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1365 return &dev->stats;
1366}
1367
1368/* Entry point for setting addressing modes */
1369static void smsc911x_set_multicast_list(struct net_device *dev)
1370{
1371 struct smsc911x_data *pdata = netdev_priv(dev);
1372 unsigned long flags;
1373
1374 if (dev->flags & IFF_PROMISC) {
1375 /* Enabling promiscuous mode */
1376 pdata->set_bits_mask = MAC_CR_PRMS_;
1377 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1378 pdata->hashhi = 0;
1379 pdata->hashlo = 0;
1380 } else if (dev->flags & IFF_ALLMULTI) {
1381 /* Enabling all multicast mode */
1382 pdata->set_bits_mask = MAC_CR_MCPAS_;
1383 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1384 pdata->hashhi = 0;
1385 pdata->hashlo = 0;
1386 } else if (dev->mc_count > 0) {
1387 /* Enabling specific multicast addresses */
1388 unsigned int hash_high = 0;
1389 unsigned int hash_low = 0;
1390 unsigned int count = 0;
1391 struct dev_mc_list *mc_list = dev->mc_list;
1392
1393 pdata->set_bits_mask = MAC_CR_HPFILT_;
1394 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1395
1396 while (mc_list) {
1397 count++;
1398 if ((mc_list->dmi_addrlen) == ETH_ALEN) {
1399 unsigned int bitnum =
1400 smsc911x_hash(mc_list->dmi_addr);
1401 unsigned int mask = 0x01 << (bitnum & 0x1F);
1402 if (bitnum & 0x20)
1403 hash_high |= mask;
1404 else
1405 hash_low |= mask;
1406 } else {
1407 SMSC_WARNING(DRV, "dmi_addrlen != 6");
1408 }
1409 mc_list = mc_list->next;
1410 }
1411 if (count != (unsigned int)dev->mc_count)
1412 SMSC_WARNING(DRV, "mc_count != dev->mc_count");
1413
1414 pdata->hashhi = hash_high;
1415 pdata->hashlo = hash_low;
1416 } else {
1417 /* Enabling local MAC address only */
1418 pdata->set_bits_mask = 0;
1419 pdata->clear_bits_mask =
1420 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1421 pdata->hashhi = 0;
1422 pdata->hashlo = 0;
1423 }
1424
1425 spin_lock_irqsave(&pdata->mac_lock, flags);
1426
1427 if (pdata->generation <= 1) {
1428 /* Older hardware revision - cannot change these flags while
1429 * receiving data */
1430 if (!pdata->multicast_update_pending) {
1431 unsigned int temp;
1432 SMSC_TRACE(HW, "scheduling mcast update");
1433 pdata->multicast_update_pending = 1;
1434
1435 /* Request the hardware to stop, then perform the
1436 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1437 temp = smsc911x_mac_read(pdata, MAC_CR);
1438 temp &= ~(MAC_CR_RXEN_);
1439 smsc911x_mac_write(pdata, MAC_CR, temp);
1440 } else {
1441 /* There is another update pending, this should now
1442 * use the newer values */
1443 }
1444 } else {
1445 /* Newer hardware revision - can write immediately */
1446 smsc911x_rx_multicast_update(pdata);
1447 }
1448
1449 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1450}
1451
1452static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1453{
1454 struct net_device *dev = dev_id;
1455 struct smsc911x_data *pdata = netdev_priv(dev);
1456 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1457 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1458 int serviced = IRQ_NONE;
1459 u32 temp;
1460
1461 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1462 temp = smsc911x_reg_read(pdata, INT_EN);
1463 temp &= (~INT_EN_SW_INT_EN_);
1464 smsc911x_reg_write(pdata, INT_EN, temp);
1465 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1466 pdata->software_irq_signal = 1;
1467 smp_wmb();
1468 serviced = IRQ_HANDLED;
1469 }
1470
1471 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1472 /* Called when there is a multicast update scheduled and
1473 * it is now safe to complete the update */
1474 SMSC_TRACE(INTR, "RX Stop interrupt");
fd9abb3d 1475 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1476 if (pdata->multicast_update_pending)
1477 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1478 serviced = IRQ_HANDLED;
1479 }
1480
1481 if (intsts & inten & INT_STS_TDFA_) {
1482 temp = smsc911x_reg_read(pdata, FIFO_INT);
1483 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1484 smsc911x_reg_write(pdata, FIFO_INT, temp);
1485 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1486 netif_wake_queue(dev);
1487 serviced = IRQ_HANDLED;
1488 }
1489
1490 if (unlikely(intsts & inten & INT_STS_RXE_)) {
1491 SMSC_TRACE(INTR, "RX Error interrupt");
1492 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1493 serviced = IRQ_HANDLED;
1494 }
1495
1496 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1497 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1498 /* Disable Rx interrupts */
1499 temp = smsc911x_reg_read(pdata, INT_EN);
1500 temp &= (~INT_EN_RSFL_EN_);
1501 smsc911x_reg_write(pdata, INT_EN, temp);
1502 /* Schedule a NAPI poll */
288379f0 1503 __napi_schedule(&pdata->napi);
fd9abb3d
SG		 1504 } else {
1505 SMSC_WARNING(RX_ERR,
288379f0 1506 "napi_schedule_prep failed");
fd9abb3d
SG		 1507 }
1508 serviced = IRQ_HANDLED;
1509 }
1510
1511 return serviced;
1512}
1513
1514#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1515static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1516{
1517 disable_irq(dev->irq);
1518 smsc911x_irqhandler(0, dev);
1519 enable_irq(dev->irq);
1520}
1521#endif /* CONFIG_NET_POLL_CONTROLLER */
1522
225ddf49
SG		 1523static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1524{
1525 struct smsc911x_data *pdata = netdev_priv(dev);
1526 struct sockaddr *addr = p;
1527
1528 /* On older hardware revisions we cannot change the mac address
1529 * registers while receiving data. Newer devices can safely change
1530 * this at any time. */
1531 if (pdata->generation <= 1 && netif_running(dev))
1532 return -EBUSY;
1533
1534 if (!is_valid_ether_addr(addr->sa_data))
1535 return -EADDRNOTAVAIL;
1536
1537 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1538
1539 spin_lock_irq(&pdata->mac_lock);
1540 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1541 spin_unlock_irq(&pdata->mac_lock);
1542
1543 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1544
1545 return 0;
1546}
1547
fd9abb3d
SG		 1548/* Standard ioctls for mii-tool */
1549static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1550{
1551 struct smsc911x_data *pdata = netdev_priv(dev);
1552
1553 if (!netif_running(dev) || !pdata->phy_dev)
1554 return -EINVAL;
1555
1556 return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
1557}
1558
1559static int
1560smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1561{
1562 struct smsc911x_data *pdata = netdev_priv(dev);
1563
1564 cmd->maxtxpkt = 1;
1565 cmd->maxrxpkt = 1;
1566 return phy_ethtool_gset(pdata->phy_dev, cmd);
1567}
1568
1569static int
1570smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1571{
1572 struct smsc911x_data *pdata = netdev_priv(dev);
1573
1574 return phy_ethtool_sset(pdata->phy_dev, cmd);
1575}
1576
1577static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1578 struct ethtool_drvinfo *info)
1579{
1580 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1581 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1582 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1583 sizeof(info->bus_info));
1584}
1585
1586static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1587{
1588 struct smsc911x_data *pdata = netdev_priv(dev);
1589
1590 return phy_start_aneg(pdata->phy_dev);
1591}
1592
1593static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1594{
1595 struct smsc911x_data *pdata = netdev_priv(dev);
1596 return pdata->msg_enable;
1597}
1598
1599static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1600{
1601 struct smsc911x_data *pdata = netdev_priv(dev);
1602 pdata->msg_enable = level;
1603}
1604
1605static int smsc911x_ethtool_getregslen(struct net_device *dev)
1606{
1607 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1608 sizeof(u32);
1609}
1610
1611static void
1612smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1613 void *buf)
1614{
1615 struct smsc911x_data *pdata = netdev_priv(dev);
1616 struct phy_device *phy_dev = pdata->phy_dev;
1617 unsigned long flags;
1618 unsigned int i;
1619 unsigned int j = 0;
1620 u32 *data = buf;
1621
1622 regs->version = pdata->idrev;
1623 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1624 data[j++] = smsc911x_reg_read(pdata, i);
1625
1626 for (i = MAC_CR; i <= WUCSR; i++) {
1627 spin_lock_irqsave(&pdata->mac_lock, flags);
1628 data[j++] = smsc911x_mac_read(pdata, i);
1629 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1630 }
1631
1632 for (i = 0; i <= 31; i++)
1633 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1634}
1635
1636static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1637{
1638 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1639 temp &= ~GPIO_CFG_EEPR_EN_;
1640 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1641 msleep(1);
1642}
1643
1644static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1645{
1646 int timeout = 100;
1647 u32 e2cmd;
1648
1649 SMSC_TRACE(DRV, "op 0x%08x", op);
1650 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
1651 SMSC_WARNING(DRV, "Busy at start");
1652 return -EBUSY;
1653 }
1654
1655 e2cmd = op | E2P_CMD_EPC_BUSY_;
1656 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1657
1658 do {
1659 msleep(1);
1660 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1661 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1662
1663 if (!timeout) {
1664 SMSC_TRACE(DRV, "TIMED OUT");
1665 return -EAGAIN;
1666 }
1667
1668 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1669 SMSC_TRACE(DRV, "Error occured during eeprom operation");
1670 return -EINVAL;
1671 }
1672
1673 return 0;
1674}
1675
1676static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1677 u8 address, u8 *data)
1678{
1679 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1680 int ret;
1681
1682 SMSC_TRACE(DRV, "address 0x%x", address);
1683 ret = smsc911x_eeprom_send_cmd(pdata, op);
1684
1685 if (!ret)
1686 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1687
1688 return ret;
1689}
1690
1691static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1692 u8 address, u8 data)
1693{
1694 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 1695 u32 temp;
fd9abb3d
SG		 1696 int ret;
1697
1698 SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
1699 ret = smsc911x_eeprom_send_cmd(pdata, op);
1700
1701 if (!ret) {
1702 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1703 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 1704
1705 /* Workaround for hardware read-after-write restriction */
1706 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1707
fd9abb3d
SG		 1708 ret = smsc911x_eeprom_send_cmd(pdata, op);
1709 }
1710
1711 return ret;
1712}
1713
1714static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1715{
1716 return SMSC911X_EEPROM_SIZE;
1717}
1718
1719static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1720 struct ethtool_eeprom *eeprom, u8 *data)
1721{
1722 struct smsc911x_data *pdata = netdev_priv(dev);
1723 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1724 int len;
1725 int i;
1726
1727 smsc911x_eeprom_enable_access(pdata);
1728
1729 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1730 for (i = 0; i < len; i++) {
1731 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1732 if (ret < 0) {
1733 eeprom->len = 0;
1734 return ret;
1735 }
1736 }
1737
1738 memcpy(data, &eeprom_data[eeprom->offset], len);
1739 eeprom->len = len;
1740 return 0;
1741}
1742
1743static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1744 struct ethtool_eeprom *eeprom, u8 *data)
1745{
1746 int ret;
1747 struct smsc911x_data *pdata = netdev_priv(dev);
1748
1749 smsc911x_eeprom_enable_access(pdata);
1750 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1751 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1752 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1753
1754 /* Single byte write, according to man page */
1755 eeprom->len = 1;
1756
1757 return ret;
1758}
1759
cb5b04fe 1760static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 1761 .get_settings = smsc911x_ethtool_getsettings,
1762 .set_settings = smsc911x_ethtool_setsettings,
1763 .get_link = ethtool_op_get_link,
1764 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1765 .nway_reset = smsc911x_ethtool_nwayreset,
1766 .get_msglevel = smsc911x_ethtool_getmsglevel,
1767 .set_msglevel = smsc911x_ethtool_setmsglevel,
1768 .get_regs_len = smsc911x_ethtool_getregslen,
1769 .get_regs = smsc911x_ethtool_getregs,
1770 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1771 .get_eeprom = smsc911x_ethtool_get_eeprom,
1772 .set_eeprom = smsc911x_ethtool_set_eeprom,
1773};
1774
631b7568
SG		 1775static const struct net_device_ops smsc911x_netdev_ops = {
1776 .ndo_open = smsc911x_open,
1777 .ndo_stop = smsc911x_stop,
1778 .ndo_start_xmit = smsc911x_hard_start_xmit,
1779 .ndo_get_stats = smsc911x_get_stats,
1780 .ndo_set_multicast_list = smsc911x_set_multicast_list,
1781 .ndo_do_ioctl = smsc911x_do_ioctl,
635ecaa7 1782 .ndo_change_mtu = eth_change_mtu,
631b7568 1783 .ndo_validate_addr = eth_validate_addr,
225ddf49 1784 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 1785#ifdef CONFIG_NET_POLL_CONTROLLER
1786 .ndo_poll_controller = smsc911x_poll_controller,
1787#endif
1788};
1789
31f45747
SG		 1790/* copies the current mac address from hardware to dev->dev_addr */
1791static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1792{
1793 struct smsc911x_data *pdata = netdev_priv(dev);
1794 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1795 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1796
1797 dev->dev_addr[0] = (u8)(mac_low32);
1798 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1799 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1800 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1801 dev->dev_addr[4] = (u8)(mac_high16);
1802 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1803}
1804
fd9abb3d
SG		 1805/* Initializing private device structures, only called from probe */
1806static int __devinit smsc911x_init(struct net_device *dev)
1807{
1808 struct smsc911x_data *pdata = netdev_priv(dev);
1809 unsigned int byte_test;
1810
1811 SMSC_TRACE(PROBE, "Driver Parameters:");
1812 SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
1813 (unsigned long)pdata->ioaddr);
1814 SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
1815 SMSC_TRACE(PROBE, "PHY will be autodetected.");
1816
fd9abb3d 1817 spin_lock_init(&pdata->dev_lock);
fd9abb3d
SG		 1818
1819 if (pdata->ioaddr == 0) {
1820 SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
1821 return -ENODEV;
1822 }
1823
1824 /* Check byte ordering */
1825 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1826 SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
1827 if (byte_test == 0x43218765) {
1828 SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
1829 "applying WORD_SWAP");
1830 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1831
1832 /* 1 dummy read of BYTE_TEST is needed after a write to
1833 * WORD_SWAP before its contents are valid */
1834 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1835
1836 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1837 }
1838
1839 if (byte_test != 0x87654321) {
1840 SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
1841 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
1842 SMSC_WARNING(PROBE,
1843 "top 16 bits equal to bottom 16 bits");
1844 SMSC_TRACE(PROBE, "This may mean the chip is set "
1845 "for 32 bit while the bus is reading 16 bit");
1846 }
1847 return -ENODEV;
1848 }
1849
1850 /* Default generation to zero (all workarounds apply) */
1851 pdata->generation = 0;
1852
1853 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1854 switch (pdata->idrev & 0xFFFF0000) {
1855 case 0x01180000:
1856 case 0x01170000:
1857 case 0x01160000:
1858 case 0x01150000:
1859 /* LAN911[5678] family */
1860 pdata->generation = pdata->idrev & 0x0000FFFF;
1861 break;
1862
1863 case 0x118A0000:
1864 case 0x117A0000:
1865 case 0x116A0000:
1866 case 0x115A0000:
1867 /* LAN921[5678] family */
1868 pdata->generation = 3;
1869 break;
1870
1871 case 0x92100000:
1872 case 0x92110000:
1873 case 0x92200000:
1874 case 0x92210000:
1875 /* LAN9210/LAN9211/LAN9220/LAN9221 */
1876 pdata->generation = 4;
1877 break;
1878
1879 default:
1880 SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
1881 pdata->idrev);
1882 return -ENODEV;
1883 }
1884
1885 SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
1886 pdata->idrev, pdata->generation);
1887
1888 if (pdata->generation == 0)
1889 SMSC_WARNING(PROBE,
1890 "This driver is not intended for this chip revision");
1891
31f45747
SG		 1892 /* workaround for platforms without an eeprom, where the mac address
1893 * is stored elsewhere and set by the bootloader. This saves the
1894 * mac address before resetting the device */
1895 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS)
1896 smsc911x_read_mac_address(dev);
1897
fd9abb3d
SG		 1898 /* Reset the LAN911x */
1899 if (smsc911x_soft_reset(pdata))
1900 return -ENODEV;
1901
1902 /* Disable all interrupt sources until we bring the device up */
1903 smsc911x_reg_write(pdata, INT_EN, 0);
1904
1905 ether_setup(dev);
fd9abb3d 1906 dev->flags |= IFF_MULTICAST;
fd9abb3d 1907 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 1908 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 1909 dev->ethtool_ops = &smsc911x_ethtool_ops;
1910
fd9abb3d
SG		 1911 return 0;
1912}
1913
1914static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
1915{
1916 struct net_device *dev;
1917 struct smsc911x_data *pdata;
1918 struct resource *res;
1919
1920 dev = platform_get_drvdata(pdev);
1921 BUG_ON(!dev);
1922 pdata = netdev_priv(dev);
1923 BUG_ON(!pdata);
1924 BUG_ON(!pdata->ioaddr);
1925 BUG_ON(!pdata->phy_dev);
1926
1927 SMSC_TRACE(IFDOWN, "Stopping driver.");
1928
1929 phy_disconnect(pdata->phy_dev);
1930 pdata->phy_dev = NULL;
1931 mdiobus_unregister(pdata->mii_bus);
1932 mdiobus_free(pdata->mii_bus);
1933
1934 platform_set_drvdata(pdev, NULL);
1935 unregister_netdev(dev);
1936 free_irq(dev->irq, dev);
1937 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1938 "smsc911x-memory");
1939 if (!res)
d4522739 1940 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d 1941
39424539 1942 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 1943
1944 iounmap(pdata->ioaddr);
1945
1946 free_netdev(dev);
1947
1948 return 0;
1949}
1950
1951static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
1952{
1953 struct net_device *dev;
1954 struct smsc911x_data *pdata;
2107fb8b 1955 struct smsc911x_platform_config *config = pdev->dev.platform_data;
61307ed8 1956 struct resource *res, *irq_res;
fd9abb3d 1957 unsigned int intcfg = 0;
61307ed8 1958 int res_size, irq_flags;
fd9abb3d 1959 int retval;
fd9abb3d
SG		 1960
1961 pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
1962
2107fb8b
SG		 1963 /* platform data specifies irq & dynamic bus configuration */
1964 if (!pdev->dev.platform_data) {
1965 pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
1966 retval = -ENODEV;
1967 goto out_0;
1968 }
1969
fd9abb3d
SG		 1970 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1971 "smsc911x-memory");
1972 if (!res)
1973 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1974 if (!res) {
1975 pr_warning("%s: Could not allocate resource.\n",
1976 SMSC_CHIPNAME);
1977 retval = -ENODEV;
1978 goto out_0;
1979 }
39424539 1980 res_size = resource_size(res);
fd9abb3d 1981
61307ed8
SG		 1982 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1983 if (!irq_res) {
1984 pr_warning("%s: Could not allocate irq resource.\n",
1985 SMSC_CHIPNAME);
1986 retval = -ENODEV;
1987 goto out_0;
1988 }
1989
fd9abb3d
SG		 1990 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
1991 retval = -EBUSY;
1992 goto out_0;
1993 }
1994
1995 dev = alloc_etherdev(sizeof(struct smsc911x_data));
1996 if (!dev) {
1997 pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
1998 retval = -ENOMEM;
1999 goto out_release_io_1;
2000 }
2001
2002 SET_NETDEV_DEV(dev, &pdev->dev);
2003
2004 pdata = netdev_priv(dev);
2005
61307ed8
SG		 2006 dev->irq = irq_res->start;
2007 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 2008 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2009
2107fb8b
SG		 2010 /* copy config parameters across to pdata */
2011 memcpy(&pdata->config, config, sizeof(pdata->config));
fd9abb3d
SG		 2012
2013 pdata->dev = dev;
2014 pdata->msg_enable = ((1 << debug) - 1);
2015
2016 if (pdata->ioaddr == NULL) {
2017 SMSC_WARNING(PROBE,
2018 "Error smsc911x base address invalid");
2019 retval = -ENOMEM;
2020 goto out_free_netdev_2;
2021 }
2022
2023 retval = smsc911x_init(dev);
2024 if (retval < 0)
2025 goto out_unmap_io_3;
2026
2027 /* configure irq polarity and type before connecting isr */
2107fb8b 2028 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2029 intcfg |= INT_CFG_IRQ_POL_;
2030
2107fb8b 2031 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2032 intcfg |= INT_CFG_IRQ_TYPE_;
2033
2034 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2035
2036 /* Ensure interrupts are globally disabled before connecting ISR */
2037 smsc911x_reg_write(pdata, INT_EN, 0);
2038 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2039
61307ed8 2040 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2041 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d
SG		 2042 if (retval) {
2043 SMSC_WARNING(PROBE,
2044 "Unable to claim requested irq: %d", dev->irq);
2045 goto out_unmap_io_3;
2046 }
2047
2048 platform_set_drvdata(pdev, dev);
2049
2050 retval = register_netdev(dev);
2051 if (retval) {
2052 SMSC_WARNING(PROBE,
2053 "Error %i registering device", retval);
2054 goto out_unset_drvdata_4;
2055 } else {
2056 SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
2057 }
2058
2059 spin_lock_init(&pdata->mac_lock);
2060
2061 retval = smsc911x_mii_init(pdev, dev);
2062 if (retval) {
2063 SMSC_WARNING(PROBE,
2064 "Error %i initialising mii", retval);
2065 goto out_unregister_netdev_5;
2066 }
2067
2068 spin_lock_irq(&pdata->mac_lock);
2069
2070 /* Check if mac address has been specified when bringing interface up */
2071 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2072 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 2073 SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
2074 } else {
2075 /* Try reading mac address from device. if EEPROM is present
2076 * it will already have been set */
31f45747 2077 smsc911x_read_mac_address(dev);
fd9abb3d
SG		 2078
2079 if (is_valid_ether_addr(dev->dev_addr)) {
2080 /* eeprom values are valid so use them */
2081 SMSC_TRACE(PROBE,
2082 "Mac Address is read from LAN911x EEPROM");
2083 } else {
2084 /* eeprom values are invalid, generate random MAC */
2085 random_ether_addr(dev->dev_addr);
225ddf49 2086 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 2087 SMSC_TRACE(PROBE,
2088 "MAC Address is set to random_ether_addr");
2089 }
2090 }
2091
2092 spin_unlock_irq(&pdata->mac_lock);
2093
63a2ebb0 2094 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2095
2096 return 0;
2097
2098out_unregister_netdev_5:
2099 unregister_netdev(dev);
2100out_unset_drvdata_4:
2101 platform_set_drvdata(pdev, NULL);
2102 free_irq(dev->irq, dev);
2103out_unmap_io_3:
2104 iounmap(pdata->ioaddr);
2105out_free_netdev_2:
2106 free_netdev(dev);
2107out_release_io_1:
39424539 2108 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2109out_0:
2110 return retval;
2111}
2112
b6907b0c
DM		 2113#ifdef CONFIG_PM
2114/* This implementation assumes the devices remains powered on its VDDVARIO
2115 * pins during suspend. */
2116
2117static int smsc911x_suspend(struct platform_device *pdev, pm_message_t state)
2118{
2119 struct net_device *dev = platform_get_drvdata(pdev);
2120 struct smsc911x_data *pdata = netdev_priv(dev);
2121
2122 /* enable wake on LAN, energy detection and the external PME
2123 * signal. */
2124 smsc911x_reg_write(pdata, PMT_CTRL,
2125 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2126 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2127
2128 return 0;
2129}
2130
2131static int smsc911x_resume(struct platform_device *pdev)
2132{
2133 struct net_device *dev = platform_get_drvdata(pdev);
2134 struct smsc911x_data *pdata = netdev_priv(dev);
2135 unsigned int to = 100;
2136
2137 /* Note 3.11 from the datasheet:
2138 * "When the LAN9220 is in a power saving state, a write of any
2139 * data to the BYTE_TEST register will wake-up the device."
2140 */
2141 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2142
2143 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2144 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2145 * if it failed. */
2146 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2147 udelay(1000);
2148
2149 return (to == 0) ? -EIO : 0;
2150}
2151
2152#else
2153#define smsc911x_suspend NULL
2154#define smsc911x_resume NULL
2155#endif
2156
fd9abb3d
SG		 2157static struct platform_driver smsc911x_driver = {
2158 .probe = smsc911x_drv_probe,
df911e2d 2159 .remove = __devexit_p(smsc911x_drv_remove),
fd9abb3d
SG		 2160 .driver = {
2161 .name = SMSC_CHIPNAME,
2162 },
b6907b0c
DM		 2163 .suspend = smsc911x_suspend,
2164 .resume = smsc911x_resume,
fd9abb3d
SG		 2165};
2166
2167/* Entry point for loading the module */
2168static int __init smsc911x_init_module(void)
2169{
2170 return platform_driver_register(&smsc911x_driver);
2171}
2172
2173/* entry point for unloading the module */
2174static void __exit smsc911x_cleanup_module(void)
2175{
2176 platform_driver_unregister(&smsc911x_driver);
2177}
2178
2179module_init(smsc911x_init_module);
2180module_exit(smsc911x_cleanup_module);
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