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fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
32#include <linux/crc32.h>
33#include <linux/delay.h>
34#include <linux/errno.h>
35#include <linux/etherdevice.h>
36#include <linux/ethtool.h>
37#include <linux/init.h>
38#include <linux/ioport.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/netdevice.h>
42#include <linux/platform_device.h>
43#include <linux/sched.h>
44#include <linux/slab.h>
45#include <linux/timer.h>
fd9abb3d
SG		 46#include <linux/bug.h>
47#include <linux/bitops.h>
48#include <linux/irq.h>
49#include <linux/io.h>
833cc67c 50#include <linux/swab.h>
fd9abb3d
SG		 51#include <linux/phy.h>
52#include <linux/smsc911x.h>
6cb87823 53#include <linux/device.h>
fd9abb3d
SG		 54#include "smsc911x.h"
55
56#define SMSC_CHIPNAME "smsc911x"
57#define SMSC_MDIONAME "smsc911x-mdio"
58#define SMSC_DRV_VERSION "2008-10-21"
59
60MODULE_LICENSE("GPL");
61MODULE_VERSION(SMSC_DRV_VERSION);
62
63#if USE_DEBUG > 0
64static int debug = 16;
65#else
66static int debug = 3;
67#endif
68
69module_param(debug, int, 0);
70MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72struct smsc911x_data {
73 void __iomem *ioaddr;
74
75 unsigned int idrev;
76
77 /* used to decide which workarounds apply */
78 unsigned int generation;
79
80 /* device configuration (copied from platform_data during probe) */
2107fb8b 81 struct smsc911x_platform_config config;
fd9abb3d
SG		 82
83 /* This needs to be acquired before calling any of below:
84 * smsc911x_mac_read(), smsc911x_mac_write()
85 */
86 spinlock_t mac_lock;
87
2107fb8b
SG		 88 /* spinlock to ensure 16-bit accesses are serialised.
89 * unused with a 32-bit bus */
fd9abb3d 90 spinlock_t dev_lock;
fd9abb3d
SG		 91
92 struct phy_device *phy_dev;
93 struct mii_bus *mii_bus;
94 int phy_irq[PHY_MAX_ADDR];
95 unsigned int using_extphy;
96 int last_duplex;
97 int last_carrier;
98
99 u32 msg_enable;
100 unsigned int gpio_setting;
101 unsigned int gpio_orig_setting;
102 struct net_device *dev;
103 struct napi_struct napi;
104
105 unsigned int software_irq_signal;
106
107#ifdef USE_PHY_WORK_AROUND
108#define MIN_PACKET_SIZE (64)
109 char loopback_tx_pkt[MIN_PACKET_SIZE];
110 char loopback_rx_pkt[MIN_PACKET_SIZE];
111 unsigned int resetcount;
112#endif
113
114 /* Members for Multicast filter workaround */
115 unsigned int multicast_update_pending;
116 unsigned int set_bits_mask;
117 unsigned int clear_bits_mask;
118 unsigned int hashhi;
119 unsigned int hashlo;
120};
121
2107fb8b 122/* The 16-bit access functions are significantly slower, due to the locking
fd9abb3d
SG		 123 * necessary. If your bus hardware can be configured to do this for you
124 * (in response to a single 32-bit operation from software), you should use
125 * the 32-bit access functions instead. */
126
127static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
128{
2107fb8b
SG		 129 if (pdata->config.flags & SMSC911X_USE_32BIT)
130 return readl(pdata->ioaddr + reg);
131
132 if (pdata->config.flags & SMSC911X_USE_16BIT) {
133 u32 data;
134 unsigned long flags;
135
136 /* these two 16-bit reads must be performed consecutively, so
137 * must not be interrupted by our own ISR (which would start
138 * another read operation) */
139 spin_lock_irqsave(&pdata->dev_lock, flags);
140 data = ((readw(pdata->ioaddr + reg) & 0xFFFF) |
141 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
142 spin_unlock_irqrestore(&pdata->dev_lock, flags);
143
144 return data;
145 }
fd9abb3d 146
2107fb8b 147 BUG();
702403af 148 return 0;
fd9abb3d
SG		 149}
150
151static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
152 u32 val)
153{
2107fb8b
SG		 154 if (pdata->config.flags & SMSC911X_USE_32BIT) {
155 writel(val, pdata->ioaddr + reg);
156 return;
157 }
158
159 if (pdata->config.flags & SMSC911X_USE_16BIT) {
160 unsigned long flags;
161
162 /* these two 16-bit writes must be performed consecutively, so
163 * must not be interrupted by our own ISR (which would start
164 * another read operation) */
165 spin_lock_irqsave(&pdata->dev_lock, flags);
166 writew(val & 0xFFFF, pdata->ioaddr + reg);
167 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
168 spin_unlock_irqrestore(&pdata->dev_lock, flags);
169 return;
170 }
fd9abb3d 171
2107fb8b 172 BUG();
fd9abb3d
SG		 173}
174
175/* Writes a packet to the TX_DATA_FIFO */
176static inline void
177smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
178 unsigned int wordcount)
179{
833cc67c
MD		 180 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
181 while (wordcount--)
182 smsc911x_reg_write(pdata, TX_DATA_FIFO, swab32(*buf++));
183 return;
184 }
185
2107fb8b
SG		 186 if (pdata->config.flags & SMSC911X_USE_32BIT) {
187 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
188 return;
189 }
190
191 if (pdata->config.flags & SMSC911X_USE_16BIT) {
192 while (wordcount--)
193 smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
194 return;
195 }
196
197 BUG();
fd9abb3d
SG		 198}
199
200/* Reads a packet out of the RX_DATA_FIFO */
201static inline void
202smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
203 unsigned int wordcount)
204{
833cc67c
MD		 205 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
206 while (wordcount--)
207 *buf++ = swab32(smsc911x_reg_read(pdata, RX_DATA_FIFO));
208 return;
209 }
210
2107fb8b
SG		 211 if (pdata->config.flags & SMSC911X_USE_32BIT) {
212 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
213 return;
214 }
fd9abb3d 215
2107fb8b
SG		 216 if (pdata->config.flags & SMSC911X_USE_16BIT) {
217 while (wordcount--)
218 *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO);
219 return;
220 }
221
222 BUG();
223}
fd9abb3d
SG		 224
225/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
226 * and smsc911x_mac_write, so assumes mac_lock is held */
227static int smsc911x_mac_complete(struct smsc911x_data *pdata)
228{
229 int i;
230 u32 val;
231
232 SMSC_ASSERT_MAC_LOCK(pdata);
233
234 for (i = 0; i < 40; i++) {
235 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
236 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
237 return 0;
238 }
239 SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
240 "MAC_CSR_CMD: 0x%08X", val);
241 return -EIO;
242}
243
244/* Fetches a MAC register value. Assumes mac_lock is acquired */
245static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
246{
247 unsigned int temp;
248
249 SMSC_ASSERT_MAC_LOCK(pdata);
250
251 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
252 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
253 SMSC_WARNING(HW, "MAC busy at entry");
254 return 0xFFFFFFFF;
255 }
256
257 /* Send the MAC cmd */
258 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
259 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
260
261 /* Workaround for hardware read-after-write restriction */
262 temp = smsc911x_reg_read(pdata, BYTE_TEST);
263
264 /* Wait for the read to complete */
265 if (likely(smsc911x_mac_complete(pdata) == 0))
266 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
267
268 SMSC_WARNING(HW, "MAC busy after read");
269 return 0xFFFFFFFF;
270}
271
272/* Set a mac register, mac_lock must be acquired before calling */
273static void smsc911x_mac_write(struct smsc911x_data *pdata,
274 unsigned int offset, u32 val)
275{
276 unsigned int temp;
277
278 SMSC_ASSERT_MAC_LOCK(pdata);
279
280 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
281 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
282 SMSC_WARNING(HW,
283 "smsc911x_mac_write failed, MAC busy at entry");
284 return;
285 }
286
287 /* Send data to write */
288 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
289
290 /* Write the actual data */
291 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
292 MAC_CSR_CMD_CSR_BUSY_));
293
294 /* Workaround for hardware read-after-write restriction */
295 temp = smsc911x_reg_read(pdata, BYTE_TEST);
296
297 /* Wait for the write to complete */
298 if (likely(smsc911x_mac_complete(pdata) == 0))
299 return;
300
301 SMSC_WARNING(HW,
302 "smsc911x_mac_write failed, MAC busy after write");
303}
304
305/* Get a phy register */
306static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
307{
308 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
309 unsigned long flags;
310 unsigned int addr;
311 int i, reg;
312
313 spin_lock_irqsave(&pdata->mac_lock, flags);
314
315 /* Confirm MII not busy */
316 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
317 SMSC_WARNING(HW,
318 "MII is busy in smsc911x_mii_read???");
319 reg = -EIO;
320 goto out;
321 }
322
323 /* Set the address, index & direction (read from PHY) */
324 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
325 smsc911x_mac_write(pdata, MII_ACC, addr);
326
327 /* Wait for read to complete w/ timeout */
328 for (i = 0; i < 100; i++)
329 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
330 reg = smsc911x_mac_read(pdata, MII_DATA);
331 goto out;
332 }
333
150899d2 334 SMSC_WARNING(HW, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 335 reg = -EIO;
336
337out:
338 spin_unlock_irqrestore(&pdata->mac_lock, flags);
339 return reg;
340}
341
342/* Set a phy register */
343static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
344 u16 val)
345{
346 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
347 unsigned long flags;
348 unsigned int addr;
349 int i, reg;
350
351 spin_lock_irqsave(&pdata->mac_lock, flags);
352
353 /* Confirm MII not busy */
354 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
355 SMSC_WARNING(HW,
356 "MII is busy in smsc911x_mii_write???");
357 reg = -EIO;
358 goto out;
359 }
360
361 /* Put the data to write in the MAC */
362 smsc911x_mac_write(pdata, MII_DATA, val);
363
364 /* Set the address, index & direction (write to PHY) */
365 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
366 MII_ACC_MII_WRITE_;
367 smsc911x_mac_write(pdata, MII_ACC, addr);
368
369 /* Wait for write to complete w/ timeout */
370 for (i = 0; i < 100; i++)
371 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
372 reg = 0;
373 goto out;
374 }
375
376 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
377 reg = -EIO;
378
379out:
380 spin_unlock_irqrestore(&pdata->mac_lock, flags);
381 return reg;
382}
383
d23f028a
SG		 384/* Switch to external phy. Assumes tx and rx are stopped. */
385static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 386{
387 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
388
d23f028a
SG		 389 /* Disable phy clocks to the MAC */
390 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
391 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
392 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
393 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 394
d23f028a
SG		 395 /* Switch to external phy */
396 hwcfg |= HW_CFG_EXT_PHY_EN_;
397 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 398
d23f028a
SG		 399 /* Enable phy clocks to the MAC */
400 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
401 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
402 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
403 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 404
d23f028a
SG		 405 hwcfg |= HW_CFG_SMI_SEL_;
406 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
407}
fd9abb3d 408
d23f028a
SG		 409/* Autodetects and enables external phy if present on supported chips.
410 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
411 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
412static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
413{
414 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 415
d23f028a
SG		 416 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
417 SMSC_TRACE(HW, "Forcing internal PHY");
418 pdata->using_extphy = 0;
419 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
420 SMSC_TRACE(HW, "Forcing external PHY");
421 smsc911x_phy_enable_external(pdata);
422 pdata->using_extphy = 1;
423 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
424 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
425 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 426 pdata->using_extphy = 1;
427 } else {
d23f028a
SG		 428 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
429 pdata->using_extphy = 0;
fd9abb3d 430 }
fd9abb3d
SG		 431}
432
433/* Fetches a tx status out of the status fifo */
434static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
435{
436 unsigned int result =
437 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
438
439 if (result != 0)
440 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
441
442 return result;
443}
444
445/* Fetches the next rx status */
446static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
447{
448 unsigned int result =
449 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
450
451 if (result != 0)
452 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
453
454 return result;
455}
456
457#ifdef USE_PHY_WORK_AROUND
458static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
459{
460 unsigned int tries;
461 u32 wrsz;
462 u32 rdsz;
463 ulong bufp;
464
465 for (tries = 0; tries < 10; tries++) {
466 unsigned int txcmd_a;
467 unsigned int txcmd_b;
468 unsigned int status;
469 unsigned int pktlength;
470 unsigned int i;
471
472 /* Zero-out rx packet memory */
473 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
474
475 /* Write tx packet to 118 */
476 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
477 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
478 txcmd_a |= MIN_PACKET_SIZE;
479
480 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
481
482 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
483 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
484
485 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
486 wrsz = MIN_PACKET_SIZE + 3;
487 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
488 wrsz >>= 2;
489
490 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
491
492 /* Wait till transmit is done */
493 i = 60;
494 do {
495 udelay(5);
496 status = smsc911x_tx_get_txstatus(pdata);
497 } while ((i--) && (!status));
498
499 if (!status) {
500 SMSC_WARNING(HW, "Failed to transmit "
501 "during loopback test");
502 continue;
503 }
504 if (status & TX_STS_ES_) {
505 SMSC_WARNING(HW, "Transmit encountered "
506 "errors during loopback test");
507 continue;
508 }
509
510 /* Wait till receive is done */
511 i = 60;
512 do {
513 udelay(5);
514 status = smsc911x_rx_get_rxstatus(pdata);
515 } while ((i--) && (!status));
516
517 if (!status) {
518 SMSC_WARNING(HW,
519 "Failed to receive during loopback test");
520 continue;
521 }
522 if (status & RX_STS_ES_) {
523 SMSC_WARNING(HW, "Receive encountered "
524 "errors during loopback test");
525 continue;
526 }
527
528 pktlength = ((status & 0x3FFF0000UL) >> 16);
529 bufp = (ulong)pdata->loopback_rx_pkt;
530 rdsz = pktlength + 3;
531 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
532 rdsz >>= 2;
533
534 smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
535
536 if (pktlength != (MIN_PACKET_SIZE + 4)) {
537 SMSC_WARNING(HW, "Unexpected packet size "
538 "during loop back test, size=%d, will retry",
539 pktlength);
540 } else {
541 unsigned int j;
542 int mismatch = 0;
543 for (j = 0; j < MIN_PACKET_SIZE; j++) {
544 if (pdata->loopback_tx_pkt[j]
545 != pdata->loopback_rx_pkt[j]) {
546 mismatch = 1;
547 break;
548 }
549 }
550 if (!mismatch) {
551 SMSC_TRACE(HW, "Successfully verified "
552 "loopback packet");
553 return 0;
554 } else {
555 SMSC_WARNING(HW, "Data mismatch "
556 "during loop back test, will retry");
557 }
558 }
559 }
560
561 return -EIO;
562}
563
564static int smsc911x_phy_reset(struct smsc911x_data *pdata)
565{
566 struct phy_device *phy_dev = pdata->phy_dev;
567 unsigned int temp;
568 unsigned int i = 100000;
569
570 BUG_ON(!phy_dev);
571 BUG_ON(!phy_dev->bus);
572
573 SMSC_TRACE(HW, "Performing PHY BCR Reset");
574 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
575 do {
576 msleep(1);
577 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
578 MII_BMCR);
579 } while ((i--) && (temp & BMCR_RESET));
580
581 if (temp & BMCR_RESET) {
582 SMSC_WARNING(HW, "PHY reset failed to complete.");
583 return -EIO;
584 }
585 /* Extra delay required because the phy may not be completed with
586 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
587 * enough delay but using 1ms here to be safe */
588 msleep(1);
589
590 return 0;
591}
592
593static int smsc911x_phy_loopbacktest(struct net_device *dev)
594{
595 struct smsc911x_data *pdata = netdev_priv(dev);
596 struct phy_device *phy_dev = pdata->phy_dev;
597 int result = -EIO;
598 unsigned int i, val;
599 unsigned long flags;
600
601 /* Initialise tx packet using broadcast destination address */
602 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
603
604 /* Use incrementing source address */
605 for (i = 6; i < 12; i++)
606 pdata->loopback_tx_pkt[i] = (char)i;
607
608 /* Set length type field */
609 pdata->loopback_tx_pkt[12] = 0x00;
610 pdata->loopback_tx_pkt[13] = 0x00;
611
612 for (i = 14; i < MIN_PACKET_SIZE; i++)
613 pdata->loopback_tx_pkt[i] = (char)i;
614
615 val = smsc911x_reg_read(pdata, HW_CFG);
616 val &= HW_CFG_TX_FIF_SZ_;
617 val |= HW_CFG_SF_;
618 smsc911x_reg_write(pdata, HW_CFG, val);
619
620 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
621 smsc911x_reg_write(pdata, RX_CFG,
622 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
623
624 for (i = 0; i < 10; i++) {
625 /* Set PHY to 10/FD, no ANEG, and loopback mode */
626 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
627 BMCR_LOOPBACK | BMCR_FULLDPLX);
628
629 /* Enable MAC tx/rx, FD */
630 spin_lock_irqsave(&pdata->mac_lock, flags);
631 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
632 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
633 spin_unlock_irqrestore(&pdata->mac_lock, flags);
634
635 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
636 result = 0;
637 break;
638 }
639 pdata->resetcount++;
640
641 /* Disable MAC rx */
642 spin_lock_irqsave(&pdata->mac_lock, flags);
643 smsc911x_mac_write(pdata, MAC_CR, 0);
644 spin_unlock_irqrestore(&pdata->mac_lock, flags);
645
646 smsc911x_phy_reset(pdata);
647 }
648
649 /* Disable MAC */
650 spin_lock_irqsave(&pdata->mac_lock, flags);
651 smsc911x_mac_write(pdata, MAC_CR, 0);
652 spin_unlock_irqrestore(&pdata->mac_lock, flags);
653
654 /* Cancel PHY loopback mode */
655 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
656
657 smsc911x_reg_write(pdata, TX_CFG, 0);
658 smsc911x_reg_write(pdata, RX_CFG, 0);
659
660 return result;
661}
662#endif /* USE_PHY_WORK_AROUND */
663
fd9abb3d
SG		 664static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
665{
666 struct phy_device *phy_dev = pdata->phy_dev;
667 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
668 u32 flow;
669 unsigned long flags;
670
671 if (phy_dev->duplex == DUPLEX_FULL) {
672 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
673 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 674 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 675
676 if (cap & FLOW_CTRL_RX)
677 flow = 0xFFFF0002;
678 else
679 flow = 0;
680
681 if (cap & FLOW_CTRL_TX)
682 afc |= 0xF;
683 else
684 afc &= ~0xF;
685
686 SMSC_TRACE(HW, "rx pause %s, tx pause %s",
687 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
688 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
689 } else {
690 SMSC_TRACE(HW, "half duplex");
691 flow = 0;
692 afc |= 0xF;
693 }
694
695 spin_lock_irqsave(&pdata->mac_lock, flags);
696 smsc911x_mac_write(pdata, FLOW, flow);
697 spin_unlock_irqrestore(&pdata->mac_lock, flags);
698
699 smsc911x_reg_write(pdata, AFC_CFG, afc);
700}
701
702/* Update link mode if anything has changed. Called periodically when the
703 * PHY is in polling mode, even if nothing has changed. */
704static void smsc911x_phy_adjust_link(struct net_device *dev)
705{
706 struct smsc911x_data *pdata = netdev_priv(dev);
707 struct phy_device *phy_dev = pdata->phy_dev;
708 unsigned long flags;
709 int carrier;
710
711 if (phy_dev->duplex != pdata->last_duplex) {
712 unsigned int mac_cr;
713 SMSC_TRACE(HW, "duplex state has changed");
714
715 spin_lock_irqsave(&pdata->mac_lock, flags);
716 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
717 if (phy_dev->duplex) {
718 SMSC_TRACE(HW,
719 "configuring for full duplex mode");
720 mac_cr |= MAC_CR_FDPX_;
721 } else {
722 SMSC_TRACE(HW,
723 "configuring for half duplex mode");
724 mac_cr &= ~MAC_CR_FDPX_;
725 }
726 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
727 spin_unlock_irqrestore(&pdata->mac_lock, flags);
728
729 smsc911x_phy_update_flowcontrol(pdata);
730 pdata->last_duplex = phy_dev->duplex;
731 }
732
733 carrier = netif_carrier_ok(dev);
734 if (carrier != pdata->last_carrier) {
735 SMSC_TRACE(HW, "carrier state has changed");
736 if (carrier) {
737 SMSC_TRACE(HW, "configuring for carrier OK");
738 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
739 (!pdata->using_extphy)) {
740 /* Restore orginal GPIO configuration */
741 pdata->gpio_setting = pdata->gpio_orig_setting;
742 smsc911x_reg_write(pdata, GPIO_CFG,
743 pdata->gpio_setting);
744 }
745 } else {
746 SMSC_TRACE(HW, "configuring for no carrier");
747 /* Check global setting that LED1
748 * usage is 10/100 indicator */
749 pdata->gpio_setting = smsc911x_reg_read(pdata,
750 GPIO_CFG);
8e95a202
JP		 751 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
752 (!pdata->using_extphy)) {
fd9abb3d
SG		 753 /* Force 10/100 LED off, after saving
754 * orginal GPIO configuration */
755 pdata->gpio_orig_setting = pdata->gpio_setting;
756
757 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
758 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
759 | GPIO_CFG_GPIODIR0_
760 | GPIO_CFG_GPIOD0_);
761 smsc911x_reg_write(pdata, GPIO_CFG,
762 pdata->gpio_setting);
763 }
764 }
765 pdata->last_carrier = carrier;
766 }
767}
768
769static int smsc911x_mii_probe(struct net_device *dev)
770{
771 struct smsc911x_data *pdata = netdev_priv(dev);
772 struct phy_device *phydev = NULL;
e4a474f8 773 int ret;
fd9abb3d
SG		 774
775 /* find the first phy */
e4a474f8 776 phydev = phy_find_first(pdata->mii_bus);
fd9abb3d
SG		 777 if (!phydev) {
778 pr_err("%s: no PHY found\n", dev->name);
779 return -ENODEV;
780 }
781
e4a474f8 782 SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
783 phy_addr, phydev->addr, phydev->phy_id);
784
785 ret = phy_connect_direct(dev, phydev,
786 &smsc911x_phy_adjust_link, 0,
787 pdata->config.phy_interface);
fd9abb3d 788
e4a474f8 789 if (ret) {
fd9abb3d 790 pr_err("%s: Could not attach to PHY\n", dev->name);
e4a474f8 791 return ret;
fd9abb3d
SG		 792 }
793
794 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7
KS		 795 dev->name, phydev->drv->name,
796 dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 797
798 /* mask with MAC supported features */
799 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
800 SUPPORTED_Asym_Pause);
801 phydev->advertising = phydev->supported;
802
803 pdata->phy_dev = phydev;
804 pdata->last_duplex = -1;
805 pdata->last_carrier = -1;
806
807#ifdef USE_PHY_WORK_AROUND
808 if (smsc911x_phy_loopbacktest(dev) < 0) {
809 SMSC_WARNING(HW, "Failed Loop Back Test");
810 return -ENODEV;
811 }
812 SMSC_TRACE(HW, "Passed Loop Back Test");
813#endif /* USE_PHY_WORK_AROUND */
814
af901ca1 815 SMSC_TRACE(HW, "phy initialised successfully");
fd9abb3d
SG		 816 return 0;
817}
818
819static int __devinit smsc911x_mii_init(struct platform_device *pdev,
820 struct net_device *dev)
821{
822 struct smsc911x_data *pdata = netdev_priv(dev);
823 int err = -ENXIO, i;
824
825 pdata->mii_bus = mdiobus_alloc();
826 if (!pdata->mii_bus) {
827 err = -ENOMEM;
828 goto err_out_1;
829 }
830
831 pdata->mii_bus->name = SMSC_MDIONAME;
832 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
833 pdata->mii_bus->priv = pdata;
834 pdata->mii_bus->read = smsc911x_mii_read;
835 pdata->mii_bus->write = smsc911x_mii_write;
836 pdata->mii_bus->irq = pdata->phy_irq;
837 for (i = 0; i < PHY_MAX_ADDR; ++i)
838 pdata->mii_bus->irq[i] = PHY_POLL;
839
840 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 841
fd9abb3d
SG		 842 switch (pdata->idrev & 0xFFFF0000) {
843 case 0x01170000:
844 case 0x01150000:
845 case 0x117A0000:
846 case 0x115A0000:
847 /* External PHY supported, try to autodetect */
d23f028a 848 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 849 break;
850 default:
851 SMSC_TRACE(HW, "External PHY is not supported, "
852 "using internal PHY");
d23f028a 853 pdata->using_extphy = 0;
fd9abb3d
SG		 854 break;
855 }
856
857 if (!pdata->using_extphy) {
858 /* Mask all PHYs except ID 1 (internal) */
859 pdata->mii_bus->phy_mask = ~(1 << 1);
860 }
861
862 if (mdiobus_register(pdata->mii_bus)) {
863 SMSC_WARNING(PROBE, "Error registering mii bus");
864 goto err_out_free_bus_2;
865 }
866
867 if (smsc911x_mii_probe(dev) < 0) {
868 SMSC_WARNING(PROBE, "Error registering mii bus");
869 goto err_out_unregister_bus_3;
870 }
871
872 return 0;
873
874err_out_unregister_bus_3:
875 mdiobus_unregister(pdata->mii_bus);
876err_out_free_bus_2:
877 mdiobus_free(pdata->mii_bus);
878err_out_1:
879 return err;
880}
881
882/* Gets the number of tx statuses in the fifo */
883static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
884{
885 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
886 & TX_FIFO_INF_TSUSED_) >> 16;
887}
888
889/* Reads tx statuses and increments counters where necessary */
890static void smsc911x_tx_update_txcounters(struct net_device *dev)
891{
892 struct smsc911x_data *pdata = netdev_priv(dev);
893 unsigned int tx_stat;
894
895 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
896 if (unlikely(tx_stat & 0x80000000)) {
897 /* In this driver the packet tag is used as the packet
898 * length. Since a packet length can never reach the
899 * size of 0x8000, this bit is reserved. It is worth
900 * noting that the "reserved bit" in the warning above
901 * does not reference a hardware defined reserved bit
902 * but rather a driver defined one.
903 */
904 SMSC_WARNING(HW,
905 "Packet tag reserved bit is high");
906 } else {
785b6f97 907 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 908 dev->stats.tx_errors++;
909 } else {
910 dev->stats.tx_packets++;
911 dev->stats.tx_bytes += (tx_stat >> 16);
912 }
785b6f97 913 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 914 dev->stats.collisions += 16;
915 dev->stats.tx_aborted_errors += 1;
916 } else {
917 dev->stats.collisions +=
918 ((tx_stat >> 3) & 0xF);
919 }
785b6f97 920 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 921 dev->stats.tx_carrier_errors += 1;
785b6f97 922 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 923 dev->stats.collisions++;
924 dev->stats.tx_aborted_errors++;
925 }
926 }
927 }
928}
929
930/* Increments the Rx error counters */
931static void
932smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
933{
934 int crc_err = 0;
935
785b6f97 936 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 937 dev->stats.rx_errors++;
785b6f97 938 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 939 dev->stats.rx_crc_errors++;
940 crc_err = 1;
941 }
942 }
943 if (likely(!crc_err)) {
785b6f97
SG		 944 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
945 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 946 dev->stats.rx_length_errors++;
fd9abb3d
SG		 947 if (rxstat & RX_STS_MCAST_)
948 dev->stats.multicast++;
949 }
950}
951
952/* Quickly dumps bad packets */
953static void
954smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
955{
956 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
957
958 if (likely(pktwords >= 4)) {
959 unsigned int timeout = 500;
960 unsigned int val;
961 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
962 do {
963 udelay(1);
964 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 965 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 966
967 if (unlikely(timeout == 0))
968 SMSC_WARNING(HW, "Timed out waiting for "
969 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
970 } else {
971 unsigned int temp;
972 while (pktwords--)
973 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
974 }
975}
976
977/* NAPI poll function */
978static int smsc911x_poll(struct napi_struct *napi, int budget)
979{
980 struct smsc911x_data *pdata =
981 container_of(napi, struct smsc911x_data, napi);
982 struct net_device *dev = pdata->dev;
983 int npackets = 0;
984
f88c5b98 985 while (npackets < budget) {
fd9abb3d
SG		 986 unsigned int pktlength;
987 unsigned int pktwords;
988 struct sk_buff *skb;
989 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
990
991 if (!rxstat) {
992 unsigned int temp;
993 /* We processed all packets available. Tell NAPI it can
994 * stop polling then re-enable rx interrupts */
995 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 996 napi_complete(napi);
fd9abb3d
SG		 997 temp = smsc911x_reg_read(pdata, INT_EN);
998 temp |= INT_EN_RSFL_EN_;
999 smsc911x_reg_write(pdata, INT_EN, temp);
1000 break;
1001 }
1002
1003 /* Count packet for NAPI scheduling, even if it has an error.
1004 * Error packets still require cycles to discard */
1005 npackets++;
1006
1007 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1008 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1009 smsc911x_rx_counterrors(dev, rxstat);
1010
1011 if (unlikely(rxstat & RX_STS_ES_)) {
1012 SMSC_WARNING(RX_ERR,
1013 "Discarding packet with error bit set");
1014 /* Packet has an error, discard it and continue with
1015 * the next */
1016 smsc911x_rx_fastforward(pdata, pktwords);
1017 dev->stats.rx_dropped++;
1018 continue;
1019 }
1020
1021 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1022 if (unlikely(!skb)) {
1023 SMSC_WARNING(RX_ERR,
1024 "Unable to allocate skb for rx packet");
1025 /* Drop the packet and stop this polling iteration */
1026 smsc911x_rx_fastforward(pdata, pktwords);
1027 dev->stats.rx_dropped++;
1028 break;
1029 }
1030
1031 skb->data = skb->head;
1032 skb_reset_tail_pointer(skb);
1033
1034 /* Align IP on 16B boundary */
1035 skb_reserve(skb, NET_IP_ALIGN);
1036 skb_put(skb, pktlength - 4);
1037 smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
1038 pktwords);
1039 skb->protocol = eth_type_trans(skb, dev);
1040 skb->ip_summed = CHECKSUM_NONE;
1041 netif_receive_skb(skb);
1042
1043 /* Update counters */
1044 dev->stats.rx_packets++;
1045 dev->stats.rx_bytes += (pktlength - 4);
fd9abb3d
SG		 1046 }
1047
1048 /* Return total received packets */
1049 return npackets;
1050}
1051
1052/* Returns hash bit number for given MAC address
1053 * Example:
1054 * 01 00 5E 00 00 01 -> returns bit number 31 */
1055static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1056{
1057 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1058}
1059
1060static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1061{
1062 /* Performs the multicast & mac_cr update. This is called when
1063 * safe on the current hardware, and with the mac_lock held */
1064 unsigned int mac_cr;
1065
1066 SMSC_ASSERT_MAC_LOCK(pdata);
1067
1068 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1069 mac_cr |= pdata->set_bits_mask;
1070 mac_cr &= ~(pdata->clear_bits_mask);
1071 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1072 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1073 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
1074 SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1075 mac_cr, pdata->hashhi, pdata->hashlo);
1076}
1077
1078static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1079{
1080 unsigned int mac_cr;
1081
1082 /* This function is only called for older LAN911x devices
1083 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1084 * be modified during Rx - newer devices immediately update the
1085 * registers.
1086 *
1087 * This is called from interrupt context */
1088
1089 spin_lock(&pdata->mac_lock);
1090
1091 /* Check Rx has stopped */
1092 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
1093 SMSC_WARNING(DRV, "Rx not stopped");
1094
1095 /* Perform the update - safe to do now Rx has stopped */
1096 smsc911x_rx_multicast_update(pdata);
1097
1098 /* Re-enable Rx */
1099 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1100 mac_cr |= MAC_CR_RXEN_;
1101 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1102
1103 pdata->multicast_update_pending = 0;
1104
1105 spin_unlock(&pdata->mac_lock);
1106}
1107
1108static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1109{
1110 unsigned int timeout;
1111 unsigned int temp;
1112
1113 /* Reset the LAN911x */
1114 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1115 timeout = 10;
1116 do {
1117 udelay(10);
1118 temp = smsc911x_reg_read(pdata, HW_CFG);
1119 } while ((--timeout) && (temp & HW_CFG_SRST_));
1120
1121 if (unlikely(temp & HW_CFG_SRST_)) {
1122 SMSC_WARNING(DRV, "Failed to complete reset");
1123 return -EIO;
1124 }
1125 return 0;
1126}
1127
1128/* Sets the device MAC address to dev_addr, called with mac_lock held */
1129static void
225ddf49 1130smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1131{
1132 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1133 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1134 (dev_addr[1] << 8) | dev_addr[0];
1135
1136 SMSC_ASSERT_MAC_LOCK(pdata);
1137
1138 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1139 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1140}
1141
1142static int smsc911x_open(struct net_device *dev)
1143{
1144 struct smsc911x_data *pdata = netdev_priv(dev);
1145 unsigned int timeout;
1146 unsigned int temp;
1147 unsigned int intcfg;
1148
1149 /* if the phy is not yet registered, retry later*/
1150 if (!pdata->phy_dev) {
1151 SMSC_WARNING(HW, "phy_dev is NULL");
1152 return -EAGAIN;
1153 }
1154
1155 if (!is_valid_ether_addr(dev->dev_addr)) {
1156 SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
1157 return -EADDRNOTAVAIL;
1158 }
1159
1160 /* Reset the LAN911x */
1161 if (smsc911x_soft_reset(pdata)) {
1162 SMSC_WARNING(HW, "soft reset failed");
1163 return -EIO;
1164 }
1165
1166 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1167 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1168
1169 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1170 timeout = 50;
f7efb6cc
SG		 1171 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1172 --timeout) {
fd9abb3d
SG		 1173 udelay(10);
1174 }
1175
1176 if (unlikely(timeout == 0))
1177 SMSC_WARNING(IFUP,
1178 "Timed out waiting for EEPROM busy bit to clear");
1179
1180 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1181
1182 /* The soft reset above cleared the device's MAC address,
1183 * restore it from local copy (set in probe) */
1184 spin_lock_irq(&pdata->mac_lock);
225ddf49 1185 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1186 spin_unlock_irq(&pdata->mac_lock);
1187
1188 /* Initialise irqs, but leave all sources disabled */
1189 smsc911x_reg_write(pdata, INT_EN, 0);
1190 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1191
1192 /* Set interrupt deassertion to 100uS */
1193 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1194
2107fb8b 1195 if (pdata->config.irq_polarity) {
fd9abb3d
SG		 1196 SMSC_TRACE(IFUP, "irq polarity: active high");
1197 intcfg |= INT_CFG_IRQ_POL_;
1198 } else {
1199 SMSC_TRACE(IFUP, "irq polarity: active low");
1200 }
1201
2107fb8b 1202 if (pdata->config.irq_type) {
fd9abb3d
SG		 1203 SMSC_TRACE(IFUP, "irq type: push-pull");
1204 intcfg |= INT_CFG_IRQ_TYPE_;
1205 } else {
1206 SMSC_TRACE(IFUP, "irq type: open drain");
1207 }
1208
1209 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1210
1211 SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
1212 pdata->software_irq_signal = 0;
1213 smp_wmb();
1214
1215 temp = smsc911x_reg_read(pdata, INT_EN);
1216 temp |= INT_EN_SW_INT_EN_;
1217 smsc911x_reg_write(pdata, INT_EN, temp);
1218
1219 timeout = 1000;
1220 while (timeout--) {
1221 if (pdata->software_irq_signal)
1222 break;
1223 msleep(1);
1224 }
1225
1226 if (!pdata->software_irq_signal) {
1227 dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
1228 dev->irq);
1229 return -ENODEV;
1230 }
1231 SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
1232
1233 dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1234 (unsigned long)pdata->ioaddr, dev->irq);
1235
44c1d6f9
SG		 1236 /* Reset the last known duplex and carrier */
1237 pdata->last_duplex = -1;
1238 pdata->last_carrier = -1;
1239
fd9abb3d
SG		 1240 /* Bring the PHY up */
1241 phy_start(pdata->phy_dev);
1242
1243 temp = smsc911x_reg_read(pdata, HW_CFG);
1244 /* Preserve TX FIFO size and external PHY configuration */
1245 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1246 temp |= HW_CFG_SF_;
1247 smsc911x_reg_write(pdata, HW_CFG, temp);
1248
1249 temp = smsc911x_reg_read(pdata, FIFO_INT);
1250 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1251 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1252 smsc911x_reg_write(pdata, FIFO_INT, temp);
1253
1254 /* set RX Data offset to 2 bytes for alignment */
1255 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1256
1257 /* enable NAPI polling before enabling RX interrupts */
1258 napi_enable(&pdata->napi);
1259
1260 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1261 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1262 smsc911x_reg_write(pdata, INT_EN, temp);
1263
1264 spin_lock_irq(&pdata->mac_lock);
1265 temp = smsc911x_mac_read(pdata, MAC_CR);
1266 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1267 smsc911x_mac_write(pdata, MAC_CR, temp);
1268 spin_unlock_irq(&pdata->mac_lock);
1269
1270 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1271
1272 netif_start_queue(dev);
1273 return 0;
1274}
1275
1276/* Entry point for stopping the interface */
1277static int smsc911x_stop(struct net_device *dev)
1278{
1279 struct smsc911x_data *pdata = netdev_priv(dev);
1280 unsigned int temp;
1281
fd9abb3d
SG		 1282 /* Disable all device interrupts */
1283 temp = smsc911x_reg_read(pdata, INT_CFG);
1284 temp &= ~INT_CFG_IRQ_EN_;
1285 smsc911x_reg_write(pdata, INT_CFG, temp);
1286
1287 /* Stop Tx and Rx polling */
1288 netif_stop_queue(dev);
1289 napi_disable(&pdata->napi);
1290
1291 /* At this point all Rx and Tx activity is stopped */
1292 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1293 smsc911x_tx_update_txcounters(dev);
1294
1295 /* Bring the PHY down */
dd045193
SG		 1296 if (pdata->phy_dev)
1297 phy_stop(pdata->phy_dev);
fd9abb3d
SG		 1298
1299 SMSC_TRACE(IFDOWN, "Interface stopped");
1300 return 0;
1301}
1302
1303/* Entry point for transmitting a packet */
1304static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1305{
1306 struct smsc911x_data *pdata = netdev_priv(dev);
1307 unsigned int freespace;
1308 unsigned int tx_cmd_a;
1309 unsigned int tx_cmd_b;
1310 unsigned int temp;
1311 u32 wrsz;
1312 ulong bufp;
1313
1314 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1315
1316 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
1317 SMSC_WARNING(TX_ERR,
1318 "Tx data fifo low, space available: %d", freespace);
1319
1320 /* Word alignment adjustment */
1321 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1322 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1323 tx_cmd_a |= (unsigned int)skb->len;
1324
1325 tx_cmd_b = ((unsigned int)skb->len) << 16;
1326 tx_cmd_b |= (unsigned int)skb->len;
1327
1328 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1329 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1330
1331 bufp = (ulong)skb->data & (~0x3);
1332 wrsz = (u32)skb->len + 3;
1333 wrsz += (u32)((ulong)skb->data & 0x3);
1334 wrsz >>= 2;
1335
1336 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
1337 freespace -= (skb->len + 32);
1338 dev_kfree_skb(skb);
1339 dev->trans_start = jiffies;
1340
1341 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1342 smsc911x_tx_update_txcounters(dev);
1343
1344 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1345 netif_stop_queue(dev);
1346 temp = smsc911x_reg_read(pdata, FIFO_INT);
1347 temp &= 0x00FFFFFF;
1348 temp |= 0x32000000;
1349 smsc911x_reg_write(pdata, FIFO_INT, temp);
1350 }
1351
1352 return NETDEV_TX_OK;
1353}
1354
1355/* Entry point for getting status counters */
1356static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1357{
1358 struct smsc911x_data *pdata = netdev_priv(dev);
1359 smsc911x_tx_update_txcounters(dev);
1360 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1361 return &dev->stats;
1362}
1363
1364/* Entry point for setting addressing modes */
1365static void smsc911x_set_multicast_list(struct net_device *dev)
1366{
1367 struct smsc911x_data *pdata = netdev_priv(dev);
1368 unsigned long flags;
1369
1370 if (dev->flags & IFF_PROMISC) {
1371 /* Enabling promiscuous mode */
1372 pdata->set_bits_mask = MAC_CR_PRMS_;
1373 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1374 pdata->hashhi = 0;
1375 pdata->hashlo = 0;
1376 } else if (dev->flags & IFF_ALLMULTI) {
1377 /* Enabling all multicast mode */
1378 pdata->set_bits_mask = MAC_CR_MCPAS_;
1379 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1380 pdata->hashhi = 0;
1381 pdata->hashlo = 0;
4cd24eaf 1382 } else if (!netdev_mc_empty(dev)) {
fd9abb3d
SG		 1383 /* Enabling specific multicast addresses */
1384 unsigned int hash_high = 0;
1385 unsigned int hash_low = 0;
2a0d18f9 1386 struct dev_mc_list *mc_list;
fd9abb3d
SG		 1387
1388 pdata->set_bits_mask = MAC_CR_HPFILT_;
1389 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1390
2a0d18f9
JP		 1391 netdev_for_each_mc_addr(mc_list, dev) {
1392 unsigned int bitnum = smsc911x_hash(mc_list->dmi_addr);
1393 unsigned int mask = 0x01 << (bitnum & 0x1F);
1394
1395 if (bitnum & 0x20)
1396 hash_high |= mask;
1397 else
1398 hash_low |= mask;
fd9abb3d 1399 }
fd9abb3d
SG		 1400
1401 pdata->hashhi = hash_high;
1402 pdata->hashlo = hash_low;
1403 } else {
1404 /* Enabling local MAC address only */
1405 pdata->set_bits_mask = 0;
1406 pdata->clear_bits_mask =
1407 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1408 pdata->hashhi = 0;
1409 pdata->hashlo = 0;
1410 }
1411
1412 spin_lock_irqsave(&pdata->mac_lock, flags);
1413
1414 if (pdata->generation <= 1) {
1415 /* Older hardware revision - cannot change these flags while
1416 * receiving data */
1417 if (!pdata->multicast_update_pending) {
1418 unsigned int temp;
1419 SMSC_TRACE(HW, "scheduling mcast update");
1420 pdata->multicast_update_pending = 1;
1421
1422 /* Request the hardware to stop, then perform the
1423 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1424 temp = smsc911x_mac_read(pdata, MAC_CR);
1425 temp &= ~(MAC_CR_RXEN_);
1426 smsc911x_mac_write(pdata, MAC_CR, temp);
1427 } else {
1428 /* There is another update pending, this should now
1429 * use the newer values */
1430 }
1431 } else {
1432 /* Newer hardware revision - can write immediately */
1433 smsc911x_rx_multicast_update(pdata);
1434 }
1435
1436 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1437}
1438
1439static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1440{
1441 struct net_device *dev = dev_id;
1442 struct smsc911x_data *pdata = netdev_priv(dev);
1443 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1444 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1445 int serviced = IRQ_NONE;
1446 u32 temp;
1447
1448 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1449 temp = smsc911x_reg_read(pdata, INT_EN);
1450 temp &= (~INT_EN_SW_INT_EN_);
1451 smsc911x_reg_write(pdata, INT_EN, temp);
1452 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1453 pdata->software_irq_signal = 1;
1454 smp_wmb();
1455 serviced = IRQ_HANDLED;
1456 }
1457
1458 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1459 /* Called when there is a multicast update scheduled and
1460 * it is now safe to complete the update */
1461 SMSC_TRACE(INTR, "RX Stop interrupt");
fd9abb3d 1462 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1463 if (pdata->multicast_update_pending)
1464 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1465 serviced = IRQ_HANDLED;
1466 }
1467
1468 if (intsts & inten & INT_STS_TDFA_) {
1469 temp = smsc911x_reg_read(pdata, FIFO_INT);
1470 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1471 smsc911x_reg_write(pdata, FIFO_INT, temp);
1472 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1473 netif_wake_queue(dev);
1474 serviced = IRQ_HANDLED;
1475 }
1476
1477 if (unlikely(intsts & inten & INT_STS_RXE_)) {
1478 SMSC_TRACE(INTR, "RX Error interrupt");
1479 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1480 serviced = IRQ_HANDLED;
1481 }
1482
1483 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1484 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1485 /* Disable Rx interrupts */
1486 temp = smsc911x_reg_read(pdata, INT_EN);
1487 temp &= (~INT_EN_RSFL_EN_);
1488 smsc911x_reg_write(pdata, INT_EN, temp);
1489 /* Schedule a NAPI poll */
288379f0 1490 __napi_schedule(&pdata->napi);
fd9abb3d
SG		 1491 } else {
1492 SMSC_WARNING(RX_ERR,
288379f0 1493 "napi_schedule_prep failed");
fd9abb3d
SG		 1494 }
1495 serviced = IRQ_HANDLED;
1496 }
1497
1498 return serviced;
1499}
1500
1501#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1502static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1503{
1504 disable_irq(dev->irq);
1505 smsc911x_irqhandler(0, dev);
1506 enable_irq(dev->irq);
1507}
1508#endif /* CONFIG_NET_POLL_CONTROLLER */
1509
225ddf49
SG		 1510static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1511{
1512 struct smsc911x_data *pdata = netdev_priv(dev);
1513 struct sockaddr *addr = p;
1514
1515 /* On older hardware revisions we cannot change the mac address
1516 * registers while receiving data. Newer devices can safely change
1517 * this at any time. */
1518 if (pdata->generation <= 1 && netif_running(dev))
1519 return -EBUSY;
1520
1521 if (!is_valid_ether_addr(addr->sa_data))
1522 return -EADDRNOTAVAIL;
1523
1524 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1525
1526 spin_lock_irq(&pdata->mac_lock);
1527 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1528 spin_unlock_irq(&pdata->mac_lock);
1529
1530 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1531
1532 return 0;
1533}
1534
fd9abb3d
SG		 1535/* Standard ioctls for mii-tool */
1536static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1537{
1538 struct smsc911x_data *pdata = netdev_priv(dev);
1539
1540 if (!netif_running(dev) || !pdata->phy_dev)
1541 return -EINVAL;
1542
1543 return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
1544}
1545
1546static int
1547smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1548{
1549 struct smsc911x_data *pdata = netdev_priv(dev);
1550
1551 cmd->maxtxpkt = 1;
1552 cmd->maxrxpkt = 1;
1553 return phy_ethtool_gset(pdata->phy_dev, cmd);
1554}
1555
1556static int
1557smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1558{
1559 struct smsc911x_data *pdata = netdev_priv(dev);
1560
1561 return phy_ethtool_sset(pdata->phy_dev, cmd);
1562}
1563
1564static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1565 struct ethtool_drvinfo *info)
1566{
1567 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1568 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1569 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1570 sizeof(info->bus_info));
1571}
1572
1573static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1574{
1575 struct smsc911x_data *pdata = netdev_priv(dev);
1576
1577 return phy_start_aneg(pdata->phy_dev);
1578}
1579
1580static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1581{
1582 struct smsc911x_data *pdata = netdev_priv(dev);
1583 return pdata->msg_enable;
1584}
1585
1586static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1587{
1588 struct smsc911x_data *pdata = netdev_priv(dev);
1589 pdata->msg_enable = level;
1590}
1591
1592static int smsc911x_ethtool_getregslen(struct net_device *dev)
1593{
1594 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1595 sizeof(u32);
1596}
1597
1598static void
1599smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1600 void *buf)
1601{
1602 struct smsc911x_data *pdata = netdev_priv(dev);
1603 struct phy_device *phy_dev = pdata->phy_dev;
1604 unsigned long flags;
1605 unsigned int i;
1606 unsigned int j = 0;
1607 u32 *data = buf;
1608
1609 regs->version = pdata->idrev;
1610 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1611 data[j++] = smsc911x_reg_read(pdata, i);
1612
1613 for (i = MAC_CR; i <= WUCSR; i++) {
1614 spin_lock_irqsave(&pdata->mac_lock, flags);
1615 data[j++] = smsc911x_mac_read(pdata, i);
1616 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1617 }
1618
1619 for (i = 0; i <= 31; i++)
1620 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1621}
1622
1623static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1624{
1625 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1626 temp &= ~GPIO_CFG_EEPR_EN_;
1627 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1628 msleep(1);
1629}
1630
1631static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1632{
1633 int timeout = 100;
1634 u32 e2cmd;
1635
1636 SMSC_TRACE(DRV, "op 0x%08x", op);
1637 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
1638 SMSC_WARNING(DRV, "Busy at start");
1639 return -EBUSY;
1640 }
1641
1642 e2cmd = op | E2P_CMD_EPC_BUSY_;
1643 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1644
1645 do {
1646 msleep(1);
1647 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1648 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1649
1650 if (!timeout) {
1651 SMSC_TRACE(DRV, "TIMED OUT");
1652 return -EAGAIN;
1653 }
1654
1655 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1656 SMSC_TRACE(DRV, "Error occured during eeprom operation");
1657 return -EINVAL;
1658 }
1659
1660 return 0;
1661}
1662
1663static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1664 u8 address, u8 *data)
1665{
1666 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1667 int ret;
1668
1669 SMSC_TRACE(DRV, "address 0x%x", address);
1670 ret = smsc911x_eeprom_send_cmd(pdata, op);
1671
1672 if (!ret)
1673 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1674
1675 return ret;
1676}
1677
1678static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1679 u8 address, u8 data)
1680{
1681 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 1682 u32 temp;
fd9abb3d
SG		 1683 int ret;
1684
1685 SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
1686 ret = smsc911x_eeprom_send_cmd(pdata, op);
1687
1688 if (!ret) {
1689 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1690 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 1691
1692 /* Workaround for hardware read-after-write restriction */
1693 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1694
fd9abb3d
SG		 1695 ret = smsc911x_eeprom_send_cmd(pdata, op);
1696 }
1697
1698 return ret;
1699}
1700
1701static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1702{
1703 return SMSC911X_EEPROM_SIZE;
1704}
1705
1706static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1707 struct ethtool_eeprom *eeprom, u8 *data)
1708{
1709 struct smsc911x_data *pdata = netdev_priv(dev);
1710 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1711 int len;
1712 int i;
1713
1714 smsc911x_eeprom_enable_access(pdata);
1715
1716 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1717 for (i = 0; i < len; i++) {
1718 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1719 if (ret < 0) {
1720 eeprom->len = 0;
1721 return ret;
1722 }
1723 }
1724
1725 memcpy(data, &eeprom_data[eeprom->offset], len);
1726 eeprom->len = len;
1727 return 0;
1728}
1729
1730static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1731 struct ethtool_eeprom *eeprom, u8 *data)
1732{
1733 int ret;
1734 struct smsc911x_data *pdata = netdev_priv(dev);
1735
1736 smsc911x_eeprom_enable_access(pdata);
1737 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1738 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1739 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1740
1741 /* Single byte write, according to man page */
1742 eeprom->len = 1;
1743
1744 return ret;
1745}
1746
cb5b04fe 1747static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 1748 .get_settings = smsc911x_ethtool_getsettings,
1749 .set_settings = smsc911x_ethtool_setsettings,
1750 .get_link = ethtool_op_get_link,
1751 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1752 .nway_reset = smsc911x_ethtool_nwayreset,
1753 .get_msglevel = smsc911x_ethtool_getmsglevel,
1754 .set_msglevel = smsc911x_ethtool_setmsglevel,
1755 .get_regs_len = smsc911x_ethtool_getregslen,
1756 .get_regs = smsc911x_ethtool_getregs,
1757 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1758 .get_eeprom = smsc911x_ethtool_get_eeprom,
1759 .set_eeprom = smsc911x_ethtool_set_eeprom,
1760};
1761
631b7568
SG		 1762static const struct net_device_ops smsc911x_netdev_ops = {
1763 .ndo_open = smsc911x_open,
1764 .ndo_stop = smsc911x_stop,
1765 .ndo_start_xmit = smsc911x_hard_start_xmit,
1766 .ndo_get_stats = smsc911x_get_stats,
1767 .ndo_set_multicast_list = smsc911x_set_multicast_list,
1768 .ndo_do_ioctl = smsc911x_do_ioctl,
635ecaa7 1769 .ndo_change_mtu = eth_change_mtu,
631b7568 1770 .ndo_validate_addr = eth_validate_addr,
225ddf49 1771 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 1772#ifdef CONFIG_NET_POLL_CONTROLLER
1773 .ndo_poll_controller = smsc911x_poll_controller,
1774#endif
1775};
1776
31f45747
SG		 1777/* copies the current mac address from hardware to dev->dev_addr */
1778static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1779{
1780 struct smsc911x_data *pdata = netdev_priv(dev);
1781 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1782 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1783
1784 dev->dev_addr[0] = (u8)(mac_low32);
1785 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1786 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1787 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1788 dev->dev_addr[4] = (u8)(mac_high16);
1789 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1790}
1791
fd9abb3d
SG		 1792/* Initializing private device structures, only called from probe */
1793static int __devinit smsc911x_init(struct net_device *dev)
1794{
1795 struct smsc911x_data *pdata = netdev_priv(dev);
1796 unsigned int byte_test;
1797
1798 SMSC_TRACE(PROBE, "Driver Parameters:");
1799 SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
1800 (unsigned long)pdata->ioaddr);
1801 SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
1802 SMSC_TRACE(PROBE, "PHY will be autodetected.");
1803
fd9abb3d 1804 spin_lock_init(&pdata->dev_lock);
fd9abb3d
SG		 1805
1806 if (pdata->ioaddr == 0) {
1807 SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
1808 return -ENODEV;
1809 }
1810
1811 /* Check byte ordering */
1812 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1813 SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
1814 if (byte_test == 0x43218765) {
1815 SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
1816 "applying WORD_SWAP");
1817 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1818
1819 /* 1 dummy read of BYTE_TEST is needed after a write to
1820 * WORD_SWAP before its contents are valid */
1821 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1822
1823 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1824 }
1825
1826 if (byte_test != 0x87654321) {
1827 SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
1828 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
1829 SMSC_WARNING(PROBE,
1830 "top 16 bits equal to bottom 16 bits");
1831 SMSC_TRACE(PROBE, "This may mean the chip is set "
1832 "for 32 bit while the bus is reading 16 bit");
1833 }
1834 return -ENODEV;
1835 }
1836
1837 /* Default generation to zero (all workarounds apply) */
1838 pdata->generation = 0;
1839
1840 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1841 switch (pdata->idrev & 0xFFFF0000) {
1842 case 0x01180000:
1843 case 0x01170000:
1844 case 0x01160000:
1845 case 0x01150000:
1846 /* LAN911[5678] family */
1847 pdata->generation = pdata->idrev & 0x0000FFFF;
1848 break;
1849
1850 case 0x118A0000:
1851 case 0x117A0000:
1852 case 0x116A0000:
1853 case 0x115A0000:
1854 /* LAN921[5678] family */
1855 pdata->generation = 3;
1856 break;
1857
1858 case 0x92100000:
1859 case 0x92110000:
1860 case 0x92200000:
1861 case 0x92210000:
1862 /* LAN9210/LAN9211/LAN9220/LAN9221 */
1863 pdata->generation = 4;
1864 break;
1865
1866 default:
1867 SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
1868 pdata->idrev);
1869 return -ENODEV;
1870 }
1871
1872 SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
1873 pdata->idrev, pdata->generation);
1874
1875 if (pdata->generation == 0)
1876 SMSC_WARNING(PROBE,
1877 "This driver is not intended for this chip revision");
1878
31f45747
SG		 1879 /* workaround for platforms without an eeprom, where the mac address
1880 * is stored elsewhere and set by the bootloader. This saves the
1881 * mac address before resetting the device */
1882 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS)
1883 smsc911x_read_mac_address(dev);
1884
fd9abb3d
SG		 1885 /* Reset the LAN911x */
1886 if (smsc911x_soft_reset(pdata))
1887 return -ENODEV;
1888
1889 /* Disable all interrupt sources until we bring the device up */
1890 smsc911x_reg_write(pdata, INT_EN, 0);
1891
1892 ether_setup(dev);
fd9abb3d 1893 dev->flags |= IFF_MULTICAST;
fd9abb3d 1894 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 1895 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 1896 dev->ethtool_ops = &smsc911x_ethtool_ops;
1897
fd9abb3d
SG		 1898 return 0;
1899}
1900
1901static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
1902{
1903 struct net_device *dev;
1904 struct smsc911x_data *pdata;
1905 struct resource *res;
1906
1907 dev = platform_get_drvdata(pdev);
1908 BUG_ON(!dev);
1909 pdata = netdev_priv(dev);
1910 BUG_ON(!pdata);
1911 BUG_ON(!pdata->ioaddr);
1912 BUG_ON(!pdata->phy_dev);
1913
1914 SMSC_TRACE(IFDOWN, "Stopping driver.");
1915
1916 phy_disconnect(pdata->phy_dev);
1917 pdata->phy_dev = NULL;
1918 mdiobus_unregister(pdata->mii_bus);
1919 mdiobus_free(pdata->mii_bus);
1920
1921 platform_set_drvdata(pdev, NULL);
1922 unregister_netdev(dev);
1923 free_irq(dev->irq, dev);
1924 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1925 "smsc911x-memory");
1926 if (!res)
d4522739 1927 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d 1928
39424539 1929 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 1930
1931 iounmap(pdata->ioaddr);
1932
1933 free_netdev(dev);
1934
1935 return 0;
1936}
1937
1938static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
1939{
1940 struct net_device *dev;
1941 struct smsc911x_data *pdata;
2107fb8b 1942 struct smsc911x_platform_config *config = pdev->dev.platform_data;
61307ed8 1943 struct resource *res, *irq_res;
fd9abb3d 1944 unsigned int intcfg = 0;
61307ed8 1945 int res_size, irq_flags;
fd9abb3d 1946 int retval;
fd9abb3d
SG		 1947
1948 pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
1949
2107fb8b
SG		 1950 /* platform data specifies irq & dynamic bus configuration */
1951 if (!pdev->dev.platform_data) {
1952 pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
1953 retval = -ENODEV;
1954 goto out_0;
1955 }
1956
fd9abb3d
SG		 1957 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1958 "smsc911x-memory");
1959 if (!res)
1960 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1961 if (!res) {
1962 pr_warning("%s: Could not allocate resource.\n",
1963 SMSC_CHIPNAME);
1964 retval = -ENODEV;
1965 goto out_0;
1966 }
39424539 1967 res_size = resource_size(res);
fd9abb3d 1968
61307ed8
SG		 1969 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1970 if (!irq_res) {
1971 pr_warning("%s: Could not allocate irq resource.\n",
1972 SMSC_CHIPNAME);
1973 retval = -ENODEV;
1974 goto out_0;
1975 }
1976
fd9abb3d
SG		 1977 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
1978 retval = -EBUSY;
1979 goto out_0;
1980 }
1981
1982 dev = alloc_etherdev(sizeof(struct smsc911x_data));
1983 if (!dev) {
1984 pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
1985 retval = -ENOMEM;
1986 goto out_release_io_1;
1987 }
1988
1989 SET_NETDEV_DEV(dev, &pdev->dev);
1990
1991 pdata = netdev_priv(dev);
1992
61307ed8
SG		 1993 dev->irq = irq_res->start;
1994 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 1995 pdata->ioaddr = ioremap_nocache(res->start, res_size);
1996
2107fb8b
SG		 1997 /* copy config parameters across to pdata */
1998 memcpy(&pdata->config, config, sizeof(pdata->config));
fd9abb3d
SG		 1999
2000 pdata->dev = dev;
2001 pdata->msg_enable = ((1 << debug) - 1);
2002
2003 if (pdata->ioaddr == NULL) {
2004 SMSC_WARNING(PROBE,
2005 "Error smsc911x base address invalid");
2006 retval = -ENOMEM;
2007 goto out_free_netdev_2;
2008 }
2009
2010 retval = smsc911x_init(dev);
2011 if (retval < 0)
2012 goto out_unmap_io_3;
2013
2014 /* configure irq polarity and type before connecting isr */
2107fb8b 2015 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2016 intcfg |= INT_CFG_IRQ_POL_;
2017
2107fb8b 2018 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2019 intcfg |= INT_CFG_IRQ_TYPE_;
2020
2021 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2022
2023 /* Ensure interrupts are globally disabled before connecting ISR */
2024 smsc911x_reg_write(pdata, INT_EN, 0);
2025 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2026
61307ed8 2027 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2028 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d
SG		 2029 if (retval) {
2030 SMSC_WARNING(PROBE,
2031 "Unable to claim requested irq: %d", dev->irq);
2032 goto out_unmap_io_3;
2033 }
2034
2035 platform_set_drvdata(pdev, dev);
2036
2037 retval = register_netdev(dev);
2038 if (retval) {
2039 SMSC_WARNING(PROBE,
2040 "Error %i registering device", retval);
2041 goto out_unset_drvdata_4;
2042 } else {
2043 SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
2044 }
2045
2046 spin_lock_init(&pdata->mac_lock);
2047
2048 retval = smsc911x_mii_init(pdev, dev);
2049 if (retval) {
2050 SMSC_WARNING(PROBE,
2051 "Error %i initialising mii", retval);
2052 goto out_unregister_netdev_5;
2053 }
2054
2055 spin_lock_irq(&pdata->mac_lock);
2056
2057 /* Check if mac address has been specified when bringing interface up */
2058 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2059 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d 2060 SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
aace4959
ML		 2061 } else if (is_valid_ether_addr(pdata->config.mac)) {
2062 memcpy(dev->dev_addr, pdata->config.mac, 6);
2063 SMSC_TRACE(PROBE, "MAC Address specified by platform data");
fd9abb3d
SG		 2064 } else {
2065 /* Try reading mac address from device. if EEPROM is present
2066 * it will already have been set */
31f45747 2067 smsc911x_read_mac_address(dev);
fd9abb3d
SG		 2068
2069 if (is_valid_ether_addr(dev->dev_addr)) {
2070 /* eeprom values are valid so use them */
2071 SMSC_TRACE(PROBE,
2072 "Mac Address is read from LAN911x EEPROM");
2073 } else {
2074 /* eeprom values are invalid, generate random MAC */
2075 random_ether_addr(dev->dev_addr);
225ddf49 2076 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 2077 SMSC_TRACE(PROBE,
2078 "MAC Address is set to random_ether_addr");
2079 }
2080 }
2081
2082 spin_unlock_irq(&pdata->mac_lock);
2083
63a2ebb0 2084 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2085
2086 return 0;
2087
2088out_unregister_netdev_5:
2089 unregister_netdev(dev);
2090out_unset_drvdata_4:
2091 platform_set_drvdata(pdev, NULL);
2092 free_irq(dev->irq, dev);
2093out_unmap_io_3:
2094 iounmap(pdata->ioaddr);
2095out_free_netdev_2:
2096 free_netdev(dev);
2097out_release_io_1:
39424539 2098 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2099out_0:
2100 return retval;
2101}
2102
b6907b0c
DM		 2103#ifdef CONFIG_PM
2104/* This implementation assumes the devices remains powered on its VDDVARIO
2105 * pins during suspend. */
2106
6cb87823
DM		 2107/* TODO: implement freeze/thaw callbacks for hibernation.*/
2108
2109static int smsc911x_suspend(struct device *dev)
b6907b0c 2110{
6cb87823
DM		 2111 struct net_device *ndev = dev_get_drvdata(dev);
2112 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2113
2114 /* enable wake on LAN, energy detection and the external PME
2115 * signal. */
2116 smsc911x_reg_write(pdata, PMT_CTRL,
2117 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2118 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2119
2120 return 0;
2121}
2122
6cb87823 2123static int smsc911x_resume(struct device *dev)
b6907b0c 2124{
6cb87823
DM		 2125 struct net_device *ndev = dev_get_drvdata(dev);
2126 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2127 unsigned int to = 100;
2128
2129 /* Note 3.11 from the datasheet:
2130 * "When the LAN9220 is in a power saving state, a write of any
2131 * data to the BYTE_TEST register will wake-up the device."
2132 */
2133 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2134
2135 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2136 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2137 * if it failed. */
2138 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2139 udelay(1000);
2140
2141 return (to == 0) ? -EIO : 0;
2142}
2143
47145210 2144static const struct dev_pm_ops smsc911x_pm_ops = {
6cb87823
DM		 2145 .suspend = smsc911x_suspend,
2146 .resume = smsc911x_resume,
2147};
2148
2149#define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2150
b6907b0c 2151#else
6cb87823 2152#define SMSC911X_PM_OPS NULL
b6907b0c
DM		 2153#endif
2154
fd9abb3d
SG		 2155static struct platform_driver smsc911x_driver = {
2156 .probe = smsc911x_drv_probe,
df911e2d 2157 .remove = __devexit_p(smsc911x_drv_remove),
fd9abb3d 2158 .driver = {
6cb87823
DM		 2159 .name = SMSC_CHIPNAME,
2160 .owner = THIS_MODULE,
2161 .pm = SMSC911X_PM_OPS,
fd9abb3d
SG		 2162 },
2163};
2164
2165/* Entry point for loading the module */
2166static int __init smsc911x_init_module(void)
2167{
2168 return platform_driver_register(&smsc911x_driver);
2169}
2170
2171/* entry point for unloading the module */
2172static void __exit smsc911x_cleanup_module(void)
2173{
2174 platform_driver_unregister(&smsc911x_driver);
2175}
2176
2177module_init(smsc911x_init_module);
2178module_exit(smsc911x_cleanup_module);
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