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fd9abb3d SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2004-2008 SMSC | |
4 | * Copyright (C) 2005-2008 ARM | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | * | |
20 | *************************************************************************** | |
21 | * Rewritten, heavily based on smsc911x simple driver by SMSC. | |
22 | * Partly uses io macros from smc91x.c by Nicolas Pitre | |
23 | * | |
24 | * Supported devices: | |
25 | * LAN9115, LAN9116, LAN9117, LAN9118 | |
26 | * LAN9215, LAN9216, LAN9217, LAN9218 | |
27 | * LAN9210, LAN9211 | |
28 | * LAN9220, LAN9221 | |
29 | * | |
30 | */ | |
31 | ||
dffc6b24 JP |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
fd9abb3d SG |
34 | #include <linux/crc32.h> |
35 | #include <linux/delay.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/etherdevice.h> | |
38 | #include <linux/ethtool.h> | |
39 | #include <linux/init.h> | |
a6b7a407 | 40 | #include <linux/interrupt.h> |
fd9abb3d SG |
41 | #include <linux/ioport.h> |
42 | #include <linux/kernel.h> | |
43 | #include <linux/module.h> | |
44 | #include <linux/netdevice.h> | |
45 | #include <linux/platform_device.h> | |
46 | #include <linux/sched.h> | |
fd9abb3d | 47 | #include <linux/timer.h> |
fd9abb3d SG |
48 | #include <linux/bug.h> |
49 | #include <linux/bitops.h> | |
50 | #include <linux/irq.h> | |
51 | #include <linux/io.h> | |
833cc67c | 52 | #include <linux/swab.h> |
fd9abb3d SG |
53 | #include <linux/phy.h> |
54 | #include <linux/smsc911x.h> | |
6cb87823 | 55 | #include <linux/device.h> |
fd9abb3d SG |
56 | #include "smsc911x.h" |
57 | ||
58 | #define SMSC_CHIPNAME "smsc911x" | |
59 | #define SMSC_MDIONAME "smsc911x-mdio" | |
60 | #define SMSC_DRV_VERSION "2008-10-21" | |
61 | ||
62 | MODULE_LICENSE("GPL"); | |
63 | MODULE_VERSION(SMSC_DRV_VERSION); | |
62038e4a | 64 | MODULE_ALIAS("platform:smsc911x"); |
fd9abb3d SG |
65 | |
66 | #if USE_DEBUG > 0 | |
67 | static int debug = 16; | |
68 | #else | |
69 | static int debug = 3; | |
70 | #endif | |
71 | ||
72 | module_param(debug, int, 0); | |
73 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
74 | ||
c326de88 MP |
75 | struct smsc911x_data; |
76 | ||
77 | struct smsc911x_ops { | |
78 | u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg); | |
79 | void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val); | |
80 | void (*rx_readfifo)(struct smsc911x_data *pdata, | |
81 | unsigned int *buf, unsigned int wordcount); | |
82 | void (*tx_writefifo)(struct smsc911x_data *pdata, | |
83 | unsigned int *buf, unsigned int wordcount); | |
84 | }; | |
85 | ||
fd9abb3d SG |
86 | struct smsc911x_data { |
87 | void __iomem *ioaddr; | |
88 | ||
89 | unsigned int idrev; | |
90 | ||
91 | /* used to decide which workarounds apply */ | |
92 | unsigned int generation; | |
93 | ||
94 | /* device configuration (copied from platform_data during probe) */ | |
2107fb8b | 95 | struct smsc911x_platform_config config; |
fd9abb3d SG |
96 | |
97 | /* This needs to be acquired before calling any of below: | |
98 | * smsc911x_mac_read(), smsc911x_mac_write() | |
99 | */ | |
100 | spinlock_t mac_lock; | |
101 | ||
492c5d94 | 102 | /* spinlock to ensure register accesses are serialised */ |
fd9abb3d | 103 | spinlock_t dev_lock; |
fd9abb3d SG |
104 | |
105 | struct phy_device *phy_dev; | |
106 | struct mii_bus *mii_bus; | |
107 | int phy_irq[PHY_MAX_ADDR]; | |
108 | unsigned int using_extphy; | |
109 | int last_duplex; | |
110 | int last_carrier; | |
111 | ||
112 | u32 msg_enable; | |
113 | unsigned int gpio_setting; | |
114 | unsigned int gpio_orig_setting; | |
115 | struct net_device *dev; | |
116 | struct napi_struct napi; | |
117 | ||
118 | unsigned int software_irq_signal; | |
119 | ||
120 | #ifdef USE_PHY_WORK_AROUND | |
121 | #define MIN_PACKET_SIZE (64) | |
122 | char loopback_tx_pkt[MIN_PACKET_SIZE]; | |
123 | char loopback_rx_pkt[MIN_PACKET_SIZE]; | |
124 | unsigned int resetcount; | |
125 | #endif | |
126 | ||
127 | /* Members for Multicast filter workaround */ | |
128 | unsigned int multicast_update_pending; | |
129 | unsigned int set_bits_mask; | |
130 | unsigned int clear_bits_mask; | |
131 | unsigned int hashhi; | |
132 | unsigned int hashlo; | |
c326de88 MP |
133 | |
134 | /* register access functions */ | |
135 | const struct smsc911x_ops *ops; | |
fd9abb3d SG |
136 | }; |
137 | ||
c326de88 MP |
138 | /* Easy access to information */ |
139 | #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift)) | |
140 | ||
492c5d94 | 141 | static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
fd9abb3d | 142 | { |
2107fb8b SG |
143 | if (pdata->config.flags & SMSC911X_USE_32BIT) |
144 | return readl(pdata->ioaddr + reg); | |
145 | ||
492c5d94 CM |
146 | if (pdata->config.flags & SMSC911X_USE_16BIT) |
147 | return ((readw(pdata->ioaddr + reg) & 0xFFFF) | | |
2107fb8b | 148 | ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16)); |
fd9abb3d | 149 | |
2107fb8b | 150 | BUG(); |
702403af | 151 | return 0; |
fd9abb3d SG |
152 | } |
153 | ||
c326de88 MP |
154 | static inline u32 |
155 | __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg) | |
156 | { | |
157 | if (pdata->config.flags & SMSC911X_USE_32BIT) | |
158 | return readl(pdata->ioaddr + __smsc_shift(pdata, reg)); | |
159 | ||
160 | if (pdata->config.flags & SMSC911X_USE_16BIT) | |
161 | return (readw(pdata->ioaddr + | |
162 | __smsc_shift(pdata, reg)) & 0xFFFF) | | |
163 | ((readw(pdata->ioaddr + | |
164 | __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16); | |
165 | ||
166 | BUG(); | |
167 | return 0; | |
168 | } | |
169 | ||
492c5d94 CM |
170 | static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
171 | { | |
172 | u32 data; | |
173 | unsigned long flags; | |
174 | ||
175 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 176 | data = pdata->ops->reg_read(pdata, reg); |
492c5d94 CM |
177 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
178 | ||
179 | return data; | |
180 | } | |
181 | ||
182 | static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, | |
183 | u32 val) | |
fd9abb3d | 184 | { |
2107fb8b SG |
185 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
186 | writel(val, pdata->ioaddr + reg); | |
187 | return; | |
188 | } | |
189 | ||
190 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
2107fb8b SG |
191 | writew(val & 0xFFFF, pdata->ioaddr + reg); |
192 | writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2); | |
2107fb8b SG |
193 | return; |
194 | } | |
fd9abb3d | 195 | |
2107fb8b | 196 | BUG(); |
fd9abb3d SG |
197 | } |
198 | ||
c326de88 MP |
199 | static inline void |
200 | __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val) | |
201 | { | |
202 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
203 | writel(val, pdata->ioaddr + __smsc_shift(pdata, reg)); | |
204 | return; | |
205 | } | |
206 | ||
207 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
208 | writew(val & 0xFFFF, | |
209 | pdata->ioaddr + __smsc_shift(pdata, reg)); | |
210 | writew((val >> 16) & 0xFFFF, | |
211 | pdata->ioaddr + __smsc_shift(pdata, reg + 2)); | |
212 | return; | |
213 | } | |
214 | ||
215 | BUG(); | |
216 | } | |
217 | ||
492c5d94 CM |
218 | static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, |
219 | u32 val) | |
220 | { | |
221 | unsigned long flags; | |
222 | ||
223 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 224 | pdata->ops->reg_write(pdata, reg, val); |
492c5d94 CM |
225 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
226 | } | |
227 | ||
fd9abb3d SG |
228 | /* Writes a packet to the TX_DATA_FIFO */ |
229 | static inline void | |
230 | smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf, | |
231 | unsigned int wordcount) | |
232 | { | |
492c5d94 CM |
233 | unsigned long flags; |
234 | ||
235 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
236 | ||
833cc67c MD |
237 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
238 | while (wordcount--) | |
492c5d94 CM |
239 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, |
240 | swab32(*buf++)); | |
241 | goto out; | |
833cc67c MD |
242 | } |
243 | ||
2107fb8b SG |
244 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
245 | writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount); | |
492c5d94 | 246 | goto out; |
2107fb8b SG |
247 | } |
248 | ||
249 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
250 | while (wordcount--) | |
492c5d94 CM |
251 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++); |
252 | goto out; | |
2107fb8b SG |
253 | } |
254 | ||
255 | BUG(); | |
492c5d94 CM |
256 | out: |
257 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
fd9abb3d SG |
258 | } |
259 | ||
c326de88 MP |
260 | /* Writes a packet to the TX_DATA_FIFO - shifted version */ |
261 | static inline void | |
262 | smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
263 | unsigned int wordcount) | |
264 | { | |
265 | unsigned long flags; | |
266 | ||
267 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
268 | ||
269 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
270 | while (wordcount--) | |
271 | __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO, | |
272 | swab32(*buf++)); | |
273 | goto out; | |
274 | } | |
275 | ||
276 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
277 | writesl(pdata->ioaddr + __smsc_shift(pdata, | |
278 | TX_DATA_FIFO), buf, wordcount); | |
279 | goto out; | |
280 | } | |
281 | ||
282 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
283 | while (wordcount--) | |
284 | __smsc911x_reg_write_shift(pdata, | |
285 | TX_DATA_FIFO, *buf++); | |
286 | goto out; | |
287 | } | |
288 | ||
289 | BUG(); | |
290 | out: | |
291 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
292 | } | |
293 | ||
fd9abb3d SG |
294 | /* Reads a packet out of the RX_DATA_FIFO */ |
295 | static inline void | |
296 | smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf, | |
297 | unsigned int wordcount) | |
298 | { | |
492c5d94 CM |
299 | unsigned long flags; |
300 | ||
301 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
302 | ||
833cc67c MD |
303 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
304 | while (wordcount--) | |
492c5d94 CM |
305 | *buf++ = swab32(__smsc911x_reg_read(pdata, |
306 | RX_DATA_FIFO)); | |
307 | goto out; | |
833cc67c MD |
308 | } |
309 | ||
2107fb8b SG |
310 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
311 | readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount); | |
492c5d94 | 312 | goto out; |
2107fb8b | 313 | } |
fd9abb3d | 314 | |
2107fb8b SG |
315 | if (pdata->config.flags & SMSC911X_USE_16BIT) { |
316 | while (wordcount--) | |
492c5d94 CM |
317 | *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO); |
318 | goto out; | |
2107fb8b SG |
319 | } |
320 | ||
321 | BUG(); | |
492c5d94 CM |
322 | out: |
323 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
2107fb8b | 324 | } |
fd9abb3d | 325 | |
c326de88 MP |
326 | /* Reads a packet out of the RX_DATA_FIFO - shifted version */ |
327 | static inline void | |
328 | smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
329 | unsigned int wordcount) | |
330 | { | |
331 | unsigned long flags; | |
332 | ||
333 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
334 | ||
335 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
336 | while (wordcount--) | |
337 | *buf++ = swab32(__smsc911x_reg_read_shift(pdata, | |
338 | RX_DATA_FIFO)); | |
339 | goto out; | |
340 | } | |
341 | ||
342 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
343 | readsl(pdata->ioaddr + __smsc_shift(pdata, | |
344 | RX_DATA_FIFO), buf, wordcount); | |
345 | goto out; | |
346 | } | |
347 | ||
348 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
349 | while (wordcount--) | |
350 | *buf++ = __smsc911x_reg_read_shift(pdata, | |
351 | RX_DATA_FIFO); | |
352 | goto out; | |
353 | } | |
354 | ||
355 | BUG(); | |
356 | out: | |
357 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
358 | } | |
359 | ||
fd9abb3d SG |
360 | /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read |
361 | * and smsc911x_mac_write, so assumes mac_lock is held */ | |
362 | static int smsc911x_mac_complete(struct smsc911x_data *pdata) | |
363 | { | |
364 | int i; | |
365 | u32 val; | |
366 | ||
367 | SMSC_ASSERT_MAC_LOCK(pdata); | |
368 | ||
369 | for (i = 0; i < 40; i++) { | |
370 | val = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
371 | if (!(val & MAC_CSR_CMD_CSR_BUSY_)) | |
372 | return 0; | |
373 | } | |
dffc6b24 JP |
374 | SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. " |
375 | "MAC_CSR_CMD: 0x%08X", val); | |
fd9abb3d SG |
376 | return -EIO; |
377 | } | |
378 | ||
379 | /* Fetches a MAC register value. Assumes mac_lock is acquired */ | |
380 | static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset) | |
381 | { | |
382 | unsigned int temp; | |
383 | ||
384 | SMSC_ASSERT_MAC_LOCK(pdata); | |
385 | ||
386 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
387 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 | 388 | SMSC_WARN(pdata, hw, "MAC busy at entry"); |
fd9abb3d SG |
389 | return 0xFFFFFFFF; |
390 | } | |
391 | ||
392 | /* Send the MAC cmd */ | |
393 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
394 | MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_)); | |
395 | ||
396 | /* Workaround for hardware read-after-write restriction */ | |
397 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
398 | ||
399 | /* Wait for the read to complete */ | |
400 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
401 | return smsc911x_reg_read(pdata, MAC_CSR_DATA); | |
402 | ||
dffc6b24 | 403 | SMSC_WARN(pdata, hw, "MAC busy after read"); |
fd9abb3d SG |
404 | return 0xFFFFFFFF; |
405 | } | |
406 | ||
407 | /* Set a mac register, mac_lock must be acquired before calling */ | |
408 | static void smsc911x_mac_write(struct smsc911x_data *pdata, | |
409 | unsigned int offset, u32 val) | |
410 | { | |
411 | unsigned int temp; | |
412 | ||
413 | SMSC_ASSERT_MAC_LOCK(pdata); | |
414 | ||
415 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
416 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 JP |
417 | SMSC_WARN(pdata, hw, |
418 | "smsc911x_mac_write failed, MAC busy at entry"); | |
fd9abb3d SG |
419 | return; |
420 | } | |
421 | ||
422 | /* Send data to write */ | |
423 | smsc911x_reg_write(pdata, MAC_CSR_DATA, val); | |
424 | ||
425 | /* Write the actual data */ | |
426 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
427 | MAC_CSR_CMD_CSR_BUSY_)); | |
428 | ||
429 | /* Workaround for hardware read-after-write restriction */ | |
430 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
431 | ||
432 | /* Wait for the write to complete */ | |
433 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
434 | return; | |
435 | ||
dffc6b24 | 436 | SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write"); |
fd9abb3d SG |
437 | } |
438 | ||
439 | /* Get a phy register */ | |
440 | static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx) | |
441 | { | |
442 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
443 | unsigned long flags; | |
444 | unsigned int addr; | |
445 | int i, reg; | |
446 | ||
447 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
448 | ||
449 | /* Confirm MII not busy */ | |
450 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 451 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???"); |
fd9abb3d SG |
452 | reg = -EIO; |
453 | goto out; | |
454 | } | |
455 | ||
456 | /* Set the address, index & direction (read from PHY) */ | |
457 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6); | |
458 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
459 | ||
460 | /* Wait for read to complete w/ timeout */ | |
461 | for (i = 0; i < 100; i++) | |
462 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
463 | reg = smsc911x_mac_read(pdata, MII_DATA); | |
464 | goto out; | |
465 | } | |
466 | ||
dffc6b24 | 467 | SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish"); |
fd9abb3d SG |
468 | reg = -EIO; |
469 | ||
470 | out: | |
471 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
472 | return reg; | |
473 | } | |
474 | ||
475 | /* Set a phy register */ | |
476 | static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | |
477 | u16 val) | |
478 | { | |
479 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
480 | unsigned long flags; | |
481 | unsigned int addr; | |
482 | int i, reg; | |
483 | ||
484 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
485 | ||
486 | /* Confirm MII not busy */ | |
487 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 488 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???"); |
fd9abb3d SG |
489 | reg = -EIO; |
490 | goto out; | |
491 | } | |
492 | ||
493 | /* Put the data to write in the MAC */ | |
494 | smsc911x_mac_write(pdata, MII_DATA, val); | |
495 | ||
496 | /* Set the address, index & direction (write to PHY) */ | |
497 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | | |
498 | MII_ACC_MII_WRITE_; | |
499 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
500 | ||
501 | /* Wait for write to complete w/ timeout */ | |
502 | for (i = 0; i < 100; i++) | |
503 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
504 | reg = 0; | |
505 | goto out; | |
506 | } | |
507 | ||
dffc6b24 | 508 | SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish"); |
fd9abb3d SG |
509 | reg = -EIO; |
510 | ||
511 | out: | |
512 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
513 | return reg; | |
514 | } | |
515 | ||
d23f028a SG |
516 | /* Switch to external phy. Assumes tx and rx are stopped. */ |
517 | static void smsc911x_phy_enable_external(struct smsc911x_data *pdata) | |
fd9abb3d SG |
518 | { |
519 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
520 | ||
d23f028a SG |
521 | /* Disable phy clocks to the MAC */ |
522 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
523 | hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; | |
524 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
525 | udelay(10); /* Enough time for clocks to stop */ | |
fd9abb3d | 526 | |
d23f028a SG |
527 | /* Switch to external phy */ |
528 | hwcfg |= HW_CFG_EXT_PHY_EN_; | |
529 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
fd9abb3d | 530 | |
d23f028a SG |
531 | /* Enable phy clocks to the MAC */ |
532 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
533 | hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_; | |
534 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
535 | udelay(10); /* Enough time for clocks to restart */ | |
fd9abb3d | 536 | |
d23f028a SG |
537 | hwcfg |= HW_CFG_SMI_SEL_; |
538 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
539 | } | |
fd9abb3d | 540 | |
d23f028a SG |
541 | /* Autodetects and enables external phy if present on supported chips. |
542 | * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY | |
543 | * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */ | |
544 | static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata) | |
545 | { | |
546 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
fd9abb3d | 547 | |
d23f028a | 548 | if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) { |
dffc6b24 | 549 | SMSC_TRACE(pdata, hw, "Forcing internal PHY"); |
d23f028a SG |
550 | pdata->using_extphy = 0; |
551 | } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) { | |
dffc6b24 | 552 | SMSC_TRACE(pdata, hw, "Forcing external PHY"); |
d23f028a SG |
553 | smsc911x_phy_enable_external(pdata); |
554 | pdata->using_extphy = 1; | |
555 | } else if (hwcfg & HW_CFG_EXT_PHY_DET_) { | |
dffc6b24 JP |
556 | SMSC_TRACE(pdata, hw, |
557 | "HW_CFG EXT_PHY_DET set, using external PHY"); | |
d23f028a | 558 | smsc911x_phy_enable_external(pdata); |
fd9abb3d SG |
559 | pdata->using_extphy = 1; |
560 | } else { | |
dffc6b24 JP |
561 | SMSC_TRACE(pdata, hw, |
562 | "HW_CFG EXT_PHY_DET clear, using internal PHY"); | |
d23f028a | 563 | pdata->using_extphy = 0; |
fd9abb3d | 564 | } |
fd9abb3d SG |
565 | } |
566 | ||
567 | /* Fetches a tx status out of the status fifo */ | |
568 | static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata) | |
569 | { | |
570 | unsigned int result = | |
571 | smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_; | |
572 | ||
573 | if (result != 0) | |
574 | result = smsc911x_reg_read(pdata, TX_STATUS_FIFO); | |
575 | ||
576 | return result; | |
577 | } | |
578 | ||
579 | /* Fetches the next rx status */ | |
580 | static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata) | |
581 | { | |
582 | unsigned int result = | |
583 | smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_; | |
584 | ||
585 | if (result != 0) | |
586 | result = smsc911x_reg_read(pdata, RX_STATUS_FIFO); | |
587 | ||
588 | return result; | |
589 | } | |
590 | ||
591 | #ifdef USE_PHY_WORK_AROUND | |
592 | static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata) | |
593 | { | |
594 | unsigned int tries; | |
595 | u32 wrsz; | |
596 | u32 rdsz; | |
597 | ulong bufp; | |
598 | ||
599 | for (tries = 0; tries < 10; tries++) { | |
600 | unsigned int txcmd_a; | |
601 | unsigned int txcmd_b; | |
602 | unsigned int status; | |
603 | unsigned int pktlength; | |
604 | unsigned int i; | |
605 | ||
606 | /* Zero-out rx packet memory */ | |
607 | memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE); | |
608 | ||
609 | /* Write tx packet to 118 */ | |
610 | txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16; | |
611 | txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
612 | txcmd_a |= MIN_PACKET_SIZE; | |
613 | ||
614 | txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE; | |
615 | ||
616 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a); | |
617 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b); | |
618 | ||
619 | bufp = (ulong)pdata->loopback_tx_pkt & (~0x3); | |
620 | wrsz = MIN_PACKET_SIZE + 3; | |
621 | wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3); | |
622 | wrsz >>= 2; | |
623 | ||
c326de88 | 624 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d SG |
625 | |
626 | /* Wait till transmit is done */ | |
627 | i = 60; | |
628 | do { | |
629 | udelay(5); | |
630 | status = smsc911x_tx_get_txstatus(pdata); | |
631 | } while ((i--) && (!status)); | |
632 | ||
633 | if (!status) { | |
dffc6b24 JP |
634 | SMSC_WARN(pdata, hw, |
635 | "Failed to transmit during loopback test"); | |
fd9abb3d SG |
636 | continue; |
637 | } | |
638 | if (status & TX_STS_ES_) { | |
dffc6b24 JP |
639 | SMSC_WARN(pdata, hw, |
640 | "Transmit encountered errors during loopback test"); | |
fd9abb3d SG |
641 | continue; |
642 | } | |
643 | ||
644 | /* Wait till receive is done */ | |
645 | i = 60; | |
646 | do { | |
647 | udelay(5); | |
648 | status = smsc911x_rx_get_rxstatus(pdata); | |
649 | } while ((i--) && (!status)); | |
650 | ||
651 | if (!status) { | |
dffc6b24 JP |
652 | SMSC_WARN(pdata, hw, |
653 | "Failed to receive during loopback test"); | |
fd9abb3d SG |
654 | continue; |
655 | } | |
656 | if (status & RX_STS_ES_) { | |
dffc6b24 JP |
657 | SMSC_WARN(pdata, hw, |
658 | "Receive encountered errors during loopback test"); | |
fd9abb3d SG |
659 | continue; |
660 | } | |
661 | ||
662 | pktlength = ((status & 0x3FFF0000UL) >> 16); | |
663 | bufp = (ulong)pdata->loopback_rx_pkt; | |
664 | rdsz = pktlength + 3; | |
665 | rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3); | |
666 | rdsz >>= 2; | |
667 | ||
c326de88 | 668 | pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz); |
fd9abb3d SG |
669 | |
670 | if (pktlength != (MIN_PACKET_SIZE + 4)) { | |
dffc6b24 JP |
671 | SMSC_WARN(pdata, hw, "Unexpected packet size " |
672 | "during loop back test, size=%d, will retry", | |
673 | pktlength); | |
fd9abb3d SG |
674 | } else { |
675 | unsigned int j; | |
676 | int mismatch = 0; | |
677 | for (j = 0; j < MIN_PACKET_SIZE; j++) { | |
678 | if (pdata->loopback_tx_pkt[j] | |
679 | != pdata->loopback_rx_pkt[j]) { | |
680 | mismatch = 1; | |
681 | break; | |
682 | } | |
683 | } | |
684 | if (!mismatch) { | |
dffc6b24 | 685 | SMSC_TRACE(pdata, hw, "Successfully verified " |
fd9abb3d SG |
686 | "loopback packet"); |
687 | return 0; | |
688 | } else { | |
dffc6b24 JP |
689 | SMSC_WARN(pdata, hw, "Data mismatch " |
690 | "during loop back test, will retry"); | |
fd9abb3d SG |
691 | } |
692 | } | |
693 | } | |
694 | ||
695 | return -EIO; | |
696 | } | |
697 | ||
698 | static int smsc911x_phy_reset(struct smsc911x_data *pdata) | |
699 | { | |
700 | struct phy_device *phy_dev = pdata->phy_dev; | |
701 | unsigned int temp; | |
702 | unsigned int i = 100000; | |
703 | ||
704 | BUG_ON(!phy_dev); | |
705 | BUG_ON(!phy_dev->bus); | |
706 | ||
dffc6b24 | 707 | SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset"); |
fd9abb3d SG |
708 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET); |
709 | do { | |
710 | msleep(1); | |
711 | temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, | |
712 | MII_BMCR); | |
713 | } while ((i--) && (temp & BMCR_RESET)); | |
714 | ||
715 | if (temp & BMCR_RESET) { | |
dffc6b24 | 716 | SMSC_WARN(pdata, hw, "PHY reset failed to complete"); |
fd9abb3d SG |
717 | return -EIO; |
718 | } | |
719 | /* Extra delay required because the phy may not be completed with | |
720 | * its reset when BMCR_RESET is cleared. Specs say 256 uS is | |
721 | * enough delay but using 1ms here to be safe */ | |
722 | msleep(1); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
727 | static int smsc911x_phy_loopbacktest(struct net_device *dev) | |
728 | { | |
729 | struct smsc911x_data *pdata = netdev_priv(dev); | |
730 | struct phy_device *phy_dev = pdata->phy_dev; | |
731 | int result = -EIO; | |
732 | unsigned int i, val; | |
733 | unsigned long flags; | |
734 | ||
735 | /* Initialise tx packet using broadcast destination address */ | |
736 | memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN); | |
737 | ||
738 | /* Use incrementing source address */ | |
739 | for (i = 6; i < 12; i++) | |
740 | pdata->loopback_tx_pkt[i] = (char)i; | |
741 | ||
742 | /* Set length type field */ | |
743 | pdata->loopback_tx_pkt[12] = 0x00; | |
744 | pdata->loopback_tx_pkt[13] = 0x00; | |
745 | ||
746 | for (i = 14; i < MIN_PACKET_SIZE; i++) | |
747 | pdata->loopback_tx_pkt[i] = (char)i; | |
748 | ||
749 | val = smsc911x_reg_read(pdata, HW_CFG); | |
750 | val &= HW_CFG_TX_FIF_SZ_; | |
751 | val |= HW_CFG_SF_; | |
752 | smsc911x_reg_write(pdata, HW_CFG, val); | |
753 | ||
754 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
755 | smsc911x_reg_write(pdata, RX_CFG, | |
756 | (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8); | |
757 | ||
758 | for (i = 0; i < 10; i++) { | |
759 | /* Set PHY to 10/FD, no ANEG, and loopback mode */ | |
760 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, | |
761 | BMCR_LOOPBACK | BMCR_FULLDPLX); | |
762 | ||
763 | /* Enable MAC tx/rx, FD */ | |
764 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
765 | smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_ | |
766 | | MAC_CR_TXEN_ | MAC_CR_RXEN_); | |
767 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
768 | ||
769 | if (smsc911x_phy_check_loopbackpkt(pdata) == 0) { | |
770 | result = 0; | |
771 | break; | |
772 | } | |
773 | pdata->resetcount++; | |
774 | ||
775 | /* Disable MAC rx */ | |
776 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
777 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
778 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
779 | ||
780 | smsc911x_phy_reset(pdata); | |
781 | } | |
782 | ||
783 | /* Disable MAC */ | |
784 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
785 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
786 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
787 | ||
788 | /* Cancel PHY loopback mode */ | |
789 | smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0); | |
790 | ||
791 | smsc911x_reg_write(pdata, TX_CFG, 0); | |
792 | smsc911x_reg_write(pdata, RX_CFG, 0); | |
793 | ||
794 | return result; | |
795 | } | |
796 | #endif /* USE_PHY_WORK_AROUND */ | |
797 | ||
fd9abb3d SG |
798 | static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata) |
799 | { | |
800 | struct phy_device *phy_dev = pdata->phy_dev; | |
801 | u32 afc = smsc911x_reg_read(pdata, AFC_CFG); | |
802 | u32 flow; | |
803 | unsigned long flags; | |
804 | ||
805 | if (phy_dev->duplex == DUPLEX_FULL) { | |
806 | u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); | |
807 | u16 rmtadv = phy_read(phy_dev, MII_LPA); | |
bc02ff95 | 808 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
fd9abb3d SG |
809 | |
810 | if (cap & FLOW_CTRL_RX) | |
811 | flow = 0xFFFF0002; | |
812 | else | |
813 | flow = 0; | |
814 | ||
815 | if (cap & FLOW_CTRL_TX) | |
816 | afc |= 0xF; | |
817 | else | |
818 | afc &= ~0xF; | |
819 | ||
dffc6b24 JP |
820 | SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s", |
821 | (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), | |
822 | (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); | |
fd9abb3d | 823 | } else { |
dffc6b24 | 824 | SMSC_TRACE(pdata, hw, "half duplex"); |
fd9abb3d SG |
825 | flow = 0; |
826 | afc |= 0xF; | |
827 | } | |
828 | ||
829 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
830 | smsc911x_mac_write(pdata, FLOW, flow); | |
831 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
832 | ||
833 | smsc911x_reg_write(pdata, AFC_CFG, afc); | |
834 | } | |
835 | ||
836 | /* Update link mode if anything has changed. Called periodically when the | |
837 | * PHY is in polling mode, even if nothing has changed. */ | |
838 | static void smsc911x_phy_adjust_link(struct net_device *dev) | |
839 | { | |
840 | struct smsc911x_data *pdata = netdev_priv(dev); | |
841 | struct phy_device *phy_dev = pdata->phy_dev; | |
842 | unsigned long flags; | |
843 | int carrier; | |
844 | ||
845 | if (phy_dev->duplex != pdata->last_duplex) { | |
846 | unsigned int mac_cr; | |
dffc6b24 | 847 | SMSC_TRACE(pdata, hw, "duplex state has changed"); |
fd9abb3d SG |
848 | |
849 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
850 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
851 | if (phy_dev->duplex) { | |
dffc6b24 JP |
852 | SMSC_TRACE(pdata, hw, |
853 | "configuring for full duplex mode"); | |
fd9abb3d SG |
854 | mac_cr |= MAC_CR_FDPX_; |
855 | } else { | |
dffc6b24 JP |
856 | SMSC_TRACE(pdata, hw, |
857 | "configuring for half duplex mode"); | |
fd9abb3d SG |
858 | mac_cr &= ~MAC_CR_FDPX_; |
859 | } | |
860 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
861 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
862 | ||
863 | smsc911x_phy_update_flowcontrol(pdata); | |
864 | pdata->last_duplex = phy_dev->duplex; | |
865 | } | |
866 | ||
867 | carrier = netif_carrier_ok(dev); | |
868 | if (carrier != pdata->last_carrier) { | |
dffc6b24 | 869 | SMSC_TRACE(pdata, hw, "carrier state has changed"); |
fd9abb3d | 870 | if (carrier) { |
dffc6b24 | 871 | SMSC_TRACE(pdata, hw, "configuring for carrier OK"); |
fd9abb3d SG |
872 | if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) && |
873 | (!pdata->using_extphy)) { | |
88393161 | 874 | /* Restore original GPIO configuration */ |
fd9abb3d SG |
875 | pdata->gpio_setting = pdata->gpio_orig_setting; |
876 | smsc911x_reg_write(pdata, GPIO_CFG, | |
877 | pdata->gpio_setting); | |
878 | } | |
879 | } else { | |
dffc6b24 | 880 | SMSC_TRACE(pdata, hw, "configuring for no carrier"); |
fd9abb3d SG |
881 | /* Check global setting that LED1 |
882 | * usage is 10/100 indicator */ | |
883 | pdata->gpio_setting = smsc911x_reg_read(pdata, | |
884 | GPIO_CFG); | |
8e95a202 JP |
885 | if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) && |
886 | (!pdata->using_extphy)) { | |
fd9abb3d | 887 | /* Force 10/100 LED off, after saving |
88393161 | 888 | * original GPIO configuration */ |
fd9abb3d SG |
889 | pdata->gpio_orig_setting = pdata->gpio_setting; |
890 | ||
891 | pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_; | |
892 | pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_ | |
893 | | GPIO_CFG_GPIODIR0_ | |
894 | | GPIO_CFG_GPIOD0_); | |
895 | smsc911x_reg_write(pdata, GPIO_CFG, | |
896 | pdata->gpio_setting); | |
897 | } | |
898 | } | |
899 | pdata->last_carrier = carrier; | |
900 | } | |
901 | } | |
902 | ||
903 | static int smsc911x_mii_probe(struct net_device *dev) | |
904 | { | |
905 | struct smsc911x_data *pdata = netdev_priv(dev); | |
906 | struct phy_device *phydev = NULL; | |
e4a474f8 | 907 | int ret; |
fd9abb3d SG |
908 | |
909 | /* find the first phy */ | |
e4a474f8 | 910 | phydev = phy_find_first(pdata->mii_bus); |
fd9abb3d | 911 | if (!phydev) { |
dffc6b24 | 912 | netdev_err(dev, "no PHY found\n"); |
fd9abb3d SG |
913 | return -ENODEV; |
914 | } | |
915 | ||
dffc6b24 JP |
916 | SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X", |
917 | phydev->addr, phydev->phy_id); | |
e4a474f8 | 918 | |
919 | ret = phy_connect_direct(dev, phydev, | |
920 | &smsc911x_phy_adjust_link, 0, | |
921 | pdata->config.phy_interface); | |
fd9abb3d | 922 | |
e4a474f8 | 923 | if (ret) { |
dffc6b24 | 924 | netdev_err(dev, "Could not attach to PHY\n"); |
e4a474f8 | 925 | return ret; |
fd9abb3d SG |
926 | } |
927 | ||
dffc6b24 JP |
928 | netdev_info(dev, |
929 | "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
930 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
fd9abb3d SG |
931 | |
932 | /* mask with MAC supported features */ | |
933 | phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | | |
934 | SUPPORTED_Asym_Pause); | |
935 | phydev->advertising = phydev->supported; | |
936 | ||
937 | pdata->phy_dev = phydev; | |
938 | pdata->last_duplex = -1; | |
939 | pdata->last_carrier = -1; | |
940 | ||
941 | #ifdef USE_PHY_WORK_AROUND | |
942 | if (smsc911x_phy_loopbacktest(dev) < 0) { | |
dffc6b24 | 943 | SMSC_WARN(pdata, hw, "Failed Loop Back Test"); |
fd9abb3d SG |
944 | return -ENODEV; |
945 | } | |
dffc6b24 | 946 | SMSC_TRACE(pdata, hw, "Passed Loop Back Test"); |
fd9abb3d SG |
947 | #endif /* USE_PHY_WORK_AROUND */ |
948 | ||
dffc6b24 | 949 | SMSC_TRACE(pdata, hw, "phy initialised successfully"); |
fd9abb3d SG |
950 | return 0; |
951 | } | |
952 | ||
953 | static int __devinit smsc911x_mii_init(struct platform_device *pdev, | |
954 | struct net_device *dev) | |
955 | { | |
956 | struct smsc911x_data *pdata = netdev_priv(dev); | |
957 | int err = -ENXIO, i; | |
958 | ||
959 | pdata->mii_bus = mdiobus_alloc(); | |
960 | if (!pdata->mii_bus) { | |
961 | err = -ENOMEM; | |
962 | goto err_out_1; | |
963 | } | |
964 | ||
965 | pdata->mii_bus->name = SMSC_MDIONAME; | |
966 | snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id); | |
967 | pdata->mii_bus->priv = pdata; | |
968 | pdata->mii_bus->read = smsc911x_mii_read; | |
969 | pdata->mii_bus->write = smsc911x_mii_write; | |
970 | pdata->mii_bus->irq = pdata->phy_irq; | |
971 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
972 | pdata->mii_bus->irq[i] = PHY_POLL; | |
973 | ||
974 | pdata->mii_bus->parent = &pdev->dev; | |
fd9abb3d | 975 | |
fd9abb3d SG |
976 | switch (pdata->idrev & 0xFFFF0000) { |
977 | case 0x01170000: | |
978 | case 0x01150000: | |
979 | case 0x117A0000: | |
980 | case 0x115A0000: | |
981 | /* External PHY supported, try to autodetect */ | |
d23f028a | 982 | smsc911x_phy_initialise_external(pdata); |
fd9abb3d SG |
983 | break; |
984 | default: | |
dffc6b24 JP |
985 | SMSC_TRACE(pdata, hw, "External PHY is not supported, " |
986 | "using internal PHY"); | |
d23f028a | 987 | pdata->using_extphy = 0; |
fd9abb3d SG |
988 | break; |
989 | } | |
990 | ||
991 | if (!pdata->using_extphy) { | |
992 | /* Mask all PHYs except ID 1 (internal) */ | |
993 | pdata->mii_bus->phy_mask = ~(1 << 1); | |
994 | } | |
995 | ||
996 | if (mdiobus_register(pdata->mii_bus)) { | |
dffc6b24 | 997 | SMSC_WARN(pdata, probe, "Error registering mii bus"); |
fd9abb3d SG |
998 | goto err_out_free_bus_2; |
999 | } | |
1000 | ||
1001 | if (smsc911x_mii_probe(dev) < 0) { | |
dffc6b24 | 1002 | SMSC_WARN(pdata, probe, "Error registering mii bus"); |
fd9abb3d SG |
1003 | goto err_out_unregister_bus_3; |
1004 | } | |
1005 | ||
1006 | return 0; | |
1007 | ||
1008 | err_out_unregister_bus_3: | |
1009 | mdiobus_unregister(pdata->mii_bus); | |
1010 | err_out_free_bus_2: | |
1011 | mdiobus_free(pdata->mii_bus); | |
1012 | err_out_1: | |
1013 | return err; | |
1014 | } | |
1015 | ||
1016 | /* Gets the number of tx statuses in the fifo */ | |
1017 | static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata) | |
1018 | { | |
1019 | return (smsc911x_reg_read(pdata, TX_FIFO_INF) | |
1020 | & TX_FIFO_INF_TSUSED_) >> 16; | |
1021 | } | |
1022 | ||
1023 | /* Reads tx statuses and increments counters where necessary */ | |
1024 | static void smsc911x_tx_update_txcounters(struct net_device *dev) | |
1025 | { | |
1026 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1027 | unsigned int tx_stat; | |
1028 | ||
1029 | while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) { | |
1030 | if (unlikely(tx_stat & 0x80000000)) { | |
1031 | /* In this driver the packet tag is used as the packet | |
1032 | * length. Since a packet length can never reach the | |
1033 | * size of 0x8000, this bit is reserved. It is worth | |
1034 | * noting that the "reserved bit" in the warning above | |
1035 | * does not reference a hardware defined reserved bit | |
1036 | * but rather a driver defined one. | |
1037 | */ | |
dffc6b24 | 1038 | SMSC_WARN(pdata, hw, "Packet tag reserved bit is high"); |
fd9abb3d | 1039 | } else { |
785b6f97 | 1040 | if (unlikely(tx_stat & TX_STS_ES_)) { |
fd9abb3d SG |
1041 | dev->stats.tx_errors++; |
1042 | } else { | |
1043 | dev->stats.tx_packets++; | |
1044 | dev->stats.tx_bytes += (tx_stat >> 16); | |
1045 | } | |
785b6f97 | 1046 | if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) { |
fd9abb3d SG |
1047 | dev->stats.collisions += 16; |
1048 | dev->stats.tx_aborted_errors += 1; | |
1049 | } else { | |
1050 | dev->stats.collisions += | |
1051 | ((tx_stat >> 3) & 0xF); | |
1052 | } | |
785b6f97 | 1053 | if (unlikely(tx_stat & TX_STS_LOST_CARRIER_)) |
fd9abb3d | 1054 | dev->stats.tx_carrier_errors += 1; |
785b6f97 | 1055 | if (unlikely(tx_stat & TX_STS_LATE_COL_)) { |
fd9abb3d SG |
1056 | dev->stats.collisions++; |
1057 | dev->stats.tx_aborted_errors++; | |
1058 | } | |
1059 | } | |
1060 | } | |
1061 | } | |
1062 | ||
1063 | /* Increments the Rx error counters */ | |
1064 | static void | |
1065 | smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat) | |
1066 | { | |
1067 | int crc_err = 0; | |
1068 | ||
785b6f97 | 1069 | if (unlikely(rxstat & RX_STS_ES_)) { |
fd9abb3d | 1070 | dev->stats.rx_errors++; |
785b6f97 | 1071 | if (unlikely(rxstat & RX_STS_CRC_ERR_)) { |
fd9abb3d SG |
1072 | dev->stats.rx_crc_errors++; |
1073 | crc_err = 1; | |
1074 | } | |
1075 | } | |
1076 | if (likely(!crc_err)) { | |
785b6f97 SG |
1077 | if (unlikely((rxstat & RX_STS_FRAME_TYPE_) && |
1078 | (rxstat & RX_STS_LENGTH_ERR_))) | |
fd9abb3d | 1079 | dev->stats.rx_length_errors++; |
fd9abb3d SG |
1080 | if (rxstat & RX_STS_MCAST_) |
1081 | dev->stats.multicast++; | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | /* Quickly dumps bad packets */ | |
1086 | static void | |
1087 | smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes) | |
1088 | { | |
1089 | unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2; | |
1090 | ||
1091 | if (likely(pktwords >= 4)) { | |
1092 | unsigned int timeout = 500; | |
1093 | unsigned int val; | |
1094 | smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_); | |
1095 | do { | |
1096 | udelay(1); | |
1097 | val = smsc911x_reg_read(pdata, RX_DP_CTRL); | |
8dacd548 | 1098 | } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout); |
fd9abb3d SG |
1099 | |
1100 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1101 | SMSC_WARN(pdata, hw, "Timed out waiting for " |
1102 | "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val); | |
fd9abb3d SG |
1103 | } else { |
1104 | unsigned int temp; | |
1105 | while (pktwords--) | |
1106 | temp = smsc911x_reg_read(pdata, RX_DATA_FIFO); | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | /* NAPI poll function */ | |
1111 | static int smsc911x_poll(struct napi_struct *napi, int budget) | |
1112 | { | |
1113 | struct smsc911x_data *pdata = | |
1114 | container_of(napi, struct smsc911x_data, napi); | |
1115 | struct net_device *dev = pdata->dev; | |
1116 | int npackets = 0; | |
1117 | ||
f88c5b98 | 1118 | while (npackets < budget) { |
fd9abb3d SG |
1119 | unsigned int pktlength; |
1120 | unsigned int pktwords; | |
1121 | struct sk_buff *skb; | |
1122 | unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata); | |
1123 | ||
1124 | if (!rxstat) { | |
1125 | unsigned int temp; | |
1126 | /* We processed all packets available. Tell NAPI it can | |
1127 | * stop polling then re-enable rx interrupts */ | |
1128 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_); | |
288379f0 | 1129 | napi_complete(napi); |
fd9abb3d SG |
1130 | temp = smsc911x_reg_read(pdata, INT_EN); |
1131 | temp |= INT_EN_RSFL_EN_; | |
1132 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1133 | break; | |
1134 | } | |
1135 | ||
1136 | /* Count packet for NAPI scheduling, even if it has an error. | |
1137 | * Error packets still require cycles to discard */ | |
1138 | npackets++; | |
1139 | ||
1140 | pktlength = ((rxstat & 0x3FFF0000) >> 16); | |
1141 | pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2; | |
1142 | smsc911x_rx_counterrors(dev, rxstat); | |
1143 | ||
1144 | if (unlikely(rxstat & RX_STS_ES_)) { | |
dffc6b24 JP |
1145 | SMSC_WARN(pdata, rx_err, |
1146 | "Discarding packet with error bit set"); | |
fd9abb3d SG |
1147 | /* Packet has an error, discard it and continue with |
1148 | * the next */ | |
1149 | smsc911x_rx_fastforward(pdata, pktwords); | |
1150 | dev->stats.rx_dropped++; | |
1151 | continue; | |
1152 | } | |
1153 | ||
1154 | skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN); | |
1155 | if (unlikely(!skb)) { | |
dffc6b24 JP |
1156 | SMSC_WARN(pdata, rx_err, |
1157 | "Unable to allocate skb for rx packet"); | |
fd9abb3d SG |
1158 | /* Drop the packet and stop this polling iteration */ |
1159 | smsc911x_rx_fastforward(pdata, pktwords); | |
1160 | dev->stats.rx_dropped++; | |
1161 | break; | |
1162 | } | |
1163 | ||
1164 | skb->data = skb->head; | |
1165 | skb_reset_tail_pointer(skb); | |
1166 | ||
1167 | /* Align IP on 16B boundary */ | |
1168 | skb_reserve(skb, NET_IP_ALIGN); | |
1169 | skb_put(skb, pktlength - 4); | |
c326de88 MP |
1170 | pdata->ops->rx_readfifo(pdata, |
1171 | (unsigned int *)skb->head, pktwords); | |
fd9abb3d | 1172 | skb->protocol = eth_type_trans(skb, dev); |
bc8acf2c | 1173 | skb_checksum_none_assert(skb); |
fd9abb3d SG |
1174 | netif_receive_skb(skb); |
1175 | ||
1176 | /* Update counters */ | |
1177 | dev->stats.rx_packets++; | |
1178 | dev->stats.rx_bytes += (pktlength - 4); | |
fd9abb3d SG |
1179 | } |
1180 | ||
1181 | /* Return total received packets */ | |
1182 | return npackets; | |
1183 | } | |
1184 | ||
1185 | /* Returns hash bit number for given MAC address | |
1186 | * Example: | |
1187 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
1188 | static unsigned int smsc911x_hash(char addr[ETH_ALEN]) | |
1189 | { | |
1190 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
1191 | } | |
1192 | ||
1193 | static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata) | |
1194 | { | |
1195 | /* Performs the multicast & mac_cr update. This is called when | |
1196 | * safe on the current hardware, and with the mac_lock held */ | |
1197 | unsigned int mac_cr; | |
1198 | ||
1199 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1200 | ||
1201 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1202 | mac_cr |= pdata->set_bits_mask; | |
1203 | mac_cr &= ~(pdata->clear_bits_mask); | |
1204 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1205 | smsc911x_mac_write(pdata, HASHH, pdata->hashhi); | |
1206 | smsc911x_mac_write(pdata, HASHL, pdata->hashlo); | |
dffc6b24 JP |
1207 | SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X", |
1208 | mac_cr, pdata->hashhi, pdata->hashlo); | |
fd9abb3d SG |
1209 | } |
1210 | ||
1211 | static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata) | |
1212 | { | |
1213 | unsigned int mac_cr; | |
1214 | ||
1215 | /* This function is only called for older LAN911x devices | |
1216 | * (revA or revB), where MAC_CR, HASHH and HASHL should not | |
1217 | * be modified during Rx - newer devices immediately update the | |
1218 | * registers. | |
1219 | * | |
1220 | * This is called from interrupt context */ | |
1221 | ||
1222 | spin_lock(&pdata->mac_lock); | |
1223 | ||
1224 | /* Check Rx has stopped */ | |
1225 | if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_) | |
dffc6b24 | 1226 | SMSC_WARN(pdata, drv, "Rx not stopped"); |
fd9abb3d SG |
1227 | |
1228 | /* Perform the update - safe to do now Rx has stopped */ | |
1229 | smsc911x_rx_multicast_update(pdata); | |
1230 | ||
1231 | /* Re-enable Rx */ | |
1232 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1233 | mac_cr |= MAC_CR_RXEN_; | |
1234 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1235 | ||
1236 | pdata->multicast_update_pending = 0; | |
1237 | ||
1238 | spin_unlock(&pdata->mac_lock); | |
1239 | } | |
1240 | ||
1241 | static int smsc911x_soft_reset(struct smsc911x_data *pdata) | |
1242 | { | |
1243 | unsigned int timeout; | |
1244 | unsigned int temp; | |
1245 | ||
1246 | /* Reset the LAN911x */ | |
1247 | smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_); | |
1248 | timeout = 10; | |
1249 | do { | |
1250 | udelay(10); | |
1251 | temp = smsc911x_reg_read(pdata, HW_CFG); | |
1252 | } while ((--timeout) && (temp & HW_CFG_SRST_)); | |
1253 | ||
1254 | if (unlikely(temp & HW_CFG_SRST_)) { | |
dffc6b24 | 1255 | SMSC_WARN(pdata, drv, "Failed to complete reset"); |
fd9abb3d SG |
1256 | return -EIO; |
1257 | } | |
1258 | return 0; | |
1259 | } | |
1260 | ||
1261 | /* Sets the device MAC address to dev_addr, called with mac_lock held */ | |
1262 | static void | |
225ddf49 | 1263 | smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6]) |
fd9abb3d SG |
1264 | { |
1265 | u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; | |
1266 | u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | | |
1267 | (dev_addr[1] << 8) | dev_addr[0]; | |
1268 | ||
1269 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1270 | ||
1271 | smsc911x_mac_write(pdata, ADDRH, mac_high16); | |
1272 | smsc911x_mac_write(pdata, ADDRL, mac_low32); | |
1273 | } | |
1274 | ||
1275 | static int smsc911x_open(struct net_device *dev) | |
1276 | { | |
1277 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1278 | unsigned int timeout; | |
1279 | unsigned int temp; | |
1280 | unsigned int intcfg; | |
1281 | ||
1282 | /* if the phy is not yet registered, retry later*/ | |
1283 | if (!pdata->phy_dev) { | |
dffc6b24 | 1284 | SMSC_WARN(pdata, hw, "phy_dev is NULL"); |
fd9abb3d SG |
1285 | return -EAGAIN; |
1286 | } | |
1287 | ||
1288 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
dffc6b24 | 1289 | SMSC_WARN(pdata, hw, "dev_addr is not a valid MAC address"); |
fd9abb3d SG |
1290 | return -EADDRNOTAVAIL; |
1291 | } | |
1292 | ||
1293 | /* Reset the LAN911x */ | |
1294 | if (smsc911x_soft_reset(pdata)) { | |
dffc6b24 | 1295 | SMSC_WARN(pdata, hw, "soft reset failed"); |
fd9abb3d SG |
1296 | return -EIO; |
1297 | } | |
1298 | ||
1299 | smsc911x_reg_write(pdata, HW_CFG, 0x00050000); | |
1300 | smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740); | |
1301 | ||
f277e65e GW |
1302 | /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */ |
1303 | spin_lock_irq(&pdata->mac_lock); | |
1304 | smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q); | |
1305 | spin_unlock_irq(&pdata->mac_lock); | |
1306 | ||
fd9abb3d SG |
1307 | /* Make sure EEPROM has finished loading before setting GPIO_CFG */ |
1308 | timeout = 50; | |
f7efb6cc SG |
1309 | while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) && |
1310 | --timeout) { | |
fd9abb3d SG |
1311 | udelay(10); |
1312 | } | |
1313 | ||
1314 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1315 | SMSC_WARN(pdata, ifup, |
1316 | "Timed out waiting for EEPROM busy bit to clear"); | |
fd9abb3d SG |
1317 | |
1318 | smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000); | |
1319 | ||
1320 | /* The soft reset above cleared the device's MAC address, | |
1321 | * restore it from local copy (set in probe) */ | |
1322 | spin_lock_irq(&pdata->mac_lock); | |
225ddf49 | 1323 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
fd9abb3d SG |
1324 | spin_unlock_irq(&pdata->mac_lock); |
1325 | ||
1326 | /* Initialise irqs, but leave all sources disabled */ | |
1327 | smsc911x_reg_write(pdata, INT_EN, 0); | |
1328 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); | |
1329 | ||
1330 | /* Set interrupt deassertion to 100uS */ | |
1331 | intcfg = ((10 << 24) | INT_CFG_IRQ_EN_); | |
1332 | ||
2107fb8b | 1333 | if (pdata->config.irq_polarity) { |
dffc6b24 | 1334 | SMSC_TRACE(pdata, ifup, "irq polarity: active high"); |
fd9abb3d SG |
1335 | intcfg |= INT_CFG_IRQ_POL_; |
1336 | } else { | |
dffc6b24 | 1337 | SMSC_TRACE(pdata, ifup, "irq polarity: active low"); |
fd9abb3d SG |
1338 | } |
1339 | ||
2107fb8b | 1340 | if (pdata->config.irq_type) { |
dffc6b24 | 1341 | SMSC_TRACE(pdata, ifup, "irq type: push-pull"); |
fd9abb3d SG |
1342 | intcfg |= INT_CFG_IRQ_TYPE_; |
1343 | } else { | |
dffc6b24 | 1344 | SMSC_TRACE(pdata, ifup, "irq type: open drain"); |
fd9abb3d SG |
1345 | } |
1346 | ||
1347 | smsc911x_reg_write(pdata, INT_CFG, intcfg); | |
1348 | ||
dffc6b24 | 1349 | SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq); |
fd9abb3d SG |
1350 | pdata->software_irq_signal = 0; |
1351 | smp_wmb(); | |
1352 | ||
1353 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1354 | temp |= INT_EN_SW_INT_EN_; | |
1355 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1356 | ||
1357 | timeout = 1000; | |
1358 | while (timeout--) { | |
1359 | if (pdata->software_irq_signal) | |
1360 | break; | |
1361 | msleep(1); | |
1362 | } | |
1363 | ||
1364 | if (!pdata->software_irq_signal) { | |
dffc6b24 JP |
1365 | netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n", |
1366 | dev->irq); | |
fd9abb3d SG |
1367 | return -ENODEV; |
1368 | } | |
dffc6b24 JP |
1369 | SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d", |
1370 | dev->irq); | |
fd9abb3d | 1371 | |
dffc6b24 JP |
1372 | netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n", |
1373 | (unsigned long)pdata->ioaddr, dev->irq); | |
fd9abb3d | 1374 | |
44c1d6f9 SG |
1375 | /* Reset the last known duplex and carrier */ |
1376 | pdata->last_duplex = -1; | |
1377 | pdata->last_carrier = -1; | |
1378 | ||
fd9abb3d SG |
1379 | /* Bring the PHY up */ |
1380 | phy_start(pdata->phy_dev); | |
1381 | ||
1382 | temp = smsc911x_reg_read(pdata, HW_CFG); | |
1383 | /* Preserve TX FIFO size and external PHY configuration */ | |
1384 | temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF); | |
1385 | temp |= HW_CFG_SF_; | |
1386 | smsc911x_reg_write(pdata, HW_CFG, temp); | |
1387 | ||
1388 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1389 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1390 | temp &= ~(FIFO_INT_RX_STS_LEVEL_); | |
1391 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1392 | ||
1393 | /* set RX Data offset to 2 bytes for alignment */ | |
1394 | smsc911x_reg_write(pdata, RX_CFG, (2 << 8)); | |
1395 | ||
1396 | /* enable NAPI polling before enabling RX interrupts */ | |
1397 | napi_enable(&pdata->napi); | |
1398 | ||
1399 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1373c0fd | 1400 | temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_); |
fd9abb3d SG |
1401 | smsc911x_reg_write(pdata, INT_EN, temp); |
1402 | ||
1403 | spin_lock_irq(&pdata->mac_lock); | |
1404 | temp = smsc911x_mac_read(pdata, MAC_CR); | |
1405 | temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_); | |
1406 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1407 | spin_unlock_irq(&pdata->mac_lock); | |
1408 | ||
1409 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
1410 | ||
1411 | netif_start_queue(dev); | |
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | /* Entry point for stopping the interface */ | |
1416 | static int smsc911x_stop(struct net_device *dev) | |
1417 | { | |
1418 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1419 | unsigned int temp; | |
1420 | ||
fd9abb3d SG |
1421 | /* Disable all device interrupts */ |
1422 | temp = smsc911x_reg_read(pdata, INT_CFG); | |
1423 | temp &= ~INT_CFG_IRQ_EN_; | |
1424 | smsc911x_reg_write(pdata, INT_CFG, temp); | |
1425 | ||
1426 | /* Stop Tx and Rx polling */ | |
1427 | netif_stop_queue(dev); | |
1428 | napi_disable(&pdata->napi); | |
1429 | ||
1430 | /* At this point all Rx and Tx activity is stopped */ | |
1431 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1432 | smsc911x_tx_update_txcounters(dev); | |
1433 | ||
1434 | /* Bring the PHY down */ | |
dd045193 SG |
1435 | if (pdata->phy_dev) |
1436 | phy_stop(pdata->phy_dev); | |
fd9abb3d | 1437 | |
dffc6b24 | 1438 | SMSC_TRACE(pdata, ifdown, "Interface stopped"); |
fd9abb3d SG |
1439 | return 0; |
1440 | } | |
1441 | ||
1442 | /* Entry point for transmitting a packet */ | |
1443 | static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1444 | { | |
1445 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1446 | unsigned int freespace; | |
1447 | unsigned int tx_cmd_a; | |
1448 | unsigned int tx_cmd_b; | |
1449 | unsigned int temp; | |
1450 | u32 wrsz; | |
1451 | ulong bufp; | |
1452 | ||
1453 | freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_; | |
1454 | ||
1455 | if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD)) | |
dffc6b24 JP |
1456 | SMSC_WARN(pdata, tx_err, |
1457 | "Tx data fifo low, space available: %d", freespace); | |
fd9abb3d SG |
1458 | |
1459 | /* Word alignment adjustment */ | |
1460 | tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16; | |
1461 | tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
1462 | tx_cmd_a |= (unsigned int)skb->len; | |
1463 | ||
1464 | tx_cmd_b = ((unsigned int)skb->len) << 16; | |
1465 | tx_cmd_b |= (unsigned int)skb->len; | |
1466 | ||
1467 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a); | |
1468 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b); | |
1469 | ||
1470 | bufp = (ulong)skb->data & (~0x3); | |
1471 | wrsz = (u32)skb->len + 3; | |
1472 | wrsz += (u32)((ulong)skb->data & 0x3); | |
1473 | wrsz >>= 2; | |
1474 | ||
c326de88 | 1475 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d | 1476 | freespace -= (skb->len + 32); |
8c0069ae | 1477 | skb_tx_timestamp(skb); |
fd9abb3d | 1478 | dev_kfree_skb(skb); |
fd9abb3d SG |
1479 | |
1480 | if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30)) | |
1481 | smsc911x_tx_update_txcounters(dev); | |
1482 | ||
1483 | if (freespace < TX_FIFO_LOW_THRESHOLD) { | |
1484 | netif_stop_queue(dev); | |
1485 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1486 | temp &= 0x00FFFFFF; | |
1487 | temp |= 0x32000000; | |
1488 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1489 | } | |
1490 | ||
1491 | return NETDEV_TX_OK; | |
1492 | } | |
1493 | ||
1494 | /* Entry point for getting status counters */ | |
1495 | static struct net_device_stats *smsc911x_get_stats(struct net_device *dev) | |
1496 | { | |
1497 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1498 | smsc911x_tx_update_txcounters(dev); | |
1499 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1500 | return &dev->stats; | |
1501 | } | |
1502 | ||
1503 | /* Entry point for setting addressing modes */ | |
1504 | static void smsc911x_set_multicast_list(struct net_device *dev) | |
1505 | { | |
1506 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1507 | unsigned long flags; | |
1508 | ||
1509 | if (dev->flags & IFF_PROMISC) { | |
1510 | /* Enabling promiscuous mode */ | |
1511 | pdata->set_bits_mask = MAC_CR_PRMS_; | |
1512 | pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1513 | pdata->hashhi = 0; | |
1514 | pdata->hashlo = 0; | |
1515 | } else if (dev->flags & IFF_ALLMULTI) { | |
1516 | /* Enabling all multicast mode */ | |
1517 | pdata->set_bits_mask = MAC_CR_MCPAS_; | |
1518 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_); | |
1519 | pdata->hashhi = 0; | |
1520 | pdata->hashlo = 0; | |
4cd24eaf | 1521 | } else if (!netdev_mc_empty(dev)) { |
fd9abb3d SG |
1522 | /* Enabling specific multicast addresses */ |
1523 | unsigned int hash_high = 0; | |
1524 | unsigned int hash_low = 0; | |
22bedad3 | 1525 | struct netdev_hw_addr *ha; |
fd9abb3d SG |
1526 | |
1527 | pdata->set_bits_mask = MAC_CR_HPFILT_; | |
1528 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_); | |
1529 | ||
22bedad3 JP |
1530 | netdev_for_each_mc_addr(ha, dev) { |
1531 | unsigned int bitnum = smsc911x_hash(ha->addr); | |
2a0d18f9 JP |
1532 | unsigned int mask = 0x01 << (bitnum & 0x1F); |
1533 | ||
1534 | if (bitnum & 0x20) | |
1535 | hash_high |= mask; | |
1536 | else | |
1537 | hash_low |= mask; | |
fd9abb3d | 1538 | } |
fd9abb3d SG |
1539 | |
1540 | pdata->hashhi = hash_high; | |
1541 | pdata->hashlo = hash_low; | |
1542 | } else { | |
1543 | /* Enabling local MAC address only */ | |
1544 | pdata->set_bits_mask = 0; | |
1545 | pdata->clear_bits_mask = | |
1546 | (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1547 | pdata->hashhi = 0; | |
1548 | pdata->hashlo = 0; | |
1549 | } | |
1550 | ||
1551 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
1552 | ||
1553 | if (pdata->generation <= 1) { | |
1554 | /* Older hardware revision - cannot change these flags while | |
1555 | * receiving data */ | |
1556 | if (!pdata->multicast_update_pending) { | |
1557 | unsigned int temp; | |
dffc6b24 | 1558 | SMSC_TRACE(pdata, hw, "scheduling mcast update"); |
fd9abb3d SG |
1559 | pdata->multicast_update_pending = 1; |
1560 | ||
1561 | /* Request the hardware to stop, then perform the | |
1562 | * update when we get an RX_STOP interrupt */ | |
fd9abb3d SG |
1563 | temp = smsc911x_mac_read(pdata, MAC_CR); |
1564 | temp &= ~(MAC_CR_RXEN_); | |
1565 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1566 | } else { | |
1567 | /* There is another update pending, this should now | |
1568 | * use the newer values */ | |
1569 | } | |
1570 | } else { | |
1571 | /* Newer hardware revision - can write immediately */ | |
1572 | smsc911x_rx_multicast_update(pdata); | |
1573 | } | |
1574 | ||
1575 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
1576 | } | |
1577 | ||
1578 | static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id) | |
1579 | { | |
1580 | struct net_device *dev = dev_id; | |
1581 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1582 | u32 intsts = smsc911x_reg_read(pdata, INT_STS); | |
1583 | u32 inten = smsc911x_reg_read(pdata, INT_EN); | |
1584 | int serviced = IRQ_NONE; | |
1585 | u32 temp; | |
1586 | ||
1587 | if (unlikely(intsts & inten & INT_STS_SW_INT_)) { | |
1588 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1589 | temp &= (~INT_EN_SW_INT_EN_); | |
1590 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1591 | smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_); | |
1592 | pdata->software_irq_signal = 1; | |
1593 | smp_wmb(); | |
1594 | serviced = IRQ_HANDLED; | |
1595 | } | |
1596 | ||
1597 | if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) { | |
1598 | /* Called when there is a multicast update scheduled and | |
1599 | * it is now safe to complete the update */ | |
dffc6b24 | 1600 | SMSC_TRACE(pdata, intr, "RX Stop interrupt"); |
fd9abb3d | 1601 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_); |
1373c0fd SG |
1602 | if (pdata->multicast_update_pending) |
1603 | smsc911x_rx_multicast_update_workaround(pdata); | |
fd9abb3d SG |
1604 | serviced = IRQ_HANDLED; |
1605 | } | |
1606 | ||
1607 | if (intsts & inten & INT_STS_TDFA_) { | |
1608 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1609 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1610 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1611 | smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_); | |
1612 | netif_wake_queue(dev); | |
1613 | serviced = IRQ_HANDLED; | |
1614 | } | |
1615 | ||
1616 | if (unlikely(intsts & inten & INT_STS_RXE_)) { | |
dffc6b24 | 1617 | SMSC_TRACE(pdata, intr, "RX Error interrupt"); |
fd9abb3d SG |
1618 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_); |
1619 | serviced = IRQ_HANDLED; | |
1620 | } | |
1621 | ||
1622 | if (likely(intsts & inten & INT_STS_RSFL_)) { | |
288379f0 | 1623 | if (likely(napi_schedule_prep(&pdata->napi))) { |
fd9abb3d SG |
1624 | /* Disable Rx interrupts */ |
1625 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1626 | temp &= (~INT_EN_RSFL_EN_); | |
1627 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1628 | /* Schedule a NAPI poll */ | |
288379f0 | 1629 | __napi_schedule(&pdata->napi); |
fd9abb3d | 1630 | } else { |
dffc6b24 | 1631 | SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed"); |
fd9abb3d SG |
1632 | } |
1633 | serviced = IRQ_HANDLED; | |
1634 | } | |
1635 | ||
1636 | return serviced; | |
1637 | } | |
1638 | ||
1639 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1757ab2f | 1640 | static void smsc911x_poll_controller(struct net_device *dev) |
fd9abb3d SG |
1641 | { |
1642 | disable_irq(dev->irq); | |
1643 | smsc911x_irqhandler(0, dev); | |
1644 | enable_irq(dev->irq); | |
1645 | } | |
1646 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
1647 | ||
225ddf49 SG |
1648 | static int smsc911x_set_mac_address(struct net_device *dev, void *p) |
1649 | { | |
1650 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1651 | struct sockaddr *addr = p; | |
1652 | ||
1653 | /* On older hardware revisions we cannot change the mac address | |
1654 | * registers while receiving data. Newer devices can safely change | |
1655 | * this at any time. */ | |
1656 | if (pdata->generation <= 1 && netif_running(dev)) | |
1657 | return -EBUSY; | |
1658 | ||
1659 | if (!is_valid_ether_addr(addr->sa_data)) | |
1660 | return -EADDRNOTAVAIL; | |
1661 | ||
1662 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
1663 | ||
1664 | spin_lock_irq(&pdata->mac_lock); | |
1665 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); | |
1666 | spin_unlock_irq(&pdata->mac_lock); | |
1667 | ||
dffc6b24 | 1668 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
225ddf49 SG |
1669 | |
1670 | return 0; | |
1671 | } | |
1672 | ||
fd9abb3d SG |
1673 | /* Standard ioctls for mii-tool */ |
1674 | static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1675 | { | |
1676 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1677 | ||
1678 | if (!netif_running(dev) || !pdata->phy_dev) | |
1679 | return -EINVAL; | |
1680 | ||
28b04113 | 1681 | return phy_mii_ioctl(pdata->phy_dev, ifr, cmd); |
fd9abb3d SG |
1682 | } |
1683 | ||
1684 | static int | |
1685 | smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1686 | { | |
1687 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1688 | ||
1689 | cmd->maxtxpkt = 1; | |
1690 | cmd->maxrxpkt = 1; | |
1691 | return phy_ethtool_gset(pdata->phy_dev, cmd); | |
1692 | } | |
1693 | ||
1694 | static int | |
1695 | smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1696 | { | |
1697 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1698 | ||
1699 | return phy_ethtool_sset(pdata->phy_dev, cmd); | |
1700 | } | |
1701 | ||
1702 | static void smsc911x_ethtool_getdrvinfo(struct net_device *dev, | |
1703 | struct ethtool_drvinfo *info) | |
1704 | { | |
1705 | strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver)); | |
1706 | strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version)); | |
db1d7bf7 | 1707 | strlcpy(info->bus_info, dev_name(dev->dev.parent), |
fd9abb3d SG |
1708 | sizeof(info->bus_info)); |
1709 | } | |
1710 | ||
1711 | static int smsc911x_ethtool_nwayreset(struct net_device *dev) | |
1712 | { | |
1713 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1714 | ||
1715 | return phy_start_aneg(pdata->phy_dev); | |
1716 | } | |
1717 | ||
1718 | static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev) | |
1719 | { | |
1720 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1721 | return pdata->msg_enable; | |
1722 | } | |
1723 | ||
1724 | static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level) | |
1725 | { | |
1726 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1727 | pdata->msg_enable = level; | |
1728 | } | |
1729 | ||
1730 | static int smsc911x_ethtool_getregslen(struct net_device *dev) | |
1731 | { | |
1732 | return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) * | |
1733 | sizeof(u32); | |
1734 | } | |
1735 | ||
1736 | static void | |
1737 | smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, | |
1738 | void *buf) | |
1739 | { | |
1740 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1741 | struct phy_device *phy_dev = pdata->phy_dev; | |
1742 | unsigned long flags; | |
1743 | unsigned int i; | |
1744 | unsigned int j = 0; | |
1745 | u32 *data = buf; | |
1746 | ||
1747 | regs->version = pdata->idrev; | |
1748 | for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32))) | |
1749 | data[j++] = smsc911x_reg_read(pdata, i); | |
1750 | ||
1751 | for (i = MAC_CR; i <= WUCSR; i++) { | |
1752 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
1753 | data[j++] = smsc911x_mac_read(pdata, i); | |
1754 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
1755 | } | |
1756 | ||
1757 | for (i = 0; i <= 31; i++) | |
1758 | data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i); | |
1759 | } | |
1760 | ||
1761 | static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata) | |
1762 | { | |
1763 | unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG); | |
1764 | temp &= ~GPIO_CFG_EEPR_EN_; | |
1765 | smsc911x_reg_write(pdata, GPIO_CFG, temp); | |
1766 | msleep(1); | |
1767 | } | |
1768 | ||
1769 | static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op) | |
1770 | { | |
1771 | int timeout = 100; | |
1772 | u32 e2cmd; | |
1773 | ||
dffc6b24 | 1774 | SMSC_TRACE(pdata, drv, "op 0x%08x", op); |
fd9abb3d | 1775 | if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) { |
dffc6b24 | 1776 | SMSC_WARN(pdata, drv, "Busy at start"); |
fd9abb3d SG |
1777 | return -EBUSY; |
1778 | } | |
1779 | ||
1780 | e2cmd = op | E2P_CMD_EPC_BUSY_; | |
1781 | smsc911x_reg_write(pdata, E2P_CMD, e2cmd); | |
1782 | ||
1783 | do { | |
1784 | msleep(1); | |
1785 | e2cmd = smsc911x_reg_read(pdata, E2P_CMD); | |
2cf0dbed | 1786 | } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); |
fd9abb3d SG |
1787 | |
1788 | if (!timeout) { | |
dffc6b24 | 1789 | SMSC_TRACE(pdata, drv, "TIMED OUT"); |
fd9abb3d SG |
1790 | return -EAGAIN; |
1791 | } | |
1792 | ||
1793 | if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { | |
1c01a80c | 1794 | SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation"); |
fd9abb3d SG |
1795 | return -EINVAL; |
1796 | } | |
1797 | ||
1798 | return 0; | |
1799 | } | |
1800 | ||
1801 | static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata, | |
1802 | u8 address, u8 *data) | |
1803 | { | |
1804 | u32 op = E2P_CMD_EPC_CMD_READ_ | address; | |
1805 | int ret; | |
1806 | ||
dffc6b24 | 1807 | SMSC_TRACE(pdata, drv, "address 0x%x", address); |
fd9abb3d SG |
1808 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
1809 | ||
1810 | if (!ret) | |
1811 | data[address] = smsc911x_reg_read(pdata, E2P_DATA); | |
1812 | ||
1813 | return ret; | |
1814 | } | |
1815 | ||
1816 | static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata, | |
1817 | u8 address, u8 data) | |
1818 | { | |
1819 | u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; | |
58add9fc | 1820 | u32 temp; |
fd9abb3d SG |
1821 | int ret; |
1822 | ||
dffc6b24 | 1823 | SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data); |
fd9abb3d SG |
1824 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
1825 | ||
1826 | if (!ret) { | |
1827 | op = E2P_CMD_EPC_CMD_WRITE_ | address; | |
1828 | smsc911x_reg_write(pdata, E2P_DATA, (u32)data); | |
58add9fc SG |
1829 | |
1830 | /* Workaround for hardware read-after-write restriction */ | |
1831 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
1832 | ||
fd9abb3d SG |
1833 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
1834 | } | |
1835 | ||
1836 | return ret; | |
1837 | } | |
1838 | ||
1839 | static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev) | |
1840 | { | |
1841 | return SMSC911X_EEPROM_SIZE; | |
1842 | } | |
1843 | ||
1844 | static int smsc911x_ethtool_get_eeprom(struct net_device *dev, | |
1845 | struct ethtool_eeprom *eeprom, u8 *data) | |
1846 | { | |
1847 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1848 | u8 eeprom_data[SMSC911X_EEPROM_SIZE]; | |
1849 | int len; | |
1850 | int i; | |
1851 | ||
1852 | smsc911x_eeprom_enable_access(pdata); | |
1853 | ||
1854 | len = min(eeprom->len, SMSC911X_EEPROM_SIZE); | |
1855 | for (i = 0; i < len; i++) { | |
1856 | int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data); | |
1857 | if (ret < 0) { | |
1858 | eeprom->len = 0; | |
1859 | return ret; | |
1860 | } | |
1861 | } | |
1862 | ||
1863 | memcpy(data, &eeprom_data[eeprom->offset], len); | |
1864 | eeprom->len = len; | |
1865 | return 0; | |
1866 | } | |
1867 | ||
1868 | static int smsc911x_ethtool_set_eeprom(struct net_device *dev, | |
1869 | struct ethtool_eeprom *eeprom, u8 *data) | |
1870 | { | |
1871 | int ret; | |
1872 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1873 | ||
1874 | smsc911x_eeprom_enable_access(pdata); | |
1875 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_); | |
1876 | ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data); | |
1877 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_); | |
1878 | ||
1879 | /* Single byte write, according to man page */ | |
1880 | eeprom->len = 1; | |
1881 | ||
1882 | return ret; | |
1883 | } | |
1884 | ||
cb5b04fe | 1885 | static const struct ethtool_ops smsc911x_ethtool_ops = { |
fd9abb3d SG |
1886 | .get_settings = smsc911x_ethtool_getsettings, |
1887 | .set_settings = smsc911x_ethtool_setsettings, | |
1888 | .get_link = ethtool_op_get_link, | |
1889 | .get_drvinfo = smsc911x_ethtool_getdrvinfo, | |
1890 | .nway_reset = smsc911x_ethtool_nwayreset, | |
1891 | .get_msglevel = smsc911x_ethtool_getmsglevel, | |
1892 | .set_msglevel = smsc911x_ethtool_setmsglevel, | |
1893 | .get_regs_len = smsc911x_ethtool_getregslen, | |
1894 | .get_regs = smsc911x_ethtool_getregs, | |
1895 | .get_eeprom_len = smsc911x_ethtool_get_eeprom_len, | |
1896 | .get_eeprom = smsc911x_ethtool_get_eeprom, | |
1897 | .set_eeprom = smsc911x_ethtool_set_eeprom, | |
1898 | }; | |
1899 | ||
631b7568 SG |
1900 | static const struct net_device_ops smsc911x_netdev_ops = { |
1901 | .ndo_open = smsc911x_open, | |
1902 | .ndo_stop = smsc911x_stop, | |
1903 | .ndo_start_xmit = smsc911x_hard_start_xmit, | |
1904 | .ndo_get_stats = smsc911x_get_stats, | |
1905 | .ndo_set_multicast_list = smsc911x_set_multicast_list, | |
1906 | .ndo_do_ioctl = smsc911x_do_ioctl, | |
635ecaa7 | 1907 | .ndo_change_mtu = eth_change_mtu, |
631b7568 | 1908 | .ndo_validate_addr = eth_validate_addr, |
225ddf49 | 1909 | .ndo_set_mac_address = smsc911x_set_mac_address, |
631b7568 SG |
1910 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1911 | .ndo_poll_controller = smsc911x_poll_controller, | |
1912 | #endif | |
1913 | }; | |
1914 | ||
31f45747 SG |
1915 | /* copies the current mac address from hardware to dev->dev_addr */ |
1916 | static void __devinit smsc911x_read_mac_address(struct net_device *dev) | |
1917 | { | |
1918 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1919 | u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH); | |
1920 | u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL); | |
1921 | ||
1922 | dev->dev_addr[0] = (u8)(mac_low32); | |
1923 | dev->dev_addr[1] = (u8)(mac_low32 >> 8); | |
1924 | dev->dev_addr[2] = (u8)(mac_low32 >> 16); | |
1925 | dev->dev_addr[3] = (u8)(mac_low32 >> 24); | |
1926 | dev->dev_addr[4] = (u8)(mac_high16); | |
1927 | dev->dev_addr[5] = (u8)(mac_high16 >> 8); | |
1928 | } | |
1929 | ||
fd9abb3d SG |
1930 | /* Initializing private device structures, only called from probe */ |
1931 | static int __devinit smsc911x_init(struct net_device *dev) | |
1932 | { | |
1933 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1934 | unsigned int byte_test; | |
1935 | ||
dffc6b24 JP |
1936 | SMSC_TRACE(pdata, probe, "Driver Parameters:"); |
1937 | SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX", | |
1938 | (unsigned long)pdata->ioaddr); | |
1939 | SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq); | |
1940 | SMSC_TRACE(pdata, probe, "PHY will be autodetected."); | |
fd9abb3d | 1941 | |
fd9abb3d | 1942 | spin_lock_init(&pdata->dev_lock); |
35a67edf | 1943 | spin_lock_init(&pdata->mac_lock); |
fd9abb3d SG |
1944 | |
1945 | if (pdata->ioaddr == 0) { | |
dffc6b24 | 1946 | SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000"); |
fd9abb3d SG |
1947 | return -ENODEV; |
1948 | } | |
1949 | ||
1950 | /* Check byte ordering */ | |
1951 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
dffc6b24 | 1952 | SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 1953 | if (byte_test == 0x43218765) { |
dffc6b24 JP |
1954 | SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, " |
1955 | "applying WORD_SWAP"); | |
fd9abb3d SG |
1956 | smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff); |
1957 | ||
1958 | /* 1 dummy read of BYTE_TEST is needed after a write to | |
1959 | * WORD_SWAP before its contents are valid */ | |
1960 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
1961 | ||
1962 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
1963 | } | |
1964 | ||
1965 | if (byte_test != 0x87654321) { | |
dffc6b24 | 1966 | SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 1967 | if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) { |
dffc6b24 JP |
1968 | SMSC_WARN(pdata, probe, |
1969 | "top 16 bits equal to bottom 16 bits"); | |
1970 | SMSC_TRACE(pdata, probe, | |
1971 | "This may mean the chip is set " | |
1972 | "for 32 bit while the bus is reading 16 bit"); | |
fd9abb3d SG |
1973 | } |
1974 | return -ENODEV; | |
1975 | } | |
1976 | ||
1977 | /* Default generation to zero (all workarounds apply) */ | |
1978 | pdata->generation = 0; | |
1979 | ||
1980 | pdata->idrev = smsc911x_reg_read(pdata, ID_REV); | |
1981 | switch (pdata->idrev & 0xFFFF0000) { | |
1982 | case 0x01180000: | |
1983 | case 0x01170000: | |
1984 | case 0x01160000: | |
1985 | case 0x01150000: | |
1986 | /* LAN911[5678] family */ | |
1987 | pdata->generation = pdata->idrev & 0x0000FFFF; | |
1988 | break; | |
1989 | ||
1990 | case 0x118A0000: | |
1991 | case 0x117A0000: | |
1992 | case 0x116A0000: | |
1993 | case 0x115A0000: | |
1994 | /* LAN921[5678] family */ | |
1995 | pdata->generation = 3; | |
1996 | break; | |
1997 | ||
1998 | case 0x92100000: | |
1999 | case 0x92110000: | |
2000 | case 0x92200000: | |
2001 | case 0x92210000: | |
2002 | /* LAN9210/LAN9211/LAN9220/LAN9221 */ | |
2003 | pdata->generation = 4; | |
2004 | break; | |
2005 | ||
2006 | default: | |
dffc6b24 JP |
2007 | SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X", |
2008 | pdata->idrev); | |
fd9abb3d SG |
2009 | return -ENODEV; |
2010 | } | |
2011 | ||
dffc6b24 JP |
2012 | SMSC_TRACE(pdata, probe, |
2013 | "LAN911x identified, idrev: 0x%08X, generation: %d", | |
2014 | pdata->idrev, pdata->generation); | |
fd9abb3d SG |
2015 | |
2016 | if (pdata->generation == 0) | |
dffc6b24 JP |
2017 | SMSC_WARN(pdata, probe, |
2018 | "This driver is not intended for this chip revision"); | |
fd9abb3d | 2019 | |
31f45747 SG |
2020 | /* workaround for platforms without an eeprom, where the mac address |
2021 | * is stored elsewhere and set by the bootloader. This saves the | |
2022 | * mac address before resetting the device */ | |
35a67edf EBS |
2023 | if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) { |
2024 | spin_lock_irq(&pdata->mac_lock); | |
31f45747 | 2025 | smsc911x_read_mac_address(dev); |
35a67edf EBS |
2026 | spin_unlock_irq(&pdata->mac_lock); |
2027 | } | |
31f45747 | 2028 | |
fd9abb3d SG |
2029 | /* Reset the LAN911x */ |
2030 | if (smsc911x_soft_reset(pdata)) | |
2031 | return -ENODEV; | |
2032 | ||
2033 | /* Disable all interrupt sources until we bring the device up */ | |
2034 | smsc911x_reg_write(pdata, INT_EN, 0); | |
2035 | ||
2036 | ether_setup(dev); | |
fd9abb3d | 2037 | dev->flags |= IFF_MULTICAST; |
fd9abb3d | 2038 | netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT); |
631b7568 | 2039 | dev->netdev_ops = &smsc911x_netdev_ops; |
fd9abb3d SG |
2040 | dev->ethtool_ops = &smsc911x_ethtool_ops; |
2041 | ||
fd9abb3d SG |
2042 | return 0; |
2043 | } | |
2044 | ||
2045 | static int __devexit smsc911x_drv_remove(struct platform_device *pdev) | |
2046 | { | |
2047 | struct net_device *dev; | |
2048 | struct smsc911x_data *pdata; | |
2049 | struct resource *res; | |
2050 | ||
2051 | dev = platform_get_drvdata(pdev); | |
2052 | BUG_ON(!dev); | |
2053 | pdata = netdev_priv(dev); | |
2054 | BUG_ON(!pdata); | |
2055 | BUG_ON(!pdata->ioaddr); | |
2056 | BUG_ON(!pdata->phy_dev); | |
2057 | ||
dffc6b24 | 2058 | SMSC_TRACE(pdata, ifdown, "Stopping driver"); |
fd9abb3d SG |
2059 | |
2060 | phy_disconnect(pdata->phy_dev); | |
2061 | pdata->phy_dev = NULL; | |
2062 | mdiobus_unregister(pdata->mii_bus); | |
2063 | mdiobus_free(pdata->mii_bus); | |
2064 | ||
2065 | platform_set_drvdata(pdev, NULL); | |
2066 | unregister_netdev(dev); | |
2067 | free_irq(dev->irq, dev); | |
2068 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
2069 | "smsc911x-memory"); | |
2070 | if (!res) | |
d4522739 | 2071 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
fd9abb3d | 2072 | |
39424539 | 2073 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2074 | |
2075 | iounmap(pdata->ioaddr); | |
2076 | ||
2077 | free_netdev(dev); | |
2078 | ||
2079 | return 0; | |
2080 | } | |
2081 | ||
c326de88 MP |
2082 | /* standard register acces */ |
2083 | static const struct smsc911x_ops standard_smsc911x_ops = { | |
2084 | .reg_read = __smsc911x_reg_read, | |
2085 | .reg_write = __smsc911x_reg_write, | |
2086 | .rx_readfifo = smsc911x_rx_readfifo, | |
2087 | .tx_writefifo = smsc911x_tx_writefifo, | |
2088 | }; | |
2089 | ||
2090 | /* shifted register access */ | |
2091 | static const struct smsc911x_ops shifted_smsc911x_ops = { | |
2092 | .reg_read = __smsc911x_reg_read_shift, | |
2093 | .reg_write = __smsc911x_reg_write_shift, | |
2094 | .rx_readfifo = smsc911x_rx_readfifo_shift, | |
2095 | .tx_writefifo = smsc911x_tx_writefifo_shift, | |
2096 | }; | |
2097 | ||
fd9abb3d SG |
2098 | static int __devinit smsc911x_drv_probe(struct platform_device *pdev) |
2099 | { | |
2100 | struct net_device *dev; | |
2101 | struct smsc911x_data *pdata; | |
2107fb8b | 2102 | struct smsc911x_platform_config *config = pdev->dev.platform_data; |
61307ed8 | 2103 | struct resource *res, *irq_res; |
fd9abb3d | 2104 | unsigned int intcfg = 0; |
61307ed8 | 2105 | int res_size, irq_flags; |
fd9abb3d | 2106 | int retval; |
fd9abb3d | 2107 | |
dffc6b24 | 2108 | pr_info("Driver version %s\n", SMSC_DRV_VERSION); |
fd9abb3d | 2109 | |
2107fb8b SG |
2110 | /* platform data specifies irq & dynamic bus configuration */ |
2111 | if (!pdev->dev.platform_data) { | |
dffc6b24 | 2112 | pr_warn("platform_data not provided\n"); |
2107fb8b SG |
2113 | retval = -ENODEV; |
2114 | goto out_0; | |
2115 | } | |
2116 | ||
fd9abb3d SG |
2117 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2118 | "smsc911x-memory"); | |
2119 | if (!res) | |
2120 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2121 | if (!res) { | |
dffc6b24 | 2122 | pr_warn("Could not allocate resource\n"); |
fd9abb3d SG |
2123 | retval = -ENODEV; |
2124 | goto out_0; | |
2125 | } | |
39424539 | 2126 | res_size = resource_size(res); |
fd9abb3d | 2127 | |
61307ed8 SG |
2128 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2129 | if (!irq_res) { | |
dffc6b24 | 2130 | pr_warn("Could not allocate irq resource\n"); |
61307ed8 SG |
2131 | retval = -ENODEV; |
2132 | goto out_0; | |
2133 | } | |
2134 | ||
fd9abb3d SG |
2135 | if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) { |
2136 | retval = -EBUSY; | |
2137 | goto out_0; | |
2138 | } | |
2139 | ||
2140 | dev = alloc_etherdev(sizeof(struct smsc911x_data)); | |
2141 | if (!dev) { | |
dffc6b24 | 2142 | pr_warn("Could not allocate device\n"); |
fd9abb3d SG |
2143 | retval = -ENOMEM; |
2144 | goto out_release_io_1; | |
2145 | } | |
2146 | ||
2147 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2148 | ||
2149 | pdata = netdev_priv(dev); | |
2150 | ||
61307ed8 SG |
2151 | dev->irq = irq_res->start; |
2152 | irq_flags = irq_res->flags & IRQF_TRIGGER_MASK; | |
fd9abb3d SG |
2153 | pdata->ioaddr = ioremap_nocache(res->start, res_size); |
2154 | ||
2107fb8b SG |
2155 | /* copy config parameters across to pdata */ |
2156 | memcpy(&pdata->config, config, sizeof(pdata->config)); | |
fd9abb3d SG |
2157 | |
2158 | pdata->dev = dev; | |
2159 | pdata->msg_enable = ((1 << debug) - 1); | |
2160 | ||
2161 | if (pdata->ioaddr == NULL) { | |
dffc6b24 | 2162 | SMSC_WARN(pdata, probe, "Error smsc911x base address invalid"); |
fd9abb3d SG |
2163 | retval = -ENOMEM; |
2164 | goto out_free_netdev_2; | |
2165 | } | |
2166 | ||
c326de88 MP |
2167 | /* assume standard, non-shifted, access to HW registers */ |
2168 | pdata->ops = &standard_smsc911x_ops; | |
2169 | /* apply the right access if shifting is needed */ | |
2170 | if (config->shift) | |
2171 | pdata->ops = &shifted_smsc911x_ops; | |
2172 | ||
fd9abb3d SG |
2173 | retval = smsc911x_init(dev); |
2174 | if (retval < 0) | |
2175 | goto out_unmap_io_3; | |
2176 | ||
2177 | /* configure irq polarity and type before connecting isr */ | |
2107fb8b | 2178 | if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH) |
fd9abb3d SG |
2179 | intcfg |= INT_CFG_IRQ_POL_; |
2180 | ||
2107fb8b | 2181 | if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL) |
fd9abb3d SG |
2182 | intcfg |= INT_CFG_IRQ_TYPE_; |
2183 | ||
2184 | smsc911x_reg_write(pdata, INT_CFG, intcfg); | |
2185 | ||
2186 | /* Ensure interrupts are globally disabled before connecting ISR */ | |
2187 | smsc911x_reg_write(pdata, INT_EN, 0); | |
2188 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); | |
2189 | ||
61307ed8 | 2190 | retval = request_irq(dev->irq, smsc911x_irqhandler, |
e81259b4 | 2191 | irq_flags | IRQF_SHARED, dev->name, dev); |
fd9abb3d | 2192 | if (retval) { |
dffc6b24 JP |
2193 | SMSC_WARN(pdata, probe, |
2194 | "Unable to claim requested irq: %d", dev->irq); | |
fd9abb3d SG |
2195 | goto out_unmap_io_3; |
2196 | } | |
2197 | ||
2198 | platform_set_drvdata(pdev, dev); | |
2199 | ||
2200 | retval = register_netdev(dev); | |
2201 | if (retval) { | |
dffc6b24 | 2202 | SMSC_WARN(pdata, probe, "Error %i registering device", retval); |
fd9abb3d SG |
2203 | goto out_unset_drvdata_4; |
2204 | } else { | |
dffc6b24 JP |
2205 | SMSC_TRACE(pdata, probe, |
2206 | "Network interface: \"%s\"", dev->name); | |
fd9abb3d SG |
2207 | } |
2208 | ||
fd9abb3d SG |
2209 | retval = smsc911x_mii_init(pdev, dev); |
2210 | if (retval) { | |
dffc6b24 | 2211 | SMSC_WARN(pdata, probe, "Error %i initialising mii", retval); |
fd9abb3d SG |
2212 | goto out_unregister_netdev_5; |
2213 | } | |
2214 | ||
2215 | spin_lock_irq(&pdata->mac_lock); | |
2216 | ||
2217 | /* Check if mac address has been specified when bringing interface up */ | |
2218 | if (is_valid_ether_addr(dev->dev_addr)) { | |
225ddf49 | 2219 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 JP |
2220 | SMSC_TRACE(pdata, probe, |
2221 | "MAC Address is specified by configuration"); | |
aace4959 ML |
2222 | } else if (is_valid_ether_addr(pdata->config.mac)) { |
2223 | memcpy(dev->dev_addr, pdata->config.mac, 6); | |
dffc6b24 JP |
2224 | SMSC_TRACE(pdata, probe, |
2225 | "MAC Address specified by platform data"); | |
fd9abb3d SG |
2226 | } else { |
2227 | /* Try reading mac address from device. if EEPROM is present | |
2228 | * it will already have been set */ | |
62747cd2 | 2229 | smsc_get_mac(dev); |
fd9abb3d SG |
2230 | |
2231 | if (is_valid_ether_addr(dev->dev_addr)) { | |
2232 | /* eeprom values are valid so use them */ | |
dffc6b24 JP |
2233 | SMSC_TRACE(pdata, probe, |
2234 | "Mac Address is read from LAN911x EEPROM"); | |
fd9abb3d SG |
2235 | } else { |
2236 | /* eeprom values are invalid, generate random MAC */ | |
2237 | random_ether_addr(dev->dev_addr); | |
225ddf49 | 2238 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 JP |
2239 | SMSC_TRACE(pdata, probe, |
2240 | "MAC Address is set to random_ether_addr"); | |
fd9abb3d SG |
2241 | } |
2242 | } | |
2243 | ||
2244 | spin_unlock_irq(&pdata->mac_lock); | |
2245 | ||
dffc6b24 | 2246 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
fd9abb3d SG |
2247 | |
2248 | return 0; | |
2249 | ||
2250 | out_unregister_netdev_5: | |
2251 | unregister_netdev(dev); | |
2252 | out_unset_drvdata_4: | |
2253 | platform_set_drvdata(pdev, NULL); | |
2254 | free_irq(dev->irq, dev); | |
2255 | out_unmap_io_3: | |
2256 | iounmap(pdata->ioaddr); | |
2257 | out_free_netdev_2: | |
2258 | free_netdev(dev); | |
2259 | out_release_io_1: | |
39424539 | 2260 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2261 | out_0: |
2262 | return retval; | |
2263 | } | |
2264 | ||
b6907b0c DM |
2265 | #ifdef CONFIG_PM |
2266 | /* This implementation assumes the devices remains powered on its VDDVARIO | |
2267 | * pins during suspend. */ | |
2268 | ||
6cb87823 DM |
2269 | /* TODO: implement freeze/thaw callbacks for hibernation.*/ |
2270 | ||
2271 | static int smsc911x_suspend(struct device *dev) | |
b6907b0c | 2272 | { |
6cb87823 DM |
2273 | struct net_device *ndev = dev_get_drvdata(dev); |
2274 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c DM |
2275 | |
2276 | /* enable wake on LAN, energy detection and the external PME | |
2277 | * signal. */ | |
2278 | smsc911x_reg_write(pdata, PMT_CTRL, | |
2279 | PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ | | |
2280 | PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_); | |
2281 | ||
2282 | return 0; | |
2283 | } | |
2284 | ||
6cb87823 | 2285 | static int smsc911x_resume(struct device *dev) |
b6907b0c | 2286 | { |
6cb87823 DM |
2287 | struct net_device *ndev = dev_get_drvdata(dev); |
2288 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c DM |
2289 | unsigned int to = 100; |
2290 | ||
2291 | /* Note 3.11 from the datasheet: | |
2292 | * "When the LAN9220 is in a power saving state, a write of any | |
2293 | * data to the BYTE_TEST register will wake-up the device." | |
2294 | */ | |
2295 | smsc911x_reg_write(pdata, BYTE_TEST, 0); | |
2296 | ||
2297 | /* poll the READY bit in PMT_CTRL. Any other access to the device is | |
2298 | * forbidden while this bit isn't set. Try for 100ms and return -EIO | |
2299 | * if it failed. */ | |
2300 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to) | |
2301 | udelay(1000); | |
2302 | ||
2303 | return (to == 0) ? -EIO : 0; | |
2304 | } | |
2305 | ||
47145210 | 2306 | static const struct dev_pm_ops smsc911x_pm_ops = { |
6cb87823 DM |
2307 | .suspend = smsc911x_suspend, |
2308 | .resume = smsc911x_resume, | |
2309 | }; | |
2310 | ||
2311 | #define SMSC911X_PM_OPS (&smsc911x_pm_ops) | |
2312 | ||
b6907b0c | 2313 | #else |
6cb87823 | 2314 | #define SMSC911X_PM_OPS NULL |
b6907b0c DM |
2315 | #endif |
2316 | ||
fd9abb3d SG |
2317 | static struct platform_driver smsc911x_driver = { |
2318 | .probe = smsc911x_drv_probe, | |
df911e2d | 2319 | .remove = __devexit_p(smsc911x_drv_remove), |
fd9abb3d | 2320 | .driver = { |
6cb87823 DM |
2321 | .name = SMSC_CHIPNAME, |
2322 | .owner = THIS_MODULE, | |
2323 | .pm = SMSC911X_PM_OPS, | |
fd9abb3d SG |
2324 | }, |
2325 | }; | |
2326 | ||
2327 | /* Entry point for loading the module */ | |
2328 | static int __init smsc911x_init_module(void) | |
2329 | { | |
62747cd2 | 2330 | SMSC_INITIALIZE(); |
fd9abb3d SG |
2331 | return platform_driver_register(&smsc911x_driver); |
2332 | } | |
2333 | ||
2334 | /* entry point for unloading the module */ | |
2335 | static void __exit smsc911x_cleanup_module(void) | |
2336 | { | |
2337 | platform_driver_unregister(&smsc911x_driver); | |
2338 | } | |
2339 | ||
2340 | module_init(smsc911x_init_module); | |
2341 | module_exit(smsc911x_cleanup_module); |