[mirror_ubuntu-artful-kernel.git] / drivers / net / stmmac / common.h

/*******************************************************************************
  STMMAC Common Header File

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/netdevice.h>
#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
#define STMMAC_VLAN_TAG_USED
#include <linux/if_vlan.h>
#endif

#include "descs.h"

#undef CHIP_DEBUG_PRINT
/* Turn-on extra printk debug for MAC core, dma and descriptors */
/* #define CHIP_DEBUG_PRINT */

#ifdef CHIP_DEBUG_PRINT
#define CHIP_DBG(fmt, args...)  printk(fmt, ## args)
#else
#define CHIP_DBG(fmt, args...)  do { } while (0)
#endif

#undef FRAME_FILTER_DEBUG
/* #define FRAME_FILTER_DEBUG */

struct stmmac_extra_stats {
	/* Transmit errors */
	unsigned long tx_underflow ____cacheline_aligned;
	unsigned long tx_carrier;
	unsigned long tx_losscarrier;
	unsigned long tx_heartbeat;
	unsigned long tx_deferred;
	unsigned long tx_vlan;
	unsigned long tx_jabber;
	unsigned long tx_frame_flushed;
	unsigned long tx_payload_error;
	unsigned long tx_ip_header_error;
	/* Receive errors */
	unsigned long rx_desc;
	unsigned long rx_partial;
	unsigned long rx_runt;
	unsigned long rx_toolong;
	unsigned long rx_collision;
	unsigned long rx_crc;
	unsigned long rx_length;
	unsigned long rx_mii;
	unsigned long rx_multicast;
	unsigned long rx_gmac_overflow;
	unsigned long rx_watchdog;
	unsigned long da_rx_filter_fail;
	unsigned long sa_rx_filter_fail;
	unsigned long rx_missed_cntr;
	unsigned long rx_overflow_cntr;
	unsigned long rx_vlan;
	/* Tx/Rx IRQ errors */
	unsigned long tx_undeflow_irq;
	unsigned long tx_process_stopped_irq;
	unsigned long tx_jabber_irq;
	unsigned long rx_overflow_irq;
	unsigned long rx_buf_unav_irq;
	unsigned long rx_process_stopped_irq;
	unsigned long rx_watchdog_irq;
	unsigned long tx_early_irq;
	unsigned long fatal_bus_error_irq;
	/* Extra info */
	unsigned long threshold;
	unsigned long tx_pkt_n;
	unsigned long rx_pkt_n;
	unsigned long poll_n;
	unsigned long sched_timer_n;
	unsigned long normal_irq_n;
};

#define HASH_TABLE_SIZE 64
#define PAUSE_TIME 0x200

/* Flow Control defines */
#define FLOW_OFF	0
#define FLOW_RX		1
#define FLOW_TX		2
#define FLOW_AUTO	(FLOW_TX | FLOW_RX)

#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */

#define HW_CSUM 1
#define NO_HW_CSUM 0
enum rx_frame_status { /* IPC status */
	good_frame = 0,
	discard_frame = 1,
	csum_none = 2,
};

enum tx_dma_irq_status {
	tx_hard_error = 1,
	tx_hard_error_bump_tc = 2,
	handle_tx_rx = 3,
};

/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
#define BUF_SIZE_16KiB 16384
#define BUF_SIZE_8KiB 8192
#define BUF_SIZE_4KiB 4096
#define BUF_SIZE_2KiB 2048

/* Power Down and WOL */
#define PMT_NOT_SUPPORTED 0
#define PMT_SUPPORTED 1

/* Common MAC defines */
#define MAC_CTRL_REG		0x00000000	/* MAC Control */
#define MAC_ENABLE_TX		0x00000008	/* Transmitter Enable */
#define MAC_RNABLE_RX		0x00000004	/* Receiver Enable */

/* MAC Management Counters register */
#define MMC_CONTROL		0x00000100	/* MMC Control */
#define MMC_HIGH_INTR		0x00000104	/* MMC High Interrupt */
#define MMC_LOW_INTR		0x00000108	/* MMC Low Interrupt */
#define MMC_HIGH_INTR_MASK	0x0000010c	/* MMC High Interrupt Mask */
#define MMC_LOW_INTR_MASK	0x00000110	/* MMC Low Interrupt Mask */

#define MMC_CONTROL_MAX_FRM_MASK	0x0003ff8	/* Maximum Frame Size */
#define MMC_CONTROL_MAX_FRM_SHIFT	3
#define MMC_CONTROL_MAX_FRAME		0x7FF

struct stmmac_desc_ops {
	/* DMA RX descriptor ring initialization */
	void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
			      int disable_rx_ic);
	/* DMA TX descriptor ring initialization */
	void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);

	/* Invoked by the xmit function to prepare the tx descriptor */
	void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
				 int csum_flag);
	/* Set/get the owner of the descriptor */
	void (*set_tx_owner) (struct dma_desc *p);
	int (*get_tx_owner) (struct dma_desc *p);
	/* Invoked by the xmit function to close the tx descriptor */
	void (*close_tx_desc) (struct dma_desc *p);
	/* Clean the tx descriptor as soon as the tx irq is received */
	void (*release_tx_desc) (struct dma_desc *p);
	/* Clear interrupt on tx frame completion. When this bit is
	 * set an interrupt happens as soon as the frame is transmitted */
	void (*clear_tx_ic) (struct dma_desc *p);
	/* Last tx segment reports the transmit status */
	int (*get_tx_ls) (struct dma_desc *p);
	/* Return the transmit status looking at the TDES1 */
	int (*tx_status) (void *data, struct stmmac_extra_stats *x,
			  struct dma_desc *p, unsigned long ioaddr);
	/* Get the buffer size from the descriptor */
	int (*get_tx_len) (struct dma_desc *p);
	/* Handle extra events on specific interrupts hw dependent */
	int (*get_rx_owner) (struct dma_desc *p);
	void (*set_rx_owner) (struct dma_desc *p);
	/* Get the receive frame size */
	int (*get_rx_frame_len) (struct dma_desc *p);
	/* Return the reception status looking at the RDES1 */
	int (*rx_status) (void *data, struct stmmac_extra_stats *x,
			  struct dma_desc *p);
};

struct stmmac_dma_ops {
	/* DMA core initialization */
	int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
	/* Dump DMA registers */
	void (*dump_regs) (unsigned long ioaddr);
	/* Set tx/rx threshold in the csr6 register
	 * An invalid value enables the store-and-forward mode */
	void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
	/* To track extra statistic (if supported) */
	void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
				   unsigned long ioaddr);
	void (*enable_dma_transmission) (unsigned long ioaddr);
	void (*enable_dma_irq) (unsigned long ioaddr);
	void (*disable_dma_irq) (unsigned long ioaddr);
	void (*start_tx) (unsigned long ioaddr);
	void (*stop_tx) (unsigned long ioaddr);
	void (*start_rx) (unsigned long ioaddr);
	void (*stop_rx) (unsigned long ioaddr);
	int (*dma_interrupt) (unsigned long ioaddr,
			      struct stmmac_extra_stats *x);
};

struct stmmac_ops {
	/* MAC core initialization */
	void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
	/* Dump MAC registers */
	void (*dump_regs) (unsigned long ioaddr);
	/* Handle extra events on specific interrupts hw dependent */
	void (*host_irq_status) (unsigned long ioaddr);
	/* Multicast filter setting */
	void (*set_filter) (struct net_device *dev);
	/* Flow control setting */
	void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex,
			   unsigned int fc, unsigned int pause_time);
	/* Set power management mode (e.g. magic frame) */
	void (*pmt) (unsigned long ioaddr, unsigned long mode);
	/* Set/Get Unicast MAC addresses */
	void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr,
			       unsigned int reg_n);
	void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr,
			       unsigned int reg_n);
};

struct mac_link {
	int port;
	int duplex;
	int speed;
};

struct mii_regs {
	unsigned int addr;	/* MII Address */
	unsigned int data;	/* MII Data */
};

struct mac_device_info {
	struct stmmac_ops	*mac;
	struct stmmac_desc_ops	*desc;
	struct stmmac_dma_ops	*dma;
	unsigned int pmt;	/* support Power-Down */
	struct mii_regs mii;	/* MII register Addresses */
	struct mac_link link;
};

struct mac_device_info *dwmac1000_setup(unsigned long addr);
struct mac_device_info *dwmac100_setup(unsigned long addr);

extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
				unsigned int high, unsigned int low);
extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
				unsigned int high, unsigned int low);
extern void dwmac_dma_flush_tx_fifo(unsigned long ioaddr);
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	STMMAC Common Header File
	3
	4	Copyright (C) 2007-2009 STMicroelectronics Ltd
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	23	*******************************************************************************/
	24
5e33c791	25	#include <linux/netdevice.h>
8f617541 GC	26	#if defined(CONFIG_VLAN_8021Q) \|\| defined(CONFIG_VLAN_8021Q_MODULE)
	27	#define STMMAC_VLAN_TAG_USED
	28	#include <linux/if_vlan.h>
	29	#endif
	30
56b106ae GC	31	#include "descs.h"
	32
	33	#undef CHIP_DEBUG_PRINT
	34	/* Turn-on extra printk debug for MAC core, dma and descriptors */
	35	/* #define CHIP_DEBUG_PRINT */
	36
	37	#ifdef CHIP_DEBUG_PRINT
	38	#define CHIP_DBG(fmt, args...) printk(fmt, ## args)
	39	#else
	40	#define CHIP_DBG(fmt, args...) do { } while (0)
	41	#endif
	42
	43	#undef FRAME_FILTER_DEBUG
	44	/* #define FRAME_FILTER_DEBUG */
47dd7a54	45
47dd7a54 GC	46	struct stmmac_extra_stats {
	47	/* Transmit errors */
	48	unsigned long tx_underflow ____cacheline_aligned;
	49	unsigned long tx_carrier;
	50	unsigned long tx_losscarrier;
	51	unsigned long tx_heartbeat;
	52	unsigned long tx_deferred;
	53	unsigned long tx_vlan;
	54	unsigned long tx_jabber;
	55	unsigned long tx_frame_flushed;
	56	unsigned long tx_payload_error;
	57	unsigned long tx_ip_header_error;
	58	/* Receive errors */
	59	unsigned long rx_desc;
	60	unsigned long rx_partial;
	61	unsigned long rx_runt;
	62	unsigned long rx_toolong;
	63	unsigned long rx_collision;
	64	unsigned long rx_crc;
1b924032	65	unsigned long rx_length;
47dd7a54 GC	66	unsigned long rx_mii;
	67	unsigned long rx_multicast;
	68	unsigned long rx_gmac_overflow;
	69	unsigned long rx_watchdog;
	70	unsigned long da_rx_filter_fail;
	71	unsigned long sa_rx_filter_fail;
	72	unsigned long rx_missed_cntr;
	73	unsigned long rx_overflow_cntr;
	74	unsigned long rx_vlan;
	75	/* Tx/Rx IRQ errors */
	76	unsigned long tx_undeflow_irq;
	77	unsigned long tx_process_stopped_irq;
	78	unsigned long tx_jabber_irq;
	79	unsigned long rx_overflow_irq;
	80	unsigned long rx_buf_unav_irq;
	81	unsigned long rx_process_stopped_irq;
	82	unsigned long rx_watchdog_irq;
	83	unsigned long tx_early_irq;
	84	unsigned long fatal_bus_error_irq;
	85	/* Extra info */
	86	unsigned long threshold;
	87	unsigned long tx_pkt_n;
	88	unsigned long rx_pkt_n;
	89	unsigned long poll_n;
	90	unsigned long sched_timer_n;
	91	unsigned long normal_irq_n;
	92	};
	93
aec7ff27 GC	94	#define HASH_TABLE_SIZE 64
	95	#define PAUSE_TIME 0x200
	96
	97	/* Flow Control defines */
	98	#define FLOW_OFF 0
	99	#define FLOW_RX 1
	100	#define FLOW_TX 2
	101	#define FLOW_AUTO (FLOW_TX \| FLOW_RX)
	102
	103	#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
	104
	105	#define HW_CSUM 1
	106	#define NO_HW_CSUM 0
	107	enum rx_frame_status { /* IPC status */
47dd7a54 GC	108	good_frame = 0,
	109	discard_frame = 1,
	110	csum_none = 2,
	111	};
	112
aec7ff27 GC	113	enum tx_dma_irq_status {
	114	tx_hard_error = 1,
	115	tx_hard_error_bump_tc = 2,
	116	handle_tx_rx = 3,
	117	};
47dd7a54	118
aec7ff27 GC	119	/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
	120	#define BUF_SIZE_16KiB 16384
	121	#define BUF_SIZE_8KiB 8192
	122	#define BUF_SIZE_4KiB 4096
	123	#define BUF_SIZE_2KiB 2048
47dd7a54	124
aec7ff27 GC	125	/* Power Down and WOL */
	126	#define PMT_NOT_SUPPORTED 0
	127	#define PMT_SUPPORTED 1
47dd7a54	128
aec7ff27 GC	129	/* Common MAC defines */
	130	#define MAC_CTRL_REG 0x00000000 /* MAC Control */
	131	#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
	132	#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54	133
aec7ff27 GC	134	/* MAC Management Counters register */
	135	#define MMC_CONTROL 0x00000100 /* MMC Control */
	136	#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
	137	#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
	138	#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
	139	#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
47dd7a54	140
aec7ff27 GC	141	#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
	142	#define MMC_CONTROL_MAX_FRM_SHIFT 3
	143	#define MMC_CONTROL_MAX_FRAME 0x7FF
47dd7a54	144
db98a0b0 GC	145	struct stmmac_desc_ops {
db98a0b0 GC	146	/* DMA RX descriptor ring initialization */
47dd7a54	147	void (init_rx_desc) (struct dma_desc p, unsigned int ring_size,
db98a0b0 GC	148	int disable_rx_ic);
db98a0b0 GC	149	/* DMA TX descriptor ring initialization */
47dd7a54 GC	150	void (init_tx_desc) (struct dma_desc p, unsigned int ring_size);
	151
	152	/* Invoked by the xmit function to prepare the tx descriptor */
	153	void (prepare_tx_desc) (struct dma_desc p, int is_fs, int len,
	154	int csum_flag);
	155	/* Set/get the owner of the descriptor */
	156	void (set_tx_owner) (struct dma_desc p);
	157	int (get_tx_owner) (struct dma_desc p);
	158	/* Invoked by the xmit function to close the tx descriptor */
	159	void (close_tx_desc) (struct dma_desc p);
	160	/* Clean the tx descriptor as soon as the tx irq is received */
	161	void (release_tx_desc) (struct dma_desc p);
	162	/* Clear interrupt on tx frame completion. When this bit is
	163	* set an interrupt happens as soon as the frame is transmitted */
	164	void (clear_tx_ic) (struct dma_desc p);
	165	/* Last tx segment reports the transmit status */
	166	int (get_tx_ls) (struct dma_desc p);
	167	/* Return the transmit status looking at the TDES1 */
	168	int (tx_status) (void data, struct stmmac_extra_stats *x,
	169	struct dma_desc *p, unsigned long ioaddr);
	170	/* Get the buffer size from the descriptor */
	171	int (get_tx_len) (struct dma_desc p);
	172	/* Handle extra events on specific interrupts hw dependent */
47dd7a54 GC	173	int (get_rx_owner) (struct dma_desc p);
	174	void (set_rx_owner) (struct dma_desc p);
	175	/* Get the receive frame size */
	176	int (get_rx_frame_len) (struct dma_desc p);
	177	/* Return the reception status looking at the RDES1 */
	178	int (rx_status) (void data, struct stmmac_extra_stats *x,
	179	struct dma_desc *p);
db98a0b0 GC	180	};
	181
	182	struct stmmac_dma_ops {
	183	/* DMA core initialization */
	184	int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
	185	/* Dump DMA registers */
	186	void (*dump_regs) (unsigned long ioaddr);
	187	/* Set tx/rx threshold in the csr6 register
	188	* An invalid value enables the store-and-forward mode */
	189	void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
	190	/* To track extra statistic (if supported) */
	191	void (dma_diagnostic_fr) (void data, struct stmmac_extra_stats *x,
	192	unsigned long ioaddr);
aec7ff27 GC	193	void (*enable_dma_transmission) (unsigned long ioaddr);
	194	void (*enable_dma_irq) (unsigned long ioaddr);
	195	void (*disable_dma_irq) (unsigned long ioaddr);
	196	void (*start_tx) (unsigned long ioaddr);
	197	void (*stop_tx) (unsigned long ioaddr);
	198	void (*start_rx) (unsigned long ioaddr);
	199	void (*stop_rx) (unsigned long ioaddr);
	200	int (*dma_interrupt) (unsigned long ioaddr,
	201	struct stmmac_extra_stats *x);
db98a0b0 GC	202	};
	203
	204	struct stmmac_ops {
	205	/* MAC core initialization */
	206	void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
	207	/* Dump MAC registers */
	208	void (*dump_regs) (unsigned long ioaddr);
	209	/* Handle extra events on specific interrupts hw dependent */
	210	void (*host_irq_status) (unsigned long ioaddr);
47dd7a54 GC	211	/* Multicast filter setting */
	212	void (set_filter) (struct net_device dev);
	213	/* Flow control setting */
	214	void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex,
	215	unsigned int fc, unsigned int pause_time);
	216	/* Set power management mode (e.g. magic frame) */
	217	void (*pmt) (unsigned long ioaddr, unsigned long mode);
	218	/* Set/Get Unicast MAC addresses */
	219	void (set_umac_addr) (unsigned long ioaddr, unsigned char addr,
db98a0b0	220	unsigned int reg_n);
47dd7a54	221	void (get_umac_addr) (unsigned long ioaddr, unsigned char addr,
db98a0b0	222	unsigned int reg_n);
47dd7a54 GC	223	};
	224
	225	struct mac_link {
	226	int port;
	227	int duplex;
	228	int speed;
	229	};
	230
	231	struct mii_regs {
	232	unsigned int addr; /* MII Address */
	233	unsigned int data; /* MII Data */
	234	};
	235
47dd7a54	236	struct mac_device_info {
db98a0b0 GC	237	struct stmmac_ops *mac;
	238	struct stmmac_desc_ops *desc;
	239	struct stmmac_dma_ops *dma;
	240	unsigned int pmt; /* support Power-Down */
	241	struct mii_regs mii; /* MII register Addresses */
	242	struct mac_link link;
47dd7a54 GC	243	};
47dd7a54 GC	244
21d437cc	245	struct mac_device_info *dwmac1000_setup(unsigned long addr);
7e848ae1	246	struct mac_device_info *dwmac100_setup(unsigned long addr);
aec7ff27 GC	247
	248	extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
	249	unsigned int high, unsigned int low);
	250	extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
	251	unsigned int high, unsigned int low);
688911c2	252	extern void dwmac_dma_flush_tx_fifo(unsigned long ioaddr);