[mirror_ubuntu-zesty-kernel.git] / drivers / net / stmmac / dwmac100.c

/*******************************************************************************
  This is the driver for the MAC 10/100 on-chip Ethernet controller
  currently tested on all the ST boards based on STb7109 and stx7200 SoCs.

  DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
  this code.

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/crc32.h>
#include <linux/mii.h>
#include <linux/phy.h>
#include <linux/slab.h>

#include "common.h"
#include "dwmac100.h"
#include "dwmac_dma.h"

#undef DWMAC100_DEBUG
/*#define DWMAC100_DEBUG*/
#ifdef DWMAC100_DEBUG
#define DBG(fmt, args...)  printk(fmt, ## args)
#else
#define DBG(fmt, args...)  do { } while (0)
#endif

static void dwmac100_core_init(unsigned long ioaddr)
{
	u32 value = readl(ioaddr + MAC_CONTROL);

	writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);

#ifdef STMMAC_VLAN_TAG_USED
	writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
#endif
	return;
}

static void dwmac100_dump_mac_regs(unsigned long ioaddr)
{
	pr_info("\t----------------------------------------------\n"
		"\t  DWMAC 100 CSR (base addr = 0x%8x)\n"
		"\t----------------------------------------------\n",
		(unsigned int)ioaddr);
	pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
		readl(ioaddr + MAC_CONTROL));
	pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
		readl(ioaddr + MAC_ADDR_HIGH));
	pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
		readl(ioaddr + MAC_ADDR_LOW));
	pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
		MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
	pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
		MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
	pr_info("\tflow control (offset 0x%x): 0x%08x\n",
		MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
	pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
		readl(ioaddr + MAC_VLAN1));
	pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
		readl(ioaddr + MAC_VLAN2));
	pr_info("\n\tMAC management counter registers\n");
	pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
		MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
	pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
		MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
	pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
		MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
	pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
		MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
	pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
		MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
	return;
}

static int dwmac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
			   u32 dma_rx)
{
	u32 value = readl(ioaddr + DMA_BUS_MODE);
	/* DMA SW reset */
	value |= DMA_BUS_MODE_SFT_RESET;
	writel(value, ioaddr + DMA_BUS_MODE);
	do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));

	/* Enable Application Access by writing to DMA CSR0 */
	writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),
	       ioaddr + DMA_BUS_MODE);

	/* Mask interrupts by writing to CSR7 */
	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);

	/* The base address of the RX/TX descriptor lists must be written into
	 * DMA CSR3 and CSR4, respectively. */
	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);

	return 0;
}

/* Store and Forward capability is not used at all..
 * The transmit threshold can be programmed by
 * setting the TTC bits in the DMA control register.*/
static void dwmac100_dma_operation_mode(unsigned long ioaddr, int txmode,
				      int rxmode)
{
	u32 csr6 = readl(ioaddr + DMA_CONTROL);

	if (txmode <= 32)
		csr6 |= DMA_CONTROL_TTC_32;
	else if (txmode <= 64)
		csr6 |= DMA_CONTROL_TTC_64;
	else
		csr6 |= DMA_CONTROL_TTC_128;

	writel(csr6, ioaddr + DMA_CONTROL);

	return;
}

static void dwmac100_dump_dma_regs(unsigned long ioaddr)
{
	int i;

	DBG(KERN_DEBUG "DWMAC 100 DMA CSR \n");
	for (i = 0; i < 9; i++)
		pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
		       (DMA_BUS_MODE + i * 4),
		       readl(ioaddr + DMA_BUS_MODE + i * 4));
	DBG(KERN_DEBUG "\t CSR20 (offset 0x%x): 0x%08x\n",
	    DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
	DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n",
	    DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
	return;
}

/* DMA controller has two counters to track the number of
 * the receive missed frames. */
static void dwmac100_dma_diagnostic_fr(void *data,
				     struct stmmac_extra_stats *x,
				     unsigned long ioaddr)
{
	struct net_device_stats *stats = (struct net_device_stats *)data;
	u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);

	if (unlikely(csr8)) {
		if (csr8 & DMA_MISSED_FRAME_OVE) {
			stats->rx_over_errors += 0x800;
			x->rx_overflow_cntr += 0x800;
		} else {
			unsigned int ove_cntr;
			ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
			stats->rx_over_errors += ove_cntr;
			x->rx_overflow_cntr += ove_cntr;
		}

		if (csr8 & DMA_MISSED_FRAME_OVE_M) {
			stats->rx_missed_errors += 0xffff;
			x->rx_missed_cntr += 0xffff;
		} else {
			unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
			stats->rx_missed_errors += miss_f;
			x->rx_missed_cntr += miss_f;
		}
	}
	return;
}

static int dwmac100_get_tx_frame_status(void *data,
				      struct stmmac_extra_stats *x,
				      struct dma_desc *p, unsigned long ioaddr)
{
	int ret = 0;
	struct net_device_stats *stats = (struct net_device_stats *)data;

	if (unlikely(p->des01.tx.error_summary)) {
		if (unlikely(p->des01.tx.underflow_error)) {
			x->tx_underflow++;
			stats->tx_fifo_errors++;
		}
		if (unlikely(p->des01.tx.no_carrier)) {
			x->tx_carrier++;
			stats->tx_carrier_errors++;
		}
		if (unlikely(p->des01.tx.loss_carrier)) {
			x->tx_losscarrier++;
			stats->tx_carrier_errors++;
		}
		if (unlikely((p->des01.tx.excessive_deferral) ||
			     (p->des01.tx.excessive_collisions) ||
			     (p->des01.tx.late_collision)))
			stats->collisions += p->des01.tx.collision_count;
		ret = -1;
	}
	if (unlikely(p->des01.tx.heartbeat_fail)) {
		x->tx_heartbeat++;
		stats->tx_heartbeat_errors++;
		ret = -1;
	}
	if (unlikely(p->des01.tx.deferred))
		x->tx_deferred++;

	return ret;
}

static int dwmac100_get_tx_len(struct dma_desc *p)
{
	return p->des01.tx.buffer1_size;
}

/* This function verifies if each incoming frame has some errors
 * and, if required, updates the multicast statistics.
 * In case of success, it returns csum_none becasue the device
 * is not able to compute the csum in HW. */
static int dwmac100_get_rx_frame_status(void *data,
				      struct stmmac_extra_stats *x,
				      struct dma_desc *p)
{
	int ret = csum_none;
	struct net_device_stats *stats = (struct net_device_stats *)data;

	if (unlikely(p->des01.rx.last_descriptor == 0)) {
		pr_warning("dwmac100 Error: Oversized Ethernet "
			   "frame spanned multiple buffers\n");
		stats->rx_length_errors++;
		return discard_frame;
	}

	if (unlikely(p->des01.rx.error_summary)) {
		if (unlikely(p->des01.rx.descriptor_error))
			x->rx_desc++;
		if (unlikely(p->des01.rx.partial_frame_error))
			x->rx_partial++;
		if (unlikely(p->des01.rx.run_frame))
			x->rx_runt++;
		if (unlikely(p->des01.rx.frame_too_long))
			x->rx_toolong++;
		if (unlikely(p->des01.rx.collision)) {
			x->rx_collision++;
			stats->collisions++;
		}
		if (unlikely(p->des01.rx.crc_error)) {
			x->rx_crc++;
			stats->rx_crc_errors++;
		}
		ret = discard_frame;
	}
	if (unlikely(p->des01.rx.dribbling))
		ret = discard_frame;

	if (unlikely(p->des01.rx.length_error)) {
		x->rx_length++;
		ret = discard_frame;
	}
	if (unlikely(p->des01.rx.mii_error)) {
		x->rx_mii++;
		ret = discard_frame;
	}
	if (p->des01.rx.multicast_frame) {
		x->rx_multicast++;
		stats->multicast++;
	}
	return ret;
}

static void dwmac100_irq_status(unsigned long ioaddr)
{
	return;
}

static void dwmac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
			  unsigned int reg_n)
{
	stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}

static void dwmac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
			  unsigned int reg_n)
{
	stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}

static void dwmac100_set_filter(struct net_device *dev)
{
	unsigned long ioaddr = dev->base_addr;
	u32 value = readl(ioaddr + MAC_CONTROL);

	if (dev->flags & IFF_PROMISC) {
		value |= MAC_CONTROL_PR;
		value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
			   MAC_CONTROL_HP);
	} else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
		   || (dev->flags & IFF_ALLMULTI)) {
		value |= MAC_CONTROL_PM;
		value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
		writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
		writel(0xffffffff, ioaddr + MAC_HASH_LOW);
	} else if (netdev_mc_empty(dev)) {	/* no multicast */
		value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
			   MAC_CONTROL_HO | MAC_CONTROL_HP);
	} else {
		u32 mc_filter[2];
		struct dev_mc_list *mclist;

		/* Perfect filter mode for physical address and Hash
		   filter for multicast */
		value |= MAC_CONTROL_HP;
		value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
			   MAC_CONTROL_IF | MAC_CONTROL_HO);

		memset(mc_filter, 0, sizeof(mc_filter));
		netdev_for_each_mc_addr(mclist, dev) {
			/* The upper 6 bits of the calculated CRC are used to
			 * index the contens of the hash table */
			int bit_nr =
			    ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
			/* The most significant bit determines the register to
			 * use (H/L) while the other 5 bits determine the bit
			 * within the register. */
			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
		}
		writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
		writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
	}

	writel(value, ioaddr + MAC_CONTROL);

	DBG(KERN_INFO "%s: CTRL reg: 0x%08x Hash regs: "
	    "HI 0x%08x, LO 0x%08x\n",
	    __func__, readl(ioaddr + MAC_CONTROL),
	    readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
	return;
}

static void dwmac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
			     unsigned int fc, unsigned int pause_time)
{
	unsigned int flow = MAC_FLOW_CTRL_ENABLE;

	if (duplex)
		flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
	writel(flow, ioaddr + MAC_FLOW_CTRL);

	return;
}

/* No PMT module supported for this Ethernet Controller.
 * Tested on ST platforms only.
 */
static void dwmac100_pmt(unsigned long ioaddr, unsigned long mode)
{
	return;
}

static void dwmac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
				int disable_rx_ic)
{
	int i;
	for (i = 0; i < ring_size; i++) {
		p->des01.rx.own = 1;
		p->des01.rx.buffer1_size = BUF_SIZE_2KiB - 1;
		if (i == ring_size - 1)
			p->des01.rx.end_ring = 1;
		if (disable_rx_ic)
			p->des01.rx.disable_ic = 1;
		p++;
	}
	return;
}

static void dwmac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
{
	int i;
	for (i = 0; i < ring_size; i++) {
		p->des01.tx.own = 0;
		if (i == ring_size - 1)
			p->des01.tx.end_ring = 1;
		p++;
	}
	return;
}

static int dwmac100_get_tx_owner(struct dma_desc *p)
{
	return p->des01.tx.own;
}

static int dwmac100_get_rx_owner(struct dma_desc *p)
{
	return p->des01.rx.own;
}

static void dwmac100_set_tx_owner(struct dma_desc *p)
{
	p->des01.tx.own = 1;
}

static void dwmac100_set_rx_owner(struct dma_desc *p)
{
	p->des01.rx.own = 1;
}

static int dwmac100_get_tx_ls(struct dma_desc *p)
{
	return p->des01.tx.last_segment;
}

static void dwmac100_release_tx_desc(struct dma_desc *p)
{
	int ter = p->des01.tx.end_ring;

	/* clean field used within the xmit */
	p->des01.tx.first_segment = 0;
	p->des01.tx.last_segment = 0;
	p->des01.tx.buffer1_size = 0;

	/* clean status reported */
	p->des01.tx.error_summary = 0;
	p->des01.tx.underflow_error = 0;
	p->des01.tx.no_carrier = 0;
	p->des01.tx.loss_carrier = 0;
	p->des01.tx.excessive_deferral = 0;
	p->des01.tx.excessive_collisions = 0;
	p->des01.tx.late_collision = 0;
	p->des01.tx.heartbeat_fail = 0;
	p->des01.tx.deferred = 0;

	/* set termination field */
	p->des01.tx.end_ring = ter;

	return;
}

static void dwmac100_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
				   int csum_flag)
{
	p->des01.tx.first_segment = is_fs;
	p->des01.tx.buffer1_size = len;
}

static void dwmac100_clear_tx_ic(struct dma_desc *p)
{
	p->des01.tx.interrupt = 0;
}

static void dwmac100_close_tx_desc(struct dma_desc *p)
{
	p->des01.tx.last_segment = 1;
	p->des01.tx.interrupt = 1;
}

static int dwmac100_get_rx_frame_len(struct dma_desc *p)
{
	return p->des01.rx.frame_length;
}

struct stmmac_ops dwmac100_ops = {
	.core_init = dwmac100_core_init,
	.dump_regs = dwmac100_dump_mac_regs,
	.host_irq_status = dwmac100_irq_status,
	.set_filter = dwmac100_set_filter,
	.flow_ctrl = dwmac100_flow_ctrl,
	.pmt = dwmac100_pmt,
	.set_umac_addr = dwmac100_set_umac_addr,
	.get_umac_addr = dwmac100_get_umac_addr,
};

struct stmmac_dma_ops dwmac100_dma_ops = {
	.init = dwmac100_dma_init,
	.dump_regs = dwmac100_dump_dma_regs,
	.dma_mode = dwmac100_dma_operation_mode,
	.dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
	.enable_dma_transmission = dwmac_enable_dma_transmission,
	.enable_dma_irq = dwmac_enable_dma_irq,
	.disable_dma_irq = dwmac_disable_dma_irq,
	.start_tx = dwmac_dma_start_tx,
	.stop_tx = dwmac_dma_stop_tx,
	.start_rx = dwmac_dma_start_rx,
	.stop_rx = dwmac_dma_stop_rx,
	.dma_interrupt = dwmac_dma_interrupt,
};

struct stmmac_desc_ops dwmac100_desc_ops = {
	.tx_status = dwmac100_get_tx_frame_status,
	.rx_status = dwmac100_get_rx_frame_status,
	.get_tx_len = dwmac100_get_tx_len,
	.init_rx_desc = dwmac100_init_rx_desc,
	.init_tx_desc = dwmac100_init_tx_desc,
	.get_tx_owner = dwmac100_get_tx_owner,
	.get_rx_owner = dwmac100_get_rx_owner,
	.release_tx_desc = dwmac100_release_tx_desc,
	.prepare_tx_desc = dwmac100_prepare_tx_desc,
	.clear_tx_ic = dwmac100_clear_tx_ic,
	.close_tx_desc = dwmac100_close_tx_desc,
	.get_tx_ls = dwmac100_get_tx_ls,
	.set_tx_owner = dwmac100_set_tx_owner,
	.set_rx_owner = dwmac100_set_rx_owner,
	.get_rx_frame_len = dwmac100_get_rx_frame_len,
};

struct mac_device_info *dwmac100_setup(unsigned long ioaddr)
{
	struct mac_device_info *mac;

	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);

	pr_info("\tDWMAC100\n");

	mac->mac = &dwmac100_ops;
	mac->desc = &dwmac100_desc_ops;
	mac->dma = &dwmac100_dma_ops;

	mac->pmt = PMT_NOT_SUPPORTED;
	mac->link.port = MAC_CONTROL_PS;
	mac->link.duplex = MAC_CONTROL_F;
	mac->link.speed = 0;
	mac->mii.addr = MAC_MII_ADDR;
	mac->mii.data = MAC_MII_DATA;

	return mac;
}
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	This is the driver for the MAC 10/100 on-chip Ethernet controller
	3	currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
	4
	5	DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
	6	this code.
	7
	8	Copyright (C) 2007-2009 STMicroelectronics Ltd
	9
	10	This program is free software; you can redistribute it and/or modify it
	11	under the terms and conditions of the GNU General Public License,
	12	version 2, as published by the Free Software Foundation.
	13
	14	This program is distributed in the hope it will be useful, but WITHOUT
	15	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	more details.
	18
	19	You should have received a copy of the GNU General Public License along with
	20	this program; if not, write to the Free Software Foundation, Inc.,
	21	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	22
	23	The full GNU General Public License is included in this distribution in
	24	the file called "COPYING".
	25
	26	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	27	*******************************************************************************/
	28
47dd7a54 GC	29	#include <linux/crc32.h>
	30	#include <linux/mii.h>
	31	#include <linux/phy.h>
5a0e3ad6	32	#include <linux/slab.h>
47dd7a54 GC	33
47dd7a54 GC	34	#include "common.h"
7e848ae1	35	#include "dwmac100.h"
aec7ff27	36	#include "dwmac_dma.h"
47dd7a54	37
7e848ae1 GC	38	#undef DWMAC100_DEBUG
	39	/#define DWMAC100_DEBUG/
	40	#ifdef DWMAC100_DEBUG
47dd7a54 GC	41	#define DBG(fmt, args...) printk(fmt, ## args)
	42	#else
	43	#define DBG(fmt, args...) do { } while (0)
	44	#endif
	45
7e848ae1	46	static void dwmac100_core_init(unsigned long ioaddr)
47dd7a54 GC	47	{
	48	u32 value = readl(ioaddr + MAC_CONTROL);
	49
	50	writel((value \| MAC_CORE_INIT), ioaddr + MAC_CONTROL);
	51
	52	#ifdef STMMAC_VLAN_TAG_USED
	53	writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
	54	#endif
	55	return;
	56	}
	57
7e848ae1	58	static void dwmac100_dump_mac_regs(unsigned long ioaddr)
47dd7a54 GC	59	{
47dd7a54 GC	60	pr_info("\t----------------------------------------------\n"
7e848ae1 GC	61	"\t DWMAC 100 CSR (base addr = 0x%8x)\n"
	62	"\t----------------------------------------------\n",
	63	(unsigned int)ioaddr);
47dd7a54	64	pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
7e848ae1	65	readl(ioaddr + MAC_CONTROL));
47dd7a54	66	pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
7e848ae1	67	readl(ioaddr + MAC_ADDR_HIGH));
47dd7a54	68	pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
7e848ae1	69	readl(ioaddr + MAC_ADDR_LOW));
47dd7a54	70	pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
7e848ae1	71	MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
47dd7a54	72	pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
7e848ae1	73	MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
47dd7a54 GC	74	pr_info("\tflow control (offset 0x%x): 0x%08x\n",
	75	MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
	76	pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
7e848ae1	77	readl(ioaddr + MAC_VLAN1));
47dd7a54	78	pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
7e848ae1	79	readl(ioaddr + MAC_VLAN2));
47dd7a54 GC	80	pr_info("\n\tMAC management counter registers\n");
47dd7a54 GC	81	pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
7e848ae1	82	MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
47dd7a54	83	pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
7e848ae1	84	MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
47dd7a54	85	pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
7e848ae1	86	MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
47dd7a54	87	pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
7e848ae1	88	MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
47dd7a54	89	pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
7e848ae1	90	MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
47dd7a54 GC	91	return;
	92	}
	93
7e848ae1	94	static int dwmac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
47dd7a54 GC	95	u32 dma_rx)
	96	{
	97	u32 value = readl(ioaddr + DMA_BUS_MODE);
	98	/* DMA SW reset */
	99	value \|= DMA_BUS_MODE_SFT_RESET;
	100	writel(value, ioaddr + DMA_BUS_MODE);
	101	do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
	102
	103	/* Enable Application Access by writing to DMA CSR0 */
	104	writel(DMA_BUS_MODE_DEFAULT \| (pbl << DMA_BUS_MODE_PBL_SHIFT),
	105	ioaddr + DMA_BUS_MODE);
	106
	107	/* Mask interrupts by writing to CSR7 */
	108	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
	109
	110	/* The base address of the RX/TX descriptor lists must be written into
	111	* DMA CSR3 and CSR4, respectively. */
	112	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
	113	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
	114
	115	return 0;
	116	}
	117
	118	/* Store and Forward capability is not used at all..
	119	* The transmit threshold can be programmed by
	120	* setting the TTC bits in the DMA control register.*/
7e848ae1	121	static void dwmac100_dma_operation_mode(unsigned long ioaddr, int txmode,
47dd7a54 GC	122	int rxmode)
	123	{
	124	u32 csr6 = readl(ioaddr + DMA_CONTROL);
	125
	126	if (txmode <= 32)
	127	csr6 \|= DMA_CONTROL_TTC_32;
	128	else if (txmode <= 64)
	129	csr6 \|= DMA_CONTROL_TTC_64;
	130	else
	131	csr6 \|= DMA_CONTROL_TTC_128;
	132
	133	writel(csr6, ioaddr + DMA_CONTROL);
	134
	135	return;
	136	}
	137
7e848ae1	138	static void dwmac100_dump_dma_regs(unsigned long ioaddr)
47dd7a54 GC	139	{
	140	int i;
	141
7e848ae1	142	DBG(KERN_DEBUG "DWMAC 100 DMA CSR \n");
47dd7a54 GC	143	for (i = 0; i < 9; i++)
	144	pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
	145	(DMA_BUS_MODE + i * 4),
	146	readl(ioaddr + DMA_BUS_MODE + i * 4));
	147	DBG(KERN_DEBUG "\t CSR20 (offset 0x%x): 0x%08x\n",
	148	DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
	149	DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n",
	150	DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
	151	return;
	152	}
	153
	154	/* DMA controller has two counters to track the number of
7e848ae1 GC	155	* the receive missed frames. */
	156	static void dwmac100_dma_diagnostic_fr(void *data,
	157	struct stmmac_extra_stats *x,
47dd7a54 GC	158	unsigned long ioaddr)
	159	{
	160	struct net_device_stats stats = (struct net_device_stats )data;
	161	u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
	162
	163	if (unlikely(csr8)) {
	164	if (csr8 & DMA_MISSED_FRAME_OVE) {
	165	stats->rx_over_errors += 0x800;
	166	x->rx_overflow_cntr += 0x800;
	167	} else {
	168	unsigned int ove_cntr;
	169	ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
	170	stats->rx_over_errors += ove_cntr;
	171	x->rx_overflow_cntr += ove_cntr;
	172	}
	173
	174	if (csr8 & DMA_MISSED_FRAME_OVE_M) {
	175	stats->rx_missed_errors += 0xffff;
	176	x->rx_missed_cntr += 0xffff;
	177	} else {
	178	unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
	179	stats->rx_missed_errors += miss_f;
	180	x->rx_missed_cntr += miss_f;
	181	}
	182	}
	183	return;
	184	}
	185
7e848ae1 GC	186	static int dwmac100_get_tx_frame_status(void *data,
7e848ae1 GC	187	struct stmmac_extra_stats *x,
47dd7a54 GC	188	struct dma_desc *p, unsigned long ioaddr)
	189	{
	190	int ret = 0;
	191	struct net_device_stats stats = (struct net_device_stats )data;
	192
	193	if (unlikely(p->des01.tx.error_summary)) {
	194	if (unlikely(p->des01.tx.underflow_error)) {
	195	x->tx_underflow++;
	196	stats->tx_fifo_errors++;
	197	}
	198	if (unlikely(p->des01.tx.no_carrier)) {
	199	x->tx_carrier++;
	200	stats->tx_carrier_errors++;
	201	}
	202	if (unlikely(p->des01.tx.loss_carrier)) {
	203	x->tx_losscarrier++;
	204	stats->tx_carrier_errors++;
	205	}
	206	if (unlikely((p->des01.tx.excessive_deferral) \|\|
	207	(p->des01.tx.excessive_collisions) \|\|
	208	(p->des01.tx.late_collision)))
	209	stats->collisions += p->des01.tx.collision_count;
	210	ret = -1;
	211	}
	212	if (unlikely(p->des01.tx.heartbeat_fail)) {
	213	x->tx_heartbeat++;
	214	stats->tx_heartbeat_errors++;
	215	ret = -1;
	216	}
	217	if (unlikely(p->des01.tx.deferred))
	218	x->tx_deferred++;
	219
	220	return ret;
	221	}
	222
7e848ae1	223	static int dwmac100_get_tx_len(struct dma_desc *p)
47dd7a54 GC	224	{
	225	return p->des01.tx.buffer1_size;
	226	}
	227
	228	/* This function verifies if each incoming frame has some errors
	229	* and, if required, updates the multicast statistics.
	230	* In case of success, it returns csum_none becasue the device
	231	* is not able to compute the csum in HW. */
7e848ae1 GC	232	static int dwmac100_get_rx_frame_status(void *data,
7e848ae1 GC	233	struct stmmac_extra_stats *x,
47dd7a54 GC	234	struct dma_desc *p)
	235	{
	236	int ret = csum_none;
	237	struct net_device_stats stats = (struct net_device_stats )data;
	238
	239	if (unlikely(p->des01.rx.last_descriptor == 0)) {
7e848ae1	240	pr_warning("dwmac100 Error: Oversized Ethernet "
47dd7a54 GC	241	"frame spanned multiple buffers\n");
	242	stats->rx_length_errors++;
	243	return discard_frame;
	244	}
	245
	246	if (unlikely(p->des01.rx.error_summary)) {
	247	if (unlikely(p->des01.rx.descriptor_error))
	248	x->rx_desc++;
	249	if (unlikely(p->des01.rx.partial_frame_error))
	250	x->rx_partial++;
	251	if (unlikely(p->des01.rx.run_frame))
	252	x->rx_runt++;
	253	if (unlikely(p->des01.rx.frame_too_long))
	254	x->rx_toolong++;
	255	if (unlikely(p->des01.rx.collision)) {
	256	x->rx_collision++;
	257	stats->collisions++;
	258	}
	259	if (unlikely(p->des01.rx.crc_error)) {
	260	x->rx_crc++;
	261	stats->rx_crc_errors++;
	262	}
	263	ret = discard_frame;
	264	}
	265	if (unlikely(p->des01.rx.dribbling))
	266	ret = discard_frame;
	267
	268	if (unlikely(p->des01.rx.length_error)) {
1b924032	269	x->rx_length++;
47dd7a54 GC	270	ret = discard_frame;
	271	}
	272	if (unlikely(p->des01.rx.mii_error)) {
	273	x->rx_mii++;
	274	ret = discard_frame;
	275	}
	276	if (p->des01.rx.multicast_frame) {
	277	x->rx_multicast++;
	278	stats->multicast++;
	279	}
	280	return ret;
	281	}
	282
7e848ae1	283	static void dwmac100_irq_status(unsigned long ioaddr)
47dd7a54 GC	284	{
	285	return;
	286	}
	287
7e848ae1	288	static void dwmac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
47dd7a54 GC	289	unsigned int reg_n)
	290	{
	291	stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
	292	}
	293
7e848ae1	294	static void dwmac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
47dd7a54 GC	295	unsigned int reg_n)
	296	{
	297	stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
	298	}
	299
7e848ae1	300	static void dwmac100_set_filter(struct net_device *dev)
47dd7a54 GC	301	{
	302	unsigned long ioaddr = dev->base_addr;
	303	u32 value = readl(ioaddr + MAC_CONTROL);
	304
	305	if (dev->flags & IFF_PROMISC) {
	306	value \|= MAC_CONTROL_PR;
	307	value &= ~(MAC_CONTROL_PM \| MAC_CONTROL_IF \| MAC_CONTROL_HO \|
	308	MAC_CONTROL_HP);
4cd24eaf	309	} else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
47dd7a54 GC	310	\|\| (dev->flags & IFF_ALLMULTI)) {
	311	value \|= MAC_CONTROL_PM;
	312	value &= ~(MAC_CONTROL_PR \| MAC_CONTROL_IF \| MAC_CONTROL_HO);
	313	writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
	314	writel(0xffffffff, ioaddr + MAC_HASH_LOW);
4cd24eaf	315	} else if (netdev_mc_empty(dev)) { /* no multicast */
47dd7a54 GC	316	value &= ~(MAC_CONTROL_PM \| MAC_CONTROL_PR \| MAC_CONTROL_IF \|
	317	MAC_CONTROL_HO \| MAC_CONTROL_HP);
	318	} else {
47dd7a54 GC	319	u32 mc_filter[2];
	320	struct dev_mc_list *mclist;
	321
	322	/* Perfect filter mode for physical address and Hash
	323	filter for multicast */
	324	value \|= MAC_CONTROL_HP;
7e848ae1 GC	325	value &= ~(MAC_CONTROL_PM \| MAC_CONTROL_PR \|
7e848ae1 GC	326	MAC_CONTROL_IF \| MAC_CONTROL_HO);
47dd7a54 GC	327
47dd7a54 GC	328	memset(mc_filter, 0, sizeof(mc_filter));
5508590c	329	netdev_for_each_mc_addr(mclist, dev) {
47dd7a54 GC	330	/* The upper 6 bits of the calculated CRC are used to
	331	* index the contens of the hash table */
	332	int bit_nr =
	333	ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
	334	/* The most significant bit determines the register to
	335	* use (H/L) while the other 5 bits determine the bit
	336	* within the register. */
	337	mc_filter[bit_nr >> 5] \|= 1 << (bit_nr & 31);
	338	}
	339	writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
	340	writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
	341	}
	342
	343	writel(value, ioaddr + MAC_CONTROL);
	344
	345	DBG(KERN_INFO "%s: CTRL reg: 0x%08x Hash regs: "
	346	"HI 0x%08x, LO 0x%08x\n",
	347	__func__, readl(ioaddr + MAC_CONTROL),
	348	readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
	349	return;
	350	}
	351
7e848ae1	352	static void dwmac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
47dd7a54 GC	353	unsigned int fc, unsigned int pause_time)
	354	{
	355	unsigned int flow = MAC_FLOW_CTRL_ENABLE;
	356
	357	if (duplex)
	358	flow \|= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
	359	writel(flow, ioaddr + MAC_FLOW_CTRL);
	360
	361	return;
	362	}
	363
7e848ae1 GC	364	/* No PMT module supported for this Ethernet Controller.
	365	* Tested on ST platforms only.
	366	*/
	367	static void dwmac100_pmt(unsigned long ioaddr, unsigned long mode)
47dd7a54 GC	368	{
	369	return;
	370	}
	371
7e848ae1	372	static void dwmac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
47dd7a54 GC	373	int disable_rx_ic)
	374	{
	375	int i;
	376	for (i = 0; i < ring_size; i++) {
	377	p->des01.rx.own = 1;
	378	p->des01.rx.buffer1_size = BUF_SIZE_2KiB - 1;
	379	if (i == ring_size - 1)
	380	p->des01.rx.end_ring = 1;
	381	if (disable_rx_ic)
	382	p->des01.rx.disable_ic = 1;
	383	p++;
	384	}
	385	return;
	386	}
	387
7e848ae1	388	static void dwmac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
47dd7a54 GC	389	{
	390	int i;
	391	for (i = 0; i < ring_size; i++) {
	392	p->des01.tx.own = 0;
	393	if (i == ring_size - 1)
	394	p->des01.tx.end_ring = 1;
	395	p++;
	396	}
	397	return;
	398	}
	399
7e848ae1	400	static int dwmac100_get_tx_owner(struct dma_desc *p)
47dd7a54 GC	401	{
	402	return p->des01.tx.own;
	403	}
	404
7e848ae1	405	static int dwmac100_get_rx_owner(struct dma_desc *p)
47dd7a54 GC	406	{
	407	return p->des01.rx.own;
	408	}
	409
7e848ae1	410	static void dwmac100_set_tx_owner(struct dma_desc *p)
47dd7a54 GC	411	{
	412	p->des01.tx.own = 1;
	413	}
	414
7e848ae1	415	static void dwmac100_set_rx_owner(struct dma_desc *p)
47dd7a54 GC	416	{
	417	p->des01.rx.own = 1;
	418	}
	419
7e848ae1	420	static int dwmac100_get_tx_ls(struct dma_desc *p)
47dd7a54 GC	421	{
	422	return p->des01.tx.last_segment;
	423	}
	424
7e848ae1	425	static void dwmac100_release_tx_desc(struct dma_desc *p)
47dd7a54 GC	426	{
	427	int ter = p->des01.tx.end_ring;
	428
	429	/* clean field used within the xmit */
	430	p->des01.tx.first_segment = 0;
	431	p->des01.tx.last_segment = 0;
	432	p->des01.tx.buffer1_size = 0;
	433
	434	/* clean status reported */
	435	p->des01.tx.error_summary = 0;
	436	p->des01.tx.underflow_error = 0;
	437	p->des01.tx.no_carrier = 0;
	438	p->des01.tx.loss_carrier = 0;
	439	p->des01.tx.excessive_deferral = 0;
	440	p->des01.tx.excessive_collisions = 0;
	441	p->des01.tx.late_collision = 0;
	442	p->des01.tx.heartbeat_fail = 0;
	443	p->des01.tx.deferred = 0;
	444
	445	/* set termination field */
	446	p->des01.tx.end_ring = ter;
	447
	448	return;
	449	}
	450
7e848ae1	451	static void dwmac100_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
47dd7a54 GC	452	int csum_flag)
	453	{
	454	p->des01.tx.first_segment = is_fs;
	455	p->des01.tx.buffer1_size = len;
	456	}
	457
7e848ae1	458	static void dwmac100_clear_tx_ic(struct dma_desc *p)
47dd7a54 GC	459	{
	460	p->des01.tx.interrupt = 0;
	461	}
	462
7e848ae1	463	static void dwmac100_close_tx_desc(struct dma_desc *p)
47dd7a54 GC	464	{
	465	p->des01.tx.last_segment = 1;
	466	p->des01.tx.interrupt = 1;
	467	}
	468
7e848ae1	469	static int dwmac100_get_rx_frame_len(struct dma_desc *p)
47dd7a54 GC	470	{
	471	return p->des01.rx.frame_length;
	472	}
	473
7e848ae1 GC	474	struct stmmac_ops dwmac100_ops = {
	475	.core_init = dwmac100_core_init,
	476	.dump_regs = dwmac100_dump_mac_regs,
	477	.host_irq_status = dwmac100_irq_status,
	478	.set_filter = dwmac100_set_filter,
	479	.flow_ctrl = dwmac100_flow_ctrl,
	480	.pmt = dwmac100_pmt,
	481	.set_umac_addr = dwmac100_set_umac_addr,
	482	.get_umac_addr = dwmac100_get_umac_addr,
db98a0b0 GC	483	};
db98a0b0 GC	484
7e848ae1 GC	485	struct stmmac_dma_ops dwmac100_dma_ops = {
	486	.init = dwmac100_dma_init,
	487	.dump_regs = dwmac100_dump_dma_regs,
	488	.dma_mode = dwmac100_dma_operation_mode,
	489	.dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
aec7ff27 GC	490	.enable_dma_transmission = dwmac_enable_dma_transmission,
	491	.enable_dma_irq = dwmac_enable_dma_irq,
	492	.disable_dma_irq = dwmac_disable_dma_irq,
	493	.start_tx = dwmac_dma_start_tx,
	494	.stop_tx = dwmac_dma_stop_tx,
	495	.start_rx = dwmac_dma_start_rx,
	496	.stop_rx = dwmac_dma_stop_rx,
	497	.dma_interrupt = dwmac_dma_interrupt,
db98a0b0 GC	498	};
db98a0b0 GC	499
7e848ae1 GC	500	struct stmmac_desc_ops dwmac100_desc_ops = {
	501	.tx_status = dwmac100_get_tx_frame_status,
	502	.rx_status = dwmac100_get_rx_frame_status,
	503	.get_tx_len = dwmac100_get_tx_len,
	504	.init_rx_desc = dwmac100_init_rx_desc,
	505	.init_tx_desc = dwmac100_init_tx_desc,
	506	.get_tx_owner = dwmac100_get_tx_owner,
	507	.get_rx_owner = dwmac100_get_rx_owner,
	508	.release_tx_desc = dwmac100_release_tx_desc,
	509	.prepare_tx_desc = dwmac100_prepare_tx_desc,
	510	.clear_tx_ic = dwmac100_clear_tx_ic,
	511	.close_tx_desc = dwmac100_close_tx_desc,
	512	.get_tx_ls = dwmac100_get_tx_ls,
	513	.set_tx_owner = dwmac100_set_tx_owner,
	514	.set_rx_owner = dwmac100_set_rx_owner,
	515	.get_rx_frame_len = dwmac100_get_rx_frame_len,
47dd7a54 GC	516	};
47dd7a54 GC	517
7e848ae1	518	struct mac_device_info *dwmac100_setup(unsigned long ioaddr)
47dd7a54 GC	519	{
	520	struct mac_device_info *mac;
	521
	522	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
	523
7e848ae1	524	pr_info("\tDWMAC100\n");
47dd7a54	525
7e848ae1 GC	526	mac->mac = &dwmac100_ops;
	527	mac->desc = &dwmac100_desc_ops;
	528	mac->dma = &dwmac100_dma_ops;
db98a0b0 GC	529
	530	mac->pmt = PMT_NOT_SUPPORTED;
	531	mac->link.port = MAC_CONTROL_PS;
	532	mac->link.duplex = MAC_CONTROL_F;
	533	mac->link.speed = 0;
	534	mac->mii.addr = MAC_MII_ADDR;
	535	mac->mii.data = MAC_MII_DATA;
47dd7a54 GC	536
	537	return mac;
	538	}