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1 | /******************************************************************************* |
2 | STMMAC Ethernet Driver -- MDIO bus implementation | |
3 | Provides Bus interface for MII registers | |
4 | ||
5 | Copyright (C) 2007-2009 STMicroelectronics Ltd | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Carl Shaw <carl.shaw@st.com> | |
24 | Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
25 | *******************************************************************************/ | |
26 | ||
27 | #include <linux/netdevice.h> | |
28 | #include <linux/mii.h> | |
29 | #include <linux/phy.h> | |
30 | ||
31 | #include "stmmac.h" | |
32 | ||
33 | #define MII_BUSY 0x00000001 | |
34 | #define MII_WRITE 0x00000002 | |
35 | ||
36 | /** | |
37 | * stmmac_mdio_read | |
38 | * @bus: points to the mii_bus structure | |
39 | * @phyaddr: MII addr reg bits 15-11 | |
40 | * @phyreg: MII addr reg bits 10-6 | |
41 | * Description: it reads data from the MII register from within the phy device. | |
42 | * For the 7111 GMAC, we must set the bit 0 in the MII address register while | |
43 | * accessing the PHY registers. | |
44 | * Fortunately, it seems this has no drawback for the 7109 MAC. | |
45 | */ | |
46 | static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) | |
47 | { | |
48 | struct net_device *ndev = bus->priv; | |
49 | struct stmmac_priv *priv = netdev_priv(ndev); | |
50 | unsigned long ioaddr = ndev->base_addr; | |
51 | unsigned int mii_address = priv->mac_type->hw.mii.addr; | |
52 | unsigned int mii_data = priv->mac_type->hw.mii.data; | |
53 | ||
54 | int data; | |
55 | u16 regValue = (((phyaddr << 11) & (0x0000F800)) | | |
56 | ((phyreg << 6) & (0x000007C0))); | |
57 | regValue |= MII_BUSY; /* in case of GMAC */ | |
58 | ||
59 | do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); | |
60 | writel(regValue, ioaddr + mii_address); | |
61 | do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); | |
62 | ||
63 | /* Read the data from the MII data register */ | |
64 | data = (int)readl(ioaddr + mii_data); | |
65 | ||
66 | return data; | |
67 | } | |
68 | ||
69 | /** | |
70 | * stmmac_mdio_write | |
71 | * @bus: points to the mii_bus structure | |
72 | * @phyaddr: MII addr reg bits 15-11 | |
73 | * @phyreg: MII addr reg bits 10-6 | |
74 | * @phydata: phy data | |
75 | * Description: it writes the data into the MII register from within the device. | |
76 | */ | |
77 | static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, | |
78 | u16 phydata) | |
79 | { | |
80 | struct net_device *ndev = bus->priv; | |
81 | struct stmmac_priv *priv = netdev_priv(ndev); | |
82 | unsigned long ioaddr = ndev->base_addr; | |
83 | unsigned int mii_address = priv->mac_type->hw.mii.addr; | |
84 | unsigned int mii_data = priv->mac_type->hw.mii.data; | |
85 | ||
86 | u16 value = | |
87 | (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) | |
88 | | MII_WRITE; | |
89 | ||
90 | value |= MII_BUSY; | |
91 | ||
92 | /* Wait until any existing MII operation is complete */ | |
93 | do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); | |
94 | ||
95 | /* Set the MII address register to write */ | |
96 | writel(phydata, ioaddr + mii_data); | |
97 | writel(value, ioaddr + mii_address); | |
98 | ||
99 | /* Wait until any existing MII operation is complete */ | |
100 | do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
105 | /** | |
106 | * stmmac_mdio_reset | |
107 | * @bus: points to the mii_bus structure | |
108 | * Description: reset the MII bus | |
109 | */ | |
110 | static int stmmac_mdio_reset(struct mii_bus *bus) | |
111 | { | |
112 | struct net_device *ndev = bus->priv; | |
113 | struct stmmac_priv *priv = netdev_priv(ndev); | |
114 | unsigned long ioaddr = ndev->base_addr; | |
115 | unsigned int mii_address = priv->mac_type->hw.mii.addr; | |
116 | ||
117 | if (priv->phy_reset) { | |
118 | pr_debug("stmmac_mdio_reset: calling phy_reset\n"); | |
119 | priv->phy_reset(priv->bsp_priv); | |
120 | } | |
121 | ||
122 | /* This is a workaround for problems with the STE101P PHY. | |
123 | * It doesn't complete its reset until at least one clock cycle | |
124 | * on MDC, so perform a dummy mdio read. | |
125 | */ | |
126 | writel(0, ioaddr + mii_address); | |
127 | ||
128 | return 0; | |
129 | } | |
130 | ||
131 | /** | |
132 | * stmmac_mdio_register | |
133 | * @ndev: net device structure | |
134 | * Description: it registers the MII bus | |
135 | */ | |
136 | int stmmac_mdio_register(struct net_device *ndev) | |
137 | { | |
138 | int err = 0; | |
139 | struct mii_bus *new_bus; | |
140 | int *irqlist; | |
141 | struct stmmac_priv *priv = netdev_priv(ndev); | |
142 | int addr, found; | |
143 | ||
144 | new_bus = mdiobus_alloc(); | |
145 | if (new_bus == NULL) | |
146 | return -ENOMEM; | |
147 | ||
148 | irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
149 | if (irqlist == NULL) { | |
150 | err = -ENOMEM; | |
151 | goto irqlist_alloc_fail; | |
152 | } | |
153 | ||
154 | /* Assign IRQ to phy at address phy_addr */ | |
155 | if (priv->phy_addr != -1) | |
156 | irqlist[priv->phy_addr] = priv->phy_irq; | |
157 | ||
158 | new_bus->name = "STMMAC MII Bus"; | |
159 | new_bus->read = &stmmac_mdio_read; | |
160 | new_bus->write = &stmmac_mdio_write; | |
161 | new_bus->reset = &stmmac_mdio_reset; | |
162 | snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->bus_id); | |
163 | new_bus->priv = ndev; | |
164 | new_bus->irq = irqlist; | |
165 | new_bus->phy_mask = priv->phy_mask; | |
166 | new_bus->parent = priv->device; | |
167 | err = mdiobus_register(new_bus); | |
168 | if (err != 0) { | |
169 | pr_err("%s: Cannot register as MDIO bus\n", new_bus->name); | |
170 | goto bus_register_fail; | |
171 | } | |
172 | ||
173 | priv->mii = new_bus; | |
174 | ||
175 | found = 0; | |
176 | for (addr = 0; addr < 32; addr++) { | |
177 | struct phy_device *phydev = new_bus->phy_map[addr]; | |
178 | if (phydev) { | |
179 | if (priv->phy_addr == -1) { | |
180 | priv->phy_addr = addr; | |
181 | phydev->irq = priv->phy_irq; | |
182 | irqlist[addr] = priv->phy_irq; | |
183 | } | |
184 | pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n", | |
185 | ndev->name, phydev->phy_id, addr, | |
186 | phydev->irq, dev_name(&phydev->dev), | |
187 | (addr == priv->phy_addr) ? " active" : ""); | |
188 | found = 1; | |
189 | } | |
190 | } | |
191 | ||
192 | if (!found) | |
193 | pr_warning("%s: No PHY found\n", ndev->name); | |
194 | ||
195 | return 0; | |
196 | bus_register_fail: | |
197 | kfree(irqlist); | |
198 | irqlist_alloc_fail: | |
199 | kfree(new_bus); | |
200 | return err; | |
201 | } | |
202 | ||
203 | /** | |
204 | * stmmac_mdio_unregister | |
205 | * @ndev: net device structure | |
206 | * Description: it unregisters the MII bus | |
207 | */ | |
208 | int stmmac_mdio_unregister(struct net_device *ndev) | |
209 | { | |
210 | struct stmmac_priv *priv = netdev_priv(ndev); | |
211 | ||
212 | mdiobus_unregister(priv->mii); | |
213 | priv->mii->priv = NULL; | |
214 | kfree(priv->mii); | |
215 | ||
216 | return 0; | |
217 | } |