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47dd7a54 GC |
1 | /******************************************************************************* |
2 | STMMAC Ethernet Driver -- MDIO bus implementation | |
3 | Provides Bus interface for MII registers | |
4 | ||
5 | Copyright (C) 2007-2009 STMicroelectronics Ltd | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Carl Shaw <carl.shaw@st.com> | |
24 | Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
25 | *******************************************************************************/ | |
26 | ||
47dd7a54 GC |
27 | #include <linux/mii.h> |
28 | #include <linux/phy.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
b7f080cf | 30 | #include <asm/io.h> |
47dd7a54 GC |
31 | |
32 | #include "stmmac.h" | |
33 | ||
34 | #define MII_BUSY 0x00000001 | |
35 | #define MII_WRITE 0x00000002 | |
36 | ||
37 | /** | |
38 | * stmmac_mdio_read | |
39 | * @bus: points to the mii_bus structure | |
40 | * @phyaddr: MII addr reg bits 15-11 | |
41 | * @phyreg: MII addr reg bits 10-6 | |
42 | * Description: it reads data from the MII register from within the phy device. | |
43 | * For the 7111 GMAC, we must set the bit 0 in the MII address register while | |
44 | * accessing the PHY registers. | |
45 | * Fortunately, it seems this has no drawback for the 7109 MAC. | |
46 | */ | |
47 | static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) | |
48 | { | |
49 | struct net_device *ndev = bus->priv; | |
50 | struct stmmac_priv *priv = netdev_priv(ndev); | |
db98a0b0 GC |
51 | unsigned int mii_address = priv->hw->mii.addr; |
52 | unsigned int mii_data = priv->hw->mii.data; | |
47dd7a54 GC |
53 | |
54 | int data; | |
55 | u16 regValue = (((phyaddr << 11) & (0x0000F800)) | | |
56 | ((phyreg << 6) & (0x000007C0))); | |
9dfeb4d9 | 57 | regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); |
47dd7a54 | 58 | |
ad01b7d4 GC |
59 | do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); |
60 | writel(regValue, priv->ioaddr + mii_address); | |
61 | do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); | |
47dd7a54 GC |
62 | |
63 | /* Read the data from the MII data register */ | |
ad01b7d4 | 64 | data = (int)readl(priv->ioaddr + mii_data); |
47dd7a54 GC |
65 | |
66 | return data; | |
67 | } | |
68 | ||
69 | /** | |
70 | * stmmac_mdio_write | |
71 | * @bus: points to the mii_bus structure | |
72 | * @phyaddr: MII addr reg bits 15-11 | |
73 | * @phyreg: MII addr reg bits 10-6 | |
74 | * @phydata: phy data | |
75 | * Description: it writes the data into the MII register from within the device. | |
76 | */ | |
77 | static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, | |
78 | u16 phydata) | |
79 | { | |
80 | struct net_device *ndev = bus->priv; | |
81 | struct stmmac_priv *priv = netdev_priv(ndev); | |
db98a0b0 GC |
82 | unsigned int mii_address = priv->hw->mii.addr; |
83 | unsigned int mii_data = priv->hw->mii.data; | |
47dd7a54 GC |
84 | |
85 | u16 value = | |
86 | (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) | |
87 | | MII_WRITE; | |
88 | ||
9dfeb4d9 | 89 | value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); |
dfb8fb96 | 90 | |
47dd7a54 GC |
91 | |
92 | /* Wait until any existing MII operation is complete */ | |
ad01b7d4 | 93 | do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); |
47dd7a54 GC |
94 | |
95 | /* Set the MII address register to write */ | |
ad01b7d4 GC |
96 | writel(phydata, priv->ioaddr + mii_data); |
97 | writel(value, priv->ioaddr + mii_address); | |
47dd7a54 GC |
98 | |
99 | /* Wait until any existing MII operation is complete */ | |
ad01b7d4 | 100 | do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); |
47dd7a54 GC |
101 | |
102 | return 0; | |
103 | } | |
104 | ||
105 | /** | |
106 | * stmmac_mdio_reset | |
107 | * @bus: points to the mii_bus structure | |
108 | * Description: reset the MII bus | |
109 | */ | |
110 | static int stmmac_mdio_reset(struct mii_bus *bus) | |
111 | { | |
112 | struct net_device *ndev = bus->priv; | |
113 | struct stmmac_priv *priv = netdev_priv(ndev); | |
db98a0b0 | 114 | unsigned int mii_address = priv->hw->mii.addr; |
47dd7a54 GC |
115 | |
116 | if (priv->phy_reset) { | |
117 | pr_debug("stmmac_mdio_reset: calling phy_reset\n"); | |
9dfeb4d9 | 118 | priv->phy_reset(priv->plat->bsp_priv); |
47dd7a54 GC |
119 | } |
120 | ||
121 | /* This is a workaround for problems with the STE101P PHY. | |
122 | * It doesn't complete its reset until at least one clock cycle | |
123 | * on MDC, so perform a dummy mdio read. | |
124 | */ | |
ad01b7d4 | 125 | writel(0, priv->ioaddr + mii_address); |
47dd7a54 GC |
126 | |
127 | return 0; | |
128 | } | |
129 | ||
130 | /** | |
131 | * stmmac_mdio_register | |
132 | * @ndev: net device structure | |
133 | * Description: it registers the MII bus | |
134 | */ | |
135 | int stmmac_mdio_register(struct net_device *ndev) | |
136 | { | |
137 | int err = 0; | |
138 | struct mii_bus *new_bus; | |
139 | int *irqlist; | |
140 | struct stmmac_priv *priv = netdev_priv(ndev); | |
141 | int addr, found; | |
142 | ||
143 | new_bus = mdiobus_alloc(); | |
144 | if (new_bus == NULL) | |
145 | return -ENOMEM; | |
146 | ||
147 | irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
148 | if (irqlist == NULL) { | |
149 | err = -ENOMEM; | |
150 | goto irqlist_alloc_fail; | |
151 | } | |
152 | ||
153 | /* Assign IRQ to phy at address phy_addr */ | |
154 | if (priv->phy_addr != -1) | |
155 | irqlist[priv->phy_addr] = priv->phy_irq; | |
156 | ||
157 | new_bus->name = "STMMAC MII Bus"; | |
158 | new_bus->read = &stmmac_mdio_read; | |
159 | new_bus->write = &stmmac_mdio_write; | |
160 | new_bus->reset = &stmmac_mdio_reset; | |
9dfeb4d9 | 161 | snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id); |
47dd7a54 GC |
162 | new_bus->priv = ndev; |
163 | new_bus->irq = irqlist; | |
164 | new_bus->phy_mask = priv->phy_mask; | |
165 | new_bus->parent = priv->device; | |
166 | err = mdiobus_register(new_bus); | |
167 | if (err != 0) { | |
168 | pr_err("%s: Cannot register as MDIO bus\n", new_bus->name); | |
169 | goto bus_register_fail; | |
170 | } | |
171 | ||
172 | priv->mii = new_bus; | |
173 | ||
174 | found = 0; | |
175 | for (addr = 0; addr < 32; addr++) { | |
176 | struct phy_device *phydev = new_bus->phy_map[addr]; | |
177 | if (phydev) { | |
178 | if (priv->phy_addr == -1) { | |
179 | priv->phy_addr = addr; | |
180 | phydev->irq = priv->phy_irq; | |
181 | irqlist[addr] = priv->phy_irq; | |
182 | } | |
183 | pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n", | |
184 | ndev->name, phydev->phy_id, addr, | |
185 | phydev->irq, dev_name(&phydev->dev), | |
186 | (addr == priv->phy_addr) ? " active" : ""); | |
187 | found = 1; | |
188 | } | |
189 | } | |
190 | ||
191 | if (!found) | |
192 | pr_warning("%s: No PHY found\n", ndev->name); | |
193 | ||
194 | return 0; | |
195 | bus_register_fail: | |
196 | kfree(irqlist); | |
197 | irqlist_alloc_fail: | |
198 | kfree(new_bus); | |
199 | return err; | |
200 | } | |
201 | ||
202 | /** | |
203 | * stmmac_mdio_unregister | |
204 | * @ndev: net device structure | |
205 | * Description: it unregisters the MII bus | |
206 | */ | |
207 | int stmmac_mdio_unregister(struct net_device *ndev) | |
208 | { | |
209 | struct stmmac_priv *priv = netdev_priv(ndev); | |
210 | ||
211 | mdiobus_unregister(priv->mii); | |
212 | priv->mii->priv = NULL; | |
213 | kfree(priv->mii); | |
214 | ||
215 | return 0; | |
216 | } |