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1da177e4 LT |
1 | /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $ |
2 | * sungem.c: Sun GEM ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com) | |
6aa20a22 | 5 | * |
1da177e4 LT |
6 | * Support for Apple GMAC and assorted PHYs, WOL, Power Management |
7 | * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org) | |
8 | * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp. | |
9 | * | |
10 | * NAPI and NETPOLL support | |
11 | * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com) | |
6aa20a22 JG |
12 | * |
13 | * TODO: | |
1da177e4 LT |
14 | * - Now that the driver was significantly simplified, I need to rework |
15 | * the locking. I'm sure we don't need _2_ spinlocks, and we probably | |
16 | * can avoid taking most of them for so long period of time (and schedule | |
17 | * instead). The main issues at this point are caused by the netdev layer | |
18 | * though: | |
6aa20a22 | 19 | * |
1da177e4 LT |
20 | * gem_change_mtu() and gem_set_multicast() are called with a read_lock() |
21 | * help by net/core/dev.c, thus they can't schedule. That means they can't | |
bea3348e | 22 | * call napi_disable() neither, thus force gem_poll() to keep a spinlock |
1da177e4 LT |
23 | * where it could have been dropped. change_mtu especially would love also to |
24 | * be able to msleep instead of horrid locked delays when resetting the HW, | |
25 | * but that read_lock() makes it impossible, unless I defer it's action to | |
26 | * the reset task, which means it'll be asynchronous (won't take effect until | |
27 | * the system schedules a bit). | |
28 | * | |
29 | * Also, it would probably be possible to also remove most of the long-life | |
30 | * locking in open/resume code path (gem_reinit_chip) by beeing more careful | |
31 | * about when we can start taking interrupts or get xmit() called... | |
32 | */ | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/types.h> | |
37 | #include <linux/fcntl.h> | |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/in.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/string.h> | |
43 | #include <linux/delay.h> | |
44 | #include <linux/init.h> | |
45 | #include <linux/errno.h> | |
46 | #include <linux/pci.h> | |
1e7f0bd8 | 47 | #include <linux/dma-mapping.h> |
1da177e4 LT |
48 | #include <linux/netdevice.h> |
49 | #include <linux/etherdevice.h> | |
50 | #include <linux/skbuff.h> | |
51 | #include <linux/mii.h> | |
52 | #include <linux/ethtool.h> | |
53 | #include <linux/crc32.h> | |
54 | #include <linux/random.h> | |
55 | #include <linux/workqueue.h> | |
56 | #include <linux/if_vlan.h> | |
57 | #include <linux/bitops.h> | |
e3968fc0 | 58 | #include <linux/mutex.h> |
d7fe0f24 | 59 | #include <linux/mm.h> |
1da177e4 LT |
60 | |
61 | #include <asm/system.h> | |
62 | #include <asm/io.h> | |
63 | #include <asm/byteorder.h> | |
64 | #include <asm/uaccess.h> | |
65 | #include <asm/irq.h> | |
66 | ||
dadb830d | 67 | #ifdef CONFIG_SPARC |
1da177e4 | 68 | #include <asm/idprom.h> |
457e1a8a | 69 | #include <asm/prom.h> |
1da177e4 LT |
70 | #endif |
71 | ||
72 | #ifdef CONFIG_PPC_PMAC | |
73 | #include <asm/pci-bridge.h> | |
74 | #include <asm/prom.h> | |
75 | #include <asm/machdep.h> | |
76 | #include <asm/pmac_feature.h> | |
77 | #endif | |
78 | ||
79 | #include "sungem_phy.h" | |
80 | #include "sungem.h" | |
81 | ||
82 | /* Stripping FCS is causing problems, disabled for now */ | |
83 | #undef STRIP_FCS | |
84 | ||
85 | #define DEFAULT_MSG (NETIF_MSG_DRV | \ | |
86 | NETIF_MSG_PROBE | \ | |
87 | NETIF_MSG_LINK) | |
88 | ||
89 | #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \ | |
90 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \ | |
63ea998a BH |
91 | SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \ |
92 | SUPPORTED_Pause | SUPPORTED_Autoneg) | |
1da177e4 LT |
93 | |
94 | #define DRV_NAME "sungem" | |
95 | #define DRV_VERSION "0.98" | |
96 | #define DRV_RELDATE "8/24/03" | |
97 | #define DRV_AUTHOR "David S. Miller (davem@redhat.com)" | |
98 | ||
99 | static char version[] __devinitdata = | |
100 | DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n"; | |
101 | ||
102 | MODULE_AUTHOR(DRV_AUTHOR); | |
103 | MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver"); | |
104 | MODULE_LICENSE("GPL"); | |
105 | ||
106 | #define GEM_MODULE_NAME "gem" | |
107 | #define PFX GEM_MODULE_NAME ": " | |
108 | ||
109 | static struct pci_device_id gem_pci_tbl[] = { | |
110 | { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM, | |
111 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
112 | ||
113 | /* These models only differ from the original GEM in | |
114 | * that their tx/rx fifos are of a different size and | |
115 | * they only support 10/100 speeds. -DaveM | |
6aa20a22 | 116 | * |
1da177e4 LT |
117 | * Apple's GMAC does support gigabit on machines with |
118 | * the BCM54xx PHYs. -BenH | |
119 | */ | |
120 | { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM, | |
121 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
122 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC, | |
123 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
124 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP, | |
125 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
126 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2, | |
127 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
128 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC, | |
129 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
130 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM, | |
131 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
7fce260a OJ |
132 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC, |
133 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
1da177e4 LT |
134 | {0, } |
135 | }; | |
136 | ||
137 | MODULE_DEVICE_TABLE(pci, gem_pci_tbl); | |
138 | ||
139 | static u16 __phy_read(struct gem *gp, int phy_addr, int reg) | |
140 | { | |
141 | u32 cmd; | |
142 | int limit = 10000; | |
143 | ||
144 | cmd = (1 << 30); | |
145 | cmd |= (2 << 28); | |
146 | cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD; | |
147 | cmd |= (reg << 18) & MIF_FRAME_REGAD; | |
148 | cmd |= (MIF_FRAME_TAMSB); | |
149 | writel(cmd, gp->regs + MIF_FRAME); | |
150 | ||
46578a69 | 151 | while (--limit) { |
1da177e4 LT |
152 | cmd = readl(gp->regs + MIF_FRAME); |
153 | if (cmd & MIF_FRAME_TALSB) | |
154 | break; | |
155 | ||
156 | udelay(10); | |
157 | } | |
158 | ||
159 | if (!limit) | |
160 | cmd = 0xffff; | |
161 | ||
162 | return cmd & MIF_FRAME_DATA; | |
163 | } | |
164 | ||
165 | static inline int _phy_read(struct net_device *dev, int mii_id, int reg) | |
166 | { | |
8f15ea42 | 167 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
168 | return __phy_read(gp, mii_id, reg); |
169 | } | |
170 | ||
171 | static inline u16 phy_read(struct gem *gp, int reg) | |
172 | { | |
173 | return __phy_read(gp, gp->mii_phy_addr, reg); | |
174 | } | |
175 | ||
176 | static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val) | |
177 | { | |
178 | u32 cmd; | |
179 | int limit = 10000; | |
180 | ||
181 | cmd = (1 << 30); | |
182 | cmd |= (1 << 28); | |
183 | cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD; | |
184 | cmd |= (reg << 18) & MIF_FRAME_REGAD; | |
185 | cmd |= (MIF_FRAME_TAMSB); | |
186 | cmd |= (val & MIF_FRAME_DATA); | |
187 | writel(cmd, gp->regs + MIF_FRAME); | |
188 | ||
189 | while (limit--) { | |
190 | cmd = readl(gp->regs + MIF_FRAME); | |
191 | if (cmd & MIF_FRAME_TALSB) | |
192 | break; | |
193 | ||
194 | udelay(10); | |
195 | } | |
196 | } | |
197 | ||
198 | static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val) | |
199 | { | |
8f15ea42 | 200 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
201 | __phy_write(gp, mii_id, reg, val & 0xffff); |
202 | } | |
203 | ||
204 | static inline void phy_write(struct gem *gp, int reg, u16 val) | |
205 | { | |
206 | __phy_write(gp, gp->mii_phy_addr, reg, val); | |
207 | } | |
208 | ||
209 | static inline void gem_enable_ints(struct gem *gp) | |
210 | { | |
211 | /* Enable all interrupts but TXDONE */ | |
212 | writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); | |
213 | } | |
214 | ||
215 | static inline void gem_disable_ints(struct gem *gp) | |
216 | { | |
217 | /* Disable all interrupts, including TXDONE */ | |
218 | writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); | |
219 | } | |
220 | ||
221 | static void gem_get_cell(struct gem *gp) | |
222 | { | |
223 | BUG_ON(gp->cell_enabled < 0); | |
224 | gp->cell_enabled++; | |
225 | #ifdef CONFIG_PPC_PMAC | |
226 | if (gp->cell_enabled == 1) { | |
227 | mb(); | |
228 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1); | |
229 | udelay(10); | |
230 | } | |
231 | #endif /* CONFIG_PPC_PMAC */ | |
232 | } | |
233 | ||
234 | /* Turn off the chip's clock */ | |
235 | static void gem_put_cell(struct gem *gp) | |
236 | { | |
237 | BUG_ON(gp->cell_enabled <= 0); | |
238 | gp->cell_enabled--; | |
239 | #ifdef CONFIG_PPC_PMAC | |
240 | if (gp->cell_enabled == 0) { | |
241 | mb(); | |
242 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0); | |
243 | udelay(10); | |
244 | } | |
245 | #endif /* CONFIG_PPC_PMAC */ | |
246 | } | |
247 | ||
248 | static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits) | |
249 | { | |
250 | if (netif_msg_intr(gp)) | |
251 | printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name); | |
252 | } | |
253 | ||
254 | static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
255 | { | |
256 | u32 pcs_istat = readl(gp->regs + PCS_ISTAT); | |
257 | u32 pcs_miistat; | |
258 | ||
259 | if (netif_msg_intr(gp)) | |
260 | printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n", | |
261 | gp->dev->name, pcs_istat); | |
262 | ||
263 | if (!(pcs_istat & PCS_ISTAT_LSC)) { | |
264 | printk(KERN_ERR "%s: PCS irq but no link status change???\n", | |
265 | dev->name); | |
266 | return 0; | |
267 | } | |
268 | ||
269 | /* The link status bit latches on zero, so you must | |
270 | * read it twice in such a case to see a transition | |
271 | * to the link being up. | |
272 | */ | |
273 | pcs_miistat = readl(gp->regs + PCS_MIISTAT); | |
274 | if (!(pcs_miistat & PCS_MIISTAT_LS)) | |
275 | pcs_miistat |= | |
276 | (readl(gp->regs + PCS_MIISTAT) & | |
277 | PCS_MIISTAT_LS); | |
278 | ||
279 | if (pcs_miistat & PCS_MIISTAT_ANC) { | |
280 | /* The remote-fault indication is only valid | |
281 | * when autoneg has completed. | |
282 | */ | |
283 | if (pcs_miistat & PCS_MIISTAT_RF) | |
284 | printk(KERN_INFO "%s: PCS AutoNEG complete, " | |
285 | "RemoteFault\n", dev->name); | |
286 | else | |
287 | printk(KERN_INFO "%s: PCS AutoNEG complete.\n", | |
288 | dev->name); | |
289 | } | |
290 | ||
291 | if (pcs_miistat & PCS_MIISTAT_LS) { | |
292 | printk(KERN_INFO "%s: PCS link is now up.\n", | |
293 | dev->name); | |
294 | netif_carrier_on(gp->dev); | |
295 | } else { | |
296 | printk(KERN_INFO "%s: PCS link is now down.\n", | |
297 | dev->name); | |
298 | netif_carrier_off(gp->dev); | |
299 | /* If this happens and the link timer is not running, | |
300 | * reset so we re-negotiate. | |
301 | */ | |
302 | if (!timer_pending(&gp->link_timer)) | |
303 | return 1; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
310 | { | |
311 | u32 txmac_stat = readl(gp->regs + MAC_TXSTAT); | |
312 | ||
313 | if (netif_msg_intr(gp)) | |
314 | printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n", | |
315 | gp->dev->name, txmac_stat); | |
316 | ||
317 | /* Defer timer expiration is quite normal, | |
318 | * don't even log the event. | |
319 | */ | |
320 | if ((txmac_stat & MAC_TXSTAT_DTE) && | |
321 | !(txmac_stat & ~MAC_TXSTAT_DTE)) | |
322 | return 0; | |
323 | ||
324 | if (txmac_stat & MAC_TXSTAT_URUN) { | |
325 | printk(KERN_ERR "%s: TX MAC xmit underrun.\n", | |
326 | dev->name); | |
327 | gp->net_stats.tx_fifo_errors++; | |
328 | } | |
329 | ||
330 | if (txmac_stat & MAC_TXSTAT_MPE) { | |
331 | printk(KERN_ERR "%s: TX MAC max packet size error.\n", | |
332 | dev->name); | |
333 | gp->net_stats.tx_errors++; | |
334 | } | |
335 | ||
336 | /* The rest are all cases of one of the 16-bit TX | |
337 | * counters expiring. | |
338 | */ | |
339 | if (txmac_stat & MAC_TXSTAT_NCE) | |
340 | gp->net_stats.collisions += 0x10000; | |
341 | ||
342 | if (txmac_stat & MAC_TXSTAT_ECE) { | |
343 | gp->net_stats.tx_aborted_errors += 0x10000; | |
344 | gp->net_stats.collisions += 0x10000; | |
345 | } | |
346 | ||
347 | if (txmac_stat & MAC_TXSTAT_LCE) { | |
348 | gp->net_stats.tx_aborted_errors += 0x10000; | |
349 | gp->net_stats.collisions += 0x10000; | |
350 | } | |
351 | ||
352 | /* We do not keep track of MAC_TXSTAT_FCE and | |
353 | * MAC_TXSTAT_PCE events. | |
354 | */ | |
355 | return 0; | |
356 | } | |
357 | ||
358 | /* When we get a RX fifo overflow, the RX unit in GEM is probably hung | |
359 | * so we do the following. | |
360 | * | |
361 | * If any part of the reset goes wrong, we return 1 and that causes the | |
362 | * whole chip to be reset. | |
363 | */ | |
364 | static int gem_rxmac_reset(struct gem *gp) | |
365 | { | |
366 | struct net_device *dev = gp->dev; | |
367 | int limit, i; | |
368 | u64 desc_dma; | |
369 | u32 val; | |
370 | ||
371 | /* First, reset & disable MAC RX. */ | |
372 | writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); | |
373 | for (limit = 0; limit < 5000; limit++) { | |
374 | if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD)) | |
375 | break; | |
376 | udelay(10); | |
377 | } | |
378 | if (limit == 5000) { | |
379 | printk(KERN_ERR "%s: RX MAC will not reset, resetting whole " | |
380 | "chip.\n", dev->name); | |
381 | return 1; | |
382 | } | |
383 | ||
384 | writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, | |
385 | gp->regs + MAC_RXCFG); | |
386 | for (limit = 0; limit < 5000; limit++) { | |
387 | if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB)) | |
388 | break; | |
389 | udelay(10); | |
390 | } | |
391 | if (limit == 5000) { | |
392 | printk(KERN_ERR "%s: RX MAC will not disable, resetting whole " | |
393 | "chip.\n", dev->name); | |
394 | return 1; | |
395 | } | |
396 | ||
397 | /* Second, disable RX DMA. */ | |
398 | writel(0, gp->regs + RXDMA_CFG); | |
399 | for (limit = 0; limit < 5000; limit++) { | |
400 | if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE)) | |
401 | break; | |
402 | udelay(10); | |
403 | } | |
404 | if (limit == 5000) { | |
405 | printk(KERN_ERR "%s: RX DMA will not disable, resetting whole " | |
406 | "chip.\n", dev->name); | |
407 | return 1; | |
408 | } | |
409 | ||
410 | udelay(5000); | |
411 | ||
412 | /* Execute RX reset command. */ | |
413 | writel(gp->swrst_base | GREG_SWRST_RXRST, | |
414 | gp->regs + GREG_SWRST); | |
415 | for (limit = 0; limit < 5000; limit++) { | |
416 | if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST)) | |
417 | break; | |
418 | udelay(10); | |
419 | } | |
420 | if (limit == 5000) { | |
421 | printk(KERN_ERR "%s: RX reset command will not execute, resetting " | |
422 | "whole chip.\n", dev->name); | |
423 | return 1; | |
424 | } | |
425 | ||
426 | /* Refresh the RX ring. */ | |
427 | for (i = 0; i < RX_RING_SIZE; i++) { | |
428 | struct gem_rxd *rxd = &gp->init_block->rxd[i]; | |
429 | ||
430 | if (gp->rx_skbs[i] == NULL) { | |
431 | printk(KERN_ERR "%s: Parts of RX ring empty, resetting " | |
432 | "whole chip.\n", dev->name); | |
433 | return 1; | |
434 | } | |
435 | ||
436 | rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); | |
437 | } | |
438 | gp->rx_new = gp->rx_old = 0; | |
439 | ||
440 | /* Now we must reprogram the rest of RX unit. */ | |
441 | desc_dma = (u64) gp->gblock_dvma; | |
442 | desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd)); | |
443 | writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); | |
444 | writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); | |
445 | writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); | |
446 | val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) | | |
447 | ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128); | |
448 | writel(val, gp->regs + RXDMA_CFG); | |
449 | if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) | |
450 | writel(((5 & RXDMA_BLANK_IPKTS) | | |
451 | ((8 << 12) & RXDMA_BLANK_ITIME)), | |
452 | gp->regs + RXDMA_BLANK); | |
453 | else | |
454 | writel(((5 & RXDMA_BLANK_IPKTS) | | |
455 | ((4 << 12) & RXDMA_BLANK_ITIME)), | |
456 | gp->regs + RXDMA_BLANK); | |
457 | val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); | |
458 | val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); | |
459 | writel(val, gp->regs + RXDMA_PTHRESH); | |
460 | val = readl(gp->regs + RXDMA_CFG); | |
461 | writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); | |
462 | writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); | |
463 | val = readl(gp->regs + MAC_RXCFG); | |
464 | writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
470 | { | |
471 | u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT); | |
472 | int ret = 0; | |
473 | ||
474 | if (netif_msg_intr(gp)) | |
475 | printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n", | |
476 | gp->dev->name, rxmac_stat); | |
477 | ||
478 | if (rxmac_stat & MAC_RXSTAT_OFLW) { | |
479 | u32 smac = readl(gp->regs + MAC_SMACHINE); | |
480 | ||
481 | printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n", | |
482 | dev->name, smac); | |
483 | gp->net_stats.rx_over_errors++; | |
484 | gp->net_stats.rx_fifo_errors++; | |
485 | ||
486 | ret = gem_rxmac_reset(gp); | |
487 | } | |
488 | ||
489 | if (rxmac_stat & MAC_RXSTAT_ACE) | |
490 | gp->net_stats.rx_frame_errors += 0x10000; | |
491 | ||
492 | if (rxmac_stat & MAC_RXSTAT_CCE) | |
493 | gp->net_stats.rx_crc_errors += 0x10000; | |
494 | ||
495 | if (rxmac_stat & MAC_RXSTAT_LCE) | |
496 | gp->net_stats.rx_length_errors += 0x10000; | |
497 | ||
498 | /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE | |
499 | * events. | |
500 | */ | |
501 | return ret; | |
502 | } | |
503 | ||
504 | static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
505 | { | |
506 | u32 mac_cstat = readl(gp->regs + MAC_CSTAT); | |
507 | ||
508 | if (netif_msg_intr(gp)) | |
509 | printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n", | |
510 | gp->dev->name, mac_cstat); | |
511 | ||
512 | /* This interrupt is just for pause frame and pause | |
513 | * tracking. It is useful for diagnostics and debug | |
514 | * but probably by default we will mask these events. | |
515 | */ | |
516 | if (mac_cstat & MAC_CSTAT_PS) | |
517 | gp->pause_entered++; | |
518 | ||
519 | if (mac_cstat & MAC_CSTAT_PRCV) | |
520 | gp->pause_last_time_recvd = (mac_cstat >> 16); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
526 | { | |
527 | u32 mif_status = readl(gp->regs + MIF_STATUS); | |
528 | u32 reg_val, changed_bits; | |
529 | ||
530 | reg_val = (mif_status & MIF_STATUS_DATA) >> 16; | |
531 | changed_bits = (mif_status & MIF_STATUS_STAT); | |
532 | ||
533 | gem_handle_mif_event(gp, reg_val, changed_bits); | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
538 | static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
539 | { | |
540 | u32 pci_estat = readl(gp->regs + GREG_PCIESTAT); | |
541 | ||
542 | if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && | |
543 | gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { | |
544 | printk(KERN_ERR "%s: PCI error [%04x] ", | |
545 | dev->name, pci_estat); | |
546 | ||
547 | if (pci_estat & GREG_PCIESTAT_BADACK) | |
548 | printk("<No ACK64# during ABS64 cycle> "); | |
549 | if (pci_estat & GREG_PCIESTAT_DTRTO) | |
550 | printk("<Delayed transaction timeout> "); | |
551 | if (pci_estat & GREG_PCIESTAT_OTHER) | |
552 | printk("<other>"); | |
553 | printk("\n"); | |
554 | } else { | |
555 | pci_estat |= GREG_PCIESTAT_OTHER; | |
556 | printk(KERN_ERR "%s: PCI error\n", dev->name); | |
557 | } | |
558 | ||
559 | if (pci_estat & GREG_PCIESTAT_OTHER) { | |
560 | u16 pci_cfg_stat; | |
561 | ||
562 | /* Interrogate PCI config space for the | |
563 | * true cause. | |
564 | */ | |
565 | pci_read_config_word(gp->pdev, PCI_STATUS, | |
566 | &pci_cfg_stat); | |
567 | printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n", | |
568 | dev->name, pci_cfg_stat); | |
569 | if (pci_cfg_stat & PCI_STATUS_PARITY) | |
570 | printk(KERN_ERR "%s: PCI parity error detected.\n", | |
571 | dev->name); | |
572 | if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT) | |
573 | printk(KERN_ERR "%s: PCI target abort.\n", | |
574 | dev->name); | |
575 | if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT) | |
576 | printk(KERN_ERR "%s: PCI master acks target abort.\n", | |
577 | dev->name); | |
578 | if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT) | |
579 | printk(KERN_ERR "%s: PCI master abort.\n", | |
580 | dev->name); | |
581 | if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR) | |
582 | printk(KERN_ERR "%s: PCI system error SERR#.\n", | |
583 | dev->name); | |
584 | if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY) | |
585 | printk(KERN_ERR "%s: PCI parity error.\n", | |
586 | dev->name); | |
587 | ||
588 | /* Write the error bits back to clear them. */ | |
589 | pci_cfg_stat &= (PCI_STATUS_PARITY | | |
590 | PCI_STATUS_SIG_TARGET_ABORT | | |
591 | PCI_STATUS_REC_TARGET_ABORT | | |
592 | PCI_STATUS_REC_MASTER_ABORT | | |
593 | PCI_STATUS_SIG_SYSTEM_ERROR | | |
594 | PCI_STATUS_DETECTED_PARITY); | |
595 | pci_write_config_word(gp->pdev, | |
596 | PCI_STATUS, pci_cfg_stat); | |
597 | } | |
598 | ||
599 | /* For all PCI errors, we should reset the chip. */ | |
600 | return 1; | |
601 | } | |
602 | ||
603 | /* All non-normal interrupt conditions get serviced here. | |
604 | * Returns non-zero if we should just exit the interrupt | |
605 | * handler right now (ie. if we reset the card which invalidates | |
606 | * all of the other original irq status bits). | |
607 | */ | |
608 | static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status) | |
609 | { | |
610 | if (gem_status & GREG_STAT_RXNOBUF) { | |
611 | /* Frame arrived, no free RX buffers available. */ | |
612 | if (netif_msg_rx_err(gp)) | |
613 | printk(KERN_DEBUG "%s: no buffer for rx frame\n", | |
614 | gp->dev->name); | |
615 | gp->net_stats.rx_dropped++; | |
616 | } | |
617 | ||
618 | if (gem_status & GREG_STAT_RXTAGERR) { | |
619 | /* corrupt RX tag framing */ | |
620 | if (netif_msg_rx_err(gp)) | |
621 | printk(KERN_DEBUG "%s: corrupt rx tag framing\n", | |
622 | gp->dev->name); | |
623 | gp->net_stats.rx_errors++; | |
624 | ||
625 | goto do_reset; | |
626 | } | |
627 | ||
628 | if (gem_status & GREG_STAT_PCS) { | |
629 | if (gem_pcs_interrupt(dev, gp, gem_status)) | |
630 | goto do_reset; | |
631 | } | |
632 | ||
633 | if (gem_status & GREG_STAT_TXMAC) { | |
634 | if (gem_txmac_interrupt(dev, gp, gem_status)) | |
635 | goto do_reset; | |
636 | } | |
637 | ||
638 | if (gem_status & GREG_STAT_RXMAC) { | |
639 | if (gem_rxmac_interrupt(dev, gp, gem_status)) | |
640 | goto do_reset; | |
641 | } | |
642 | ||
643 | if (gem_status & GREG_STAT_MAC) { | |
644 | if (gem_mac_interrupt(dev, gp, gem_status)) | |
645 | goto do_reset; | |
646 | } | |
647 | ||
648 | if (gem_status & GREG_STAT_MIF) { | |
649 | if (gem_mif_interrupt(dev, gp, gem_status)) | |
650 | goto do_reset; | |
651 | } | |
652 | ||
653 | if (gem_status & GREG_STAT_PCIERR) { | |
654 | if (gem_pci_interrupt(dev, gp, gem_status)) | |
655 | goto do_reset; | |
656 | } | |
657 | ||
658 | return 0; | |
659 | ||
660 | do_reset: | |
661 | gp->reset_task_pending = 1; | |
662 | schedule_work(&gp->reset_task); | |
663 | ||
664 | return 1; | |
665 | } | |
666 | ||
667 | static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status) | |
668 | { | |
669 | int entry, limit; | |
670 | ||
671 | if (netif_msg_intr(gp)) | |
672 | printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n", | |
673 | gp->dev->name, gem_status); | |
674 | ||
675 | entry = gp->tx_old; | |
676 | limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT); | |
677 | while (entry != limit) { | |
678 | struct sk_buff *skb; | |
679 | struct gem_txd *txd; | |
680 | dma_addr_t dma_addr; | |
681 | u32 dma_len; | |
682 | int frag; | |
683 | ||
684 | if (netif_msg_tx_done(gp)) | |
685 | printk(KERN_DEBUG "%s: tx done, slot %d\n", | |
686 | gp->dev->name, entry); | |
687 | skb = gp->tx_skbs[entry]; | |
688 | if (skb_shinfo(skb)->nr_frags) { | |
689 | int last = entry + skb_shinfo(skb)->nr_frags; | |
690 | int walk = entry; | |
691 | int incomplete = 0; | |
692 | ||
693 | last &= (TX_RING_SIZE - 1); | |
694 | for (;;) { | |
695 | walk = NEXT_TX(walk); | |
696 | if (walk == limit) | |
697 | incomplete = 1; | |
698 | if (walk == last) | |
699 | break; | |
700 | } | |
701 | if (incomplete) | |
702 | break; | |
703 | } | |
704 | gp->tx_skbs[entry] = NULL; | |
705 | gp->net_stats.tx_bytes += skb->len; | |
706 | ||
707 | for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { | |
708 | txd = &gp->init_block->txd[entry]; | |
709 | ||
710 | dma_addr = le64_to_cpu(txd->buffer); | |
711 | dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ; | |
712 | ||
713 | pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); | |
714 | entry = NEXT_TX(entry); | |
715 | } | |
716 | ||
717 | gp->net_stats.tx_packets++; | |
718 | dev_kfree_skb_irq(skb); | |
719 | } | |
720 | gp->tx_old = entry; | |
721 | ||
722 | if (netif_queue_stopped(dev) && | |
723 | TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) | |
724 | netif_wake_queue(dev); | |
725 | } | |
726 | ||
727 | static __inline__ void gem_post_rxds(struct gem *gp, int limit) | |
728 | { | |
729 | int cluster_start, curr, count, kick; | |
730 | ||
731 | cluster_start = curr = (gp->rx_new & ~(4 - 1)); | |
732 | count = 0; | |
733 | kick = -1; | |
734 | wmb(); | |
735 | while (curr != limit) { | |
736 | curr = NEXT_RX(curr); | |
737 | if (++count == 4) { | |
738 | struct gem_rxd *rxd = | |
739 | &gp->init_block->rxd[cluster_start]; | |
740 | for (;;) { | |
741 | rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); | |
742 | rxd++; | |
743 | cluster_start = NEXT_RX(cluster_start); | |
744 | if (cluster_start == curr) | |
745 | break; | |
746 | } | |
747 | kick = curr; | |
748 | count = 0; | |
749 | } | |
750 | } | |
751 | if (kick >= 0) { | |
752 | mb(); | |
753 | writel(kick, gp->regs + RXDMA_KICK); | |
754 | } | |
755 | } | |
756 | ||
757 | static int gem_rx(struct gem *gp, int work_to_do) | |
758 | { | |
759 | int entry, drops, work_done = 0; | |
760 | u32 done; | |
439104b3 | 761 | __sum16 csum; |
1da177e4 LT |
762 | |
763 | if (netif_msg_rx_status(gp)) | |
764 | printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n", | |
765 | gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new); | |
766 | ||
767 | entry = gp->rx_new; | |
768 | drops = 0; | |
769 | done = readl(gp->regs + RXDMA_DONE); | |
770 | for (;;) { | |
771 | struct gem_rxd *rxd = &gp->init_block->rxd[entry]; | |
772 | struct sk_buff *skb; | |
439104b3 | 773 | u64 status = le64_to_cpu(rxd->status_word); |
1da177e4 LT |
774 | dma_addr_t dma_addr; |
775 | int len; | |
776 | ||
777 | if ((status & RXDCTRL_OWN) != 0) | |
778 | break; | |
779 | ||
780 | if (work_done >= RX_RING_SIZE || work_done >= work_to_do) | |
781 | break; | |
782 | ||
783 | /* When writing back RX descriptor, GEM writes status | |
784 | * then buffer address, possibly in seperate transactions. | |
785 | * If we don't wait for the chip to write both, we could | |
786 | * post a new buffer to this descriptor then have GEM spam | |
787 | * on the buffer address. We sync on the RX completion | |
788 | * register to prevent this from happening. | |
789 | */ | |
790 | if (entry == done) { | |
791 | done = readl(gp->regs + RXDMA_DONE); | |
792 | if (entry == done) | |
793 | break; | |
794 | } | |
795 | ||
796 | /* We can now account for the work we're about to do */ | |
797 | work_done++; | |
798 | ||
799 | skb = gp->rx_skbs[entry]; | |
800 | ||
801 | len = (status & RXDCTRL_BUFSZ) >> 16; | |
802 | if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) { | |
803 | gp->net_stats.rx_errors++; | |
804 | if (len < ETH_ZLEN) | |
805 | gp->net_stats.rx_length_errors++; | |
806 | if (len & RXDCTRL_BAD) | |
807 | gp->net_stats.rx_crc_errors++; | |
808 | ||
809 | /* We'll just return it to GEM. */ | |
810 | drop_it: | |
811 | gp->net_stats.rx_dropped++; | |
812 | goto next; | |
813 | } | |
814 | ||
439104b3 | 815 | dma_addr = le64_to_cpu(rxd->buffer); |
1da177e4 LT |
816 | if (len > RX_COPY_THRESHOLD) { |
817 | struct sk_buff *new_skb; | |
818 | ||
819 | new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC); | |
820 | if (new_skb == NULL) { | |
821 | drops++; | |
822 | goto drop_it; | |
823 | } | |
824 | pci_unmap_page(gp->pdev, dma_addr, | |
825 | RX_BUF_ALLOC_SIZE(gp), | |
826 | PCI_DMA_FROMDEVICE); | |
827 | gp->rx_skbs[entry] = new_skb; | |
828 | new_skb->dev = gp->dev; | |
829 | skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET)); | |
830 | rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev, | |
831 | virt_to_page(new_skb->data), | |
832 | offset_in_page(new_skb->data), | |
833 | RX_BUF_ALLOC_SIZE(gp), | |
834 | PCI_DMA_FROMDEVICE)); | |
835 | skb_reserve(new_skb, RX_OFFSET); | |
836 | ||
837 | /* Trim the original skb for the netif. */ | |
838 | skb_trim(skb, len); | |
839 | } else { | |
840 | struct sk_buff *copy_skb = dev_alloc_skb(len + 2); | |
841 | ||
842 | if (copy_skb == NULL) { | |
843 | drops++; | |
844 | goto drop_it; | |
845 | } | |
846 | ||
1da177e4 LT |
847 | skb_reserve(copy_skb, 2); |
848 | skb_put(copy_skb, len); | |
849 | pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 850 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
851 | pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
852 | ||
853 | /* We'll reuse the original ring buffer. */ | |
854 | skb = copy_skb; | |
855 | } | |
856 | ||
439104b3 AV |
857 | csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff); |
858 | skb->csum = csum_unfold(csum); | |
84fa7933 | 859 | skb->ip_summed = CHECKSUM_COMPLETE; |
1da177e4 LT |
860 | skb->protocol = eth_type_trans(skb, gp->dev); |
861 | ||
862 | netif_receive_skb(skb); | |
863 | ||
864 | gp->net_stats.rx_packets++; | |
865 | gp->net_stats.rx_bytes += len; | |
1da177e4 LT |
866 | |
867 | next: | |
868 | entry = NEXT_RX(entry); | |
869 | } | |
870 | ||
871 | gem_post_rxds(gp, entry); | |
872 | ||
873 | gp->rx_new = entry; | |
874 | ||
875 | if (drops) | |
876 | printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", | |
877 | gp->dev->name); | |
878 | ||
879 | return work_done; | |
880 | } | |
881 | ||
bea3348e | 882 | static int gem_poll(struct napi_struct *napi, int budget) |
1da177e4 | 883 | { |
bea3348e SH |
884 | struct gem *gp = container_of(napi, struct gem, napi); |
885 | struct net_device *dev = gp->dev; | |
1da177e4 | 886 | unsigned long flags; |
bea3348e | 887 | int work_done; |
1da177e4 LT |
888 | |
889 | /* | |
6aa20a22 | 890 | * NAPI locking nightmare: See comment at head of driver |
1da177e4 LT |
891 | */ |
892 | spin_lock_irqsave(&gp->lock, flags); | |
893 | ||
bea3348e | 894 | work_done = 0; |
1da177e4 | 895 | do { |
1da177e4 LT |
896 | /* Handle anomalies */ |
897 | if (gp->status & GREG_STAT_ABNORMAL) { | |
898 | if (gem_abnormal_irq(dev, gp, gp->status)) | |
899 | break; | |
900 | } | |
901 | ||
902 | /* Run TX completion thread */ | |
903 | spin_lock(&gp->tx_lock); | |
904 | gem_tx(dev, gp, gp->status); | |
905 | spin_unlock(&gp->tx_lock); | |
906 | ||
907 | spin_unlock_irqrestore(&gp->lock, flags); | |
908 | ||
6aa20a22 JG |
909 | /* Run RX thread. We don't use any locking here, |
910 | * code willing to do bad things - like cleaning the | |
bea3348e | 911 | * rx ring - must call napi_disable(), which |
1da177e4 LT |
912 | * schedule_timeout()'s if polling is already disabled. |
913 | */ | |
da990a24 | 914 | work_done += gem_rx(gp, budget - work_done); |
1da177e4 | 915 | |
bea3348e SH |
916 | if (work_done >= budget) |
917 | return work_done; | |
1da177e4 LT |
918 | |
919 | spin_lock_irqsave(&gp->lock, flags); | |
6aa20a22 | 920 | |
1da177e4 LT |
921 | gp->status = readl(gp->regs + GREG_STAT); |
922 | } while (gp->status & GREG_STAT_NAPI); | |
923 | ||
288379f0 | 924 | __napi_complete(napi); |
1da177e4 LT |
925 | gem_enable_ints(gp); |
926 | ||
927 | spin_unlock_irqrestore(&gp->lock, flags); | |
bea3348e SH |
928 | |
929 | return work_done; | |
1da177e4 LT |
930 | } |
931 | ||
7d12e780 | 932 | static irqreturn_t gem_interrupt(int irq, void *dev_id) |
1da177e4 LT |
933 | { |
934 | struct net_device *dev = dev_id; | |
8f15ea42 | 935 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
936 | unsigned long flags; |
937 | ||
938 | /* Swallow interrupts when shutting the chip down, though | |
939 | * that shouldn't happen, we should have done free_irq() at | |
940 | * this point... | |
941 | */ | |
942 | if (!gp->running) | |
943 | return IRQ_HANDLED; | |
944 | ||
945 | spin_lock_irqsave(&gp->lock, flags); | |
6aa20a22 | 946 | |
288379f0 | 947 | if (napi_schedule_prep(&gp->napi)) { |
1da177e4 LT |
948 | u32 gem_status = readl(gp->regs + GREG_STAT); |
949 | ||
950 | if (gem_status == 0) { | |
bea3348e | 951 | napi_enable(&gp->napi); |
1da177e4 LT |
952 | spin_unlock_irqrestore(&gp->lock, flags); |
953 | return IRQ_NONE; | |
954 | } | |
955 | gp->status = gem_status; | |
956 | gem_disable_ints(gp); | |
288379f0 | 957 | __napi_schedule(&gp->napi); |
1da177e4 LT |
958 | } |
959 | ||
960 | spin_unlock_irqrestore(&gp->lock, flags); | |
6aa20a22 | 961 | |
1da177e4 | 962 | /* If polling was disabled at the time we received that |
6aa20a22 | 963 | * interrupt, we may return IRQ_HANDLED here while we |
1da177e4 LT |
964 | * should return IRQ_NONE. No big deal... |
965 | */ | |
966 | return IRQ_HANDLED; | |
967 | } | |
968 | ||
969 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
970 | static void gem_poll_controller(struct net_device *dev) | |
971 | { | |
972 | /* gem_interrupt is safe to reentrance so no need | |
973 | * to disable_irq here. | |
974 | */ | |
7d12e780 | 975 | gem_interrupt(dev->irq, dev); |
1da177e4 LT |
976 | } |
977 | #endif | |
978 | ||
979 | static void gem_tx_timeout(struct net_device *dev) | |
980 | { | |
8f15ea42 | 981 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
982 | |
983 | printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name); | |
984 | if (!gp->running) { | |
985 | printk("%s: hrm.. hw not running !\n", dev->name); | |
986 | return; | |
987 | } | |
988 | printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n", | |
989 | dev->name, | |
990 | readl(gp->regs + TXDMA_CFG), | |
991 | readl(gp->regs + MAC_TXSTAT), | |
992 | readl(gp->regs + MAC_TXCFG)); | |
993 | printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n", | |
994 | dev->name, | |
995 | readl(gp->regs + RXDMA_CFG), | |
996 | readl(gp->regs + MAC_RXSTAT), | |
997 | readl(gp->regs + MAC_RXCFG)); | |
998 | ||
999 | spin_lock_irq(&gp->lock); | |
1000 | spin_lock(&gp->tx_lock); | |
1001 | ||
1002 | gp->reset_task_pending = 1; | |
1003 | schedule_work(&gp->reset_task); | |
1004 | ||
1005 | spin_unlock(&gp->tx_lock); | |
1006 | spin_unlock_irq(&gp->lock); | |
1007 | } | |
1008 | ||
1009 | static __inline__ int gem_intme(int entry) | |
1010 | { | |
1011 | /* Algorithm: IRQ every 1/2 of descriptors. */ | |
1012 | if (!(entry & ((TX_RING_SIZE>>1)-1))) | |
1013 | return 1; | |
1014 | ||
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1019 | { | |
8f15ea42 | 1020 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
1021 | int entry; |
1022 | u64 ctrl; | |
1023 | unsigned long flags; | |
1024 | ||
1025 | ctrl = 0; | |
84fa7933 | 1026 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
ea2ae17d ACM |
1027 | const u64 csum_start_off = skb_transport_offset(skb); |
1028 | const u64 csum_stuff_off = csum_start_off + skb->csum_offset; | |
1da177e4 LT |
1029 | |
1030 | ctrl = (TXDCTRL_CENAB | | |
1031 | (csum_start_off << 15) | | |
1032 | (csum_stuff_off << 21)); | |
1033 | } | |
1034 | ||
1035 | local_irq_save(flags); | |
1036 | if (!spin_trylock(&gp->tx_lock)) { | |
1037 | /* Tell upper layer to requeue */ | |
1038 | local_irq_restore(flags); | |
1039 | return NETDEV_TX_LOCKED; | |
1040 | } | |
1041 | /* We raced with gem_do_stop() */ | |
1042 | if (!gp->running) { | |
1043 | spin_unlock_irqrestore(&gp->tx_lock, flags); | |
1044 | return NETDEV_TX_BUSY; | |
1045 | } | |
1046 | ||
1047 | /* This is a hard error, log it. */ | |
1048 | if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) { | |
1049 | netif_stop_queue(dev); | |
1050 | spin_unlock_irqrestore(&gp->tx_lock, flags); | |
1051 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n", | |
1052 | dev->name); | |
1053 | return NETDEV_TX_BUSY; | |
1054 | } | |
1055 | ||
1056 | entry = gp->tx_new; | |
1057 | gp->tx_skbs[entry] = skb; | |
1058 | ||
1059 | if (skb_shinfo(skb)->nr_frags == 0) { | |
1060 | struct gem_txd *txd = &gp->init_block->txd[entry]; | |
1061 | dma_addr_t mapping; | |
1062 | u32 len; | |
1063 | ||
1064 | len = skb->len; | |
1065 | mapping = pci_map_page(gp->pdev, | |
1066 | virt_to_page(skb->data), | |
1067 | offset_in_page(skb->data), | |
1068 | len, PCI_DMA_TODEVICE); | |
1069 | ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len; | |
1070 | if (gem_intme(entry)) | |
1071 | ctrl |= TXDCTRL_INTME; | |
1072 | txd->buffer = cpu_to_le64(mapping); | |
1073 | wmb(); | |
1074 | txd->control_word = cpu_to_le64(ctrl); | |
1075 | entry = NEXT_TX(entry); | |
1076 | } else { | |
1077 | struct gem_txd *txd; | |
1078 | u32 first_len; | |
1079 | u64 intme; | |
1080 | dma_addr_t first_mapping; | |
1081 | int frag, first_entry = entry; | |
1082 | ||
1083 | intme = 0; | |
1084 | if (gem_intme(entry)) | |
1085 | intme |= TXDCTRL_INTME; | |
1086 | ||
1087 | /* We must give this initial chunk to the device last. | |
1088 | * Otherwise we could race with the device. | |
1089 | */ | |
1090 | first_len = skb_headlen(skb); | |
1091 | first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data), | |
1092 | offset_in_page(skb->data), | |
1093 | first_len, PCI_DMA_TODEVICE); | |
1094 | entry = NEXT_TX(entry); | |
1095 | ||
1096 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { | |
1097 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
1098 | u32 len; | |
1099 | dma_addr_t mapping; | |
1100 | u64 this_ctrl; | |
1101 | ||
1102 | len = this_frag->size; | |
1103 | mapping = pci_map_page(gp->pdev, | |
1104 | this_frag->page, | |
1105 | this_frag->page_offset, | |
1106 | len, PCI_DMA_TODEVICE); | |
1107 | this_ctrl = ctrl; | |
1108 | if (frag == skb_shinfo(skb)->nr_frags - 1) | |
1109 | this_ctrl |= TXDCTRL_EOF; | |
6aa20a22 | 1110 | |
1da177e4 LT |
1111 | txd = &gp->init_block->txd[entry]; |
1112 | txd->buffer = cpu_to_le64(mapping); | |
1113 | wmb(); | |
1114 | txd->control_word = cpu_to_le64(this_ctrl | len); | |
1115 | ||
1116 | if (gem_intme(entry)) | |
1117 | intme |= TXDCTRL_INTME; | |
1118 | ||
1119 | entry = NEXT_TX(entry); | |
1120 | } | |
1121 | txd = &gp->init_block->txd[first_entry]; | |
1122 | txd->buffer = cpu_to_le64(first_mapping); | |
1123 | wmb(); | |
1124 | txd->control_word = | |
1125 | cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len); | |
1126 | } | |
1127 | ||
1128 | gp->tx_new = entry; | |
1129 | if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1)) | |
1130 | netif_stop_queue(dev); | |
1131 | ||
1132 | if (netif_msg_tx_queued(gp)) | |
1133 | printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n", | |
1134 | dev->name, entry, skb->len); | |
1135 | mb(); | |
1136 | writel(gp->tx_new, gp->regs + TXDMA_KICK); | |
1137 | spin_unlock_irqrestore(&gp->tx_lock, flags); | |
1138 | ||
1139 | dev->trans_start = jiffies; | |
1140 | ||
1141 | return NETDEV_TX_OK; | |
1142 | } | |
1143 | ||
8c83f80b DM |
1144 | static void gem_pcs_reset(struct gem *gp) |
1145 | { | |
1146 | int limit; | |
1147 | u32 val; | |
1148 | ||
1149 | /* Reset PCS unit. */ | |
1150 | val = readl(gp->regs + PCS_MIICTRL); | |
1151 | val |= PCS_MIICTRL_RST; | |
1152 | writel(val, gp->regs + PCS_MIICTRL); | |
1153 | ||
1154 | limit = 32; | |
1155 | while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) { | |
1156 | udelay(100); | |
1157 | if (limit-- <= 0) | |
1158 | break; | |
1159 | } | |
d13c11f6 | 1160 | if (limit < 0) |
8c83f80b DM |
1161 | printk(KERN_WARNING "%s: PCS reset bit would not clear.\n", |
1162 | gp->dev->name); | |
1163 | } | |
1164 | ||
1165 | static void gem_pcs_reinit_adv(struct gem *gp) | |
1166 | { | |
1167 | u32 val; | |
1168 | ||
1169 | /* Make sure PCS is disabled while changing advertisement | |
1170 | * configuration. | |
1171 | */ | |
1172 | val = readl(gp->regs + PCS_CFG); | |
1173 | val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO); | |
1174 | writel(val, gp->regs + PCS_CFG); | |
1175 | ||
1176 | /* Advertise all capabilities except assymetric | |
1177 | * pause. | |
1178 | */ | |
1179 | val = readl(gp->regs + PCS_MIIADV); | |
1180 | val |= (PCS_MIIADV_FD | PCS_MIIADV_HD | | |
1181 | PCS_MIIADV_SP | PCS_MIIADV_AP); | |
1182 | writel(val, gp->regs + PCS_MIIADV); | |
1183 | ||
1184 | /* Enable and restart auto-negotiation, disable wrapback/loopback, | |
1185 | * and re-enable PCS. | |
1186 | */ | |
1187 | val = readl(gp->regs + PCS_MIICTRL); | |
1188 | val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE); | |
1189 | val &= ~PCS_MIICTRL_WB; | |
1190 | writel(val, gp->regs + PCS_MIICTRL); | |
1191 | ||
1192 | val = readl(gp->regs + PCS_CFG); | |
1193 | val |= PCS_CFG_ENABLE; | |
1194 | writel(val, gp->regs + PCS_CFG); | |
1195 | ||
1196 | /* Make sure serialink loopback is off. The meaning | |
1197 | * of this bit is logically inverted based upon whether | |
1198 | * you are in Serialink or SERDES mode. | |
1199 | */ | |
1200 | val = readl(gp->regs + PCS_SCTRL); | |
1201 | if (gp->phy_type == phy_serialink) | |
1202 | val &= ~PCS_SCTRL_LOOP; | |
1203 | else | |
1204 | val |= PCS_SCTRL_LOOP; | |
1205 | writel(val, gp->regs + PCS_SCTRL); | |
1206 | } | |
1207 | ||
1da177e4 LT |
1208 | #define STOP_TRIES 32 |
1209 | ||
1210 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1211 | static void gem_reset(struct gem *gp) | |
1212 | { | |
1213 | int limit; | |
1214 | u32 val; | |
1215 | ||
1216 | /* Make sure we won't get any more interrupts */ | |
1217 | writel(0xffffffff, gp->regs + GREG_IMASK); | |
1218 | ||
1219 | /* Reset the chip */ | |
1220 | writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST, | |
1221 | gp->regs + GREG_SWRST); | |
1222 | ||
1223 | limit = STOP_TRIES; | |
1224 | ||
1225 | do { | |
1226 | udelay(20); | |
1227 | val = readl(gp->regs + GREG_SWRST); | |
1228 | if (limit-- <= 0) | |
1229 | break; | |
1230 | } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST)); | |
1231 | ||
4a8fd2cf | 1232 | if (limit < 0) |
1da177e4 | 1233 | printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name); |
8c83f80b DM |
1234 | |
1235 | if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes) | |
1236 | gem_pcs_reinit_adv(gp); | |
1da177e4 LT |
1237 | } |
1238 | ||
1239 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1240 | static void gem_start_dma(struct gem *gp) | |
1241 | { | |
1242 | u32 val; | |
6aa20a22 | 1243 | |
1da177e4 LT |
1244 | /* We are ready to rock, turn everything on. */ |
1245 | val = readl(gp->regs + TXDMA_CFG); | |
1246 | writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); | |
1247 | val = readl(gp->regs + RXDMA_CFG); | |
1248 | writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); | |
1249 | val = readl(gp->regs + MAC_TXCFG); | |
1250 | writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); | |
1251 | val = readl(gp->regs + MAC_RXCFG); | |
1252 | writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); | |
1253 | ||
1254 | (void) readl(gp->regs + MAC_RXCFG); | |
1255 | udelay(100); | |
1256 | ||
1257 | gem_enable_ints(gp); | |
1258 | ||
1259 | writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); | |
1260 | } | |
1261 | ||
1262 | /* Must be invoked under gp->lock and gp->tx_lock. DMA won't be | |
1263 | * actually stopped before about 4ms tho ... | |
1264 | */ | |
1265 | static void gem_stop_dma(struct gem *gp) | |
1266 | { | |
1267 | u32 val; | |
1268 | ||
1269 | /* We are done rocking, turn everything off. */ | |
1270 | val = readl(gp->regs + TXDMA_CFG); | |
1271 | writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); | |
1272 | val = readl(gp->regs + RXDMA_CFG); | |
1273 | writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); | |
1274 | val = readl(gp->regs + MAC_TXCFG); | |
1275 | writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); | |
1276 | val = readl(gp->regs + MAC_RXCFG); | |
1277 | writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); | |
1278 | ||
1279 | (void) readl(gp->regs + MAC_RXCFG); | |
1280 | ||
1281 | /* Need to wait a bit ... done by the caller */ | |
1282 | } | |
1283 | ||
1284 | ||
1285 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1286 | // XXX dbl check what that function should do when called on PCS PHY | |
1287 | static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep) | |
1288 | { | |
1289 | u32 advertise, features; | |
1290 | int autoneg; | |
1291 | int speed; | |
1292 | int duplex; | |
1293 | ||
1294 | if (gp->phy_type != phy_mii_mdio0 && | |
1295 | gp->phy_type != phy_mii_mdio1) | |
1296 | goto non_mii; | |
1297 | ||
1298 | /* Setup advertise */ | |
1299 | if (found_mii_phy(gp)) | |
1300 | features = gp->phy_mii.def->features; | |
1301 | else | |
1302 | features = 0; | |
1303 | ||
1304 | advertise = features & ADVERTISE_MASK; | |
1305 | if (gp->phy_mii.advertising != 0) | |
1306 | advertise &= gp->phy_mii.advertising; | |
1307 | ||
1308 | autoneg = gp->want_autoneg; | |
1309 | speed = gp->phy_mii.speed; | |
1310 | duplex = gp->phy_mii.duplex; | |
6aa20a22 | 1311 | |
1da177e4 LT |
1312 | /* Setup link parameters */ |
1313 | if (!ep) | |
1314 | goto start_aneg; | |
1315 | if (ep->autoneg == AUTONEG_ENABLE) { | |
1316 | advertise = ep->advertising; | |
1317 | autoneg = 1; | |
1318 | } else { | |
1319 | autoneg = 0; | |
1320 | speed = ep->speed; | |
1321 | duplex = ep->duplex; | |
1322 | } | |
1323 | ||
1324 | start_aneg: | |
1325 | /* Sanitize settings based on PHY capabilities */ | |
1326 | if ((features & SUPPORTED_Autoneg) == 0) | |
1327 | autoneg = 0; | |
1328 | if (speed == SPEED_1000 && | |
1329 | !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full))) | |
1330 | speed = SPEED_100; | |
1331 | if (speed == SPEED_100 && | |
1332 | !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full))) | |
1333 | speed = SPEED_10; | |
1334 | if (duplex == DUPLEX_FULL && | |
1335 | !(features & (SUPPORTED_1000baseT_Full | | |
1336 | SUPPORTED_100baseT_Full | | |
1337 | SUPPORTED_10baseT_Full))) | |
1338 | duplex = DUPLEX_HALF; | |
1339 | if (speed == 0) | |
1340 | speed = SPEED_10; | |
6aa20a22 | 1341 | |
1da177e4 LT |
1342 | /* If we are asleep, we don't try to actually setup the PHY, we |
1343 | * just store the settings | |
1344 | */ | |
1345 | if (gp->asleep) { | |
1346 | gp->phy_mii.autoneg = gp->want_autoneg = autoneg; | |
1347 | gp->phy_mii.speed = speed; | |
1348 | gp->phy_mii.duplex = duplex; | |
1349 | return; | |
1350 | } | |
1351 | ||
1352 | /* Configure PHY & start aneg */ | |
1353 | gp->want_autoneg = autoneg; | |
1354 | if (autoneg) { | |
1355 | if (found_mii_phy(gp)) | |
1356 | gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise); | |
1357 | gp->lstate = link_aneg; | |
1358 | } else { | |
1359 | if (found_mii_phy(gp)) | |
1360 | gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex); | |
1361 | gp->lstate = link_force_ok; | |
1362 | } | |
1363 | ||
1364 | non_mii: | |
1365 | gp->timer_ticks = 0; | |
1366 | mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); | |
1367 | } | |
1368 | ||
1369 | /* A link-up condition has occurred, initialize and enable the | |
1370 | * rest of the chip. | |
1371 | * | |
1372 | * Must be invoked under gp->lock and gp->tx_lock. | |
1373 | */ | |
1374 | static int gem_set_link_modes(struct gem *gp) | |
1375 | { | |
1376 | u32 val; | |
1377 | int full_duplex, speed, pause; | |
1378 | ||
1379 | full_duplex = 0; | |
1380 | speed = SPEED_10; | |
1381 | pause = 0; | |
1382 | ||
1383 | if (found_mii_phy(gp)) { | |
1384 | if (gp->phy_mii.def->ops->read_link(&gp->phy_mii)) | |
1385 | return 1; | |
1386 | full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL); | |
1387 | speed = gp->phy_mii.speed; | |
1388 | pause = gp->phy_mii.pause; | |
1389 | } else if (gp->phy_type == phy_serialink || | |
1390 | gp->phy_type == phy_serdes) { | |
1391 | u32 pcs_lpa = readl(gp->regs + PCS_MIILP); | |
1392 | ||
8c83f80b | 1393 | if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes) |
1da177e4 LT |
1394 | full_duplex = 1; |
1395 | speed = SPEED_1000; | |
1396 | } | |
1397 | ||
1398 | if (netif_msg_link(gp)) | |
1399 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n", | |
1400 | gp->dev->name, speed, (full_duplex ? "full" : "half")); | |
1401 | ||
1402 | if (!gp->running) | |
1403 | return 0; | |
1404 | ||
1405 | val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU); | |
1406 | if (full_duplex) { | |
1407 | val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL); | |
1408 | } else { | |
1409 | /* MAC_TXCFG_NBO must be zero. */ | |
6aa20a22 | 1410 | } |
1da177e4 LT |
1411 | writel(val, gp->regs + MAC_TXCFG); |
1412 | ||
1413 | val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED); | |
1414 | if (!full_duplex && | |
1415 | (gp->phy_type == phy_mii_mdio0 || | |
1416 | gp->phy_type == phy_mii_mdio1)) { | |
1417 | val |= MAC_XIFCFG_DISE; | |
1418 | } else if (full_duplex) { | |
1419 | val |= MAC_XIFCFG_FLED; | |
1420 | } | |
1421 | ||
1422 | if (speed == SPEED_1000) | |
1423 | val |= (MAC_XIFCFG_GMII); | |
1424 | ||
1425 | writel(val, gp->regs + MAC_XIFCFG); | |
1426 | ||
1427 | /* If gigabit and half-duplex, enable carrier extension | |
1428 | * mode. Else, disable it. | |
1429 | */ | |
1430 | if (speed == SPEED_1000 && !full_duplex) { | |
1431 | val = readl(gp->regs + MAC_TXCFG); | |
1432 | writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); | |
1433 | ||
1434 | val = readl(gp->regs + MAC_RXCFG); | |
1435 | writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); | |
1436 | } else { | |
1437 | val = readl(gp->regs + MAC_TXCFG); | |
1438 | writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); | |
1439 | ||
1440 | val = readl(gp->regs + MAC_RXCFG); | |
1441 | writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); | |
1442 | } | |
1443 | ||
1444 | if (gp->phy_type == phy_serialink || | |
1445 | gp->phy_type == phy_serdes) { | |
1446 | u32 pcs_lpa = readl(gp->regs + PCS_MIILP); | |
1447 | ||
1448 | if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP)) | |
1449 | pause = 1; | |
1450 | } | |
1451 | ||
1452 | if (netif_msg_link(gp)) { | |
1453 | if (pause) { | |
1454 | printk(KERN_INFO "%s: Pause is enabled " | |
1455 | "(rxfifo: %d off: %d on: %d)\n", | |
1456 | gp->dev->name, | |
1457 | gp->rx_fifo_sz, | |
1458 | gp->rx_pause_off, | |
1459 | gp->rx_pause_on); | |
1460 | } else { | |
1461 | printk(KERN_INFO "%s: Pause is disabled\n", | |
1462 | gp->dev->name); | |
1463 | } | |
1464 | } | |
1465 | ||
1466 | if (!full_duplex) | |
1467 | writel(512, gp->regs + MAC_STIME); | |
1468 | else | |
1469 | writel(64, gp->regs + MAC_STIME); | |
1470 | val = readl(gp->regs + MAC_MCCFG); | |
1471 | if (pause) | |
1472 | val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE); | |
1473 | else | |
1474 | val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE); | |
1475 | writel(val, gp->regs + MAC_MCCFG); | |
1476 | ||
1477 | gem_start_dma(gp); | |
1478 | ||
1479 | return 0; | |
1480 | } | |
1481 | ||
1482 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1483 | static int gem_mdio_link_not_up(struct gem *gp) | |
1484 | { | |
1485 | switch (gp->lstate) { | |
1486 | case link_force_ret: | |
1487 | if (netif_msg_link(gp)) | |
1488 | printk(KERN_INFO "%s: Autoneg failed again, keeping" | |
1489 | " forced mode\n", gp->dev->name); | |
1490 | gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, | |
1491 | gp->last_forced_speed, DUPLEX_HALF); | |
1492 | gp->timer_ticks = 5; | |
1493 | gp->lstate = link_force_ok; | |
1494 | return 0; | |
1495 | case link_aneg: | |
1496 | /* We try forced modes after a failed aneg only on PHYs that don't | |
1497 | * have "magic_aneg" bit set, which means they internally do the | |
1498 | * while forced-mode thingy. On these, we just restart aneg | |
1499 | */ | |
1500 | if (gp->phy_mii.def->magic_aneg) | |
1501 | return 1; | |
1502 | if (netif_msg_link(gp)) | |
1503 | printk(KERN_INFO "%s: switching to forced 100bt\n", | |
1504 | gp->dev->name); | |
1505 | /* Try forced modes. */ | |
1506 | gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100, | |
1507 | DUPLEX_HALF); | |
1508 | gp->timer_ticks = 5; | |
1509 | gp->lstate = link_force_try; | |
1510 | return 0; | |
1511 | case link_force_try: | |
1512 | /* Downgrade from 100 to 10 Mbps if necessary. | |
1513 | * If already at 10Mbps, warn user about the | |
1514 | * situation every 10 ticks. | |
1515 | */ | |
1516 | if (gp->phy_mii.speed == SPEED_100) { | |
1517 | gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10, | |
1518 | DUPLEX_HALF); | |
1519 | gp->timer_ticks = 5; | |
1520 | if (netif_msg_link(gp)) | |
1521 | printk(KERN_INFO "%s: switching to forced 10bt\n", | |
1522 | gp->dev->name); | |
1523 | return 0; | |
1524 | } else | |
1525 | return 1; | |
1526 | default: | |
1527 | return 0; | |
1528 | } | |
1529 | } | |
1530 | ||
1531 | static void gem_link_timer(unsigned long data) | |
1532 | { | |
1533 | struct gem *gp = (struct gem *) data; | |
1534 | int restart_aneg = 0; | |
6aa20a22 | 1535 | |
1da177e4 LT |
1536 | if (gp->asleep) |
1537 | return; | |
1538 | ||
1539 | spin_lock_irq(&gp->lock); | |
1540 | spin_lock(&gp->tx_lock); | |
1541 | gem_get_cell(gp); | |
1542 | ||
1543 | /* If the reset task is still pending, we just | |
1544 | * reschedule the link timer | |
1545 | */ | |
1546 | if (gp->reset_task_pending) | |
1547 | goto restart; | |
6aa20a22 | 1548 | |
1da177e4 LT |
1549 | if (gp->phy_type == phy_serialink || |
1550 | gp->phy_type == phy_serdes) { | |
1551 | u32 val = readl(gp->regs + PCS_MIISTAT); | |
1552 | ||
1553 | if (!(val & PCS_MIISTAT_LS)) | |
1554 | val = readl(gp->regs + PCS_MIISTAT); | |
1555 | ||
1556 | if ((val & PCS_MIISTAT_LS) != 0) { | |
8c83f80b DM |
1557 | if (gp->lstate == link_up) |
1558 | goto restart; | |
1559 | ||
1da177e4 LT |
1560 | gp->lstate = link_up; |
1561 | netif_carrier_on(gp->dev); | |
1562 | (void)gem_set_link_modes(gp); | |
1563 | } | |
1564 | goto restart; | |
1565 | } | |
1566 | if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) { | |
1567 | /* Ok, here we got a link. If we had it due to a forced | |
1568 | * fallback, and we were configured for autoneg, we do | |
1569 | * retry a short autoneg pass. If you know your hub is | |
1570 | * broken, use ethtool ;) | |
1571 | */ | |
1572 | if (gp->lstate == link_force_try && gp->want_autoneg) { | |
1573 | gp->lstate = link_force_ret; | |
1574 | gp->last_forced_speed = gp->phy_mii.speed; | |
1575 | gp->timer_ticks = 5; | |
1576 | if (netif_msg_link(gp)) | |
1577 | printk(KERN_INFO "%s: Got link after fallback, retrying" | |
1578 | " autoneg once...\n", gp->dev->name); | |
1579 | gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising); | |
1580 | } else if (gp->lstate != link_up) { | |
1581 | gp->lstate = link_up; | |
1582 | netif_carrier_on(gp->dev); | |
1583 | if (gem_set_link_modes(gp)) | |
1584 | restart_aneg = 1; | |
1585 | } | |
1586 | } else { | |
1587 | /* If the link was previously up, we restart the | |
1588 | * whole process | |
1589 | */ | |
1590 | if (gp->lstate == link_up) { | |
1591 | gp->lstate = link_down; | |
1592 | if (netif_msg_link(gp)) | |
1593 | printk(KERN_INFO "%s: Link down\n", | |
1594 | gp->dev->name); | |
1595 | netif_carrier_off(gp->dev); | |
1596 | gp->reset_task_pending = 1; | |
1597 | schedule_work(&gp->reset_task); | |
1598 | restart_aneg = 1; | |
1599 | } else if (++gp->timer_ticks > 10) { | |
1600 | if (found_mii_phy(gp)) | |
1601 | restart_aneg = gem_mdio_link_not_up(gp); | |
1602 | else | |
1603 | restart_aneg = 1; | |
1604 | } | |
1605 | } | |
1606 | if (restart_aneg) { | |
1607 | gem_begin_auto_negotiation(gp, NULL); | |
1608 | goto out_unlock; | |
1609 | } | |
1610 | restart: | |
1611 | mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); | |
1612 | out_unlock: | |
1613 | gem_put_cell(gp); | |
1614 | spin_unlock(&gp->tx_lock); | |
1615 | spin_unlock_irq(&gp->lock); | |
1616 | } | |
1617 | ||
1618 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1619 | static void gem_clean_rings(struct gem *gp) | |
1620 | { | |
1621 | struct gem_init_block *gb = gp->init_block; | |
1622 | struct sk_buff *skb; | |
1623 | int i; | |
1624 | dma_addr_t dma_addr; | |
1625 | ||
1626 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1627 | struct gem_rxd *rxd; | |
1628 | ||
1629 | rxd = &gb->rxd[i]; | |
1630 | if (gp->rx_skbs[i] != NULL) { | |
1631 | skb = gp->rx_skbs[i]; | |
1632 | dma_addr = le64_to_cpu(rxd->buffer); | |
1633 | pci_unmap_page(gp->pdev, dma_addr, | |
1634 | RX_BUF_ALLOC_SIZE(gp), | |
1635 | PCI_DMA_FROMDEVICE); | |
1636 | dev_kfree_skb_any(skb); | |
1637 | gp->rx_skbs[i] = NULL; | |
1638 | } | |
1639 | rxd->status_word = 0; | |
1640 | wmb(); | |
1641 | rxd->buffer = 0; | |
1642 | } | |
1643 | ||
1644 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1645 | if (gp->tx_skbs[i] != NULL) { | |
1646 | struct gem_txd *txd; | |
1647 | int frag; | |
1648 | ||
1649 | skb = gp->tx_skbs[i]; | |
1650 | gp->tx_skbs[i] = NULL; | |
1651 | ||
1652 | for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { | |
1653 | int ent = i & (TX_RING_SIZE - 1); | |
1654 | ||
1655 | txd = &gb->txd[ent]; | |
1656 | dma_addr = le64_to_cpu(txd->buffer); | |
1657 | pci_unmap_page(gp->pdev, dma_addr, | |
1658 | le64_to_cpu(txd->control_word) & | |
1659 | TXDCTRL_BUFSZ, PCI_DMA_TODEVICE); | |
1660 | ||
1661 | if (frag != skb_shinfo(skb)->nr_frags) | |
1662 | i++; | |
1663 | } | |
1664 | dev_kfree_skb_any(skb); | |
1665 | } | |
1666 | } | |
1667 | } | |
1668 | ||
1669 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1670 | static void gem_init_rings(struct gem *gp) | |
1671 | { | |
1672 | struct gem_init_block *gb = gp->init_block; | |
1673 | struct net_device *dev = gp->dev; | |
1674 | int i; | |
1675 | dma_addr_t dma_addr; | |
1676 | ||
1677 | gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0; | |
1678 | ||
1679 | gem_clean_rings(gp); | |
1680 | ||
1681 | gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN, | |
1682 | (unsigned)VLAN_ETH_FRAME_LEN); | |
1683 | ||
1684 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1685 | struct sk_buff *skb; | |
1686 | struct gem_rxd *rxd = &gb->rxd[i]; | |
1687 | ||
1688 | skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC); | |
1689 | if (!skb) { | |
1690 | rxd->buffer = 0; | |
1691 | rxd->status_word = 0; | |
1692 | continue; | |
1693 | } | |
1694 | ||
1695 | gp->rx_skbs[i] = skb; | |
1696 | skb->dev = dev; | |
1697 | skb_put(skb, (gp->rx_buf_sz + RX_OFFSET)); | |
1698 | dma_addr = pci_map_page(gp->pdev, | |
1699 | virt_to_page(skb->data), | |
1700 | offset_in_page(skb->data), | |
1701 | RX_BUF_ALLOC_SIZE(gp), | |
1702 | PCI_DMA_FROMDEVICE); | |
1703 | rxd->buffer = cpu_to_le64(dma_addr); | |
1704 | wmb(); | |
1705 | rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); | |
1706 | skb_reserve(skb, RX_OFFSET); | |
1707 | } | |
1708 | ||
1709 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1710 | struct gem_txd *txd = &gb->txd[i]; | |
1711 | ||
1712 | txd->control_word = 0; | |
1713 | wmb(); | |
1714 | txd->buffer = 0; | |
1715 | } | |
1716 | wmb(); | |
1717 | } | |
1718 | ||
1719 | /* Init PHY interface and start link poll state machine */ | |
1720 | static void gem_init_phy(struct gem *gp) | |
1721 | { | |
7fb76aa0 | 1722 | u32 mifcfg; |
1da177e4 LT |
1723 | |
1724 | /* Revert MIF CFG setting done on stop_phy */ | |
7fb76aa0 DM |
1725 | mifcfg = readl(gp->regs + MIF_CFG); |
1726 | mifcfg &= ~MIF_CFG_BBMODE; | |
1727 | writel(mifcfg, gp->regs + MIF_CFG); | |
6aa20a22 | 1728 | |
1da177e4 LT |
1729 | if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) { |
1730 | int i; | |
1731 | ||
7fb76aa0 DM |
1732 | /* Those delay sucks, the HW seem to love them though, I'll |
1733 | * serisouly consider breaking some locks here to be able | |
1734 | * to schedule instead | |
1735 | */ | |
1736 | for (i = 0; i < 3; i++) { | |
1da177e4 | 1737 | #ifdef CONFIG_PPC_PMAC |
7fb76aa0 DM |
1738 | pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0); |
1739 | msleep(20); | |
1da177e4 | 1740 | #endif |
7fb76aa0 DM |
1741 | /* Some PHYs used by apple have problem getting back to us, |
1742 | * we do an additional reset here | |
1743 | */ | |
1744 | phy_write(gp, MII_BMCR, BMCR_RESET); | |
1745 | msleep(20); | |
1746 | if (phy_read(gp, MII_BMCR) != 0xffff) | |
1da177e4 | 1747 | break; |
7fb76aa0 DM |
1748 | if (i == 2) |
1749 | printk(KERN_WARNING "%s: GMAC PHY not responding !\n", | |
1750 | gp->dev->name); | |
1da177e4 LT |
1751 | } |
1752 | } | |
1753 | ||
1754 | if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && | |
1755 | gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { | |
1756 | u32 val; | |
1757 | ||
1758 | /* Init datapath mode register. */ | |
1759 | if (gp->phy_type == phy_mii_mdio0 || | |
1760 | gp->phy_type == phy_mii_mdio1) { | |
1761 | val = PCS_DMODE_MGM; | |
1762 | } else if (gp->phy_type == phy_serialink) { | |
1763 | val = PCS_DMODE_SM | PCS_DMODE_GMOE; | |
1764 | } else { | |
1765 | val = PCS_DMODE_ESM; | |
1766 | } | |
1767 | ||
1768 | writel(val, gp->regs + PCS_DMODE); | |
1769 | } | |
1770 | ||
1771 | if (gp->phy_type == phy_mii_mdio0 || | |
1772 | gp->phy_type == phy_mii_mdio1) { | |
1773 | // XXX check for errors | |
1774 | mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr); | |
1775 | ||
1776 | /* Init PHY */ | |
1777 | if (gp->phy_mii.def && gp->phy_mii.def->ops->init) | |
1778 | gp->phy_mii.def->ops->init(&gp->phy_mii); | |
1779 | } else { | |
8c83f80b DM |
1780 | gem_pcs_reset(gp); |
1781 | gem_pcs_reinit_adv(gp); | |
1da177e4 LT |
1782 | } |
1783 | ||
1784 | /* Default aneg parameters */ | |
1785 | gp->timer_ticks = 0; | |
1786 | gp->lstate = link_down; | |
1787 | netif_carrier_off(gp->dev); | |
1788 | ||
1789 | /* Can I advertise gigabit here ? I'd need BCM PHY docs... */ | |
1790 | spin_lock_irq(&gp->lock); | |
1791 | gem_begin_auto_negotiation(gp, NULL); | |
1792 | spin_unlock_irq(&gp->lock); | |
1793 | } | |
1794 | ||
1795 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1796 | static void gem_init_dma(struct gem *gp) | |
1797 | { | |
1798 | u64 desc_dma = (u64) gp->gblock_dvma; | |
1799 | u32 val; | |
1800 | ||
1801 | val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE); | |
1802 | writel(val, gp->regs + TXDMA_CFG); | |
1803 | ||
1804 | writel(desc_dma >> 32, gp->regs + TXDMA_DBHI); | |
1805 | writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW); | |
1806 | desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd)); | |
1807 | ||
1808 | writel(0, gp->regs + TXDMA_KICK); | |
1809 | ||
1810 | val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) | | |
1811 | ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128); | |
1812 | writel(val, gp->regs + RXDMA_CFG); | |
1813 | ||
1814 | writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); | |
1815 | writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); | |
1816 | ||
1817 | writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); | |
1818 | ||
1819 | val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); | |
1820 | val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); | |
1821 | writel(val, gp->regs + RXDMA_PTHRESH); | |
1822 | ||
1823 | if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) | |
1824 | writel(((5 & RXDMA_BLANK_IPKTS) | | |
1825 | ((8 << 12) & RXDMA_BLANK_ITIME)), | |
1826 | gp->regs + RXDMA_BLANK); | |
1827 | else | |
1828 | writel(((5 & RXDMA_BLANK_IPKTS) | | |
1829 | ((4 << 12) & RXDMA_BLANK_ITIME)), | |
1830 | gp->regs + RXDMA_BLANK); | |
1831 | } | |
1832 | ||
1833 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1834 | static u32 gem_setup_multicast(struct gem *gp) | |
1835 | { | |
1836 | u32 rxcfg = 0; | |
1837 | int i; | |
6aa20a22 | 1838 | |
1da177e4 LT |
1839 | if ((gp->dev->flags & IFF_ALLMULTI) || |
1840 | (gp->dev->mc_count > 256)) { | |
1841 | for (i=0; i<16; i++) | |
1842 | writel(0xffff, gp->regs + MAC_HASH0 + (i << 2)); | |
1843 | rxcfg |= MAC_RXCFG_HFE; | |
1844 | } else if (gp->dev->flags & IFF_PROMISC) { | |
1845 | rxcfg |= MAC_RXCFG_PROM; | |
1846 | } else { | |
1847 | u16 hash_table[16]; | |
1848 | u32 crc; | |
1849 | struct dev_mc_list *dmi = gp->dev->mc_list; | |
1850 | int i; | |
1851 | ||
1852 | for (i = 0; i < 16; i++) | |
1853 | hash_table[i] = 0; | |
1854 | ||
1855 | for (i = 0; i < gp->dev->mc_count; i++) { | |
1856 | char *addrs = dmi->dmi_addr; | |
1857 | ||
1858 | dmi = dmi->next; | |
1859 | ||
1860 | if (!(*addrs & 1)) | |
1861 | continue; | |
1862 | ||
1863 | crc = ether_crc_le(6, addrs); | |
1864 | crc >>= 24; | |
1865 | hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); | |
1866 | } | |
1867 | for (i=0; i<16; i++) | |
1868 | writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2)); | |
1869 | rxcfg |= MAC_RXCFG_HFE; | |
1870 | } | |
1871 | ||
1872 | return rxcfg; | |
1873 | } | |
1874 | ||
1875 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1876 | static void gem_init_mac(struct gem *gp) | |
1877 | { | |
1878 | unsigned char *e = &gp->dev->dev_addr[0]; | |
1879 | ||
1880 | writel(0x1bf0, gp->regs + MAC_SNDPAUSE); | |
1881 | ||
1882 | writel(0x00, gp->regs + MAC_IPG0); | |
1883 | writel(0x08, gp->regs + MAC_IPG1); | |
1884 | writel(0x04, gp->regs + MAC_IPG2); | |
1885 | writel(0x40, gp->regs + MAC_STIME); | |
1886 | writel(0x40, gp->regs + MAC_MINFSZ); | |
1887 | ||
1888 | /* Ethernet payload + header + FCS + optional VLAN tag. */ | |
1889 | writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ); | |
1890 | ||
1891 | writel(0x07, gp->regs + MAC_PASIZE); | |
1892 | writel(0x04, gp->regs + MAC_JAMSIZE); | |
1893 | writel(0x10, gp->regs + MAC_ATTLIM); | |
1894 | writel(0x8808, gp->regs + MAC_MCTYPE); | |
1895 | ||
1896 | writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED); | |
1897 | ||
1898 | writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); | |
1899 | writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); | |
1900 | writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); | |
1901 | ||
1902 | writel(0, gp->regs + MAC_ADDR3); | |
1903 | writel(0, gp->regs + MAC_ADDR4); | |
1904 | writel(0, gp->regs + MAC_ADDR5); | |
1905 | ||
1906 | writel(0x0001, gp->regs + MAC_ADDR6); | |
1907 | writel(0xc200, gp->regs + MAC_ADDR7); | |
1908 | writel(0x0180, gp->regs + MAC_ADDR8); | |
1909 | ||
1910 | writel(0, gp->regs + MAC_AFILT0); | |
1911 | writel(0, gp->regs + MAC_AFILT1); | |
1912 | writel(0, gp->regs + MAC_AFILT2); | |
1913 | writel(0, gp->regs + MAC_AF21MSK); | |
1914 | writel(0, gp->regs + MAC_AF0MSK); | |
1915 | ||
1916 | gp->mac_rx_cfg = gem_setup_multicast(gp); | |
1917 | #ifdef STRIP_FCS | |
1918 | gp->mac_rx_cfg |= MAC_RXCFG_SFCS; | |
1919 | #endif | |
1920 | writel(0, gp->regs + MAC_NCOLL); | |
1921 | writel(0, gp->regs + MAC_FASUCC); | |
1922 | writel(0, gp->regs + MAC_ECOLL); | |
1923 | writel(0, gp->regs + MAC_LCOLL); | |
1924 | writel(0, gp->regs + MAC_DTIMER); | |
1925 | writel(0, gp->regs + MAC_PATMPS); | |
1926 | writel(0, gp->regs + MAC_RFCTR); | |
1927 | writel(0, gp->regs + MAC_LERR); | |
1928 | writel(0, gp->regs + MAC_AERR); | |
1929 | writel(0, gp->regs + MAC_FCSERR); | |
1930 | writel(0, gp->regs + MAC_RXCVERR); | |
1931 | ||
1932 | /* Clear RX/TX/MAC/XIF config, we will set these up and enable | |
1933 | * them once a link is established. | |
1934 | */ | |
1935 | writel(0, gp->regs + MAC_TXCFG); | |
1936 | writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG); | |
1937 | writel(0, gp->regs + MAC_MCCFG); | |
1938 | writel(0, gp->regs + MAC_XIFCFG); | |
1939 | ||
1940 | /* Setup MAC interrupts. We want to get all of the interesting | |
1941 | * counter expiration events, but we do not want to hear about | |
1942 | * normal rx/tx as the DMA engine tells us that. | |
1943 | */ | |
1944 | writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK); | |
1945 | writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); | |
1946 | ||
1947 | /* Don't enable even the PAUSE interrupts for now, we | |
1948 | * make no use of those events other than to record them. | |
1949 | */ | |
1950 | writel(0xffffffff, gp->regs + MAC_MCMASK); | |
1951 | ||
1952 | /* Don't enable GEM's WOL in normal operations | |
1953 | */ | |
1954 | if (gp->has_wol) | |
1955 | writel(0, gp->regs + WOL_WAKECSR); | |
1956 | } | |
1957 | ||
1958 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
1959 | static void gem_init_pause_thresholds(struct gem *gp) | |
1960 | { | |
1961 | u32 cfg; | |
1962 | ||
1963 | /* Calculate pause thresholds. Setting the OFF threshold to the | |
1964 | * full RX fifo size effectively disables PAUSE generation which | |
1965 | * is what we do for 10/100 only GEMs which have FIFOs too small | |
1966 | * to make real gains from PAUSE. | |
1967 | */ | |
1968 | if (gp->rx_fifo_sz <= (2 * 1024)) { | |
1969 | gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz; | |
1970 | } else { | |
1971 | int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63; | |
1972 | int off = (gp->rx_fifo_sz - (max_frame * 2)); | |
1973 | int on = off - max_frame; | |
1974 | ||
1975 | gp->rx_pause_off = off; | |
1976 | gp->rx_pause_on = on; | |
1977 | } | |
1978 | ||
1979 | ||
1980 | /* Configure the chip "burst" DMA mode & enable some | |
1981 | * HW bug fixes on Apple version | |
1982 | */ | |
1983 | cfg = 0; | |
1984 | if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) | |
1985 | cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX; | |
1986 | #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA) | |
1987 | cfg |= GREG_CFG_IBURST; | |
1988 | #endif | |
1989 | cfg |= ((31 << 1) & GREG_CFG_TXDMALIM); | |
1990 | cfg |= ((31 << 6) & GREG_CFG_RXDMALIM); | |
1991 | writel(cfg, gp->regs + GREG_CFG); | |
1992 | ||
1993 | /* If Infinite Burst didn't stick, then use different | |
1994 | * thresholds (and Apple bug fixes don't exist) | |
1995 | */ | |
1996 | if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) { | |
1997 | cfg = ((2 << 1) & GREG_CFG_TXDMALIM); | |
1998 | cfg |= ((8 << 6) & GREG_CFG_RXDMALIM); | |
1999 | writel(cfg, gp->regs + GREG_CFG); | |
6aa20a22 | 2000 | } |
1da177e4 LT |
2001 | } |
2002 | ||
2003 | static int gem_check_invariants(struct gem *gp) | |
2004 | { | |
2005 | struct pci_dev *pdev = gp->pdev; | |
2006 | u32 mif_cfg; | |
2007 | ||
2008 | /* On Apple's sungem, we can't rely on registers as the chip | |
2009 | * was been powered down by the firmware. The PHY is looked | |
2010 | * up later on. | |
2011 | */ | |
2012 | if (pdev->vendor == PCI_VENDOR_ID_APPLE) { | |
2013 | gp->phy_type = phy_mii_mdio0; | |
2014 | gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; | |
2015 | gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; | |
2016 | gp->swrst_base = 0; | |
2017 | ||
2018 | mif_cfg = readl(gp->regs + MIF_CFG); | |
2019 | mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1); | |
2020 | mif_cfg |= MIF_CFG_MDI0; | |
2021 | writel(mif_cfg, gp->regs + MIF_CFG); | |
2022 | writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE); | |
2023 | writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG); | |
2024 | ||
2025 | /* We hard-code the PHY address so we can properly bring it out of | |
2026 | * reset later on, we can't really probe it at this point, though | |
2027 | * that isn't an issue. | |
2028 | */ | |
2029 | if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC) | |
2030 | gp->mii_phy_addr = 1; | |
2031 | else | |
2032 | gp->mii_phy_addr = 0; | |
2033 | ||
2034 | return 0; | |
2035 | } | |
2036 | ||
2037 | mif_cfg = readl(gp->regs + MIF_CFG); | |
2038 | ||
2039 | if (pdev->vendor == PCI_VENDOR_ID_SUN && | |
2040 | pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) { | |
2041 | /* One of the MII PHYs _must_ be present | |
2042 | * as this chip has no gigabit PHY. | |
2043 | */ | |
2044 | if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) { | |
2045 | printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n", | |
2046 | mif_cfg); | |
2047 | return -1; | |
2048 | } | |
2049 | } | |
2050 | ||
2051 | /* Determine initial PHY interface type guess. MDIO1 is the | |
2052 | * external PHY and thus takes precedence over MDIO0. | |
2053 | */ | |
6aa20a22 | 2054 | |
1da177e4 LT |
2055 | if (mif_cfg & MIF_CFG_MDI1) { |
2056 | gp->phy_type = phy_mii_mdio1; | |
2057 | mif_cfg |= MIF_CFG_PSELECT; | |
2058 | writel(mif_cfg, gp->regs + MIF_CFG); | |
2059 | } else if (mif_cfg & MIF_CFG_MDI0) { | |
2060 | gp->phy_type = phy_mii_mdio0; | |
2061 | mif_cfg &= ~MIF_CFG_PSELECT; | |
2062 | writel(mif_cfg, gp->regs + MIF_CFG); | |
2063 | } else { | |
2064 | gp->phy_type = phy_serialink; | |
2065 | } | |
2066 | if (gp->phy_type == phy_mii_mdio1 || | |
2067 | gp->phy_type == phy_mii_mdio0) { | |
2068 | int i; | |
2069 | ||
2070 | for (i = 0; i < 32; i++) { | |
2071 | gp->mii_phy_addr = i; | |
2072 | if (phy_read(gp, MII_BMCR) != 0xffff) | |
2073 | break; | |
2074 | } | |
2075 | if (i == 32) { | |
2076 | if (pdev->device != PCI_DEVICE_ID_SUN_GEM) { | |
2077 | printk(KERN_ERR PFX "RIO MII phy will not respond.\n"); | |
2078 | return -1; | |
2079 | } | |
2080 | gp->phy_type = phy_serdes; | |
2081 | } | |
2082 | } | |
2083 | ||
2084 | /* Fetch the FIFO configurations now too. */ | |
2085 | gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; | |
2086 | gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; | |
2087 | ||
2088 | if (pdev->vendor == PCI_VENDOR_ID_SUN) { | |
2089 | if (pdev->device == PCI_DEVICE_ID_SUN_GEM) { | |
2090 | if (gp->tx_fifo_sz != (9 * 1024) || | |
2091 | gp->rx_fifo_sz != (20 * 1024)) { | |
2092 | printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n", | |
2093 | gp->tx_fifo_sz, gp->rx_fifo_sz); | |
2094 | return -1; | |
2095 | } | |
2096 | gp->swrst_base = 0; | |
2097 | } else { | |
2098 | if (gp->tx_fifo_sz != (2 * 1024) || | |
2099 | gp->rx_fifo_sz != (2 * 1024)) { | |
2100 | printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n", | |
2101 | gp->tx_fifo_sz, gp->rx_fifo_sz); | |
2102 | return -1; | |
2103 | } | |
2104 | gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT; | |
2105 | } | |
2106 | } | |
2107 | ||
2108 | return 0; | |
2109 | } | |
2110 | ||
2111 | /* Must be invoked under gp->lock and gp->tx_lock. */ | |
2112 | static void gem_reinit_chip(struct gem *gp) | |
2113 | { | |
2114 | /* Reset the chip */ | |
2115 | gem_reset(gp); | |
2116 | ||
2117 | /* Make sure ints are disabled */ | |
2118 | gem_disable_ints(gp); | |
2119 | ||
2120 | /* Allocate & setup ring buffers */ | |
2121 | gem_init_rings(gp); | |
2122 | ||
2123 | /* Configure pause thresholds */ | |
2124 | gem_init_pause_thresholds(gp); | |
2125 | ||
2126 | /* Init DMA & MAC engines */ | |
2127 | gem_init_dma(gp); | |
2128 | gem_init_mac(gp); | |
2129 | } | |
2130 | ||
2131 | ||
2132 | /* Must be invoked with no lock held. */ | |
2133 | static void gem_stop_phy(struct gem *gp, int wol) | |
2134 | { | |
7fb76aa0 | 2135 | u32 mifcfg; |
1da177e4 LT |
2136 | unsigned long flags; |
2137 | ||
2138 | /* Let the chip settle down a bit, it seems that helps | |
2139 | * for sleep mode on some models | |
2140 | */ | |
2141 | msleep(10); | |
2142 | ||
2143 | /* Make sure we aren't polling PHY status change. We | |
2144 | * don't currently use that feature though | |
2145 | */ | |
7fb76aa0 DM |
2146 | mifcfg = readl(gp->regs + MIF_CFG); |
2147 | mifcfg &= ~MIF_CFG_POLL; | |
2148 | writel(mifcfg, gp->regs + MIF_CFG); | |
1da177e4 LT |
2149 | |
2150 | if (wol && gp->has_wol) { | |
2151 | unsigned char *e = &gp->dev->dev_addr[0]; | |
2152 | u32 csr; | |
2153 | ||
2154 | /* Setup wake-on-lan for MAGIC packet */ | |
2155 | writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB, | |
6aa20a22 | 2156 | gp->regs + MAC_RXCFG); |
1da177e4 LT |
2157 | writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0); |
2158 | writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1); | |
2159 | writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2); | |
2160 | ||
2161 | writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT); | |
2162 | csr = WOL_WAKECSR_ENABLE; | |
2163 | if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0) | |
2164 | csr |= WOL_WAKECSR_MII; | |
2165 | writel(csr, gp->regs + WOL_WAKECSR); | |
2166 | } else { | |
2167 | writel(0, gp->regs + MAC_RXCFG); | |
2168 | (void)readl(gp->regs + MAC_RXCFG); | |
2169 | /* Machine sleep will die in strange ways if we | |
2170 | * dont wait a bit here, looks like the chip takes | |
2171 | * some time to really shut down | |
2172 | */ | |
2173 | msleep(10); | |
2174 | } | |
2175 | ||
2176 | writel(0, gp->regs + MAC_TXCFG); | |
2177 | writel(0, gp->regs + MAC_XIFCFG); | |
2178 | writel(0, gp->regs + TXDMA_CFG); | |
2179 | writel(0, gp->regs + RXDMA_CFG); | |
2180 | ||
2181 | if (!wol) { | |
2182 | spin_lock_irqsave(&gp->lock, flags); | |
2183 | spin_lock(&gp->tx_lock); | |
2184 | gem_reset(gp); | |
2185 | writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST); | |
2186 | writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); | |
2187 | spin_unlock(&gp->tx_lock); | |
2188 | spin_unlock_irqrestore(&gp->lock, flags); | |
2189 | ||
2190 | /* No need to take the lock here */ | |
2191 | ||
2192 | if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend) | |
2193 | gp->phy_mii.def->ops->suspend(&gp->phy_mii); | |
2194 | ||
2195 | /* According to Apple, we must set the MDIO pins to this begnign | |
2196 | * state or we may 1) eat more current, 2) damage some PHYs | |
2197 | */ | |
7fb76aa0 | 2198 | writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG); |
1da177e4 LT |
2199 | writel(0, gp->regs + MIF_BBCLK); |
2200 | writel(0, gp->regs + MIF_BBDATA); | |
2201 | writel(0, gp->regs + MIF_BBOENAB); | |
2202 | writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG); | |
2203 | (void) readl(gp->regs + MAC_XIFCFG); | |
2204 | } | |
2205 | } | |
2206 | ||
2207 | ||
2208 | static int gem_do_start(struct net_device *dev) | |
2209 | { | |
8f15ea42 | 2210 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2211 | unsigned long flags; |
2212 | ||
2213 | spin_lock_irqsave(&gp->lock, flags); | |
2214 | spin_lock(&gp->tx_lock); | |
2215 | ||
2216 | /* Enable the cell */ | |
2217 | gem_get_cell(gp); | |
2218 | ||
2219 | /* Init & setup chip hardware */ | |
2220 | gem_reinit_chip(gp); | |
2221 | ||
2222 | gp->running = 1; | |
2223 | ||
71822faa IV |
2224 | napi_enable(&gp->napi); |
2225 | ||
1da177e4 LT |
2226 | if (gp->lstate == link_up) { |
2227 | netif_carrier_on(gp->dev); | |
2228 | gem_set_link_modes(gp); | |
2229 | } | |
2230 | ||
2231 | netif_wake_queue(gp->dev); | |
2232 | ||
2233 | spin_unlock(&gp->tx_lock); | |
2234 | spin_unlock_irqrestore(&gp->lock, flags); | |
2235 | ||
2236 | if (request_irq(gp->pdev->irq, gem_interrupt, | |
1fb9df5d | 2237 | IRQF_SHARED, dev->name, (void *)dev)) { |
1da177e4 LT |
2238 | printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name); |
2239 | ||
2240 | spin_lock_irqsave(&gp->lock, flags); | |
2241 | spin_lock(&gp->tx_lock); | |
2242 | ||
71822faa IV |
2243 | napi_disable(&gp->napi); |
2244 | ||
1da177e4 LT |
2245 | gp->running = 0; |
2246 | gem_reset(gp); | |
2247 | gem_clean_rings(gp); | |
2248 | gem_put_cell(gp); | |
6aa20a22 | 2249 | |
1da177e4 LT |
2250 | spin_unlock(&gp->tx_lock); |
2251 | spin_unlock_irqrestore(&gp->lock, flags); | |
2252 | ||
2253 | return -EAGAIN; | |
2254 | } | |
2255 | ||
2256 | return 0; | |
2257 | } | |
2258 | ||
2259 | static void gem_do_stop(struct net_device *dev, int wol) | |
2260 | { | |
8f15ea42 | 2261 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2262 | unsigned long flags; |
2263 | ||
2264 | spin_lock_irqsave(&gp->lock, flags); | |
2265 | spin_lock(&gp->tx_lock); | |
2266 | ||
2267 | gp->running = 0; | |
2268 | ||
2269 | /* Stop netif queue */ | |
2270 | netif_stop_queue(dev); | |
2271 | ||
2272 | /* Make sure ints are disabled */ | |
2273 | gem_disable_ints(gp); | |
2274 | ||
2275 | /* We can drop the lock now */ | |
2276 | spin_unlock(&gp->tx_lock); | |
2277 | spin_unlock_irqrestore(&gp->lock, flags); | |
2278 | ||
2279 | /* If we are going to sleep with WOL */ | |
2280 | gem_stop_dma(gp); | |
2281 | msleep(10); | |
2282 | if (!wol) | |
2283 | gem_reset(gp); | |
2284 | msleep(10); | |
2285 | ||
2286 | /* Get rid of rings */ | |
2287 | gem_clean_rings(gp); | |
2288 | ||
2289 | /* No irq needed anymore */ | |
2290 | free_irq(gp->pdev->irq, (void *) dev); | |
2291 | ||
2292 | /* Cell not needed neither if no WOL */ | |
2293 | if (!wol) { | |
2294 | spin_lock_irqsave(&gp->lock, flags); | |
2295 | gem_put_cell(gp); | |
2296 | spin_unlock_irqrestore(&gp->lock, flags); | |
2297 | } | |
2298 | } | |
2299 | ||
c4028958 | 2300 | static void gem_reset_task(struct work_struct *work) |
1da177e4 | 2301 | { |
c4028958 | 2302 | struct gem *gp = container_of(work, struct gem, reset_task); |
1da177e4 | 2303 | |
e3968fc0 | 2304 | mutex_lock(&gp->pm_mutex); |
1da177e4 | 2305 | |
dde655c9 JB |
2306 | if (gp->opened) |
2307 | napi_disable(&gp->napi); | |
1da177e4 LT |
2308 | |
2309 | spin_lock_irq(&gp->lock); | |
2310 | spin_lock(&gp->tx_lock); | |
2311 | ||
1da177e4 LT |
2312 | if (gp->running) { |
2313 | netif_stop_queue(gp->dev); | |
2314 | ||
2315 | /* Reset the chip & rings */ | |
2316 | gem_reinit_chip(gp); | |
2317 | if (gp->lstate == link_up) | |
2318 | gem_set_link_modes(gp); | |
2319 | netif_wake_queue(gp->dev); | |
2320 | } | |
dde655c9 | 2321 | |
1da177e4 LT |
2322 | gp->reset_task_pending = 0; |
2323 | ||
2324 | spin_unlock(&gp->tx_lock); | |
2325 | spin_unlock_irq(&gp->lock); | |
2326 | ||
dde655c9 JB |
2327 | if (gp->opened) |
2328 | napi_enable(&gp->napi); | |
1da177e4 | 2329 | |
e3968fc0 | 2330 | mutex_unlock(&gp->pm_mutex); |
1da177e4 LT |
2331 | } |
2332 | ||
2333 | ||
2334 | static int gem_open(struct net_device *dev) | |
2335 | { | |
8f15ea42 | 2336 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2337 | int rc = 0; |
2338 | ||
e3968fc0 | 2339 | mutex_lock(&gp->pm_mutex); |
1da177e4 LT |
2340 | |
2341 | /* We need the cell enabled */ | |
2342 | if (!gp->asleep) | |
2343 | rc = gem_do_start(dev); | |
2344 | gp->opened = (rc == 0); | |
2345 | ||
e3968fc0 | 2346 | mutex_unlock(&gp->pm_mutex); |
1da177e4 LT |
2347 | |
2348 | return rc; | |
2349 | } | |
2350 | ||
2351 | static int gem_close(struct net_device *dev) | |
2352 | { | |
8f15ea42 | 2353 | struct gem *gp = netdev_priv(dev); |
1da177e4 | 2354 | |
e3968fc0 | 2355 | mutex_lock(&gp->pm_mutex); |
1da177e4 | 2356 | |
62768e28 JB |
2357 | napi_disable(&gp->napi); |
2358 | ||
6aa20a22 | 2359 | gp->opened = 0; |
1da177e4 LT |
2360 | if (!gp->asleep) |
2361 | gem_do_stop(dev, 0); | |
2362 | ||
e3968fc0 | 2363 | mutex_unlock(&gp->pm_mutex); |
6aa20a22 | 2364 | |
1da177e4 LT |
2365 | return 0; |
2366 | } | |
2367 | ||
2368 | #ifdef CONFIG_PM | |
2369 | static int gem_suspend(struct pci_dev *pdev, pm_message_t state) | |
2370 | { | |
2371 | struct net_device *dev = pci_get_drvdata(pdev); | |
8f15ea42 | 2372 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2373 | unsigned long flags; |
2374 | ||
e3968fc0 | 2375 | mutex_lock(&gp->pm_mutex); |
1da177e4 | 2376 | |
1da177e4 LT |
2377 | printk(KERN_INFO "%s: suspending, WakeOnLan %s\n", |
2378 | dev->name, | |
2379 | (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled"); | |
6aa20a22 | 2380 | |
1da177e4 LT |
2381 | /* Keep the cell enabled during the entire operation */ |
2382 | spin_lock_irqsave(&gp->lock, flags); | |
2383 | spin_lock(&gp->tx_lock); | |
2384 | gem_get_cell(gp); | |
2385 | spin_unlock(&gp->tx_lock); | |
2386 | spin_unlock_irqrestore(&gp->lock, flags); | |
2387 | ||
2388 | /* If the driver is opened, we stop the MAC */ | |
2389 | if (gp->opened) { | |
62768e28 JB |
2390 | napi_disable(&gp->napi); |
2391 | ||
1da177e4 LT |
2392 | /* Stop traffic, mark us closed */ |
2393 | netif_device_detach(dev); | |
2394 | ||
2395 | /* Switch off MAC, remember WOL setting */ | |
2396 | gp->asleep_wol = gp->wake_on_lan; | |
2397 | gem_do_stop(dev, gp->asleep_wol); | |
2398 | } else | |
2399 | gp->asleep_wol = 0; | |
2400 | ||
2401 | /* Mark us asleep */ | |
2402 | gp->asleep = 1; | |
2403 | wmb(); | |
2404 | ||
2405 | /* Stop the link timer */ | |
2406 | del_timer_sync(&gp->link_timer); | |
2407 | ||
e3968fc0 | 2408 | /* Now we release the mutex to not block the reset task who |
1da177e4 LT |
2409 | * can take it too. We are marked asleep, so there will be no |
2410 | * conflict here | |
2411 | */ | |
e3968fc0 | 2412 | mutex_unlock(&gp->pm_mutex); |
1da177e4 LT |
2413 | |
2414 | /* Wait for a pending reset task to complete */ | |
2415 | while (gp->reset_task_pending) | |
2416 | yield(); | |
2417 | flush_scheduled_work(); | |
2418 | ||
2419 | /* Shut the PHY down eventually and setup WOL */ | |
2420 | gem_stop_phy(gp, gp->asleep_wol); | |
2421 | ||
2422 | /* Make sure bus master is disabled */ | |
2423 | pci_disable_device(gp->pdev); | |
2424 | ||
2425 | /* Release the cell, no need to take a lock at this point since | |
2426 | * nothing else can happen now | |
2427 | */ | |
2428 | gem_put_cell(gp); | |
2429 | ||
2430 | return 0; | |
2431 | } | |
2432 | ||
2433 | static int gem_resume(struct pci_dev *pdev) | |
2434 | { | |
2435 | struct net_device *dev = pci_get_drvdata(pdev); | |
8f15ea42 | 2436 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2437 | unsigned long flags; |
2438 | ||
2439 | printk(KERN_INFO "%s: resuming\n", dev->name); | |
2440 | ||
e3968fc0 | 2441 | mutex_lock(&gp->pm_mutex); |
1da177e4 LT |
2442 | |
2443 | /* Keep the cell enabled during the entire operation, no need to | |
2444 | * take a lock here tho since nothing else can happen while we are | |
2445 | * marked asleep | |
2446 | */ | |
2447 | gem_get_cell(gp); | |
2448 | ||
2449 | /* Make sure PCI access and bus master are enabled */ | |
2450 | if (pci_enable_device(gp->pdev)) { | |
2451 | printk(KERN_ERR "%s: Can't re-enable chip !\n", | |
2452 | dev->name); | |
2453 | /* Put cell and forget it for now, it will be considered as | |
2454 | * still asleep, a new sleep cycle may bring it back | |
2455 | */ | |
2456 | gem_put_cell(gp); | |
e3968fc0 | 2457 | mutex_unlock(&gp->pm_mutex); |
1da177e4 LT |
2458 | return 0; |
2459 | } | |
2460 | pci_set_master(gp->pdev); | |
2461 | ||
2462 | /* Reset everything */ | |
2463 | gem_reset(gp); | |
2464 | ||
2465 | /* Mark us woken up */ | |
2466 | gp->asleep = 0; | |
2467 | wmb(); | |
2468 | ||
2469 | /* Bring the PHY back. Again, lock is useless at this point as | |
2470 | * nothing can be happening until we restart the whole thing | |
2471 | */ | |
2472 | gem_init_phy(gp); | |
2473 | ||
2474 | /* If we were opened, bring everything back */ | |
2475 | if (gp->opened) { | |
2476 | /* Restart MAC */ | |
2477 | gem_do_start(dev); | |
2478 | ||
2479 | /* Re-attach net device */ | |
2480 | netif_device_attach(dev); | |
1da177e4 LT |
2481 | } |
2482 | ||
2483 | spin_lock_irqsave(&gp->lock, flags); | |
2484 | spin_lock(&gp->tx_lock); | |
2485 | ||
2486 | /* If we had WOL enabled, the cell clock was never turned off during | |
2487 | * sleep, so we end up beeing unbalanced. Fix that here | |
2488 | */ | |
2489 | if (gp->asleep_wol) | |
2490 | gem_put_cell(gp); | |
2491 | ||
2492 | /* This function doesn't need to hold the cell, it will be held if the | |
2493 | * driver is open by gem_do_start(). | |
2494 | */ | |
2495 | gem_put_cell(gp); | |
2496 | ||
2497 | spin_unlock(&gp->tx_lock); | |
2498 | spin_unlock_irqrestore(&gp->lock, flags); | |
2499 | ||
e3968fc0 | 2500 | mutex_unlock(&gp->pm_mutex); |
1da177e4 LT |
2501 | |
2502 | return 0; | |
2503 | } | |
2504 | #endif /* CONFIG_PM */ | |
2505 | ||
2506 | static struct net_device_stats *gem_get_stats(struct net_device *dev) | |
2507 | { | |
8f15ea42 | 2508 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2509 | struct net_device_stats *stats = &gp->net_stats; |
2510 | ||
2511 | spin_lock_irq(&gp->lock); | |
2512 | spin_lock(&gp->tx_lock); | |
2513 | ||
2514 | /* I have seen this being called while the PM was in progress, | |
2515 | * so we shield against this | |
2516 | */ | |
2517 | if (gp->running) { | |
2518 | stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR); | |
2519 | writel(0, gp->regs + MAC_FCSERR); | |
2520 | ||
2521 | stats->rx_frame_errors += readl(gp->regs + MAC_AERR); | |
2522 | writel(0, gp->regs + MAC_AERR); | |
2523 | ||
2524 | stats->rx_length_errors += readl(gp->regs + MAC_LERR); | |
2525 | writel(0, gp->regs + MAC_LERR); | |
2526 | ||
2527 | stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL); | |
2528 | stats->collisions += | |
2529 | (readl(gp->regs + MAC_ECOLL) + | |
2530 | readl(gp->regs + MAC_LCOLL)); | |
2531 | writel(0, gp->regs + MAC_ECOLL); | |
2532 | writel(0, gp->regs + MAC_LCOLL); | |
2533 | } | |
2534 | ||
2535 | spin_unlock(&gp->tx_lock); | |
2536 | spin_unlock_irq(&gp->lock); | |
2537 | ||
2538 | return &gp->net_stats; | |
2539 | } | |
2540 | ||
09c72ec8 RV |
2541 | static int gem_set_mac_address(struct net_device *dev, void *addr) |
2542 | { | |
2543 | struct sockaddr *macaddr = (struct sockaddr *) addr; | |
8f15ea42 | 2544 | struct gem *gp = netdev_priv(dev); |
09c72ec8 RV |
2545 | unsigned char *e = &dev->dev_addr[0]; |
2546 | ||
2547 | if (!is_valid_ether_addr(macaddr->sa_data)) | |
2548 | return -EADDRNOTAVAIL; | |
2549 | ||
2550 | if (!netif_running(dev) || !netif_device_present(dev)) { | |
2551 | /* We'll just catch it later when the | |
2552 | * device is up'd or resumed. | |
2553 | */ | |
2554 | memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len); | |
2555 | return 0; | |
2556 | } | |
2557 | ||
2558 | mutex_lock(&gp->pm_mutex); | |
2559 | memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len); | |
2560 | if (gp->running) { | |
2561 | writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); | |
2562 | writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); | |
2563 | writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); | |
2564 | } | |
2565 | mutex_unlock(&gp->pm_mutex); | |
2566 | ||
2567 | return 0; | |
2568 | } | |
2569 | ||
1da177e4 LT |
2570 | static void gem_set_multicast(struct net_device *dev) |
2571 | { | |
8f15ea42 | 2572 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2573 | u32 rxcfg, rxcfg_new; |
2574 | int limit = 10000; | |
6aa20a22 | 2575 | |
1da177e4 LT |
2576 | |
2577 | spin_lock_irq(&gp->lock); | |
2578 | spin_lock(&gp->tx_lock); | |
2579 | ||
2580 | if (!gp->running) | |
2581 | goto bail; | |
2582 | ||
2583 | netif_stop_queue(dev); | |
2584 | ||
2585 | rxcfg = readl(gp->regs + MAC_RXCFG); | |
2586 | rxcfg_new = gem_setup_multicast(gp); | |
2587 | #ifdef STRIP_FCS | |
2588 | rxcfg_new |= MAC_RXCFG_SFCS; | |
2589 | #endif | |
2590 | gp->mac_rx_cfg = rxcfg_new; | |
6aa20a22 | 2591 | |
1da177e4 LT |
2592 | writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); |
2593 | while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) { | |
2594 | if (!limit--) | |
2595 | break; | |
2596 | udelay(10); | |
2597 | } | |
2598 | ||
2599 | rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE); | |
2600 | rxcfg |= rxcfg_new; | |
2601 | ||
2602 | writel(rxcfg, gp->regs + MAC_RXCFG); | |
2603 | ||
2604 | netif_wake_queue(dev); | |
2605 | ||
2606 | bail: | |
2607 | spin_unlock(&gp->tx_lock); | |
2608 | spin_unlock_irq(&gp->lock); | |
2609 | } | |
2610 | ||
2611 | /* Jumbo-grams don't seem to work :-( */ | |
2612 | #define GEM_MIN_MTU 68 | |
2613 | #if 1 | |
2614 | #define GEM_MAX_MTU 1500 | |
2615 | #else | |
2616 | #define GEM_MAX_MTU 9000 | |
2617 | #endif | |
2618 | ||
2619 | static int gem_change_mtu(struct net_device *dev, int new_mtu) | |
2620 | { | |
8f15ea42 | 2621 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2622 | |
2623 | if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU) | |
2624 | return -EINVAL; | |
2625 | ||
2626 | if (!netif_running(dev) || !netif_device_present(dev)) { | |
2627 | /* We'll just catch it later when the | |
2628 | * device is up'd or resumed. | |
2629 | */ | |
2630 | dev->mtu = new_mtu; | |
2631 | return 0; | |
2632 | } | |
2633 | ||
e3968fc0 | 2634 | mutex_lock(&gp->pm_mutex); |
1da177e4 LT |
2635 | spin_lock_irq(&gp->lock); |
2636 | spin_lock(&gp->tx_lock); | |
2637 | dev->mtu = new_mtu; | |
2638 | if (gp->running) { | |
2639 | gem_reinit_chip(gp); | |
2640 | if (gp->lstate == link_up) | |
2641 | gem_set_link_modes(gp); | |
2642 | } | |
2643 | spin_unlock(&gp->tx_lock); | |
2644 | spin_unlock_irq(&gp->lock); | |
e3968fc0 | 2645 | mutex_unlock(&gp->pm_mutex); |
1da177e4 LT |
2646 | |
2647 | return 0; | |
2648 | } | |
2649 | ||
2650 | static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
2651 | { | |
8f15ea42 | 2652 | struct gem *gp = netdev_priv(dev); |
6aa20a22 | 2653 | |
1da177e4 LT |
2654 | strcpy(info->driver, DRV_NAME); |
2655 | strcpy(info->version, DRV_VERSION); | |
2656 | strcpy(info->bus_info, pci_name(gp->pdev)); | |
2657 | } | |
6aa20a22 | 2658 | |
1da177e4 LT |
2659 | static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
2660 | { | |
8f15ea42 | 2661 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2662 | |
2663 | if (gp->phy_type == phy_mii_mdio0 || | |
2664 | gp->phy_type == phy_mii_mdio1) { | |
2665 | if (gp->phy_mii.def) | |
2666 | cmd->supported = gp->phy_mii.def->features; | |
2667 | else | |
2668 | cmd->supported = (SUPPORTED_10baseT_Half | | |
2669 | SUPPORTED_10baseT_Full); | |
2670 | ||
2671 | /* XXX hardcoded stuff for now */ | |
2672 | cmd->port = PORT_MII; | |
2673 | cmd->transceiver = XCVR_EXTERNAL; | |
2674 | cmd->phy_address = 0; /* XXX fixed PHYAD */ | |
2675 | ||
2676 | /* Return current PHY settings */ | |
2677 | spin_lock_irq(&gp->lock); | |
2678 | cmd->autoneg = gp->want_autoneg; | |
2679 | cmd->speed = gp->phy_mii.speed; | |
6aa20a22 | 2680 | cmd->duplex = gp->phy_mii.duplex; |
1da177e4 LT |
2681 | cmd->advertising = gp->phy_mii.advertising; |
2682 | ||
2683 | /* If we started with a forced mode, we don't have a default | |
2684 | * advertise set, we need to return something sensible so | |
2685 | * userland can re-enable autoneg properly. | |
2686 | */ | |
2687 | if (cmd->advertising == 0) | |
2688 | cmd->advertising = cmd->supported; | |
2689 | spin_unlock_irq(&gp->lock); | |
2690 | } else { // XXX PCS ? | |
2691 | cmd->supported = | |
2692 | (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
2693 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
2694 | SUPPORTED_Autoneg); | |
2695 | cmd->advertising = cmd->supported; | |
2696 | cmd->speed = 0; | |
2697 | cmd->duplex = cmd->port = cmd->phy_address = | |
2698 | cmd->transceiver = cmd->autoneg = 0; | |
fbf0229e HL |
2699 | |
2700 | /* serdes means usually a Fibre connector, with most fixed */ | |
2701 | if (gp->phy_type == phy_serdes) { | |
2702 | cmd->port = PORT_FIBRE; | |
2703 | cmd->supported = (SUPPORTED_1000baseT_Half | | |
2704 | SUPPORTED_1000baseT_Full | | |
2705 | SUPPORTED_FIBRE | SUPPORTED_Autoneg | | |
2706 | SUPPORTED_Pause | SUPPORTED_Asym_Pause); | |
2707 | cmd->advertising = cmd->supported; | |
2708 | cmd->transceiver = XCVR_INTERNAL; | |
2709 | if (gp->lstate == link_up) | |
2710 | cmd->speed = SPEED_1000; | |
2711 | cmd->duplex = DUPLEX_FULL; | |
2712 | cmd->autoneg = 1; | |
2713 | } | |
1da177e4 LT |
2714 | } |
2715 | cmd->maxtxpkt = cmd->maxrxpkt = 0; | |
2716 | ||
2717 | return 0; | |
2718 | } | |
2719 | ||
2720 | static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2721 | { | |
8f15ea42 | 2722 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2723 | |
2724 | /* Verify the settings we care about. */ | |
2725 | if (cmd->autoneg != AUTONEG_ENABLE && | |
2726 | cmd->autoneg != AUTONEG_DISABLE) | |
2727 | return -EINVAL; | |
2728 | ||
2729 | if (cmd->autoneg == AUTONEG_ENABLE && | |
2730 | cmd->advertising == 0) | |
2731 | return -EINVAL; | |
2732 | ||
2733 | if (cmd->autoneg == AUTONEG_DISABLE && | |
2734 | ((cmd->speed != SPEED_1000 && | |
2735 | cmd->speed != SPEED_100 && | |
2736 | cmd->speed != SPEED_10) || | |
2737 | (cmd->duplex != DUPLEX_HALF && | |
2738 | cmd->duplex != DUPLEX_FULL))) | |
2739 | return -EINVAL; | |
6aa20a22 | 2740 | |
1da177e4 LT |
2741 | /* Apply settings and restart link process. */ |
2742 | spin_lock_irq(&gp->lock); | |
2743 | gem_get_cell(gp); | |
2744 | gem_begin_auto_negotiation(gp, cmd); | |
2745 | gem_put_cell(gp); | |
2746 | spin_unlock_irq(&gp->lock); | |
2747 | ||
2748 | return 0; | |
2749 | } | |
2750 | ||
2751 | static int gem_nway_reset(struct net_device *dev) | |
2752 | { | |
8f15ea42 | 2753 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2754 | |
2755 | if (!gp->want_autoneg) | |
2756 | return -EINVAL; | |
2757 | ||
2758 | /* Restart link process. */ | |
2759 | spin_lock_irq(&gp->lock); | |
2760 | gem_get_cell(gp); | |
2761 | gem_begin_auto_negotiation(gp, NULL); | |
2762 | gem_put_cell(gp); | |
2763 | spin_unlock_irq(&gp->lock); | |
2764 | ||
2765 | return 0; | |
2766 | } | |
2767 | ||
2768 | static u32 gem_get_msglevel(struct net_device *dev) | |
2769 | { | |
8f15ea42 | 2770 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2771 | return gp->msg_enable; |
2772 | } | |
6aa20a22 | 2773 | |
1da177e4 LT |
2774 | static void gem_set_msglevel(struct net_device *dev, u32 value) |
2775 | { | |
8f15ea42 | 2776 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2777 | gp->msg_enable = value; |
2778 | } | |
2779 | ||
2780 | ||
2781 | /* Add more when I understand how to program the chip */ | |
2782 | /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */ | |
2783 | ||
2784 | #define WOL_SUPPORTED_MASK (WAKE_MAGIC) | |
2785 | ||
2786 | static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2787 | { | |
8f15ea42 | 2788 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2789 | |
2790 | /* Add more when I understand how to program the chip */ | |
2791 | if (gp->has_wol) { | |
2792 | wol->supported = WOL_SUPPORTED_MASK; | |
2793 | wol->wolopts = gp->wake_on_lan; | |
2794 | } else { | |
2795 | wol->supported = 0; | |
2796 | wol->wolopts = 0; | |
2797 | } | |
2798 | } | |
2799 | ||
2800 | static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2801 | { | |
8f15ea42 | 2802 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2803 | |
2804 | if (!gp->has_wol) | |
2805 | return -EOPNOTSUPP; | |
2806 | gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK; | |
2807 | return 0; | |
2808 | } | |
2809 | ||
7282d491 | 2810 | static const struct ethtool_ops gem_ethtool_ops = { |
1da177e4 LT |
2811 | .get_drvinfo = gem_get_drvinfo, |
2812 | .get_link = ethtool_op_get_link, | |
2813 | .get_settings = gem_get_settings, | |
2814 | .set_settings = gem_set_settings, | |
2815 | .nway_reset = gem_nway_reset, | |
2816 | .get_msglevel = gem_get_msglevel, | |
2817 | .set_msglevel = gem_set_msglevel, | |
2818 | .get_wol = gem_get_wol, | |
2819 | .set_wol = gem_set_wol, | |
2820 | }; | |
2821 | ||
2822 | static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2823 | { | |
8f15ea42 | 2824 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2825 | struct mii_ioctl_data *data = if_mii(ifr); |
2826 | int rc = -EOPNOTSUPP; | |
2827 | unsigned long flags; | |
2828 | ||
e3968fc0 | 2829 | /* Hold the PM mutex while doing ioctl's or we may collide |
1da177e4 LT |
2830 | * with power management. |
2831 | */ | |
e3968fc0 | 2832 | mutex_lock(&gp->pm_mutex); |
6aa20a22 | 2833 | |
1da177e4 LT |
2834 | spin_lock_irqsave(&gp->lock, flags); |
2835 | gem_get_cell(gp); | |
2836 | spin_unlock_irqrestore(&gp->lock, flags); | |
2837 | ||
2838 | switch (cmd) { | |
2839 | case SIOCGMIIPHY: /* Get address of MII PHY in use. */ | |
2840 | data->phy_id = gp->mii_phy_addr; | |
2841 | /* Fallthrough... */ | |
2842 | ||
2843 | case SIOCGMIIREG: /* Read MII PHY register. */ | |
2844 | if (!gp->running) | |
2845 | rc = -EAGAIN; | |
2846 | else { | |
2847 | data->val_out = __phy_read(gp, data->phy_id & 0x1f, | |
2848 | data->reg_num & 0x1f); | |
2849 | rc = 0; | |
2850 | } | |
2851 | break; | |
2852 | ||
2853 | case SIOCSMIIREG: /* Write MII PHY register. */ | |
2854 | if (!capable(CAP_NET_ADMIN)) | |
2855 | rc = -EPERM; | |
2856 | else if (!gp->running) | |
2857 | rc = -EAGAIN; | |
2858 | else { | |
2859 | __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, | |
2860 | data->val_in); | |
2861 | rc = 0; | |
2862 | } | |
2863 | break; | |
2864 | }; | |
6aa20a22 | 2865 | |
1da177e4 LT |
2866 | spin_lock_irqsave(&gp->lock, flags); |
2867 | gem_put_cell(gp); | |
2868 | spin_unlock_irqrestore(&gp->lock, flags); | |
2869 | ||
e3968fc0 | 2870 | mutex_unlock(&gp->pm_mutex); |
6aa20a22 | 2871 | |
1da177e4 LT |
2872 | return rc; |
2873 | } | |
2874 | ||
dadb830d | 2875 | #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC)) |
1da177e4 | 2876 | /* Fetch MAC address from vital product data of PCI ROM. */ |
4120b028 | 2877 | static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr) |
1da177e4 LT |
2878 | { |
2879 | int this_offset; | |
2880 | ||
2881 | for (this_offset = 0x20; this_offset < len; this_offset++) { | |
2882 | void __iomem *p = rom_base + this_offset; | |
2883 | int i; | |
2884 | ||
2885 | if (readb(p + 0) != 0x90 || | |
2886 | readb(p + 1) != 0x00 || | |
2887 | readb(p + 2) != 0x09 || | |
2888 | readb(p + 3) != 0x4e || | |
2889 | readb(p + 4) != 0x41 || | |
2890 | readb(p + 5) != 0x06) | |
2891 | continue; | |
2892 | ||
2893 | this_offset += 6; | |
2894 | p += 6; | |
2895 | ||
2896 | for (i = 0; i < 6; i++) | |
2897 | dev_addr[i] = readb(p + i); | |
4120b028 | 2898 | return 1; |
1da177e4 | 2899 | } |
4120b028 | 2900 | return 0; |
1da177e4 LT |
2901 | } |
2902 | ||
2903 | static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr) | |
2904 | { | |
4120b028 LT |
2905 | size_t size; |
2906 | void __iomem *p = pci_map_rom(pdev, &size); | |
1da177e4 | 2907 | |
4120b028 LT |
2908 | if (p) { |
2909 | int found; | |
1da177e4 | 2910 | |
4120b028 LT |
2911 | found = readb(p) == 0x55 && |
2912 | readb(p + 1) == 0xaa && | |
2913 | find_eth_addr_in_vpd(p, (64 * 1024), dev_addr); | |
2914 | pci_unmap_rom(pdev, p); | |
2915 | if (found) | |
2916 | return; | |
2917 | } | |
1da177e4 | 2918 | |
1da177e4 LT |
2919 | /* Sun MAC prefix then 3 random bytes. */ |
2920 | dev_addr[0] = 0x08; | |
2921 | dev_addr[1] = 0x00; | |
2922 | dev_addr[2] = 0x20; | |
2923 | get_random_bytes(dev_addr + 3, 3); | |
2924 | return; | |
2925 | } | |
2926 | #endif /* not Sparc and not PPC */ | |
2927 | ||
2928 | static int __devinit gem_get_device_address(struct gem *gp) | |
2929 | { | |
dadb830d | 2930 | #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC) |
1da177e4 | 2931 | struct net_device *dev = gp->dev; |
1a2509c9 | 2932 | const unsigned char *addr; |
1da177e4 | 2933 | |
40cd3a45 | 2934 | addr = of_get_property(gp->of_node, "local-mac-address", NULL); |
1da177e4 | 2935 | if (addr == NULL) { |
457e1a8a DM |
2936 | #ifdef CONFIG_SPARC |
2937 | addr = idprom->id_ethaddr; | |
2938 | #else | |
1da177e4 LT |
2939 | printk("\n"); |
2940 | printk(KERN_ERR "%s: can't get mac-address\n", dev->name); | |
2941 | return -1; | |
457e1a8a | 2942 | #endif |
1da177e4 LT |
2943 | } |
2944 | memcpy(dev->dev_addr, addr, 6); | |
2945 | #else | |
2946 | get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr); | |
2947 | #endif | |
2948 | return 0; | |
2949 | } | |
2950 | ||
14904398 | 2951 | static void gem_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
2952 | { |
2953 | struct net_device *dev = pci_get_drvdata(pdev); | |
2954 | ||
2955 | if (dev) { | |
8f15ea42 | 2956 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2957 | |
2958 | unregister_netdev(dev); | |
2959 | ||
2960 | /* Stop the link timer */ | |
2961 | del_timer_sync(&gp->link_timer); | |
2962 | ||
2963 | /* We shouldn't need any locking here */ | |
2964 | gem_get_cell(gp); | |
2965 | ||
2966 | /* Wait for a pending reset task to complete */ | |
2967 | while (gp->reset_task_pending) | |
2968 | yield(); | |
2969 | flush_scheduled_work(); | |
2970 | ||
2971 | /* Shut the PHY down */ | |
2972 | gem_stop_phy(gp, 0); | |
2973 | ||
2974 | gem_put_cell(gp); | |
2975 | ||
2976 | /* Make sure bus master is disabled */ | |
2977 | pci_disable_device(gp->pdev); | |
2978 | ||
2979 | /* Free resources */ | |
2980 | pci_free_consistent(pdev, | |
2981 | sizeof(struct gem_init_block), | |
2982 | gp->init_block, | |
2983 | gp->gblock_dvma); | |
2984 | iounmap(gp->regs); | |
2985 | pci_release_regions(pdev); | |
2986 | free_netdev(dev); | |
2987 | ||
2988 | pci_set_drvdata(pdev, NULL); | |
2989 | } | |
2990 | } | |
2991 | ||
d9a811d5 SH |
2992 | static const struct net_device_ops gem_netdev_ops = { |
2993 | .ndo_open = gem_open, | |
2994 | .ndo_stop = gem_close, | |
2995 | .ndo_start_xmit = gem_start_xmit, | |
2996 | .ndo_get_stats = gem_get_stats, | |
2997 | .ndo_set_multicast_list = gem_set_multicast, | |
2998 | .ndo_do_ioctl = gem_ioctl, | |
2999 | .ndo_tx_timeout = gem_tx_timeout, | |
3000 | .ndo_change_mtu = gem_change_mtu, | |
d9a811d5 | 3001 | .ndo_validate_addr = eth_validate_addr, |
5ed0102f SH |
3002 | .ndo_set_mac_address = gem_set_mac_address, |
3003 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3004 | .ndo_poll_controller = gem_poll_controller, | |
3005 | #endif | |
d9a811d5 SH |
3006 | }; |
3007 | ||
1da177e4 LT |
3008 | static int __devinit gem_init_one(struct pci_dev *pdev, |
3009 | const struct pci_device_id *ent) | |
3010 | { | |
3011 | static int gem_version_printed = 0; | |
3012 | unsigned long gemreg_base, gemreg_len; | |
3013 | struct net_device *dev; | |
3014 | struct gem *gp; | |
0795af57 | 3015 | int err, pci_using_dac; |
1da177e4 LT |
3016 | |
3017 | if (gem_version_printed++ == 0) | |
3018 | printk(KERN_INFO "%s", version); | |
3019 | ||
3020 | /* Apple gmac note: during probe, the chip is powered up by | |
3021 | * the arch code to allow the code below to work (and to let | |
3022 | * the chip be probed on the config space. It won't stay powered | |
3023 | * up until the interface is brought up however, so we can't rely | |
3024 | * on register configuration done at this point. | |
3025 | */ | |
3026 | err = pci_enable_device(pdev); | |
3027 | if (err) { | |
3028 | printk(KERN_ERR PFX "Cannot enable MMIO operation, " | |
3029 | "aborting.\n"); | |
3030 | return err; | |
3031 | } | |
3032 | pci_set_master(pdev); | |
3033 | ||
3034 | /* Configure DMA attributes. */ | |
3035 | ||
3036 | /* All of the GEM documentation states that 64-bit DMA addressing | |
3037 | * is fully supported and should work just fine. However the | |
3038 | * front end for RIO based GEMs is different and only supports | |
3039 | * 32-bit addressing. | |
3040 | * | |
3041 | * For now we assume the various PPC GEMs are 32-bit only as well. | |
3042 | */ | |
3043 | if (pdev->vendor == PCI_VENDOR_ID_SUN && | |
3044 | pdev->device == PCI_DEVICE_ID_SUN_GEM && | |
1e7f0bd8 | 3045 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
1da177e4 LT |
3046 | pci_using_dac = 1; |
3047 | } else { | |
1e7f0bd8 | 3048 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
1da177e4 LT |
3049 | if (err) { |
3050 | printk(KERN_ERR PFX "No usable DMA configuration, " | |
3051 | "aborting.\n"); | |
3052 | goto err_disable_device; | |
3053 | } | |
3054 | pci_using_dac = 0; | |
3055 | } | |
6aa20a22 | 3056 | |
1da177e4 LT |
3057 | gemreg_base = pci_resource_start(pdev, 0); |
3058 | gemreg_len = pci_resource_len(pdev, 0); | |
3059 | ||
3060 | if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) { | |
3061 | printk(KERN_ERR PFX "Cannot find proper PCI device " | |
3062 | "base address, aborting.\n"); | |
3063 | err = -ENODEV; | |
3064 | goto err_disable_device; | |
3065 | } | |
3066 | ||
3067 | dev = alloc_etherdev(sizeof(*gp)); | |
3068 | if (!dev) { | |
3069 | printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n"); | |
3070 | err = -ENOMEM; | |
3071 | goto err_disable_device; | |
3072 | } | |
1da177e4 LT |
3073 | SET_NETDEV_DEV(dev, &pdev->dev); |
3074 | ||
8f15ea42 | 3075 | gp = netdev_priv(dev); |
1da177e4 LT |
3076 | |
3077 | err = pci_request_regions(pdev, DRV_NAME); | |
3078 | if (err) { | |
3079 | printk(KERN_ERR PFX "Cannot obtain PCI resources, " | |
3080 | "aborting.\n"); | |
3081 | goto err_out_free_netdev; | |
3082 | } | |
3083 | ||
3084 | gp->pdev = pdev; | |
3085 | dev->base_addr = (long) pdev; | |
3086 | gp->dev = dev; | |
3087 | ||
3088 | gp->msg_enable = DEFAULT_MSG; | |
3089 | ||
3090 | spin_lock_init(&gp->lock); | |
3091 | spin_lock_init(&gp->tx_lock); | |
e3968fc0 | 3092 | mutex_init(&gp->pm_mutex); |
1da177e4 LT |
3093 | |
3094 | init_timer(&gp->link_timer); | |
3095 | gp->link_timer.function = gem_link_timer; | |
3096 | gp->link_timer.data = (unsigned long) gp; | |
3097 | ||
c4028958 | 3098 | INIT_WORK(&gp->reset_task, gem_reset_task); |
6aa20a22 | 3099 | |
1da177e4 LT |
3100 | gp->lstate = link_down; |
3101 | gp->timer_ticks = 0; | |
3102 | netif_carrier_off(dev); | |
3103 | ||
3104 | gp->regs = ioremap(gemreg_base, gemreg_len); | |
79ea13ce | 3105 | if (!gp->regs) { |
1da177e4 LT |
3106 | printk(KERN_ERR PFX "Cannot map device registers, " |
3107 | "aborting.\n"); | |
3108 | err = -EIO; | |
3109 | goto err_out_free_res; | |
3110 | } | |
3111 | ||
3112 | /* On Apple, we want a reference to the Open Firmware device-tree | |
3113 | * node. We use it for clock control. | |
3114 | */ | |
457e1a8a | 3115 | #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC) |
1da177e4 LT |
3116 | gp->of_node = pci_device_to_OF_node(pdev); |
3117 | #endif | |
3118 | ||
3119 | /* Only Apple version supports WOL afaik */ | |
3120 | if (pdev->vendor == PCI_VENDOR_ID_APPLE) | |
3121 | gp->has_wol = 1; | |
3122 | ||
3123 | /* Make sure cell is enabled */ | |
3124 | gem_get_cell(gp); | |
3125 | ||
3126 | /* Make sure everything is stopped and in init state */ | |
3127 | gem_reset(gp); | |
3128 | ||
3129 | /* Fill up the mii_phy structure (even if we won't use it) */ | |
3130 | gp->phy_mii.dev = dev; | |
3131 | gp->phy_mii.mdio_read = _phy_read; | |
3132 | gp->phy_mii.mdio_write = _phy_write; | |
3c326fe9 BH |
3133 | #ifdef CONFIG_PPC_PMAC |
3134 | gp->phy_mii.platform_data = gp->of_node; | |
3135 | #endif | |
1da177e4 LT |
3136 | /* By default, we start with autoneg */ |
3137 | gp->want_autoneg = 1; | |
3138 | ||
3139 | /* Check fifo sizes, PHY type, etc... */ | |
3140 | if (gem_check_invariants(gp)) { | |
3141 | err = -ENODEV; | |
3142 | goto err_out_iounmap; | |
3143 | } | |
3144 | ||
3145 | /* It is guaranteed that the returned buffer will be at least | |
3146 | * PAGE_SIZE aligned. | |
3147 | */ | |
3148 | gp->init_block = (struct gem_init_block *) | |
3149 | pci_alloc_consistent(pdev, sizeof(struct gem_init_block), | |
3150 | &gp->gblock_dvma); | |
3151 | if (!gp->init_block) { | |
3152 | printk(KERN_ERR PFX "Cannot allocate init block, " | |
3153 | "aborting.\n"); | |
3154 | err = -ENOMEM; | |
3155 | goto err_out_iounmap; | |
3156 | } | |
3157 | ||
3158 | if (gem_get_device_address(gp)) | |
3159 | goto err_out_free_consistent; | |
3160 | ||
d9a811d5 | 3161 | dev->netdev_ops = &gem_netdev_ops; |
bea3348e | 3162 | netif_napi_add(dev, &gp->napi, gem_poll, 64); |
1da177e4 | 3163 | dev->ethtool_ops = &gem_ethtool_ops; |
1da177e4 | 3164 | dev->watchdog_timeo = 5 * HZ; |
1da177e4 LT |
3165 | dev->irq = pdev->irq; |
3166 | dev->dma = 0; | |
1da177e4 LT |
3167 | |
3168 | /* Set that now, in case PM kicks in now */ | |
3169 | pci_set_drvdata(pdev, dev); | |
3170 | ||
3171 | /* Detect & init PHY, start autoneg, we release the cell now | |
3172 | * too, it will be managed by whoever needs it | |
3173 | */ | |
3174 | gem_init_phy(gp); | |
3175 | ||
3176 | spin_lock_irq(&gp->lock); | |
3177 | gem_put_cell(gp); | |
3178 | spin_unlock_irq(&gp->lock); | |
3179 | ||
3180 | /* Register with kernel */ | |
3181 | if (register_netdev(dev)) { | |
3182 | printk(KERN_ERR PFX "Cannot register net device, " | |
3183 | "aborting.\n"); | |
3184 | err = -ENOMEM; | |
3185 | goto err_out_free_consistent; | |
3186 | } | |
3187 | ||
e174961c JB |
3188 | printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n", |
3189 | dev->name, dev->dev_addr); | |
1da177e4 LT |
3190 | |
3191 | if (gp->phy_type == phy_mii_mdio0 || | |
3192 | gp->phy_type == phy_mii_mdio1) | |
6aa20a22 | 3193 | printk(KERN_INFO "%s: Found %s PHY\n", dev->name, |
1da177e4 LT |
3194 | gp->phy_mii.def ? gp->phy_mii.def->name : "no"); |
3195 | ||
3196 | /* GEM can do it all... */ | |
3197 | dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX; | |
3198 | if (pci_using_dac) | |
3199 | dev->features |= NETIF_F_HIGHDMA; | |
3200 | ||
3201 | return 0; | |
3202 | ||
3203 | err_out_free_consistent: | |
3204 | gem_remove_one(pdev); | |
3205 | err_out_iounmap: | |
3206 | gem_put_cell(gp); | |
3207 | iounmap(gp->regs); | |
3208 | ||
3209 | err_out_free_res: | |
3210 | pci_release_regions(pdev); | |
3211 | ||
3212 | err_out_free_netdev: | |
3213 | free_netdev(dev); | |
3214 | err_disable_device: | |
3215 | pci_disable_device(pdev); | |
3216 | return err; | |
3217 | ||
3218 | } | |
3219 | ||
3220 | ||
3221 | static struct pci_driver gem_driver = { | |
3222 | .name = GEM_MODULE_NAME, | |
3223 | .id_table = gem_pci_tbl, | |
3224 | .probe = gem_init_one, | |
14904398 | 3225 | .remove = gem_remove_one, |
1da177e4 LT |
3226 | #ifdef CONFIG_PM |
3227 | .suspend = gem_suspend, | |
3228 | .resume = gem_resume, | |
3229 | #endif /* CONFIG_PM */ | |
3230 | }; | |
3231 | ||
3232 | static int __init gem_init(void) | |
3233 | { | |
29917620 | 3234 | return pci_register_driver(&gem_driver); |
1da177e4 LT |
3235 | } |
3236 | ||
3237 | static void __exit gem_cleanup(void) | |
3238 | { | |
3239 | pci_unregister_driver(&gem_driver); | |
3240 | } | |
3241 | ||
3242 | module_init(gem_init); | |
3243 | module_exit(gem_cleanup); |