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Commit | Line | Data |
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eea221ce AN |
1 | /* |
2 | * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux. | |
1da177e4 LT |
3 | * |
4 | * Based on skelton.c by Donald Becker. | |
1da177e4 | 5 | * |
eea221ce AN |
6 | * This driver is a replacement of older and less maintained version. |
7 | * This is a header of the older version: | |
8 | * -----<snip>----- | |
9 | * Copyright 2001 MontaVista Software Inc. | |
10 | * Author: MontaVista Software, Inc. | |
11 | * ahennessy@mvista.com | |
12 | * Copyright (C) 2000-2001 Toshiba Corporation | |
13 | * static const char *version = | |
14 | * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n"; | |
15 | * -----<snip>----- | |
1da177e4 | 16 | * |
eea221ce AN |
17 | * This file is subject to the terms and conditions of the GNU General Public |
18 | * License. See the file "COPYING" in the main directory of this archive | |
19 | * for more details. | |
1da177e4 | 20 | * |
eea221ce AN |
21 | * (C) Copyright TOSHIBA CORPORATION 2004-2005 |
22 | * All Rights Reserved. | |
1da177e4 LT |
23 | */ |
24 | ||
c6a2dbba | 25 | #define DRV_VERSION "1.39" |
eea221ce AN |
26 | static const char *version = "tc35815.c:v" DRV_VERSION "\n"; |
27 | #define MODNAME "tc35815" | |
1da177e4 LT |
28 | |
29 | #include <linux/module.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/types.h> | |
32 | #include <linux/fcntl.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/ioport.h> | |
35 | #include <linux/in.h> | |
82a9928d | 36 | #include <linux/if_vlan.h> |
1da177e4 LT |
37 | #include <linux/slab.h> |
38 | #include <linux/string.h> | |
eea221ce | 39 | #include <linux/spinlock.h> |
1da177e4 LT |
40 | #include <linux/errno.h> |
41 | #include <linux/init.h> | |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/etherdevice.h> | |
44 | #include <linux/skbuff.h> | |
45 | #include <linux/delay.h> | |
46 | #include <linux/pci.h> | |
c6686fe3 AN |
47 | #include <linux/phy.h> |
48 | #include <linux/workqueue.h> | |
bd43da8f | 49 | #include <linux/platform_device.h> |
70c71606 | 50 | #include <linux/prefetch.h> |
1da177e4 | 51 | #include <asm/io.h> |
1da177e4 LT |
52 | #include <asm/byteorder.h> |
53 | ||
c6686fe3 | 54 | enum tc35815_chiptype { |
eea221ce AN |
55 | TC35815CF = 0, |
56 | TC35815_NWU, | |
57 | TC35815_TX4939, | |
c6686fe3 | 58 | }; |
eea221ce | 59 | |
c6686fe3 | 60 | /* indexed by tc35815_chiptype, above */ |
eea221ce AN |
61 | static const struct { |
62 | const char *name; | |
c6686fe3 | 63 | } chip_info[] __devinitdata = { |
eea221ce AN |
64 | { "TOSHIBA TC35815CF 10/100BaseTX" }, |
65 | { "TOSHIBA TC35815 with Wake on LAN" }, | |
66 | { "TOSHIBA TC35815/TX4939" }, | |
67 | }; | |
68 | ||
a3aa1884 | 69 | static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = { |
eea221ce AN |
70 | {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF }, |
71 | {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU }, | |
72 | {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 }, | |
73 | {0,} | |
74 | }; | |
7f225b42 | 75 | MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl); |
1da177e4 | 76 | |
eea221ce AN |
77 | /* see MODULE_PARM_DESC */ |
78 | static struct tc35815_options { | |
79 | int speed; | |
80 | int duplex; | |
eea221ce | 81 | } options; |
1da177e4 LT |
82 | |
83 | /* | |
84 | * Registers | |
85 | */ | |
86 | struct tc35815_regs { | |
22adf7e5 AN |
87 | __u32 DMA_Ctl; /* 0x00 */ |
88 | __u32 TxFrmPtr; | |
89 | __u32 TxThrsh; | |
90 | __u32 TxPollCtr; | |
91 | __u32 BLFrmPtr; | |
92 | __u32 RxFragSize; | |
93 | __u32 Int_En; | |
94 | __u32 FDA_Bas; | |
95 | __u32 FDA_Lim; /* 0x20 */ | |
96 | __u32 Int_Src; | |
97 | __u32 unused0[2]; | |
98 | __u32 PauseCnt; | |
99 | __u32 RemPauCnt; | |
100 | __u32 TxCtlFrmStat; | |
101 | __u32 unused1; | |
102 | __u32 MAC_Ctl; /* 0x40 */ | |
103 | __u32 CAM_Ctl; | |
104 | __u32 Tx_Ctl; | |
105 | __u32 Tx_Stat; | |
106 | __u32 Rx_Ctl; | |
107 | __u32 Rx_Stat; | |
108 | __u32 MD_Data; | |
109 | __u32 MD_CA; | |
110 | __u32 CAM_Adr; /* 0x60 */ | |
111 | __u32 CAM_Data; | |
112 | __u32 CAM_Ena; | |
113 | __u32 PROM_Ctl; | |
114 | __u32 PROM_Data; | |
115 | __u32 Algn_Cnt; | |
116 | __u32 CRC_Cnt; | |
117 | __u32 Miss_Cnt; | |
1da177e4 LT |
118 | }; |
119 | ||
120 | /* | |
121 | * Bit assignments | |
122 | */ | |
25985edc | 123 | /* DMA_Ctl bit assign ------------------------------------------------------- */ |
7f225b42 AN |
124 | #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */ |
125 | #define DMA_RxAlign_1 0x00400000 | |
126 | #define DMA_RxAlign_2 0x00800000 | |
127 | #define DMA_RxAlign_3 0x00c00000 | |
128 | #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */ | |
25985edc | 129 | #define DMA_IntMask 0x00040000 /* 1:Interrupt mask */ |
7f225b42 AN |
130 | #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */ |
131 | #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */ | |
132 | #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */ | |
133 | #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */ | |
134 | #define DMA_TestMode 0x00002000 /* 1:Test Mode */ | |
135 | #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */ | |
136 | #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */ | |
1da177e4 | 137 | |
25985edc | 138 | /* RxFragSize bit assign ---------------------------------------------------- */ |
7f225b42 AN |
139 | #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */ |
140 | #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */ | |
1da177e4 | 141 | |
25985edc | 142 | /* MAC_Ctl bit assign ------------------------------------------------------- */ |
7f225b42 AN |
143 | #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */ |
144 | #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */ | |
145 | #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */ | |
146 | #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */ | |
147 | #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */ | |
148 | #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/ | |
149 | #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */ | |
150 | #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */ | |
151 | #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */ | |
152 | #define MAC_Reset 0x00000004 /* 1:Software Reset */ | |
153 | #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */ | |
154 | #define MAC_HaltReq 0x00000001 /* 1:Halt request */ | |
1da177e4 | 155 | |
25985edc | 156 | /* PROM_Ctl bit assign ------------------------------------------------------ */ |
7f225b42 AN |
157 | #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */ |
158 | #define PROM_Read 0x00004000 /*10:Read operation */ | |
159 | #define PROM_Write 0x00002000 /*01:Write operation */ | |
160 | #define PROM_Erase 0x00006000 /*11:Erase operation */ | |
161 | /*00:Enable or Disable Writting, */ | |
162 | /* as specified in PROM_Addr. */ | |
163 | #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */ | |
164 | /*00xxxx: disable */ | |
1da177e4 | 165 | |
25985edc | 166 | /* CAM_Ctl bit assign ------------------------------------------------------- */ |
7f225b42 AN |
167 | #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */ |
168 | #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/ | |
169 | /* accept other */ | |
170 | #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */ | |
171 | #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */ | |
172 | #define CAM_StationAcc 0x00000001 /* 1:unicast accept */ | |
1da177e4 | 173 | |
25985edc | 174 | /* CAM_Ena bit assign ------------------------------------------------------- */ |
7f225b42 | 175 | #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */ |
1da177e4 | 176 | #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */ |
7f225b42 | 177 | #define CAM_Ena_Bit(index) (1 << (index)) |
1da177e4 LT |
178 | #define CAM_ENTRY_DESTINATION 0 |
179 | #define CAM_ENTRY_SOURCE 1 | |
180 | #define CAM_ENTRY_MACCTL 20 | |
181 | ||
25985edc | 182 | /* Tx_Ctl bit assign -------------------------------------------------------- */ |
7f225b42 AN |
183 | #define Tx_En 0x00000001 /* 1:Transmit enable */ |
184 | #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */ | |
185 | #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */ | |
186 | #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */ | |
187 | #define Tx_FBack 0x00000010 /* 1:Fast Back-off */ | |
188 | #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */ | |
189 | #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */ | |
190 | #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */ | |
191 | #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */ | |
192 | #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */ | |
193 | #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */ | |
194 | #define Tx_EnComp 0x00004000 /* 1:Enable Completion */ | |
1da177e4 | 195 | |
25985edc | 196 | /* Tx_Stat bit assign ------------------------------------------------------- */ |
7f225b42 AN |
197 | #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */ |
198 | #define Tx_ExColl 0x00000010 /* Excessive Collision */ | |
199 | #define Tx_TXDefer 0x00000020 /* Transmit Defered */ | |
200 | #define Tx_Paused 0x00000040 /* Transmit Paused */ | |
201 | #define Tx_IntTx 0x00000080 /* Interrupt on Tx */ | |
202 | #define Tx_Under 0x00000100 /* Underrun */ | |
203 | #define Tx_Defer 0x00000200 /* Deferral */ | |
204 | #define Tx_NCarr 0x00000400 /* No Carrier */ | |
205 | #define Tx_10Stat 0x00000800 /* 10Mbps Status */ | |
206 | #define Tx_LateColl 0x00001000 /* Late Collision */ | |
207 | #define Tx_TxPar 0x00002000 /* Tx Parity Error */ | |
208 | #define Tx_Comp 0x00004000 /* Completion */ | |
209 | #define Tx_Halted 0x00008000 /* Tx Halted */ | |
210 | #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */ | |
1da177e4 | 211 | |
25985edc | 212 | /* Rx_Ctl bit assign -------------------------------------------------------- */ |
7f225b42 AN |
213 | #define Rx_EnGood 0x00004000 /* 1:Enable Good */ |
214 | #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */ | |
215 | #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */ | |
216 | #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */ | |
217 | #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */ | |
218 | #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */ | |
219 | #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */ | |
220 | #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */ | |
221 | #define Rx_ShortEn 0x00000008 /* 1:Short Enable */ | |
222 | #define Rx_LongEn 0x00000004 /* 1:Long Enable */ | |
223 | #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */ | |
224 | #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */ | |
1da177e4 | 225 | |
25985edc | 226 | /* Rx_Stat bit assign ------------------------------------------------------- */ |
7f225b42 AN |
227 | #define Rx_Halted 0x00008000 /* Rx Halted */ |
228 | #define Rx_Good 0x00004000 /* Rx Good */ | |
229 | #define Rx_RxPar 0x00002000 /* Rx Parity Error */ | |
842e08bd | 230 | #define Rx_TypePkt 0x00001000 /* Rx Type Packet */ |
7f225b42 AN |
231 | #define Rx_LongErr 0x00000800 /* Rx Long Error */ |
232 | #define Rx_Over 0x00000400 /* Rx Overflow */ | |
233 | #define Rx_CRCErr 0x00000200 /* Rx CRC Error */ | |
234 | #define Rx_Align 0x00000100 /* Rx Alignment Error */ | |
235 | #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */ | |
236 | #define Rx_IntRx 0x00000040 /* Rx Interrupt */ | |
237 | #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */ | |
842e08bd | 238 | #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */ |
7f225b42 | 239 | |
842e08bd | 240 | #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */ |
1da177e4 | 241 | |
25985edc | 242 | /* Int_En bit assign -------------------------------------------------------- */ |
7f225b42 AN |
243 | #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */ |
244 | #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */ | |
245 | #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */ | |
246 | #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */ | |
247 | #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */ | |
248 | #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */ | |
249 | #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */ | |
250 | #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */ | |
251 | #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */ | |
252 | #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */ | |
253 | #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */ | |
254 | #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */ | |
255 | /* Exhausted Enable */ | |
1da177e4 | 256 | |
25985edc | 257 | /* Int_Src bit assign ------------------------------------------------------- */ |
7f225b42 AN |
258 | #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */ |
259 | #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */ | |
260 | #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */ | |
261 | #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */ | |
262 | #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */ | |
263 | #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */ | |
264 | #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */ | |
265 | #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */ | |
266 | #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */ | |
267 | #define Int_SWInt 0x00000020 /* 1:Software request & Clear */ | |
268 | #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */ | |
269 | #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */ | |
270 | #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */ | |
271 | #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */ | |
272 | #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */ | |
1da177e4 | 273 | |
25985edc LDM |
274 | /* MD_CA bit assign --------------------------------------------------------- */ |
275 | #define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */ | |
7f225b42 AN |
276 | #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */ |
277 | #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */ | |
1da177e4 LT |
278 | |
279 | ||
1da177e4 LT |
280 | /* |
281 | * Descriptors | |
282 | */ | |
283 | ||
284 | /* Frame descripter */ | |
285 | struct FDesc { | |
286 | volatile __u32 FDNext; | |
287 | volatile __u32 FDSystem; | |
288 | volatile __u32 FDStat; | |
289 | volatile __u32 FDCtl; | |
290 | }; | |
291 | ||
292 | /* Buffer descripter */ | |
293 | struct BDesc { | |
294 | volatile __u32 BuffData; | |
295 | volatile __u32 BDCtl; | |
296 | }; | |
297 | ||
298 | #define FD_ALIGN 16 | |
299 | ||
25985edc | 300 | /* Frame Descripter bit assign ---------------------------------------------- */ |
7f225b42 AN |
301 | #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */ |
302 | #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */ | |
303 | #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */ | |
1da177e4 | 304 | #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */ |
7f225b42 AN |
305 | #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */ |
306 | #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */ | |
1da177e4 LT |
307 | #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */ |
308 | #define FD_FrmOpt_Packing 0x04000000 /* Rx only */ | |
7f225b42 AN |
309 | #define FD_CownsFD 0x80000000 /* FD Controller owner bit */ |
310 | #define FD_Next_EOL 0x00000001 /* FD EOL indicator */ | |
311 | #define FD_BDCnt_SHIFT 16 | |
1da177e4 | 312 | |
25985edc LDM |
313 | /* Buffer Descripter bit assign --------------------------------------------- */ |
314 | #define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */ | |
7f225b42 AN |
315 | #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */ |
316 | #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */ | |
317 | #define BD_CownsBD 0x80000000 /* BD Controller owner bit */ | |
318 | #define BD_RxBDID_SHIFT 16 | |
1da177e4 LT |
319 | #define BD_RxBDSeqN_SHIFT 24 |
320 | ||
321 | ||
322 | /* Some useful constants. */ | |
1da177e4 | 323 | |
a02b7b7a | 324 | #define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \ |
eea221ce AN |
325 | Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \ |
326 | Tx_En) /* maybe 0x7b01 */ | |
297713de | 327 | /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */ |
1da177e4 | 328 | #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \ |
297713de | 329 | | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */ |
1da177e4 | 330 | #define INT_EN_CMD (Int_NRAbtEn | \ |
eea221ce | 331 | Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \ |
1da177e4 LT |
332 | Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \ |
333 | Int_STargAbtEn | \ | |
334 | Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/ | |
eea221ce | 335 | #define DMA_CTL_CMD DMA_BURST_SIZE |
c6686fe3 | 336 | #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF) |
1da177e4 LT |
337 | |
338 | /* Tuning parameters */ | |
339 | #define DMA_BURST_SIZE 32 | |
340 | #define TX_THRESHOLD 1024 | |
7f225b42 AN |
341 | /* used threshold with packet max byte for low pci transfer ability.*/ |
342 | #define TX_THRESHOLD_MAX 1536 | |
25985edc | 343 | /* setting threshold max value when overrun error occurred this count. */ |
7f225b42 | 344 | #define TX_THRESHOLD_KEEP_LIMIT 10 |
1da177e4 | 345 | |
eea221ce | 346 | /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */ |
eea221ce AN |
347 | #define FD_PAGE_NUM 4 |
348 | #define RX_BUF_NUM 128 /* < 256 */ | |
349 | #define RX_FD_NUM 256 /* >= 32 */ | |
350 | #define TX_FD_NUM 128 | |
351 | #if RX_CTL_CMD & Rx_LongEn | |
352 | #define RX_BUF_SIZE PAGE_SIZE | |
353 | #elif RX_CTL_CMD & Rx_StripCRC | |
82a9928d AN |
354 | #define RX_BUF_SIZE \ |
355 | L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN) | |
eea221ce | 356 | #else |
82a9928d AN |
357 | #define RX_BUF_SIZE \ |
358 | L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN) | |
eea221ce | 359 | #endif |
eea221ce AN |
360 | #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */ |
361 | #define NAPI_WEIGHT 16 | |
1da177e4 LT |
362 | |
363 | struct TxFD { | |
364 | struct FDesc fd; | |
365 | struct BDesc bd; | |
366 | struct BDesc unused; | |
367 | }; | |
368 | ||
369 | struct RxFD { | |
370 | struct FDesc fd; | |
371 | struct BDesc bd[0]; /* variable length */ | |
372 | }; | |
373 | ||
374 | struct FrFD { | |
375 | struct FDesc fd; | |
eea221ce | 376 | struct BDesc bd[RX_BUF_NUM]; |
1da177e4 LT |
377 | }; |
378 | ||
379 | ||
22adf7e5 AN |
380 | #define tc_readl(addr) ioread32(addr) |
381 | #define tc_writel(d, addr) iowrite32(d, addr) | |
1da177e4 | 382 | |
eea221ce AN |
383 | #define TC35815_TX_TIMEOUT msecs_to_jiffies(400) |
384 | ||
c6686fe3 | 385 | /* Information that need to be kept for each controller. */ |
1da177e4 | 386 | struct tc35815_local { |
eea221ce | 387 | struct pci_dev *pci_dev; |
1da177e4 | 388 | |
bea3348e SH |
389 | struct net_device *dev; |
390 | struct napi_struct napi; | |
391 | ||
1da177e4 | 392 | /* statistics */ |
1da177e4 LT |
393 | struct { |
394 | int max_tx_qlen; | |
395 | int tx_ints; | |
396 | int rx_ints; | |
7f225b42 | 397 | int tx_underrun; |
1da177e4 LT |
398 | } lstats; |
399 | ||
eea221ce AN |
400 | /* Tx control lock. This protects the transmit buffer ring |
401 | * state along with the "tx full" state of the driver. This | |
402 | * means all netif_queue flow control actions are protected | |
403 | * by this lock as well. | |
404 | */ | |
405 | spinlock_t lock; | |
dee7399c | 406 | spinlock_t rx_lock; |
eea221ce | 407 | |
298cf9be | 408 | struct mii_bus *mii_bus; |
c6686fe3 AN |
409 | struct phy_device *phy_dev; |
410 | int duplex; | |
411 | int speed; | |
412 | int link; | |
413 | struct work_struct restart_work; | |
1da177e4 LT |
414 | |
415 | /* | |
416 | * Transmitting: Batch Mode. | |
417 | * 1 BD in 1 TxFD. | |
a02b7b7a | 418 | * Receiving: Non-Packing Mode. |
eea221ce AN |
419 | * 1 circular FD for Free Buffer List. |
420 | * RX_BUF_NUM BD in Free Buffer FD. | |
421 | * One Free Buffer BD has ETH_FRAME_LEN data buffer. | |
1da177e4 | 422 | */ |
7f225b42 | 423 | void *fd_buf; /* for TxFD, RxFD, FrFD */ |
eea221ce | 424 | dma_addr_t fd_buf_dma; |
1da177e4 | 425 | struct TxFD *tfd_base; |
eea221ce AN |
426 | unsigned int tfd_start; |
427 | unsigned int tfd_end; | |
1da177e4 LT |
428 | struct RxFD *rfd_base; |
429 | struct RxFD *rfd_limit; | |
430 | struct RxFD *rfd_cur; | |
431 | struct FrFD *fbl_ptr; | |
eea221ce AN |
432 | unsigned int fbl_count; |
433 | struct { | |
434 | struct sk_buff *skb; | |
435 | dma_addr_t skb_dma; | |
436 | } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM]; | |
eea221ce | 437 | u32 msg_enable; |
c6686fe3 | 438 | enum tc35815_chiptype chiptype; |
1da177e4 LT |
439 | }; |
440 | ||
eea221ce AN |
441 | static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt) |
442 | { | |
443 | return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf); | |
444 | } | |
445 | #ifdef DEBUG | |
446 | static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus) | |
447 | { | |
448 | return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma)); | |
449 | } | |
450 | #endif | |
eea221ce AN |
451 | static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev, |
452 | struct pci_dev *hwdev, | |
453 | dma_addr_t *dma_handle) | |
454 | { | |
455 | struct sk_buff *skb; | |
456 | skb = dev_alloc_skb(RX_BUF_SIZE); | |
457 | if (!skb) | |
458 | return NULL; | |
eea221ce AN |
459 | *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE, |
460 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 461 | if (pci_dma_mapping_error(hwdev, *dma_handle)) { |
eea221ce AN |
462 | dev_kfree_skb_any(skb); |
463 | return NULL; | |
464 | } | |
465 | skb_reserve(skb, 2); /* make IP header 4byte aligned */ | |
466 | return skb; | |
467 | } | |
468 | ||
469 | static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle) | |
470 | { | |
471 | pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE, | |
472 | PCI_DMA_FROMDEVICE); | |
473 | dev_kfree_skb_any(skb); | |
474 | } | |
1da177e4 | 475 | |
eea221ce | 476 | /* Index to functions, as function prototypes. */ |
1da177e4 LT |
477 | |
478 | static int tc35815_open(struct net_device *dev); | |
479 | static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev); | |
eea221ce | 480 | static irqreturn_t tc35815_interrupt(int irq, void *dev_id); |
eea221ce | 481 | static int tc35815_rx(struct net_device *dev, int limit); |
bea3348e | 482 | static int tc35815_poll(struct napi_struct *napi, int budget); |
1da177e4 LT |
483 | static void tc35815_txdone(struct net_device *dev); |
484 | static int tc35815_close(struct net_device *dev); | |
485 | static struct net_device_stats *tc35815_get_stats(struct net_device *dev); | |
486 | static void tc35815_set_multicast_list(struct net_device *dev); | |
7f225b42 | 487 | static void tc35815_tx_timeout(struct net_device *dev); |
eea221ce AN |
488 | static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
489 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
490 | static void tc35815_poll_controller(struct net_device *dev); | |
491 | #endif | |
492 | static const struct ethtool_ops tc35815_ethtool_ops; | |
1da177e4 | 493 | |
eea221ce | 494 | /* Example routines you must write ;->. */ |
7f225b42 AN |
495 | static void tc35815_chip_reset(struct net_device *dev); |
496 | static void tc35815_chip_init(struct net_device *dev); | |
1da177e4 | 497 | |
eea221ce AN |
498 | #ifdef DEBUG |
499 | static void panic_queues(struct net_device *dev); | |
500 | #endif | |
1da177e4 | 501 | |
c6686fe3 AN |
502 | static void tc35815_restart_work(struct work_struct *work); |
503 | ||
504 | static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum) | |
505 | { | |
506 | struct net_device *dev = bus->priv; | |
507 | struct tc35815_regs __iomem *tr = | |
508 | (struct tc35815_regs __iomem *)dev->base_addr; | |
c60a5cf7 | 509 | unsigned long timeout = jiffies + HZ; |
c6686fe3 AN |
510 | |
511 | tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA); | |
c60a5cf7 | 512 | udelay(12); /* it takes 32 x 400ns at least */ |
c6686fe3 AN |
513 | while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { |
514 | if (time_after(jiffies, timeout)) | |
515 | return -EIO; | |
516 | cpu_relax(); | |
517 | } | |
518 | return tc_readl(&tr->MD_Data) & 0xffff; | |
519 | } | |
520 | ||
521 | static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val) | |
522 | { | |
523 | struct net_device *dev = bus->priv; | |
524 | struct tc35815_regs __iomem *tr = | |
525 | (struct tc35815_regs __iomem *)dev->base_addr; | |
c60a5cf7 | 526 | unsigned long timeout = jiffies + HZ; |
c6686fe3 AN |
527 | |
528 | tc_writel(val, &tr->MD_Data); | |
529 | tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f), | |
530 | &tr->MD_CA); | |
c60a5cf7 | 531 | udelay(12); /* it takes 32 x 400ns at least */ |
c6686fe3 AN |
532 | while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { |
533 | if (time_after(jiffies, timeout)) | |
534 | return -EIO; | |
535 | cpu_relax(); | |
536 | } | |
537 | return 0; | |
538 | } | |
539 | ||
540 | static void tc_handle_link_change(struct net_device *dev) | |
541 | { | |
542 | struct tc35815_local *lp = netdev_priv(dev); | |
543 | struct phy_device *phydev = lp->phy_dev; | |
544 | unsigned long flags; | |
545 | int status_change = 0; | |
546 | ||
547 | spin_lock_irqsave(&lp->lock, flags); | |
548 | if (phydev->link && | |
549 | (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) { | |
550 | struct tc35815_regs __iomem *tr = | |
551 | (struct tc35815_regs __iomem *)dev->base_addr; | |
552 | u32 reg; | |
553 | ||
554 | reg = tc_readl(&tr->MAC_Ctl); | |
555 | reg |= MAC_HaltReq; | |
556 | tc_writel(reg, &tr->MAC_Ctl); | |
557 | if (phydev->duplex == DUPLEX_FULL) | |
558 | reg |= MAC_FullDup; | |
559 | else | |
560 | reg &= ~MAC_FullDup; | |
561 | tc_writel(reg, &tr->MAC_Ctl); | |
562 | reg &= ~MAC_HaltReq; | |
563 | tc_writel(reg, &tr->MAC_Ctl); | |
564 | ||
565 | /* | |
566 | * TX4939 PCFG.SPEEDn bit will be changed on | |
567 | * NETDEV_CHANGE event. | |
568 | */ | |
c6686fe3 AN |
569 | /* |
570 | * WORKAROUND: enable LostCrS only if half duplex | |
571 | * operation. | |
572 | * (TX4939 does not have EnLCarr) | |
573 | */ | |
574 | if (phydev->duplex == DUPLEX_HALF && | |
575 | lp->chiptype != TC35815_TX4939) | |
576 | tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr, | |
577 | &tr->Tx_Ctl); | |
c6686fe3 AN |
578 | |
579 | lp->speed = phydev->speed; | |
580 | lp->duplex = phydev->duplex; | |
581 | status_change = 1; | |
582 | } | |
583 | ||
584 | if (phydev->link != lp->link) { | |
585 | if (phydev->link) { | |
c6686fe3 AN |
586 | /* delayed promiscuous enabling */ |
587 | if (dev->flags & IFF_PROMISC) | |
588 | tc35815_set_multicast_list(dev); | |
c6686fe3 AN |
589 | } else { |
590 | lp->speed = 0; | |
591 | lp->duplex = -1; | |
592 | } | |
593 | lp->link = phydev->link; | |
594 | ||
595 | status_change = 1; | |
596 | } | |
597 | spin_unlock_irqrestore(&lp->lock, flags); | |
598 | ||
599 | if (status_change && netif_msg_link(lp)) { | |
600 | phy_print_status(phydev); | |
72903831 JP |
601 | pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n", |
602 | dev->name, | |
603 | phy_read(phydev, MII_BMCR), | |
604 | phy_read(phydev, MII_BMSR), | |
605 | phy_read(phydev, MII_LPA)); | |
c6686fe3 AN |
606 | } |
607 | } | |
608 | ||
609 | static int tc_mii_probe(struct net_device *dev) | |
610 | { | |
611 | struct tc35815_local *lp = netdev_priv(dev); | |
612 | struct phy_device *phydev = NULL; | |
613 | int phy_addr; | |
614 | u32 dropmask; | |
615 | ||
616 | /* find the first phy */ | |
617 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
298cf9be | 618 | if (lp->mii_bus->phy_map[phy_addr]) { |
c6686fe3 AN |
619 | if (phydev) { |
620 | printk(KERN_ERR "%s: multiple PHYs found\n", | |
621 | dev->name); | |
622 | return -EINVAL; | |
623 | } | |
298cf9be | 624 | phydev = lp->mii_bus->phy_map[phy_addr]; |
c6686fe3 AN |
625 | break; |
626 | } | |
627 | } | |
628 | ||
629 | if (!phydev) { | |
630 | printk(KERN_ERR "%s: no PHY found\n", dev->name); | |
631 | return -ENODEV; | |
632 | } | |
633 | ||
634 | /* attach the mac to the phy */ | |
db1d7bf7 | 635 | phydev = phy_connect(dev, dev_name(&phydev->dev), |
c6686fe3 AN |
636 | &tc_handle_link_change, 0, |
637 | lp->chiptype == TC35815_TX4939 ? | |
638 | PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII); | |
639 | if (IS_ERR(phydev)) { | |
640 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
641 | return PTR_ERR(phydev); | |
642 | } | |
643 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
644 | "(mii_bus:phy_addr=%s, id=%x)\n", | |
db1d7bf7 | 645 | dev->name, phydev->drv->name, dev_name(&phydev->dev), |
c6686fe3 AN |
646 | phydev->phy_id); |
647 | ||
648 | /* mask with MAC supported features */ | |
649 | phydev->supported &= PHY_BASIC_FEATURES; | |
650 | dropmask = 0; | |
651 | if (options.speed == 10) | |
652 | dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full; | |
653 | else if (options.speed == 100) | |
654 | dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full; | |
655 | if (options.duplex == 1) | |
656 | dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full; | |
657 | else if (options.duplex == 2) | |
658 | dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half; | |
659 | phydev->supported &= ~dropmask; | |
660 | phydev->advertising = phydev->supported; | |
661 | ||
662 | lp->link = 0; | |
663 | lp->speed = 0; | |
664 | lp->duplex = -1; | |
665 | lp->phy_dev = phydev; | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
670 | static int tc_mii_init(struct net_device *dev) | |
671 | { | |
672 | struct tc35815_local *lp = netdev_priv(dev); | |
673 | int err; | |
674 | int i; | |
675 | ||
298cf9be LB |
676 | lp->mii_bus = mdiobus_alloc(); |
677 | if (lp->mii_bus == NULL) { | |
c6686fe3 AN |
678 | err = -ENOMEM; |
679 | goto err_out; | |
680 | } | |
681 | ||
298cf9be LB |
682 | lp->mii_bus->name = "tc35815_mii_bus"; |
683 | lp->mii_bus->read = tc_mdio_read; | |
684 | lp->mii_bus->write = tc_mdio_write; | |
685 | snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", | |
686 | (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn); | |
687 | lp->mii_bus->priv = dev; | |
688 | lp->mii_bus->parent = &lp->pci_dev->dev; | |
689 | lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
690 | if (!lp->mii_bus->irq) { | |
691 | err = -ENOMEM; | |
692 | goto err_out_free_mii_bus; | |
693 | } | |
694 | ||
c6686fe3 | 695 | for (i = 0; i < PHY_MAX_ADDR; i++) |
298cf9be | 696 | lp->mii_bus->irq[i] = PHY_POLL; |
c6686fe3 | 697 | |
298cf9be | 698 | err = mdiobus_register(lp->mii_bus); |
c6686fe3 AN |
699 | if (err) |
700 | goto err_out_free_mdio_irq; | |
701 | err = tc_mii_probe(dev); | |
702 | if (err) | |
703 | goto err_out_unregister_bus; | |
704 | return 0; | |
705 | ||
706 | err_out_unregister_bus: | |
298cf9be | 707 | mdiobus_unregister(lp->mii_bus); |
c6686fe3 | 708 | err_out_free_mdio_irq: |
298cf9be | 709 | kfree(lp->mii_bus->irq); |
51cf756c | 710 | err_out_free_mii_bus: |
298cf9be | 711 | mdiobus_free(lp->mii_bus); |
c6686fe3 AN |
712 | err_out: |
713 | return err; | |
714 | } | |
1da177e4 | 715 | |
bd43da8f AN |
716 | #ifdef CONFIG_CPU_TX49XX |
717 | /* | |
718 | * Find a platform_device providing a MAC address. The platform code | |
719 | * should provide a "tc35815-mac" device with a MAC address in its | |
720 | * platform_data. | |
721 | */ | |
722 | static int __devinit tc35815_mac_match(struct device *dev, void *data) | |
723 | { | |
724 | struct platform_device *plat_dev = to_platform_device(dev); | |
725 | struct pci_dev *pci_dev = data; | |
06675e6f | 726 | unsigned int id = pci_dev->irq; |
bd43da8f AN |
727 | return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id; |
728 | } | |
729 | ||
730 | static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev) | |
731 | { | |
ee79b7fb | 732 | struct tc35815_local *lp = netdev_priv(dev); |
bd43da8f AN |
733 | struct device *pd = bus_find_device(&platform_bus_type, NULL, |
734 | lp->pci_dev, tc35815_mac_match); | |
735 | if (pd) { | |
736 | if (pd->platform_data) | |
737 | memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN); | |
738 | put_device(pd); | |
739 | return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV; | |
740 | } | |
741 | return -ENODEV; | |
742 | } | |
743 | #else | |
308a9068 | 744 | static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev) |
bd43da8f AN |
745 | { |
746 | return -ENODEV; | |
747 | } | |
748 | #endif | |
749 | ||
7f225b42 | 750 | static int __devinit tc35815_init_dev_addr(struct net_device *dev) |
eea221ce AN |
751 | { |
752 | struct tc35815_regs __iomem *tr = | |
753 | (struct tc35815_regs __iomem *)dev->base_addr; | |
754 | int i; | |
755 | ||
eea221ce AN |
756 | while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) |
757 | ; | |
758 | for (i = 0; i < 6; i += 2) { | |
759 | unsigned short data; | |
760 | tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl); | |
761 | while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) | |
762 | ; | |
763 | data = tc_readl(&tr->PROM_Data); | |
764 | dev->dev_addr[i] = data & 0xff; | |
765 | dev->dev_addr[i+1] = data >> 8; | |
766 | } | |
bd43da8f AN |
767 | if (!is_valid_ether_addr(dev->dev_addr)) |
768 | return tc35815_read_plat_dev_addr(dev); | |
769 | return 0; | |
eea221ce | 770 | } |
1da177e4 | 771 | |
5a1c28b3 AB |
772 | static const struct net_device_ops tc35815_netdev_ops = { |
773 | .ndo_open = tc35815_open, | |
774 | .ndo_stop = tc35815_close, | |
775 | .ndo_start_xmit = tc35815_send_packet, | |
776 | .ndo_get_stats = tc35815_get_stats, | |
777 | .ndo_set_multicast_list = tc35815_set_multicast_list, | |
778 | .ndo_tx_timeout = tc35815_tx_timeout, | |
779 | .ndo_do_ioctl = tc35815_ioctl, | |
780 | .ndo_validate_addr = eth_validate_addr, | |
781 | .ndo_change_mtu = eth_change_mtu, | |
782 | .ndo_set_mac_address = eth_mac_addr, | |
783 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
784 | .ndo_poll_controller = tc35815_poll_controller, | |
785 | #endif | |
786 | }; | |
787 | ||
7f225b42 AN |
788 | static int __devinit tc35815_init_one(struct pci_dev *pdev, |
789 | const struct pci_device_id *ent) | |
1da177e4 | 790 | { |
eea221ce AN |
791 | void __iomem *ioaddr = NULL; |
792 | struct net_device *dev; | |
793 | struct tc35815_local *lp; | |
794 | int rc; | |
eea221ce AN |
795 | |
796 | static int printed_version; | |
797 | if (!printed_version++) { | |
798 | printk(version); | |
799 | dev_printk(KERN_DEBUG, &pdev->dev, | |
c6686fe3 AN |
800 | "speed:%d duplex:%d\n", |
801 | options.speed, options.duplex); | |
eea221ce AN |
802 | } |
803 | ||
804 | if (!pdev->irq) { | |
805 | dev_warn(&pdev->dev, "no IRQ assigned.\n"); | |
806 | return -ENODEV; | |
807 | } | |
1da177e4 | 808 | |
eea221ce | 809 | /* dev zeroed in alloc_etherdev */ |
7f225b42 | 810 | dev = alloc_etherdev(sizeof(*lp)); |
eea221ce AN |
811 | if (dev == NULL) { |
812 | dev_err(&pdev->dev, "unable to alloc new ethernet\n"); | |
813 | return -ENOMEM; | |
814 | } | |
eea221ce | 815 | SET_NETDEV_DEV(dev, &pdev->dev); |
ee79b7fb | 816 | lp = netdev_priv(dev); |
bea3348e | 817 | lp->dev = dev; |
1da177e4 | 818 | |
eea221ce | 819 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ |
22adf7e5 | 820 | rc = pcim_enable_device(pdev); |
eea221ce AN |
821 | if (rc) |
822 | goto err_out; | |
22adf7e5 | 823 | rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME); |
eea221ce | 824 | if (rc) |
1da177e4 | 825 | goto err_out; |
22adf7e5 AN |
826 | pci_set_master(pdev); |
827 | ioaddr = pcim_iomap_table(pdev)[1]; | |
1da177e4 | 828 | |
eea221ce | 829 | /* Initialize the device structure. */ |
5a1c28b3 | 830 | dev->netdev_ops = &tc35815_netdev_ops; |
eea221ce | 831 | dev->ethtool_ops = &tc35815_ethtool_ops; |
eea221ce | 832 | dev->watchdog_timeo = TC35815_TX_TIMEOUT; |
bea3348e | 833 | netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT); |
1da177e4 | 834 | |
eea221ce | 835 | dev->irq = pdev->irq; |
7f225b42 | 836 | dev->base_addr = (unsigned long)ioaddr; |
1da177e4 | 837 | |
c6686fe3 | 838 | INIT_WORK(&lp->restart_work, tc35815_restart_work); |
eea221ce | 839 | spin_lock_init(&lp->lock); |
dee7399c | 840 | spin_lock_init(&lp->rx_lock); |
eea221ce | 841 | lp->pci_dev = pdev; |
c6686fe3 | 842 | lp->chiptype = ent->driver_data; |
1da177e4 | 843 | |
eea221ce AN |
844 | lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK; |
845 | pci_set_drvdata(pdev, dev); | |
1da177e4 | 846 | |
eea221ce | 847 | /* Soft reset the chip. */ |
1da177e4 LT |
848 | tc35815_chip_reset(dev); |
849 | ||
eea221ce | 850 | /* Retrieve the ethernet address. */ |
bd43da8f AN |
851 | if (tc35815_init_dev_addr(dev)) { |
852 | dev_warn(&pdev->dev, "not valid ether addr\n"); | |
853 | random_ether_addr(dev->dev_addr); | |
854 | } | |
eea221ce | 855 | |
7f225b42 | 856 | rc = register_netdev(dev); |
eea221ce | 857 | if (rc) |
1e2cfeef | 858 | goto err_out; |
eea221ce AN |
859 | |
860 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
e174961c | 861 | printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n", |
eea221ce | 862 | dev->name, |
c6686fe3 | 863 | chip_info[ent->driver_data].name, |
eea221ce | 864 | dev->base_addr, |
e174961c | 865 | dev->dev_addr, |
eea221ce AN |
866 | dev->irq); |
867 | ||
c6686fe3 AN |
868 | rc = tc_mii_init(dev); |
869 | if (rc) | |
870 | goto err_out_unregister; | |
1da177e4 | 871 | |
eea221ce | 872 | return 0; |
1da177e4 | 873 | |
c6686fe3 AN |
874 | err_out_unregister: |
875 | unregister_netdev(dev); | |
eea221ce | 876 | err_out: |
7f225b42 | 877 | free_netdev(dev); |
eea221ce AN |
878 | return rc; |
879 | } | |
1da177e4 | 880 | |
1da177e4 | 881 | |
7f225b42 | 882 | static void __devexit tc35815_remove_one(struct pci_dev *pdev) |
eea221ce | 883 | { |
7f225b42 | 884 | struct net_device *dev = pci_get_drvdata(pdev); |
c6686fe3 | 885 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 | 886 | |
c6686fe3 | 887 | phy_disconnect(lp->phy_dev); |
298cf9be LB |
888 | mdiobus_unregister(lp->mii_bus); |
889 | kfree(lp->mii_bus->irq); | |
890 | mdiobus_free(lp->mii_bus); | |
7f225b42 AN |
891 | unregister_netdev(dev); |
892 | free_netdev(dev); | |
893 | pci_set_drvdata(pdev, NULL); | |
1da177e4 LT |
894 | } |
895 | ||
1da177e4 LT |
896 | static int |
897 | tc35815_init_queues(struct net_device *dev) | |
898 | { | |
ee79b7fb | 899 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
900 | int i; |
901 | unsigned long fd_addr; | |
902 | ||
903 | if (!lp->fd_buf) { | |
eea221ce AN |
904 | BUG_ON(sizeof(struct FDesc) + |
905 | sizeof(struct BDesc) * RX_BUF_NUM + | |
906 | sizeof(struct FDesc) * RX_FD_NUM + | |
907 | sizeof(struct TxFD) * TX_FD_NUM > | |
908 | PAGE_SIZE * FD_PAGE_NUM); | |
1da177e4 | 909 | |
7f225b42 AN |
910 | lp->fd_buf = pci_alloc_consistent(lp->pci_dev, |
911 | PAGE_SIZE * FD_PAGE_NUM, | |
912 | &lp->fd_buf_dma); | |
913 | if (!lp->fd_buf) | |
1da177e4 | 914 | return -ENOMEM; |
eea221ce | 915 | for (i = 0; i < RX_BUF_NUM; i++) { |
eea221ce AN |
916 | lp->rx_skbs[i].skb = |
917 | alloc_rxbuf_skb(dev, lp->pci_dev, | |
918 | &lp->rx_skbs[i].skb_dma); | |
919 | if (!lp->rx_skbs[i].skb) { | |
920 | while (--i >= 0) { | |
921 | free_rxbuf_skb(lp->pci_dev, | |
922 | lp->rx_skbs[i].skb, | |
923 | lp->rx_skbs[i].skb_dma); | |
924 | lp->rx_skbs[i].skb = NULL; | |
925 | } | |
926 | pci_free_consistent(lp->pci_dev, | |
927 | PAGE_SIZE * FD_PAGE_NUM, | |
928 | lp->fd_buf, | |
929 | lp->fd_buf_dma); | |
930 | lp->fd_buf = NULL; | |
1da177e4 LT |
931 | return -ENOMEM; |
932 | } | |
1da177e4 | 933 | } |
eea221ce AN |
934 | printk(KERN_DEBUG "%s: FD buf %p DataBuf", |
935 | dev->name, lp->fd_buf); | |
eea221ce | 936 | printk("\n"); |
1da177e4 | 937 | } else { |
7f225b42 AN |
938 | for (i = 0; i < FD_PAGE_NUM; i++) |
939 | clear_page((void *)((unsigned long)lp->fd_buf + | |
940 | i * PAGE_SIZE)); | |
1da177e4 | 941 | } |
1da177e4 | 942 | fd_addr = (unsigned long)lp->fd_buf; |
1da177e4 LT |
943 | |
944 | /* Free Descriptors (for Receive) */ | |
945 | lp->rfd_base = (struct RxFD *)fd_addr; | |
946 | fd_addr += sizeof(struct RxFD) * RX_FD_NUM; | |
7f225b42 | 947 | for (i = 0; i < RX_FD_NUM; i++) |
1da177e4 | 948 | lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD); |
1da177e4 | 949 | lp->rfd_cur = lp->rfd_base; |
eea221ce | 950 | lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1); |
1da177e4 LT |
951 | |
952 | /* Transmit Descriptors */ | |
953 | lp->tfd_base = (struct TxFD *)fd_addr; | |
954 | fd_addr += sizeof(struct TxFD) * TX_FD_NUM; | |
955 | for (i = 0; i < TX_FD_NUM; i++) { | |
eea221ce AN |
956 | lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1])); |
957 | lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); | |
1da177e4 LT |
958 | lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0); |
959 | } | |
eea221ce | 960 | lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0])); |
1da177e4 LT |
961 | lp->tfd_start = 0; |
962 | lp->tfd_end = 0; | |
963 | ||
964 | /* Buffer List (for Receive) */ | |
965 | lp->fbl_ptr = (struct FrFD *)fd_addr; | |
eea221ce AN |
966 | lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr)); |
967 | lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD); | |
eea221ce AN |
968 | /* |
969 | * move all allocated skbs to head of rx_skbs[] array. | |
970 | * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in | |
971 | * tc35815_rx() had failed. | |
972 | */ | |
973 | lp->fbl_count = 0; | |
974 | for (i = 0; i < RX_BUF_NUM; i++) { | |
975 | if (lp->rx_skbs[i].skb) { | |
976 | if (i != lp->fbl_count) { | |
977 | lp->rx_skbs[lp->fbl_count].skb = | |
978 | lp->rx_skbs[i].skb; | |
979 | lp->rx_skbs[lp->fbl_count].skb_dma = | |
980 | lp->rx_skbs[i].skb_dma; | |
981 | } | |
982 | lp->fbl_count++; | |
983 | } | |
984 | } | |
eea221ce | 985 | for (i = 0; i < RX_BUF_NUM; i++) { |
eea221ce AN |
986 | if (i >= lp->fbl_count) { |
987 | lp->fbl_ptr->bd[i].BuffData = 0; | |
988 | lp->fbl_ptr->bd[i].BDCtl = 0; | |
989 | continue; | |
990 | } | |
991 | lp->fbl_ptr->bd[i].BuffData = | |
992 | cpu_to_le32(lp->rx_skbs[i].skb_dma); | |
1da177e4 LT |
993 | /* BDID is index of FrFD.bd[] */ |
994 | lp->fbl_ptr->bd[i].BDCtl = | |
eea221ce AN |
995 | cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) | |
996 | RX_BUF_SIZE); | |
1da177e4 | 997 | } |
1da177e4 | 998 | |
eea221ce AN |
999 | printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n", |
1000 | dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr); | |
1da177e4 LT |
1001 | return 0; |
1002 | } | |
1003 | ||
1004 | static void | |
1005 | tc35815_clear_queues(struct net_device *dev) | |
1006 | { | |
ee79b7fb | 1007 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1008 | int i; |
1009 | ||
1010 | for (i = 0; i < TX_FD_NUM; i++) { | |
eea221ce AN |
1011 | u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); |
1012 | struct sk_buff *skb = | |
1013 | fdsystem != 0xffffffff ? | |
1014 | lp->tx_skbs[fdsystem].skb : NULL; | |
1015 | #ifdef DEBUG | |
1016 | if (lp->tx_skbs[i].skb != skb) { | |
1017 | printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); | |
1018 | panic_queues(dev); | |
1019 | } | |
1020 | #else | |
1021 | BUG_ON(lp->tx_skbs[i].skb != skb); | |
1022 | #endif | |
1023 | if (skb) { | |
1024 | pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); | |
1025 | lp->tx_skbs[i].skb = NULL; | |
1026 | lp->tx_skbs[i].skb_dma = 0; | |
1da177e4 | 1027 | dev_kfree_skb_any(skb); |
eea221ce AN |
1028 | } |
1029 | lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); | |
1da177e4 LT |
1030 | } |
1031 | ||
1032 | tc35815_init_queues(dev); | |
1033 | } | |
1034 | ||
1035 | static void | |
1036 | tc35815_free_queues(struct net_device *dev) | |
1037 | { | |
ee79b7fb | 1038 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1039 | int i; |
1040 | ||
1041 | if (lp->tfd_base) { | |
1042 | for (i = 0; i < TX_FD_NUM; i++) { | |
eea221ce AN |
1043 | u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); |
1044 | struct sk_buff *skb = | |
1045 | fdsystem != 0xffffffff ? | |
1046 | lp->tx_skbs[fdsystem].skb : NULL; | |
1047 | #ifdef DEBUG | |
1048 | if (lp->tx_skbs[i].skb != skb) { | |
1049 | printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); | |
1050 | panic_queues(dev); | |
1051 | } | |
1052 | #else | |
1053 | BUG_ON(lp->tx_skbs[i].skb != skb); | |
1054 | #endif | |
1055 | if (skb) { | |
1056 | dev_kfree_skb(skb); | |
1057 | pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); | |
1058 | lp->tx_skbs[i].skb = NULL; | |
1059 | lp->tx_skbs[i].skb_dma = 0; | |
1060 | } | |
1061 | lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); | |
1da177e4 LT |
1062 | } |
1063 | } | |
1064 | ||
1da177e4 LT |
1065 | lp->rfd_base = NULL; |
1066 | lp->rfd_limit = NULL; | |
1067 | lp->rfd_cur = NULL; | |
1068 | lp->fbl_ptr = NULL; | |
1069 | ||
eea221ce | 1070 | for (i = 0; i < RX_BUF_NUM; i++) { |
eea221ce AN |
1071 | if (lp->rx_skbs[i].skb) { |
1072 | free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb, | |
1073 | lp->rx_skbs[i].skb_dma); | |
1074 | lp->rx_skbs[i].skb = NULL; | |
1075 | } | |
eea221ce AN |
1076 | } |
1077 | if (lp->fd_buf) { | |
1078 | pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM, | |
1079 | lp->fd_buf, lp->fd_buf_dma); | |
1080 | lp->fd_buf = NULL; | |
1da177e4 | 1081 | } |
1da177e4 LT |
1082 | } |
1083 | ||
1084 | static void | |
1085 | dump_txfd(struct TxFD *fd) | |
1086 | { | |
1087 | printk("TxFD(%p): %08x %08x %08x %08x\n", fd, | |
1088 | le32_to_cpu(fd->fd.FDNext), | |
1089 | le32_to_cpu(fd->fd.FDSystem), | |
1090 | le32_to_cpu(fd->fd.FDStat), | |
1091 | le32_to_cpu(fd->fd.FDCtl)); | |
1092 | printk("BD: "); | |
1093 | printk(" %08x %08x", | |
1094 | le32_to_cpu(fd->bd.BuffData), | |
1095 | le32_to_cpu(fd->bd.BDCtl)); | |
1096 | printk("\n"); | |
1097 | } | |
1098 | ||
1099 | static int | |
1100 | dump_rxfd(struct RxFD *fd) | |
1101 | { | |
1102 | int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; | |
1103 | if (bd_count > 8) | |
1104 | bd_count = 8; | |
1105 | printk("RxFD(%p): %08x %08x %08x %08x\n", fd, | |
1106 | le32_to_cpu(fd->fd.FDNext), | |
1107 | le32_to_cpu(fd->fd.FDSystem), | |
1108 | le32_to_cpu(fd->fd.FDStat), | |
1109 | le32_to_cpu(fd->fd.FDCtl)); | |
1110 | if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD) | |
7f225b42 | 1111 | return 0; |
1da177e4 LT |
1112 | printk("BD: "); |
1113 | for (i = 0; i < bd_count; i++) | |
1114 | printk(" %08x %08x", | |
1115 | le32_to_cpu(fd->bd[i].BuffData), | |
1116 | le32_to_cpu(fd->bd[i].BDCtl)); | |
1117 | printk("\n"); | |
1118 | return bd_count; | |
1119 | } | |
1120 | ||
a02b7b7a | 1121 | #ifdef DEBUG |
1da177e4 LT |
1122 | static void |
1123 | dump_frfd(struct FrFD *fd) | |
1124 | { | |
1125 | int i; | |
1126 | printk("FrFD(%p): %08x %08x %08x %08x\n", fd, | |
1127 | le32_to_cpu(fd->fd.FDNext), | |
1128 | le32_to_cpu(fd->fd.FDSystem), | |
1129 | le32_to_cpu(fd->fd.FDStat), | |
1130 | le32_to_cpu(fd->fd.FDCtl)); | |
1131 | printk("BD: "); | |
eea221ce | 1132 | for (i = 0; i < RX_BUF_NUM; i++) |
1da177e4 LT |
1133 | printk(" %08x %08x", |
1134 | le32_to_cpu(fd->bd[i].BuffData), | |
1135 | le32_to_cpu(fd->bd[i].BDCtl)); | |
1136 | printk("\n"); | |
1137 | } | |
1138 | ||
1139 | static void | |
1140 | panic_queues(struct net_device *dev) | |
1141 | { | |
ee79b7fb | 1142 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1143 | int i; |
1144 | ||
eea221ce | 1145 | printk("TxFD base %p, start %u, end %u\n", |
1da177e4 LT |
1146 | lp->tfd_base, lp->tfd_start, lp->tfd_end); |
1147 | printk("RxFD base %p limit %p cur %p\n", | |
1148 | lp->rfd_base, lp->rfd_limit, lp->rfd_cur); | |
1149 | printk("FrFD %p\n", lp->fbl_ptr); | |
1150 | for (i = 0; i < TX_FD_NUM; i++) | |
1151 | dump_txfd(&lp->tfd_base[i]); | |
1152 | for (i = 0; i < RX_FD_NUM; i++) { | |
1153 | int bd_count = dump_rxfd(&lp->rfd_base[i]); | |
1154 | i += (bd_count + 1) / 2; /* skip BDs */ | |
1155 | } | |
1156 | dump_frfd(lp->fbl_ptr); | |
1157 | panic("%s: Illegal queue state.", dev->name); | |
1158 | } | |
1da177e4 LT |
1159 | #endif |
1160 | ||
958eb80b | 1161 | static void print_eth(const u8 *add) |
1da177e4 | 1162 | { |
958eb80b | 1163 | printk(KERN_DEBUG "print_eth(%p)\n", add); |
e174961c JB |
1164 | printk(KERN_DEBUG " %pM => %pM : %02x%02x\n", |
1165 | add + 6, add, add[12], add[13]); | |
1da177e4 LT |
1166 | } |
1167 | ||
eea221ce AN |
1168 | static int tc35815_tx_full(struct net_device *dev) |
1169 | { | |
ee79b7fb | 1170 | struct tc35815_local *lp = netdev_priv(dev); |
807540ba | 1171 | return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end; |
eea221ce AN |
1172 | } |
1173 | ||
1174 | static void tc35815_restart(struct net_device *dev) | |
1175 | { | |
ee79b7fb | 1176 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce | 1177 | |
c6686fe3 | 1178 | if (lp->phy_dev) { |
eea221ce | 1179 | int timeout; |
c6686fe3 AN |
1180 | |
1181 | phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET); | |
eea221ce AN |
1182 | timeout = 100; |
1183 | while (--timeout) { | |
c6686fe3 | 1184 | if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET)) |
eea221ce AN |
1185 | break; |
1186 | udelay(1); | |
1187 | } | |
1188 | if (!timeout) | |
1189 | printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name); | |
1190 | } | |
1191 | ||
dee7399c | 1192 | spin_lock_bh(&lp->rx_lock); |
c6686fe3 | 1193 | spin_lock_irq(&lp->lock); |
eea221ce AN |
1194 | tc35815_chip_reset(dev); |
1195 | tc35815_clear_queues(dev); | |
1196 | tc35815_chip_init(dev); | |
1197 | /* Reconfigure CAM again since tc35815_chip_init() initialize it. */ | |
1198 | tc35815_set_multicast_list(dev); | |
c6686fe3 | 1199 | spin_unlock_irq(&lp->lock); |
dee7399c | 1200 | spin_unlock_bh(&lp->rx_lock); |
c6686fe3 AN |
1201 | |
1202 | netif_wake_queue(dev); | |
eea221ce AN |
1203 | } |
1204 | ||
c6686fe3 AN |
1205 | static void tc35815_restart_work(struct work_struct *work) |
1206 | { | |
1207 | struct tc35815_local *lp = | |
1208 | container_of(work, struct tc35815_local, restart_work); | |
1209 | struct net_device *dev = lp->dev; | |
1210 | ||
1211 | tc35815_restart(dev); | |
1212 | } | |
1213 | ||
1214 | static void tc35815_schedule_restart(struct net_device *dev) | |
eea221ce | 1215 | { |
ee79b7fb | 1216 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1217 | struct tc35815_regs __iomem *tr = |
1218 | (struct tc35815_regs __iomem *)dev->base_addr; | |
dee7399c | 1219 | unsigned long flags; |
eea221ce | 1220 | |
c6686fe3 | 1221 | /* disable interrupts */ |
dee7399c | 1222 | spin_lock_irqsave(&lp->lock, flags); |
c6686fe3 AN |
1223 | tc_writel(0, &tr->Int_En); |
1224 | tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl); | |
1225 | schedule_work(&lp->restart_work); | |
dee7399c | 1226 | spin_unlock_irqrestore(&lp->lock, flags); |
c6686fe3 AN |
1227 | } |
1228 | ||
1229 | static void tc35815_tx_timeout(struct net_device *dev) | |
1230 | { | |
1231 | struct tc35815_regs __iomem *tr = | |
1232 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1233 | ||
eea221ce AN |
1234 | printk(KERN_WARNING "%s: transmit timed out, status %#x\n", |
1235 | dev->name, tc_readl(&tr->Tx_Stat)); | |
1236 | ||
1237 | /* Try to restart the adaptor. */ | |
c6686fe3 | 1238 | tc35815_schedule_restart(dev); |
c201abd9 | 1239 | dev->stats.tx_errors++; |
eea221ce AN |
1240 | } |
1241 | ||
1da177e4 | 1242 | /* |
c6686fe3 | 1243 | * Open/initialize the controller. This is called (in the current kernel) |
1da177e4 LT |
1244 | * sometime after booting when the 'ifconfig' program is run. |
1245 | * | |
1246 | * This routine should set everything up anew at each open, even | |
1247 | * registers that "should" only need to be set once at boot, so that | |
1248 | * there is non-reboot way to recover if something goes wrong. | |
1249 | */ | |
1250 | static int | |
1251 | tc35815_open(struct net_device *dev) | |
1252 | { | |
ee79b7fb | 1253 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce | 1254 | |
1da177e4 LT |
1255 | /* |
1256 | * This is used if the interrupt line can turned off (shared). | |
1257 | * See 3c503.c for an example of selecting the IRQ at config-time. | |
1258 | */ | |
a0607fd3 | 1259 | if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED, |
7f225b42 | 1260 | dev->name, dev)) |
1da177e4 | 1261 | return -EAGAIN; |
1da177e4 LT |
1262 | |
1263 | tc35815_chip_reset(dev); | |
1264 | ||
1265 | if (tc35815_init_queues(dev) != 0) { | |
1266 | free_irq(dev->irq, dev); | |
1267 | return -EAGAIN; | |
1268 | } | |
1269 | ||
bea3348e | 1270 | napi_enable(&lp->napi); |
bea3348e | 1271 | |
1da177e4 | 1272 | /* Reset the hardware here. Don't forget to set the station address. */ |
eea221ce | 1273 | spin_lock_irq(&lp->lock); |
1da177e4 | 1274 | tc35815_chip_init(dev); |
eea221ce | 1275 | spin_unlock_irq(&lp->lock); |
1da177e4 | 1276 | |
59524a37 | 1277 | netif_carrier_off(dev); |
c6686fe3 AN |
1278 | /* schedule a link state check */ |
1279 | phy_start(lp->phy_dev); | |
1280 | ||
eea221ce AN |
1281 | /* We are now ready to accept transmit requeusts from |
1282 | * the queueing layer of the networking. | |
1283 | */ | |
1da177e4 LT |
1284 | netif_start_queue(dev); |
1285 | ||
1286 | return 0; | |
1287 | } | |
1288 | ||
eea221ce AN |
1289 | /* This will only be invoked if your driver is _not_ in XOFF state. |
1290 | * What this means is that you need not check it, and that this | |
1291 | * invariant will hold if you make sure that the netif_*_queue() | |
1292 | * calls are done at the proper times. | |
1293 | */ | |
1294 | static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev) | |
1da177e4 | 1295 | { |
ee79b7fb | 1296 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce | 1297 | struct TxFD *txfd; |
1da177e4 LT |
1298 | unsigned long flags; |
1299 | ||
eea221ce AN |
1300 | /* If some error occurs while trying to transmit this |
1301 | * packet, you should return '1' from this function. | |
1302 | * In such a case you _may not_ do anything to the | |
1303 | * SKB, it is still owned by the network queueing | |
1304 | * layer when an error is returned. This means you | |
1305 | * may not modify any SKB fields, you may not free | |
1306 | * the SKB, etc. | |
1307 | */ | |
1308 | ||
1309 | /* This is the most common case for modern hardware. | |
1310 | * The spinlock protects this code from the TX complete | |
1311 | * hardware interrupt handler. Queue flow control is | |
1312 | * thus managed under this lock as well. | |
1313 | */ | |
1da177e4 | 1314 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 1315 | |
eea221ce AN |
1316 | /* failsafe... (handle txdone now if half of FDs are used) */ |
1317 | if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM > | |
1318 | TX_FD_NUM / 2) | |
1319 | tc35815_txdone(dev); | |
1320 | ||
1321 | if (netif_msg_pktdata(lp)) | |
1322 | print_eth(skb->data); | |
1323 | #ifdef DEBUG | |
1324 | if (lp->tx_skbs[lp->tfd_start].skb) { | |
1325 | printk("%s: tx_skbs conflict.\n", dev->name); | |
1326 | panic_queues(dev); | |
1da177e4 | 1327 | } |
eea221ce AN |
1328 | #else |
1329 | BUG_ON(lp->tx_skbs[lp->tfd_start].skb); | |
1da177e4 | 1330 | #endif |
eea221ce AN |
1331 | lp->tx_skbs[lp->tfd_start].skb = skb; |
1332 | lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); | |
1333 | ||
1334 | /*add to ring */ | |
1335 | txfd = &lp->tfd_base[lp->tfd_start]; | |
1336 | txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma); | |
1337 | txfd->bd.BDCtl = cpu_to_le32(skb->len); | |
1338 | txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start); | |
1339 | txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT)); | |
1340 | ||
1341 | if (lp->tfd_start == lp->tfd_end) { | |
1342 | struct tc35815_regs __iomem *tr = | |
1343 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1344 | /* Start DMA Transmitter. */ | |
1345 | txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL); | |
eea221ce | 1346 | txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); |
eea221ce AN |
1347 | if (netif_msg_tx_queued(lp)) { |
1348 | printk("%s: starting TxFD.\n", dev->name); | |
1349 | dump_txfd(txfd); | |
1350 | } | |
1351 | tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); | |
1352 | } else { | |
1353 | txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL); | |
1354 | if (netif_msg_tx_queued(lp)) { | |
1355 | printk("%s: queueing TxFD.\n", dev->name); | |
1356 | dump_txfd(txfd); | |
1da177e4 | 1357 | } |
eea221ce AN |
1358 | } |
1359 | lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM; | |
1da177e4 | 1360 | |
eea221ce AN |
1361 | /* If we just used up the very last entry in the |
1362 | * TX ring on this device, tell the queueing | |
1363 | * layer to send no more. | |
1364 | */ | |
1365 | if (tc35815_tx_full(dev)) { | |
1366 | if (netif_msg_tx_queued(lp)) | |
1367 | printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name); | |
1368 | netif_stop_queue(dev); | |
1da177e4 LT |
1369 | } |
1370 | ||
eea221ce AN |
1371 | /* When the TX completion hw interrupt arrives, this |
1372 | * is when the transmit statistics are updated. | |
1373 | */ | |
1374 | ||
1375 | spin_unlock_irqrestore(&lp->lock, flags); | |
6ed10654 | 1376 | return NETDEV_TX_OK; |
1da177e4 LT |
1377 | } |
1378 | ||
1379 | #define FATAL_ERROR_INT \ | |
1380 | (Int_IntPCI | Int_DmParErr | Int_IntNRAbt) | |
eea221ce | 1381 | static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status) |
1da177e4 LT |
1382 | { |
1383 | static int count; | |
1384 | printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):", | |
1385 | dev->name, status); | |
1da177e4 LT |
1386 | if (status & Int_IntPCI) |
1387 | printk(" IntPCI"); | |
1388 | if (status & Int_DmParErr) | |
1389 | printk(" DmParErr"); | |
1390 | if (status & Int_IntNRAbt) | |
1391 | printk(" IntNRAbt"); | |
1392 | printk("\n"); | |
1393 | if (count++ > 100) | |
1394 | panic("%s: Too many fatal errors.", dev->name); | |
eea221ce | 1395 | printk(KERN_WARNING "%s: Resetting ...\n", dev->name); |
1da177e4 | 1396 | /* Try to restart the adaptor. */ |
c6686fe3 | 1397 | tc35815_schedule_restart(dev); |
eea221ce AN |
1398 | } |
1399 | ||
eea221ce | 1400 | static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit) |
eea221ce | 1401 | { |
ee79b7fb | 1402 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1403 | int ret = -1; |
1404 | ||
1405 | /* Fatal errors... */ | |
1406 | if (status & FATAL_ERROR_INT) { | |
1407 | tc35815_fatal_error_interrupt(dev, status); | |
1408 | return 0; | |
1409 | } | |
1410 | /* recoverable errors */ | |
1411 | if (status & Int_IntFDAEx) { | |
db30f5ef AN |
1412 | if (netif_msg_rx_err(lp)) |
1413 | dev_warn(&dev->dev, | |
1414 | "Free Descriptor Area Exhausted (%#x).\n", | |
1415 | status); | |
c201abd9 | 1416 | dev->stats.rx_dropped++; |
eea221ce AN |
1417 | ret = 0; |
1418 | } | |
1419 | if (status & Int_IntBLEx) { | |
db30f5ef AN |
1420 | if (netif_msg_rx_err(lp)) |
1421 | dev_warn(&dev->dev, | |
1422 | "Buffer List Exhausted (%#x).\n", | |
1423 | status); | |
c201abd9 | 1424 | dev->stats.rx_dropped++; |
eea221ce AN |
1425 | ret = 0; |
1426 | } | |
1427 | if (status & Int_IntExBD) { | |
db30f5ef AN |
1428 | if (netif_msg_rx_err(lp)) |
1429 | dev_warn(&dev->dev, | |
1430 | "Excessive Buffer Descriptiors (%#x).\n", | |
1431 | status); | |
c201abd9 | 1432 | dev->stats.rx_length_errors++; |
eea221ce AN |
1433 | ret = 0; |
1434 | } | |
1435 | ||
1436 | /* normal notification */ | |
1437 | if (status & Int_IntMacRx) { | |
1438 | /* Got a packet(s). */ | |
eea221ce | 1439 | ret = tc35815_rx(dev, limit); |
eea221ce AN |
1440 | lp->lstats.rx_ints++; |
1441 | } | |
1442 | if (status & Int_IntMacTx) { | |
1443 | /* Transmit complete. */ | |
1444 | lp->lstats.tx_ints++; | |
dee7399c | 1445 | spin_lock_irq(&lp->lock); |
eea221ce | 1446 | tc35815_txdone(dev); |
dee7399c | 1447 | spin_unlock_irq(&lp->lock); |
02c5c8ec AN |
1448 | if (ret < 0) |
1449 | ret = 0; | |
eea221ce AN |
1450 | } |
1451 | return ret; | |
1da177e4 LT |
1452 | } |
1453 | ||
1454 | /* | |
1455 | * The typical workload of the driver: | |
eea221ce | 1456 | * Handle the network interface interrupts. |
1da177e4 | 1457 | */ |
7d12e780 | 1458 | static irqreturn_t tc35815_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1459 | { |
1460 | struct net_device *dev = dev_id; | |
bea3348e | 1461 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1462 | struct tc35815_regs __iomem *tr = |
1463 | (struct tc35815_regs __iomem *)dev->base_addr; | |
eea221ce AN |
1464 | u32 dmactl = tc_readl(&tr->DMA_Ctl); |
1465 | ||
1466 | if (!(dmactl & DMA_IntMask)) { | |
1467 | /* disable interrupts */ | |
1468 | tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl); | |
288379f0 BH |
1469 | if (napi_schedule_prep(&lp->napi)) |
1470 | __napi_schedule(&lp->napi); | |
eea221ce AN |
1471 | else { |
1472 | printk(KERN_ERR "%s: interrupt taken in poll\n", | |
1473 | dev->name); | |
1474 | BUG(); | |
1da177e4 | 1475 | } |
eea221ce AN |
1476 | (void)tc_readl(&tr->Int_Src); /* flush */ |
1477 | return IRQ_HANDLED; | |
1478 | } | |
1479 | return IRQ_NONE; | |
eea221ce | 1480 | } |
1da177e4 | 1481 | |
eea221ce AN |
1482 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1483 | static void tc35815_poll_controller(struct net_device *dev) | |
1484 | { | |
1485 | disable_irq(dev->irq); | |
1486 | tc35815_interrupt(dev->irq, dev); | |
1487 | enable_irq(dev->irq); | |
1da177e4 | 1488 | } |
eea221ce | 1489 | #endif |
1da177e4 LT |
1490 | |
1491 | /* We have a good packet(s), get it/them out of the buffers. */ | |
eea221ce AN |
1492 | static int |
1493 | tc35815_rx(struct net_device *dev, int limit) | |
1da177e4 | 1494 | { |
ee79b7fb | 1495 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1496 | unsigned int fdctl; |
1497 | int i; | |
eea221ce | 1498 | int received = 0; |
1da177e4 LT |
1499 | |
1500 | while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) { | |
1501 | int status = le32_to_cpu(lp->rfd_cur->fd.FDStat); | |
1502 | int pkt_len = fdctl & FD_FDLength_MASK; | |
1da177e4 | 1503 | int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; |
eea221ce AN |
1504 | #ifdef DEBUG |
1505 | struct RxFD *next_rfd; | |
1506 | #endif | |
1507 | #if (RX_CTL_CMD & Rx_StripCRC) == 0 | |
82a9928d | 1508 | pkt_len -= ETH_FCS_LEN; |
eea221ce | 1509 | #endif |
1da177e4 | 1510 | |
eea221ce | 1511 | if (netif_msg_rx_status(lp)) |
1da177e4 LT |
1512 | dump_rxfd(lp->rfd_cur); |
1513 | if (status & Rx_Good) { | |
1da177e4 LT |
1514 | struct sk_buff *skb; |
1515 | unsigned char *data; | |
eea221ce | 1516 | int cur_bd; |
6aa20a22 | 1517 | |
eea221ce AN |
1518 | if (--limit < 0) |
1519 | break; | |
eea221ce AN |
1520 | BUG_ON(bd_count > 1); |
1521 | cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl) | |
1522 | & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; | |
1523 | #ifdef DEBUG | |
1524 | if (cur_bd >= RX_BUF_NUM) { | |
1525 | printk("%s: invalid BDID.\n", dev->name); | |
1526 | panic_queues(dev); | |
1527 | } | |
1528 | BUG_ON(lp->rx_skbs[cur_bd].skb_dma != | |
1529 | (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3)); | |
1530 | if (!lp->rx_skbs[cur_bd].skb) { | |
1531 | printk("%s: NULL skb.\n", dev->name); | |
1532 | panic_queues(dev); | |
1533 | } | |
1534 | #else | |
1535 | BUG_ON(cur_bd >= RX_BUF_NUM); | |
1da177e4 | 1536 | #endif |
eea221ce AN |
1537 | skb = lp->rx_skbs[cur_bd].skb; |
1538 | prefetch(skb->data); | |
1539 | lp->rx_skbs[cur_bd].skb = NULL; | |
eea221ce AN |
1540 | pci_unmap_single(lp->pci_dev, |
1541 | lp->rx_skbs[cur_bd].skb_dma, | |
1542 | RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
82a9928d AN |
1543 | if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN) |
1544 | memmove(skb->data, skb->data - NET_IP_ALIGN, | |
1545 | pkt_len); | |
eea221ce | 1546 | data = skb_put(skb, pkt_len); |
eea221ce | 1547 | if (netif_msg_pktdata(lp)) |
1da177e4 LT |
1548 | print_eth(data); |
1549 | skb->protocol = eth_type_trans(skb, dev); | |
eea221ce AN |
1550 | netif_receive_skb(skb); |
1551 | received++; | |
c201abd9 AN |
1552 | dev->stats.rx_packets++; |
1553 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 | 1554 | } else { |
c201abd9 | 1555 | dev->stats.rx_errors++; |
db30f5ef AN |
1556 | if (netif_msg_rx_err(lp)) |
1557 | dev_info(&dev->dev, "Rx error (status %x)\n", | |
1558 | status & Rx_Stat_Mask); | |
1da177e4 LT |
1559 | /* WORKAROUND: LongErr and CRCErr means Overflow. */ |
1560 | if ((status & Rx_LongErr) && (status & Rx_CRCErr)) { | |
1561 | status &= ~(Rx_LongErr|Rx_CRCErr); | |
1562 | status |= Rx_Over; | |
1563 | } | |
c201abd9 AN |
1564 | if (status & Rx_LongErr) |
1565 | dev->stats.rx_length_errors++; | |
1566 | if (status & Rx_Over) | |
1567 | dev->stats.rx_fifo_errors++; | |
1568 | if (status & Rx_CRCErr) | |
1569 | dev->stats.rx_crc_errors++; | |
1570 | if (status & Rx_Align) | |
1571 | dev->stats.rx_frame_errors++; | |
1da177e4 LT |
1572 | } |
1573 | ||
1574 | if (bd_count > 0) { | |
1575 | /* put Free Buffer back to controller */ | |
1576 | int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl); | |
1577 | unsigned char id = | |
1578 | (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; | |
eea221ce AN |
1579 | #ifdef DEBUG |
1580 | if (id >= RX_BUF_NUM) { | |
1da177e4 LT |
1581 | printk("%s: invalid BDID.\n", dev->name); |
1582 | panic_queues(dev); | |
1583 | } | |
eea221ce AN |
1584 | #else |
1585 | BUG_ON(id >= RX_BUF_NUM); | |
1586 | #endif | |
1da177e4 | 1587 | /* free old buffers */ |
ccc57aac | 1588 | lp->fbl_count--; |
eea221ce | 1589 | while (lp->fbl_count < RX_BUF_NUM) |
eea221ce | 1590 | { |
eea221ce AN |
1591 | unsigned char curid = |
1592 | (id + 1 + lp->fbl_count) % RX_BUF_NUM; | |
eea221ce AN |
1593 | struct BDesc *bd = &lp->fbl_ptr->bd[curid]; |
1594 | #ifdef DEBUG | |
1595 | bdctl = le32_to_cpu(bd->BDCtl); | |
1da177e4 LT |
1596 | if (bdctl & BD_CownsBD) { |
1597 | printk("%s: Freeing invalid BD.\n", | |
1598 | dev->name); | |
1599 | panic_queues(dev); | |
1600 | } | |
eea221ce | 1601 | #endif |
3a4fa0a2 | 1602 | /* pass BD to controller */ |
eea221ce AN |
1603 | if (!lp->rx_skbs[curid].skb) { |
1604 | lp->rx_skbs[curid].skb = | |
1605 | alloc_rxbuf_skb(dev, | |
1606 | lp->pci_dev, | |
1607 | &lp->rx_skbs[curid].skb_dma); | |
1608 | if (!lp->rx_skbs[curid].skb) | |
1609 | break; /* try on next reception */ | |
1610 | bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma); | |
1611 | } | |
1da177e4 | 1612 | /* Note: BDLength was modified by chip. */ |
eea221ce AN |
1613 | bd->BDCtl = cpu_to_le32(BD_CownsBD | |
1614 | (curid << BD_RxBDID_SHIFT) | | |
1615 | RX_BUF_SIZE); | |
eea221ce | 1616 | lp->fbl_count++; |
1da177e4 LT |
1617 | } |
1618 | } | |
1619 | ||
1620 | /* put RxFD back to controller */ | |
eea221ce AN |
1621 | #ifdef DEBUG |
1622 | next_rfd = fd_bus_to_virt(lp, | |
1623 | le32_to_cpu(lp->rfd_cur->fd.FDNext)); | |
1da177e4 LT |
1624 | if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) { |
1625 | printk("%s: RxFD FDNext invalid.\n", dev->name); | |
1626 | panic_queues(dev); | |
1627 | } | |
eea221ce | 1628 | #endif |
1da177e4 | 1629 | for (i = 0; i < (bd_count + 1) / 2 + 1; i++) { |
3a4fa0a2 | 1630 | /* pass FD to controller */ |
eea221ce AN |
1631 | #ifdef DEBUG |
1632 | lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead); | |
1633 | #else | |
1634 | lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL); | |
1635 | #endif | |
1da177e4 LT |
1636 | lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD); |
1637 | lp->rfd_cur++; | |
1da177e4 | 1638 | } |
eea221ce AN |
1639 | if (lp->rfd_cur > lp->rfd_limit) |
1640 | lp->rfd_cur = lp->rfd_base; | |
1641 | #ifdef DEBUG | |
1642 | if (lp->rfd_cur != next_rfd) | |
1643 | printk("rfd_cur = %p, next_rfd %p\n", | |
1644 | lp->rfd_cur, next_rfd); | |
1645 | #endif | |
1da177e4 LT |
1646 | } |
1647 | ||
eea221ce | 1648 | return received; |
1da177e4 LT |
1649 | } |
1650 | ||
bea3348e | 1651 | static int tc35815_poll(struct napi_struct *napi, int budget) |
eea221ce | 1652 | { |
bea3348e SH |
1653 | struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi); |
1654 | struct net_device *dev = lp->dev; | |
eea221ce AN |
1655 | struct tc35815_regs __iomem *tr = |
1656 | (struct tc35815_regs __iomem *)dev->base_addr; | |
eea221ce AN |
1657 | int received = 0, handled; |
1658 | u32 status; | |
1659 | ||
dee7399c | 1660 | spin_lock(&lp->rx_lock); |
eea221ce AN |
1661 | status = tc_readl(&tr->Int_Src); |
1662 | do { | |
db30f5ef AN |
1663 | /* BLEx, FDAEx will be cleared later */ |
1664 | tc_writel(status & ~(Int_BLEx | Int_FDAEx), | |
1665 | &tr->Int_Src); /* write to clear */ | |
eea221ce | 1666 | |
a2c465db | 1667 | handled = tc35815_do_interrupt(dev, status, budget - received); |
db30f5ef AN |
1668 | if (status & (Int_BLEx | Int_FDAEx)) |
1669 | tc_writel(status & (Int_BLEx | Int_FDAEx), | |
1670 | &tr->Int_Src); | |
eea221ce AN |
1671 | if (handled >= 0) { |
1672 | received += handled; | |
bea3348e | 1673 | if (received >= budget) |
eea221ce AN |
1674 | break; |
1675 | } | |
1676 | status = tc_readl(&tr->Int_Src); | |
1677 | } while (status); | |
dee7399c | 1678 | spin_unlock(&lp->rx_lock); |
eea221ce | 1679 | |
bea3348e | 1680 | if (received < budget) { |
288379f0 | 1681 | napi_complete(napi); |
bea3348e SH |
1682 | /* enable interrupts */ |
1683 | tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl); | |
1684 | } | |
1685 | return received; | |
eea221ce | 1686 | } |
eea221ce | 1687 | |
1da177e4 | 1688 | #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr) |
1da177e4 LT |
1689 | |
1690 | static void | |
1691 | tc35815_check_tx_stat(struct net_device *dev, int status) | |
1692 | { | |
ee79b7fb | 1693 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1694 | const char *msg = NULL; |
1695 | ||
1696 | /* count collisions */ | |
1697 | if (status & Tx_ExColl) | |
c201abd9 | 1698 | dev->stats.collisions += 16; |
1da177e4 | 1699 | if (status & Tx_TxColl_MASK) |
c201abd9 | 1700 | dev->stats.collisions += status & Tx_TxColl_MASK; |
1da177e4 | 1701 | |
eea221ce | 1702 | /* TX4939 does not have NCarr */ |
c6686fe3 | 1703 | if (lp->chiptype == TC35815_TX4939) |
eea221ce | 1704 | status &= ~Tx_NCarr; |
1da177e4 | 1705 | /* WORKAROUND: ignore LostCrS in full duplex operation */ |
c6686fe3 | 1706 | if (!lp->link || lp->duplex == DUPLEX_FULL) |
1da177e4 LT |
1707 | status &= ~Tx_NCarr; |
1708 | ||
1709 | if (!(status & TX_STA_ERR)) { | |
1710 | /* no error. */ | |
c201abd9 | 1711 | dev->stats.tx_packets++; |
1da177e4 LT |
1712 | return; |
1713 | } | |
1714 | ||
c201abd9 | 1715 | dev->stats.tx_errors++; |
1da177e4 | 1716 | if (status & Tx_ExColl) { |
c201abd9 | 1717 | dev->stats.tx_aborted_errors++; |
1da177e4 LT |
1718 | msg = "Excessive Collision."; |
1719 | } | |
1720 | if (status & Tx_Under) { | |
c201abd9 | 1721 | dev->stats.tx_fifo_errors++; |
1da177e4 | 1722 | msg = "Tx FIFO Underrun."; |
eea221ce AN |
1723 | if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) { |
1724 | lp->lstats.tx_underrun++; | |
1725 | if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) { | |
1726 | struct tc35815_regs __iomem *tr = | |
1727 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1728 | tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh); | |
1729 | msg = "Tx FIFO Underrun.Change Tx threshold to max."; | |
1730 | } | |
1731 | } | |
1da177e4 LT |
1732 | } |
1733 | if (status & Tx_Defer) { | |
c201abd9 | 1734 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1735 | msg = "Excessive Deferral."; |
1736 | } | |
1da177e4 | 1737 | if (status & Tx_NCarr) { |
c201abd9 | 1738 | dev->stats.tx_carrier_errors++; |
1da177e4 LT |
1739 | msg = "Lost Carrier Sense."; |
1740 | } | |
1da177e4 | 1741 | if (status & Tx_LateColl) { |
c201abd9 | 1742 | dev->stats.tx_aborted_errors++; |
1da177e4 LT |
1743 | msg = "Late Collision."; |
1744 | } | |
1745 | if (status & Tx_TxPar) { | |
c201abd9 | 1746 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1747 | msg = "Transmit Parity Error."; |
1748 | } | |
1749 | if (status & Tx_SQErr) { | |
c201abd9 | 1750 | dev->stats.tx_heartbeat_errors++; |
1da177e4 LT |
1751 | msg = "Signal Quality Error."; |
1752 | } | |
eea221ce | 1753 | if (msg && netif_msg_tx_err(lp)) |
1da177e4 LT |
1754 | printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status); |
1755 | } | |
1756 | ||
eea221ce AN |
1757 | /* This handles TX complete events posted by the device |
1758 | * via interrupts. | |
1759 | */ | |
1da177e4 LT |
1760 | static void |
1761 | tc35815_txdone(struct net_device *dev) | |
1762 | { | |
ee79b7fb | 1763 | struct tc35815_local *lp = netdev_priv(dev); |
1da177e4 LT |
1764 | struct TxFD *txfd; |
1765 | unsigned int fdctl; | |
1da177e4 LT |
1766 | |
1767 | txfd = &lp->tfd_base[lp->tfd_end]; | |
1768 | while (lp->tfd_start != lp->tfd_end && | |
1769 | !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) { | |
1770 | int status = le32_to_cpu(txfd->fd.FDStat); | |
1771 | struct sk_buff *skb; | |
1772 | unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext); | |
eea221ce | 1773 | u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem); |
1da177e4 | 1774 | |
eea221ce | 1775 | if (netif_msg_tx_done(lp)) { |
1da177e4 LT |
1776 | printk("%s: complete TxFD.\n", dev->name); |
1777 | dump_txfd(txfd); | |
1778 | } | |
1779 | tc35815_check_tx_stat(dev, status); | |
1780 | ||
eea221ce AN |
1781 | skb = fdsystem != 0xffffffff ? |
1782 | lp->tx_skbs[fdsystem].skb : NULL; | |
1783 | #ifdef DEBUG | |
1784 | if (lp->tx_skbs[lp->tfd_end].skb != skb) { | |
1785 | printk("%s: tx_skbs mismatch.\n", dev->name); | |
1786 | panic_queues(dev); | |
1787 | } | |
1788 | #else | |
1789 | BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb); | |
1790 | #endif | |
1da177e4 | 1791 | if (skb) { |
c201abd9 | 1792 | dev->stats.tx_bytes += skb->len; |
eea221ce AN |
1793 | pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE); |
1794 | lp->tx_skbs[lp->tfd_end].skb = NULL; | |
1795 | lp->tx_skbs[lp->tfd_end].skb_dma = 0; | |
1da177e4 LT |
1796 | dev_kfree_skb_any(skb); |
1797 | } | |
eea221ce | 1798 | txfd->fd.FDSystem = cpu_to_le32(0xffffffff); |
1da177e4 | 1799 | |
1da177e4 LT |
1800 | lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM; |
1801 | txfd = &lp->tfd_base[lp->tfd_end]; | |
eea221ce AN |
1802 | #ifdef DEBUG |
1803 | if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) { | |
1da177e4 LT |
1804 | printk("%s: TxFD FDNext invalid.\n", dev->name); |
1805 | panic_queues(dev); | |
1806 | } | |
eea221ce | 1807 | #endif |
1da177e4 LT |
1808 | if (fdnext & FD_Next_EOL) { |
1809 | /* DMA Transmitter has been stopping... */ | |
1810 | if (lp->tfd_end != lp->tfd_start) { | |
eea221ce AN |
1811 | struct tc35815_regs __iomem *tr = |
1812 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1da177e4 | 1813 | int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM; |
7f225b42 | 1814 | struct TxFD *txhead = &lp->tfd_base[head]; |
1da177e4 LT |
1815 | int qlen = (lp->tfd_start + TX_FD_NUM |
1816 | - lp->tfd_end) % TX_FD_NUM; | |
1817 | ||
eea221ce | 1818 | #ifdef DEBUG |
1da177e4 LT |
1819 | if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) { |
1820 | printk("%s: TxFD FDCtl invalid.\n", dev->name); | |
1821 | panic_queues(dev); | |
1822 | } | |
eea221ce | 1823 | #endif |
1da177e4 LT |
1824 | /* log max queue length */ |
1825 | if (lp->lstats.max_tx_qlen < qlen) | |
1826 | lp->lstats.max_tx_qlen = qlen; | |
1827 | ||
1828 | ||
1829 | /* start DMA Transmitter again */ | |
1830 | txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL); | |
1da177e4 | 1831 | txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); |
eea221ce | 1832 | if (netif_msg_tx_queued(lp)) { |
1da177e4 LT |
1833 | printk("%s: start TxFD on queue.\n", |
1834 | dev->name); | |
1835 | dump_txfd(txfd); | |
1836 | } | |
eea221ce | 1837 | tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); |
1da177e4 LT |
1838 | } |
1839 | break; | |
1840 | } | |
1841 | } | |
1842 | ||
eea221ce AN |
1843 | /* If we had stopped the queue due to a "tx full" |
1844 | * condition, and space has now been made available, | |
1845 | * wake up the queue. | |
1846 | */ | |
7f225b42 | 1847 | if (netif_queue_stopped(dev) && !tc35815_tx_full(dev)) |
eea221ce | 1848 | netif_wake_queue(dev); |
1da177e4 LT |
1849 | } |
1850 | ||
1851 | /* The inverse routine to tc35815_open(). */ | |
1852 | static int | |
1853 | tc35815_close(struct net_device *dev) | |
1854 | { | |
ee79b7fb | 1855 | struct tc35815_local *lp = netdev_priv(dev); |
bea3348e | 1856 | |
1da177e4 | 1857 | netif_stop_queue(dev); |
bea3348e | 1858 | napi_disable(&lp->napi); |
c6686fe3 AN |
1859 | if (lp->phy_dev) |
1860 | phy_stop(lp->phy_dev); | |
1861 | cancel_work_sync(&lp->restart_work); | |
1da177e4 LT |
1862 | |
1863 | /* Flush the Tx and disable Rx here. */ | |
1da177e4 LT |
1864 | tc35815_chip_reset(dev); |
1865 | free_irq(dev->irq, dev); | |
1866 | ||
1867 | tc35815_free_queues(dev); | |
1868 | ||
1869 | return 0; | |
eea221ce | 1870 | |
1da177e4 LT |
1871 | } |
1872 | ||
1873 | /* | |
1874 | * Get the current statistics. | |
1875 | * This may be called with the card open or closed. | |
1876 | */ | |
1877 | static struct net_device_stats *tc35815_get_stats(struct net_device *dev) | |
1878 | { | |
eea221ce AN |
1879 | struct tc35815_regs __iomem *tr = |
1880 | (struct tc35815_regs __iomem *)dev->base_addr; | |
c201abd9 | 1881 | if (netif_running(dev)) |
1da177e4 | 1882 | /* Update the statistics from the device registers. */ |
7bb82e83 | 1883 | dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt); |
1da177e4 | 1884 | |
c201abd9 | 1885 | return &dev->stats; |
1da177e4 LT |
1886 | } |
1887 | ||
eea221ce | 1888 | static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr) |
1da177e4 | 1889 | { |
ee79b7fb | 1890 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1891 | struct tc35815_regs __iomem *tr = |
1892 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1da177e4 | 1893 | int cam_index = index * 6; |
eea221ce AN |
1894 | u32 cam_data; |
1895 | u32 saved_addr; | |
958eb80b | 1896 | |
1da177e4 LT |
1897 | saved_addr = tc_readl(&tr->CAM_Adr); |
1898 | ||
958eb80b | 1899 | if (netif_msg_hw(lp)) |
e174961c JB |
1900 | printk(KERN_DEBUG "%s: CAM %d: %pM\n", |
1901 | dev->name, index, addr); | |
1da177e4 LT |
1902 | if (index & 1) { |
1903 | /* read modify write */ | |
1904 | tc_writel(cam_index - 2, &tr->CAM_Adr); | |
1905 | cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000; | |
1906 | cam_data |= addr[0] << 8 | addr[1]; | |
1907 | tc_writel(cam_data, &tr->CAM_Data); | |
1908 | /* write whole word */ | |
1909 | tc_writel(cam_index + 2, &tr->CAM_Adr); | |
1910 | cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; | |
1911 | tc_writel(cam_data, &tr->CAM_Data); | |
1912 | } else { | |
1913 | /* write whole word */ | |
1914 | tc_writel(cam_index, &tr->CAM_Adr); | |
1915 | cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; | |
1916 | tc_writel(cam_data, &tr->CAM_Data); | |
1917 | /* read modify write */ | |
1918 | tc_writel(cam_index + 4, &tr->CAM_Adr); | |
1919 | cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff; | |
1920 | cam_data |= addr[4] << 24 | (addr[5] << 16); | |
1921 | tc_writel(cam_data, &tr->CAM_Data); | |
1922 | } | |
1923 | ||
1da177e4 LT |
1924 | tc_writel(saved_addr, &tr->CAM_Adr); |
1925 | } | |
1926 | ||
1927 | ||
1928 | /* | |
1929 | * Set or clear the multicast filter for this adaptor. | |
1930 | * num_addrs == -1 Promiscuous mode, receive all packets | |
1931 | * num_addrs == 0 Normal mode, clear multicast list | |
1932 | * num_addrs > 0 Multicast mode, receive normal and MC packets, | |
1933 | * and do best-effort filtering. | |
1934 | */ | |
1935 | static void | |
1936 | tc35815_set_multicast_list(struct net_device *dev) | |
1937 | { | |
eea221ce AN |
1938 | struct tc35815_regs __iomem *tr = |
1939 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1da177e4 | 1940 | |
7f225b42 | 1941 | if (dev->flags & IFF_PROMISC) { |
eea221ce AN |
1942 | /* With some (all?) 100MHalf HUB, controller will hang |
1943 | * if we enabled promiscuous mode before linkup... */ | |
ee79b7fb | 1944 | struct tc35815_local *lp = netdev_priv(dev); |
c6686fe3 AN |
1945 | |
1946 | if (!lp->link) | |
eea221ce | 1947 | return; |
1da177e4 LT |
1948 | /* Enable promiscuous mode */ |
1949 | tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl); | |
7f225b42 | 1950 | } else if ((dev->flags & IFF_ALLMULTI) || |
4cd24eaf | 1951 | netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) { |
1da177e4 LT |
1952 | /* CAM 0, 1, 20 are reserved. */ |
1953 | /* Disable promiscuous mode, use normal mode. */ | |
1954 | tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl); | |
4cd24eaf | 1955 | } else if (!netdev_mc_empty(dev)) { |
22bedad3 | 1956 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1957 | int i; |
1958 | int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE); | |
1959 | ||
1960 | tc_writel(0, &tr->CAM_Ctl); | |
1961 | /* Walk the address list, and load the filter */ | |
567ec874 | 1962 | i = 0; |
22bedad3 | 1963 | netdev_for_each_mc_addr(ha, dev) { |
1da177e4 | 1964 | /* entry 0,1 is reserved. */ |
22bedad3 | 1965 | tc35815_set_cam_entry(dev, i + 2, ha->addr); |
1da177e4 | 1966 | ena_bits |= CAM_Ena_Bit(i + 2); |
567ec874 | 1967 | i++; |
1da177e4 LT |
1968 | } |
1969 | tc_writel(ena_bits, &tr->CAM_Ena); | |
1970 | tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); | |
7f225b42 | 1971 | } else { |
1da177e4 LT |
1972 | tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); |
1973 | tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); | |
1974 | } | |
1975 | } | |
1976 | ||
eea221ce | 1977 | static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
1da177e4 | 1978 | { |
ee79b7fb | 1979 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
1980 | strcpy(info->driver, MODNAME); |
1981 | strcpy(info->version, DRV_VERSION); | |
1982 | strcpy(info->bus_info, pci_name(lp->pci_dev)); | |
1983 | } | |
6aa20a22 | 1984 | |
eea221ce AN |
1985 | static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1986 | { | |
ee79b7fb | 1987 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce | 1988 | |
c6686fe3 AN |
1989 | if (!lp->phy_dev) |
1990 | return -ENODEV; | |
1991 | return phy_ethtool_gset(lp->phy_dev, cmd); | |
eea221ce AN |
1992 | } |
1993 | ||
c6686fe3 | 1994 | static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
eea221ce | 1995 | { |
ee79b7fb | 1996 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce | 1997 | |
c6686fe3 AN |
1998 | if (!lp->phy_dev) |
1999 | return -ENODEV; | |
2000 | return phy_ethtool_sset(lp->phy_dev, cmd); | |
eea221ce AN |
2001 | } |
2002 | ||
2003 | static u32 tc35815_get_msglevel(struct net_device *dev) | |
2004 | { | |
ee79b7fb | 2005 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
2006 | return lp->msg_enable; |
2007 | } | |
2008 | ||
2009 | static void tc35815_set_msglevel(struct net_device *dev, u32 datum) | |
2010 | { | |
ee79b7fb | 2011 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
2012 | lp->msg_enable = datum; |
2013 | } | |
2014 | ||
b9f2c044 | 2015 | static int tc35815_get_sset_count(struct net_device *dev, int sset) |
eea221ce | 2016 | { |
ee79b7fb | 2017 | struct tc35815_local *lp = netdev_priv(dev); |
b9f2c044 JG |
2018 | |
2019 | switch (sset) { | |
2020 | case ETH_SS_STATS: | |
2021 | return sizeof(lp->lstats) / sizeof(int); | |
2022 | default: | |
2023 | return -EOPNOTSUPP; | |
2024 | } | |
eea221ce | 2025 | } |
1da177e4 | 2026 | |
eea221ce AN |
2027 | static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) |
2028 | { | |
ee79b7fb | 2029 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
2030 | data[0] = lp->lstats.max_tx_qlen; |
2031 | data[1] = lp->lstats.tx_ints; | |
2032 | data[2] = lp->lstats.rx_ints; | |
2033 | data[3] = lp->lstats.tx_underrun; | |
2034 | } | |
2035 | ||
2036 | static struct { | |
2037 | const char str[ETH_GSTRING_LEN]; | |
2038 | } ethtool_stats_keys[] = { | |
2039 | { "max_tx_qlen" }, | |
2040 | { "tx_ints" }, | |
2041 | { "rx_ints" }, | |
2042 | { "tx_underrun" }, | |
2043 | }; | |
2044 | ||
2045 | static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
2046 | { | |
2047 | memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); | |
2048 | } | |
2049 | ||
2050 | static const struct ethtool_ops tc35815_ethtool_ops = { | |
2051 | .get_drvinfo = tc35815_get_drvinfo, | |
2052 | .get_settings = tc35815_get_settings, | |
2053 | .set_settings = tc35815_set_settings, | |
c6686fe3 | 2054 | .get_link = ethtool_op_get_link, |
eea221ce AN |
2055 | .get_msglevel = tc35815_get_msglevel, |
2056 | .set_msglevel = tc35815_set_msglevel, | |
2057 | .get_strings = tc35815_get_strings, | |
b9f2c044 | 2058 | .get_sset_count = tc35815_get_sset_count, |
eea221ce | 2059 | .get_ethtool_stats = tc35815_get_ethtool_stats, |
eea221ce AN |
2060 | }; |
2061 | ||
2062 | static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2063 | { | |
ee79b7fb | 2064 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
2065 | |
2066 | if (!netif_running(dev)) | |
2067 | return -EINVAL; | |
c6686fe3 AN |
2068 | if (!lp->phy_dev) |
2069 | return -ENODEV; | |
28b04113 | 2070 | return phy_mii_ioctl(lp->phy_dev, rq, cmd); |
eea221ce AN |
2071 | } |
2072 | ||
2073 | static void tc35815_chip_reset(struct net_device *dev) | |
2074 | { | |
2075 | struct tc35815_regs __iomem *tr = | |
2076 | (struct tc35815_regs __iomem *)dev->base_addr; | |
2077 | int i; | |
1da177e4 LT |
2078 | /* reset the controller */ |
2079 | tc_writel(MAC_Reset, &tr->MAC_Ctl); | |
eea221ce AN |
2080 | udelay(4); /* 3200ns */ |
2081 | i = 0; | |
2082 | while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) { | |
2083 | if (i++ > 100) { | |
2084 | printk(KERN_ERR "%s: MAC reset failed.\n", dev->name); | |
2085 | break; | |
2086 | } | |
2087 | mdelay(1); | |
2088 | } | |
1da177e4 LT |
2089 | tc_writel(0, &tr->MAC_Ctl); |
2090 | ||
2091 | /* initialize registers to default value */ | |
2092 | tc_writel(0, &tr->DMA_Ctl); | |
2093 | tc_writel(0, &tr->TxThrsh); | |
2094 | tc_writel(0, &tr->TxPollCtr); | |
2095 | tc_writel(0, &tr->RxFragSize); | |
2096 | tc_writel(0, &tr->Int_En); | |
2097 | tc_writel(0, &tr->FDA_Bas); | |
2098 | tc_writel(0, &tr->FDA_Lim); | |
2099 | tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */ | |
2100 | tc_writel(0, &tr->CAM_Ctl); | |
2101 | tc_writel(0, &tr->Tx_Ctl); | |
2102 | tc_writel(0, &tr->Rx_Ctl); | |
2103 | tc_writel(0, &tr->CAM_Ena); | |
2104 | (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */ | |
2105 | ||
eea221ce AN |
2106 | /* initialize internal SRAM */ |
2107 | tc_writel(DMA_TestMode, &tr->DMA_Ctl); | |
2108 | for (i = 0; i < 0x1000; i += 4) { | |
2109 | tc_writel(i, &tr->CAM_Adr); | |
2110 | tc_writel(0, &tr->CAM_Data); | |
2111 | } | |
2112 | tc_writel(0, &tr->DMA_Ctl); | |
1da177e4 LT |
2113 | } |
2114 | ||
2115 | static void tc35815_chip_init(struct net_device *dev) | |
2116 | { | |
ee79b7fb | 2117 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
2118 | struct tc35815_regs __iomem *tr = |
2119 | (struct tc35815_regs __iomem *)dev->base_addr; | |
1da177e4 LT |
2120 | unsigned long txctl = TX_CTL_CMD; |
2121 | ||
1da177e4 | 2122 | /* load station address to CAM */ |
eea221ce | 2123 | tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr); |
1da177e4 LT |
2124 | |
2125 | /* Enable CAM (broadcast and unicast) */ | |
2126 | tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); | |
2127 | tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); | |
2128 | ||
eea221ce AN |
2129 | /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */ |
2130 | if (HAVE_DMA_RXALIGN(lp)) | |
2131 | tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl); | |
2132 | else | |
2133 | tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl); | |
1da177e4 LT |
2134 | tc_writel(0, &tr->TxPollCtr); /* Batch mode */ |
2135 | tc_writel(TX_THRESHOLD, &tr->TxThrsh); | |
2136 | tc_writel(INT_EN_CMD, &tr->Int_En); | |
2137 | ||
2138 | /* set queues */ | |
eea221ce | 2139 | tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas); |
1da177e4 LT |
2140 | tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base, |
2141 | &tr->FDA_Lim); | |
2142 | /* | |
2143 | * Activation method: | |
eea221ce | 2144 | * First, enable the MAC Transmitter and the DMA Receive circuits. |
1da177e4 LT |
2145 | * Then enable the DMA Transmitter and the MAC Receive circuits. |
2146 | */ | |
eea221ce | 2147 | tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */ |
1da177e4 | 2148 | tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */ |
eea221ce | 2149 | |
1da177e4 | 2150 | /* start MAC transmitter */ |
eea221ce | 2151 | /* TX4939 does not have EnLCarr */ |
c6686fe3 | 2152 | if (lp->chiptype == TC35815_TX4939) |
eea221ce | 2153 | txctl &= ~Tx_EnLCarr; |
1da177e4 | 2154 | /* WORKAROUND: ignore LostCrS in full duplex operation */ |
c6686fe3 | 2155 | if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL) |
eea221ce | 2156 | txctl &= ~Tx_EnLCarr; |
1da177e4 | 2157 | tc_writel(txctl, &tr->Tx_Ctl); |
eea221ce AN |
2158 | } |
2159 | ||
2160 | #ifdef CONFIG_PM | |
2161 | static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state) | |
2162 | { | |
2163 | struct net_device *dev = pci_get_drvdata(pdev); | |
ee79b7fb | 2164 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
2165 | unsigned long flags; |
2166 | ||
2167 | pci_save_state(pdev); | |
2168 | if (!netif_running(dev)) | |
2169 | return 0; | |
2170 | netif_device_detach(dev); | |
c6686fe3 AN |
2171 | if (lp->phy_dev) |
2172 | phy_stop(lp->phy_dev); | |
eea221ce | 2173 | spin_lock_irqsave(&lp->lock, flags); |
eea221ce | 2174 | tc35815_chip_reset(dev); |
1da177e4 | 2175 | spin_unlock_irqrestore(&lp->lock, flags); |
eea221ce AN |
2176 | pci_set_power_state(pdev, PCI_D3hot); |
2177 | return 0; | |
1da177e4 LT |
2178 | } |
2179 | ||
eea221ce AN |
2180 | static int tc35815_resume(struct pci_dev *pdev) |
2181 | { | |
2182 | struct net_device *dev = pci_get_drvdata(pdev); | |
ee79b7fb | 2183 | struct tc35815_local *lp = netdev_priv(dev); |
eea221ce AN |
2184 | |
2185 | pci_restore_state(pdev); | |
2186 | if (!netif_running(dev)) | |
2187 | return 0; | |
2188 | pci_set_power_state(pdev, PCI_D0); | |
eea221ce | 2189 | tc35815_restart(dev); |
59524a37 | 2190 | netif_carrier_off(dev); |
c6686fe3 AN |
2191 | if (lp->phy_dev) |
2192 | phy_start(lp->phy_dev); | |
eea221ce AN |
2193 | netif_device_attach(dev); |
2194 | return 0; | |
2195 | } | |
2196 | #endif /* CONFIG_PM */ | |
2197 | ||
2198 | static struct pci_driver tc35815_pci_driver = { | |
2199 | .name = MODNAME, | |
2200 | .id_table = tc35815_pci_tbl, | |
2201 | .probe = tc35815_init_one, | |
2202 | .remove = __devexit_p(tc35815_remove_one), | |
2203 | #ifdef CONFIG_PM | |
2204 | .suspend = tc35815_suspend, | |
2205 | .resume = tc35815_resume, | |
2206 | #endif | |
1da177e4 LT |
2207 | }; |
2208 | ||
eea221ce AN |
2209 | module_param_named(speed, options.speed, int, 0); |
2210 | MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps"); | |
2211 | module_param_named(duplex, options.duplex, int, 0); | |
2212 | MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full"); | |
eea221ce | 2213 | |
1da177e4 LT |
2214 | static int __init tc35815_init_module(void) |
2215 | { | |
eea221ce | 2216 | return pci_register_driver(&tc35815_pci_driver); |
1da177e4 LT |
2217 | } |
2218 | ||
2219 | static void __exit tc35815_cleanup_module(void) | |
2220 | { | |
eea221ce | 2221 | pci_unregister_driver(&tc35815_pci_driver); |
1da177e4 | 2222 | } |
420e8524 | 2223 | |
1da177e4 LT |
2224 | module_init(tc35815_init_module); |
2225 | module_exit(tc35815_cleanup_module); | |
eea221ce AN |
2226 | |
2227 | MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver"); | |
2228 | MODULE_LICENSE("GPL"); |