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tc35815: Kill non-napi code
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CommitLineData
eea221ce
AN
1/*
2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
1da177e4
LT
3 *
4 * Based on skelton.c by Donald Becker.
1da177e4 5 *
eea221ce
AN
6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
8 * -----<snip>-----
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
15 * -----<snip>-----
1da177e4 16 *
eea221ce
AN
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
1da177e4 20 *
eea221ce
AN
21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
1da177e4
LT
23 */
24
c6a2dbba 25#define DRV_VERSION "1.39"
eea221ce
AN
26static const char *version = "tc35815.c:v" DRV_VERSION "\n";
27#define MODNAME "tc35815"
1da177e4
LT
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/fcntl.h>
33#include <linux/interrupt.h>
34#include <linux/ioport.h>
35#include <linux/in.h>
82a9928d 36#include <linux/if_vlan.h>
1da177e4
LT
37#include <linux/slab.h>
38#include <linux/string.h>
eea221ce 39#include <linux/spinlock.h>
1da177e4
LT
40#include <linux/errno.h>
41#include <linux/init.h>
42#include <linux/netdevice.h>
43#include <linux/etherdevice.h>
44#include <linux/skbuff.h>
45#include <linux/delay.h>
46#include <linux/pci.h>
c6686fe3
AN
47#include <linux/phy.h>
48#include <linux/workqueue.h>
bd43da8f 49#include <linux/platform_device.h>
1da177e4 50#include <asm/io.h>
1da177e4
LT
51#include <asm/byteorder.h>
52
1da177e4
LT
53/* First, a few definitions that the brave might change. */
54
1da177e4 55#define GATHER_TXINT /* On-Demand Tx Interrupt */
eea221ce
AN
56#define WORKAROUND_LOSTCAR
57#define WORKAROUND_100HALF_PROMISC
58/* #define TC35815_USE_PACKEDBUFFER */
59
c6686fe3 60enum tc35815_chiptype {
eea221ce
AN
61 TC35815CF = 0,
62 TC35815_NWU,
63 TC35815_TX4939,
c6686fe3 64};
eea221ce 65
c6686fe3 66/* indexed by tc35815_chiptype, above */
eea221ce
AN
67static const struct {
68 const char *name;
c6686fe3 69} chip_info[] __devinitdata = {
eea221ce
AN
70 { "TOSHIBA TC35815CF 10/100BaseTX" },
71 { "TOSHIBA TC35815 with Wake on LAN" },
72 { "TOSHIBA TC35815/TX4939" },
73};
74
75static const struct pci_device_id tc35815_pci_tbl[] = {
76 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
77 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
78 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
79 {0,}
80};
7f225b42 81MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
1da177e4 82
eea221ce
AN
83/* see MODULE_PARM_DESC */
84static struct tc35815_options {
85 int speed;
86 int duplex;
eea221ce 87} options;
1da177e4
LT
88
89/*
90 * Registers
91 */
92struct tc35815_regs {
22adf7e5
AN
93 __u32 DMA_Ctl; /* 0x00 */
94 __u32 TxFrmPtr;
95 __u32 TxThrsh;
96 __u32 TxPollCtr;
97 __u32 BLFrmPtr;
98 __u32 RxFragSize;
99 __u32 Int_En;
100 __u32 FDA_Bas;
101 __u32 FDA_Lim; /* 0x20 */
102 __u32 Int_Src;
103 __u32 unused0[2];
104 __u32 PauseCnt;
105 __u32 RemPauCnt;
106 __u32 TxCtlFrmStat;
107 __u32 unused1;
108 __u32 MAC_Ctl; /* 0x40 */
109 __u32 CAM_Ctl;
110 __u32 Tx_Ctl;
111 __u32 Tx_Stat;
112 __u32 Rx_Ctl;
113 __u32 Rx_Stat;
114 __u32 MD_Data;
115 __u32 MD_CA;
116 __u32 CAM_Adr; /* 0x60 */
117 __u32 CAM_Data;
118 __u32 CAM_Ena;
119 __u32 PROM_Ctl;
120 __u32 PROM_Data;
121 __u32 Algn_Cnt;
122 __u32 CRC_Cnt;
123 __u32 Miss_Cnt;
1da177e4
LT
124};
125
126/*
127 * Bit assignments
128 */
129/* DMA_Ctl bit asign ------------------------------------------------------- */
7f225b42
AN
130#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
131#define DMA_RxAlign_1 0x00400000
132#define DMA_RxAlign_2 0x00800000
133#define DMA_RxAlign_3 0x00c00000
134#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
135#define DMA_IntMask 0x00040000 /* 1:Interupt mask */
136#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
137#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
138#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
139#define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
140#define DMA_TestMode 0x00002000 /* 1:Test Mode */
141#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
142#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
1da177e4
LT
143
144/* RxFragSize bit asign ---------------------------------------------------- */
7f225b42
AN
145#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
146#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
1da177e4
LT
147
148/* MAC_Ctl bit asign ------------------------------------------------------- */
7f225b42
AN
149#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
150#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
151#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
152#define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
153#define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
154#define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
155#define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
156#define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
157#define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
158#define MAC_Reset 0x00000004 /* 1:Software Reset */
159#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
160#define MAC_HaltReq 0x00000001 /* 1:Halt request */
1da177e4
LT
161
162/* PROM_Ctl bit asign ------------------------------------------------------ */
7f225b42
AN
163#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
164#define PROM_Read 0x00004000 /*10:Read operation */
165#define PROM_Write 0x00002000 /*01:Write operation */
166#define PROM_Erase 0x00006000 /*11:Erase operation */
167 /*00:Enable or Disable Writting, */
168 /* as specified in PROM_Addr. */
169#define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
170 /*00xxxx: disable */
1da177e4
LT
171
172/* CAM_Ctl bit asign ------------------------------------------------------- */
7f225b42
AN
173#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
174#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
175 /* accept other */
176#define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
177#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
178#define CAM_StationAcc 0x00000001 /* 1:unicast accept */
1da177e4
LT
179
180/* CAM_Ena bit asign ------------------------------------------------------- */
7f225b42 181#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
1da177e4 182#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
7f225b42 183#define CAM_Ena_Bit(index) (1 << (index))
1da177e4
LT
184#define CAM_ENTRY_DESTINATION 0
185#define CAM_ENTRY_SOURCE 1
186#define CAM_ENTRY_MACCTL 20
187
188/* Tx_Ctl bit asign -------------------------------------------------------- */
7f225b42
AN
189#define Tx_En 0x00000001 /* 1:Transmit enable */
190#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
191#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
192#define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
193#define Tx_FBack 0x00000010 /* 1:Fast Back-off */
194#define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
195#define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
196#define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
197#define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
198#define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
199#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
200#define Tx_EnComp 0x00004000 /* 1:Enable Completion */
1da177e4
LT
201
202/* Tx_Stat bit asign ------------------------------------------------------- */
7f225b42
AN
203#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
204#define Tx_ExColl 0x00000010 /* Excessive Collision */
205#define Tx_TXDefer 0x00000020 /* Transmit Defered */
206#define Tx_Paused 0x00000040 /* Transmit Paused */
207#define Tx_IntTx 0x00000080 /* Interrupt on Tx */
208#define Tx_Under 0x00000100 /* Underrun */
209#define Tx_Defer 0x00000200 /* Deferral */
210#define Tx_NCarr 0x00000400 /* No Carrier */
211#define Tx_10Stat 0x00000800 /* 10Mbps Status */
212#define Tx_LateColl 0x00001000 /* Late Collision */
213#define Tx_TxPar 0x00002000 /* Tx Parity Error */
214#define Tx_Comp 0x00004000 /* Completion */
215#define Tx_Halted 0x00008000 /* Tx Halted */
216#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
1da177e4
LT
217
218/* Rx_Ctl bit asign -------------------------------------------------------- */
7f225b42
AN
219#define Rx_EnGood 0x00004000 /* 1:Enable Good */
220#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
221#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
222#define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
223#define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
224#define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
225#define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
226#define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
227#define Rx_ShortEn 0x00000008 /* 1:Short Enable */
228#define Rx_LongEn 0x00000004 /* 1:Long Enable */
229#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
230#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
1da177e4
LT
231
232/* Rx_Stat bit asign ------------------------------------------------------- */
7f225b42
AN
233#define Rx_Halted 0x00008000 /* Rx Halted */
234#define Rx_Good 0x00004000 /* Rx Good */
235#define Rx_RxPar 0x00002000 /* Rx Parity Error */
842e08bd 236#define Rx_TypePkt 0x00001000 /* Rx Type Packet */
7f225b42
AN
237#define Rx_LongErr 0x00000800 /* Rx Long Error */
238#define Rx_Over 0x00000400 /* Rx Overflow */
239#define Rx_CRCErr 0x00000200 /* Rx CRC Error */
240#define Rx_Align 0x00000100 /* Rx Alignment Error */
241#define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
242#define Rx_IntRx 0x00000040 /* Rx Interrupt */
243#define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
842e08bd 244#define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
7f225b42 245
842e08bd 246#define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
1da177e4
LT
247
248/* Int_En bit asign -------------------------------------------------------- */
7f225b42
AN
249#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
250#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
251#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
252#define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
253#define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
254#define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
255#define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
256#define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
257#define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
258#define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
259#define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
260#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
261 /* Exhausted Enable */
1da177e4
LT
262
263/* Int_Src bit asign ------------------------------------------------------- */
7f225b42
AN
264#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
265#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
266#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
267#define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
268#define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
269#define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
270#define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
271#define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
272#define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
273#define Int_SWInt 0x00000020 /* 1:Software request & Clear */
274#define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
275#define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
276#define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
277#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
278#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
1da177e4
LT
279
280/* MD_CA bit asign --------------------------------------------------------- */
7f225b42
AN
281#define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
282#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
283#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
1da177e4
LT
284
285
1da177e4
LT
286/*
287 * Descriptors
288 */
289
290/* Frame descripter */
291struct FDesc {
292 volatile __u32 FDNext;
293 volatile __u32 FDSystem;
294 volatile __u32 FDStat;
295 volatile __u32 FDCtl;
296};
297
298/* Buffer descripter */
299struct BDesc {
300 volatile __u32 BuffData;
301 volatile __u32 BDCtl;
302};
303
304#define FD_ALIGN 16
305
306/* Frame Descripter bit asign ---------------------------------------------- */
7f225b42
AN
307#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
308#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
309#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
1da177e4 310#define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
7f225b42
AN
311#define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
312#define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
1da177e4
LT
313#define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
314#define FD_FrmOpt_Packing 0x04000000 /* Rx only */
7f225b42
AN
315#define FD_CownsFD 0x80000000 /* FD Controller owner bit */
316#define FD_Next_EOL 0x00000001 /* FD EOL indicator */
317#define FD_BDCnt_SHIFT 16
1da177e4
LT
318
319/* Buffer Descripter bit asign --------------------------------------------- */
7f225b42
AN
320#define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
321#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
322#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
323#define BD_CownsBD 0x80000000 /* BD Controller owner bit */
324#define BD_RxBDID_SHIFT 16
1da177e4
LT
325#define BD_RxBDSeqN_SHIFT 24
326
327
328/* Some useful constants. */
329#undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
330
331#ifdef NO_CHECK_CARRIER
332#define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
eea221ce
AN
333 Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
334 Tx_En) /* maybe 0x7b01 */
1da177e4
LT
335#else
336#define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
eea221ce
AN
337 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
338 Tx_En) /* maybe 0x7b01 */
1da177e4 339#endif
297713de 340/* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
1da177e4 341#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
297713de 342 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
1da177e4 343#define INT_EN_CMD (Int_NRAbtEn | \
eea221ce 344 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
1da177e4
LT
345 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
346 Int_STargAbtEn | \
347 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
eea221ce 348#define DMA_CTL_CMD DMA_BURST_SIZE
c6686fe3 349#define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
1da177e4
LT
350
351/* Tuning parameters */
352#define DMA_BURST_SIZE 32
353#define TX_THRESHOLD 1024
7f225b42
AN
354/* used threshold with packet max byte for low pci transfer ability.*/
355#define TX_THRESHOLD_MAX 1536
356/* setting threshold max value when overrun error occured this count. */
357#define TX_THRESHOLD_KEEP_LIMIT 10
1da177e4 358
eea221ce
AN
359/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
360#ifdef TC35815_USE_PACKEDBUFFER
1da177e4 361#define FD_PAGE_NUM 2
eea221ce 362#define RX_BUF_NUM 8 /* >= 2 */
1da177e4
LT
363#define RX_FD_NUM 250 /* >= 32 */
364#define TX_FD_NUM 128
eea221ce
AN
365#define RX_BUF_SIZE PAGE_SIZE
366#else /* TC35815_USE_PACKEDBUFFER */
367#define FD_PAGE_NUM 4
368#define RX_BUF_NUM 128 /* < 256 */
369#define RX_FD_NUM 256 /* >= 32 */
370#define TX_FD_NUM 128
371#if RX_CTL_CMD & Rx_LongEn
372#define RX_BUF_SIZE PAGE_SIZE
373#elif RX_CTL_CMD & Rx_StripCRC
82a9928d
AN
374#define RX_BUF_SIZE \
375 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
eea221ce 376#else
82a9928d
AN
377#define RX_BUF_SIZE \
378 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
eea221ce
AN
379#endif
380#endif /* TC35815_USE_PACKEDBUFFER */
381#define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
382#define NAPI_WEIGHT 16
1da177e4
LT
383
384struct TxFD {
385 struct FDesc fd;
386 struct BDesc bd;
387 struct BDesc unused;
388};
389
390struct RxFD {
391 struct FDesc fd;
392 struct BDesc bd[0]; /* variable length */
393};
394
395struct FrFD {
396 struct FDesc fd;
eea221ce 397 struct BDesc bd[RX_BUF_NUM];
1da177e4
LT
398};
399
400
22adf7e5
AN
401#define tc_readl(addr) ioread32(addr)
402#define tc_writel(d, addr) iowrite32(d, addr)
1da177e4 403
eea221ce
AN
404#define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
405
c6686fe3 406/* Information that need to be kept for each controller. */
1da177e4 407struct tc35815_local {
eea221ce 408 struct pci_dev *pci_dev;
1da177e4 409
bea3348e
SH
410 struct net_device *dev;
411 struct napi_struct napi;
412
1da177e4 413 /* statistics */
1da177e4
LT
414 struct {
415 int max_tx_qlen;
416 int tx_ints;
417 int rx_ints;
7f225b42 418 int tx_underrun;
1da177e4
LT
419 } lstats;
420
eea221ce
AN
421 /* Tx control lock. This protects the transmit buffer ring
422 * state along with the "tx full" state of the driver. This
423 * means all netif_queue flow control actions are protected
424 * by this lock as well.
425 */
426 spinlock_t lock;
427
298cf9be 428 struct mii_bus *mii_bus;
c6686fe3
AN
429 struct phy_device *phy_dev;
430 int duplex;
431 int speed;
432 int link;
433 struct work_struct restart_work;
1da177e4
LT
434
435 /*
436 * Transmitting: Batch Mode.
437 * 1 BD in 1 TxFD.
eea221ce 438 * Receiving: Packing Mode. (TC35815_USE_PACKEDBUFFER)
1da177e4 439 * 1 circular FD for Free Buffer List.
eea221ce 440 * RX_BUF_NUM BD in Free Buffer FD.
1da177e4 441 * One Free Buffer BD has PAGE_SIZE data buffer.
eea221ce
AN
442 * Or Non-Packing Mode.
443 * 1 circular FD for Free Buffer List.
444 * RX_BUF_NUM BD in Free Buffer FD.
445 * One Free Buffer BD has ETH_FRAME_LEN data buffer.
1da177e4 446 */
7f225b42 447 void *fd_buf; /* for TxFD, RxFD, FrFD */
eea221ce 448 dma_addr_t fd_buf_dma;
1da177e4 449 struct TxFD *tfd_base;
eea221ce
AN
450 unsigned int tfd_start;
451 unsigned int tfd_end;
1da177e4
LT
452 struct RxFD *rfd_base;
453 struct RxFD *rfd_limit;
454 struct RxFD *rfd_cur;
455 struct FrFD *fbl_ptr;
eea221ce 456#ifdef TC35815_USE_PACKEDBUFFER
1da177e4 457 unsigned char fbl_curid;
7f225b42 458 void *data_buf[RX_BUF_NUM]; /* packing */
eea221ce
AN
459 dma_addr_t data_buf_dma[RX_BUF_NUM];
460 struct {
461 struct sk_buff *skb;
462 dma_addr_t skb_dma;
463 } tx_skbs[TX_FD_NUM];
464#else
465 unsigned int fbl_count;
466 struct {
467 struct sk_buff *skb;
468 dma_addr_t skb_dma;
469 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
470#endif
eea221ce 471 u32 msg_enable;
c6686fe3 472 enum tc35815_chiptype chiptype;
1da177e4
LT
473};
474
eea221ce
AN
475static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
476{
477 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
478}
479#ifdef DEBUG
480static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
481{
482 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
483}
484#endif
485#ifdef TC35815_USE_PACKEDBUFFER
486static inline void *rxbuf_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
487{
488 int i;
489 for (i = 0; i < RX_BUF_NUM; i++) {
490 if (bus >= lp->data_buf_dma[i] &&
491 bus < lp->data_buf_dma[i] + PAGE_SIZE)
492 return (void *)((u8 *)lp->data_buf[i] +
493 (bus - lp->data_buf_dma[i]));
494 }
495 return NULL;
496}
497
498#define TC35815_DMA_SYNC_ONDEMAND
7f225b42 499static void *alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
eea221ce
AN
500{
501#ifdef TC35815_DMA_SYNC_ONDEMAND
502 void *buf;
503 /* pci_map + pci_dma_sync will be more effective than
504 * pci_alloc_consistent on some archs. */
7f225b42
AN
505 buf = (void *)__get_free_page(GFP_ATOMIC);
506 if (!buf)
eea221ce
AN
507 return NULL;
508 *dma_handle = pci_map_single(hwdev, buf, PAGE_SIZE,
509 PCI_DMA_FROMDEVICE);
8d8bb39b 510 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
eea221ce
AN
511 free_page((unsigned long)buf);
512 return NULL;
513 }
514 return buf;
515#else
516 return pci_alloc_consistent(hwdev, PAGE_SIZE, dma_handle);
517#endif
518}
519
520static void free_rxbuf_page(struct pci_dev *hwdev, void *buf, dma_addr_t dma_handle)
521{
522#ifdef TC35815_DMA_SYNC_ONDEMAND
523 pci_unmap_single(hwdev, dma_handle, PAGE_SIZE, PCI_DMA_FROMDEVICE);
524 free_page((unsigned long)buf);
525#else
526 pci_free_consistent(hwdev, PAGE_SIZE, buf, dma_handle);
527#endif
528}
529#else /* TC35815_USE_PACKEDBUFFER */
530static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
531 struct pci_dev *hwdev,
532 dma_addr_t *dma_handle)
533{
534 struct sk_buff *skb;
535 skb = dev_alloc_skb(RX_BUF_SIZE);
536 if (!skb)
537 return NULL;
eea221ce
AN
538 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
539 PCI_DMA_FROMDEVICE);
8d8bb39b 540 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
eea221ce
AN
541 dev_kfree_skb_any(skb);
542 return NULL;
543 }
544 skb_reserve(skb, 2); /* make IP header 4byte aligned */
545 return skb;
546}
547
548static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
549{
550 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
551 PCI_DMA_FROMDEVICE);
552 dev_kfree_skb_any(skb);
553}
554#endif /* TC35815_USE_PACKEDBUFFER */
1da177e4 555
eea221ce 556/* Index to functions, as function prototypes. */
1da177e4
LT
557
558static int tc35815_open(struct net_device *dev);
559static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
eea221ce 560static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
eea221ce 561static int tc35815_rx(struct net_device *dev, int limit);
bea3348e 562static int tc35815_poll(struct napi_struct *napi, int budget);
1da177e4
LT
563static void tc35815_txdone(struct net_device *dev);
564static int tc35815_close(struct net_device *dev);
565static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
566static void tc35815_set_multicast_list(struct net_device *dev);
7f225b42 567static void tc35815_tx_timeout(struct net_device *dev);
eea221ce
AN
568static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
569#ifdef CONFIG_NET_POLL_CONTROLLER
570static void tc35815_poll_controller(struct net_device *dev);
571#endif
572static const struct ethtool_ops tc35815_ethtool_ops;
1da177e4 573
eea221ce 574/* Example routines you must write ;->. */
7f225b42
AN
575static void tc35815_chip_reset(struct net_device *dev);
576static void tc35815_chip_init(struct net_device *dev);
1da177e4 577
eea221ce
AN
578#ifdef DEBUG
579static void panic_queues(struct net_device *dev);
580#endif
1da177e4 581
c6686fe3
AN
582static void tc35815_restart_work(struct work_struct *work);
583
584static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
585{
586 struct net_device *dev = bus->priv;
587 struct tc35815_regs __iomem *tr =
588 (struct tc35815_regs __iomem *)dev->base_addr;
c60a5cf7 589 unsigned long timeout = jiffies + HZ;
c6686fe3
AN
590
591 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
c60a5cf7 592 udelay(12); /* it takes 32 x 400ns at least */
c6686fe3
AN
593 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
594 if (time_after(jiffies, timeout))
595 return -EIO;
596 cpu_relax();
597 }
598 return tc_readl(&tr->MD_Data) & 0xffff;
599}
600
601static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
602{
603 struct net_device *dev = bus->priv;
604 struct tc35815_regs __iomem *tr =
605 (struct tc35815_regs __iomem *)dev->base_addr;
c60a5cf7 606 unsigned long timeout = jiffies + HZ;
c6686fe3
AN
607
608 tc_writel(val, &tr->MD_Data);
609 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
610 &tr->MD_CA);
c60a5cf7 611 udelay(12); /* it takes 32 x 400ns at least */
c6686fe3
AN
612 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
613 if (time_after(jiffies, timeout))
614 return -EIO;
615 cpu_relax();
616 }
617 return 0;
618}
619
620static void tc_handle_link_change(struct net_device *dev)
621{
622 struct tc35815_local *lp = netdev_priv(dev);
623 struct phy_device *phydev = lp->phy_dev;
624 unsigned long flags;
625 int status_change = 0;
626
627 spin_lock_irqsave(&lp->lock, flags);
628 if (phydev->link &&
629 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
630 struct tc35815_regs __iomem *tr =
631 (struct tc35815_regs __iomem *)dev->base_addr;
632 u32 reg;
633
634 reg = tc_readl(&tr->MAC_Ctl);
635 reg |= MAC_HaltReq;
636 tc_writel(reg, &tr->MAC_Ctl);
637 if (phydev->duplex == DUPLEX_FULL)
638 reg |= MAC_FullDup;
639 else
640 reg &= ~MAC_FullDup;
641 tc_writel(reg, &tr->MAC_Ctl);
642 reg &= ~MAC_HaltReq;
643 tc_writel(reg, &tr->MAC_Ctl);
644
645 /*
646 * TX4939 PCFG.SPEEDn bit will be changed on
647 * NETDEV_CHANGE event.
648 */
649
650#if !defined(NO_CHECK_CARRIER) && defined(WORKAROUND_LOSTCAR)
651 /*
652 * WORKAROUND: enable LostCrS only if half duplex
653 * operation.
654 * (TX4939 does not have EnLCarr)
655 */
656 if (phydev->duplex == DUPLEX_HALF &&
657 lp->chiptype != TC35815_TX4939)
658 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
659 &tr->Tx_Ctl);
660#endif
661
662 lp->speed = phydev->speed;
663 lp->duplex = phydev->duplex;
664 status_change = 1;
665 }
666
667 if (phydev->link != lp->link) {
668 if (phydev->link) {
669#ifdef WORKAROUND_100HALF_PROMISC
670 /* delayed promiscuous enabling */
671 if (dev->flags & IFF_PROMISC)
672 tc35815_set_multicast_list(dev);
673#endif
c6686fe3
AN
674 } else {
675 lp->speed = 0;
676 lp->duplex = -1;
677 }
678 lp->link = phydev->link;
679
680 status_change = 1;
681 }
682 spin_unlock_irqrestore(&lp->lock, flags);
683
684 if (status_change && netif_msg_link(lp)) {
685 phy_print_status(phydev);
72903831
JP
686 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
687 dev->name,
688 phy_read(phydev, MII_BMCR),
689 phy_read(phydev, MII_BMSR),
690 phy_read(phydev, MII_LPA));
c6686fe3
AN
691 }
692}
693
694static int tc_mii_probe(struct net_device *dev)
695{
696 struct tc35815_local *lp = netdev_priv(dev);
697 struct phy_device *phydev = NULL;
698 int phy_addr;
699 u32 dropmask;
700
701 /* find the first phy */
702 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
298cf9be 703 if (lp->mii_bus->phy_map[phy_addr]) {
c6686fe3
AN
704 if (phydev) {
705 printk(KERN_ERR "%s: multiple PHYs found\n",
706 dev->name);
707 return -EINVAL;
708 }
298cf9be 709 phydev = lp->mii_bus->phy_map[phy_addr];
c6686fe3
AN
710 break;
711 }
712 }
713
714 if (!phydev) {
715 printk(KERN_ERR "%s: no PHY found\n", dev->name);
716 return -ENODEV;
717 }
718
719 /* attach the mac to the phy */
db1d7bf7 720 phydev = phy_connect(dev, dev_name(&phydev->dev),
c6686fe3
AN
721 &tc_handle_link_change, 0,
722 lp->chiptype == TC35815_TX4939 ?
723 PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
724 if (IS_ERR(phydev)) {
725 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
726 return PTR_ERR(phydev);
727 }
728 printk(KERN_INFO "%s: attached PHY driver [%s] "
729 "(mii_bus:phy_addr=%s, id=%x)\n",
db1d7bf7 730 dev->name, phydev->drv->name, dev_name(&phydev->dev),
c6686fe3
AN
731 phydev->phy_id);
732
733 /* mask with MAC supported features */
734 phydev->supported &= PHY_BASIC_FEATURES;
735 dropmask = 0;
736 if (options.speed == 10)
737 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
738 else if (options.speed == 100)
739 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
740 if (options.duplex == 1)
741 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
742 else if (options.duplex == 2)
743 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
744 phydev->supported &= ~dropmask;
745 phydev->advertising = phydev->supported;
746
747 lp->link = 0;
748 lp->speed = 0;
749 lp->duplex = -1;
750 lp->phy_dev = phydev;
751
752 return 0;
753}
754
755static int tc_mii_init(struct net_device *dev)
756{
757 struct tc35815_local *lp = netdev_priv(dev);
758 int err;
759 int i;
760
298cf9be
LB
761 lp->mii_bus = mdiobus_alloc();
762 if (lp->mii_bus == NULL) {
c6686fe3
AN
763 err = -ENOMEM;
764 goto err_out;
765 }
766
298cf9be
LB
767 lp->mii_bus->name = "tc35815_mii_bus";
768 lp->mii_bus->read = tc_mdio_read;
769 lp->mii_bus->write = tc_mdio_write;
770 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
771 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
772 lp->mii_bus->priv = dev;
773 lp->mii_bus->parent = &lp->pci_dev->dev;
774 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
775 if (!lp->mii_bus->irq) {
776 err = -ENOMEM;
777 goto err_out_free_mii_bus;
778 }
779
c6686fe3 780 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 781 lp->mii_bus->irq[i] = PHY_POLL;
c6686fe3 782
298cf9be 783 err = mdiobus_register(lp->mii_bus);
c6686fe3
AN
784 if (err)
785 goto err_out_free_mdio_irq;
786 err = tc_mii_probe(dev);
787 if (err)
788 goto err_out_unregister_bus;
789 return 0;
790
791err_out_unregister_bus:
298cf9be 792 mdiobus_unregister(lp->mii_bus);
c6686fe3 793err_out_free_mdio_irq:
298cf9be 794 kfree(lp->mii_bus->irq);
51cf756c 795err_out_free_mii_bus:
298cf9be 796 mdiobus_free(lp->mii_bus);
c6686fe3
AN
797err_out:
798 return err;
799}
1da177e4 800
bd43da8f
AN
801#ifdef CONFIG_CPU_TX49XX
802/*
803 * Find a platform_device providing a MAC address. The platform code
804 * should provide a "tc35815-mac" device with a MAC address in its
805 * platform_data.
806 */
807static int __devinit tc35815_mac_match(struct device *dev, void *data)
808{
809 struct platform_device *plat_dev = to_platform_device(dev);
810 struct pci_dev *pci_dev = data;
06675e6f 811 unsigned int id = pci_dev->irq;
bd43da8f
AN
812 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
813}
814
815static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
816{
ee79b7fb 817 struct tc35815_local *lp = netdev_priv(dev);
bd43da8f
AN
818 struct device *pd = bus_find_device(&platform_bus_type, NULL,
819 lp->pci_dev, tc35815_mac_match);
820 if (pd) {
821 if (pd->platform_data)
822 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
823 put_device(pd);
824 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
825 }
826 return -ENODEV;
827}
828#else
308a9068 829static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
bd43da8f
AN
830{
831 return -ENODEV;
832}
833#endif
834
7f225b42 835static int __devinit tc35815_init_dev_addr(struct net_device *dev)
eea221ce
AN
836{
837 struct tc35815_regs __iomem *tr =
838 (struct tc35815_regs __iomem *)dev->base_addr;
839 int i;
840
eea221ce
AN
841 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
842 ;
843 for (i = 0; i < 6; i += 2) {
844 unsigned short data;
845 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
846 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
847 ;
848 data = tc_readl(&tr->PROM_Data);
849 dev->dev_addr[i] = data & 0xff;
850 dev->dev_addr[i+1] = data >> 8;
851 }
bd43da8f
AN
852 if (!is_valid_ether_addr(dev->dev_addr))
853 return tc35815_read_plat_dev_addr(dev);
854 return 0;
eea221ce 855}
1da177e4 856
5a1c28b3
AB
857static const struct net_device_ops tc35815_netdev_ops = {
858 .ndo_open = tc35815_open,
859 .ndo_stop = tc35815_close,
860 .ndo_start_xmit = tc35815_send_packet,
861 .ndo_get_stats = tc35815_get_stats,
862 .ndo_set_multicast_list = tc35815_set_multicast_list,
863 .ndo_tx_timeout = tc35815_tx_timeout,
864 .ndo_do_ioctl = tc35815_ioctl,
865 .ndo_validate_addr = eth_validate_addr,
866 .ndo_change_mtu = eth_change_mtu,
867 .ndo_set_mac_address = eth_mac_addr,
868#ifdef CONFIG_NET_POLL_CONTROLLER
869 .ndo_poll_controller = tc35815_poll_controller,
870#endif
871};
872
7f225b42
AN
873static int __devinit tc35815_init_one(struct pci_dev *pdev,
874 const struct pci_device_id *ent)
1da177e4 875{
eea221ce
AN
876 void __iomem *ioaddr = NULL;
877 struct net_device *dev;
878 struct tc35815_local *lp;
879 int rc;
eea221ce
AN
880
881 static int printed_version;
882 if (!printed_version++) {
883 printk(version);
884 dev_printk(KERN_DEBUG, &pdev->dev,
c6686fe3
AN
885 "speed:%d duplex:%d\n",
886 options.speed, options.duplex);
eea221ce
AN
887 }
888
889 if (!pdev->irq) {
890 dev_warn(&pdev->dev, "no IRQ assigned.\n");
891 return -ENODEV;
892 }
1da177e4 893
eea221ce 894 /* dev zeroed in alloc_etherdev */
7f225b42 895 dev = alloc_etherdev(sizeof(*lp));
eea221ce
AN
896 if (dev == NULL) {
897 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
898 return -ENOMEM;
899 }
eea221ce 900 SET_NETDEV_DEV(dev, &pdev->dev);
ee79b7fb 901 lp = netdev_priv(dev);
bea3348e 902 lp->dev = dev;
1da177e4 903
eea221ce 904 /* enable device (incl. PCI PM wakeup), and bus-mastering */
22adf7e5 905 rc = pcim_enable_device(pdev);
eea221ce
AN
906 if (rc)
907 goto err_out;
22adf7e5 908 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
eea221ce 909 if (rc)
1da177e4 910 goto err_out;
22adf7e5
AN
911 pci_set_master(pdev);
912 ioaddr = pcim_iomap_table(pdev)[1];
1da177e4 913
eea221ce 914 /* Initialize the device structure. */
5a1c28b3 915 dev->netdev_ops = &tc35815_netdev_ops;
eea221ce 916 dev->ethtool_ops = &tc35815_ethtool_ops;
eea221ce 917 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
bea3348e 918 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
1da177e4 919
eea221ce 920 dev->irq = pdev->irq;
7f225b42 921 dev->base_addr = (unsigned long)ioaddr;
1da177e4 922
c6686fe3 923 INIT_WORK(&lp->restart_work, tc35815_restart_work);
eea221ce
AN
924 spin_lock_init(&lp->lock);
925 lp->pci_dev = pdev;
c6686fe3 926 lp->chiptype = ent->driver_data;
1da177e4 927
eea221ce
AN
928 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
929 pci_set_drvdata(pdev, dev);
1da177e4 930
eea221ce 931 /* Soft reset the chip. */
1da177e4
LT
932 tc35815_chip_reset(dev);
933
eea221ce 934 /* Retrieve the ethernet address. */
bd43da8f
AN
935 if (tc35815_init_dev_addr(dev)) {
936 dev_warn(&pdev->dev, "not valid ether addr\n");
937 random_ether_addr(dev->dev_addr);
938 }
eea221ce 939
7f225b42 940 rc = register_netdev(dev);
eea221ce 941 if (rc)
22adf7e5 942 goto err_out;
eea221ce
AN
943
944 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
e174961c 945 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
eea221ce 946 dev->name,
c6686fe3 947 chip_info[ent->driver_data].name,
eea221ce 948 dev->base_addr,
e174961c 949 dev->dev_addr,
eea221ce
AN
950 dev->irq);
951
c6686fe3
AN
952 rc = tc_mii_init(dev);
953 if (rc)
954 goto err_out_unregister;
1da177e4 955
eea221ce 956 return 0;
1da177e4 957
c6686fe3
AN
958err_out_unregister:
959 unregister_netdev(dev);
eea221ce 960err_out:
7f225b42 961 free_netdev(dev);
eea221ce
AN
962 return rc;
963}
1da177e4 964
1da177e4 965
7f225b42 966static void __devexit tc35815_remove_one(struct pci_dev *pdev)
eea221ce 967{
7f225b42 968 struct net_device *dev = pci_get_drvdata(pdev);
c6686fe3 969 struct tc35815_local *lp = netdev_priv(dev);
1da177e4 970
c6686fe3 971 phy_disconnect(lp->phy_dev);
298cf9be
LB
972 mdiobus_unregister(lp->mii_bus);
973 kfree(lp->mii_bus->irq);
974 mdiobus_free(lp->mii_bus);
7f225b42
AN
975 unregister_netdev(dev);
976 free_netdev(dev);
977 pci_set_drvdata(pdev, NULL);
1da177e4
LT
978}
979
1da177e4
LT
980static int
981tc35815_init_queues(struct net_device *dev)
982{
ee79b7fb 983 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT
984 int i;
985 unsigned long fd_addr;
986
987 if (!lp->fd_buf) {
eea221ce
AN
988 BUG_ON(sizeof(struct FDesc) +
989 sizeof(struct BDesc) * RX_BUF_NUM +
990 sizeof(struct FDesc) * RX_FD_NUM +
991 sizeof(struct TxFD) * TX_FD_NUM >
992 PAGE_SIZE * FD_PAGE_NUM);
1da177e4 993
7f225b42
AN
994 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
995 PAGE_SIZE * FD_PAGE_NUM,
996 &lp->fd_buf_dma);
997 if (!lp->fd_buf)
1da177e4 998 return -ENOMEM;
eea221ce
AN
999 for (i = 0; i < RX_BUF_NUM; i++) {
1000#ifdef TC35815_USE_PACKEDBUFFER
7f225b42
AN
1001 lp->data_buf[i] =
1002 alloc_rxbuf_page(lp->pci_dev,
1003 &lp->data_buf_dma[i]);
1004 if (!lp->data_buf[i]) {
1da177e4 1005 while (--i >= 0) {
eea221ce
AN
1006 free_rxbuf_page(lp->pci_dev,
1007 lp->data_buf[i],
1008 lp->data_buf_dma[i]);
1009 lp->data_buf[i] = NULL;
1da177e4 1010 }
eea221ce
AN
1011 pci_free_consistent(lp->pci_dev,
1012 PAGE_SIZE * FD_PAGE_NUM,
1013 lp->fd_buf,
1014 lp->fd_buf_dma);
1015 lp->fd_buf = NULL;
1016 return -ENOMEM;
1017 }
1018#else
1019 lp->rx_skbs[i].skb =
1020 alloc_rxbuf_skb(dev, lp->pci_dev,
1021 &lp->rx_skbs[i].skb_dma);
1022 if (!lp->rx_skbs[i].skb) {
1023 while (--i >= 0) {
1024 free_rxbuf_skb(lp->pci_dev,
1025 lp->rx_skbs[i].skb,
1026 lp->rx_skbs[i].skb_dma);
1027 lp->rx_skbs[i].skb = NULL;
1028 }
1029 pci_free_consistent(lp->pci_dev,
1030 PAGE_SIZE * FD_PAGE_NUM,
1031 lp->fd_buf,
1032 lp->fd_buf_dma);
1033 lp->fd_buf = NULL;
1da177e4
LT
1034 return -ENOMEM;
1035 }
1da177e4
LT
1036#endif
1037 }
eea221ce
AN
1038 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
1039 dev->name, lp->fd_buf);
1040#ifdef TC35815_USE_PACKEDBUFFER
1041 printk(" DataBuf");
1042 for (i = 0; i < RX_BUF_NUM; i++)
1043 printk(" %p", lp->data_buf[i]);
1da177e4 1044#endif
eea221ce 1045 printk("\n");
1da177e4 1046 } else {
7f225b42
AN
1047 for (i = 0; i < FD_PAGE_NUM; i++)
1048 clear_page((void *)((unsigned long)lp->fd_buf +
1049 i * PAGE_SIZE));
1da177e4 1050 }
1da177e4 1051 fd_addr = (unsigned long)lp->fd_buf;
1da177e4
LT
1052
1053 /* Free Descriptors (for Receive) */
1054 lp->rfd_base = (struct RxFD *)fd_addr;
1055 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
7f225b42 1056 for (i = 0; i < RX_FD_NUM; i++)
1da177e4 1057 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
1da177e4 1058 lp->rfd_cur = lp->rfd_base;
eea221ce 1059 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
1da177e4
LT
1060
1061 /* Transmit Descriptors */
1062 lp->tfd_base = (struct TxFD *)fd_addr;
1063 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
1064 for (i = 0; i < TX_FD_NUM; i++) {
eea221ce
AN
1065 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
1066 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1da177e4
LT
1067 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
1068 }
eea221ce 1069 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
1da177e4
LT
1070 lp->tfd_start = 0;
1071 lp->tfd_end = 0;
1072
1073 /* Buffer List (for Receive) */
1074 lp->fbl_ptr = (struct FrFD *)fd_addr;
eea221ce
AN
1075 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
1076 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
1077#ifndef TC35815_USE_PACKEDBUFFER
1078 /*
1079 * move all allocated skbs to head of rx_skbs[] array.
1080 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
1081 * tc35815_rx() had failed.
1082 */
1083 lp->fbl_count = 0;
1084 for (i = 0; i < RX_BUF_NUM; i++) {
1085 if (lp->rx_skbs[i].skb) {
1086 if (i != lp->fbl_count) {
1087 lp->rx_skbs[lp->fbl_count].skb =
1088 lp->rx_skbs[i].skb;
1089 lp->rx_skbs[lp->fbl_count].skb_dma =
1090 lp->rx_skbs[i].skb_dma;
1091 }
1092 lp->fbl_count++;
1093 }
1094 }
1095#endif
1096 for (i = 0; i < RX_BUF_NUM; i++) {
1097#ifdef TC35815_USE_PACKEDBUFFER
1098 lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(lp->data_buf_dma[i]);
1099#else
1100 if (i >= lp->fbl_count) {
1101 lp->fbl_ptr->bd[i].BuffData = 0;
1102 lp->fbl_ptr->bd[i].BDCtl = 0;
1103 continue;
1104 }
1105 lp->fbl_ptr->bd[i].BuffData =
1106 cpu_to_le32(lp->rx_skbs[i].skb_dma);
1107#endif
1da177e4
LT
1108 /* BDID is index of FrFD.bd[] */
1109 lp->fbl_ptr->bd[i].BDCtl =
eea221ce
AN
1110 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
1111 RX_BUF_SIZE);
1da177e4 1112 }
eea221ce 1113#ifdef TC35815_USE_PACKEDBUFFER
1da177e4 1114 lp->fbl_curid = 0;
eea221ce 1115#endif
1da177e4 1116
eea221ce
AN
1117 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
1118 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
1da177e4
LT
1119 return 0;
1120}
1121
1122static void
1123tc35815_clear_queues(struct net_device *dev)
1124{
ee79b7fb 1125 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT
1126 int i;
1127
1128 for (i = 0; i < TX_FD_NUM; i++) {
eea221ce
AN
1129 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1130 struct sk_buff *skb =
1131 fdsystem != 0xffffffff ?
1132 lp->tx_skbs[fdsystem].skb : NULL;
1133#ifdef DEBUG
1134 if (lp->tx_skbs[i].skb != skb) {
1135 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1136 panic_queues(dev);
1137 }
1138#else
1139 BUG_ON(lp->tx_skbs[i].skb != skb);
1140#endif
1141 if (skb) {
1142 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1143 lp->tx_skbs[i].skb = NULL;
1144 lp->tx_skbs[i].skb_dma = 0;
1da177e4 1145 dev_kfree_skb_any(skb);
eea221ce
AN
1146 }
1147 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1da177e4
LT
1148 }
1149
1150 tc35815_init_queues(dev);
1151}
1152
1153static void
1154tc35815_free_queues(struct net_device *dev)
1155{
ee79b7fb 1156 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT
1157 int i;
1158
1159 if (lp->tfd_base) {
1160 for (i = 0; i < TX_FD_NUM; i++) {
eea221ce
AN
1161 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1162 struct sk_buff *skb =
1163 fdsystem != 0xffffffff ?
1164 lp->tx_skbs[fdsystem].skb : NULL;
1165#ifdef DEBUG
1166 if (lp->tx_skbs[i].skb != skb) {
1167 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1168 panic_queues(dev);
1169 }
1170#else
1171 BUG_ON(lp->tx_skbs[i].skb != skb);
1172#endif
1173 if (skb) {
1174 dev_kfree_skb(skb);
1175 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1176 lp->tx_skbs[i].skb = NULL;
1177 lp->tx_skbs[i].skb_dma = 0;
1178 }
1179 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1da177e4
LT
1180 }
1181 }
1182
1da177e4
LT
1183 lp->rfd_base = NULL;
1184 lp->rfd_limit = NULL;
1185 lp->rfd_cur = NULL;
1186 lp->fbl_ptr = NULL;
1187
eea221ce
AN
1188 for (i = 0; i < RX_BUF_NUM; i++) {
1189#ifdef TC35815_USE_PACKEDBUFFER
1190 if (lp->data_buf[i]) {
1191 free_rxbuf_page(lp->pci_dev,
1192 lp->data_buf[i], lp->data_buf_dma[i]);
1193 lp->data_buf[i] = NULL;
1194 }
1195#else
1196 if (lp->rx_skbs[i].skb) {
1197 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1198 lp->rx_skbs[i].skb_dma);
1199 lp->rx_skbs[i].skb = NULL;
1200 }
1201#endif
1202 }
1203 if (lp->fd_buf) {
1204 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1205 lp->fd_buf, lp->fd_buf_dma);
1206 lp->fd_buf = NULL;
1da177e4 1207 }
1da177e4
LT
1208}
1209
1210static void
1211dump_txfd(struct TxFD *fd)
1212{
1213 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1214 le32_to_cpu(fd->fd.FDNext),
1215 le32_to_cpu(fd->fd.FDSystem),
1216 le32_to_cpu(fd->fd.FDStat),
1217 le32_to_cpu(fd->fd.FDCtl));
1218 printk("BD: ");
1219 printk(" %08x %08x",
1220 le32_to_cpu(fd->bd.BuffData),
1221 le32_to_cpu(fd->bd.BDCtl));
1222 printk("\n");
1223}
1224
1225static int
1226dump_rxfd(struct RxFD *fd)
1227{
1228 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1229 if (bd_count > 8)
1230 bd_count = 8;
1231 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1232 le32_to_cpu(fd->fd.FDNext),
1233 le32_to_cpu(fd->fd.FDSystem),
1234 le32_to_cpu(fd->fd.FDStat),
1235 le32_to_cpu(fd->fd.FDCtl));
1236 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
7f225b42 1237 return 0;
1da177e4
LT
1238 printk("BD: ");
1239 for (i = 0; i < bd_count; i++)
1240 printk(" %08x %08x",
1241 le32_to_cpu(fd->bd[i].BuffData),
1242 le32_to_cpu(fd->bd[i].BDCtl));
1243 printk("\n");
1244 return bd_count;
1245}
1246
eea221ce 1247#if defined(DEBUG) || defined(TC35815_USE_PACKEDBUFFER)
1da177e4
LT
1248static void
1249dump_frfd(struct FrFD *fd)
1250{
1251 int i;
1252 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1253 le32_to_cpu(fd->fd.FDNext),
1254 le32_to_cpu(fd->fd.FDSystem),
1255 le32_to_cpu(fd->fd.FDStat),
1256 le32_to_cpu(fd->fd.FDCtl));
1257 printk("BD: ");
eea221ce 1258 for (i = 0; i < RX_BUF_NUM; i++)
1da177e4
LT
1259 printk(" %08x %08x",
1260 le32_to_cpu(fd->bd[i].BuffData),
1261 le32_to_cpu(fd->bd[i].BDCtl));
1262 printk("\n");
1263}
eea221ce 1264#endif
1da177e4 1265
eea221ce 1266#ifdef DEBUG
1da177e4
LT
1267static void
1268panic_queues(struct net_device *dev)
1269{
ee79b7fb 1270 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT
1271 int i;
1272
eea221ce 1273 printk("TxFD base %p, start %u, end %u\n",
1da177e4
LT
1274 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1275 printk("RxFD base %p limit %p cur %p\n",
1276 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1277 printk("FrFD %p\n", lp->fbl_ptr);
1278 for (i = 0; i < TX_FD_NUM; i++)
1279 dump_txfd(&lp->tfd_base[i]);
1280 for (i = 0; i < RX_FD_NUM; i++) {
1281 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1282 i += (bd_count + 1) / 2; /* skip BDs */
1283 }
1284 dump_frfd(lp->fbl_ptr);
1285 panic("%s: Illegal queue state.", dev->name);
1286}
1da177e4
LT
1287#endif
1288
958eb80b 1289static void print_eth(const u8 *add)
1da177e4 1290{
958eb80b 1291 printk(KERN_DEBUG "print_eth(%p)\n", add);
e174961c
JB
1292 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1293 add + 6, add, add[12], add[13]);
1da177e4
LT
1294}
1295
eea221ce
AN
1296static int tc35815_tx_full(struct net_device *dev)
1297{
ee79b7fb 1298 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
1299 return ((lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end);
1300}
1301
1302static void tc35815_restart(struct net_device *dev)
1303{
ee79b7fb 1304 struct tc35815_local *lp = netdev_priv(dev);
eea221ce 1305
c6686fe3 1306 if (lp->phy_dev) {
eea221ce 1307 int timeout;
c6686fe3
AN
1308
1309 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
eea221ce
AN
1310 timeout = 100;
1311 while (--timeout) {
c6686fe3 1312 if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
eea221ce
AN
1313 break;
1314 udelay(1);
1315 }
1316 if (!timeout)
1317 printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1318 }
1319
c6686fe3 1320 spin_lock_irq(&lp->lock);
eea221ce
AN
1321 tc35815_chip_reset(dev);
1322 tc35815_clear_queues(dev);
1323 tc35815_chip_init(dev);
1324 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1325 tc35815_set_multicast_list(dev);
c6686fe3
AN
1326 spin_unlock_irq(&lp->lock);
1327
1328 netif_wake_queue(dev);
eea221ce
AN
1329}
1330
c6686fe3
AN
1331static void tc35815_restart_work(struct work_struct *work)
1332{
1333 struct tc35815_local *lp =
1334 container_of(work, struct tc35815_local, restart_work);
1335 struct net_device *dev = lp->dev;
1336
1337 tc35815_restart(dev);
1338}
1339
1340static void tc35815_schedule_restart(struct net_device *dev)
eea221ce 1341{
ee79b7fb 1342 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
1343 struct tc35815_regs __iomem *tr =
1344 (struct tc35815_regs __iomem *)dev->base_addr;
1345
c6686fe3
AN
1346 /* disable interrupts */
1347 tc_writel(0, &tr->Int_En);
1348 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1349 schedule_work(&lp->restart_work);
1350}
1351
1352static void tc35815_tx_timeout(struct net_device *dev)
1353{
1354 struct tc35815_regs __iomem *tr =
1355 (struct tc35815_regs __iomem *)dev->base_addr;
1356
eea221ce
AN
1357 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1358 dev->name, tc_readl(&tr->Tx_Stat));
1359
1360 /* Try to restart the adaptor. */
c6686fe3 1361 tc35815_schedule_restart(dev);
c201abd9 1362 dev->stats.tx_errors++;
eea221ce
AN
1363}
1364
1da177e4 1365/*
c6686fe3 1366 * Open/initialize the controller. This is called (in the current kernel)
1da177e4
LT
1367 * sometime after booting when the 'ifconfig' program is run.
1368 *
1369 * This routine should set everything up anew at each open, even
1370 * registers that "should" only need to be set once at boot, so that
1371 * there is non-reboot way to recover if something goes wrong.
1372 */
1373static int
1374tc35815_open(struct net_device *dev)
1375{
ee79b7fb 1376 struct tc35815_local *lp = netdev_priv(dev);
eea221ce 1377
1da177e4
LT
1378 /*
1379 * This is used if the interrupt line can turned off (shared).
1380 * See 3c503.c for an example of selecting the IRQ at config-time.
1381 */
7f225b42
AN
1382 if (request_irq(dev->irq, &tc35815_interrupt, IRQF_SHARED,
1383 dev->name, dev))
1da177e4 1384 return -EAGAIN;
1da177e4
LT
1385
1386 tc35815_chip_reset(dev);
1387
1388 if (tc35815_init_queues(dev) != 0) {
1389 free_irq(dev->irq, dev);
1390 return -EAGAIN;
1391 }
1392
bea3348e 1393 napi_enable(&lp->napi);
bea3348e 1394
1da177e4 1395 /* Reset the hardware here. Don't forget to set the station address. */
eea221ce 1396 spin_lock_irq(&lp->lock);
1da177e4 1397 tc35815_chip_init(dev);
eea221ce 1398 spin_unlock_irq(&lp->lock);
1da177e4 1399
59524a37 1400 netif_carrier_off(dev);
c6686fe3
AN
1401 /* schedule a link state check */
1402 phy_start(lp->phy_dev);
1403
eea221ce
AN
1404 /* We are now ready to accept transmit requeusts from
1405 * the queueing layer of the networking.
1406 */
1da177e4
LT
1407 netif_start_queue(dev);
1408
1409 return 0;
1410}
1411
eea221ce
AN
1412/* This will only be invoked if your driver is _not_ in XOFF state.
1413 * What this means is that you need not check it, and that this
1414 * invariant will hold if you make sure that the netif_*_queue()
1415 * calls are done at the proper times.
1416 */
1417static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1da177e4 1418{
ee79b7fb 1419 struct tc35815_local *lp = netdev_priv(dev);
eea221ce 1420 struct TxFD *txfd;
1da177e4
LT
1421 unsigned long flags;
1422
eea221ce
AN
1423 /* If some error occurs while trying to transmit this
1424 * packet, you should return '1' from this function.
1425 * In such a case you _may not_ do anything to the
1426 * SKB, it is still owned by the network queueing
1427 * layer when an error is returned. This means you
1428 * may not modify any SKB fields, you may not free
1429 * the SKB, etc.
1430 */
1431
1432 /* This is the most common case for modern hardware.
1433 * The spinlock protects this code from the TX complete
1434 * hardware interrupt handler. Queue flow control is
1435 * thus managed under this lock as well.
1436 */
1da177e4 1437 spin_lock_irqsave(&lp->lock, flags);
1da177e4 1438
eea221ce
AN
1439 /* failsafe... (handle txdone now if half of FDs are used) */
1440 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1441 TX_FD_NUM / 2)
1442 tc35815_txdone(dev);
1443
1444 if (netif_msg_pktdata(lp))
1445 print_eth(skb->data);
1446#ifdef DEBUG
1447 if (lp->tx_skbs[lp->tfd_start].skb) {
1448 printk("%s: tx_skbs conflict.\n", dev->name);
1449 panic_queues(dev);
1da177e4 1450 }
eea221ce
AN
1451#else
1452 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1da177e4 1453#endif
eea221ce
AN
1454 lp->tx_skbs[lp->tfd_start].skb = skb;
1455 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1456
1457 /*add to ring */
1458 txfd = &lp->tfd_base[lp->tfd_start];
1459 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1460 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1461 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1462 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1463
1464 if (lp->tfd_start == lp->tfd_end) {
1465 struct tc35815_regs __iomem *tr =
1466 (struct tc35815_regs __iomem *)dev->base_addr;
1467 /* Start DMA Transmitter. */
1468 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1da177e4 1469#ifdef GATHER_TXINT
eea221ce 1470 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1da177e4 1471#endif
eea221ce
AN
1472 if (netif_msg_tx_queued(lp)) {
1473 printk("%s: starting TxFD.\n", dev->name);
1474 dump_txfd(txfd);
1475 }
1476 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1477 } else {
1478 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1479 if (netif_msg_tx_queued(lp)) {
1480 printk("%s: queueing TxFD.\n", dev->name);
1481 dump_txfd(txfd);
1da177e4 1482 }
eea221ce
AN
1483 }
1484 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1da177e4 1485
eea221ce 1486 dev->trans_start = jiffies;
1da177e4 1487
eea221ce
AN
1488 /* If we just used up the very last entry in the
1489 * TX ring on this device, tell the queueing
1490 * layer to send no more.
1491 */
1492 if (tc35815_tx_full(dev)) {
1493 if (netif_msg_tx_queued(lp))
1494 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1495 netif_stop_queue(dev);
1da177e4
LT
1496 }
1497
eea221ce
AN
1498 /* When the TX completion hw interrupt arrives, this
1499 * is when the transmit statistics are updated.
1500 */
1501
1502 spin_unlock_irqrestore(&lp->lock, flags);
6ed10654 1503 return NETDEV_TX_OK;
1da177e4
LT
1504}
1505
1506#define FATAL_ERROR_INT \
1507 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
eea221ce 1508static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1da177e4
LT
1509{
1510 static int count;
1511 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1512 dev->name, status);
1da177e4
LT
1513 if (status & Int_IntPCI)
1514 printk(" IntPCI");
1515 if (status & Int_DmParErr)
1516 printk(" DmParErr");
1517 if (status & Int_IntNRAbt)
1518 printk(" IntNRAbt");
1519 printk("\n");
1520 if (count++ > 100)
1521 panic("%s: Too many fatal errors.", dev->name);
eea221ce 1522 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1da177e4 1523 /* Try to restart the adaptor. */
c6686fe3 1524 tc35815_schedule_restart(dev);
eea221ce
AN
1525}
1526
eea221ce 1527static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
eea221ce 1528{
ee79b7fb 1529 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
1530 int ret = -1;
1531
1532 /* Fatal errors... */
1533 if (status & FATAL_ERROR_INT) {
1534 tc35815_fatal_error_interrupt(dev, status);
1535 return 0;
1536 }
1537 /* recoverable errors */
1538 if (status & Int_IntFDAEx) {
db30f5ef
AN
1539 if (netif_msg_rx_err(lp))
1540 dev_warn(&dev->dev,
1541 "Free Descriptor Area Exhausted (%#x).\n",
1542 status);
c201abd9 1543 dev->stats.rx_dropped++;
eea221ce
AN
1544 ret = 0;
1545 }
1546 if (status & Int_IntBLEx) {
db30f5ef
AN
1547 if (netif_msg_rx_err(lp))
1548 dev_warn(&dev->dev,
1549 "Buffer List Exhausted (%#x).\n",
1550 status);
c201abd9 1551 dev->stats.rx_dropped++;
eea221ce
AN
1552 ret = 0;
1553 }
1554 if (status & Int_IntExBD) {
db30f5ef
AN
1555 if (netif_msg_rx_err(lp))
1556 dev_warn(&dev->dev,
1557 "Excessive Buffer Descriptiors (%#x).\n",
1558 status);
c201abd9 1559 dev->stats.rx_length_errors++;
eea221ce
AN
1560 ret = 0;
1561 }
1562
1563 /* normal notification */
1564 if (status & Int_IntMacRx) {
1565 /* Got a packet(s). */
eea221ce 1566 ret = tc35815_rx(dev, limit);
eea221ce
AN
1567 lp->lstats.rx_ints++;
1568 }
1569 if (status & Int_IntMacTx) {
1570 /* Transmit complete. */
1571 lp->lstats.tx_ints++;
1572 tc35815_txdone(dev);
1573 netif_wake_queue(dev);
02c5c8ec
AN
1574 if (ret < 0)
1575 ret = 0;
eea221ce
AN
1576 }
1577 return ret;
1da177e4
LT
1578}
1579
1580/*
1581 * The typical workload of the driver:
eea221ce 1582 * Handle the network interface interrupts.
1da177e4 1583 */
7d12e780 1584static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1da177e4
LT
1585{
1586 struct net_device *dev = dev_id;
bea3348e 1587 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
1588 struct tc35815_regs __iomem *tr =
1589 (struct tc35815_regs __iomem *)dev->base_addr;
eea221ce
AN
1590 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1591
1592 if (!(dmactl & DMA_IntMask)) {
1593 /* disable interrupts */
1594 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
288379f0
BH
1595 if (napi_schedule_prep(&lp->napi))
1596 __napi_schedule(&lp->napi);
eea221ce
AN
1597 else {
1598 printk(KERN_ERR "%s: interrupt taken in poll\n",
1599 dev->name);
1600 BUG();
1da177e4 1601 }
eea221ce
AN
1602 (void)tc_readl(&tr->Int_Src); /* flush */
1603 return IRQ_HANDLED;
1604 }
1605 return IRQ_NONE;
eea221ce 1606}
1da177e4 1607
eea221ce
AN
1608#ifdef CONFIG_NET_POLL_CONTROLLER
1609static void tc35815_poll_controller(struct net_device *dev)
1610{
1611 disable_irq(dev->irq);
1612 tc35815_interrupt(dev->irq, dev);
1613 enable_irq(dev->irq);
1da177e4 1614}
eea221ce 1615#endif
1da177e4
LT
1616
1617/* We have a good packet(s), get it/them out of the buffers. */
eea221ce
AN
1618static int
1619tc35815_rx(struct net_device *dev, int limit)
1da177e4 1620{
ee79b7fb 1621 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT
1622 unsigned int fdctl;
1623 int i;
eea221ce 1624 int received = 0;
1da177e4
LT
1625
1626 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1627 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1628 int pkt_len = fdctl & FD_FDLength_MASK;
1da177e4 1629 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
eea221ce
AN
1630#ifdef DEBUG
1631 struct RxFD *next_rfd;
1632#endif
1633#if (RX_CTL_CMD & Rx_StripCRC) == 0
82a9928d 1634 pkt_len -= ETH_FCS_LEN;
eea221ce 1635#endif
1da177e4 1636
eea221ce 1637 if (netif_msg_rx_status(lp))
1da177e4
LT
1638 dump_rxfd(lp->rfd_cur);
1639 if (status & Rx_Good) {
1da177e4
LT
1640 struct sk_buff *skb;
1641 unsigned char *data;
eea221ce
AN
1642 int cur_bd;
1643#ifdef TC35815_USE_PACKEDBUFFER
1644 int offset;
1645#endif
6aa20a22 1646
eea221ce
AN
1647 if (--limit < 0)
1648 break;
eea221ce
AN
1649#ifdef TC35815_USE_PACKEDBUFFER
1650 BUG_ON(bd_count > 2);
82a9928d 1651 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
1da177e4
LT
1652 if (skb == NULL) {
1653 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
1654 dev->name);
c201abd9 1655 dev->stats.rx_dropped++;
1da177e4
LT
1656 break;
1657 }
82a9928d 1658 skb_reserve(skb, NET_IP_ALIGN);
1da177e4
LT
1659
1660 data = skb_put(skb, pkt_len);
1661
1662 /* copy from receive buffer */
1663 cur_bd = 0;
1664 offset = 0;
1665 while (offset < pkt_len && cur_bd < bd_count) {
1666 int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
1667 BD_BuffLength_MASK;
eea221ce
AN
1668 dma_addr_t dma = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData);
1669 void *rxbuf = rxbuf_bus_to_virt(lp, dma);
1670 if (offset + len > pkt_len)
1671 len = pkt_len - offset;
1672#ifdef TC35815_DMA_SYNC_ONDEMAND
1673 pci_dma_sync_single_for_cpu(lp->pci_dev,
1674 dma, len,
1675 PCI_DMA_FROMDEVICE);
1da177e4
LT
1676#endif
1677 memcpy(data + offset, rxbuf, len);
793bc0af
AN
1678#ifdef TC35815_DMA_SYNC_ONDEMAND
1679 pci_dma_sync_single_for_device(lp->pci_dev,
1680 dma, len,
1681 PCI_DMA_FROMDEVICE);
1682#endif
1da177e4
LT
1683 offset += len;
1684 cur_bd++;
1685 }
eea221ce
AN
1686#else /* TC35815_USE_PACKEDBUFFER */
1687 BUG_ON(bd_count > 1);
1688 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1689 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1690#ifdef DEBUG
1691 if (cur_bd >= RX_BUF_NUM) {
1692 printk("%s: invalid BDID.\n", dev->name);
1693 panic_queues(dev);
1694 }
1695 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1696 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1697 if (!lp->rx_skbs[cur_bd].skb) {
1698 printk("%s: NULL skb.\n", dev->name);
1699 panic_queues(dev);
1700 }
1701#else
1702 BUG_ON(cur_bd >= RX_BUF_NUM);
1da177e4 1703#endif
eea221ce
AN
1704 skb = lp->rx_skbs[cur_bd].skb;
1705 prefetch(skb->data);
1706 lp->rx_skbs[cur_bd].skb = NULL;
eea221ce
AN
1707 pci_unmap_single(lp->pci_dev,
1708 lp->rx_skbs[cur_bd].skb_dma,
1709 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
82a9928d
AN
1710 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1711 memmove(skb->data, skb->data - NET_IP_ALIGN,
1712 pkt_len);
eea221ce
AN
1713 data = skb_put(skb, pkt_len);
1714#endif /* TC35815_USE_PACKEDBUFFER */
1715 if (netif_msg_pktdata(lp))
1da177e4
LT
1716 print_eth(data);
1717 skb->protocol = eth_type_trans(skb, dev);
eea221ce
AN
1718 netif_receive_skb(skb);
1719 received++;
c201abd9
AN
1720 dev->stats.rx_packets++;
1721 dev->stats.rx_bytes += pkt_len;
1da177e4 1722 } else {
c201abd9 1723 dev->stats.rx_errors++;
db30f5ef
AN
1724 if (netif_msg_rx_err(lp))
1725 dev_info(&dev->dev, "Rx error (status %x)\n",
1726 status & Rx_Stat_Mask);
1da177e4
LT
1727 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1728 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1729 status &= ~(Rx_LongErr|Rx_CRCErr);
1730 status |= Rx_Over;
1731 }
c201abd9
AN
1732 if (status & Rx_LongErr)
1733 dev->stats.rx_length_errors++;
1734 if (status & Rx_Over)
1735 dev->stats.rx_fifo_errors++;
1736 if (status & Rx_CRCErr)
1737 dev->stats.rx_crc_errors++;
1738 if (status & Rx_Align)
1739 dev->stats.rx_frame_errors++;
1da177e4
LT
1740 }
1741
1742 if (bd_count > 0) {
1743 /* put Free Buffer back to controller */
1744 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1745 unsigned char id =
1746 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
eea221ce
AN
1747#ifdef DEBUG
1748 if (id >= RX_BUF_NUM) {
1da177e4
LT
1749 printk("%s: invalid BDID.\n", dev->name);
1750 panic_queues(dev);
1751 }
eea221ce
AN
1752#else
1753 BUG_ON(id >= RX_BUF_NUM);
1754#endif
1da177e4 1755 /* free old buffers */
eea221ce
AN
1756#ifdef TC35815_USE_PACKEDBUFFER
1757 while (lp->fbl_curid != id)
1758#else
ccc57aac 1759 lp->fbl_count--;
eea221ce
AN
1760 while (lp->fbl_count < RX_BUF_NUM)
1761#endif
1762 {
1763#ifdef TC35815_USE_PACKEDBUFFER
1764 unsigned char curid = lp->fbl_curid;
1765#else
1766 unsigned char curid =
1767 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1768#endif
1769 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1770#ifdef DEBUG
1771 bdctl = le32_to_cpu(bd->BDCtl);
1da177e4
LT
1772 if (bdctl & BD_CownsBD) {
1773 printk("%s: Freeing invalid BD.\n",
1774 dev->name);
1775 panic_queues(dev);
1776 }
eea221ce 1777#endif
3a4fa0a2 1778 /* pass BD to controller */
eea221ce
AN
1779#ifndef TC35815_USE_PACKEDBUFFER
1780 if (!lp->rx_skbs[curid].skb) {
1781 lp->rx_skbs[curid].skb =
1782 alloc_rxbuf_skb(dev,
1783 lp->pci_dev,
1784 &lp->rx_skbs[curid].skb_dma);
1785 if (!lp->rx_skbs[curid].skb)
1786 break; /* try on next reception */
1787 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1788 }
1789#endif /* TC35815_USE_PACKEDBUFFER */
1da177e4 1790 /* Note: BDLength was modified by chip. */
eea221ce
AN
1791 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1792 (curid << BD_RxBDID_SHIFT) |
1793 RX_BUF_SIZE);
1794#ifdef TC35815_USE_PACKEDBUFFER
1795 lp->fbl_curid = (curid + 1) % RX_BUF_NUM;
1796 if (netif_msg_rx_status(lp)) {
1da177e4
LT
1797 printk("%s: Entering new FBD %d\n",
1798 dev->name, lp->fbl_curid);
1799 dump_frfd(lp->fbl_ptr);
1800 }
eea221ce
AN
1801#else
1802 lp->fbl_count++;
1803#endif
1da177e4
LT
1804 }
1805 }
1806
1807 /* put RxFD back to controller */
eea221ce
AN
1808#ifdef DEBUG
1809 next_rfd = fd_bus_to_virt(lp,
1810 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1da177e4
LT
1811 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1812 printk("%s: RxFD FDNext invalid.\n", dev->name);
1813 panic_queues(dev);
1814 }
eea221ce 1815#endif
1da177e4 1816 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
3a4fa0a2 1817 /* pass FD to controller */
eea221ce
AN
1818#ifdef DEBUG
1819 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1820#else
1821 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1822#endif
1da177e4
LT
1823 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1824 lp->rfd_cur++;
1da177e4 1825 }
eea221ce
AN
1826 if (lp->rfd_cur > lp->rfd_limit)
1827 lp->rfd_cur = lp->rfd_base;
1828#ifdef DEBUG
1829 if (lp->rfd_cur != next_rfd)
1830 printk("rfd_cur = %p, next_rfd %p\n",
1831 lp->rfd_cur, next_rfd);
1832#endif
1da177e4
LT
1833 }
1834
eea221ce 1835 return received;
1da177e4
LT
1836}
1837
bea3348e 1838static int tc35815_poll(struct napi_struct *napi, int budget)
eea221ce 1839{
bea3348e
SH
1840 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1841 struct net_device *dev = lp->dev;
eea221ce
AN
1842 struct tc35815_regs __iomem *tr =
1843 (struct tc35815_regs __iomem *)dev->base_addr;
eea221ce
AN
1844 int received = 0, handled;
1845 u32 status;
1846
1847 spin_lock(&lp->lock);
1848 status = tc_readl(&tr->Int_Src);
1849 do {
db30f5ef
AN
1850 /* BLEx, FDAEx will be cleared later */
1851 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1852 &tr->Int_Src); /* write to clear */
eea221ce 1853
a2c465db 1854 handled = tc35815_do_interrupt(dev, status, budget - received);
db30f5ef
AN
1855 if (status & (Int_BLEx | Int_FDAEx))
1856 tc_writel(status & (Int_BLEx | Int_FDAEx),
1857 &tr->Int_Src);
eea221ce
AN
1858 if (handled >= 0) {
1859 received += handled;
bea3348e 1860 if (received >= budget)
eea221ce
AN
1861 break;
1862 }
1863 status = tc_readl(&tr->Int_Src);
1864 } while (status);
1865 spin_unlock(&lp->lock);
1866
bea3348e 1867 if (received < budget) {
288379f0 1868 napi_complete(napi);
bea3348e
SH
1869 /* enable interrupts */
1870 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1871 }
1872 return received;
eea221ce 1873}
eea221ce 1874
1da177e4
LT
1875#ifdef NO_CHECK_CARRIER
1876#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1877#else
1878#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1879#endif
1880
1881static void
1882tc35815_check_tx_stat(struct net_device *dev, int status)
1883{
ee79b7fb 1884 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT
1885 const char *msg = NULL;
1886
1887 /* count collisions */
1888 if (status & Tx_ExColl)
c201abd9 1889 dev->stats.collisions += 16;
1da177e4 1890 if (status & Tx_TxColl_MASK)
c201abd9 1891 dev->stats.collisions += status & Tx_TxColl_MASK;
1da177e4 1892
eea221ce
AN
1893#ifndef NO_CHECK_CARRIER
1894 /* TX4939 does not have NCarr */
c6686fe3 1895 if (lp->chiptype == TC35815_TX4939)
eea221ce
AN
1896 status &= ~Tx_NCarr;
1897#ifdef WORKAROUND_LOSTCAR
1da177e4 1898 /* WORKAROUND: ignore LostCrS in full duplex operation */
c6686fe3 1899 if (!lp->link || lp->duplex == DUPLEX_FULL)
1da177e4 1900 status &= ~Tx_NCarr;
eea221ce
AN
1901#endif
1902#endif
1da177e4
LT
1903
1904 if (!(status & TX_STA_ERR)) {
1905 /* no error. */
c201abd9 1906 dev->stats.tx_packets++;
1da177e4
LT
1907 return;
1908 }
1909
c201abd9 1910 dev->stats.tx_errors++;
1da177e4 1911 if (status & Tx_ExColl) {
c201abd9 1912 dev->stats.tx_aborted_errors++;
1da177e4
LT
1913 msg = "Excessive Collision.";
1914 }
1915 if (status & Tx_Under) {
c201abd9 1916 dev->stats.tx_fifo_errors++;
1da177e4 1917 msg = "Tx FIFO Underrun.";
eea221ce
AN
1918 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1919 lp->lstats.tx_underrun++;
1920 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1921 struct tc35815_regs __iomem *tr =
1922 (struct tc35815_regs __iomem *)dev->base_addr;
1923 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1924 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1925 }
1926 }
1da177e4
LT
1927 }
1928 if (status & Tx_Defer) {
c201abd9 1929 dev->stats.tx_fifo_errors++;
1da177e4
LT
1930 msg = "Excessive Deferral.";
1931 }
1932#ifndef NO_CHECK_CARRIER
1933 if (status & Tx_NCarr) {
c201abd9 1934 dev->stats.tx_carrier_errors++;
1da177e4
LT
1935 msg = "Lost Carrier Sense.";
1936 }
1937#endif
1938 if (status & Tx_LateColl) {
c201abd9 1939 dev->stats.tx_aborted_errors++;
1da177e4
LT
1940 msg = "Late Collision.";
1941 }
1942 if (status & Tx_TxPar) {
c201abd9 1943 dev->stats.tx_fifo_errors++;
1da177e4
LT
1944 msg = "Transmit Parity Error.";
1945 }
1946 if (status & Tx_SQErr) {
c201abd9 1947 dev->stats.tx_heartbeat_errors++;
1da177e4
LT
1948 msg = "Signal Quality Error.";
1949 }
eea221ce 1950 if (msg && netif_msg_tx_err(lp))
1da177e4
LT
1951 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1952}
1953
eea221ce
AN
1954/* This handles TX complete events posted by the device
1955 * via interrupts.
1956 */
1da177e4
LT
1957static void
1958tc35815_txdone(struct net_device *dev)
1959{
ee79b7fb 1960 struct tc35815_local *lp = netdev_priv(dev);
1da177e4
LT
1961 struct TxFD *txfd;
1962 unsigned int fdctl;
1da177e4
LT
1963
1964 txfd = &lp->tfd_base[lp->tfd_end];
1965 while (lp->tfd_start != lp->tfd_end &&
1966 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1967 int status = le32_to_cpu(txfd->fd.FDStat);
1968 struct sk_buff *skb;
1969 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
eea221ce 1970 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1da177e4 1971
eea221ce 1972 if (netif_msg_tx_done(lp)) {
1da177e4
LT
1973 printk("%s: complete TxFD.\n", dev->name);
1974 dump_txfd(txfd);
1975 }
1976 tc35815_check_tx_stat(dev, status);
1977
eea221ce
AN
1978 skb = fdsystem != 0xffffffff ?
1979 lp->tx_skbs[fdsystem].skb : NULL;
1980#ifdef DEBUG
1981 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1982 printk("%s: tx_skbs mismatch.\n", dev->name);
1983 panic_queues(dev);
1984 }
1985#else
1986 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1987#endif
1da177e4 1988 if (skb) {
c201abd9 1989 dev->stats.tx_bytes += skb->len;
eea221ce
AN
1990 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1991 lp->tx_skbs[lp->tfd_end].skb = NULL;
1992 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1da177e4
LT
1993 dev_kfree_skb_any(skb);
1994 }
eea221ce 1995 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1da177e4 1996
1da177e4
LT
1997 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1998 txfd = &lp->tfd_base[lp->tfd_end];
eea221ce
AN
1999#ifdef DEBUG
2000 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1da177e4
LT
2001 printk("%s: TxFD FDNext invalid.\n", dev->name);
2002 panic_queues(dev);
2003 }
eea221ce 2004#endif
1da177e4
LT
2005 if (fdnext & FD_Next_EOL) {
2006 /* DMA Transmitter has been stopping... */
2007 if (lp->tfd_end != lp->tfd_start) {
eea221ce
AN
2008 struct tc35815_regs __iomem *tr =
2009 (struct tc35815_regs __iomem *)dev->base_addr;
1da177e4 2010 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
7f225b42 2011 struct TxFD *txhead = &lp->tfd_base[head];
1da177e4
LT
2012 int qlen = (lp->tfd_start + TX_FD_NUM
2013 - lp->tfd_end) % TX_FD_NUM;
2014
eea221ce 2015#ifdef DEBUG
1da177e4
LT
2016 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
2017 printk("%s: TxFD FDCtl invalid.\n", dev->name);
2018 panic_queues(dev);
2019 }
eea221ce 2020#endif
1da177e4
LT
2021 /* log max queue length */
2022 if (lp->lstats.max_tx_qlen < qlen)
2023 lp->lstats.max_tx_qlen = qlen;
2024
2025
2026 /* start DMA Transmitter again */
2027 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
2028#ifdef GATHER_TXINT
2029 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
2030#endif
eea221ce 2031 if (netif_msg_tx_queued(lp)) {
1da177e4
LT
2032 printk("%s: start TxFD on queue.\n",
2033 dev->name);
2034 dump_txfd(txfd);
2035 }
eea221ce 2036 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1da177e4
LT
2037 }
2038 break;
2039 }
2040 }
2041
eea221ce
AN
2042 /* If we had stopped the queue due to a "tx full"
2043 * condition, and space has now been made available,
2044 * wake up the queue.
2045 */
7f225b42 2046 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
eea221ce 2047 netif_wake_queue(dev);
1da177e4
LT
2048}
2049
2050/* The inverse routine to tc35815_open(). */
2051static int
2052tc35815_close(struct net_device *dev)
2053{
ee79b7fb 2054 struct tc35815_local *lp = netdev_priv(dev);
bea3348e 2055
1da177e4 2056 netif_stop_queue(dev);
bea3348e 2057 napi_disable(&lp->napi);
c6686fe3
AN
2058 if (lp->phy_dev)
2059 phy_stop(lp->phy_dev);
2060 cancel_work_sync(&lp->restart_work);
1da177e4
LT
2061
2062 /* Flush the Tx and disable Rx here. */
1da177e4
LT
2063 tc35815_chip_reset(dev);
2064 free_irq(dev->irq, dev);
2065
2066 tc35815_free_queues(dev);
2067
2068 return 0;
eea221ce 2069
1da177e4
LT
2070}
2071
2072/*
2073 * Get the current statistics.
2074 * This may be called with the card open or closed.
2075 */
2076static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
2077{
eea221ce
AN
2078 struct tc35815_regs __iomem *tr =
2079 (struct tc35815_regs __iomem *)dev->base_addr;
c201abd9 2080 if (netif_running(dev))
1da177e4 2081 /* Update the statistics from the device registers. */
7bb82e83 2082 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1da177e4 2083
c201abd9 2084 return &dev->stats;
1da177e4
LT
2085}
2086
eea221ce 2087static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1da177e4 2088{
ee79b7fb 2089 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
2090 struct tc35815_regs __iomem *tr =
2091 (struct tc35815_regs __iomem *)dev->base_addr;
1da177e4 2092 int cam_index = index * 6;
eea221ce
AN
2093 u32 cam_data;
2094 u32 saved_addr;
958eb80b 2095
1da177e4
LT
2096 saved_addr = tc_readl(&tr->CAM_Adr);
2097
958eb80b 2098 if (netif_msg_hw(lp))
e174961c
JB
2099 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
2100 dev->name, index, addr);
1da177e4
LT
2101 if (index & 1) {
2102 /* read modify write */
2103 tc_writel(cam_index - 2, &tr->CAM_Adr);
2104 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
2105 cam_data |= addr[0] << 8 | addr[1];
2106 tc_writel(cam_data, &tr->CAM_Data);
2107 /* write whole word */
2108 tc_writel(cam_index + 2, &tr->CAM_Adr);
2109 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
2110 tc_writel(cam_data, &tr->CAM_Data);
2111 } else {
2112 /* write whole word */
2113 tc_writel(cam_index, &tr->CAM_Adr);
2114 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
2115 tc_writel(cam_data, &tr->CAM_Data);
2116 /* read modify write */
2117 tc_writel(cam_index + 4, &tr->CAM_Adr);
2118 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
2119 cam_data |= addr[4] << 24 | (addr[5] << 16);
2120 tc_writel(cam_data, &tr->CAM_Data);
2121 }
2122
1da177e4
LT
2123 tc_writel(saved_addr, &tr->CAM_Adr);
2124}
2125
2126
2127/*
2128 * Set or clear the multicast filter for this adaptor.
2129 * num_addrs == -1 Promiscuous mode, receive all packets
2130 * num_addrs == 0 Normal mode, clear multicast list
2131 * num_addrs > 0 Multicast mode, receive normal and MC packets,
2132 * and do best-effort filtering.
2133 */
2134static void
2135tc35815_set_multicast_list(struct net_device *dev)
2136{
eea221ce
AN
2137 struct tc35815_regs __iomem *tr =
2138 (struct tc35815_regs __iomem *)dev->base_addr;
1da177e4 2139
7f225b42 2140 if (dev->flags & IFF_PROMISC) {
eea221ce
AN
2141#ifdef WORKAROUND_100HALF_PROMISC
2142 /* With some (all?) 100MHalf HUB, controller will hang
2143 * if we enabled promiscuous mode before linkup... */
ee79b7fb 2144 struct tc35815_local *lp = netdev_priv(dev);
c6686fe3
AN
2145
2146 if (!lp->link)
eea221ce
AN
2147 return;
2148#endif
1da177e4
LT
2149 /* Enable promiscuous mode */
2150 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
7f225b42
AN
2151 } else if ((dev->flags & IFF_ALLMULTI) ||
2152 dev->mc_count > CAM_ENTRY_MAX - 3) {
1da177e4
LT
2153 /* CAM 0, 1, 20 are reserved. */
2154 /* Disable promiscuous mode, use normal mode. */
2155 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
7f225b42
AN
2156 } else if (dev->mc_count) {
2157 struct dev_mc_list *cur_addr = dev->mc_list;
1da177e4
LT
2158 int i;
2159 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
2160
2161 tc_writel(0, &tr->CAM_Ctl);
2162 /* Walk the address list, and load the filter */
2163 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
2164 if (!cur_addr)
2165 break;
2166 /* entry 0,1 is reserved. */
eea221ce 2167 tc35815_set_cam_entry(dev, i + 2, cur_addr->dmi_addr);
1da177e4
LT
2168 ena_bits |= CAM_Ena_Bit(i + 2);
2169 }
2170 tc_writel(ena_bits, &tr->CAM_Ena);
2171 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
7f225b42 2172 } else {
1da177e4
LT
2173 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2174 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2175 }
2176}
2177
eea221ce 2178static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1da177e4 2179{
ee79b7fb 2180 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
2181 strcpy(info->driver, MODNAME);
2182 strcpy(info->version, DRV_VERSION);
2183 strcpy(info->bus_info, pci_name(lp->pci_dev));
2184}
6aa20a22 2185
eea221ce
AN
2186static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2187{
ee79b7fb 2188 struct tc35815_local *lp = netdev_priv(dev);
eea221ce 2189
c6686fe3
AN
2190 if (!lp->phy_dev)
2191 return -ENODEV;
2192 return phy_ethtool_gset(lp->phy_dev, cmd);
eea221ce
AN
2193}
2194
c6686fe3 2195static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
eea221ce 2196{
ee79b7fb 2197 struct tc35815_local *lp = netdev_priv(dev);
eea221ce 2198
c6686fe3
AN
2199 if (!lp->phy_dev)
2200 return -ENODEV;
2201 return phy_ethtool_sset(lp->phy_dev, cmd);
eea221ce
AN
2202}
2203
2204static u32 tc35815_get_msglevel(struct net_device *dev)
2205{
ee79b7fb 2206 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
2207 return lp->msg_enable;
2208}
2209
2210static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2211{
ee79b7fb 2212 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
2213 lp->msg_enable = datum;
2214}
2215
b9f2c044 2216static int tc35815_get_sset_count(struct net_device *dev, int sset)
eea221ce 2217{
ee79b7fb 2218 struct tc35815_local *lp = netdev_priv(dev);
b9f2c044
JG
2219
2220 switch (sset) {
2221 case ETH_SS_STATS:
2222 return sizeof(lp->lstats) / sizeof(int);
2223 default:
2224 return -EOPNOTSUPP;
2225 }
eea221ce 2226}
1da177e4 2227
eea221ce
AN
2228static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2229{
ee79b7fb 2230 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
2231 data[0] = lp->lstats.max_tx_qlen;
2232 data[1] = lp->lstats.tx_ints;
2233 data[2] = lp->lstats.rx_ints;
2234 data[3] = lp->lstats.tx_underrun;
2235}
2236
2237static struct {
2238 const char str[ETH_GSTRING_LEN];
2239} ethtool_stats_keys[] = {
2240 { "max_tx_qlen" },
2241 { "tx_ints" },
2242 { "rx_ints" },
2243 { "tx_underrun" },
2244};
2245
2246static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2247{
2248 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2249}
2250
2251static const struct ethtool_ops tc35815_ethtool_ops = {
2252 .get_drvinfo = tc35815_get_drvinfo,
2253 .get_settings = tc35815_get_settings,
2254 .set_settings = tc35815_set_settings,
c6686fe3 2255 .get_link = ethtool_op_get_link,
eea221ce
AN
2256 .get_msglevel = tc35815_get_msglevel,
2257 .set_msglevel = tc35815_set_msglevel,
2258 .get_strings = tc35815_get_strings,
b9f2c044 2259 .get_sset_count = tc35815_get_sset_count,
eea221ce 2260 .get_ethtool_stats = tc35815_get_ethtool_stats,
eea221ce
AN
2261};
2262
2263static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2264{
ee79b7fb 2265 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
2266
2267 if (!netif_running(dev))
2268 return -EINVAL;
c6686fe3
AN
2269 if (!lp->phy_dev)
2270 return -ENODEV;
2271 return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd);
eea221ce
AN
2272}
2273
2274static void tc35815_chip_reset(struct net_device *dev)
2275{
2276 struct tc35815_regs __iomem *tr =
2277 (struct tc35815_regs __iomem *)dev->base_addr;
2278 int i;
1da177e4
LT
2279 /* reset the controller */
2280 tc_writel(MAC_Reset, &tr->MAC_Ctl);
eea221ce
AN
2281 udelay(4); /* 3200ns */
2282 i = 0;
2283 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2284 if (i++ > 100) {
2285 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2286 break;
2287 }
2288 mdelay(1);
2289 }
1da177e4
LT
2290 tc_writel(0, &tr->MAC_Ctl);
2291
2292 /* initialize registers to default value */
2293 tc_writel(0, &tr->DMA_Ctl);
2294 tc_writel(0, &tr->TxThrsh);
2295 tc_writel(0, &tr->TxPollCtr);
2296 tc_writel(0, &tr->RxFragSize);
2297 tc_writel(0, &tr->Int_En);
2298 tc_writel(0, &tr->FDA_Bas);
2299 tc_writel(0, &tr->FDA_Lim);
2300 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2301 tc_writel(0, &tr->CAM_Ctl);
2302 tc_writel(0, &tr->Tx_Ctl);
2303 tc_writel(0, &tr->Rx_Ctl);
2304 tc_writel(0, &tr->CAM_Ena);
2305 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2306
eea221ce
AN
2307 /* initialize internal SRAM */
2308 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2309 for (i = 0; i < 0x1000; i += 4) {
2310 tc_writel(i, &tr->CAM_Adr);
2311 tc_writel(0, &tr->CAM_Data);
2312 }
2313 tc_writel(0, &tr->DMA_Ctl);
1da177e4
LT
2314}
2315
2316static void tc35815_chip_init(struct net_device *dev)
2317{
ee79b7fb 2318 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
2319 struct tc35815_regs __iomem *tr =
2320 (struct tc35815_regs __iomem *)dev->base_addr;
1da177e4
LT
2321 unsigned long txctl = TX_CTL_CMD;
2322
1da177e4 2323 /* load station address to CAM */
eea221ce 2324 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
1da177e4
LT
2325
2326 /* Enable CAM (broadcast and unicast) */
2327 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2328 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2329
eea221ce
AN
2330 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2331 if (HAVE_DMA_RXALIGN(lp))
2332 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2333 else
2334 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2335#ifdef TC35815_USE_PACKEDBUFFER
1da177e4 2336 tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
eea221ce 2337#endif
1da177e4
LT
2338 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2339 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2340 tc_writel(INT_EN_CMD, &tr->Int_En);
2341
2342 /* set queues */
eea221ce 2343 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
1da177e4
LT
2344 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2345 &tr->FDA_Lim);
2346 /*
2347 * Activation method:
eea221ce 2348 * First, enable the MAC Transmitter and the DMA Receive circuits.
1da177e4
LT
2349 * Then enable the DMA Transmitter and the MAC Receive circuits.
2350 */
eea221ce 2351 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
1da177e4 2352 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
eea221ce 2353
1da177e4 2354 /* start MAC transmitter */
eea221ce
AN
2355#ifndef NO_CHECK_CARRIER
2356 /* TX4939 does not have EnLCarr */
c6686fe3 2357 if (lp->chiptype == TC35815_TX4939)
eea221ce
AN
2358 txctl &= ~Tx_EnLCarr;
2359#ifdef WORKAROUND_LOSTCAR
1da177e4 2360 /* WORKAROUND: ignore LostCrS in full duplex operation */
c6686fe3 2361 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
eea221ce
AN
2362 txctl &= ~Tx_EnLCarr;
2363#endif
2364#endif /* !NO_CHECK_CARRIER */
1da177e4
LT
2365#ifdef GATHER_TXINT
2366 txctl &= ~Tx_EnComp; /* disable global tx completion int. */
2367#endif
2368 tc_writel(txctl, &tr->Tx_Ctl);
eea221ce
AN
2369}
2370
2371#ifdef CONFIG_PM
2372static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2373{
2374 struct net_device *dev = pci_get_drvdata(pdev);
ee79b7fb 2375 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
2376 unsigned long flags;
2377
2378 pci_save_state(pdev);
2379 if (!netif_running(dev))
2380 return 0;
2381 netif_device_detach(dev);
c6686fe3
AN
2382 if (lp->phy_dev)
2383 phy_stop(lp->phy_dev);
eea221ce 2384 spin_lock_irqsave(&lp->lock, flags);
eea221ce 2385 tc35815_chip_reset(dev);
1da177e4 2386 spin_unlock_irqrestore(&lp->lock, flags);
eea221ce
AN
2387 pci_set_power_state(pdev, PCI_D3hot);
2388 return 0;
1da177e4
LT
2389}
2390
eea221ce
AN
2391static int tc35815_resume(struct pci_dev *pdev)
2392{
2393 struct net_device *dev = pci_get_drvdata(pdev);
ee79b7fb 2394 struct tc35815_local *lp = netdev_priv(dev);
eea221ce
AN
2395
2396 pci_restore_state(pdev);
2397 if (!netif_running(dev))
2398 return 0;
2399 pci_set_power_state(pdev, PCI_D0);
eea221ce 2400 tc35815_restart(dev);
59524a37 2401 netif_carrier_off(dev);
c6686fe3
AN
2402 if (lp->phy_dev)
2403 phy_start(lp->phy_dev);
eea221ce
AN
2404 netif_device_attach(dev);
2405 return 0;
2406}
2407#endif /* CONFIG_PM */
2408
2409static struct pci_driver tc35815_pci_driver = {
2410 .name = MODNAME,
2411 .id_table = tc35815_pci_tbl,
2412 .probe = tc35815_init_one,
2413 .remove = __devexit_p(tc35815_remove_one),
2414#ifdef CONFIG_PM
2415 .suspend = tc35815_suspend,
2416 .resume = tc35815_resume,
2417#endif
1da177e4
LT
2418};
2419
eea221ce
AN
2420module_param_named(speed, options.speed, int, 0);
2421MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2422module_param_named(duplex, options.duplex, int, 0);
2423MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
eea221ce 2424
1da177e4
LT
2425static int __init tc35815_init_module(void)
2426{
eea221ce 2427 return pci_register_driver(&tc35815_pci_driver);
1da177e4
LT
2428}
2429
2430static void __exit tc35815_cleanup_module(void)
2431{
eea221ce 2432 pci_unregister_driver(&tc35815_pci_driver);
1da177e4 2433}
420e8524 2434
1da177e4
LT
2435module_init(tc35815_init_module);
2436module_exit(tc35815_cleanup_module);
eea221ce
AN
2437
2438MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2439MODULE_LICENSE("GPL");