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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
b86fb2cf | 7 | * Copyright (C) 2005-2011 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 LT |
28 | #include <linux/init.h> |
29 | #include <linux/ioport.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/ethtool.h> | |
3110f5f5 | 35 | #include <linux/mdio.h> |
1da177e4 | 36 | #include <linux/mii.h> |
158d7abd | 37 | #include <linux/phy.h> |
a9daf367 | 38 | #include <linux/brcmphy.h> |
1da177e4 LT |
39 | #include <linux/if_vlan.h> |
40 | #include <linux/ip.h> | |
41 | #include <linux/tcp.h> | |
42 | #include <linux/workqueue.h> | |
61487480 | 43 | #include <linux/prefetch.h> |
f9a5f7d3 | 44 | #include <linux/dma-mapping.h> |
077f849d | 45 | #include <linux/firmware.h> |
1da177e4 LT |
46 | |
47 | #include <net/checksum.h> | |
c9bdd4b5 | 48 | #include <net/ip.h> |
1da177e4 LT |
49 | |
50 | #include <asm/system.h> | |
27fd9de8 | 51 | #include <linux/io.h> |
1da177e4 | 52 | #include <asm/byteorder.h> |
27fd9de8 | 53 | #include <linux/uaccess.h> |
1da177e4 | 54 | |
49b6e95f | 55 | #ifdef CONFIG_SPARC |
1da177e4 | 56 | #include <asm/idprom.h> |
49b6e95f | 57 | #include <asm/prom.h> |
1da177e4 LT |
58 | #endif |
59 | ||
63532394 MC |
60 | #define BAR_0 0 |
61 | #define BAR_2 2 | |
62 | ||
1da177e4 LT |
63 | #include "tg3.h" |
64 | ||
65 | #define DRV_MODULE_NAME "tg3" | |
6867c843 | 66 | #define TG3_MAJ_NUM 3 |
b86fb2cf | 67 | #define TG3_MIN_NUM 117 |
6867c843 MC |
68 | #define DRV_MODULE_VERSION \ |
69 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
b86fb2cf | 70 | #define DRV_MODULE_RELDATE "January 25, 2011" |
1da177e4 LT |
71 | |
72 | #define TG3_DEF_MAC_MODE 0 | |
73 | #define TG3_DEF_RX_MODE 0 | |
74 | #define TG3_DEF_TX_MODE 0 | |
75 | #define TG3_DEF_MSG_ENABLE \ | |
76 | (NETIF_MSG_DRV | \ | |
77 | NETIF_MSG_PROBE | \ | |
78 | NETIF_MSG_LINK | \ | |
79 | NETIF_MSG_TIMER | \ | |
80 | NETIF_MSG_IFDOWN | \ | |
81 | NETIF_MSG_IFUP | \ | |
82 | NETIF_MSG_RX_ERR | \ | |
83 | NETIF_MSG_TX_ERR) | |
84 | ||
85 | /* length of time before we decide the hardware is borked, | |
86 | * and dev->tx_timeout() should be called to fix the problem | |
87 | */ | |
88 | #define TG3_TX_TIMEOUT (5 * HZ) | |
89 | ||
90 | /* hardware minimum and maximum for a single frame's data payload */ | |
91 | #define TG3_MIN_MTU 60 | |
92 | #define TG3_MAX_MTU(tp) \ | |
8f666b07 | 93 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
94 | |
95 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
96 | * You can't change the ring sizes, but you can change where you place | |
97 | * them in the NIC onboard memory. | |
98 | */ | |
7cb32cf2 | 99 | #define TG3_RX_STD_RING_SIZE(tp) \ |
de9f5230 MC |
100 | ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ |
101 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) | |
1da177e4 | 102 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 103 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
de9f5230 MC |
104 | ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ |
105 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) | |
1da177e4 | 106 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
c6cdf436 | 107 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
108 | |
109 | /* Do not place this n-ring entries value into the tp struct itself, | |
110 | * we really want to expose these constants to GCC so that modulo et | |
111 | * al. operations are done with shifts and masks instead of with | |
112 | * hw multiply/modulo instructions. Another solution would be to | |
113 | * replace things like '% foo' with '& (foo - 1)'. | |
114 | */ | |
1da177e4 LT |
115 | |
116 | #define TG3_TX_RING_SIZE 512 | |
117 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
118 | ||
2c49a44d MC |
119 | #define TG3_RX_STD_RING_BYTES(tp) \ |
120 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
121 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
122 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
123 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 124 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
125 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
126 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
127 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
128 | ||
287be12e MC |
129 | #define TG3_DMA_BYTE_ENAB 64 |
130 | ||
131 | #define TG3_RX_STD_DMA_SZ 1536 | |
132 | #define TG3_RX_JMB_DMA_SZ 9046 | |
133 | ||
134 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
135 | ||
136 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
137 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 138 | |
2c49a44d MC |
139 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
140 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 141 | |
2c49a44d MC |
142 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
143 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 144 | |
d2757fc4 MC |
145 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
146 | * that are at least dword aligned when used in PCIX mode. The driver | |
147 | * works around this bug by double copying the packet. This workaround | |
148 | * is built into the normal double copy length check for efficiency. | |
149 | * | |
150 | * However, the double copy is only necessary on those architectures | |
151 | * where unaligned memory accesses are inefficient. For those architectures | |
152 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
153 | * the 5701 in the normal rx path. Doing so saves a device structure | |
154 | * dereference by hardcoding the double copy threshold in place. | |
155 | */ | |
156 | #define TG3_RX_COPY_THRESHOLD 256 | |
157 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
158 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
159 | #else | |
160 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
161 | #endif | |
162 | ||
1da177e4 | 163 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 164 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
1da177e4 | 165 | |
ad829268 MC |
166 | #define TG3_RAW_IP_ALIGN 2 |
167 | ||
c6cdf436 MC |
168 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
169 | ||
077f849d JSR |
170 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
171 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
172 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
173 | ||
1da177e4 | 174 | static char version[] __devinitdata = |
05dbe005 | 175 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
176 | |
177 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
178 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
179 | MODULE_LICENSE("GPL"); | |
180 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
181 | MODULE_FIRMWARE(FIRMWARE_TG3); |
182 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
183 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
184 | ||
1da177e4 LT |
185 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
186 | module_param(tg3_debug, int, 0); | |
187 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
188 | ||
a3aa1884 | 189 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
190 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
191 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
192 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
193 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
194 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
195 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
196 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
197 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
198 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
199 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
200 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
201 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
202 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
203 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
204 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
205 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
206 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
207 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
208 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
209 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
210 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
211 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 212 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 213 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 214 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
215 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
13185217 HK |
263 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
264 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
265 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
266 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
267 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
268 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
269 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
270 | {} | |
1da177e4 LT |
271 | }; |
272 | ||
273 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
274 | ||
50da859d | 275 | static const struct { |
1da177e4 | 276 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 277 | } ethtool_stats_keys[] = { |
1da177e4 LT |
278 | { "rx_octets" }, |
279 | { "rx_fragments" }, | |
280 | { "rx_ucast_packets" }, | |
281 | { "rx_mcast_packets" }, | |
282 | { "rx_bcast_packets" }, | |
283 | { "rx_fcs_errors" }, | |
284 | { "rx_align_errors" }, | |
285 | { "rx_xon_pause_rcvd" }, | |
286 | { "rx_xoff_pause_rcvd" }, | |
287 | { "rx_mac_ctrl_rcvd" }, | |
288 | { "rx_xoff_entered" }, | |
289 | { "rx_frame_too_long_errors" }, | |
290 | { "rx_jabbers" }, | |
291 | { "rx_undersize_packets" }, | |
292 | { "rx_in_length_errors" }, | |
293 | { "rx_out_length_errors" }, | |
294 | { "rx_64_or_less_octet_packets" }, | |
295 | { "rx_65_to_127_octet_packets" }, | |
296 | { "rx_128_to_255_octet_packets" }, | |
297 | { "rx_256_to_511_octet_packets" }, | |
298 | { "rx_512_to_1023_octet_packets" }, | |
299 | { "rx_1024_to_1522_octet_packets" }, | |
300 | { "rx_1523_to_2047_octet_packets" }, | |
301 | { "rx_2048_to_4095_octet_packets" }, | |
302 | { "rx_4096_to_8191_octet_packets" }, | |
303 | { "rx_8192_to_9022_octet_packets" }, | |
304 | ||
305 | { "tx_octets" }, | |
306 | { "tx_collisions" }, | |
307 | ||
308 | { "tx_xon_sent" }, | |
309 | { "tx_xoff_sent" }, | |
310 | { "tx_flow_control" }, | |
311 | { "tx_mac_errors" }, | |
312 | { "tx_single_collisions" }, | |
313 | { "tx_mult_collisions" }, | |
314 | { "tx_deferred" }, | |
315 | { "tx_excessive_collisions" }, | |
316 | { "tx_late_collisions" }, | |
317 | { "tx_collide_2times" }, | |
318 | { "tx_collide_3times" }, | |
319 | { "tx_collide_4times" }, | |
320 | { "tx_collide_5times" }, | |
321 | { "tx_collide_6times" }, | |
322 | { "tx_collide_7times" }, | |
323 | { "tx_collide_8times" }, | |
324 | { "tx_collide_9times" }, | |
325 | { "tx_collide_10times" }, | |
326 | { "tx_collide_11times" }, | |
327 | { "tx_collide_12times" }, | |
328 | { "tx_collide_13times" }, | |
329 | { "tx_collide_14times" }, | |
330 | { "tx_collide_15times" }, | |
331 | { "tx_ucast_packets" }, | |
332 | { "tx_mcast_packets" }, | |
333 | { "tx_bcast_packets" }, | |
334 | { "tx_carrier_sense_errors" }, | |
335 | { "tx_discards" }, | |
336 | { "tx_errors" }, | |
337 | ||
338 | { "dma_writeq_full" }, | |
339 | { "dma_write_prioq_full" }, | |
340 | { "rxbds_empty" }, | |
341 | { "rx_discards" }, | |
4d958473 | 342 | { "mbuf_lwm_thresh_hit" }, |
1da177e4 LT |
343 | { "rx_errors" }, |
344 | { "rx_threshold_hit" }, | |
345 | ||
346 | { "dma_readq_full" }, | |
347 | { "dma_read_prioq_full" }, | |
348 | { "tx_comp_queue_full" }, | |
349 | ||
350 | { "ring_set_send_prod_index" }, | |
351 | { "ring_status_update" }, | |
352 | { "nic_irqs" }, | |
353 | { "nic_avoided_irqs" }, | |
354 | { "nic_tx_threshold_hit" } | |
355 | }; | |
356 | ||
48fa55a0 MC |
357 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
358 | ||
359 | ||
50da859d | 360 | static const struct { |
4cafd3f5 | 361 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 362 | } ethtool_test_keys[] = { |
4cafd3f5 MC |
363 | { "nvram test (online) " }, |
364 | { "link test (online) " }, | |
365 | { "register test (offline)" }, | |
366 | { "memory test (offline)" }, | |
367 | { "loopback test (offline)" }, | |
368 | { "interrupt test (offline)" }, | |
369 | }; | |
370 | ||
48fa55a0 MC |
371 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
372 | ||
373 | ||
b401e9e2 MC |
374 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
375 | { | |
376 | writel(val, tp->regs + off); | |
377 | } | |
378 | ||
379 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
380 | { | |
de6f31eb | 381 | return readl(tp->regs + off); |
b401e9e2 MC |
382 | } |
383 | ||
0d3031d9 MC |
384 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
385 | { | |
386 | writel(val, tp->aperegs + off); | |
387 | } | |
388 | ||
389 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
390 | { | |
de6f31eb | 391 | return readl(tp->aperegs + off); |
0d3031d9 MC |
392 | } |
393 | ||
1da177e4 LT |
394 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
395 | { | |
6892914f MC |
396 | unsigned long flags; |
397 | ||
398 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
399 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
400 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 401 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
402 | } |
403 | ||
404 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
405 | { | |
406 | writel(val, tp->regs + off); | |
407 | readl(tp->regs + off); | |
1da177e4 LT |
408 | } |
409 | ||
6892914f | 410 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 411 | { |
6892914f MC |
412 | unsigned long flags; |
413 | u32 val; | |
414 | ||
415 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
416 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
417 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
418 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
419 | return val; | |
420 | } | |
421 | ||
422 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
423 | { | |
424 | unsigned long flags; | |
425 | ||
426 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
427 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
428 | TG3_64BIT_REG_LOW, val); | |
429 | return; | |
430 | } | |
66711e66 | 431 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
432 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
433 | TG3_64BIT_REG_LOW, val); | |
434 | return; | |
1da177e4 | 435 | } |
6892914f MC |
436 | |
437 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
438 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
439 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
440 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
441 | ||
442 | /* In indirect mode when disabling interrupts, we also need | |
443 | * to clear the interrupt bit in the GRC local ctrl register. | |
444 | */ | |
445 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
446 | (val == 0x1)) { | |
447 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
448 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
449 | } | |
450 | } | |
451 | ||
452 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
453 | { | |
454 | unsigned long flags; | |
455 | u32 val; | |
456 | ||
457 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
458 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
459 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
460 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
461 | return val; | |
462 | } | |
463 | ||
b401e9e2 MC |
464 | /* usec_wait specifies the wait time in usec when writing to certain registers |
465 | * where it is unsafe to read back the register without some delay. | |
466 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
467 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
468 | */ | |
469 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 470 | { |
b401e9e2 MC |
471 | if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || |
472 | (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
473 | /* Non-posted methods */ | |
474 | tp->write32(tp, off, val); | |
475 | else { | |
476 | /* Posted method */ | |
477 | tg3_write32(tp, off, val); | |
478 | if (usec_wait) | |
479 | udelay(usec_wait); | |
480 | tp->read32(tp, off); | |
481 | } | |
482 | /* Wait again after the read for the posted method to guarantee that | |
483 | * the wait time is met. | |
484 | */ | |
485 | if (usec_wait) | |
486 | udelay(usec_wait); | |
1da177e4 LT |
487 | } |
488 | ||
09ee929c MC |
489 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
490 | { | |
491 | tp->write32_mbox(tp, off, val); | |
6892914f MC |
492 | if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && |
493 | !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
494 | tp->read32_mbox(tp, off); | |
09ee929c MC |
495 | } |
496 | ||
20094930 | 497 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
498 | { |
499 | void __iomem *mbox = tp->regs + off; | |
500 | writel(val, mbox); | |
501 | if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) | |
502 | writel(val, mbox); | |
503 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
504 | readl(mbox); | |
505 | } | |
506 | ||
b5d3772c MC |
507 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
508 | { | |
de6f31eb | 509 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
510 | } |
511 | ||
512 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
513 | { | |
514 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
515 | } | |
516 | ||
c6cdf436 | 517 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 518 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
519 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
520 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
521 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 522 | |
c6cdf436 MC |
523 | #define tw32(reg, val) tp->write32(tp, reg, val) |
524 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
525 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
526 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
527 | |
528 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
529 | { | |
6892914f MC |
530 | unsigned long flags; |
531 | ||
b5d3772c MC |
532 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
533 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
534 | return; | |
535 | ||
6892914f | 536 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
537 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
538 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
539 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 540 | |
bbadf503 MC |
541 | /* Always leave this as zero. */ |
542 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
543 | } else { | |
544 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
545 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 546 | |
bbadf503 MC |
547 | /* Always leave this as zero. */ |
548 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
549 | } | |
550 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
551 | } |
552 | ||
1da177e4 LT |
553 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
554 | { | |
6892914f MC |
555 | unsigned long flags; |
556 | ||
b5d3772c MC |
557 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
558 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
559 | *val = 0; | |
560 | return; | |
561 | } | |
562 | ||
6892914f | 563 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
564 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
565 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
566 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 567 | |
bbadf503 MC |
568 | /* Always leave this as zero. */ |
569 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
570 | } else { | |
571 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
572 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
573 | ||
574 | /* Always leave this as zero. */ | |
575 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
576 | } | |
6892914f | 577 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
578 | } |
579 | ||
0d3031d9 MC |
580 | static void tg3_ape_lock_init(struct tg3 *tp) |
581 | { | |
582 | int i; | |
f92d9dc1 MC |
583 | u32 regbase; |
584 | ||
585 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
586 | regbase = TG3_APE_LOCK_GRANT; | |
587 | else | |
588 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
589 | |
590 | /* Make sure the driver hasn't any stale locks. */ | |
591 | for (i = 0; i < 8; i++) | |
f92d9dc1 | 592 | tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER); |
0d3031d9 MC |
593 | } |
594 | ||
595 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
596 | { | |
597 | int i, off; | |
598 | int ret = 0; | |
f92d9dc1 | 599 | u32 status, req, gnt; |
0d3031d9 MC |
600 | |
601 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
602 | return 0; | |
603 | ||
604 | switch (locknum) { | |
33f401ae MC |
605 | case TG3_APE_LOCK_GRC: |
606 | case TG3_APE_LOCK_MEM: | |
607 | break; | |
608 | default: | |
609 | return -EINVAL; | |
0d3031d9 MC |
610 | } |
611 | ||
f92d9dc1 MC |
612 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
613 | req = TG3_APE_LOCK_REQ; | |
614 | gnt = TG3_APE_LOCK_GRANT; | |
615 | } else { | |
616 | req = TG3_APE_PER_LOCK_REQ; | |
617 | gnt = TG3_APE_PER_LOCK_GRANT; | |
618 | } | |
619 | ||
0d3031d9 MC |
620 | off = 4 * locknum; |
621 | ||
f92d9dc1 | 622 | tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER); |
0d3031d9 MC |
623 | |
624 | /* Wait for up to 1 millisecond to acquire lock. */ | |
625 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 626 | status = tg3_ape_read32(tp, gnt + off); |
0d3031d9 MC |
627 | if (status == APE_LOCK_GRANT_DRIVER) |
628 | break; | |
629 | udelay(10); | |
630 | } | |
631 | ||
632 | if (status != APE_LOCK_GRANT_DRIVER) { | |
633 | /* Revoke the lock request. */ | |
f92d9dc1 | 634 | tg3_ape_write32(tp, gnt + off, |
0d3031d9 MC |
635 | APE_LOCK_GRANT_DRIVER); |
636 | ||
637 | ret = -EBUSY; | |
638 | } | |
639 | ||
640 | return ret; | |
641 | } | |
642 | ||
643 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
644 | { | |
f92d9dc1 | 645 | u32 gnt; |
0d3031d9 MC |
646 | |
647 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
648 | return; | |
649 | ||
650 | switch (locknum) { | |
33f401ae MC |
651 | case TG3_APE_LOCK_GRC: |
652 | case TG3_APE_LOCK_MEM: | |
653 | break; | |
654 | default: | |
655 | return; | |
0d3031d9 MC |
656 | } |
657 | ||
f92d9dc1 MC |
658 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
659 | gnt = TG3_APE_LOCK_GRANT; | |
660 | else | |
661 | gnt = TG3_APE_PER_LOCK_GRANT; | |
662 | ||
663 | tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER); | |
0d3031d9 MC |
664 | } |
665 | ||
1da177e4 LT |
666 | static void tg3_disable_ints(struct tg3 *tp) |
667 | { | |
89aeb3bc MC |
668 | int i; |
669 | ||
1da177e4 LT |
670 | tw32(TG3PCI_MISC_HOST_CTRL, |
671 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
672 | for (i = 0; i < tp->irq_max; i++) |
673 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
674 | } |
675 | ||
1da177e4 LT |
676 | static void tg3_enable_ints(struct tg3 *tp) |
677 | { | |
89aeb3bc | 678 | int i; |
89aeb3bc | 679 | |
bbe832c0 MC |
680 | tp->irq_sync = 0; |
681 | wmb(); | |
682 | ||
1da177e4 LT |
683 | tw32(TG3PCI_MISC_HOST_CTRL, |
684 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 685 | |
f89f38b8 | 686 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
687 | for (i = 0; i < tp->irq_cnt; i++) { |
688 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 689 | |
898a56f8 | 690 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
89aeb3bc MC |
691 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) |
692 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
f19af9c2 | 693 | |
f89f38b8 | 694 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 695 | } |
f19af9c2 MC |
696 | |
697 | /* Force an initial interrupt */ | |
698 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
699 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) | |
700 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
701 | else | |
f89f38b8 MC |
702 | tw32(HOSTCC_MODE, tp->coal_now); |
703 | ||
704 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
705 | } |
706 | ||
17375d25 | 707 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 708 | { |
17375d25 | 709 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 710 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
711 | unsigned int work_exists = 0; |
712 | ||
713 | /* check for phy events */ | |
714 | if (!(tp->tg3_flags & | |
715 | (TG3_FLAG_USE_LINKCHG_REG | | |
716 | TG3_FLAG_POLL_SERDES))) { | |
717 | if (sblk->status & SD_STATUS_LINK_CHG) | |
718 | work_exists = 1; | |
719 | } | |
720 | /* check for RX/TX work to do */ | |
f3f3f27e | 721 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 722 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
723 | work_exists = 1; |
724 | ||
725 | return work_exists; | |
726 | } | |
727 | ||
17375d25 | 728 | /* tg3_int_reenable |
04237ddd MC |
729 | * similar to tg3_enable_ints, but it accurately determines whether there |
730 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 731 | * which reenables interrupts |
1da177e4 | 732 | */ |
17375d25 | 733 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 734 | { |
17375d25 MC |
735 | struct tg3 *tp = tnapi->tp; |
736 | ||
898a56f8 | 737 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
738 | mmiowb(); |
739 | ||
fac9b83e DM |
740 | /* When doing tagged status, this work check is unnecessary. |
741 | * The last_tag we write above tells the chip which piece of | |
742 | * work we've completed. | |
743 | */ | |
744 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
17375d25 | 745 | tg3_has_work(tnapi)) |
04237ddd | 746 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 747 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
748 | } |
749 | ||
1da177e4 LT |
750 | static void tg3_switch_clocks(struct tg3 *tp) |
751 | { | |
f6eb9b1f | 752 | u32 clock_ctrl; |
1da177e4 LT |
753 | u32 orig_clock_ctrl; |
754 | ||
795d01c5 MC |
755 | if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
756 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
4cf78e4f MC |
757 | return; |
758 | ||
f6eb9b1f MC |
759 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
760 | ||
1da177e4 LT |
761 | orig_clock_ctrl = clock_ctrl; |
762 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
763 | CLOCK_CTRL_CLKRUN_OENABLE | | |
764 | 0x1f); | |
765 | tp->pci_clock_ctrl = clock_ctrl; | |
766 | ||
767 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
768 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
b401e9e2 MC |
769 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
770 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
771 | } |
772 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
773 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
774 | clock_ctrl | | |
775 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
776 | 40); | |
777 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
778 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
779 | 40); | |
1da177e4 | 780 | } |
b401e9e2 | 781 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
782 | } |
783 | ||
784 | #define PHY_BUSY_LOOPS 5000 | |
785 | ||
786 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
787 | { | |
788 | u32 frame_val; | |
789 | unsigned int loops; | |
790 | int ret; | |
791 | ||
792 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
793 | tw32_f(MAC_MI_MODE, | |
794 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
795 | udelay(80); | |
796 | } | |
797 | ||
798 | *val = 0x0; | |
799 | ||
882e9793 | 800 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
801 | MI_COM_PHY_ADDR_MASK); |
802 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
803 | MI_COM_REG_ADDR_MASK); | |
804 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 805 | |
1da177e4 LT |
806 | tw32_f(MAC_MI_COM, frame_val); |
807 | ||
808 | loops = PHY_BUSY_LOOPS; | |
809 | while (loops != 0) { | |
810 | udelay(10); | |
811 | frame_val = tr32(MAC_MI_COM); | |
812 | ||
813 | if ((frame_val & MI_COM_BUSY) == 0) { | |
814 | udelay(5); | |
815 | frame_val = tr32(MAC_MI_COM); | |
816 | break; | |
817 | } | |
818 | loops -= 1; | |
819 | } | |
820 | ||
821 | ret = -EBUSY; | |
822 | if (loops != 0) { | |
823 | *val = frame_val & MI_COM_DATA_MASK; | |
824 | ret = 0; | |
825 | } | |
826 | ||
827 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
828 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
829 | udelay(80); | |
830 | } | |
831 | ||
832 | return ret; | |
833 | } | |
834 | ||
835 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
836 | { | |
837 | u32 frame_val; | |
838 | unsigned int loops; | |
839 | int ret; | |
840 | ||
f07e9af3 | 841 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
b5d3772c MC |
842 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) |
843 | return 0; | |
844 | ||
1da177e4 LT |
845 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
846 | tw32_f(MAC_MI_MODE, | |
847 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
848 | udelay(80); | |
849 | } | |
850 | ||
882e9793 | 851 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
852 | MI_COM_PHY_ADDR_MASK); |
853 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
854 | MI_COM_REG_ADDR_MASK); | |
855 | frame_val |= (val & MI_COM_DATA_MASK); | |
856 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 857 | |
1da177e4 LT |
858 | tw32_f(MAC_MI_COM, frame_val); |
859 | ||
860 | loops = PHY_BUSY_LOOPS; | |
861 | while (loops != 0) { | |
862 | udelay(10); | |
863 | frame_val = tr32(MAC_MI_COM); | |
864 | if ((frame_val & MI_COM_BUSY) == 0) { | |
865 | udelay(5); | |
866 | frame_val = tr32(MAC_MI_COM); | |
867 | break; | |
868 | } | |
869 | loops -= 1; | |
870 | } | |
871 | ||
872 | ret = -EBUSY; | |
873 | if (loops != 0) | |
874 | ret = 0; | |
875 | ||
876 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
877 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
878 | udelay(80); | |
879 | } | |
880 | ||
881 | return ret; | |
882 | } | |
883 | ||
b0988c15 MC |
884 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
885 | { | |
886 | int err; | |
887 | ||
888 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
889 | if (err) | |
890 | goto done; | |
891 | ||
892 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
893 | if (err) | |
894 | goto done; | |
895 | ||
896 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
897 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
898 | if (err) | |
899 | goto done; | |
900 | ||
901 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
902 | ||
903 | done: | |
904 | return err; | |
905 | } | |
906 | ||
907 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
908 | { | |
909 | int err; | |
910 | ||
911 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
912 | if (err) | |
913 | goto done; | |
914 | ||
915 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
916 | if (err) | |
917 | goto done; | |
918 | ||
919 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
920 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
921 | if (err) | |
922 | goto done; | |
923 | ||
924 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
925 | ||
926 | done: | |
927 | return err; | |
928 | } | |
929 | ||
930 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) | |
931 | { | |
932 | int err; | |
933 | ||
934 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
935 | if (!err) | |
936 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
937 | ||
938 | return err; | |
939 | } | |
940 | ||
941 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | |
942 | { | |
943 | int err; | |
944 | ||
945 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
946 | if (!err) | |
947 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
948 | ||
949 | return err; | |
950 | } | |
951 | ||
15ee95c3 MC |
952 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
953 | { | |
954 | int err; | |
955 | ||
956 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
957 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | | |
958 | MII_TG3_AUXCTL_SHDWSEL_MISC); | |
959 | if (!err) | |
960 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); | |
961 | ||
962 | return err; | |
963 | } | |
964 | ||
b4bd2929 MC |
965 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
966 | { | |
967 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) | |
968 | set |= MII_TG3_AUXCTL_MISC_WREN; | |
969 | ||
970 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); | |
971 | } | |
972 | ||
1d36ba45 MC |
973 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
974 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
975 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ | |
976 | MII_TG3_AUXCTL_ACTL_TX_6DB) | |
977 | ||
978 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ | |
979 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ | |
980 | MII_TG3_AUXCTL_ACTL_TX_6DB); | |
981 | ||
95e2869a MC |
982 | static int tg3_bmcr_reset(struct tg3 *tp) |
983 | { | |
984 | u32 phy_control; | |
985 | int limit, err; | |
986 | ||
987 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
988 | * clears or we time out. | |
989 | */ | |
990 | phy_control = BMCR_RESET; | |
991 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
992 | if (err != 0) | |
993 | return -EBUSY; | |
994 | ||
995 | limit = 5000; | |
996 | while (limit--) { | |
997 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
998 | if (err != 0) | |
999 | return -EBUSY; | |
1000 | ||
1001 | if ((phy_control & BMCR_RESET) == 0) { | |
1002 | udelay(40); | |
1003 | break; | |
1004 | } | |
1005 | udelay(10); | |
1006 | } | |
d4675b52 | 1007 | if (limit < 0) |
95e2869a MC |
1008 | return -EBUSY; |
1009 | ||
1010 | return 0; | |
1011 | } | |
1012 | ||
158d7abd MC |
1013 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
1014 | { | |
3d16543d | 1015 | struct tg3 *tp = bp->priv; |
158d7abd MC |
1016 | u32 val; |
1017 | ||
24bb4fb6 | 1018 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1019 | |
1020 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
1021 | val = -EIO; |
1022 | ||
1023 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
1024 | |
1025 | return val; | |
1026 | } | |
1027 | ||
1028 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
1029 | { | |
3d16543d | 1030 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 1031 | u32 ret = 0; |
158d7abd | 1032 | |
24bb4fb6 | 1033 | spin_lock_bh(&tp->lock); |
158d7abd MC |
1034 | |
1035 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 1036 | ret = -EIO; |
158d7abd | 1037 | |
24bb4fb6 MC |
1038 | spin_unlock_bh(&tp->lock); |
1039 | ||
1040 | return ret; | |
158d7abd MC |
1041 | } |
1042 | ||
1043 | static int tg3_mdio_reset(struct mii_bus *bp) | |
1044 | { | |
1045 | return 0; | |
1046 | } | |
1047 | ||
9c61d6bc | 1048 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
1049 | { |
1050 | u32 val; | |
fcb389df | 1051 | struct phy_device *phydev; |
a9daf367 | 1052 | |
3f0e3ad7 | 1053 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 1054 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
1055 | case PHY_ID_BCM50610: |
1056 | case PHY_ID_BCM50610M: | |
fcb389df MC |
1057 | val = MAC_PHYCFG2_50610_LED_MODES; |
1058 | break; | |
6a443a0f | 1059 | case PHY_ID_BCMAC131: |
fcb389df MC |
1060 | val = MAC_PHYCFG2_AC131_LED_MODES; |
1061 | break; | |
6a443a0f | 1062 | case PHY_ID_RTL8211C: |
fcb389df MC |
1063 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
1064 | break; | |
6a443a0f | 1065 | case PHY_ID_RTL8201E: |
fcb389df MC |
1066 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
1067 | break; | |
1068 | default: | |
a9daf367 | 1069 | return; |
fcb389df MC |
1070 | } |
1071 | ||
1072 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
1073 | tw32(MAC_PHYCFG2, val); | |
1074 | ||
1075 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1076 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1077 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1078 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1079 | tw32(MAC_PHYCFG1, val); |
1080 | ||
1081 | return; | |
1082 | } | |
1083 | ||
14417063 | 1084 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) |
fcb389df MC |
1085 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1086 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1087 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1088 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1089 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1090 | MAC_PHYCFG2_INBAND_ENABLE; | |
1091 | ||
1092 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1093 | |
bb85fbb6 MC |
1094 | val = tr32(MAC_PHYCFG1); |
1095 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1096 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
14417063 | 1097 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
1098 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1099 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
1100 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1101 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
1102 | } | |
bb85fbb6 MC |
1103 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1104 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1105 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1106 | |
a9daf367 MC |
1107 | val = tr32(MAC_EXT_RGMII_MODE); |
1108 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1109 | MAC_RGMII_MODE_RX_QUALITY | | |
1110 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1111 | MAC_RGMII_MODE_RX_ENG_DET | | |
1112 | MAC_RGMII_MODE_TX_ENABLE | | |
1113 | MAC_RGMII_MODE_TX_LOWPWR | | |
1114 | MAC_RGMII_MODE_TX_RESET); | |
14417063 | 1115 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
1116 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1117 | val |= MAC_RGMII_MODE_RX_INT_B | | |
1118 | MAC_RGMII_MODE_RX_QUALITY | | |
1119 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1120 | MAC_RGMII_MODE_RX_ENG_DET; | |
1121 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1122 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
1123 | MAC_RGMII_MODE_TX_LOWPWR | | |
1124 | MAC_RGMII_MODE_TX_RESET; | |
1125 | } | |
1126 | tw32(MAC_EXT_RGMII_MODE, val); | |
1127 | } | |
1128 | ||
158d7abd MC |
1129 | static void tg3_mdio_start(struct tg3 *tp) |
1130 | { | |
158d7abd MC |
1131 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1132 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1133 | udelay(80); | |
a9daf367 | 1134 | |
9ea4818d MC |
1135 | if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && |
1136 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1137 | tg3_mdio_config_5785(tp); | |
1138 | } | |
1139 | ||
1140 | static int tg3_mdio_init(struct tg3 *tp) | |
1141 | { | |
1142 | int i; | |
1143 | u32 reg; | |
1144 | struct phy_device *phydev; | |
1145 | ||
0a58d668 | 1146 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
9c7df915 | 1147 | u32 is_serdes; |
882e9793 | 1148 | |
9c7df915 | 1149 | tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1; |
882e9793 | 1150 | |
d1ec96af MC |
1151 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1152 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1153 | else | |
1154 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1155 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1156 | if (is_serdes) |
1157 | tp->phy_addr += 7; | |
1158 | } else | |
3f0e3ad7 | 1159 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1160 | |
158d7abd MC |
1161 | tg3_mdio_start(tp); |
1162 | ||
1163 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || | |
1164 | (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)) | |
1165 | return 0; | |
1166 | ||
298cf9be LB |
1167 | tp->mdio_bus = mdiobus_alloc(); |
1168 | if (tp->mdio_bus == NULL) | |
1169 | return -ENOMEM; | |
158d7abd | 1170 | |
298cf9be LB |
1171 | tp->mdio_bus->name = "tg3 mdio bus"; |
1172 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1173 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1174 | tp->mdio_bus->priv = tp; |
1175 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1176 | tp->mdio_bus->read = &tg3_mdio_read; | |
1177 | tp->mdio_bus->write = &tg3_mdio_write; | |
1178 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1179 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1180 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1181 | |
1182 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1183 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1184 | |
1185 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1186 | * Unfortunately, it does not ensure the PHY is powered up before | |
1187 | * accessing the PHY ID registers. A chip reset is the | |
1188 | * quickest way to bring the device back to an operational state.. | |
1189 | */ | |
1190 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1191 | tg3_bmcr_reset(tp); | |
1192 | ||
298cf9be | 1193 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1194 | if (i) { |
ab96b241 | 1195 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1196 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1197 | return i; |
1198 | } | |
158d7abd | 1199 | |
3f0e3ad7 | 1200 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1201 | |
9c61d6bc | 1202 | if (!phydev || !phydev->drv) { |
ab96b241 | 1203 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1204 | mdiobus_unregister(tp->mdio_bus); |
1205 | mdiobus_free(tp->mdio_bus); | |
1206 | return -ENODEV; | |
1207 | } | |
1208 | ||
1209 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1210 | case PHY_ID_BCM57780: |
321d32a0 | 1211 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1212 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1213 | break; |
6a443a0f MC |
1214 | case PHY_ID_BCM50610: |
1215 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1216 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1217 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1218 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1219 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
14417063 | 1220 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE) |
a9daf367 MC |
1221 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
1222 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1223 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1224 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1225 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
fcb389df | 1226 | /* fallthru */ |
6a443a0f | 1227 | case PHY_ID_RTL8211C: |
fcb389df | 1228 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1229 | break; |
6a443a0f MC |
1230 | case PHY_ID_RTL8201E: |
1231 | case PHY_ID_BCMAC131: | |
a9daf367 | 1232 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1233 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1234 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1235 | break; |
1236 | } | |
1237 | ||
9c61d6bc MC |
1238 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; |
1239 | ||
1240 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1241 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1242 | |
1243 | return 0; | |
158d7abd MC |
1244 | } |
1245 | ||
1246 | static void tg3_mdio_fini(struct tg3 *tp) | |
1247 | { | |
1248 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
1249 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; | |
298cf9be LB |
1250 | mdiobus_unregister(tp->mdio_bus); |
1251 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1252 | } |
1253 | } | |
1254 | ||
4ba526ce MC |
1255 | /* tp->lock is held. */ |
1256 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1257 | { | |
1258 | u32 val; | |
1259 | ||
1260 | val = tr32(GRC_RX_CPU_EVENT); | |
1261 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1262 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1263 | ||
1264 | tp->last_event_jiffies = jiffies; | |
1265 | } | |
1266 | ||
1267 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1268 | ||
95e2869a MC |
1269 | /* tp->lock is held. */ |
1270 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1271 | { | |
1272 | int i; | |
4ba526ce MC |
1273 | unsigned int delay_cnt; |
1274 | long time_remain; | |
1275 | ||
1276 | /* If enough time has passed, no wait is necessary. */ | |
1277 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1278 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1279 | (long)jiffies; | |
1280 | if (time_remain < 0) | |
1281 | return; | |
1282 | ||
1283 | /* Check if we can shorten the wait time. */ | |
1284 | delay_cnt = jiffies_to_usecs(time_remain); | |
1285 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1286 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1287 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1288 | |
4ba526ce | 1289 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1290 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1291 | break; | |
4ba526ce | 1292 | udelay(8); |
95e2869a MC |
1293 | } |
1294 | } | |
1295 | ||
1296 | /* tp->lock is held. */ | |
1297 | static void tg3_ump_link_report(struct tg3 *tp) | |
1298 | { | |
1299 | u32 reg; | |
1300 | u32 val; | |
1301 | ||
1302 | if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
1303 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
1304 | return; | |
1305 | ||
1306 | tg3_wait_for_event_ack(tp); | |
1307 | ||
1308 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1309 | ||
1310 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1311 | ||
1312 | val = 0; | |
1313 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1314 | val = reg << 16; | |
1315 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1316 | val |= (reg & 0xffff); | |
1317 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1318 | ||
1319 | val = 0; | |
1320 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1321 | val = reg << 16; | |
1322 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1323 | val |= (reg & 0xffff); | |
1324 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1325 | ||
1326 | val = 0; | |
f07e9af3 | 1327 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1328 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1329 | val = reg << 16; | |
1330 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1331 | val |= (reg & 0xffff); | |
1332 | } | |
1333 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1334 | ||
1335 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1336 | val = reg << 16; | |
1337 | else | |
1338 | val = 0; | |
1339 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1340 | ||
4ba526ce | 1341 | tg3_generate_fw_event(tp); |
95e2869a MC |
1342 | } |
1343 | ||
1344 | static void tg3_link_report(struct tg3 *tp) | |
1345 | { | |
1346 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1347 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1348 | tg3_ump_link_report(tp); |
1349 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1350 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1351 | (tp->link_config.active_speed == SPEED_1000 ? | |
1352 | 1000 : | |
1353 | (tp->link_config.active_speed == SPEED_100 ? | |
1354 | 100 : 10)), | |
1355 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1356 | "full" : "half")); | |
1357 | ||
1358 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1359 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1360 | "on" : "off", | |
1361 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1362 | "on" : "off"); | |
95e2869a MC |
1363 | tg3_ump_link_report(tp); |
1364 | } | |
1365 | } | |
1366 | ||
1367 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1368 | { | |
1369 | u16 miireg; | |
1370 | ||
e18ce346 | 1371 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1372 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1373 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1374 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1375 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1376 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1377 | else | |
1378 | miireg = 0; | |
1379 | ||
1380 | return miireg; | |
1381 | } | |
1382 | ||
1383 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1384 | { | |
1385 | u16 miireg; | |
1386 | ||
e18ce346 | 1387 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1388 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1389 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1390 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1391 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1392 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1393 | else | |
1394 | miireg = 0; | |
1395 | ||
1396 | return miireg; | |
1397 | } | |
1398 | ||
95e2869a MC |
1399 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1400 | { | |
1401 | u8 cap = 0; | |
1402 | ||
1403 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1404 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1405 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1406 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1407 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1408 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1409 | } else { |
1410 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1411 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1412 | } |
1413 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1414 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1415 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1416 | } |
1417 | ||
1418 | return cap; | |
1419 | } | |
1420 | ||
f51f3562 | 1421 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1422 | { |
b02fd9e3 | 1423 | u8 autoneg; |
f51f3562 | 1424 | u8 flowctrl = 0; |
95e2869a MC |
1425 | u32 old_rx_mode = tp->rx_mode; |
1426 | u32 old_tx_mode = tp->tx_mode; | |
1427 | ||
b02fd9e3 | 1428 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
3f0e3ad7 | 1429 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1430 | else |
1431 | autoneg = tp->link_config.autoneg; | |
1432 | ||
1433 | if (autoneg == AUTONEG_ENABLE && | |
95e2869a | 1434 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { |
f07e9af3 | 1435 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1436 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1437 | else |
bc02ff95 | 1438 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1439 | } else |
1440 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1441 | |
f51f3562 | 1442 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1443 | |
e18ce346 | 1444 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1445 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1446 | else | |
1447 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1448 | ||
f51f3562 | 1449 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1450 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1451 | |
e18ce346 | 1452 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1453 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1454 | else | |
1455 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1456 | ||
f51f3562 | 1457 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1458 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1459 | } |
1460 | ||
b02fd9e3 MC |
1461 | static void tg3_adjust_link(struct net_device *dev) |
1462 | { | |
1463 | u8 oldflowctrl, linkmesg = 0; | |
1464 | u32 mac_mode, lcl_adv, rmt_adv; | |
1465 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1466 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1467 | |
24bb4fb6 | 1468 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1469 | |
1470 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1471 | MAC_MODE_HALF_DUPLEX); | |
1472 | ||
1473 | oldflowctrl = tp->link_config.active_flowctrl; | |
1474 | ||
1475 | if (phydev->link) { | |
1476 | lcl_adv = 0; | |
1477 | rmt_adv = 0; | |
1478 | ||
1479 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1480 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1481 | else if (phydev->speed == SPEED_1000 || |
1482 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1483 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1484 | else |
1485 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1486 | |
1487 | if (phydev->duplex == DUPLEX_HALF) | |
1488 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1489 | else { | |
1490 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1491 | tp->link_config.flowctrl); | |
1492 | ||
1493 | if (phydev->pause) | |
1494 | rmt_adv = LPA_PAUSE_CAP; | |
1495 | if (phydev->asym_pause) | |
1496 | rmt_adv |= LPA_PAUSE_ASYM; | |
1497 | } | |
1498 | ||
1499 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1500 | } else | |
1501 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1502 | ||
1503 | if (mac_mode != tp->mac_mode) { | |
1504 | tp->mac_mode = mac_mode; | |
1505 | tw32_f(MAC_MODE, tp->mac_mode); | |
1506 | udelay(40); | |
1507 | } | |
1508 | ||
fcb389df MC |
1509 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1510 | if (phydev->speed == SPEED_10) | |
1511 | tw32(MAC_MI_STAT, | |
1512 | MAC_MI_STAT_10MBPS_MODE | | |
1513 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1514 | else | |
1515 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1516 | } | |
1517 | ||
b02fd9e3 MC |
1518 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1519 | tw32(MAC_TX_LENGTHS, | |
1520 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1521 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1522 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1523 | else | |
1524 | tw32(MAC_TX_LENGTHS, | |
1525 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1526 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1527 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1528 | ||
1529 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1530 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1531 | phydev->speed != tp->link_config.active_speed || | |
1532 | phydev->duplex != tp->link_config.active_duplex || | |
1533 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1534 | linkmesg = 1; |
b02fd9e3 MC |
1535 | |
1536 | tp->link_config.active_speed = phydev->speed; | |
1537 | tp->link_config.active_duplex = phydev->duplex; | |
1538 | ||
24bb4fb6 | 1539 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1540 | |
1541 | if (linkmesg) | |
1542 | tg3_link_report(tp); | |
1543 | } | |
1544 | ||
1545 | static int tg3_phy_init(struct tg3 *tp) | |
1546 | { | |
1547 | struct phy_device *phydev; | |
1548 | ||
f07e9af3 | 1549 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1550 | return 0; |
1551 | ||
1552 | /* Bring the PHY back to a known state. */ | |
1553 | tg3_bmcr_reset(tp); | |
1554 | ||
3f0e3ad7 | 1555 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1556 | |
1557 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1558 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1559 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1560 | if (IS_ERR(phydev)) { |
ab96b241 | 1561 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1562 | return PTR_ERR(phydev); |
1563 | } | |
1564 | ||
b02fd9e3 | 1565 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1566 | switch (phydev->interface) { |
1567 | case PHY_INTERFACE_MODE_GMII: | |
1568 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1569 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1570 | phydev->supported &= (PHY_GBIT_FEATURES | |
1571 | SUPPORTED_Pause | | |
1572 | SUPPORTED_Asym_Pause); | |
1573 | break; | |
1574 | } | |
1575 | /* fallthru */ | |
9c61d6bc MC |
1576 | case PHY_INTERFACE_MODE_MII: |
1577 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1578 | SUPPORTED_Pause | | |
1579 | SUPPORTED_Asym_Pause); | |
1580 | break; | |
1581 | default: | |
3f0e3ad7 | 1582 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1583 | return -EINVAL; |
1584 | } | |
1585 | ||
f07e9af3 | 1586 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1587 | |
1588 | phydev->advertising = phydev->supported; | |
1589 | ||
b02fd9e3 MC |
1590 | return 0; |
1591 | } | |
1592 | ||
1593 | static void tg3_phy_start(struct tg3 *tp) | |
1594 | { | |
1595 | struct phy_device *phydev; | |
1596 | ||
f07e9af3 | 1597 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1598 | return; |
1599 | ||
3f0e3ad7 | 1600 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1601 | |
80096068 MC |
1602 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1603 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
b02fd9e3 MC |
1604 | phydev->speed = tp->link_config.orig_speed; |
1605 | phydev->duplex = tp->link_config.orig_duplex; | |
1606 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1607 | phydev->advertising = tp->link_config.orig_advertising; | |
1608 | } | |
1609 | ||
1610 | phy_start(phydev); | |
1611 | ||
1612 | phy_start_aneg(phydev); | |
1613 | } | |
1614 | ||
1615 | static void tg3_phy_stop(struct tg3 *tp) | |
1616 | { | |
f07e9af3 | 1617 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1618 | return; |
1619 | ||
3f0e3ad7 | 1620 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1621 | } |
1622 | ||
1623 | static void tg3_phy_fini(struct tg3 *tp) | |
1624 | { | |
f07e9af3 | 1625 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1626 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1627 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1628 | } |
1629 | } | |
1630 | ||
7f97a4bd MC |
1631 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1632 | { | |
1633 | u32 phytest; | |
1634 | ||
1635 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1636 | u32 phy; | |
1637 | ||
1638 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1639 | phytest | MII_TG3_FET_SHADOW_EN); | |
1640 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1641 | if (enable) | |
1642 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1643 | else | |
1644 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1645 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1646 | } | |
1647 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1648 | } | |
1649 | } | |
1650 | ||
6833c043 MC |
1651 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1652 | { | |
1653 | u32 reg; | |
1654 | ||
ecf1410b | 1655 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
0a58d668 | 1656 | ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
f07e9af3 | 1657 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1658 | return; |
1659 | ||
f07e9af3 | 1660 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1661 | tg3_phy_fet_toggle_apd(tp, enable); |
1662 | return; | |
1663 | } | |
1664 | ||
6833c043 MC |
1665 | reg = MII_TG3_MISC_SHDW_WREN | |
1666 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1667 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1668 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1669 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1670 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1671 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1672 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1673 | ||
1674 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1675 | ||
1676 | ||
1677 | reg = MII_TG3_MISC_SHDW_WREN | | |
1678 | MII_TG3_MISC_SHDW_APD_SEL | | |
1679 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1680 | if (enable) | |
1681 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1682 | ||
1683 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1684 | } | |
1685 | ||
9ef8ca99 MC |
1686 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1687 | { | |
1688 | u32 phy; | |
1689 | ||
1690 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
f07e9af3 | 1691 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
1692 | return; |
1693 | ||
f07e9af3 | 1694 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
1695 | u32 ephy; |
1696 | ||
535ef6e1 MC |
1697 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1698 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1699 | ||
1700 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1701 | ephy | MII_TG3_FET_SHADOW_EN); | |
1702 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1703 | if (enable) |
535ef6e1 | 1704 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1705 | else |
535ef6e1 MC |
1706 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1707 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1708 | } |
535ef6e1 | 1709 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1710 | } |
1711 | } else { | |
15ee95c3 MC |
1712 | int ret; |
1713 | ||
1714 | ret = tg3_phy_auxctl_read(tp, | |
1715 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); | |
1716 | if (!ret) { | |
9ef8ca99 MC |
1717 | if (enable) |
1718 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1719 | else | |
1720 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
b4bd2929 MC |
1721 | tg3_phy_auxctl_write(tp, |
1722 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); | |
9ef8ca99 MC |
1723 | } |
1724 | } | |
1725 | } | |
1726 | ||
1da177e4 LT |
1727 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1728 | { | |
15ee95c3 | 1729 | int ret; |
1da177e4 LT |
1730 | u32 val; |
1731 | ||
f07e9af3 | 1732 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
1733 | return; |
1734 | ||
15ee95c3 MC |
1735 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
1736 | if (!ret) | |
b4bd2929 MC |
1737 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
1738 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); | |
1da177e4 LT |
1739 | } |
1740 | ||
b2a5c19c MC |
1741 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1742 | { | |
1743 | u32 otp, phy; | |
1744 | ||
1745 | if (!tp->phy_otp) | |
1746 | return; | |
1747 | ||
1748 | otp = tp->phy_otp; | |
1749 | ||
1d36ba45 MC |
1750 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
1751 | return; | |
b2a5c19c MC |
1752 | |
1753 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1754 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1755 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1756 | ||
1757 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1758 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1759 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1760 | ||
1761 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1762 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1763 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1764 | ||
1765 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1766 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1767 | ||
1768 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1769 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1770 | ||
1771 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1772 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1773 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1774 | ||
1d36ba45 | 1775 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
b2a5c19c MC |
1776 | } |
1777 | ||
52b02d04 MC |
1778 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
1779 | { | |
1780 | u32 val; | |
1781 | ||
1782 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
1783 | return; | |
1784 | ||
1785 | tp->setlpicnt = 0; | |
1786 | ||
1787 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
1788 | current_link_up == 1 && | |
a6b68dab MC |
1789 | tp->link_config.active_duplex == DUPLEX_FULL && |
1790 | (tp->link_config.active_speed == SPEED_100 || | |
1791 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
1792 | u32 eeectl; |
1793 | ||
1794 | if (tp->link_config.active_speed == SPEED_1000) | |
1795 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
1796 | else | |
1797 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
1798 | ||
1799 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
1800 | ||
3110f5f5 MC |
1801 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
1802 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 1803 | |
21a00ab2 MC |
1804 | switch (val) { |
1805 | case TG3_CL45_D7_EEERES_STAT_LP_1000T: | |
1806 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { | |
1807 | case ASIC_REV_5717: | |
1808 | case ASIC_REV_5719: | |
1809 | case ASIC_REV_57765: | |
1d36ba45 MC |
1810 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
1811 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, | |
1812 | 0x0000); | |
1813 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
1814 | } | |
21a00ab2 MC |
1815 | } |
1816 | /* Fallthrough */ | |
1817 | case TG3_CL45_D7_EEERES_STAT_LP_100TX: | |
52b02d04 | 1818 | tp->setlpicnt = 2; |
21a00ab2 | 1819 | } |
52b02d04 MC |
1820 | } |
1821 | ||
1822 | if (!tp->setlpicnt) { | |
1823 | val = tr32(TG3_CPMU_EEE_MODE); | |
1824 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
1825 | } | |
1826 | } | |
1827 | ||
1da177e4 LT |
1828 | static int tg3_wait_macro_done(struct tg3 *tp) |
1829 | { | |
1830 | int limit = 100; | |
1831 | ||
1832 | while (limit--) { | |
1833 | u32 tmp32; | |
1834 | ||
f08aa1a8 | 1835 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
1836 | if ((tmp32 & 0x1000) == 0) |
1837 | break; | |
1838 | } | |
1839 | } | |
d4675b52 | 1840 | if (limit < 0) |
1da177e4 LT |
1841 | return -EBUSY; |
1842 | ||
1843 | return 0; | |
1844 | } | |
1845 | ||
1846 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1847 | { | |
1848 | static const u32 test_pat[4][6] = { | |
1849 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1850 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1851 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1852 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1853 | }; | |
1854 | int chan; | |
1855 | ||
1856 | for (chan = 0; chan < 4; chan++) { | |
1857 | int i; | |
1858 | ||
1859 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1860 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1861 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1862 | |
1863 | for (i = 0; i < 6; i++) | |
1864 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1865 | test_pat[chan][i]); | |
1866 | ||
f08aa1a8 | 1867 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1868 | if (tg3_wait_macro_done(tp)) { |
1869 | *resetp = 1; | |
1870 | return -EBUSY; | |
1871 | } | |
1872 | ||
1873 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1874 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1875 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
1876 | if (tg3_wait_macro_done(tp)) { |
1877 | *resetp = 1; | |
1878 | return -EBUSY; | |
1879 | } | |
1880 | ||
f08aa1a8 | 1881 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
1882 | if (tg3_wait_macro_done(tp)) { |
1883 | *resetp = 1; | |
1884 | return -EBUSY; | |
1885 | } | |
1886 | ||
1887 | for (i = 0; i < 6; i += 2) { | |
1888 | u32 low, high; | |
1889 | ||
1890 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1891 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1892 | tg3_wait_macro_done(tp)) { | |
1893 | *resetp = 1; | |
1894 | return -EBUSY; | |
1895 | } | |
1896 | low &= 0x7fff; | |
1897 | high &= 0x000f; | |
1898 | if (low != test_pat[chan][i] || | |
1899 | high != test_pat[chan][i+1]) { | |
1900 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1901 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1902 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1903 | ||
1904 | return -EBUSY; | |
1905 | } | |
1906 | } | |
1907 | } | |
1908 | ||
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1913 | { | |
1914 | int chan; | |
1915 | ||
1916 | for (chan = 0; chan < 4; chan++) { | |
1917 | int i; | |
1918 | ||
1919 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1920 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1921 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1922 | for (i = 0; i < 6; i++) |
1923 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 1924 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1925 | if (tg3_wait_macro_done(tp)) |
1926 | return -EBUSY; | |
1927 | } | |
1928 | ||
1929 | return 0; | |
1930 | } | |
1931 | ||
1932 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1933 | { | |
1934 | u32 reg32, phy9_orig; | |
1935 | int retries, do_phy_reset, err; | |
1936 | ||
1937 | retries = 10; | |
1938 | do_phy_reset = 1; | |
1939 | do { | |
1940 | if (do_phy_reset) { | |
1941 | err = tg3_bmcr_reset(tp); | |
1942 | if (err) | |
1943 | return err; | |
1944 | do_phy_reset = 0; | |
1945 | } | |
1946 | ||
1947 | /* Disable transmitter and interrupt. */ | |
1948 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1949 | continue; | |
1950 | ||
1951 | reg32 |= 0x3000; | |
1952 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1953 | ||
1954 | /* Set full-duplex, 1000 mbps. */ | |
1955 | tg3_writephy(tp, MII_BMCR, | |
1956 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1957 | ||
1958 | /* Set to master mode. */ | |
1959 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1960 | continue; | |
1961 | ||
1962 | tg3_writephy(tp, MII_TG3_CTRL, | |
1963 | (MII_TG3_CTRL_AS_MASTER | | |
1964 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1965 | ||
1d36ba45 MC |
1966 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
1967 | if (err) | |
1968 | return err; | |
1da177e4 LT |
1969 | |
1970 | /* Block the PHY control access. */ | |
6ee7c0a0 | 1971 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
1972 | |
1973 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
1974 | if (!err) | |
1975 | break; | |
1976 | } while (--retries); | |
1977 | ||
1978 | err = tg3_phy_reset_chanpat(tp); | |
1979 | if (err) | |
1980 | return err; | |
1981 | ||
6ee7c0a0 | 1982 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
1983 | |
1984 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 1985 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 | 1986 | |
1d36ba45 | 1987 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 LT |
1988 | |
1989 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
1990 | ||
1991 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
1992 | reg32 &= ~0x3000; | |
1993 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1994 | } else if (!err) | |
1995 | err = -EBUSY; | |
1996 | ||
1997 | return err; | |
1998 | } | |
1999 | ||
2000 | /* This will reset the tigon3 PHY if there is no valid | |
2001 | * link unless the FORCE argument is non-zero. | |
2002 | */ | |
2003 | static int tg3_phy_reset(struct tg3 *tp) | |
2004 | { | |
f833c4c1 | 2005 | u32 val, cpmuctrl; |
1da177e4 LT |
2006 | int err; |
2007 | ||
60189ddf | 2008 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2009 | val = tr32(GRC_MISC_CFG); |
2010 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
2011 | udelay(40); | |
2012 | } | |
f833c4c1 MC |
2013 | err = tg3_readphy(tp, MII_BMSR, &val); |
2014 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2015 | if (err != 0) |
2016 | return -EBUSY; | |
2017 | ||
c8e1e82b MC |
2018 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
2019 | netif_carrier_off(tp->dev); | |
2020 | tg3_link_report(tp); | |
2021 | } | |
2022 | ||
1da177e4 LT |
2023 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2024 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2025 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2026 | err = tg3_phy_reset_5703_4_5(tp); | |
2027 | if (err) | |
2028 | return err; | |
2029 | goto out; | |
2030 | } | |
2031 | ||
b2a5c19c MC |
2032 | cpmuctrl = 0; |
2033 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2034 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2035 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2036 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2037 | tw32(TG3_CPMU_CTRL, | |
2038 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2039 | } | |
2040 | ||
1da177e4 LT |
2041 | err = tg3_bmcr_reset(tp); |
2042 | if (err) | |
2043 | return err; | |
2044 | ||
b2a5c19c | 2045 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2046 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2047 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2048 | |
2049 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2050 | } | |
2051 | ||
bcb37f6c MC |
2052 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2053 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2054 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2055 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2056 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2057 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2058 | udelay(40); | |
2059 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2060 | } | |
2061 | } | |
2062 | ||
0a58d668 | 2063 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
f07e9af3 | 2064 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2065 | return 0; |
2066 | ||
b2a5c19c MC |
2067 | tg3_phy_apply_otp(tp); |
2068 | ||
f07e9af3 | 2069 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2070 | tg3_phy_toggle_apd(tp, true); |
2071 | else | |
2072 | tg3_phy_toggle_apd(tp, false); | |
2073 | ||
1da177e4 | 2074 | out: |
1d36ba45 MC |
2075 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
2076 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | |
6ee7c0a0 MC |
2077 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2078 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1d36ba45 | 2079 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1da177e4 | 2080 | } |
1d36ba45 | 2081 | |
f07e9af3 | 2082 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2083 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2084 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2085 | } |
1d36ba45 | 2086 | |
f07e9af3 | 2087 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1d36ba45 MC |
2088 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2089 | tg3_phydsp_write(tp, 0x000a, 0x310b); | |
2090 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2091 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
2092 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2093 | } | |
f07e9af3 | 2094 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
1d36ba45 MC |
2095 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
2096 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
2097 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { | |
2098 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2099 | tg3_writephy(tp, MII_TG3_TEST1, | |
2100 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2101 | } else | |
2102 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
2103 | ||
2104 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | |
2105 | } | |
c424cb24 | 2106 | } |
1d36ba45 | 2107 | |
1da177e4 LT |
2108 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2109 | /* support jumbo frames */ | |
79eb6904 | 2110 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 | 2111 | /* Cannot do read-modify-write on 5401 */ |
b4bd2929 | 2112 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
8f666b07 | 2113 | } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 | 2114 | /* Set bit 14 with read-modify-write to preserve other bits */ |
15ee95c3 MC |
2115 | err = tg3_phy_auxctl_read(tp, |
2116 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); | |
2117 | if (!err) | |
b4bd2929 MC |
2118 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
2119 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); | |
1da177e4 LT |
2120 | } |
2121 | ||
2122 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2123 | * jumbo frames transmission. | |
2124 | */ | |
8f666b07 | 2125 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
f833c4c1 | 2126 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2127 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2128 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2129 | } |
2130 | ||
715116a1 | 2131 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2132 | /* adjust output voltage */ |
535ef6e1 | 2133 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2134 | } |
2135 | ||
9ef8ca99 | 2136 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2137 | tg3_phy_set_wirespeed(tp); |
2138 | return 0; | |
2139 | } | |
2140 | ||
2141 | static void tg3_frob_aux_power(struct tg3 *tp) | |
2142 | { | |
683644b7 | 2143 | bool need_vaux = false; |
1da177e4 | 2144 | |
334355aa MC |
2145 | /* The GPIOs do something completely different on 57765. */ |
2146 | if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 || | |
a50d0796 | 2147 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
334355aa | 2148 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
1da177e4 LT |
2149 | return; |
2150 | ||
683644b7 MC |
2151 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
2152 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
d78b59f5 MC |
2153 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2154 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) && | |
683644b7 | 2155 | tp->pdev_peer != tp->pdev) { |
8c2dc7e1 MC |
2156 | struct net_device *dev_peer; |
2157 | ||
2158 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2159 | |
bc1c7567 | 2160 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2161 | if (dev_peer) { |
2162 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2163 | ||
2164 | if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) | |
2165 | return; | |
2166 | ||
2167 | if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) || | |
2168 | (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
2169 | need_vaux = true; | |
2170 | } | |
1da177e4 LT |
2171 | } |
2172 | ||
683644b7 MC |
2173 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) || |
2174 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
2175 | need_vaux = true; | |
2176 | ||
2177 | if (need_vaux) { | |
1da177e4 LT |
2178 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2179 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
b401e9e2 MC |
2180 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2181 | (GRC_LCLCTRL_GPIO_OE0 | | |
2182 | GRC_LCLCTRL_GPIO_OE1 | | |
2183 | GRC_LCLCTRL_GPIO_OE2 | | |
2184 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2185 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2186 | 100); | |
8d519ab2 MC |
2187 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
2188 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
2189 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ |
2190 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2191 | GRC_LCLCTRL_GPIO_OE1 | | |
2192 | GRC_LCLCTRL_GPIO_OE2 | | |
2193 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2194 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2195 | tp->grc_local_ctrl; | |
2196 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2197 | ||
2198 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2199 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2200 | ||
2201 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2202 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1da177e4 LT |
2203 | } else { |
2204 | u32 no_gpio2; | |
dc56b7d4 | 2205 | u32 grc_local_ctrl = 0; |
1da177e4 | 2206 | |
dc56b7d4 MC |
2207 | /* Workaround to prevent overdrawing Amps. */ |
2208 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2209 | ASIC_REV_5714) { | |
2210 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
b401e9e2 MC |
2211 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2212 | grc_local_ctrl, 100); | |
dc56b7d4 MC |
2213 | } |
2214 | ||
1da177e4 LT |
2215 | /* On 5753 and variants, GPIO2 cannot be used. */ |
2216 | no_gpio2 = tp->nic_sram_data_cfg & | |
2217 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2218 | ||
dc56b7d4 | 2219 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | |
1da177e4 LT |
2220 | GRC_LCLCTRL_GPIO_OE1 | |
2221 | GRC_LCLCTRL_GPIO_OE2 | | |
2222 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2223 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2224 | if (no_gpio2) { | |
2225 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2226 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2227 | } | |
b401e9e2 MC |
2228 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2229 | grc_local_ctrl, 100); | |
1da177e4 LT |
2230 | |
2231 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2232 | ||
b401e9e2 MC |
2233 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2234 | grc_local_ctrl, 100); | |
1da177e4 LT |
2235 | |
2236 | if (!no_gpio2) { | |
2237 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
b401e9e2 MC |
2238 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2239 | grc_local_ctrl, 100); | |
1da177e4 LT |
2240 | } |
2241 | } | |
2242 | } else { | |
2243 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2244 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
b401e9e2 MC |
2245 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2246 | (GRC_LCLCTRL_GPIO_OE1 | | |
2247 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 | 2248 | |
b401e9e2 MC |
2249 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2250 | GRC_LCLCTRL_GPIO_OE1, 100); | |
1da177e4 | 2251 | |
b401e9e2 MC |
2252 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2253 | (GRC_LCLCTRL_GPIO_OE1 | | |
2254 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 LT |
2255 | } |
2256 | } | |
2257 | } | |
2258 | ||
e8f3f6ca MC |
2259 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2260 | { | |
2261 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2262 | return 1; | |
79eb6904 | 2263 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2264 | if (speed != SPEED_10) |
2265 | return 1; | |
2266 | } else if (speed == SPEED_10) | |
2267 | return 1; | |
2268 | ||
2269 | return 0; | |
2270 | } | |
2271 | ||
1da177e4 LT |
2272 | static int tg3_setup_phy(struct tg3 *, int); |
2273 | ||
2274 | #define RESET_KIND_SHUTDOWN 0 | |
2275 | #define RESET_KIND_INIT 1 | |
2276 | #define RESET_KIND_SUSPEND 2 | |
2277 | ||
2278 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2279 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2280 | ||
0a459aac | 2281 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2282 | { |
ce057f01 MC |
2283 | u32 val; |
2284 | ||
f07e9af3 | 2285 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2286 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2287 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2288 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2289 | ||
2290 | sg_dig_ctrl |= | |
2291 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2292 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2293 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2294 | } | |
3f7045c1 | 2295 | return; |
5129724a | 2296 | } |
3f7045c1 | 2297 | |
60189ddf | 2298 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2299 | tg3_bmcr_reset(tp); |
2300 | val = tr32(GRC_MISC_CFG); | |
2301 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2302 | udelay(40); | |
2303 | return; | |
f07e9af3 | 2304 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2305 | u32 phytest; |
2306 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2307 | u32 phy; | |
2308 | ||
2309 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2310 | tg3_writephy(tp, MII_BMCR, | |
2311 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2312 | ||
2313 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2314 | phytest | MII_TG3_FET_SHADOW_EN); | |
2315 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2316 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2317 | tg3_writephy(tp, | |
2318 | MII_TG3_FET_SHDW_AUXMODE4, | |
2319 | phy); | |
2320 | } | |
2321 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2322 | } | |
2323 | return; | |
0a459aac | 2324 | } else if (do_low_power) { |
715116a1 MC |
2325 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2326 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac | 2327 | |
b4bd2929 MC |
2328 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
2329 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2330 | MII_TG3_AUXCTL_PCTL_VREG_11V; | |
2331 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); | |
715116a1 | 2332 | } |
3f7045c1 | 2333 | |
15c3b696 MC |
2334 | /* The PHY should not be powered down on some chips because |
2335 | * of bugs. | |
2336 | */ | |
2337 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2338 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2339 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
f07e9af3 | 2340 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
15c3b696 | 2341 | return; |
ce057f01 | 2342 | |
bcb37f6c MC |
2343 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2344 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2345 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2346 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2347 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2348 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2349 | } | |
2350 | ||
15c3b696 MC |
2351 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2352 | } | |
2353 | ||
ffbcfed4 MC |
2354 | /* tp->lock is held. */ |
2355 | static int tg3_nvram_lock(struct tg3 *tp) | |
2356 | { | |
2357 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2358 | int i; | |
2359 | ||
2360 | if (tp->nvram_lock_cnt == 0) { | |
2361 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2362 | for (i = 0; i < 8000; i++) { | |
2363 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2364 | break; | |
2365 | udelay(20); | |
2366 | } | |
2367 | if (i == 8000) { | |
2368 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2369 | return -ENODEV; | |
2370 | } | |
2371 | } | |
2372 | tp->nvram_lock_cnt++; | |
2373 | } | |
2374 | return 0; | |
2375 | } | |
2376 | ||
2377 | /* tp->lock is held. */ | |
2378 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2379 | { | |
2380 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2381 | if (tp->nvram_lock_cnt > 0) | |
2382 | tp->nvram_lock_cnt--; | |
2383 | if (tp->nvram_lock_cnt == 0) | |
2384 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2385 | } | |
2386 | } | |
2387 | ||
2388 | /* tp->lock is held. */ | |
2389 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2390 | { | |
2391 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2392 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2393 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2394 | ||
2395 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2396 | } | |
2397 | } | |
2398 | ||
2399 | /* tp->lock is held. */ | |
2400 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2401 | { | |
2402 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2403 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2404 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2405 | ||
2406 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2407 | } | |
2408 | } | |
2409 | ||
2410 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2411 | u32 offset, u32 *val) | |
2412 | { | |
2413 | u32 tmp; | |
2414 | int i; | |
2415 | ||
2416 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2417 | return -EINVAL; | |
2418 | ||
2419 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2420 | EEPROM_ADDR_DEVID_MASK | | |
2421 | EEPROM_ADDR_READ); | |
2422 | tw32(GRC_EEPROM_ADDR, | |
2423 | tmp | | |
2424 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2425 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2426 | EEPROM_ADDR_ADDR_MASK) | | |
2427 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2428 | ||
2429 | for (i = 0; i < 1000; i++) { | |
2430 | tmp = tr32(GRC_EEPROM_ADDR); | |
2431 | ||
2432 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2433 | break; | |
2434 | msleep(1); | |
2435 | } | |
2436 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2437 | return -EBUSY; | |
2438 | ||
62cedd11 MC |
2439 | tmp = tr32(GRC_EEPROM_DATA); |
2440 | ||
2441 | /* | |
2442 | * The data will always be opposite the native endian | |
2443 | * format. Perform a blind byteswap to compensate. | |
2444 | */ | |
2445 | *val = swab32(tmp); | |
2446 | ||
ffbcfed4 MC |
2447 | return 0; |
2448 | } | |
2449 | ||
2450 | #define NVRAM_CMD_TIMEOUT 10000 | |
2451 | ||
2452 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2453 | { | |
2454 | int i; | |
2455 | ||
2456 | tw32(NVRAM_CMD, nvram_cmd); | |
2457 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2458 | udelay(10); | |
2459 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2460 | udelay(10); | |
2461 | break; | |
2462 | } | |
2463 | } | |
2464 | ||
2465 | if (i == NVRAM_CMD_TIMEOUT) | |
2466 | return -EBUSY; | |
2467 | ||
2468 | return 0; | |
2469 | } | |
2470 | ||
2471 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2472 | { | |
2473 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2474 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2475 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2476 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2477 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2478 | ||
2479 | addr = ((addr / tp->nvram_pagesize) << | |
2480 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2481 | (addr % tp->nvram_pagesize); | |
2482 | ||
2483 | return addr; | |
2484 | } | |
2485 | ||
2486 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2487 | { | |
2488 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2489 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2490 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2491 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2492 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2493 | ||
2494 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2495 | tp->nvram_pagesize) + | |
2496 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2497 | ||
2498 | return addr; | |
2499 | } | |
2500 | ||
e4f34110 MC |
2501 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2502 | * the byteswapping settings for all other register accesses. | |
2503 | * tg3 devices are BE devices, so on a BE machine, the data | |
2504 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2505 | * machine, the 32-bit value will be byteswapped. | |
2506 | */ | |
ffbcfed4 MC |
2507 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2508 | { | |
2509 | int ret; | |
2510 | ||
2511 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | |
2512 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
2513 | ||
2514 | offset = tg3_nvram_phys_addr(tp, offset); | |
2515 | ||
2516 | if (offset > NVRAM_ADDR_MSK) | |
2517 | return -EINVAL; | |
2518 | ||
2519 | ret = tg3_nvram_lock(tp); | |
2520 | if (ret) | |
2521 | return ret; | |
2522 | ||
2523 | tg3_enable_nvram_access(tp); | |
2524 | ||
2525 | tw32(NVRAM_ADDR, offset); | |
2526 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2527 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2528 | ||
2529 | if (ret == 0) | |
e4f34110 | 2530 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2531 | |
2532 | tg3_disable_nvram_access(tp); | |
2533 | ||
2534 | tg3_nvram_unlock(tp); | |
2535 | ||
2536 | return ret; | |
2537 | } | |
2538 | ||
a9dc529d MC |
2539 | /* Ensures NVRAM data is in bytestream format. */ |
2540 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2541 | { |
2542 | u32 v; | |
a9dc529d | 2543 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2544 | if (!res) |
a9dc529d | 2545 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2546 | return res; |
2547 | } | |
2548 | ||
3f007891 MC |
2549 | /* tp->lock is held. */ |
2550 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2551 | { | |
2552 | u32 addr_high, addr_low; | |
2553 | int i; | |
2554 | ||
2555 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2556 | tp->dev->dev_addr[1]); | |
2557 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2558 | (tp->dev->dev_addr[3] << 16) | | |
2559 | (tp->dev->dev_addr[4] << 8) | | |
2560 | (tp->dev->dev_addr[5] << 0)); | |
2561 | for (i = 0; i < 4; i++) { | |
2562 | if (i == 1 && skip_mac_1) | |
2563 | continue; | |
2564 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2565 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2566 | } | |
2567 | ||
2568 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2569 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2570 | for (i = 0; i < 12; i++) { | |
2571 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2572 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2573 | } | |
2574 | } | |
2575 | ||
2576 | addr_high = (tp->dev->dev_addr[0] + | |
2577 | tp->dev->dev_addr[1] + | |
2578 | tp->dev->dev_addr[2] + | |
2579 | tp->dev->dev_addr[3] + | |
2580 | tp->dev->dev_addr[4] + | |
2581 | tp->dev->dev_addr[5]) & | |
2582 | TX_BACKOFF_SEED_MASK; | |
2583 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2584 | } | |
2585 | ||
c866b7ea | 2586 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 2587 | { |
c866b7ea RW |
2588 | /* |
2589 | * Make sure register accesses (indirect or otherwise) will function | |
2590 | * correctly. | |
1da177e4 LT |
2591 | */ |
2592 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
2593 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
2594 | } | |
1da177e4 | 2595 | |
c866b7ea RW |
2596 | static int tg3_power_up(struct tg3 *tp) |
2597 | { | |
2598 | tg3_enable_register_access(tp); | |
8c6bda1a | 2599 | |
c866b7ea | 2600 | pci_set_power_state(tp->pdev, PCI_D0); |
1da177e4 | 2601 | |
c866b7ea RW |
2602 | /* Switch out of Vaux if it is a NIC */ |
2603 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
2604 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); | |
1da177e4 | 2605 | |
c866b7ea RW |
2606 | return 0; |
2607 | } | |
1da177e4 | 2608 | |
c866b7ea RW |
2609 | static int tg3_power_down_prepare(struct tg3 *tp) |
2610 | { | |
2611 | u32 misc_host_ctrl; | |
2612 | bool device_should_wake, do_low_power; | |
2613 | ||
2614 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
2615 | |
2616 | /* Restore the CLKREQ setting. */ | |
2617 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2618 | u16 lnkctl; | |
2619 | ||
2620 | pci_read_config_word(tp->pdev, | |
2621 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2622 | &lnkctl); | |
2623 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2624 | pci_write_config_word(tp->pdev, | |
2625 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2626 | lnkctl); | |
2627 | } | |
2628 | ||
1da177e4 LT |
2629 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2630 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2631 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2632 | ||
c866b7ea | 2633 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
05ac4cb7 MC |
2634 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
2635 | ||
dd477003 | 2636 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
0a459aac | 2637 | do_low_power = false; |
f07e9af3 | 2638 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 2639 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 2640 | struct phy_device *phydev; |
0a459aac | 2641 | u32 phyid, advertising; |
b02fd9e3 | 2642 | |
3f0e3ad7 | 2643 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 2644 | |
80096068 | 2645 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 MC |
2646 | |
2647 | tp->link_config.orig_speed = phydev->speed; | |
2648 | tp->link_config.orig_duplex = phydev->duplex; | |
2649 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2650 | tp->link_config.orig_advertising = phydev->advertising; | |
2651 | ||
2652 | advertising = ADVERTISED_TP | | |
2653 | ADVERTISED_Pause | | |
2654 | ADVERTISED_Autoneg | | |
2655 | ADVERTISED_10baseT_Half; | |
2656 | ||
2657 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
05ac4cb7 | 2658 | device_should_wake) { |
b02fd9e3 MC |
2659 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) |
2660 | advertising |= | |
2661 | ADVERTISED_100baseT_Half | | |
2662 | ADVERTISED_100baseT_Full | | |
2663 | ADVERTISED_10baseT_Full; | |
2664 | else | |
2665 | advertising |= ADVERTISED_10baseT_Full; | |
2666 | } | |
2667 | ||
2668 | phydev->advertising = advertising; | |
2669 | ||
2670 | phy_start_aneg(phydev); | |
0a459aac MC |
2671 | |
2672 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
2673 | if (phyid != PHY_ID_BCMAC131) { |
2674 | phyid &= PHY_BCM_OUI_MASK; | |
2675 | if (phyid == PHY_BCM_OUI_1 || | |
2676 | phyid == PHY_BCM_OUI_2 || | |
2677 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
2678 | do_low_power = true; |
2679 | } | |
b02fd9e3 | 2680 | } |
dd477003 | 2681 | } else { |
2023276e | 2682 | do_low_power = true; |
0a459aac | 2683 | |
80096068 MC |
2684 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
2685 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
2686 | tp->link_config.orig_speed = tp->link_config.speed; |
2687 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2688 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2689 | } | |
1da177e4 | 2690 | |
f07e9af3 | 2691 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
dd477003 MC |
2692 | tp->link_config.speed = SPEED_10; |
2693 | tp->link_config.duplex = DUPLEX_HALF; | |
2694 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2695 | tg3_setup_phy(tp, 0); | |
2696 | } | |
1da177e4 LT |
2697 | } |
2698 | ||
b5d3772c MC |
2699 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2700 | u32 val; | |
2701 | ||
2702 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2703 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2704 | } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
6921d201 MC |
2705 | int i; |
2706 | u32 val; | |
2707 | ||
2708 | for (i = 0; i < 200; i++) { | |
2709 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2710 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2711 | break; | |
2712 | msleep(1); | |
2713 | } | |
2714 | } | |
a85feb8c GZ |
2715 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
2716 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2717 | WOL_DRV_STATE_SHUTDOWN | | |
2718 | WOL_DRV_WOL | | |
2719 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2720 | |
05ac4cb7 | 2721 | if (device_should_wake) { |
1da177e4 LT |
2722 | u32 mac_mode; |
2723 | ||
f07e9af3 | 2724 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
b4bd2929 MC |
2725 | if (do_low_power && |
2726 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
2727 | tg3_phy_auxctl_write(tp, | |
2728 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, | |
2729 | MII_TG3_AUXCTL_PCTL_WOL_EN | | |
2730 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2731 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); | |
dd477003 MC |
2732 | udelay(40); |
2733 | } | |
1da177e4 | 2734 | |
f07e9af3 | 2735 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
2736 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
2737 | else | |
2738 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2739 | |
e8f3f6ca MC |
2740 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2741 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2742 | ASIC_REV_5700) { | |
2743 | u32 speed = (tp->tg3_flags & | |
2744 | TG3_FLAG_WOL_SPEED_100MB) ? | |
2745 | SPEED_100 : SPEED_10; | |
2746 | if (tg3_5700_link_polarity(tp, speed)) | |
2747 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2748 | else | |
2749 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2750 | } | |
1da177e4 LT |
2751 | } else { |
2752 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2753 | } | |
2754 | ||
cbf46853 | 2755 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) |
1da177e4 LT |
2756 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2757 | ||
05ac4cb7 MC |
2758 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
2759 | if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
2760 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && | |
2761 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2762 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))) | |
2763 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
1da177e4 | 2764 | |
d2394e6b MC |
2765 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
2766 | mac_mode |= MAC_MODE_APE_TX_EN | | |
2767 | MAC_MODE_APE_RX_EN | | |
2768 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 2769 | |
1da177e4 LT |
2770 | tw32_f(MAC_MODE, mac_mode); |
2771 | udelay(100); | |
2772 | ||
2773 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2774 | udelay(10); | |
2775 | } | |
2776 | ||
2777 | if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && | |
2778 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2779 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2780 | u32 base_val; | |
2781 | ||
2782 | base_val = tp->pci_clock_ctrl; | |
2783 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2784 | CLOCK_CTRL_TXCLK_DISABLE); | |
2785 | ||
b401e9e2 MC |
2786 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2787 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
d7b0a857 | 2788 | } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
795d01c5 | 2789 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
d7b0a857 | 2790 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { |
4cf78e4f | 2791 | /* do nothing */ |
85e94ced | 2792 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
1da177e4 LT |
2793 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { |
2794 | u32 newbits1, newbits2; | |
2795 | ||
2796 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2797 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2798 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2799 | CLOCK_CTRL_TXCLK_DISABLE | | |
2800 | CLOCK_CTRL_ALTCLK); | |
2801 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2802 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
2803 | newbits1 = CLOCK_CTRL_625_CORE; | |
2804 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2805 | } else { | |
2806 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2807 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2808 | } | |
2809 | ||
b401e9e2 MC |
2810 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2811 | 40); | |
1da177e4 | 2812 | |
b401e9e2 MC |
2813 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2814 | 40); | |
1da177e4 LT |
2815 | |
2816 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
2817 | u32 newbits3; | |
2818 | ||
2819 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2820 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2821 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2822 | CLOCK_CTRL_TXCLK_DISABLE | | |
2823 | CLOCK_CTRL_44MHZ_CORE); | |
2824 | } else { | |
2825 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2826 | } | |
2827 | ||
b401e9e2 MC |
2828 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
2829 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
2830 | } |
2831 | } | |
2832 | ||
05ac4cb7 | 2833 | if (!(device_should_wake) && |
22435849 | 2834 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
0a459aac | 2835 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 2836 | |
1da177e4 LT |
2837 | tg3_frob_aux_power(tp); |
2838 | ||
2839 | /* Workaround for unstable PLL clock */ | |
2840 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2841 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2842 | u32 val = tr32(0x7d00); | |
2843 | ||
2844 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2845 | tw32(0x7d00, val); | |
6921d201 | 2846 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
ec41c7df MC |
2847 | int err; |
2848 | ||
2849 | err = tg3_nvram_lock(tp); | |
1da177e4 | 2850 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
2851 | if (!err) |
2852 | tg3_nvram_unlock(tp); | |
6921d201 | 2853 | } |
1da177e4 LT |
2854 | } |
2855 | ||
bbadf503 MC |
2856 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
2857 | ||
c866b7ea RW |
2858 | return 0; |
2859 | } | |
12dac075 | 2860 | |
c866b7ea RW |
2861 | static void tg3_power_down(struct tg3 *tp) |
2862 | { | |
2863 | tg3_power_down_prepare(tp); | |
1da177e4 | 2864 | |
c866b7ea RW |
2865 | pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
2866 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
1da177e4 LT |
2867 | } |
2868 | ||
1da177e4 LT |
2869 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
2870 | { | |
2871 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2872 | case MII_TG3_AUX_STAT_10HALF: | |
2873 | *speed = SPEED_10; | |
2874 | *duplex = DUPLEX_HALF; | |
2875 | break; | |
2876 | ||
2877 | case MII_TG3_AUX_STAT_10FULL: | |
2878 | *speed = SPEED_10; | |
2879 | *duplex = DUPLEX_FULL; | |
2880 | break; | |
2881 | ||
2882 | case MII_TG3_AUX_STAT_100HALF: | |
2883 | *speed = SPEED_100; | |
2884 | *duplex = DUPLEX_HALF; | |
2885 | break; | |
2886 | ||
2887 | case MII_TG3_AUX_STAT_100FULL: | |
2888 | *speed = SPEED_100; | |
2889 | *duplex = DUPLEX_FULL; | |
2890 | break; | |
2891 | ||
2892 | case MII_TG3_AUX_STAT_1000HALF: | |
2893 | *speed = SPEED_1000; | |
2894 | *duplex = DUPLEX_HALF; | |
2895 | break; | |
2896 | ||
2897 | case MII_TG3_AUX_STAT_1000FULL: | |
2898 | *speed = SPEED_1000; | |
2899 | *duplex = DUPLEX_FULL; | |
2900 | break; | |
2901 | ||
2902 | default: | |
f07e9af3 | 2903 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
2904 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
2905 | SPEED_10; | |
2906 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2907 | DUPLEX_HALF; | |
2908 | break; | |
2909 | } | |
1da177e4 LT |
2910 | *speed = SPEED_INVALID; |
2911 | *duplex = DUPLEX_INVALID; | |
2912 | break; | |
855e1111 | 2913 | } |
1da177e4 LT |
2914 | } |
2915 | ||
2916 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
2917 | { | |
2918 | u32 new_adv; | |
2919 | int i; | |
2920 | ||
80096068 | 2921 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1da177e4 LT |
2922 | /* Entering low power mode. Disable gigabit and |
2923 | * 100baseT advertisements. | |
2924 | */ | |
2925 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2926 | ||
2927 | new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2928 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
2929 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2930 | new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); | |
2931 | ||
2932 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2933 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
f07e9af3 | 2934 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
1da177e4 LT |
2935 | tp->link_config.advertising &= |
2936 | ~(ADVERTISED_1000baseT_Half | | |
2937 | ADVERTISED_1000baseT_Full); | |
2938 | ||
ba4d07a8 | 2939 | new_adv = ADVERTISE_CSMA; |
1da177e4 LT |
2940 | if (tp->link_config.advertising & ADVERTISED_10baseT_Half) |
2941 | new_adv |= ADVERTISE_10HALF; | |
2942 | if (tp->link_config.advertising & ADVERTISED_10baseT_Full) | |
2943 | new_adv |= ADVERTISE_10FULL; | |
2944 | if (tp->link_config.advertising & ADVERTISED_100baseT_Half) | |
2945 | new_adv |= ADVERTISE_100HALF; | |
2946 | if (tp->link_config.advertising & ADVERTISED_100baseT_Full) | |
2947 | new_adv |= ADVERTISE_100FULL; | |
ba4d07a8 MC |
2948 | |
2949 | new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2950 | ||
1da177e4 LT |
2951 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2952 | ||
2953 | if (tp->link_config.advertising & | |
2954 | (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { | |
2955 | new_adv = 0; | |
2956 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
2957 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2958 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
2959 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
f07e9af3 | 2960 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) && |
1da177e4 LT |
2961 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
2962 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) | |
2963 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2964 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2965 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2966 | } else { | |
2967 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2968 | } | |
2969 | } else { | |
ba4d07a8 MC |
2970 | new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); |
2971 | new_adv |= ADVERTISE_CSMA; | |
2972 | ||
1da177e4 LT |
2973 | /* Asking for a specific link mode. */ |
2974 | if (tp->link_config.speed == SPEED_1000) { | |
1da177e4 LT |
2975 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2976 | ||
2977 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2978 | new_adv = MII_TG3_CTRL_ADV_1000_FULL; | |
2979 | else | |
2980 | new_adv = MII_TG3_CTRL_ADV_1000_HALF; | |
2981 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2982 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2983 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2984 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
1da177e4 | 2985 | } else { |
1da177e4 LT |
2986 | if (tp->link_config.speed == SPEED_100) { |
2987 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2988 | new_adv |= ADVERTISE_100FULL; | |
2989 | else | |
2990 | new_adv |= ADVERTISE_100HALF; | |
2991 | } else { | |
2992 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2993 | new_adv |= ADVERTISE_10FULL; | |
2994 | else | |
2995 | new_adv |= ADVERTISE_10HALF; | |
2996 | } | |
2997 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
ba4d07a8 MC |
2998 | |
2999 | new_adv = 0; | |
1da177e4 | 3000 | } |
ba4d07a8 MC |
3001 | |
3002 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
1da177e4 LT |
3003 | } |
3004 | ||
52b02d04 | 3005 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { |
a6b68dab | 3006 | u32 val; |
52b02d04 MC |
3007 | |
3008 | tw32(TG3_CPMU_EEE_MODE, | |
3009 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
3010 | ||
1d36ba45 | 3011 | TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
52b02d04 | 3012 | |
21a00ab2 MC |
3013 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
3014 | case ASIC_REV_5717: | |
3015 | case ASIC_REV_57765: | |
3016 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
3017 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
3018 | MII_TG3_DSP_CH34TP2_HIBW01); | |
3019 | /* Fall through */ | |
3020 | case ASIC_REV_5719: | |
3021 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
3022 | MII_TG3_DSP_TAP26_RMRXSTO | | |
3023 | MII_TG3_DSP_TAP26_OPCSINPT; | |
3024 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
3025 | } | |
52b02d04 | 3026 | |
a6b68dab | 3027 | val = 0; |
52b02d04 MC |
3028 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { |
3029 | /* Advertise 100-BaseTX EEE ability */ | |
3030 | if (tp->link_config.advertising & | |
3110f5f5 MC |
3031 | ADVERTISED_100baseT_Full) |
3032 | val |= MDIO_AN_EEE_ADV_100TX; | |
52b02d04 MC |
3033 | /* Advertise 1000-BaseT EEE ability */ |
3034 | if (tp->link_config.advertising & | |
3110f5f5 MC |
3035 | ADVERTISED_1000baseT_Full) |
3036 | val |= MDIO_AN_EEE_ADV_1000T; | |
52b02d04 | 3037 | } |
3110f5f5 | 3038 | tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); |
52b02d04 | 3039 | |
1d36ba45 | 3040 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
52b02d04 MC |
3041 | } |
3042 | ||
1da177e4 LT |
3043 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
3044 | tp->link_config.speed != SPEED_INVALID) { | |
3045 | u32 bmcr, orig_bmcr; | |
3046 | ||
3047 | tp->link_config.active_speed = tp->link_config.speed; | |
3048 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3049 | ||
3050 | bmcr = 0; | |
3051 | switch (tp->link_config.speed) { | |
3052 | default: | |
3053 | case SPEED_10: | |
3054 | break; | |
3055 | ||
3056 | case SPEED_100: | |
3057 | bmcr |= BMCR_SPEED100; | |
3058 | break; | |
3059 | ||
3060 | case SPEED_1000: | |
3061 | bmcr |= TG3_BMCR_SPEED1000; | |
3062 | break; | |
855e1111 | 3063 | } |
1da177e4 LT |
3064 | |
3065 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3066 | bmcr |= BMCR_FULLDPLX; | |
3067 | ||
3068 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3069 | (bmcr != orig_bmcr)) { | |
3070 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3071 | for (i = 0; i < 1500; i++) { | |
3072 | u32 tmp; | |
3073 | ||
3074 | udelay(10); | |
3075 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3076 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3077 | continue; | |
3078 | if (!(tmp & BMSR_LSTATUS)) { | |
3079 | udelay(40); | |
3080 | break; | |
3081 | } | |
3082 | } | |
3083 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3084 | udelay(40); | |
3085 | } | |
3086 | } else { | |
3087 | tg3_writephy(tp, MII_BMCR, | |
3088 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3089 | } | |
3090 | } | |
3091 | ||
3092 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3093 | { | |
3094 | int err; | |
3095 | ||
3096 | /* Turn off tap power management. */ | |
3097 | /* Set Extended packet length bit */ | |
b4bd2929 | 3098 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
1da177e4 | 3099 | |
6ee7c0a0 MC |
3100 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3101 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3102 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3103 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3104 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3105 | |
3106 | udelay(40); | |
3107 | ||
3108 | return err; | |
3109 | } | |
3110 | ||
3600d918 | 3111 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 3112 | { |
3600d918 MC |
3113 | u32 adv_reg, all_mask = 0; |
3114 | ||
3115 | if (mask & ADVERTISED_10baseT_Half) | |
3116 | all_mask |= ADVERTISE_10HALF; | |
3117 | if (mask & ADVERTISED_10baseT_Full) | |
3118 | all_mask |= ADVERTISE_10FULL; | |
3119 | if (mask & ADVERTISED_100baseT_Half) | |
3120 | all_mask |= ADVERTISE_100HALF; | |
3121 | if (mask & ADVERTISED_100baseT_Full) | |
3122 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
3123 | |
3124 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
3125 | return 0; | |
3126 | ||
1da177e4 LT |
3127 | if ((adv_reg & all_mask) != all_mask) |
3128 | return 0; | |
f07e9af3 | 3129 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
3130 | u32 tg3_ctrl; |
3131 | ||
3600d918 MC |
3132 | all_mask = 0; |
3133 | if (mask & ADVERTISED_1000baseT_Half) | |
3134 | all_mask |= ADVERTISE_1000HALF; | |
3135 | if (mask & ADVERTISED_1000baseT_Full) | |
3136 | all_mask |= ADVERTISE_1000FULL; | |
3137 | ||
1da177e4 LT |
3138 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) |
3139 | return 0; | |
3140 | ||
1da177e4 LT |
3141 | if ((tg3_ctrl & all_mask) != all_mask) |
3142 | return 0; | |
3143 | } | |
3144 | return 1; | |
3145 | } | |
3146 | ||
ef167e27 MC |
3147 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
3148 | { | |
3149 | u32 curadv, reqadv; | |
3150 | ||
3151 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3152 | return 1; | |
3153 | ||
3154 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3155 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3156 | ||
3157 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3158 | if (curadv != reqadv) | |
3159 | return 0; | |
3160 | ||
3161 | if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) | |
3162 | tg3_readphy(tp, MII_LPA, rmtadv); | |
3163 | } else { | |
3164 | /* Reprogram the advertisement register, even if it | |
3165 | * does not affect the current link. If the link | |
3166 | * gets renegotiated in the future, we can save an | |
3167 | * additional renegotiation cycle by advertising | |
3168 | * it correctly in the first place. | |
3169 | */ | |
3170 | if (curadv != reqadv) { | |
3171 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3172 | ADVERTISE_PAUSE_ASYM); | |
3173 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3174 | } | |
3175 | } | |
3176 | ||
3177 | return 1; | |
3178 | } | |
3179 | ||
1da177e4 LT |
3180 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3181 | { | |
3182 | int current_link_up; | |
f833c4c1 | 3183 | u32 bmsr, val; |
ef167e27 | 3184 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3185 | u16 current_speed; |
3186 | u8 current_duplex; | |
3187 | int i, err; | |
3188 | ||
3189 | tw32(MAC_EVENT, 0); | |
3190 | ||
3191 | tw32_f(MAC_STATUS, | |
3192 | (MAC_STATUS_SYNC_CHANGED | | |
3193 | MAC_STATUS_CFG_CHANGED | | |
3194 | MAC_STATUS_MI_COMPLETION | | |
3195 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3196 | udelay(40); | |
3197 | ||
8ef21428 MC |
3198 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3199 | tw32_f(MAC_MI_MODE, | |
3200 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3201 | udelay(80); | |
3202 | } | |
1da177e4 | 3203 | |
b4bd2929 | 3204 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
1da177e4 LT |
3205 | |
3206 | /* Some third-party PHYs need to be reset on link going | |
3207 | * down. | |
3208 | */ | |
3209 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3210 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3211 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3212 | netif_carrier_ok(tp->dev)) { | |
3213 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3214 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3215 | !(bmsr & BMSR_LSTATUS)) | |
3216 | force_reset = 1; | |
3217 | } | |
3218 | if (force_reset) | |
3219 | tg3_phy_reset(tp); | |
3220 | ||
79eb6904 | 3221 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3222 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3223 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
3224 | !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) | |
3225 | bmsr = 0; | |
3226 | ||
3227 | if (!(bmsr & BMSR_LSTATUS)) { | |
3228 | err = tg3_init_5401phy_dsp(tp); | |
3229 | if (err) | |
3230 | return err; | |
3231 | ||
3232 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3233 | for (i = 0; i < 1000; i++) { | |
3234 | udelay(10); | |
3235 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3236 | (bmsr & BMSR_LSTATUS)) { | |
3237 | udelay(40); | |
3238 | break; | |
3239 | } | |
3240 | } | |
3241 | ||
79eb6904 MC |
3242 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3243 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3244 | !(bmsr & BMSR_LSTATUS) && |
3245 | tp->link_config.active_speed == SPEED_1000) { | |
3246 | err = tg3_phy_reset(tp); | |
3247 | if (!err) | |
3248 | err = tg3_init_5401phy_dsp(tp); | |
3249 | if (err) | |
3250 | return err; | |
3251 | } | |
3252 | } | |
3253 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3254 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3255 | /* 5701 {A0,B0} CRC bug workaround */ | |
3256 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
3257 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
3258 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3259 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
3260 | } |
3261 | ||
3262 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
3263 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
3264 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 3265 | |
f07e9af3 | 3266 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 3267 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 3268 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
3269 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3270 | ||
3271 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3272 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3273 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3274 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3275 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3276 | else | |
3277 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3278 | } | |
3279 | ||
3280 | current_link_up = 0; | |
3281 | current_speed = SPEED_INVALID; | |
3282 | current_duplex = DUPLEX_INVALID; | |
3283 | ||
f07e9af3 | 3284 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
15ee95c3 MC |
3285 | err = tg3_phy_auxctl_read(tp, |
3286 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3287 | &val); | |
3288 | if (!err && !(val & (1 << 10))) { | |
b4bd2929 MC |
3289 | tg3_phy_auxctl_write(tp, |
3290 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, | |
3291 | val | (1 << 10)); | |
1da177e4 LT |
3292 | goto relink; |
3293 | } | |
3294 | } | |
3295 | ||
3296 | bmsr = 0; | |
3297 | for (i = 0; i < 100; i++) { | |
3298 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3299 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3300 | (bmsr & BMSR_LSTATUS)) | |
3301 | break; | |
3302 | udelay(40); | |
3303 | } | |
3304 | ||
3305 | if (bmsr & BMSR_LSTATUS) { | |
3306 | u32 aux_stat, bmcr; | |
3307 | ||
3308 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3309 | for (i = 0; i < 2000; i++) { | |
3310 | udelay(10); | |
3311 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3312 | aux_stat) | |
3313 | break; | |
3314 | } | |
3315 | ||
3316 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3317 | ¤t_speed, | |
3318 | ¤t_duplex); | |
3319 | ||
3320 | bmcr = 0; | |
3321 | for (i = 0; i < 200; i++) { | |
3322 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3323 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3324 | continue; | |
3325 | if (bmcr && bmcr != 0x7fff) | |
3326 | break; | |
3327 | udelay(10); | |
3328 | } | |
3329 | ||
ef167e27 MC |
3330 | lcl_adv = 0; |
3331 | rmt_adv = 0; | |
1da177e4 | 3332 | |
ef167e27 MC |
3333 | tp->link_config.active_speed = current_speed; |
3334 | tp->link_config.active_duplex = current_duplex; | |
3335 | ||
3336 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3337 | if ((bmcr & BMCR_ANENABLE) && | |
3338 | tg3_copper_is_advertising_all(tp, | |
3339 | tp->link_config.advertising)) { | |
3340 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3341 | &rmt_adv)) | |
3342 | current_link_up = 1; | |
1da177e4 LT |
3343 | } |
3344 | } else { | |
3345 | if (!(bmcr & BMCR_ANENABLE) && | |
3346 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3347 | tp->link_config.duplex == current_duplex && |
3348 | tp->link_config.flowctrl == | |
3349 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3350 | current_link_up = 1; |
1da177e4 LT |
3351 | } |
3352 | } | |
3353 | ||
ef167e27 MC |
3354 | if (current_link_up == 1 && |
3355 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3356 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3357 | } |
3358 | ||
1da177e4 | 3359 | relink: |
80096068 | 3360 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
3361 | tg3_phy_copper_begin(tp); |
3362 | ||
f833c4c1 MC |
3363 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3364 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3365 | (bmsr & BMSR_LSTATUS)) | |
1da177e4 LT |
3366 | current_link_up = 1; |
3367 | } | |
3368 | ||
3369 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3370 | if (current_link_up == 1) { | |
3371 | if (tp->link_config.active_speed == SPEED_100 || | |
3372 | tp->link_config.active_speed == SPEED_10) | |
3373 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3374 | else | |
3375 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 3376 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
3377 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
3378 | else | |
1da177e4 LT |
3379 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3380 | ||
3381 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3382 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3383 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3384 | ||
1da177e4 | 3385 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3386 | if (current_link_up == 1 && |
3387 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3388 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3389 | else |
3390 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3391 | } |
3392 | ||
3393 | /* ??? Without this setting Netgear GA302T PHY does not | |
3394 | * ??? send/receive packets... | |
3395 | */ | |
79eb6904 | 3396 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
3397 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
3398 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3399 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3400 | udelay(80); | |
3401 | } | |
3402 | ||
3403 | tw32_f(MAC_MODE, tp->mac_mode); | |
3404 | udelay(40); | |
3405 | ||
52b02d04 MC |
3406 | tg3_phy_eee_adjust(tp, current_link_up); |
3407 | ||
1da177e4 LT |
3408 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
3409 | /* Polled via timer. */ | |
3410 | tw32_f(MAC_EVENT, 0); | |
3411 | } else { | |
3412 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3413 | } | |
3414 | udelay(40); | |
3415 | ||
3416 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3417 | current_link_up == 1 && | |
3418 | tp->link_config.active_speed == SPEED_1000 && | |
3419 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || | |
3420 | (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { | |
3421 | udelay(120); | |
3422 | tw32_f(MAC_STATUS, | |
3423 | (MAC_STATUS_SYNC_CHANGED | | |
3424 | MAC_STATUS_CFG_CHANGED)); | |
3425 | udelay(40); | |
3426 | tg3_write_mem(tp, | |
3427 | NIC_SRAM_FIRMWARE_MBOX, | |
3428 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3429 | } | |
3430 | ||
5e7dfd0f MC |
3431 | /* Prevent send BD corruption. */ |
3432 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
3433 | u16 oldlnkctl, newlnkctl; | |
3434 | ||
3435 | pci_read_config_word(tp->pdev, | |
3436 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3437 | &oldlnkctl); | |
3438 | if (tp->link_config.active_speed == SPEED_100 || | |
3439 | tp->link_config.active_speed == SPEED_10) | |
3440 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3441 | else | |
3442 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3443 | if (newlnkctl != oldlnkctl) | |
3444 | pci_write_config_word(tp->pdev, | |
3445 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3446 | newlnkctl); | |
3447 | } | |
3448 | ||
1da177e4 LT |
3449 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3450 | if (current_link_up) | |
3451 | netif_carrier_on(tp->dev); | |
3452 | else | |
3453 | netif_carrier_off(tp->dev); | |
3454 | tg3_link_report(tp); | |
3455 | } | |
3456 | ||
3457 | return 0; | |
3458 | } | |
3459 | ||
3460 | struct tg3_fiber_aneginfo { | |
3461 | int state; | |
3462 | #define ANEG_STATE_UNKNOWN 0 | |
3463 | #define ANEG_STATE_AN_ENABLE 1 | |
3464 | #define ANEG_STATE_RESTART_INIT 2 | |
3465 | #define ANEG_STATE_RESTART 3 | |
3466 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3467 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3468 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3469 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3470 | #define ANEG_STATE_ACK_DETECT 8 | |
3471 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3472 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3473 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3474 | #define ANEG_STATE_IDLE_DETECT 12 | |
3475 | #define ANEG_STATE_LINK_OK 13 | |
3476 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3477 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3478 | ||
3479 | u32 flags; | |
3480 | #define MR_AN_ENABLE 0x00000001 | |
3481 | #define MR_RESTART_AN 0x00000002 | |
3482 | #define MR_AN_COMPLETE 0x00000004 | |
3483 | #define MR_PAGE_RX 0x00000008 | |
3484 | #define MR_NP_LOADED 0x00000010 | |
3485 | #define MR_TOGGLE_TX 0x00000020 | |
3486 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3487 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3488 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3489 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3490 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3491 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3492 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3493 | #define MR_TOGGLE_RX 0x00002000 | |
3494 | #define MR_NP_RX 0x00004000 | |
3495 | ||
3496 | #define MR_LINK_OK 0x80000000 | |
3497 | ||
3498 | unsigned long link_time, cur_time; | |
3499 | ||
3500 | u32 ability_match_cfg; | |
3501 | int ability_match_count; | |
3502 | ||
3503 | char ability_match, idle_match, ack_match; | |
3504 | ||
3505 | u32 txconfig, rxconfig; | |
3506 | #define ANEG_CFG_NP 0x00000080 | |
3507 | #define ANEG_CFG_ACK 0x00000040 | |
3508 | #define ANEG_CFG_RF2 0x00000020 | |
3509 | #define ANEG_CFG_RF1 0x00000010 | |
3510 | #define ANEG_CFG_PS2 0x00000001 | |
3511 | #define ANEG_CFG_PS1 0x00008000 | |
3512 | #define ANEG_CFG_HD 0x00004000 | |
3513 | #define ANEG_CFG_FD 0x00002000 | |
3514 | #define ANEG_CFG_INVAL 0x00001f06 | |
3515 | ||
3516 | }; | |
3517 | #define ANEG_OK 0 | |
3518 | #define ANEG_DONE 1 | |
3519 | #define ANEG_TIMER_ENAB 2 | |
3520 | #define ANEG_FAILED -1 | |
3521 | ||
3522 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3523 | ||
3524 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3525 | struct tg3_fiber_aneginfo *ap) | |
3526 | { | |
5be73b47 | 3527 | u16 flowctrl; |
1da177e4 LT |
3528 | unsigned long delta; |
3529 | u32 rx_cfg_reg; | |
3530 | int ret; | |
3531 | ||
3532 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3533 | ap->rxconfig = 0; | |
3534 | ap->link_time = 0; | |
3535 | ap->cur_time = 0; | |
3536 | ap->ability_match_cfg = 0; | |
3537 | ap->ability_match_count = 0; | |
3538 | ap->ability_match = 0; | |
3539 | ap->idle_match = 0; | |
3540 | ap->ack_match = 0; | |
3541 | } | |
3542 | ap->cur_time++; | |
3543 | ||
3544 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3545 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3546 | ||
3547 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3548 | ap->ability_match_cfg = rx_cfg_reg; | |
3549 | ap->ability_match = 0; | |
3550 | ap->ability_match_count = 0; | |
3551 | } else { | |
3552 | if (++ap->ability_match_count > 1) { | |
3553 | ap->ability_match = 1; | |
3554 | ap->ability_match_cfg = rx_cfg_reg; | |
3555 | } | |
3556 | } | |
3557 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3558 | ap->ack_match = 1; | |
3559 | else | |
3560 | ap->ack_match = 0; | |
3561 | ||
3562 | ap->idle_match = 0; | |
3563 | } else { | |
3564 | ap->idle_match = 1; | |
3565 | ap->ability_match_cfg = 0; | |
3566 | ap->ability_match_count = 0; | |
3567 | ap->ability_match = 0; | |
3568 | ap->ack_match = 0; | |
3569 | ||
3570 | rx_cfg_reg = 0; | |
3571 | } | |
3572 | ||
3573 | ap->rxconfig = rx_cfg_reg; | |
3574 | ret = ANEG_OK; | |
3575 | ||
33f401ae | 3576 | switch (ap->state) { |
1da177e4 LT |
3577 | case ANEG_STATE_UNKNOWN: |
3578 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3579 | ap->state = ANEG_STATE_AN_ENABLE; | |
3580 | ||
3581 | /* fallthru */ | |
3582 | case ANEG_STATE_AN_ENABLE: | |
3583 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3584 | if (ap->flags & MR_AN_ENABLE) { | |
3585 | ap->link_time = 0; | |
3586 | ap->cur_time = 0; | |
3587 | ap->ability_match_cfg = 0; | |
3588 | ap->ability_match_count = 0; | |
3589 | ap->ability_match = 0; | |
3590 | ap->idle_match = 0; | |
3591 | ap->ack_match = 0; | |
3592 | ||
3593 | ap->state = ANEG_STATE_RESTART_INIT; | |
3594 | } else { | |
3595 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3596 | } | |
3597 | break; | |
3598 | ||
3599 | case ANEG_STATE_RESTART_INIT: | |
3600 | ap->link_time = ap->cur_time; | |
3601 | ap->flags &= ~(MR_NP_LOADED); | |
3602 | ap->txconfig = 0; | |
3603 | tw32(MAC_TX_AUTO_NEG, 0); | |
3604 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3605 | tw32_f(MAC_MODE, tp->mac_mode); | |
3606 | udelay(40); | |
3607 | ||
3608 | ret = ANEG_TIMER_ENAB; | |
3609 | ap->state = ANEG_STATE_RESTART; | |
3610 | ||
3611 | /* fallthru */ | |
3612 | case ANEG_STATE_RESTART: | |
3613 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 3614 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 3615 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 3616 | else |
1da177e4 | 3617 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
3618 | break; |
3619 | ||
3620 | case ANEG_STATE_DISABLE_LINK_OK: | |
3621 | ret = ANEG_DONE; | |
3622 | break; | |
3623 | ||
3624 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3625 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3626 | ap->txconfig = ANEG_CFG_FD; |
3627 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3628 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3629 | ap->txconfig |= ANEG_CFG_PS1; | |
3630 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3631 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3632 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3633 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3634 | tw32_f(MAC_MODE, tp->mac_mode); | |
3635 | udelay(40); | |
3636 | ||
3637 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3638 | break; | |
3639 | ||
3640 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 3641 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 3642 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
3643 | break; |
3644 | ||
3645 | case ANEG_STATE_ACK_DETECT_INIT: | |
3646 | ap->txconfig |= ANEG_CFG_ACK; | |
3647 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3648 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3649 | tw32_f(MAC_MODE, tp->mac_mode); | |
3650 | udelay(40); | |
3651 | ||
3652 | ap->state = ANEG_STATE_ACK_DETECT; | |
3653 | ||
3654 | /* fallthru */ | |
3655 | case ANEG_STATE_ACK_DETECT: | |
3656 | if (ap->ack_match != 0) { | |
3657 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3658 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3659 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3660 | } else { | |
3661 | ap->state = ANEG_STATE_AN_ENABLE; | |
3662 | } | |
3663 | } else if (ap->ability_match != 0 && | |
3664 | ap->rxconfig == 0) { | |
3665 | ap->state = ANEG_STATE_AN_ENABLE; | |
3666 | } | |
3667 | break; | |
3668 | ||
3669 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3670 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3671 | ret = ANEG_FAILED; | |
3672 | break; | |
3673 | } | |
3674 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3675 | MR_LP_ADV_HALF_DUPLEX | | |
3676 | MR_LP_ADV_SYM_PAUSE | | |
3677 | MR_LP_ADV_ASYM_PAUSE | | |
3678 | MR_LP_ADV_REMOTE_FAULT1 | | |
3679 | MR_LP_ADV_REMOTE_FAULT2 | | |
3680 | MR_LP_ADV_NEXT_PAGE | | |
3681 | MR_TOGGLE_RX | | |
3682 | MR_NP_RX); | |
3683 | if (ap->rxconfig & ANEG_CFG_FD) | |
3684 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3685 | if (ap->rxconfig & ANEG_CFG_HD) | |
3686 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3687 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3688 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3689 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3690 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3691 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3692 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3693 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3694 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3695 | if (ap->rxconfig & ANEG_CFG_NP) | |
3696 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3697 | ||
3698 | ap->link_time = ap->cur_time; | |
3699 | ||
3700 | ap->flags ^= (MR_TOGGLE_TX); | |
3701 | if (ap->rxconfig & 0x0008) | |
3702 | ap->flags |= MR_TOGGLE_RX; | |
3703 | if (ap->rxconfig & ANEG_CFG_NP) | |
3704 | ap->flags |= MR_NP_RX; | |
3705 | ap->flags |= MR_PAGE_RX; | |
3706 | ||
3707 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3708 | ret = ANEG_TIMER_ENAB; | |
3709 | break; | |
3710 | ||
3711 | case ANEG_STATE_COMPLETE_ACK: | |
3712 | if (ap->ability_match != 0 && | |
3713 | ap->rxconfig == 0) { | |
3714 | ap->state = ANEG_STATE_AN_ENABLE; | |
3715 | break; | |
3716 | } | |
3717 | delta = ap->cur_time - ap->link_time; | |
3718 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3719 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3720 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3721 | } else { | |
3722 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3723 | !(ap->flags & MR_NP_RX)) { | |
3724 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3725 | } else { | |
3726 | ret = ANEG_FAILED; | |
3727 | } | |
3728 | } | |
3729 | } | |
3730 | break; | |
3731 | ||
3732 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3733 | ap->link_time = ap->cur_time; | |
3734 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3735 | tw32_f(MAC_MODE, tp->mac_mode); | |
3736 | udelay(40); | |
3737 | ||
3738 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3739 | ret = ANEG_TIMER_ENAB; | |
3740 | break; | |
3741 | ||
3742 | case ANEG_STATE_IDLE_DETECT: | |
3743 | if (ap->ability_match != 0 && | |
3744 | ap->rxconfig == 0) { | |
3745 | ap->state = ANEG_STATE_AN_ENABLE; | |
3746 | break; | |
3747 | } | |
3748 | delta = ap->cur_time - ap->link_time; | |
3749 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3750 | /* XXX another gem from the Broadcom driver :( */ | |
3751 | ap->state = ANEG_STATE_LINK_OK; | |
3752 | } | |
3753 | break; | |
3754 | ||
3755 | case ANEG_STATE_LINK_OK: | |
3756 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3757 | ret = ANEG_DONE; | |
3758 | break; | |
3759 | ||
3760 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3761 | /* ??? unimplemented */ | |
3762 | break; | |
3763 | ||
3764 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3765 | /* ??? unimplemented */ | |
3766 | break; | |
3767 | ||
3768 | default: | |
3769 | ret = ANEG_FAILED; | |
3770 | break; | |
855e1111 | 3771 | } |
1da177e4 LT |
3772 | |
3773 | return ret; | |
3774 | } | |
3775 | ||
5be73b47 | 3776 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3777 | { |
3778 | int res = 0; | |
3779 | struct tg3_fiber_aneginfo aninfo; | |
3780 | int status = ANEG_FAILED; | |
3781 | unsigned int tick; | |
3782 | u32 tmp; | |
3783 | ||
3784 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3785 | ||
3786 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3787 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3788 | udelay(40); | |
3789 | ||
3790 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3791 | udelay(40); | |
3792 | ||
3793 | memset(&aninfo, 0, sizeof(aninfo)); | |
3794 | aninfo.flags |= MR_AN_ENABLE; | |
3795 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3796 | aninfo.cur_time = 0; | |
3797 | tick = 0; | |
3798 | while (++tick < 195000) { | |
3799 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3800 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3801 | break; | |
3802 | ||
3803 | udelay(1); | |
3804 | } | |
3805 | ||
3806 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3807 | tw32_f(MAC_MODE, tp->mac_mode); | |
3808 | udelay(40); | |
3809 | ||
5be73b47 MC |
3810 | *txflags = aninfo.txconfig; |
3811 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3812 | |
3813 | if (status == ANEG_DONE && | |
3814 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3815 | MR_LP_ADV_FULL_DUPLEX))) | |
3816 | res = 1; | |
3817 | ||
3818 | return res; | |
3819 | } | |
3820 | ||
3821 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3822 | { | |
3823 | u32 mac_status = tr32(MAC_STATUS); | |
3824 | int i; | |
3825 | ||
3826 | /* Reset when initting first time or we have a link. */ | |
3827 | if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && | |
3828 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3829 | return; | |
3830 | ||
3831 | /* Set PLL lock range. */ | |
3832 | tg3_writephy(tp, 0x16, 0x8007); | |
3833 | ||
3834 | /* SW reset */ | |
3835 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3836 | ||
3837 | /* Wait for reset to complete. */ | |
3838 | /* XXX schedule_timeout() ... */ | |
3839 | for (i = 0; i < 500; i++) | |
3840 | udelay(10); | |
3841 | ||
3842 | /* Config mode; select PMA/Ch 1 regs. */ | |
3843 | tg3_writephy(tp, 0x10, 0x8411); | |
3844 | ||
3845 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3846 | tg3_writephy(tp, 0x11, 0x0a10); | |
3847 | ||
3848 | tg3_writephy(tp, 0x18, 0x00a0); | |
3849 | tg3_writephy(tp, 0x16, 0x41ff); | |
3850 | ||
3851 | /* Assert and deassert POR. */ | |
3852 | tg3_writephy(tp, 0x13, 0x0400); | |
3853 | udelay(40); | |
3854 | tg3_writephy(tp, 0x13, 0x0000); | |
3855 | ||
3856 | tg3_writephy(tp, 0x11, 0x0a50); | |
3857 | udelay(40); | |
3858 | tg3_writephy(tp, 0x11, 0x0a10); | |
3859 | ||
3860 | /* Wait for signal to stabilize */ | |
3861 | /* XXX schedule_timeout() ... */ | |
3862 | for (i = 0; i < 15000; i++) | |
3863 | udelay(10); | |
3864 | ||
3865 | /* Deselect the channel register so we can read the PHYID | |
3866 | * later. | |
3867 | */ | |
3868 | tg3_writephy(tp, 0x10, 0x8011); | |
3869 | } | |
3870 | ||
3871 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3872 | { | |
82cd3d11 | 3873 | u16 flowctrl; |
1da177e4 LT |
3874 | u32 sg_dig_ctrl, sg_dig_status; |
3875 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3876 | int workaround, port_a; | |
3877 | int current_link_up; | |
3878 | ||
3879 | serdes_cfg = 0; | |
3880 | expected_sg_dig_ctrl = 0; | |
3881 | workaround = 0; | |
3882 | port_a = 1; | |
3883 | current_link_up = 0; | |
3884 | ||
3885 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3886 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3887 | workaround = 1; | |
3888 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3889 | port_a = 0; | |
3890 | ||
3891 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3892 | /* preserve bits 20-23 for voltage regulator */ | |
3893 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3894 | } | |
3895 | ||
3896 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3897 | ||
3898 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 3899 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
3900 | if (workaround) { |
3901 | u32 val = serdes_cfg; | |
3902 | ||
3903 | if (port_a) | |
3904 | val |= 0xc010000; | |
3905 | else | |
3906 | val |= 0x4010000; | |
3907 | tw32_f(MAC_SERDES_CFG, val); | |
3908 | } | |
c98f6e3b MC |
3909 | |
3910 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
3911 | } |
3912 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3913 | tg3_setup_flow_control(tp, 0, 0); | |
3914 | current_link_up = 1; | |
3915 | } | |
3916 | goto out; | |
3917 | } | |
3918 | ||
3919 | /* Want auto-negotiation. */ | |
c98f6e3b | 3920 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 3921 | |
82cd3d11 MC |
3922 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
3923 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3924 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3925 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3926 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
3927 | |
3928 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 3929 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
3930 | tp->serdes_counter && |
3931 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3932 | MAC_STATUS_RCVD_CFG)) == | |
3933 | MAC_STATUS_PCS_SYNCED)) { | |
3934 | tp->serdes_counter--; | |
3935 | current_link_up = 1; | |
3936 | goto out; | |
3937 | } | |
3938 | restart_autoneg: | |
1da177e4 LT |
3939 | if (workaround) |
3940 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 3941 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
3942 | udelay(5); |
3943 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3944 | ||
3d3ebe74 | 3945 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 3946 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
3947 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
3948 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 3949 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
3950 | mac_status = tr32(MAC_STATUS); |
3951 | ||
c98f6e3b | 3952 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 3953 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
3954 | u32 local_adv = 0, remote_adv = 0; |
3955 | ||
3956 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3957 | local_adv |= ADVERTISE_1000XPAUSE; | |
3958 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3959 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 3960 | |
c98f6e3b | 3961 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 3962 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 3963 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 3964 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
3965 | |
3966 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3967 | current_link_up = 1; | |
3d3ebe74 | 3968 | tp->serdes_counter = 0; |
f07e9af3 | 3969 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 3970 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
3971 | if (tp->serdes_counter) |
3972 | tp->serdes_counter--; | |
1da177e4 LT |
3973 | else { |
3974 | if (workaround) { | |
3975 | u32 val = serdes_cfg; | |
3976 | ||
3977 | if (port_a) | |
3978 | val |= 0xc010000; | |
3979 | else | |
3980 | val |= 0x4010000; | |
3981 | ||
3982 | tw32_f(MAC_SERDES_CFG, val); | |
3983 | } | |
3984 | ||
c98f6e3b | 3985 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
3986 | udelay(40); |
3987 | ||
3988 | /* Link parallel detection - link is up */ | |
3989 | /* only if we have PCS_SYNC and not */ | |
3990 | /* receiving config code words */ | |
3991 | mac_status = tr32(MAC_STATUS); | |
3992 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
3993 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
3994 | tg3_setup_flow_control(tp, 0, 0); | |
3995 | current_link_up = 1; | |
f07e9af3 MC |
3996 | tp->phy_flags |= |
3997 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
3998 | tp->serdes_counter = |
3999 | SERDES_PARALLEL_DET_TIMEOUT; | |
4000 | } else | |
4001 | goto restart_autoneg; | |
1da177e4 LT |
4002 | } |
4003 | } | |
3d3ebe74 MC |
4004 | } else { |
4005 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 4006 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
4007 | } |
4008 | ||
4009 | out: | |
4010 | return current_link_up; | |
4011 | } | |
4012 | ||
4013 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
4014 | { | |
4015 | int current_link_up = 0; | |
4016 | ||
5cf64b8a | 4017 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 4018 | goto out; |
1da177e4 LT |
4019 | |
4020 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 4021 | u32 txflags, rxflags; |
1da177e4 | 4022 | int i; |
6aa20a22 | 4023 | |
5be73b47 MC |
4024 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
4025 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 4026 | |
5be73b47 MC |
4027 | if (txflags & ANEG_CFG_PS1) |
4028 | local_adv |= ADVERTISE_1000XPAUSE; | |
4029 | if (txflags & ANEG_CFG_PS2) | |
4030 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4031 | ||
4032 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4033 | remote_adv |= LPA_1000XPAUSE; | |
4034 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4035 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
4036 | |
4037 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4038 | ||
1da177e4 LT |
4039 | current_link_up = 1; |
4040 | } | |
4041 | for (i = 0; i < 30; i++) { | |
4042 | udelay(20); | |
4043 | tw32_f(MAC_STATUS, | |
4044 | (MAC_STATUS_SYNC_CHANGED | | |
4045 | MAC_STATUS_CFG_CHANGED)); | |
4046 | udelay(40); | |
4047 | if ((tr32(MAC_STATUS) & | |
4048 | (MAC_STATUS_SYNC_CHANGED | | |
4049 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4050 | break; | |
4051 | } | |
4052 | ||
4053 | mac_status = tr32(MAC_STATUS); | |
4054 | if (current_link_up == 0 && | |
4055 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4056 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4057 | current_link_up = 1; | |
4058 | } else { | |
5be73b47 MC |
4059 | tg3_setup_flow_control(tp, 0, 0); |
4060 | ||
1da177e4 LT |
4061 | /* Forcing 1000FD link up. */ |
4062 | current_link_up = 1; | |
1da177e4 LT |
4063 | |
4064 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4065 | udelay(40); | |
e8f3f6ca MC |
4066 | |
4067 | tw32_f(MAC_MODE, tp->mac_mode); | |
4068 | udelay(40); | |
1da177e4 LT |
4069 | } |
4070 | ||
4071 | out: | |
4072 | return current_link_up; | |
4073 | } | |
4074 | ||
4075 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4076 | { | |
4077 | u32 orig_pause_cfg; | |
4078 | u16 orig_active_speed; | |
4079 | u8 orig_active_duplex; | |
4080 | u32 mac_status; | |
4081 | int current_link_up; | |
4082 | int i; | |
4083 | ||
8d018621 | 4084 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4085 | orig_active_speed = tp->link_config.active_speed; |
4086 | orig_active_duplex = tp->link_config.active_duplex; | |
4087 | ||
4088 | if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && | |
4089 | netif_carrier_ok(tp->dev) && | |
4090 | (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { | |
4091 | mac_status = tr32(MAC_STATUS); | |
4092 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4093 | MAC_STATUS_SIGNAL_DET | | |
4094 | MAC_STATUS_CFG_CHANGED | | |
4095 | MAC_STATUS_RCVD_CFG); | |
4096 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4097 | MAC_STATUS_SIGNAL_DET)) { | |
4098 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4099 | MAC_STATUS_CFG_CHANGED)); | |
4100 | return 0; | |
4101 | } | |
4102 | } | |
4103 | ||
4104 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4105 | ||
4106 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4107 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4108 | tw32_f(MAC_MODE, tp->mac_mode); | |
4109 | udelay(40); | |
4110 | ||
79eb6904 | 4111 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
4112 | tg3_init_bcm8002(tp); |
4113 | ||
4114 | /* Enable link change event even when serdes polling. */ | |
4115 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4116 | udelay(40); | |
4117 | ||
4118 | current_link_up = 0; | |
4119 | mac_status = tr32(MAC_STATUS); | |
4120 | ||
4121 | if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) | |
4122 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
4123 | else | |
4124 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4125 | ||
898a56f8 | 4126 | tp->napi[0].hw_status->status = |
1da177e4 | 4127 | (SD_STATUS_UPDATED | |
898a56f8 | 4128 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4129 | |
4130 | for (i = 0; i < 100; i++) { | |
4131 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4132 | MAC_STATUS_CFG_CHANGED)); | |
4133 | udelay(5); | |
4134 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4135 | MAC_STATUS_CFG_CHANGED | |
4136 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4137 | break; |
4138 | } | |
4139 | ||
4140 | mac_status = tr32(MAC_STATUS); | |
4141 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4142 | current_link_up = 0; | |
3d3ebe74 MC |
4143 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4144 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4145 | tw32_f(MAC_MODE, (tp->mac_mode | |
4146 | MAC_MODE_SEND_CONFIGS)); | |
4147 | udelay(1); | |
4148 | tw32_f(MAC_MODE, tp->mac_mode); | |
4149 | } | |
4150 | } | |
4151 | ||
4152 | if (current_link_up == 1) { | |
4153 | tp->link_config.active_speed = SPEED_1000; | |
4154 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4155 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4156 | LED_CTRL_LNKLED_OVERRIDE | | |
4157 | LED_CTRL_1000MBPS_ON)); | |
4158 | } else { | |
4159 | tp->link_config.active_speed = SPEED_INVALID; | |
4160 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4161 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4162 | LED_CTRL_LNKLED_OVERRIDE | | |
4163 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4164 | } | |
4165 | ||
4166 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4167 | if (current_link_up) | |
4168 | netif_carrier_on(tp->dev); | |
4169 | else | |
4170 | netif_carrier_off(tp->dev); | |
4171 | tg3_link_report(tp); | |
4172 | } else { | |
8d018621 | 4173 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4174 | if (orig_pause_cfg != now_pause_cfg || |
4175 | orig_active_speed != tp->link_config.active_speed || | |
4176 | orig_active_duplex != tp->link_config.active_duplex) | |
4177 | tg3_link_report(tp); | |
4178 | } | |
4179 | ||
4180 | return 0; | |
4181 | } | |
4182 | ||
747e8f8b MC |
4183 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4184 | { | |
4185 | int current_link_up, err = 0; | |
4186 | u32 bmsr, bmcr; | |
4187 | u16 current_speed; | |
4188 | u8 current_duplex; | |
ef167e27 | 4189 | u32 local_adv, remote_adv; |
747e8f8b MC |
4190 | |
4191 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4192 | tw32_f(MAC_MODE, tp->mac_mode); | |
4193 | udelay(40); | |
4194 | ||
4195 | tw32(MAC_EVENT, 0); | |
4196 | ||
4197 | tw32_f(MAC_STATUS, | |
4198 | (MAC_STATUS_SYNC_CHANGED | | |
4199 | MAC_STATUS_CFG_CHANGED | | |
4200 | MAC_STATUS_MI_COMPLETION | | |
4201 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4202 | udelay(40); | |
4203 | ||
4204 | if (force_reset) | |
4205 | tg3_phy_reset(tp); | |
4206 | ||
4207 | current_link_up = 0; | |
4208 | current_speed = SPEED_INVALID; | |
4209 | current_duplex = DUPLEX_INVALID; | |
4210 | ||
4211 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4212 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4213 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4214 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4215 | bmsr |= BMSR_LSTATUS; | |
4216 | else | |
4217 | bmsr &= ~BMSR_LSTATUS; | |
4218 | } | |
747e8f8b MC |
4219 | |
4220 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4221 | ||
4222 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 4223 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4224 | /* do nothing, just check for link up at the end */ |
4225 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4226 | u32 adv, new_adv; | |
4227 | ||
4228 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4229 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4230 | ADVERTISE_1000XPAUSE | | |
4231 | ADVERTISE_1000XPSE_ASYM | | |
4232 | ADVERTISE_SLCT); | |
4233 | ||
ba4d07a8 | 4234 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4235 | |
4236 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4237 | new_adv |= ADVERTISE_1000XHALF; | |
4238 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4239 | new_adv |= ADVERTISE_1000XFULL; | |
4240 | ||
4241 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4242 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4243 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4244 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4245 | ||
4246 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4247 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 4248 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4249 | |
4250 | return err; | |
4251 | } | |
4252 | } else { | |
4253 | u32 new_bmcr; | |
4254 | ||
4255 | bmcr &= ~BMCR_SPEED1000; | |
4256 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4257 | ||
4258 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4259 | new_bmcr |= BMCR_FULLDPLX; | |
4260 | ||
4261 | if (new_bmcr != bmcr) { | |
4262 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4263 | * to be set on write. | |
4264 | */ | |
4265 | new_bmcr |= BMCR_SPEED1000; | |
4266 | ||
4267 | /* Force a linkdown */ | |
4268 | if (netif_carrier_ok(tp->dev)) { | |
4269 | u32 adv; | |
4270 | ||
4271 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4272 | adv &= ~(ADVERTISE_1000XFULL | | |
4273 | ADVERTISE_1000XHALF | | |
4274 | ADVERTISE_SLCT); | |
4275 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4276 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4277 | BMCR_ANRESTART | | |
4278 | BMCR_ANENABLE); | |
4279 | udelay(10); | |
4280 | netif_carrier_off(tp->dev); | |
4281 | } | |
4282 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4283 | bmcr = new_bmcr; | |
4284 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4285 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4286 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4287 | ASIC_REV_5714) { | |
4288 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4289 | bmsr |= BMSR_LSTATUS; | |
4290 | else | |
4291 | bmsr &= ~BMSR_LSTATUS; | |
4292 | } | |
f07e9af3 | 4293 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4294 | } |
4295 | } | |
4296 | ||
4297 | if (bmsr & BMSR_LSTATUS) { | |
4298 | current_speed = SPEED_1000; | |
4299 | current_link_up = 1; | |
4300 | if (bmcr & BMCR_FULLDPLX) | |
4301 | current_duplex = DUPLEX_FULL; | |
4302 | else | |
4303 | current_duplex = DUPLEX_HALF; | |
4304 | ||
ef167e27 MC |
4305 | local_adv = 0; |
4306 | remote_adv = 0; | |
4307 | ||
747e8f8b | 4308 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4309 | u32 common; |
747e8f8b MC |
4310 | |
4311 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4312 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4313 | common = local_adv & remote_adv; | |
4314 | if (common & (ADVERTISE_1000XHALF | | |
4315 | ADVERTISE_1000XFULL)) { | |
4316 | if (common & ADVERTISE_1000XFULL) | |
4317 | current_duplex = DUPLEX_FULL; | |
4318 | else | |
4319 | current_duplex = DUPLEX_HALF; | |
57d8b880 MC |
4320 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
4321 | /* Link is up via parallel detect */ | |
859a5887 | 4322 | } else { |
747e8f8b | 4323 | current_link_up = 0; |
859a5887 | 4324 | } |
747e8f8b MC |
4325 | } |
4326 | } | |
4327 | ||
ef167e27 MC |
4328 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4329 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4330 | ||
747e8f8b MC |
4331 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4332 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4333 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4334 | ||
4335 | tw32_f(MAC_MODE, tp->mac_mode); | |
4336 | udelay(40); | |
4337 | ||
4338 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4339 | ||
4340 | tp->link_config.active_speed = current_speed; | |
4341 | tp->link_config.active_duplex = current_duplex; | |
4342 | ||
4343 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4344 | if (current_link_up) | |
4345 | netif_carrier_on(tp->dev); | |
4346 | else { | |
4347 | netif_carrier_off(tp->dev); | |
f07e9af3 | 4348 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4349 | } |
4350 | tg3_link_report(tp); | |
4351 | } | |
4352 | return err; | |
4353 | } | |
4354 | ||
4355 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4356 | { | |
3d3ebe74 | 4357 | if (tp->serdes_counter) { |
747e8f8b | 4358 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4359 | tp->serdes_counter--; |
747e8f8b MC |
4360 | return; |
4361 | } | |
c6cdf436 | 4362 | |
747e8f8b MC |
4363 | if (!netif_carrier_ok(tp->dev) && |
4364 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4365 | u32 bmcr; | |
4366 | ||
4367 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4368 | if (bmcr & BMCR_ANENABLE) { | |
4369 | u32 phy1, phy2; | |
4370 | ||
4371 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
4372 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
4373 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
4374 | |
4375 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4376 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4377 | MII_TG3_DSP_EXP1_INT_STAT); | |
4378 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4379 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4380 | |
4381 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4382 | /* We have signal detect and not receiving | |
4383 | * config code words, link is up by parallel | |
4384 | * detection. | |
4385 | */ | |
4386 | ||
4387 | bmcr &= ~BMCR_ANENABLE; | |
4388 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4389 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 4390 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4391 | } |
4392 | } | |
859a5887 MC |
4393 | } else if (netif_carrier_ok(tp->dev) && |
4394 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 4395 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4396 | u32 phy2; |
4397 | ||
4398 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4399 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4400 | MII_TG3_DSP_EXP1_INT_STAT); | |
4401 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4402 | if (phy2 & 0x20) { |
4403 | u32 bmcr; | |
4404 | ||
4405 | /* Config code words received, turn on autoneg. */ | |
4406 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4407 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4408 | ||
f07e9af3 | 4409 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4410 | |
4411 | } | |
4412 | } | |
4413 | } | |
4414 | ||
1da177e4 LT |
4415 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4416 | { | |
f2096f94 | 4417 | u32 val; |
1da177e4 LT |
4418 | int err; |
4419 | ||
f07e9af3 | 4420 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 4421 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 4422 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 4423 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 4424 | else |
1da177e4 | 4425 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 4426 | |
bcb37f6c | 4427 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 4428 | u32 scale; |
aa6c91fe MC |
4429 | |
4430 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4431 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4432 | scale = 65; | |
4433 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4434 | scale = 6; | |
4435 | else | |
4436 | scale = 12; | |
4437 | ||
4438 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4439 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4440 | tw32(GRC_MISC_CFG, val); | |
4441 | } | |
4442 | ||
f2096f94 MC |
4443 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
4444 | (6 << TX_LENGTHS_IPG_SHIFT); | |
4445 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
4446 | val |= tr32(MAC_TX_LENGTHS) & | |
4447 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
4448 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
4449 | ||
1da177e4 LT |
4450 | if (tp->link_config.active_speed == SPEED_1000 && |
4451 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
4452 | tw32(MAC_TX_LENGTHS, val | |
4453 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 4454 | else |
f2096f94 MC |
4455 | tw32(MAC_TX_LENGTHS, val | |
4456 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 LT |
4457 | |
4458 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4459 | if (netif_carrier_ok(tp->dev)) { | |
4460 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4461 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4462 | } else { |
4463 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4464 | } | |
4465 | } | |
4466 | ||
8ed5d97e | 4467 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { |
f2096f94 | 4468 | val = tr32(PCIE_PWR_MGMT_THRESH); |
8ed5d97e MC |
4469 | if (!netif_carrier_ok(tp->dev)) |
4470 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4471 | tp->pwrmgmt_thresh; | |
4472 | else | |
4473 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4474 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4475 | } | |
4476 | ||
1da177e4 LT |
4477 | return err; |
4478 | } | |
4479 | ||
66cfd1bd MC |
4480 | static inline int tg3_irq_sync(struct tg3 *tp) |
4481 | { | |
4482 | return tp->irq_sync; | |
4483 | } | |
4484 | ||
97bd8e49 MC |
4485 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
4486 | { | |
4487 | int i; | |
4488 | ||
4489 | dst = (u32 *)((u8 *)dst + off); | |
4490 | for (i = 0; i < len; i += sizeof(u32)) | |
4491 | *dst++ = tr32(off + i); | |
4492 | } | |
4493 | ||
4494 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
4495 | { | |
4496 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
4497 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
4498 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
4499 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
4500 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
4501 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
4502 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
4503 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
4504 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
4505 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
4506 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
4507 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
4508 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
4509 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
4510 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
4511 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
4512 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
4513 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
4514 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
4515 | ||
4516 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) | |
4517 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); | |
4518 | ||
4519 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
4520 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
4521 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
4522 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
4523 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
4524 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
4525 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
4526 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
4527 | ||
4528 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4529 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); | |
4530 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
4531 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
4532 | } | |
4533 | ||
4534 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
4535 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
4536 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
4537 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
4538 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
4539 | ||
4540 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
4541 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); | |
4542 | } | |
4543 | ||
4544 | static void tg3_dump_state(struct tg3 *tp) | |
4545 | { | |
4546 | int i; | |
4547 | u32 *regs; | |
4548 | ||
4549 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
4550 | if (!regs) { | |
4551 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
4552 | return; | |
4553 | } | |
4554 | ||
4555 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
4556 | /* Read up to but not including private PCI registers */ | |
4557 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
4558 | regs[i / sizeof(u32)] = tr32(i); | |
4559 | } else | |
4560 | tg3_dump_legacy_regs(tp, regs); | |
4561 | ||
4562 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
4563 | if (!regs[i + 0] && !regs[i + 1] && | |
4564 | !regs[i + 2] && !regs[i + 3]) | |
4565 | continue; | |
4566 | ||
4567 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
4568 | i * 4, | |
4569 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
4570 | } | |
4571 | ||
4572 | kfree(regs); | |
4573 | ||
4574 | for (i = 0; i < tp->irq_cnt; i++) { | |
4575 | struct tg3_napi *tnapi = &tp->napi[i]; | |
4576 | ||
4577 | /* SW status block */ | |
4578 | netdev_err(tp->dev, | |
4579 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
4580 | i, | |
4581 | tnapi->hw_status->status, | |
4582 | tnapi->hw_status->status_tag, | |
4583 | tnapi->hw_status->rx_jumbo_consumer, | |
4584 | tnapi->hw_status->rx_consumer, | |
4585 | tnapi->hw_status->rx_mini_consumer, | |
4586 | tnapi->hw_status->idx[0].rx_producer, | |
4587 | tnapi->hw_status->idx[0].tx_consumer); | |
4588 | ||
4589 | netdev_err(tp->dev, | |
4590 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
4591 | i, | |
4592 | tnapi->last_tag, tnapi->last_irq_tag, | |
4593 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
4594 | tnapi->rx_rcb_ptr, | |
4595 | tnapi->prodring.rx_std_prod_idx, | |
4596 | tnapi->prodring.rx_std_cons_idx, | |
4597 | tnapi->prodring.rx_jmb_prod_idx, | |
4598 | tnapi->prodring.rx_jmb_cons_idx); | |
4599 | } | |
4600 | } | |
4601 | ||
df3e6548 MC |
4602 | /* This is called whenever we suspect that the system chipset is re- |
4603 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4604 | * is bogus tx completions. We try to recover by setting the | |
4605 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4606 | * in the workqueue. | |
4607 | */ | |
4608 | static void tg3_tx_recover(struct tg3 *tp) | |
4609 | { | |
4610 | BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || | |
4611 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4612 | ||
5129c3a3 MC |
4613 | netdev_warn(tp->dev, |
4614 | "The system may be re-ordering memory-mapped I/O " | |
4615 | "cycles to the network device, attempting to recover. " | |
4616 | "Please report the problem to the driver maintainer " | |
4617 | "and include system chipset information.\n"); | |
df3e6548 MC |
4618 | |
4619 | spin_lock(&tp->lock); | |
df3e6548 | 4620 | tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; |
df3e6548 MC |
4621 | spin_unlock(&tp->lock); |
4622 | } | |
4623 | ||
f3f3f27e | 4624 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 4625 | { |
f65aac16 MC |
4626 | /* Tell compiler to fetch tx indices from memory. */ |
4627 | barrier(); | |
f3f3f27e MC |
4628 | return tnapi->tx_pending - |
4629 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4630 | } |
4631 | ||
1da177e4 LT |
4632 | /* Tigon3 never reports partial packet sends. So we do not |
4633 | * need special logic to handle SKBs that have not had all | |
4634 | * of their frags sent yet, like SunGEM does. | |
4635 | */ | |
17375d25 | 4636 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4637 | { |
17375d25 | 4638 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4639 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4640 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
4641 | struct netdev_queue *txq; |
4642 | int index = tnapi - tp->napi; | |
4643 | ||
19cfaecc | 4644 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 MC |
4645 | index--; |
4646 | ||
4647 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
4648 | |
4649 | while (sw_idx != hw_idx) { | |
f4188d8a | 4650 | struct ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4651 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4652 | int i, tx_bug = 0; |
4653 | ||
4654 | if (unlikely(skb == NULL)) { | |
4655 | tg3_tx_recover(tp); | |
4656 | return; | |
4657 | } | |
1da177e4 | 4658 | |
f4188d8a | 4659 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 4660 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4661 | skb_headlen(skb), |
4662 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4663 | |
4664 | ri->skb = NULL; | |
4665 | ||
4666 | sw_idx = NEXT_TX(sw_idx); | |
4667 | ||
4668 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4669 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4670 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4671 | tx_bug = 1; | |
f4188d8a AD |
4672 | |
4673 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 4674 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4675 | skb_shinfo(skb)->frags[i].size, |
4676 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4677 | sw_idx = NEXT_TX(sw_idx); |
4678 | } | |
4679 | ||
f47c11ee | 4680 | dev_kfree_skb(skb); |
df3e6548 MC |
4681 | |
4682 | if (unlikely(tx_bug)) { | |
4683 | tg3_tx_recover(tp); | |
4684 | return; | |
4685 | } | |
1da177e4 LT |
4686 | } |
4687 | ||
f3f3f27e | 4688 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4689 | |
1b2a7205 MC |
4690 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4691 | * before checking for netif_queue_stopped(). Without the | |
4692 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4693 | * will miss it and cause the queue to be stopped forever. | |
4694 | */ | |
4695 | smp_mb(); | |
4696 | ||
fe5f5787 | 4697 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 4698 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
4699 | __netif_tx_lock(txq, smp_processor_id()); |
4700 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 4701 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
4702 | netif_tx_wake_queue(txq); |
4703 | __netif_tx_unlock(txq); | |
51b91468 | 4704 | } |
1da177e4 LT |
4705 | } |
4706 | ||
2b2cdb65 MC |
4707 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
4708 | { | |
4709 | if (!ri->skb) | |
4710 | return; | |
4711 | ||
4e5e4f0d | 4712 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 MC |
4713 | map_sz, PCI_DMA_FROMDEVICE); |
4714 | dev_kfree_skb_any(ri->skb); | |
4715 | ri->skb = NULL; | |
4716 | } | |
4717 | ||
1da177e4 LT |
4718 | /* Returns size of skb allocated or < 0 on error. |
4719 | * | |
4720 | * We only need to fill in the address because the other members | |
4721 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4722 | * | |
4723 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4724 | * posting buffers we only dirty the first cache line of the RX | |
4725 | * descriptor (containing the address). Whereas for the RX status | |
4726 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4727 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4728 | */ | |
86b21e59 | 4729 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 4730 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
4731 | { |
4732 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 4733 | struct ring_info *map; |
1da177e4 LT |
4734 | struct sk_buff *skb; |
4735 | dma_addr_t mapping; | |
4736 | int skb_size, dest_idx; | |
4737 | ||
1da177e4 LT |
4738 | switch (opaque_key) { |
4739 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4740 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
4741 | desc = &tpr->rx_std[dest_idx]; |
4742 | map = &tpr->rx_std_buffers[dest_idx]; | |
287be12e | 4743 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4744 | break; |
4745 | ||
4746 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4747 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 4748 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4749 | map = &tpr->rx_jmb_buffers[dest_idx]; |
287be12e | 4750 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4751 | break; |
4752 | ||
4753 | default: | |
4754 | return -EINVAL; | |
855e1111 | 4755 | } |
1da177e4 LT |
4756 | |
4757 | /* Do not overwrite any of the map or rp information | |
4758 | * until we are sure we can commit to a new buffer. | |
4759 | * | |
4760 | * Callers depend upon this behavior and assume that | |
4761 | * we leave everything unchanged if we fail. | |
4762 | */ | |
287be12e | 4763 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4764 | if (skb == NULL) |
4765 | return -ENOMEM; | |
4766 | ||
1da177e4 LT |
4767 | skb_reserve(skb, tp->rx_offset); |
4768 | ||
287be12e | 4769 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 4770 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
4771 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
4772 | dev_kfree_skb(skb); | |
4773 | return -EIO; | |
4774 | } | |
1da177e4 LT |
4775 | |
4776 | map->skb = skb; | |
4e5e4f0d | 4777 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 4778 | |
1da177e4 LT |
4779 | desc->addr_hi = ((u64)mapping >> 32); |
4780 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4781 | ||
4782 | return skb_size; | |
4783 | } | |
4784 | ||
4785 | /* We only need to move over in the address because the other | |
4786 | * members of the RX descriptor are invariant. See notes above | |
4787 | * tg3_alloc_rx_skb for full details. | |
4788 | */ | |
a3896167 MC |
4789 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
4790 | struct tg3_rx_prodring_set *dpr, | |
4791 | u32 opaque_key, int src_idx, | |
4792 | u32 dest_idx_unmasked) | |
1da177e4 | 4793 | { |
17375d25 | 4794 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4795 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4796 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 4797 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 4798 | int dest_idx; |
1da177e4 LT |
4799 | |
4800 | switch (opaque_key) { | |
4801 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4802 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
4803 | dest_desc = &dpr->rx_std[dest_idx]; |
4804 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4805 | src_desc = &spr->rx_std[src_idx]; | |
4806 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4807 | break; |
4808 | ||
4809 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4810 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
4811 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
4812 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
4813 | src_desc = &spr->rx_jmb[src_idx].std; | |
4814 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
4815 | break; |
4816 | ||
4817 | default: | |
4818 | return; | |
855e1111 | 4819 | } |
1da177e4 LT |
4820 | |
4821 | dest_map->skb = src_map->skb; | |
4e5e4f0d FT |
4822 | dma_unmap_addr_set(dest_map, mapping, |
4823 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
4824 | dest_desc->addr_hi = src_desc->addr_hi; |
4825 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
4826 | |
4827 | /* Ensure that the update to the skb happens after the physical | |
4828 | * addresses have been transferred to the new BD location. | |
4829 | */ | |
4830 | smp_wmb(); | |
4831 | ||
1da177e4 LT |
4832 | src_map->skb = NULL; |
4833 | } | |
4834 | ||
1da177e4 LT |
4835 | /* The RX ring scheme is composed of multiple rings which post fresh |
4836 | * buffers to the chip, and one special ring the chip uses to report | |
4837 | * status back to the host. | |
4838 | * | |
4839 | * The special ring reports the status of received packets to the | |
4840 | * host. The chip does not write into the original descriptor the | |
4841 | * RX buffer was obtained from. The chip simply takes the original | |
4842 | * descriptor as provided by the host, updates the status and length | |
4843 | * field, then writes this into the next status ring entry. | |
4844 | * | |
4845 | * Each ring the host uses to post buffers to the chip is described | |
4846 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4847 | * it is first placed into the on-chip ram. When the packet's length | |
4848 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4849 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4850 | * which is within the range of the new packet's length is chosen. | |
4851 | * | |
4852 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4853 | * sense from a cache coherency perspective. If only the host writes | |
4854 | * to the buffer post rings, and only the chip writes to the rx status | |
4855 | * rings, then cache lines never move beyond shared-modified state. | |
4856 | * If both the host and chip were to write into the same ring, cache line | |
4857 | * eviction could occur since both entities want it in an exclusive state. | |
4858 | */ | |
17375d25 | 4859 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 4860 | { |
17375d25 | 4861 | struct tg3 *tp = tnapi->tp; |
f92905de | 4862 | u32 work_mask, rx_std_posted = 0; |
4361935a | 4863 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 4864 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 4865 | u16 hw_idx; |
1da177e4 | 4866 | int received; |
8fea32b9 | 4867 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 4868 | |
8d9d7cfc | 4869 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
4870 | /* |
4871 | * We need to order the read of hw_idx and the read of | |
4872 | * the opaque cookie. | |
4873 | */ | |
4874 | rmb(); | |
1da177e4 LT |
4875 | work_mask = 0; |
4876 | received = 0; | |
4361935a MC |
4877 | std_prod_idx = tpr->rx_std_prod_idx; |
4878 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 4879 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 4880 | struct ring_info *ri; |
72334482 | 4881 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
4882 | unsigned int len; |
4883 | struct sk_buff *skb; | |
4884 | dma_addr_t dma_addr; | |
4885 | u32 opaque_key, desc_idx, *post_ptr; | |
4886 | ||
4887 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4888 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4889 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 4890 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 4891 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4892 | skb = ri->skb; |
4361935a | 4893 | post_ptr = &std_prod_idx; |
f92905de | 4894 | rx_std_posted++; |
1da177e4 | 4895 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 4896 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 4897 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4898 | skb = ri->skb; |
4361935a | 4899 | post_ptr = &jmb_prod_idx; |
21f581a5 | 4900 | } else |
1da177e4 | 4901 | goto next_pkt_nopost; |
1da177e4 LT |
4902 | |
4903 | work_mask |= opaque_key; | |
4904 | ||
4905 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4906 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4907 | drop_it: | |
a3896167 | 4908 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4909 | desc_idx, *post_ptr); |
4910 | drop_it_no_recycle: | |
4911 | /* Other statistics kept track of by card. */ | |
b0057c51 | 4912 | tp->rx_dropped++; |
1da177e4 LT |
4913 | goto next_pkt; |
4914 | } | |
4915 | ||
ad829268 MC |
4916 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
4917 | ETH_FCS_LEN; | |
1da177e4 | 4918 | |
d2757fc4 | 4919 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
4920 | int skb_size; |
4921 | ||
86b21e59 | 4922 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, |
afc081f8 | 4923 | *post_ptr); |
1da177e4 LT |
4924 | if (skb_size < 0) |
4925 | goto drop_it; | |
4926 | ||
287be12e | 4927 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
4928 | PCI_DMA_FROMDEVICE); |
4929 | ||
61e800cf MC |
4930 | /* Ensure that the update to the skb happens |
4931 | * after the usage of the old DMA mapping. | |
4932 | */ | |
4933 | smp_wmb(); | |
4934 | ||
4935 | ri->skb = NULL; | |
4936 | ||
1da177e4 LT |
4937 | skb_put(skb, len); |
4938 | } else { | |
4939 | struct sk_buff *copy_skb; | |
4940 | ||
a3896167 | 4941 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4942 | desc_idx, *post_ptr); |
4943 | ||
bf933c80 | 4944 | copy_skb = netdev_alloc_skb(tp->dev, len + |
9dc7a113 | 4945 | TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4946 | if (copy_skb == NULL) |
4947 | goto drop_it_no_recycle; | |
4948 | ||
bf933c80 | 4949 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4950 | skb_put(copy_skb, len); |
4951 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 4952 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
4953 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
4954 | ||
4955 | /* We'll reuse the original ring buffer. */ | |
4956 | skb = copy_skb; | |
4957 | } | |
4958 | ||
dc668910 | 4959 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
4960 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
4961 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4962 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4963 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4964 | else | |
bc8acf2c | 4965 | skb_checksum_none_assert(skb); |
1da177e4 LT |
4966 | |
4967 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
4968 | |
4969 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4970 | skb->protocol != htons(ETH_P_8021Q)) { | |
4971 | dev_kfree_skb(skb); | |
b0057c51 | 4972 | goto drop_it_no_recycle; |
f7b493e0 MC |
4973 | } |
4974 | ||
9dc7a113 | 4975 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
4976 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
4977 | __vlan_hwaccel_put_tag(skb, | |
4978 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 4979 | |
bf933c80 | 4980 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 4981 | |
1da177e4 LT |
4982 | received++; |
4983 | budget--; | |
4984 | ||
4985 | next_pkt: | |
4986 | (*post_ptr)++; | |
f92905de MC |
4987 | |
4988 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
4989 | tpr->rx_std_prod_idx = std_prod_idx & |
4990 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
4991 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
4992 | tpr->rx_std_prod_idx); | |
f92905de MC |
4993 | work_mask &= ~RXD_OPAQUE_RING_STD; |
4994 | rx_std_posted = 0; | |
4995 | } | |
1da177e4 | 4996 | next_pkt_nopost: |
483ba50b | 4997 | sw_idx++; |
7cb32cf2 | 4998 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
4999 | |
5000 | /* Refresh hw_idx to see if there is new work */ | |
5001 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 5002 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
5003 | rmb(); |
5004 | } | |
1da177e4 LT |
5005 | } |
5006 | ||
5007 | /* ACK the status ring. */ | |
72334482 MC |
5008 | tnapi->rx_rcb_ptr = sw_idx; |
5009 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
5010 | |
5011 | /* Refill RX ring(s). */ | |
e4af1af9 | 5012 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { |
b196c7e4 | 5013 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
5014 | tpr->rx_std_prod_idx = std_prod_idx & |
5015 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5016 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
5017 | tpr->rx_std_prod_idx); | |
5018 | } | |
5019 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
5020 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
5021 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
5022 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
5023 | tpr->rx_jmb_prod_idx); | |
5024 | } | |
5025 | mmiowb(); | |
5026 | } else if (work_mask) { | |
5027 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
5028 | * updated before the producer indices can be updated. | |
5029 | */ | |
5030 | smp_wmb(); | |
5031 | ||
2c49a44d MC |
5032 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
5033 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 5034 | |
e4af1af9 MC |
5035 | if (tnapi != &tp->napi[1]) |
5036 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 5037 | } |
1da177e4 LT |
5038 | |
5039 | return received; | |
5040 | } | |
5041 | ||
35f2d7d0 | 5042 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 5043 | { |
1da177e4 LT |
5044 | /* handle link change and other phy events */ |
5045 | if (!(tp->tg3_flags & | |
5046 | (TG3_FLAG_USE_LINKCHG_REG | | |
5047 | TG3_FLAG_POLL_SERDES))) { | |
35f2d7d0 MC |
5048 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
5049 | ||
1da177e4 LT |
5050 | if (sblk->status & SD_STATUS_LINK_CHG) { |
5051 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 5052 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 5053 | spin_lock(&tp->lock); |
dd477003 MC |
5054 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
5055 | tw32_f(MAC_STATUS, | |
5056 | (MAC_STATUS_SYNC_CHANGED | | |
5057 | MAC_STATUS_CFG_CHANGED | | |
5058 | MAC_STATUS_MI_COMPLETION | | |
5059 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5060 | udelay(40); | |
5061 | } else | |
5062 | tg3_setup_phy(tp, 0); | |
f47c11ee | 5063 | spin_unlock(&tp->lock); |
1da177e4 LT |
5064 | } |
5065 | } | |
35f2d7d0 MC |
5066 | } |
5067 | ||
f89f38b8 MC |
5068 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
5069 | struct tg3_rx_prodring_set *dpr, | |
5070 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
5071 | { |
5072 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 5073 | int i, err = 0; |
b196c7e4 MC |
5074 | |
5075 | while (1) { | |
5076 | src_prod_idx = spr->rx_std_prod_idx; | |
5077 | ||
5078 | /* Make sure updates to the rx_std_buffers[] entries and the | |
5079 | * standard producer index are seen in the correct order. | |
5080 | */ | |
5081 | smp_rmb(); | |
5082 | ||
5083 | if (spr->rx_std_cons_idx == src_prod_idx) | |
5084 | break; | |
5085 | ||
5086 | if (spr->rx_std_cons_idx < src_prod_idx) | |
5087 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
5088 | else | |
2c49a44d MC |
5089 | cpycnt = tp->rx_std_ring_mask + 1 - |
5090 | spr->rx_std_cons_idx; | |
b196c7e4 | 5091 | |
2c49a44d MC |
5092 | cpycnt = min(cpycnt, |
5093 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
5094 | |
5095 | si = spr->rx_std_cons_idx; | |
5096 | di = dpr->rx_std_prod_idx; | |
5097 | ||
e92967bf MC |
5098 | for (i = di; i < di + cpycnt; i++) { |
5099 | if (dpr->rx_std_buffers[i].skb) { | |
5100 | cpycnt = i - di; | |
f89f38b8 | 5101 | err = -ENOSPC; |
e92967bf MC |
5102 | break; |
5103 | } | |
5104 | } | |
5105 | ||
5106 | if (!cpycnt) | |
5107 | break; | |
5108 | ||
5109 | /* Ensure that updates to the rx_std_buffers ring and the | |
5110 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5111 | * ordered correctly WRT the skb check above. | |
5112 | */ | |
5113 | smp_rmb(); | |
5114 | ||
b196c7e4 MC |
5115 | memcpy(&dpr->rx_std_buffers[di], |
5116 | &spr->rx_std_buffers[si], | |
5117 | cpycnt * sizeof(struct ring_info)); | |
5118 | ||
5119 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5120 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5121 | sbd = &spr->rx_std[si]; | |
5122 | dbd = &dpr->rx_std[di]; | |
5123 | dbd->addr_hi = sbd->addr_hi; | |
5124 | dbd->addr_lo = sbd->addr_lo; | |
5125 | } | |
5126 | ||
2c49a44d MC |
5127 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
5128 | tp->rx_std_ring_mask; | |
5129 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
5130 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5131 | } |
5132 | ||
5133 | while (1) { | |
5134 | src_prod_idx = spr->rx_jmb_prod_idx; | |
5135 | ||
5136 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
5137 | * the jumbo producer index are seen in the correct order. | |
5138 | */ | |
5139 | smp_rmb(); | |
5140 | ||
5141 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
5142 | break; | |
5143 | ||
5144 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
5145 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
5146 | else | |
2c49a44d MC |
5147 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
5148 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
5149 | |
5150 | cpycnt = min(cpycnt, | |
2c49a44d | 5151 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
5152 | |
5153 | si = spr->rx_jmb_cons_idx; | |
5154 | di = dpr->rx_jmb_prod_idx; | |
5155 | ||
e92967bf MC |
5156 | for (i = di; i < di + cpycnt; i++) { |
5157 | if (dpr->rx_jmb_buffers[i].skb) { | |
5158 | cpycnt = i - di; | |
f89f38b8 | 5159 | err = -ENOSPC; |
e92967bf MC |
5160 | break; |
5161 | } | |
5162 | } | |
5163 | ||
5164 | if (!cpycnt) | |
5165 | break; | |
5166 | ||
5167 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
5168 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5169 | * ordered correctly WRT the skb check above. | |
5170 | */ | |
5171 | smp_rmb(); | |
5172 | ||
b196c7e4 MC |
5173 | memcpy(&dpr->rx_jmb_buffers[di], |
5174 | &spr->rx_jmb_buffers[si], | |
5175 | cpycnt * sizeof(struct ring_info)); | |
5176 | ||
5177 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5178 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5179 | sbd = &spr->rx_jmb[si].std; | |
5180 | dbd = &dpr->rx_jmb[di].std; | |
5181 | dbd->addr_hi = sbd->addr_hi; | |
5182 | dbd->addr_lo = sbd->addr_lo; | |
5183 | } | |
5184 | ||
2c49a44d MC |
5185 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
5186 | tp->rx_jmb_ring_mask; | |
5187 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5188 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 5189 | } |
f89f38b8 MC |
5190 | |
5191 | return err; | |
b196c7e4 MC |
5192 | } |
5193 | ||
35f2d7d0 MC |
5194 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
5195 | { | |
5196 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
5197 | |
5198 | /* run TX completion thread */ | |
f3f3f27e | 5199 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 5200 | tg3_tx(tnapi); |
6f535763 | 5201 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) |
4fd7ab59 | 5202 | return work_done; |
1da177e4 LT |
5203 | } |
5204 | ||
1da177e4 LT |
5205 | /* run RX thread, within the bounds set by NAPI. |
5206 | * All RX "locking" is done by ensuring outside | |
bea3348e | 5207 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 5208 | */ |
8d9d7cfc | 5209 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 5210 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 5211 | |
b196c7e4 | 5212 | if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 5213 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 5214 | int i, err = 0; |
e4af1af9 MC |
5215 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
5216 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 5217 | |
e4af1af9 | 5218 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 5219 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 5220 | &tp->napi[i].prodring); |
b196c7e4 MC |
5221 | |
5222 | wmb(); | |
5223 | ||
e4af1af9 MC |
5224 | if (std_prod_idx != dpr->rx_std_prod_idx) |
5225 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5226 | dpr->rx_std_prod_idx); | |
b196c7e4 | 5227 | |
e4af1af9 MC |
5228 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
5229 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5230 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
5231 | |
5232 | mmiowb(); | |
f89f38b8 MC |
5233 | |
5234 | if (err) | |
5235 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
5236 | } |
5237 | ||
6f535763 DM |
5238 | return work_done; |
5239 | } | |
5240 | ||
35f2d7d0 MC |
5241 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5242 | { | |
5243 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5244 | struct tg3 *tp = tnapi->tp; | |
5245 | int work_done = 0; | |
5246 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5247 | ||
5248 | while (1) { | |
5249 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5250 | ||
5251 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5252 | goto tx_recovery; | |
5253 | ||
5254 | if (unlikely(work_done >= budget)) | |
5255 | break; | |
5256 | ||
c6cdf436 | 5257 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5258 | * to tell the hw how much work has been processed, |
5259 | * so we must read it before checking for more work. | |
5260 | */ | |
5261 | tnapi->last_tag = sblk->status_tag; | |
5262 | tnapi->last_irq_tag = tnapi->last_tag; | |
5263 | rmb(); | |
5264 | ||
5265 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5266 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5267 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5268 | napi_complete(napi); |
5269 | /* Reenable interrupts. */ | |
5270 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5271 | mmiowb(); | |
5272 | break; | |
5273 | } | |
5274 | } | |
5275 | ||
5276 | return work_done; | |
5277 | ||
5278 | tx_recovery: | |
5279 | /* work_done is guaranteed to be less than budget. */ | |
5280 | napi_complete(napi); | |
5281 | schedule_work(&tp->reset_task); | |
5282 | return work_done; | |
5283 | } | |
5284 | ||
e64de4e6 MC |
5285 | static void tg3_process_error(struct tg3 *tp) |
5286 | { | |
5287 | u32 val; | |
5288 | bool real_error = false; | |
5289 | ||
5290 | if (tp->tg3_flags & TG3_FLAG_ERROR_PROCESSED) | |
5291 | return; | |
5292 | ||
5293 | /* Check Flow Attention register */ | |
5294 | val = tr32(HOSTCC_FLOW_ATTN); | |
5295 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
5296 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
5297 | real_error = true; | |
5298 | } | |
5299 | ||
5300 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
5301 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
5302 | real_error = true; | |
5303 | } | |
5304 | ||
5305 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
5306 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
5307 | real_error = true; | |
5308 | } | |
5309 | ||
5310 | if (!real_error) | |
5311 | return; | |
5312 | ||
5313 | tg3_dump_state(tp); | |
5314 | ||
5315 | tp->tg3_flags |= TG3_FLAG_ERROR_PROCESSED; | |
5316 | schedule_work(&tp->reset_task); | |
5317 | } | |
5318 | ||
6f535763 DM |
5319 | static int tg3_poll(struct napi_struct *napi, int budget) |
5320 | { | |
8ef0442f MC |
5321 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
5322 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 5323 | int work_done = 0; |
898a56f8 | 5324 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
5325 | |
5326 | while (1) { | |
e64de4e6 MC |
5327 | if (sblk->status & SD_STATUS_ERROR) |
5328 | tg3_process_error(tp); | |
5329 | ||
35f2d7d0 MC |
5330 | tg3_poll_link(tp); |
5331 | ||
17375d25 | 5332 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 DM |
5333 | |
5334 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5335 | goto tx_recovery; | |
5336 | ||
5337 | if (unlikely(work_done >= budget)) | |
5338 | break; | |
5339 | ||
4fd7ab59 | 5340 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { |
17375d25 | 5341 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
5342 | * to tell the hw how much work has been processed, |
5343 | * so we must read it before checking for more work. | |
5344 | */ | |
898a56f8 MC |
5345 | tnapi->last_tag = sblk->status_tag; |
5346 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
5347 | rmb(); |
5348 | } else | |
5349 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 5350 | |
17375d25 | 5351 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 5352 | napi_complete(napi); |
17375d25 | 5353 | tg3_int_reenable(tnapi); |
6f535763 DM |
5354 | break; |
5355 | } | |
1da177e4 LT |
5356 | } |
5357 | ||
bea3348e | 5358 | return work_done; |
6f535763 DM |
5359 | |
5360 | tx_recovery: | |
4fd7ab59 | 5361 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 5362 | napi_complete(napi); |
6f535763 | 5363 | schedule_work(&tp->reset_task); |
4fd7ab59 | 5364 | return work_done; |
1da177e4 LT |
5365 | } |
5366 | ||
66cfd1bd MC |
5367 | static void tg3_napi_disable(struct tg3 *tp) |
5368 | { | |
5369 | int i; | |
5370 | ||
5371 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
5372 | napi_disable(&tp->napi[i].napi); | |
5373 | } | |
5374 | ||
5375 | static void tg3_napi_enable(struct tg3 *tp) | |
5376 | { | |
5377 | int i; | |
5378 | ||
5379 | for (i = 0; i < tp->irq_cnt; i++) | |
5380 | napi_enable(&tp->napi[i].napi); | |
5381 | } | |
5382 | ||
5383 | static void tg3_napi_init(struct tg3 *tp) | |
5384 | { | |
5385 | int i; | |
5386 | ||
5387 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
5388 | for (i = 1; i < tp->irq_cnt; i++) | |
5389 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
5390 | } | |
5391 | ||
5392 | static void tg3_napi_fini(struct tg3 *tp) | |
5393 | { | |
5394 | int i; | |
5395 | ||
5396 | for (i = 0; i < tp->irq_cnt; i++) | |
5397 | netif_napi_del(&tp->napi[i].napi); | |
5398 | } | |
5399 | ||
5400 | static inline void tg3_netif_stop(struct tg3 *tp) | |
5401 | { | |
5402 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5403 | tg3_napi_disable(tp); | |
5404 | netif_tx_disable(tp->dev); | |
5405 | } | |
5406 | ||
5407 | static inline void tg3_netif_start(struct tg3 *tp) | |
5408 | { | |
5409 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
5410 | * appropriate so long as all callers are assured to | |
5411 | * have free tx slots (such as after tg3_init_hw) | |
5412 | */ | |
5413 | netif_tx_wake_all_queues(tp->dev); | |
5414 | ||
5415 | tg3_napi_enable(tp); | |
5416 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
5417 | tg3_enable_ints(tp); | |
5418 | } | |
5419 | ||
f47c11ee DM |
5420 | static void tg3_irq_quiesce(struct tg3 *tp) |
5421 | { | |
4f125f42 MC |
5422 | int i; |
5423 | ||
f47c11ee DM |
5424 | BUG_ON(tp->irq_sync); |
5425 | ||
5426 | tp->irq_sync = 1; | |
5427 | smp_mb(); | |
5428 | ||
4f125f42 MC |
5429 | for (i = 0; i < tp->irq_cnt; i++) |
5430 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
5431 | } |
5432 | ||
f47c11ee DM |
5433 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
5434 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5435 | * with as well. Most of the time, this is not necessary except when | |
5436 | * shutting down the device. | |
5437 | */ | |
5438 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5439 | { | |
46966545 | 5440 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
5441 | if (irq_sync) |
5442 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
5443 | } |
5444 | ||
5445 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5446 | { | |
f47c11ee DM |
5447 | spin_unlock_bh(&tp->lock); |
5448 | } | |
5449 | ||
fcfa0a32 MC |
5450 | /* One-shot MSI handler - Chip automatically disables interrupt |
5451 | * after sending MSI so driver doesn't have to do it. | |
5452 | */ | |
7d12e780 | 5453 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 5454 | { |
09943a18 MC |
5455 | struct tg3_napi *tnapi = dev_id; |
5456 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 5457 | |
898a56f8 | 5458 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5459 | if (tnapi->rx_rcb) |
5460 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
5461 | |
5462 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 5463 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
5464 | |
5465 | return IRQ_HANDLED; | |
5466 | } | |
5467 | ||
88b06bc2 MC |
5468 | /* MSI ISR - No need to check for interrupt sharing and no need to |
5469 | * flush status block and interrupt mailbox. PCI ordering rules | |
5470 | * guarantee that MSI will arrive after the status block. | |
5471 | */ | |
7d12e780 | 5472 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 5473 | { |
09943a18 MC |
5474 | struct tg3_napi *tnapi = dev_id; |
5475 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 5476 | |
898a56f8 | 5477 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5478 | if (tnapi->rx_rcb) |
5479 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 5480 | /* |
fac9b83e | 5481 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 5482 | * chip-internal interrupt pending events. |
fac9b83e | 5483 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
5484 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
5485 | * event coalescing. | |
5486 | */ | |
5487 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 5488 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 5489 | napi_schedule(&tnapi->napi); |
61487480 | 5490 | |
88b06bc2 MC |
5491 | return IRQ_RETVAL(1); |
5492 | } | |
5493 | ||
7d12e780 | 5494 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 5495 | { |
09943a18 MC |
5496 | struct tg3_napi *tnapi = dev_id; |
5497 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5498 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
5499 | unsigned int handled = 1; |
5500 | ||
1da177e4 LT |
5501 | /* In INTx mode, it is possible for the interrupt to arrive at |
5502 | * the CPU before the status block posted prior to the interrupt. | |
5503 | * Reading the PCI State register will confirm whether the | |
5504 | * interrupt is ours and will flush the status block. | |
5505 | */ | |
d18edcb2 MC |
5506 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
5507 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
5508 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5509 | handled = 0; | |
f47c11ee | 5510 | goto out; |
fac9b83e | 5511 | } |
d18edcb2 MC |
5512 | } |
5513 | ||
5514 | /* | |
5515 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5516 | * chip-internal interrupt pending events. | |
5517 | * Writing non-zero to intr-mbox-0 additional tells the | |
5518 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5519 | * event coalescing. | |
c04cb347 MC |
5520 | * |
5521 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5522 | * spurious interrupts. The flush impacts performance but | |
5523 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5524 | */ |
c04cb347 | 5525 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
5526 | if (tg3_irq_sync(tp)) |
5527 | goto out; | |
5528 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 5529 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 5530 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 5531 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
5532 | } else { |
5533 | /* No work, shared interrupt perhaps? re-enable | |
5534 | * interrupts, and flush that PCI write | |
5535 | */ | |
5536 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5537 | 0x00000000); | |
fac9b83e | 5538 | } |
f47c11ee | 5539 | out: |
fac9b83e DM |
5540 | return IRQ_RETVAL(handled); |
5541 | } | |
5542 | ||
7d12e780 | 5543 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 5544 | { |
09943a18 MC |
5545 | struct tg3_napi *tnapi = dev_id; |
5546 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5547 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
5548 | unsigned int handled = 1; |
5549 | ||
fac9b83e DM |
5550 | /* In INTx mode, it is possible for the interrupt to arrive at |
5551 | * the CPU before the status block posted prior to the interrupt. | |
5552 | * Reading the PCI State register will confirm whether the | |
5553 | * interrupt is ours and will flush the status block. | |
5554 | */ | |
898a56f8 | 5555 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
d18edcb2 MC |
5556 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || |
5557 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5558 | handled = 0; | |
f47c11ee | 5559 | goto out; |
1da177e4 | 5560 | } |
d18edcb2 MC |
5561 | } |
5562 | ||
5563 | /* | |
5564 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5565 | * chip-internal interrupt pending events. | |
5566 | * writing non-zero to intr-mbox-0 additional tells the | |
5567 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5568 | * event coalescing. | |
c04cb347 MC |
5569 | * |
5570 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5571 | * spurious interrupts. The flush impacts performance but | |
5572 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5573 | */ |
c04cb347 | 5574 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
5575 | |
5576 | /* | |
5577 | * In a shared interrupt configuration, sometimes other devices' | |
5578 | * interrupts will scream. We record the current status tag here | |
5579 | * so that the above check can report that the screaming interrupts | |
5580 | * are unhandled. Eventually they will be silenced. | |
5581 | */ | |
898a56f8 | 5582 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 5583 | |
d18edcb2 MC |
5584 | if (tg3_irq_sync(tp)) |
5585 | goto out; | |
624f8e50 | 5586 | |
72334482 | 5587 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 5588 | |
09943a18 | 5589 | napi_schedule(&tnapi->napi); |
624f8e50 | 5590 | |
f47c11ee | 5591 | out: |
1da177e4 LT |
5592 | return IRQ_RETVAL(handled); |
5593 | } | |
5594 | ||
7938109f | 5595 | /* ISR for interrupt test */ |
7d12e780 | 5596 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 5597 | { |
09943a18 MC |
5598 | struct tg3_napi *tnapi = dev_id; |
5599 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5600 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 5601 | |
f9804ddb MC |
5602 | if ((sblk->status & SD_STATUS_UPDATED) || |
5603 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 5604 | tg3_disable_ints(tp); |
7938109f MC |
5605 | return IRQ_RETVAL(1); |
5606 | } | |
5607 | return IRQ_RETVAL(0); | |
5608 | } | |
5609 | ||
8e7a22e3 | 5610 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 5611 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 5612 | |
b9ec6c1b MC |
5613 | /* Restart hardware after configuration changes, self-test, etc. |
5614 | * Invoked with tp->lock held. | |
5615 | */ | |
5616 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
5617 | __releases(tp->lock) |
5618 | __acquires(tp->lock) | |
b9ec6c1b MC |
5619 | { |
5620 | int err; | |
5621 | ||
5622 | err = tg3_init_hw(tp, reset_phy); | |
5623 | if (err) { | |
5129c3a3 MC |
5624 | netdev_err(tp->dev, |
5625 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
5626 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
5627 | tg3_full_unlock(tp); | |
5628 | del_timer_sync(&tp->timer); | |
5629 | tp->irq_sync = 0; | |
fed97810 | 5630 | tg3_napi_enable(tp); |
b9ec6c1b MC |
5631 | dev_close(tp->dev); |
5632 | tg3_full_lock(tp, 0); | |
5633 | } | |
5634 | return err; | |
5635 | } | |
5636 | ||
1da177e4 LT |
5637 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5638 | static void tg3_poll_controller(struct net_device *dev) | |
5639 | { | |
4f125f42 | 5640 | int i; |
88b06bc2 MC |
5641 | struct tg3 *tp = netdev_priv(dev); |
5642 | ||
4f125f42 | 5643 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 5644 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
5645 | } |
5646 | #endif | |
5647 | ||
c4028958 | 5648 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 5649 | { |
c4028958 | 5650 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 5651 | int err; |
1da177e4 LT |
5652 | unsigned int restart_timer; |
5653 | ||
7faa006f | 5654 | tg3_full_lock(tp, 0); |
7faa006f MC |
5655 | |
5656 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
5657 | tg3_full_unlock(tp); |
5658 | return; | |
5659 | } | |
5660 | ||
5661 | tg3_full_unlock(tp); | |
5662 | ||
b02fd9e3 MC |
5663 | tg3_phy_stop(tp); |
5664 | ||
1da177e4 LT |
5665 | tg3_netif_stop(tp); |
5666 | ||
f47c11ee | 5667 | tg3_full_lock(tp, 1); |
1da177e4 LT |
5668 | |
5669 | restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; | |
5670 | tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; | |
5671 | ||
df3e6548 MC |
5672 | if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { |
5673 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
5674 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
5675 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
5676 | tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; | |
5677 | } | |
5678 | ||
944d980e | 5679 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
5680 | err = tg3_init_hw(tp, 1); |
5681 | if (err) | |
b9ec6c1b | 5682 | goto out; |
1da177e4 LT |
5683 | |
5684 | tg3_netif_start(tp); | |
5685 | ||
1da177e4 LT |
5686 | if (restart_timer) |
5687 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 5688 | |
b9ec6c1b | 5689 | out: |
7faa006f | 5690 | tg3_full_unlock(tp); |
b02fd9e3 MC |
5691 | |
5692 | if (!err) | |
5693 | tg3_phy_start(tp); | |
1da177e4 LT |
5694 | } |
5695 | ||
5696 | static void tg3_tx_timeout(struct net_device *dev) | |
5697 | { | |
5698 | struct tg3 *tp = netdev_priv(dev); | |
5699 | ||
b0408751 | 5700 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 5701 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 5702 | tg3_dump_state(tp); |
b0408751 | 5703 | } |
1da177e4 LT |
5704 | |
5705 | schedule_work(&tp->reset_task); | |
5706 | } | |
5707 | ||
c58ec932 MC |
5708 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5709 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5710 | { | |
5711 | u32 base = (u32) mapping & 0xffffffff; | |
5712 | ||
807540ba | 5713 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
5714 | } |
5715 | ||
72f2afb8 MC |
5716 | /* Test for DMA addresses > 40-bit */ |
5717 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5718 | int len) | |
5719 | { | |
5720 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
6728a8e2 | 5721 | if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) |
807540ba | 5722 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
5723 | return 0; |
5724 | #else | |
5725 | return 0; | |
5726 | #endif | |
5727 | } | |
5728 | ||
f3f3f27e | 5729 | static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32); |
1da177e4 | 5730 | |
72f2afb8 | 5731 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 MC |
5732 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
5733 | struct sk_buff *skb, u32 last_plus_one, | |
5734 | u32 *start, u32 base_flags, u32 mss) | |
1da177e4 | 5735 | { |
24f4efd4 | 5736 | struct tg3 *tp = tnapi->tp; |
41588ba1 | 5737 | struct sk_buff *new_skb; |
c58ec932 | 5738 | dma_addr_t new_addr = 0; |
1da177e4 | 5739 | u32 entry = *start; |
c58ec932 | 5740 | int i, ret = 0; |
1da177e4 | 5741 | |
41588ba1 MC |
5742 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
5743 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5744 | else { | |
5745 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5746 | ||
5747 | new_skb = skb_copy_expand(skb, | |
5748 | skb_headroom(skb) + more_headroom, | |
5749 | skb_tailroom(skb), GFP_ATOMIC); | |
5750 | } | |
5751 | ||
1da177e4 | 5752 | if (!new_skb) { |
c58ec932 MC |
5753 | ret = -1; |
5754 | } else { | |
5755 | /* New SKB is guaranteed to be linear. */ | |
5756 | entry = *start; | |
f4188d8a AD |
5757 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
5758 | PCI_DMA_TODEVICE); | |
5759 | /* Make sure the mapping succeeded */ | |
5760 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
5761 | ret = -1; | |
5762 | dev_kfree_skb(new_skb); | |
5763 | new_skb = NULL; | |
90079ce8 | 5764 | |
c58ec932 MC |
5765 | /* Make sure new skb does not cross any 4G boundaries. |
5766 | * Drop the packet if it does. | |
5767 | */ | |
f4188d8a AD |
5768 | } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5769 | tg3_4g_overflow_test(new_addr, new_skb->len)) { | |
5770 | pci_unmap_single(tp->pdev, new_addr, new_skb->len, | |
5771 | PCI_DMA_TODEVICE); | |
c58ec932 MC |
5772 | ret = -1; |
5773 | dev_kfree_skb(new_skb); | |
5774 | new_skb = NULL; | |
5775 | } else { | |
f3f3f27e | 5776 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, |
c58ec932 MC |
5777 | base_flags, 1 | (mss << 1)); |
5778 | *start = NEXT_TX(entry); | |
5779 | } | |
1da177e4 LT |
5780 | } |
5781 | ||
1da177e4 LT |
5782 | /* Now clean up the sw ring entries. */ |
5783 | i = 0; | |
5784 | while (entry != last_plus_one) { | |
f4188d8a AD |
5785 | int len; |
5786 | ||
f3f3f27e | 5787 | if (i == 0) |
f4188d8a | 5788 | len = skb_headlen(skb); |
f3f3f27e | 5789 | else |
f4188d8a AD |
5790 | len = skb_shinfo(skb)->frags[i-1].size; |
5791 | ||
5792 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 5793 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
5794 | mapping), |
5795 | len, PCI_DMA_TODEVICE); | |
5796 | if (i == 0) { | |
5797 | tnapi->tx_buffers[entry].skb = new_skb; | |
4e5e4f0d | 5798 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
5799 | new_addr); |
5800 | } else { | |
f3f3f27e | 5801 | tnapi->tx_buffers[entry].skb = NULL; |
f4188d8a | 5802 | } |
1da177e4 LT |
5803 | entry = NEXT_TX(entry); |
5804 | i++; | |
5805 | } | |
5806 | ||
5807 | dev_kfree_skb(skb); | |
5808 | ||
c58ec932 | 5809 | return ret; |
1da177e4 LT |
5810 | } |
5811 | ||
f3f3f27e | 5812 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, |
1da177e4 LT |
5813 | dma_addr_t mapping, int len, u32 flags, |
5814 | u32 mss_and_is_end) | |
5815 | { | |
f3f3f27e | 5816 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; |
1da177e4 LT |
5817 | int is_end = (mss_and_is_end & 0x1); |
5818 | u32 mss = (mss_and_is_end >> 1); | |
5819 | u32 vlan_tag = 0; | |
5820 | ||
5821 | if (is_end) | |
5822 | flags |= TXD_FLAG_END; | |
5823 | if (flags & TXD_FLAG_VLAN) { | |
5824 | vlan_tag = flags >> 16; | |
5825 | flags &= 0xffff; | |
5826 | } | |
5827 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5828 | ||
5829 | txd->addr_hi = ((u64) mapping >> 32); | |
5830 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5831 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5832 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5833 | } | |
5834 | ||
5a6f3074 | 5835 | /* hard_start_xmit for devices that don't have any bugs and |
e849cdc3 | 5836 | * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only. |
5a6f3074 | 5837 | */ |
61357325 SH |
5838 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, |
5839 | struct net_device *dev) | |
5a6f3074 MC |
5840 | { |
5841 | struct tg3 *tp = netdev_priv(dev); | |
5a6f3074 | 5842 | u32 len, entry, base_flags, mss; |
90079ce8 | 5843 | dma_addr_t mapping; |
fe5f5787 MC |
5844 | struct tg3_napi *tnapi; |
5845 | struct netdev_queue *txq; | |
f4188d8a AD |
5846 | unsigned int i, last; |
5847 | ||
fe5f5787 MC |
5848 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5849 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 5850 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 | 5851 | tnapi++; |
5a6f3074 | 5852 | |
00b70504 | 5853 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5854 | * and TX reclaim runs via tp->napi.poll inside of a software |
5a6f3074 MC |
5855 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5856 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5857 | */ | |
f3f3f27e | 5858 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
fe5f5787 MC |
5859 | if (!netif_tx_queue_stopped(txq)) { |
5860 | netif_tx_stop_queue(txq); | |
5a6f3074 MC |
5861 | |
5862 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
5863 | netdev_err(dev, |
5864 | "BUG! Tx Ring full when queue awake!\n"); | |
5a6f3074 | 5865 | } |
5a6f3074 MC |
5866 | return NETDEV_TX_BUSY; |
5867 | } | |
5868 | ||
f3f3f27e | 5869 | entry = tnapi->tx_prod; |
5a6f3074 | 5870 | base_flags = 0; |
be98da6a MC |
5871 | mss = skb_shinfo(skb)->gso_size; |
5872 | if (mss) { | |
5a6f3074 | 5873 | int tcp_opt_len, ip_tcp_len; |
f6eb9b1f | 5874 | u32 hdrlen; |
5a6f3074 MC |
5875 | |
5876 | if (skb_header_cloned(skb) && | |
5877 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5878 | dev_kfree_skb(skb); | |
5879 | goto out_unlock; | |
5880 | } | |
5881 | ||
02e96080 | 5882 | if (skb_is_gso_v6(skb)) { |
f6eb9b1f | 5883 | hdrlen = skb_headlen(skb) - ETH_HLEN; |
02e96080 | 5884 | } else { |
eddc9ec5 ACM |
5885 | struct iphdr *iph = ip_hdr(skb); |
5886 | ||
ab6a5bb6 | 5887 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5888 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
b0026624 | 5889 | |
eddc9ec5 ACM |
5890 | iph->check = 0; |
5891 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
f6eb9b1f | 5892 | hdrlen = ip_tcp_len + tcp_opt_len; |
b0026624 | 5893 | } |
5a6f3074 | 5894 | |
e849cdc3 | 5895 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
f6eb9b1f MC |
5896 | mss |= (hdrlen & 0xc) << 12; |
5897 | if (hdrlen & 0x10) | |
5898 | base_flags |= 0x00000010; | |
5899 | base_flags |= (hdrlen & 0x3e0) << 5; | |
5900 | } else | |
5901 | mss |= hdrlen << 9; | |
5902 | ||
5a6f3074 MC |
5903 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5904 | TXD_FLAG_CPU_POST_DMA); | |
5905 | ||
aa8223c7 | 5906 | tcp_hdr(skb)->check = 0; |
5a6f3074 | 5907 | |
859a5887 | 5908 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
5a6f3074 | 5909 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
859a5887 MC |
5910 | } |
5911 | ||
eab6d18d | 5912 | if (vlan_tx_tag_present(skb)) |
5a6f3074 MC |
5913 | base_flags |= (TXD_FLAG_VLAN | |
5914 | (vlan_tx_tag_get(skb) << 16)); | |
5a6f3074 | 5915 | |
f4188d8a AD |
5916 | len = skb_headlen(skb); |
5917 | ||
5918 | /* Queue skb data, a.k.a. the main skb fragment. */ | |
5919 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5920 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
5921 | dev_kfree_skb(skb); |
5922 | goto out_unlock; | |
5923 | } | |
5924 | ||
f3f3f27e | 5925 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 5926 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
fe5f5787 | 5927 | |
b703df6f | 5928 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
8fc2f995 | 5929 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
f6eb9b1f MC |
5930 | base_flags |= TXD_FLAG_JMB_PKT; |
5931 | ||
f3f3f27e | 5932 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
5a6f3074 MC |
5933 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5934 | ||
5935 | entry = NEXT_TX(entry); | |
5936 | ||
5937 | /* Now loop through additional data fragments, and queue them. */ | |
5938 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5a6f3074 MC |
5939 | last = skb_shinfo(skb)->nr_frags - 1; |
5940 | for (i = 0; i <= last; i++) { | |
5941 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5942 | ||
5943 | len = frag->size; | |
f4188d8a AD |
5944 | mapping = pci_map_page(tp->pdev, |
5945 | frag->page, | |
5946 | frag->page_offset, | |
5947 | len, PCI_DMA_TODEVICE); | |
5948 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
5949 | goto dma_error; | |
5950 | ||
f3f3f27e | 5951 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 5952 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a | 5953 | mapping); |
5a6f3074 | 5954 | |
f3f3f27e | 5955 | tg3_set_txd(tnapi, entry, mapping, len, |
5a6f3074 MC |
5956 | base_flags, (i == last) | (mss << 1)); |
5957 | ||
5958 | entry = NEXT_TX(entry); | |
5959 | } | |
5960 | } | |
5961 | ||
5962 | /* Packets are ready, update Tx producer idx local and on card. */ | |
f3f3f27e | 5963 | tw32_tx_mbox(tnapi->prodmbox, entry); |
5a6f3074 | 5964 | |
f3f3f27e MC |
5965 | tnapi->tx_prod = entry; |
5966 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
fe5f5787 | 5967 | netif_tx_stop_queue(txq); |
f65aac16 MC |
5968 | |
5969 | /* netif_tx_stop_queue() must be done before checking | |
5970 | * checking tx index in tg3_tx_avail() below, because in | |
5971 | * tg3_tx(), we update tx index before checking for | |
5972 | * netif_tx_queue_stopped(). | |
5973 | */ | |
5974 | smp_mb(); | |
f3f3f27e | 5975 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
fe5f5787 | 5976 | netif_tx_wake_queue(txq); |
5a6f3074 MC |
5977 | } |
5978 | ||
5979 | out_unlock: | |
cdd0db05 | 5980 | mmiowb(); |
5a6f3074 MC |
5981 | |
5982 | return NETDEV_TX_OK; | |
f4188d8a AD |
5983 | |
5984 | dma_error: | |
5985 | last = i; | |
5986 | entry = tnapi->tx_prod; | |
5987 | tnapi->tx_buffers[entry].skb = NULL; | |
5988 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 5989 | dma_unmap_addr(&tnapi->tx_buffers[entry], mapping), |
f4188d8a AD |
5990 | skb_headlen(skb), |
5991 | PCI_DMA_TODEVICE); | |
5992 | for (i = 0; i <= last; i++) { | |
5993 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5994 | entry = NEXT_TX(entry); | |
5995 | ||
5996 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 5997 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
5998 | mapping), |
5999 | frag->size, PCI_DMA_TODEVICE); | |
6000 | } | |
6001 | ||
6002 | dev_kfree_skb(skb); | |
6003 | return NETDEV_TX_OK; | |
5a6f3074 MC |
6004 | } |
6005 | ||
61357325 SH |
6006 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *, |
6007 | struct net_device *); | |
52c0fd83 MC |
6008 | |
6009 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
6010 | * TSO header is greater than 80 bytes. | |
6011 | */ | |
6012 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
6013 | { | |
6014 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 6015 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
6016 | |
6017 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 6018 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 6019 | netif_stop_queue(tp->dev); |
f65aac16 MC |
6020 | |
6021 | /* netif_tx_stop_queue() must be done before checking | |
6022 | * checking tx index in tg3_tx_avail() below, because in | |
6023 | * tg3_tx(), we update tx index before checking for | |
6024 | * netif_tx_queue_stopped(). | |
6025 | */ | |
6026 | smp_mb(); | |
f3f3f27e | 6027 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
6028 | return NETDEV_TX_BUSY; |
6029 | ||
6030 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
6031 | } |
6032 | ||
6033 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 6034 | if (IS_ERR(segs)) |
52c0fd83 MC |
6035 | goto tg3_tso_bug_end; |
6036 | ||
6037 | do { | |
6038 | nskb = segs; | |
6039 | segs = segs->next; | |
6040 | nskb->next = NULL; | |
6041 | tg3_start_xmit_dma_bug(nskb, tp->dev); | |
6042 | } while (segs); | |
6043 | ||
6044 | tg3_tso_bug_end: | |
6045 | dev_kfree_skb(skb); | |
6046 | ||
6047 | return NETDEV_TX_OK; | |
6048 | } | |
52c0fd83 | 6049 | |
5a6f3074 MC |
6050 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
6051 | * support TG3_FLG2_HW_TSO_1 or firmware TSO only. | |
6052 | */ | |
61357325 SH |
6053 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb, |
6054 | struct net_device *dev) | |
1da177e4 LT |
6055 | { |
6056 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 LT |
6057 | u32 len, entry, base_flags, mss; |
6058 | int would_hit_hwbug; | |
90079ce8 | 6059 | dma_addr_t mapping; |
24f4efd4 MC |
6060 | struct tg3_napi *tnapi; |
6061 | struct netdev_queue *txq; | |
f4188d8a AD |
6062 | unsigned int i, last; |
6063 | ||
24f4efd4 MC |
6064 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
6065 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 6066 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
24f4efd4 | 6067 | tnapi++; |
1da177e4 | 6068 | |
00b70504 | 6069 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 6070 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
6071 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
6072 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 6073 | */ |
f3f3f27e | 6074 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
6075 | if (!netif_tx_queue_stopped(txq)) { |
6076 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
6077 | |
6078 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
6079 | netdev_err(dev, |
6080 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 6081 | } |
1da177e4 LT |
6082 | return NETDEV_TX_BUSY; |
6083 | } | |
6084 | ||
f3f3f27e | 6085 | entry = tnapi->tx_prod; |
1da177e4 | 6086 | base_flags = 0; |
84fa7933 | 6087 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 6088 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 6089 | |
be98da6a MC |
6090 | mss = skb_shinfo(skb)->gso_size; |
6091 | if (mss) { | |
eddc9ec5 | 6092 | struct iphdr *iph; |
34195c3d | 6093 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
6094 | |
6095 | if (skb_header_cloned(skb) && | |
6096 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
6097 | dev_kfree_skb(skb); | |
6098 | goto out_unlock; | |
6099 | } | |
6100 | ||
34195c3d | 6101 | iph = ip_hdr(skb); |
ab6a5bb6 | 6102 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 6103 | |
02e96080 | 6104 | if (skb_is_gso_v6(skb)) { |
34195c3d MC |
6105 | hdr_len = skb_headlen(skb) - ETH_HLEN; |
6106 | } else { | |
6107 | u32 ip_tcp_len; | |
6108 | ||
6109 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
6110 | hdr_len = ip_tcp_len + tcp_opt_len; | |
6111 | ||
6112 | iph->check = 0; | |
6113 | iph->tot_len = htons(mss + hdr_len); | |
6114 | } | |
6115 | ||
52c0fd83 | 6116 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
7f62ad5d | 6117 | (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) |
de6f31eb | 6118 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 6119 | |
1da177e4 LT |
6120 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
6121 | TXD_FLAG_CPU_POST_DMA); | |
6122 | ||
1da177e4 | 6123 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { |
aa8223c7 | 6124 | tcp_hdr(skb)->check = 0; |
1da177e4 | 6125 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
6126 | } else |
6127 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6128 | iph->daddr, 0, | |
6129 | IPPROTO_TCP, | |
6130 | 0); | |
1da177e4 | 6131 | |
615774fe MC |
6132 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
6133 | mss |= (hdr_len & 0xc) << 12; | |
6134 | if (hdr_len & 0x10) | |
6135 | base_flags |= 0x00000010; | |
6136 | base_flags |= (hdr_len & 0x3e0) << 5; | |
6137 | } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) | |
92c6b8d1 MC |
6138 | mss |= hdr_len << 9; |
6139 | else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) || | |
6140 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
eddc9ec5 | 6141 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6142 | int tsflags; |
6143 | ||
eddc9ec5 | 6144 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6145 | mss |= (tsflags << 11); |
6146 | } | |
6147 | } else { | |
eddc9ec5 | 6148 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6149 | int tsflags; |
6150 | ||
eddc9ec5 | 6151 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6152 | base_flags |= tsflags << 12; |
6153 | } | |
6154 | } | |
6155 | } | |
bf933c80 | 6156 | |
eab6d18d | 6157 | if (vlan_tx_tag_present(skb)) |
1da177e4 LT |
6158 | base_flags |= (TXD_FLAG_VLAN | |
6159 | (vlan_tx_tag_get(skb) << 16)); | |
1da177e4 | 6160 | |
b703df6f | 6161 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
8fc2f995 | 6162 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
615774fe MC |
6163 | base_flags |= TXD_FLAG_JMB_PKT; |
6164 | ||
f4188d8a AD |
6165 | len = skb_headlen(skb); |
6166 | ||
6167 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
6168 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
6169 | dev_kfree_skb(skb); |
6170 | goto out_unlock; | |
6171 | } | |
6172 | ||
f3f3f27e | 6173 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 6174 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
6175 | |
6176 | would_hit_hwbug = 0; | |
6177 | ||
92c6b8d1 MC |
6178 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8) |
6179 | would_hit_hwbug = 1; | |
6180 | ||
0e1406dd MC |
6181 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
6182 | tg3_4g_overflow_test(mapping, len)) | |
6183 | would_hit_hwbug = 1; | |
6184 | ||
6185 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && | |
6186 | tg3_40bit_overflow_test(tp, mapping, len)) | |
41588ba1 | 6187 | would_hit_hwbug = 1; |
0e1406dd MC |
6188 | |
6189 | if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) | |
c58ec932 | 6190 | would_hit_hwbug = 1; |
1da177e4 | 6191 | |
f3f3f27e | 6192 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
1da177e4 LT |
6193 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
6194 | ||
6195 | entry = NEXT_TX(entry); | |
6196 | ||
6197 | /* Now loop through additional data fragments, and queue them. */ | |
6198 | if (skb_shinfo(skb)->nr_frags > 0) { | |
1da177e4 LT |
6199 | last = skb_shinfo(skb)->nr_frags - 1; |
6200 | for (i = 0; i <= last; i++) { | |
6201 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6202 | ||
6203 | len = frag->size; | |
f4188d8a AD |
6204 | mapping = pci_map_page(tp->pdev, |
6205 | frag->page, | |
6206 | frag->page_offset, | |
6207 | len, PCI_DMA_TODEVICE); | |
1da177e4 | 6208 | |
f3f3f27e | 6209 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6210 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
6211 | mapping); |
6212 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
6213 | goto dma_error; | |
1da177e4 | 6214 | |
92c6b8d1 MC |
6215 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && |
6216 | len <= 8) | |
6217 | would_hit_hwbug = 1; | |
6218 | ||
0e1406dd MC |
6219 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
6220 | tg3_4g_overflow_test(mapping, len)) | |
c58ec932 | 6221 | would_hit_hwbug = 1; |
1da177e4 | 6222 | |
0e1406dd MC |
6223 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && |
6224 | tg3_40bit_overflow_test(tp, mapping, len)) | |
72f2afb8 MC |
6225 | would_hit_hwbug = 1; |
6226 | ||
1da177e4 | 6227 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
f3f3f27e | 6228 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6229 | base_flags, (i == last)|(mss << 1)); |
6230 | else | |
f3f3f27e | 6231 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6232 | base_flags, (i == last)); |
6233 | ||
6234 | entry = NEXT_TX(entry); | |
6235 | } | |
6236 | } | |
6237 | ||
6238 | if (would_hit_hwbug) { | |
6239 | u32 last_plus_one = entry; | |
6240 | u32 start; | |
1da177e4 | 6241 | |
c58ec932 MC |
6242 | start = entry - 1 - skb_shinfo(skb)->nr_frags; |
6243 | start &= (TG3_TX_RING_SIZE - 1); | |
1da177e4 LT |
6244 | |
6245 | /* If the workaround fails due to memory/mapping | |
6246 | * failure, silently drop this packet. | |
6247 | */ | |
24f4efd4 | 6248 | if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one, |
c58ec932 | 6249 | &start, base_flags, mss)) |
1da177e4 LT |
6250 | goto out_unlock; |
6251 | ||
6252 | entry = start; | |
6253 | } | |
6254 | ||
6255 | /* Packets are ready, update Tx producer idx local and on card. */ | |
24f4efd4 | 6256 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 6257 | |
f3f3f27e MC |
6258 | tnapi->tx_prod = entry; |
6259 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 6260 | netif_tx_stop_queue(txq); |
f65aac16 MC |
6261 | |
6262 | /* netif_tx_stop_queue() must be done before checking | |
6263 | * checking tx index in tg3_tx_avail() below, because in | |
6264 | * tg3_tx(), we update tx index before checking for | |
6265 | * netif_tx_queue_stopped(). | |
6266 | */ | |
6267 | smp_mb(); | |
f3f3f27e | 6268 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 6269 | netif_tx_wake_queue(txq); |
51b91468 | 6270 | } |
1da177e4 LT |
6271 | |
6272 | out_unlock: | |
cdd0db05 | 6273 | mmiowb(); |
1da177e4 LT |
6274 | |
6275 | return NETDEV_TX_OK; | |
f4188d8a AD |
6276 | |
6277 | dma_error: | |
6278 | last = i; | |
6279 | entry = tnapi->tx_prod; | |
6280 | tnapi->tx_buffers[entry].skb = NULL; | |
6281 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 6282 | dma_unmap_addr(&tnapi->tx_buffers[entry], mapping), |
f4188d8a AD |
6283 | skb_headlen(skb), |
6284 | PCI_DMA_TODEVICE); | |
6285 | for (i = 0; i <= last; i++) { | |
6286 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6287 | entry = NEXT_TX(entry); | |
6288 | ||
6289 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6290 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
6291 | mapping), |
6292 | frag->size, PCI_DMA_TODEVICE); | |
6293 | } | |
6294 | ||
6295 | dev_kfree_skb(skb); | |
6296 | return NETDEV_TX_OK; | |
1da177e4 LT |
6297 | } |
6298 | ||
dc668910 MM |
6299 | static u32 tg3_fix_features(struct net_device *dev, u32 features) |
6300 | { | |
6301 | struct tg3 *tp = netdev_priv(dev); | |
6302 | ||
6303 | if (dev->mtu > ETH_DATA_LEN && (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
6304 | features &= ~NETIF_F_ALL_TSO; | |
6305 | ||
6306 | return features; | |
6307 | } | |
6308 | ||
1da177e4 LT |
6309 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
6310 | int new_mtu) | |
6311 | { | |
6312 | dev->mtu = new_mtu; | |
6313 | ||
ef7f5ec0 | 6314 | if (new_mtu > ETH_DATA_LEN) { |
a4e2b347 | 6315 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { |
dc668910 | 6316 | netdev_update_features(dev); |
ef7f5ec0 | 6317 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
859a5887 | 6318 | } else { |
ef7f5ec0 | 6319 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
859a5887 | 6320 | } |
ef7f5ec0 | 6321 | } else { |
dc668910 | 6322 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { |
ef7f5ec0 | 6323 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
dc668910 MM |
6324 | netdev_update_features(dev); |
6325 | } | |
0f893dc6 | 6326 | tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; |
ef7f5ec0 | 6327 | } |
1da177e4 LT |
6328 | } |
6329 | ||
6330 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
6331 | { | |
6332 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 6333 | int err; |
1da177e4 LT |
6334 | |
6335 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
6336 | return -EINVAL; | |
6337 | ||
6338 | if (!netif_running(dev)) { | |
6339 | /* We'll just catch it later when the | |
6340 | * device is up'd. | |
6341 | */ | |
6342 | tg3_set_mtu(dev, tp, new_mtu); | |
6343 | return 0; | |
6344 | } | |
6345 | ||
b02fd9e3 MC |
6346 | tg3_phy_stop(tp); |
6347 | ||
1da177e4 | 6348 | tg3_netif_stop(tp); |
f47c11ee DM |
6349 | |
6350 | tg3_full_lock(tp, 1); | |
1da177e4 | 6351 | |
944d980e | 6352 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
6353 | |
6354 | tg3_set_mtu(dev, tp, new_mtu); | |
6355 | ||
b9ec6c1b | 6356 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 6357 | |
b9ec6c1b MC |
6358 | if (!err) |
6359 | tg3_netif_start(tp); | |
1da177e4 | 6360 | |
f47c11ee | 6361 | tg3_full_unlock(tp); |
1da177e4 | 6362 | |
b02fd9e3 MC |
6363 | if (!err) |
6364 | tg3_phy_start(tp); | |
6365 | ||
b9ec6c1b | 6366 | return err; |
1da177e4 LT |
6367 | } |
6368 | ||
21f581a5 MC |
6369 | static void tg3_rx_prodring_free(struct tg3 *tp, |
6370 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6371 | { |
1da177e4 LT |
6372 | int i; |
6373 | ||
8fea32b9 | 6374 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 6375 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 6376 | i = (i + 1) & tp->rx_std_ring_mask) |
b196c7e4 MC |
6377 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6378 | tp->rx_pkt_map_sz); | |
6379 | ||
6380 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
6381 | for (i = tpr->rx_jmb_cons_idx; | |
6382 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 6383 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
b196c7e4 MC |
6384 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6385 | TG3_RX_JMB_MAP_SZ); | |
6386 | } | |
6387 | } | |
6388 | ||
2b2cdb65 | 6389 | return; |
b196c7e4 | 6390 | } |
1da177e4 | 6391 | |
2c49a44d | 6392 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
2b2cdb65 MC |
6393 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6394 | tp->rx_pkt_map_sz); | |
1da177e4 | 6395 | |
48035728 MC |
6396 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
6397 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
2c49a44d | 6398 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
2b2cdb65 MC |
6399 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6400 | TG3_RX_JMB_MAP_SZ); | |
1da177e4 LT |
6401 | } |
6402 | } | |
6403 | ||
c6cdf436 | 6404 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
6405 | * |
6406 | * The chip has been shut down and the driver detached from | |
6407 | * the networking, so no interrupts or new tx packets will | |
6408 | * end up in the driver. tp->{tx,}lock are held and thus | |
6409 | * we may not sleep. | |
6410 | */ | |
21f581a5 MC |
6411 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
6412 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6413 | { |
287be12e | 6414 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 6415 | |
b196c7e4 MC |
6416 | tpr->rx_std_cons_idx = 0; |
6417 | tpr->rx_std_prod_idx = 0; | |
6418 | tpr->rx_jmb_cons_idx = 0; | |
6419 | tpr->rx_jmb_prod_idx = 0; | |
6420 | ||
8fea32b9 | 6421 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
6422 | memset(&tpr->rx_std_buffers[0], 0, |
6423 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 6424 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 6425 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 6426 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
6427 | goto done; |
6428 | } | |
6429 | ||
1da177e4 | 6430 | /* Zero out all descriptors. */ |
2c49a44d | 6431 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 6432 | |
287be12e | 6433 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
a4e2b347 | 6434 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && |
287be12e MC |
6435 | tp->dev->mtu > ETH_DATA_LEN) |
6436 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6437 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 6438 | |
1da177e4 LT |
6439 | /* Initialize invariants of the rings, we only set this |
6440 | * stuff once. This works because the card does not | |
6441 | * write into the rx buffer posting rings. | |
6442 | */ | |
2c49a44d | 6443 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
6444 | struct tg3_rx_buffer_desc *rxd; |
6445 | ||
21f581a5 | 6446 | rxd = &tpr->rx_std[i]; |
287be12e | 6447 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
6448 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
6449 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6450 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6451 | } | |
6452 | ||
1da177e4 LT |
6453 | /* Now allocate fresh SKBs for each rx ring. */ |
6454 | for (i = 0; i < tp->rx_pending; i++) { | |
86b21e59 | 6455 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
6456 | netdev_warn(tp->dev, |
6457 | "Using a smaller RX standard ring. Only " | |
6458 | "%d out of %d buffers were allocated " | |
6459 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 6460 | if (i == 0) |
cf7a7298 | 6461 | goto initfail; |
32d8c572 | 6462 | tp->rx_pending = i; |
1da177e4 | 6463 | break; |
32d8c572 | 6464 | } |
1da177e4 LT |
6465 | } |
6466 | ||
48035728 MC |
6467 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) || |
6468 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
cf7a7298 MC |
6469 | goto done; |
6470 | ||
2c49a44d | 6471 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 6472 | |
0d86df80 MC |
6473 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)) |
6474 | goto done; | |
cf7a7298 | 6475 | |
2c49a44d | 6476 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
6477 | struct tg3_rx_buffer_desc *rxd; |
6478 | ||
6479 | rxd = &tpr->rx_jmb[i].std; | |
6480 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6481 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6482 | RXD_FLAG_JUMBO; | |
6483 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6484 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6485 | } | |
6486 | ||
6487 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6488 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
5129c3a3 MC |
6489 | netdev_warn(tp->dev, |
6490 | "Using a smaller RX jumbo ring. Only %d " | |
6491 | "out of %d buffers were allocated " | |
6492 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
6493 | if (i == 0) |
6494 | goto initfail; | |
6495 | tp->rx_jumbo_pending = i; | |
6496 | break; | |
1da177e4 LT |
6497 | } |
6498 | } | |
cf7a7298 MC |
6499 | |
6500 | done: | |
32d8c572 | 6501 | return 0; |
cf7a7298 MC |
6502 | |
6503 | initfail: | |
21f581a5 | 6504 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 6505 | return -ENOMEM; |
1da177e4 LT |
6506 | } |
6507 | ||
21f581a5 MC |
6508 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
6509 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6510 | { |
21f581a5 MC |
6511 | kfree(tpr->rx_std_buffers); |
6512 | tpr->rx_std_buffers = NULL; | |
6513 | kfree(tpr->rx_jmb_buffers); | |
6514 | tpr->rx_jmb_buffers = NULL; | |
6515 | if (tpr->rx_std) { | |
4bae65c8 MC |
6516 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
6517 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 6518 | tpr->rx_std = NULL; |
1da177e4 | 6519 | } |
21f581a5 | 6520 | if (tpr->rx_jmb) { |
4bae65c8 MC |
6521 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
6522 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 6523 | tpr->rx_jmb = NULL; |
1da177e4 | 6524 | } |
cf7a7298 MC |
6525 | } |
6526 | ||
21f581a5 MC |
6527 | static int tg3_rx_prodring_init(struct tg3 *tp, |
6528 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 6529 | { |
2c49a44d MC |
6530 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
6531 | GFP_KERNEL); | |
21f581a5 | 6532 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
6533 | return -ENOMEM; |
6534 | ||
4bae65c8 MC |
6535 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
6536 | TG3_RX_STD_RING_BYTES(tp), | |
6537 | &tpr->rx_std_mapping, | |
6538 | GFP_KERNEL); | |
21f581a5 | 6539 | if (!tpr->rx_std) |
cf7a7298 MC |
6540 | goto err_out; |
6541 | ||
48035728 MC |
6542 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
6543 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
2c49a44d | 6544 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
6545 | GFP_KERNEL); |
6546 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
6547 | goto err_out; |
6548 | ||
4bae65c8 MC |
6549 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
6550 | TG3_RX_JMB_RING_BYTES(tp), | |
6551 | &tpr->rx_jmb_mapping, | |
6552 | GFP_KERNEL); | |
21f581a5 | 6553 | if (!tpr->rx_jmb) |
cf7a7298 MC |
6554 | goto err_out; |
6555 | } | |
6556 | ||
6557 | return 0; | |
6558 | ||
6559 | err_out: | |
21f581a5 | 6560 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
6561 | return -ENOMEM; |
6562 | } | |
6563 | ||
6564 | /* Free up pending packets in all rx/tx rings. | |
6565 | * | |
6566 | * The chip has been shut down and the driver detached from | |
6567 | * the networking, so no interrupts or new tx packets will | |
6568 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6569 | * in an interrupt context and thus may sleep. | |
6570 | */ | |
6571 | static void tg3_free_rings(struct tg3 *tp) | |
6572 | { | |
f77a6a8e | 6573 | int i, j; |
cf7a7298 | 6574 | |
f77a6a8e MC |
6575 | for (j = 0; j < tp->irq_cnt; j++) { |
6576 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 6577 | |
8fea32b9 | 6578 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 6579 | |
0c1d0e2b MC |
6580 | if (!tnapi->tx_buffers) |
6581 | continue; | |
6582 | ||
f77a6a8e | 6583 | for (i = 0; i < TG3_TX_RING_SIZE; ) { |
f4188d8a | 6584 | struct ring_info *txp; |
f77a6a8e | 6585 | struct sk_buff *skb; |
f4188d8a | 6586 | unsigned int k; |
cf7a7298 | 6587 | |
f77a6a8e MC |
6588 | txp = &tnapi->tx_buffers[i]; |
6589 | skb = txp->skb; | |
cf7a7298 | 6590 | |
f77a6a8e MC |
6591 | if (skb == NULL) { |
6592 | i++; | |
6593 | continue; | |
6594 | } | |
cf7a7298 | 6595 | |
f4188d8a | 6596 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 6597 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6598 | skb_headlen(skb), |
6599 | PCI_DMA_TODEVICE); | |
f77a6a8e | 6600 | txp->skb = NULL; |
cf7a7298 | 6601 | |
f4188d8a AD |
6602 | i++; |
6603 | ||
6604 | for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { | |
6605 | txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; | |
6606 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6607 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6608 | skb_shinfo(skb)->frags[k].size, |
6609 | PCI_DMA_TODEVICE); | |
6610 | i++; | |
6611 | } | |
f77a6a8e MC |
6612 | |
6613 | dev_kfree_skb_any(skb); | |
6614 | } | |
2b2cdb65 | 6615 | } |
cf7a7298 MC |
6616 | } |
6617 | ||
6618 | /* Initialize tx/rx rings for packet processing. | |
6619 | * | |
6620 | * The chip has been shut down and the driver detached from | |
6621 | * the networking, so no interrupts or new tx packets will | |
6622 | * end up in the driver. tp->{tx,}lock are held and thus | |
6623 | * we may not sleep. | |
6624 | */ | |
6625 | static int tg3_init_rings(struct tg3 *tp) | |
6626 | { | |
f77a6a8e | 6627 | int i; |
72334482 | 6628 | |
cf7a7298 MC |
6629 | /* Free up all the SKBs. */ |
6630 | tg3_free_rings(tp); | |
6631 | ||
f77a6a8e MC |
6632 | for (i = 0; i < tp->irq_cnt; i++) { |
6633 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6634 | ||
6635 | tnapi->last_tag = 0; | |
6636 | tnapi->last_irq_tag = 0; | |
6637 | tnapi->hw_status->status = 0; | |
6638 | tnapi->hw_status->status_tag = 0; | |
6639 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 6640 | |
f77a6a8e MC |
6641 | tnapi->tx_prod = 0; |
6642 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
6643 | if (tnapi->tx_ring) |
6644 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
6645 | |
6646 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
6647 | if (tnapi->rx_rcb) |
6648 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 6649 | |
8fea32b9 | 6650 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 6651 | tg3_free_rings(tp); |
2b2cdb65 | 6652 | return -ENOMEM; |
e4af1af9 | 6653 | } |
f77a6a8e | 6654 | } |
72334482 | 6655 | |
2b2cdb65 | 6656 | return 0; |
cf7a7298 MC |
6657 | } |
6658 | ||
6659 | /* | |
6660 | * Must not be invoked with interrupt sources disabled and | |
6661 | * the hardware shutdown down. | |
6662 | */ | |
6663 | static void tg3_free_consistent(struct tg3 *tp) | |
6664 | { | |
f77a6a8e | 6665 | int i; |
898a56f8 | 6666 | |
f77a6a8e MC |
6667 | for (i = 0; i < tp->irq_cnt; i++) { |
6668 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6669 | ||
6670 | if (tnapi->tx_ring) { | |
4bae65c8 | 6671 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
6672 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
6673 | tnapi->tx_ring = NULL; | |
6674 | } | |
6675 | ||
6676 | kfree(tnapi->tx_buffers); | |
6677 | tnapi->tx_buffers = NULL; | |
6678 | ||
6679 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
6680 | dma_free_coherent(&tp->pdev->dev, |
6681 | TG3_RX_RCB_RING_BYTES(tp), | |
6682 | tnapi->rx_rcb, | |
6683 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
6684 | tnapi->rx_rcb = NULL; |
6685 | } | |
6686 | ||
8fea32b9 MC |
6687 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
6688 | ||
f77a6a8e | 6689 | if (tnapi->hw_status) { |
4bae65c8 MC |
6690 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
6691 | tnapi->hw_status, | |
6692 | tnapi->status_mapping); | |
f77a6a8e MC |
6693 | tnapi->hw_status = NULL; |
6694 | } | |
1da177e4 | 6695 | } |
f77a6a8e | 6696 | |
1da177e4 | 6697 | if (tp->hw_stats) { |
4bae65c8 MC |
6698 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
6699 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
6700 | tp->hw_stats = NULL; |
6701 | } | |
6702 | } | |
6703 | ||
6704 | /* | |
6705 | * Must not be invoked with interrupt sources disabled and | |
6706 | * the hardware shutdown down. Can sleep. | |
6707 | */ | |
6708 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6709 | { | |
f77a6a8e | 6710 | int i; |
898a56f8 | 6711 | |
4bae65c8 MC |
6712 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
6713 | sizeof(struct tg3_hw_stats), | |
6714 | &tp->stats_mapping, | |
6715 | GFP_KERNEL); | |
f77a6a8e | 6716 | if (!tp->hw_stats) |
1da177e4 LT |
6717 | goto err_out; |
6718 | ||
f77a6a8e | 6719 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 6720 | |
f77a6a8e MC |
6721 | for (i = 0; i < tp->irq_cnt; i++) { |
6722 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 6723 | struct tg3_hw_status *sblk; |
1da177e4 | 6724 | |
4bae65c8 MC |
6725 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
6726 | TG3_HW_STATUS_SIZE, | |
6727 | &tnapi->status_mapping, | |
6728 | GFP_KERNEL); | |
f77a6a8e MC |
6729 | if (!tnapi->hw_status) |
6730 | goto err_out; | |
898a56f8 | 6731 | |
f77a6a8e | 6732 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
6733 | sblk = tnapi->hw_status; |
6734 | ||
8fea32b9 MC |
6735 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
6736 | goto err_out; | |
6737 | ||
19cfaecc MC |
6738 | /* If multivector TSS is enabled, vector 0 does not handle |
6739 | * tx interrupts. Don't allocate any resources for it. | |
6740 | */ | |
6741 | if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) || | |
6742 | (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) { | |
6743 | tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * | |
6744 | TG3_TX_RING_SIZE, | |
6745 | GFP_KERNEL); | |
6746 | if (!tnapi->tx_buffers) | |
6747 | goto err_out; | |
6748 | ||
4bae65c8 MC |
6749 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
6750 | TG3_TX_RING_BYTES, | |
6751 | &tnapi->tx_desc_mapping, | |
6752 | GFP_KERNEL); | |
19cfaecc MC |
6753 | if (!tnapi->tx_ring) |
6754 | goto err_out; | |
6755 | } | |
6756 | ||
8d9d7cfc MC |
6757 | /* |
6758 | * When RSS is enabled, the status block format changes | |
6759 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6760 | * and "rx_mini_consumer" members get mapped to the | |
6761 | * other three rx return ring producer indexes. | |
6762 | */ | |
6763 | switch (i) { | |
6764 | default: | |
6765 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6766 | break; | |
6767 | case 2: | |
6768 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6769 | break; | |
6770 | case 3: | |
6771 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6772 | break; | |
6773 | case 4: | |
6774 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6775 | break; | |
6776 | } | |
72334482 | 6777 | |
0c1d0e2b MC |
6778 | /* |
6779 | * If multivector RSS is enabled, vector 0 does not handle | |
6780 | * rx or tx interrupts. Don't allocate any resources for it. | |
6781 | */ | |
6782 | if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) | |
6783 | continue; | |
6784 | ||
4bae65c8 MC |
6785 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
6786 | TG3_RX_RCB_RING_BYTES(tp), | |
6787 | &tnapi->rx_rcb_mapping, | |
6788 | GFP_KERNEL); | |
f77a6a8e MC |
6789 | if (!tnapi->rx_rcb) |
6790 | goto err_out; | |
72334482 | 6791 | |
f77a6a8e | 6792 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 6793 | } |
1da177e4 LT |
6794 | |
6795 | return 0; | |
6796 | ||
6797 | err_out: | |
6798 | tg3_free_consistent(tp); | |
6799 | return -ENOMEM; | |
6800 | } | |
6801 | ||
6802 | #define MAX_WAIT_CNT 1000 | |
6803 | ||
6804 | /* To stop a block, clear the enable bit and poll till it | |
6805 | * clears. tp->lock is held. | |
6806 | */ | |
b3b7d6be | 6807 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
6808 | { |
6809 | unsigned int i; | |
6810 | u32 val; | |
6811 | ||
6812 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
6813 | switch (ofs) { | |
6814 | case RCVLSC_MODE: | |
6815 | case DMAC_MODE: | |
6816 | case MBFREE_MODE: | |
6817 | case BUFMGR_MODE: | |
6818 | case MEMARB_MODE: | |
6819 | /* We can't enable/disable these bits of the | |
6820 | * 5705/5750, just say success. | |
6821 | */ | |
6822 | return 0; | |
6823 | ||
6824 | default: | |
6825 | break; | |
855e1111 | 6826 | } |
1da177e4 LT |
6827 | } |
6828 | ||
6829 | val = tr32(ofs); | |
6830 | val &= ~enable_bit; | |
6831 | tw32_f(ofs, val); | |
6832 | ||
6833 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6834 | udelay(100); | |
6835 | val = tr32(ofs); | |
6836 | if ((val & enable_bit) == 0) | |
6837 | break; | |
6838 | } | |
6839 | ||
b3b7d6be | 6840 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
6841 | dev_err(&tp->pdev->dev, |
6842 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
6843 | ofs, enable_bit); | |
1da177e4 LT |
6844 | return -ENODEV; |
6845 | } | |
6846 | ||
6847 | return 0; | |
6848 | } | |
6849 | ||
6850 | /* tp->lock is held. */ | |
b3b7d6be | 6851 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
6852 | { |
6853 | int i, err; | |
6854 | ||
6855 | tg3_disable_ints(tp); | |
6856 | ||
6857 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6858 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6859 | udelay(10); | |
6860 | ||
b3b7d6be DM |
6861 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
6862 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6863 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6864 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6865 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6866 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6867 | ||
6868 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6869 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6870 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6871 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6872 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6873 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6874 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
6875 | |
6876 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6877 | tw32_f(MAC_MODE, tp->mac_mode); | |
6878 | udelay(40); | |
6879 | ||
6880 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6881 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6882 | ||
6883 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6884 | udelay(100); | |
6885 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6886 | break; | |
6887 | } | |
6888 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
6889 | dev_err(&tp->pdev->dev, |
6890 | "%s timed out, TX_MODE_ENABLE will not clear " | |
6891 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 6892 | err |= -ENODEV; |
1da177e4 LT |
6893 | } |
6894 | ||
e6de8ad1 | 6895 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
6896 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
6897 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
6898 | |
6899 | tw32(FTQ_RESET, 0xffffffff); | |
6900 | tw32(FTQ_RESET, 0x00000000); | |
6901 | ||
b3b7d6be DM |
6902 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
6903 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 6904 | |
f77a6a8e MC |
6905 | for (i = 0; i < tp->irq_cnt; i++) { |
6906 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6907 | if (tnapi->hw_status) | |
6908 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6909 | } | |
1da177e4 LT |
6910 | if (tp->hw_stats) |
6911 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6912 | ||
1da177e4 LT |
6913 | return err; |
6914 | } | |
6915 | ||
0d3031d9 MC |
6916 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
6917 | { | |
6918 | int i; | |
6919 | u32 apedata; | |
6920 | ||
dc6d0744 MC |
6921 | /* NCSI does not support APE events */ |
6922 | if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI) | |
6923 | return; | |
6924 | ||
0d3031d9 MC |
6925 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); |
6926 | if (apedata != APE_SEG_SIG_MAGIC) | |
6927 | return; | |
6928 | ||
6929 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 6930 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
6931 | return; |
6932 | ||
6933 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6934 | for (i = 0; i < 10; i++) { | |
6935 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6936 | return; | |
6937 | ||
6938 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6939 | ||
6940 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6941 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6942 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6943 | ||
6944 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6945 | ||
6946 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6947 | break; | |
6948 | ||
6949 | udelay(100); | |
6950 | } | |
6951 | ||
6952 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6953 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6954 | } | |
6955 | ||
6956 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6957 | { | |
6958 | u32 event; | |
6959 | u32 apedata; | |
6960 | ||
6961 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
6962 | return; | |
6963 | ||
6964 | switch (kind) { | |
33f401ae MC |
6965 | case RESET_KIND_INIT: |
6966 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6967 | APE_HOST_SEG_SIG_MAGIC); | |
6968 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6969 | APE_HOST_SEG_LEN_MAGIC); | |
6970 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6971 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6972 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6867c843 | 6973 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); |
33f401ae MC |
6974 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, |
6975 | APE_HOST_BEHAV_NO_PHYLOCK); | |
dc6d0744 MC |
6976 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, |
6977 | TG3_APE_HOST_DRVR_STATE_START); | |
33f401ae MC |
6978 | |
6979 | event = APE_EVENT_STATUS_STATE_START; | |
6980 | break; | |
6981 | case RESET_KIND_SHUTDOWN: | |
6982 | /* With the interface we are currently using, | |
6983 | * APE does not track driver state. Wiping | |
6984 | * out the HOST SEGMENT SIGNATURE forces | |
6985 | * the APE to assume OS absent status. | |
6986 | */ | |
6987 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
b2aee154 | 6988 | |
dc6d0744 MC |
6989 | if (device_may_wakeup(&tp->pdev->dev) && |
6990 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) { | |
6991 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
6992 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
6993 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
6994 | } else | |
6995 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
6996 | ||
6997 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
6998 | ||
33f401ae MC |
6999 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
7000 | break; | |
7001 | case RESET_KIND_SUSPEND: | |
7002 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
7003 | break; | |
7004 | default: | |
7005 | return; | |
0d3031d9 MC |
7006 | } |
7007 | ||
7008 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
7009 | ||
7010 | tg3_ape_send_event(tp, event); | |
7011 | } | |
7012 | ||
1da177e4 LT |
7013 | /* tp->lock is held. */ |
7014 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
7015 | { | |
f49639e6 DM |
7016 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
7017 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 LT |
7018 | |
7019 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
7020 | switch (kind) { | |
7021 | case RESET_KIND_INIT: | |
7022 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7023 | DRV_STATE_START); | |
7024 | break; | |
7025 | ||
7026 | case RESET_KIND_SHUTDOWN: | |
7027 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7028 | DRV_STATE_UNLOAD); | |
7029 | break; | |
7030 | ||
7031 | case RESET_KIND_SUSPEND: | |
7032 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7033 | DRV_STATE_SUSPEND); | |
7034 | break; | |
7035 | ||
7036 | default: | |
7037 | break; | |
855e1111 | 7038 | } |
1da177e4 | 7039 | } |
0d3031d9 MC |
7040 | |
7041 | if (kind == RESET_KIND_INIT || | |
7042 | kind == RESET_KIND_SUSPEND) | |
7043 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
7044 | } |
7045 | ||
7046 | /* tp->lock is held. */ | |
7047 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
7048 | { | |
7049 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
7050 | switch (kind) { | |
7051 | case RESET_KIND_INIT: | |
7052 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7053 | DRV_STATE_START_DONE); | |
7054 | break; | |
7055 | ||
7056 | case RESET_KIND_SHUTDOWN: | |
7057 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7058 | DRV_STATE_UNLOAD_DONE); | |
7059 | break; | |
7060 | ||
7061 | default: | |
7062 | break; | |
855e1111 | 7063 | } |
1da177e4 | 7064 | } |
0d3031d9 MC |
7065 | |
7066 | if (kind == RESET_KIND_SHUTDOWN) | |
7067 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
7068 | } |
7069 | ||
7070 | /* tp->lock is held. */ | |
7071 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
7072 | { | |
7073 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
7074 | switch (kind) { | |
7075 | case RESET_KIND_INIT: | |
7076 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7077 | DRV_STATE_START); | |
7078 | break; | |
7079 | ||
7080 | case RESET_KIND_SHUTDOWN: | |
7081 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7082 | DRV_STATE_UNLOAD); | |
7083 | break; | |
7084 | ||
7085 | case RESET_KIND_SUSPEND: | |
7086 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7087 | DRV_STATE_SUSPEND); | |
7088 | break; | |
7089 | ||
7090 | default: | |
7091 | break; | |
855e1111 | 7092 | } |
1da177e4 LT |
7093 | } |
7094 | } | |
7095 | ||
7a6f4369 MC |
7096 | static int tg3_poll_fw(struct tg3 *tp) |
7097 | { | |
7098 | int i; | |
7099 | u32 val; | |
7100 | ||
b5d3772c | 7101 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
7102 | /* Wait up to 20ms for init done. */ |
7103 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
7104 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
7105 | return 0; | |
0ccead18 | 7106 | udelay(100); |
b5d3772c MC |
7107 | } |
7108 | return -ENODEV; | |
7109 | } | |
7110 | ||
7a6f4369 MC |
7111 | /* Wait for firmware initialization to complete. */ |
7112 | for (i = 0; i < 100000; i++) { | |
7113 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
7114 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
7115 | break; | |
7116 | udelay(10); | |
7117 | } | |
7118 | ||
7119 | /* Chip might not be fitted with firmware. Some Sun onboard | |
7120 | * parts are configured like that. So don't signal the timeout | |
7121 | * of the above loop as an error, but do report the lack of | |
7122 | * running firmware once. | |
7123 | */ | |
7124 | if (i >= 100000 && | |
7125 | !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { | |
7126 | tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED; | |
7127 | ||
05dbe005 | 7128 | netdev_info(tp->dev, "No firmware running\n"); |
7a6f4369 MC |
7129 | } |
7130 | ||
6b10c165 MC |
7131 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
7132 | /* The 57765 A0 needs a little more | |
7133 | * time to do some important work. | |
7134 | */ | |
7135 | mdelay(10); | |
7136 | } | |
7137 | ||
7a6f4369 MC |
7138 | return 0; |
7139 | } | |
7140 | ||
ee6a99b5 MC |
7141 | /* Save PCI command register before chip reset */ |
7142 | static void tg3_save_pci_state(struct tg3 *tp) | |
7143 | { | |
8a6eac90 | 7144 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
7145 | } |
7146 | ||
7147 | /* Restore PCI state after chip reset */ | |
7148 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7149 | { | |
7150 | u32 val; | |
7151 | ||
7152 | /* Re-enable indirect register accesses. */ | |
7153 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7154 | tp->misc_host_ctrl); | |
7155 | ||
7156 | /* Set MAX PCI retry to zero. */ | |
7157 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7158 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
7159 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) | |
7160 | val |= PCISTATE_RETRY_SAME_DMA; | |
0d3031d9 MC |
7161 | /* Allow reads and writes to the APE register and memory space. */ |
7162 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
7163 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
7164 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7165 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
7166 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
7167 | ||
8a6eac90 | 7168 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 7169 | |
fcb389df MC |
7170 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
7171 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
cf79003d | 7172 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
fcb389df MC |
7173 | else { |
7174 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7175 | tp->pci_cacheline_sz); | |
7176 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7177 | tp->pci_lat_timer); | |
7178 | } | |
114342f2 | 7179 | } |
5f5c51e3 | 7180 | |
ee6a99b5 | 7181 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
52f4490c | 7182 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
9974a356 MC |
7183 | u16 pcix_cmd; |
7184 | ||
7185 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7186 | &pcix_cmd); | |
7187 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7188 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7189 | pcix_cmd); | |
7190 | } | |
ee6a99b5 MC |
7191 | |
7192 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
ee6a99b5 MC |
7193 | |
7194 | /* Chip reset on 5780 will reset MSI enable bit, | |
7195 | * so need to restore it. | |
7196 | */ | |
7197 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7198 | u16 ctrl; | |
7199 | ||
7200 | pci_read_config_word(tp->pdev, | |
7201 | tp->msi_cap + PCI_MSI_FLAGS, | |
7202 | &ctrl); | |
7203 | pci_write_config_word(tp->pdev, | |
7204 | tp->msi_cap + PCI_MSI_FLAGS, | |
7205 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7206 | val = tr32(MSGINT_MODE); | |
7207 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7208 | } | |
7209 | } | |
7210 | } | |
7211 | ||
1da177e4 LT |
7212 | static void tg3_stop_fw(struct tg3 *); |
7213 | ||
7214 | /* tp->lock is held. */ | |
7215 | static int tg3_chip_reset(struct tg3 *tp) | |
7216 | { | |
7217 | u32 val; | |
1ee582d8 | 7218 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7219 | int i, err; |
1da177e4 | 7220 | |
f49639e6 DM |
7221 | tg3_nvram_lock(tp); |
7222 | ||
77b483f1 MC |
7223 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7224 | ||
f49639e6 DM |
7225 | /* No matching tg3_nvram_unlock() after this because |
7226 | * chip reset below will undo the nvram lock. | |
7227 | */ | |
7228 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7229 | |
ee6a99b5 MC |
7230 | /* GRC_MISC_CFG core clock reset will clear the memory |
7231 | * enable bit in PCI register 4 and the MSI enable bit | |
7232 | * on some chips, so we save relevant registers here. | |
7233 | */ | |
7234 | tg3_save_pci_state(tp); | |
7235 | ||
d9ab5ad1 | 7236 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
321d32a0 | 7237 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) |
d9ab5ad1 MC |
7238 | tw32(GRC_FASTBOOT_PC, 0); |
7239 | ||
1da177e4 LT |
7240 | /* |
7241 | * We must avoid the readl() that normally takes place. | |
7242 | * It locks machines, causes machine checks, and other | |
7243 | * fun things. So, temporarily disable the 5701 | |
7244 | * hardware workaround, while we do the reset. | |
7245 | */ | |
1ee582d8 MC |
7246 | write_op = tp->write32; |
7247 | if (write_op == tg3_write_flush_reg32) | |
7248 | tp->write32 = tg3_write32; | |
1da177e4 | 7249 | |
d18edcb2 MC |
7250 | /* Prevent the irq handler from reading or writing PCI registers |
7251 | * during chip reset when the memory enable bit in the PCI command | |
7252 | * register may be cleared. The chip does not generate interrupt | |
7253 | * at this time, but the irq handler may still be called due to irq | |
7254 | * sharing or irqpoll. | |
7255 | */ | |
7256 | tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; | |
f77a6a8e MC |
7257 | for (i = 0; i < tp->irq_cnt; i++) { |
7258 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7259 | if (tnapi->hw_status) { | |
7260 | tnapi->hw_status->status = 0; | |
7261 | tnapi->hw_status->status_tag = 0; | |
7262 | } | |
7263 | tnapi->last_tag = 0; | |
7264 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7265 | } |
d18edcb2 | 7266 | smp_mb(); |
4f125f42 MC |
7267 | |
7268 | for (i = 0; i < tp->irq_cnt; i++) | |
7269 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7270 | |
255ca311 MC |
7271 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7272 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7273 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7274 | } | |
7275 | ||
1da177e4 LT |
7276 | /* do the reset */ |
7277 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7278 | ||
7279 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
88075d91 MC |
7280 | /* Force PCIe 1.0a mode */ |
7281 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
1407deb1 | 7282 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
88075d91 MC |
7283 | tr32(TG3_PCIE_PHY_TSTCTL) == |
7284 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7285 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7286 | ||
1da177e4 LT |
7287 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7288 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7289 | val |= (1 << 29); | |
7290 | } | |
7291 | } | |
7292 | ||
b5d3772c MC |
7293 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7294 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7295 | tw32(GRC_VCPU_EXT_CTRL, | |
7296 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7297 | } | |
7298 | ||
f37500d3 MC |
7299 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
7300 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
7301 | !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) | |
1da177e4 | 7302 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7303 | |
1da177e4 LT |
7304 | tw32(GRC_MISC_CFG, val); |
7305 | ||
1ee582d8 MC |
7306 | /* restore 5701 hardware bug workaround write method */ |
7307 | tp->write32 = write_op; | |
1da177e4 LT |
7308 | |
7309 | /* Unfortunately, we have to delay before the PCI read back. | |
7310 | * Some 575X chips even will not respond to a PCI cfg access | |
7311 | * when the reset command is given to the chip. | |
7312 | * | |
7313 | * How do these hardware designers expect things to work | |
7314 | * properly if the PCI write is posted for a long period | |
7315 | * of time? It is always necessary to have some method by | |
7316 | * which a register read back can occur to push the write | |
7317 | * out which does the reset. | |
7318 | * | |
7319 | * For most tg3 variants the trick below was working. | |
7320 | * Ho hum... | |
7321 | */ | |
7322 | udelay(120); | |
7323 | ||
7324 | /* Flush PCI posted writes. The normal MMIO registers | |
7325 | * are inaccessible at this time so this is the only | |
7326 | * way to make this reliably (actually, this is no longer | |
7327 | * the case, see above). I tried to use indirect | |
7328 | * register read/write but this upset some 5701 variants. | |
7329 | */ | |
7330 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7331 | ||
7332 | udelay(120); | |
7333 | ||
5e7dfd0f | 7334 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { |
e7126997 MC |
7335 | u16 val16; |
7336 | ||
1da177e4 LT |
7337 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7338 | int i; | |
7339 | u32 cfg_val; | |
7340 | ||
7341 | /* Wait for link training to complete. */ | |
7342 | for (i = 0; i < 5000; i++) | |
7343 | udelay(100); | |
7344 | ||
7345 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7346 | pci_write_config_dword(tp->pdev, 0xc4, | |
7347 | cfg_val | (1 << 15)); | |
7348 | } | |
5e7dfd0f | 7349 | |
e7126997 MC |
7350 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7351 | pci_read_config_word(tp->pdev, | |
7352 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
7353 | &val16); | |
7354 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7355 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7356 | /* | |
7357 | * Older PCIe devices only support the 128 byte | |
7358 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7359 | */ |
6de34cb9 | 7360 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) |
e7126997 | 7361 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f MC |
7362 | pci_write_config_word(tp->pdev, |
7363 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
e7126997 | 7364 | val16); |
5e7dfd0f | 7365 | |
cf79003d | 7366 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
5e7dfd0f MC |
7367 | |
7368 | /* Clear error status */ | |
7369 | pci_write_config_word(tp->pdev, | |
7370 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
7371 | PCI_EXP_DEVSTA_CED | | |
7372 | PCI_EXP_DEVSTA_NFED | | |
7373 | PCI_EXP_DEVSTA_FED | | |
7374 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7375 | } |
7376 | ||
ee6a99b5 | 7377 | tg3_restore_pci_state(tp); |
1da177e4 | 7378 | |
e64de4e6 MC |
7379 | tp->tg3_flags &= ~(TG3_FLAG_CHIP_RESETTING | |
7380 | TG3_FLAG_ERROR_PROCESSED); | |
d18edcb2 | 7381 | |
ee6a99b5 MC |
7382 | val = 0; |
7383 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
4cf78e4f | 7384 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7385 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7386 | |
7387 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7388 | tg3_stop_fw(tp); | |
7389 | tw32(0x5000, 0x400); | |
7390 | } | |
7391 | ||
7392 | tw32(GRC_MODE, tp->grc_mode); | |
7393 | ||
7394 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7395 | val = tr32(0xc4); |
1da177e4 LT |
7396 | |
7397 | tw32(0xc4, val | (1 << 15)); | |
7398 | } | |
7399 | ||
7400 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7401 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7402 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7403 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7404 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7405 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7406 | } | |
7407 | ||
d2394e6b MC |
7408 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7409 | tp->mac_mode = MAC_MODE_APE_TX_EN | | |
7410 | MAC_MODE_APE_RX_EN | | |
7411 | MAC_MODE_TDE_ENABLE; | |
7412 | ||
f07e9af3 | 7413 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
d2394e6b MC |
7414 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; |
7415 | val = tp->mac_mode; | |
f07e9af3 | 7416 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
d2394e6b MC |
7417 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
7418 | val = tp->mac_mode; | |
1da177e4 | 7419 | } else |
d2394e6b MC |
7420 | val = 0; |
7421 | ||
7422 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
7423 | udelay(40); |
7424 | ||
77b483f1 MC |
7425 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7426 | ||
7a6f4369 MC |
7427 | err = tg3_poll_fw(tp); |
7428 | if (err) | |
7429 | return err; | |
1da177e4 | 7430 | |
0a9140cf MC |
7431 | tg3_mdio_start(tp); |
7432 | ||
1da177e4 | 7433 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
f6eb9b1f MC |
7434 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7435 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
1407deb1 | 7436 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
ab0049b4 | 7437 | val = tr32(0x7c00); |
1da177e4 LT |
7438 | |
7439 | tw32(0x7c00, val | (1 << 25)); | |
7440 | } | |
7441 | ||
d78b59f5 MC |
7442 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
7443 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
7444 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
7445 | } | |
7446 | ||
1da177e4 LT |
7447 | /* Reprobe ASF enable state. */ |
7448 | tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; | |
7449 | tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; | |
7450 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
7451 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7452 | u32 nic_cfg; | |
7453 | ||
7454 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7455 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
7456 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
4ba526ce | 7457 | tp->last_event_jiffies = jiffies; |
cbf46853 | 7458 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
7459 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
7460 | } | |
7461 | } | |
7462 | ||
7463 | return 0; | |
7464 | } | |
7465 | ||
7466 | /* tp->lock is held. */ | |
7467 | static void tg3_stop_fw(struct tg3 *tp) | |
7468 | { | |
0d3031d9 MC |
7469 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
7470 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
7471 | /* Wait for RX cpu to ACK the previous event. */ |
7472 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7473 | |
7474 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
7475 | |
7476 | tg3_generate_fw_event(tp); | |
1da177e4 | 7477 | |
7c5026aa MC |
7478 | /* Wait for RX cpu to ACK this event. */ |
7479 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7480 | } |
7481 | } | |
7482 | ||
7483 | /* tp->lock is held. */ | |
944d980e | 7484 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7485 | { |
7486 | int err; | |
7487 | ||
7488 | tg3_stop_fw(tp); | |
7489 | ||
944d980e | 7490 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7491 | |
b3b7d6be | 7492 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7493 | err = tg3_chip_reset(tp); |
7494 | ||
daba2a63 MC |
7495 | __tg3_set_mac_addr(tp, 0); |
7496 | ||
944d980e MC |
7497 | tg3_write_sig_legacy(tp, kind); |
7498 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
7499 | |
7500 | if (err) | |
7501 | return err; | |
7502 | ||
7503 | return 0; | |
7504 | } | |
7505 | ||
1da177e4 LT |
7506 | #define RX_CPU_SCRATCH_BASE 0x30000 |
7507 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7508 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7509 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7510 | ||
7511 | /* tp->lock is held. */ | |
7512 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7513 | { | |
7514 | int i; | |
7515 | ||
5d9428de ES |
7516 | BUG_ON(offset == TX_CPU_BASE && |
7517 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)); | |
1da177e4 | 7518 | |
b5d3772c MC |
7519 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7520 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7521 | ||
7522 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7523 | return 0; | |
7524 | } | |
1da177e4 LT |
7525 | if (offset == RX_CPU_BASE) { |
7526 | for (i = 0; i < 10000; i++) { | |
7527 | tw32(offset + CPU_STATE, 0xffffffff); | |
7528 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7529 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7530 | break; | |
7531 | } | |
7532 | ||
7533 | tw32(offset + CPU_STATE, 0xffffffff); | |
7534 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7535 | udelay(10); | |
7536 | } else { | |
7537 | for (i = 0; i < 10000; i++) { | |
7538 | tw32(offset + CPU_STATE, 0xffffffff); | |
7539 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7540 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7541 | break; | |
7542 | } | |
7543 | } | |
7544 | ||
7545 | if (i >= 10000) { | |
05dbe005 JP |
7546 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
7547 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
1da177e4 LT |
7548 | return -ENODEV; |
7549 | } | |
ec41c7df MC |
7550 | |
7551 | /* Clear firmware's nvram arbitration. */ | |
7552 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
7553 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
1da177e4 LT |
7554 | return 0; |
7555 | } | |
7556 | ||
7557 | struct fw_info { | |
077f849d JSR |
7558 | unsigned int fw_base; |
7559 | unsigned int fw_len; | |
7560 | const __be32 *fw_data; | |
1da177e4 LT |
7561 | }; |
7562 | ||
7563 | /* tp->lock is held. */ | |
7564 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7565 | int cpu_scratch_size, struct fw_info *info) | |
7566 | { | |
ec41c7df | 7567 | int err, lock_err, i; |
1da177e4 LT |
7568 | void (*write_op)(struct tg3 *, u32, u32); |
7569 | ||
7570 | if (cpu_base == TX_CPU_BASE && | |
7571 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
5129c3a3 MC |
7572 | netdev_err(tp->dev, |
7573 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
05dbe005 | 7574 | __func__); |
1da177e4 LT |
7575 | return -EINVAL; |
7576 | } | |
7577 | ||
7578 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
7579 | write_op = tg3_write_mem; | |
7580 | else | |
7581 | write_op = tg3_write_indirect_reg32; | |
7582 | ||
1b628151 MC |
7583 | /* It is possible that bootcode is still loading at this point. |
7584 | * Get the nvram lock first before halting the cpu. | |
7585 | */ | |
ec41c7df | 7586 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 7587 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
7588 | if (!lock_err) |
7589 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
7590 | if (err) |
7591 | goto out; | |
7592 | ||
7593 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7594 | write_op(tp, cpu_scratch_base + i, 0); | |
7595 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7596 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 7597 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 7598 | write_op(tp, (cpu_scratch_base + |
077f849d | 7599 | (info->fw_base & 0xffff) + |
1da177e4 | 7600 | (i * sizeof(u32))), |
077f849d | 7601 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
7602 | |
7603 | err = 0; | |
7604 | ||
7605 | out: | |
1da177e4 LT |
7606 | return err; |
7607 | } | |
7608 | ||
7609 | /* tp->lock is held. */ | |
7610 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7611 | { | |
7612 | struct fw_info info; | |
077f849d | 7613 | const __be32 *fw_data; |
1da177e4 LT |
7614 | int err, i; |
7615 | ||
077f849d JSR |
7616 | fw_data = (void *)tp->fw->data; |
7617 | ||
7618 | /* Firmware blob starts with version numbers, followed by | |
7619 | start address and length. We are setting complete length. | |
7620 | length = end_address_of_bss - start_address_of_text. | |
7621 | Remainder is the blob to be loaded contiguously | |
7622 | from start address. */ | |
7623 | ||
7624 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7625 | info.fw_len = tp->fw->size - 12; | |
7626 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
7627 | |
7628 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7629 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7630 | &info); | |
7631 | if (err) | |
7632 | return err; | |
7633 | ||
7634 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7635 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7636 | &info); | |
7637 | if (err) | |
7638 | return err; | |
7639 | ||
7640 | /* Now startup only the RX cpu. */ | |
7641 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 7642 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7643 | |
7644 | for (i = 0; i < 5; i++) { | |
077f849d | 7645 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
7646 | break; |
7647 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7648 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7649 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7650 | udelay(1000); |
7651 | } | |
7652 | if (i >= 5) { | |
5129c3a3 MC |
7653 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
7654 | "should be %08x\n", __func__, | |
05dbe005 | 7655 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); |
1da177e4 LT |
7656 | return -ENODEV; |
7657 | } | |
7658 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7659 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7660 | ||
7661 | return 0; | |
7662 | } | |
7663 | ||
1da177e4 | 7664 | /* 5705 needs a special version of the TSO firmware. */ |
1da177e4 LT |
7665 | |
7666 | /* tp->lock is held. */ | |
7667 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7668 | { | |
7669 | struct fw_info info; | |
077f849d | 7670 | const __be32 *fw_data; |
1da177e4 LT |
7671 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
7672 | int err, i; | |
7673 | ||
7674 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
7675 | return 0; | |
7676 | ||
077f849d JSR |
7677 | fw_data = (void *)tp->fw->data; |
7678 | ||
7679 | /* Firmware blob starts with version numbers, followed by | |
7680 | start address and length. We are setting complete length. | |
7681 | length = end_address_of_bss - start_address_of_text. | |
7682 | Remainder is the blob to be loaded contiguously | |
7683 | from start address. */ | |
7684 | ||
7685 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7686 | cpu_scratch_size = tp->fw_len; | |
7687 | info.fw_len = tp->fw->size - 12; | |
7688 | info.fw_data = &fw_data[3]; | |
7689 | ||
1da177e4 | 7690 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7691 | cpu_base = RX_CPU_BASE; |
7692 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 7693 | } else { |
1da177e4 LT |
7694 | cpu_base = TX_CPU_BASE; |
7695 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7696 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7697 | } | |
7698 | ||
7699 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7700 | cpu_scratch_base, cpu_scratch_size, | |
7701 | &info); | |
7702 | if (err) | |
7703 | return err; | |
7704 | ||
7705 | /* Now startup the cpu. */ | |
7706 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 7707 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7708 | |
7709 | for (i = 0; i < 5; i++) { | |
077f849d | 7710 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
7711 | break; |
7712 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7713 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7714 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7715 | udelay(1000); |
7716 | } | |
7717 | if (i >= 5) { | |
5129c3a3 MC |
7718 | netdev_err(tp->dev, |
7719 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
05dbe005 | 7720 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); |
1da177e4 LT |
7721 | return -ENODEV; |
7722 | } | |
7723 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7724 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7725 | return 0; | |
7726 | } | |
7727 | ||
1da177e4 | 7728 | |
1da177e4 LT |
7729 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7730 | { | |
7731 | struct tg3 *tp = netdev_priv(dev); | |
7732 | struct sockaddr *addr = p; | |
986e0aeb | 7733 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7734 | |
f9804ddb MC |
7735 | if (!is_valid_ether_addr(addr->sa_data)) |
7736 | return -EINVAL; | |
7737 | ||
1da177e4 LT |
7738 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7739 | ||
e75f7c90 MC |
7740 | if (!netif_running(dev)) |
7741 | return 0; | |
7742 | ||
58712ef9 | 7743 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { |
986e0aeb | 7744 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7745 | |
986e0aeb MC |
7746 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7747 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7748 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7749 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7750 | ||
7751 | /* Skip MAC addr 1 if ASF is using it. */ | |
7752 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7753 | !(addr1_high == 0 && addr1_low == 0)) | |
7754 | skip_mac_1 = 1; | |
58712ef9 | 7755 | } |
986e0aeb MC |
7756 | spin_lock_bh(&tp->lock); |
7757 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7758 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7759 | |
b9ec6c1b | 7760 | return err; |
1da177e4 LT |
7761 | } |
7762 | ||
7763 | /* tp->lock is held. */ | |
7764 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7765 | dma_addr_t mapping, u32 maxlen_flags, | |
7766 | u32 nic_addr) | |
7767 | { | |
7768 | tg3_write_mem(tp, | |
7769 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7770 | ((u64) mapping >> 32)); | |
7771 | tg3_write_mem(tp, | |
7772 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7773 | ((u64) mapping & 0xffffffff)); | |
7774 | tg3_write_mem(tp, | |
7775 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7776 | maxlen_flags); | |
7777 | ||
7778 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7779 | tg3_write_mem(tp, | |
7780 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7781 | nic_addr); | |
7782 | } | |
7783 | ||
7784 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7785 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7786 | { |
b6080e12 MC |
7787 | int i; |
7788 | ||
19cfaecc | 7789 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) { |
b6080e12 MC |
7790 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7791 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7792 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7793 | } else { |
7794 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7795 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7796 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7797 | } |
b6080e12 | 7798 | |
20d7375c | 7799 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { |
19cfaecc MC |
7800 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
7801 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7802 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7803 | } else { | |
b6080e12 MC |
7804 | tw32(HOSTCC_RXCOL_TICKS, 0); |
7805 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7806 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7807 | } |
b6080e12 | 7808 | |
15f9850d DM |
7809 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
7810 | u32 val = ec->stats_block_coalesce_usecs; | |
7811 | ||
b6080e12 MC |
7812 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7813 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7814 | ||
15f9850d DM |
7815 | if (!netif_carrier_ok(tp->dev)) |
7816 | val = 0; | |
7817 | ||
7818 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7819 | } | |
b6080e12 MC |
7820 | |
7821 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7822 | u32 reg; | |
7823 | ||
7824 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7825 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
7826 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
7827 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
7828 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
7829 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc MC |
7830 | |
7831 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7832 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
7833 | tw32(reg, ec->tx_coalesce_usecs); | |
7834 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7835 | tw32(reg, ec->tx_max_coalesced_frames); | |
7836 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7837 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7838 | } | |
b6080e12 MC |
7839 | } |
7840 | ||
7841 | for (; i < tp->irq_max - 1; i++) { | |
7842 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 7843 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 7844 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc MC |
7845 | |
7846 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7847 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7848 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7849 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7850 | } | |
b6080e12 | 7851 | } |
15f9850d | 7852 | } |
1da177e4 | 7853 | |
2d31ecaf MC |
7854 | /* tp->lock is held. */ |
7855 | static void tg3_rings_reset(struct tg3 *tp) | |
7856 | { | |
7857 | int i; | |
f77a6a8e | 7858 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
7859 | struct tg3_napi *tnapi = &tp->napi[0]; |
7860 | ||
7861 | /* Disable all transmit rings but the first. */ | |
7862 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7863 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; | |
0a58d668 | 7864 | else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
3d37728b | 7865 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
b703df6f MC |
7866 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
7867 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
2d31ecaf MC |
7868 | else |
7869 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7870 | ||
7871 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7872 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7873 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7874 | BDINFO_FLAGS_DISABLED); | |
7875 | ||
7876 | ||
7877 | /* Disable all receive return rings but the first. */ | |
0a58d668 | 7878 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
f6eb9b1f MC |
7879 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
7880 | else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
2d31ecaf | 7881 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f MC |
7882 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
7883 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2d31ecaf MC |
7884 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
7885 | else | |
7886 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7887 | ||
7888 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7889 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7890 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7891 | BDINFO_FLAGS_DISABLED); | |
7892 | ||
7893 | /* Disable interrupts */ | |
7894 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
7895 | ||
7896 | /* Zero mailbox registers. */ | |
f77a6a8e | 7897 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) { |
6fd45cb8 | 7898 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
7899 | tp->napi[i].tx_prod = 0; |
7900 | tp->napi[i].tx_cons = 0; | |
c2353a32 MC |
7901 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
7902 | tw32_mailbox(tp->napi[i].prodmbox, 0); | |
f77a6a8e MC |
7903 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
7904 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7905 | } | |
c2353a32 MC |
7906 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) |
7907 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
f77a6a8e MC |
7908 | } else { |
7909 | tp->napi[0].tx_prod = 0; | |
7910 | tp->napi[0].tx_cons = 0; | |
7911 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7912 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7913 | } | |
2d31ecaf MC |
7914 | |
7915 | /* Make sure the NIC-based send BD rings are disabled. */ | |
7916 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7917 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
7918 | for (i = 0; i < 16; i++) | |
7919 | tw32_tx_mbox(mbox + i * 8, 0); | |
7920 | } | |
7921 | ||
7922 | txrcb = NIC_SRAM_SEND_RCB; | |
7923 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7924 | ||
7925 | /* Clear status block in ram. */ | |
7926 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7927 | ||
7928 | /* Set status block DMA address */ | |
7929 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7930 | ((u64) tnapi->status_mapping >> 32)); | |
7931 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7932 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7933 | ||
f77a6a8e MC |
7934 | if (tnapi->tx_ring) { |
7935 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7936 | (TG3_TX_RING_SIZE << | |
7937 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7938 | NIC_SRAM_TX_BUFFER_DESC); | |
7939 | txrcb += TG3_BDINFO_SIZE; | |
7940 | } | |
7941 | ||
7942 | if (tnapi->rx_rcb) { | |
7943 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
7944 | (tp->rx_ret_ring_mask + 1) << |
7945 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
7946 | rxrcb += TG3_BDINFO_SIZE; |
7947 | } | |
7948 | ||
7949 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 7950 | |
f77a6a8e MC |
7951 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
7952 | u64 mapping = (u64)tnapi->status_mapping; | |
7953 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7954 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7955 | ||
7956 | /* Clear status block in ram. */ | |
7957 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7958 | ||
19cfaecc MC |
7959 | if (tnapi->tx_ring) { |
7960 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7961 | (TG3_TX_RING_SIZE << | |
7962 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7963 | NIC_SRAM_TX_BUFFER_DESC); | |
7964 | txrcb += TG3_BDINFO_SIZE; | |
7965 | } | |
f77a6a8e MC |
7966 | |
7967 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 7968 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
7969 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
7970 | ||
7971 | stblk += 8; | |
f77a6a8e MC |
7972 | rxrcb += TG3_BDINFO_SIZE; |
7973 | } | |
2d31ecaf MC |
7974 | } |
7975 | ||
eb07a940 MC |
7976 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
7977 | { | |
7978 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
7979 | ||
7980 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS) || | |
7981 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
7982 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
7983 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
7984 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; | |
7985 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
7986 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
7987 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
7988 | else | |
7989 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
7990 | ||
7991 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
7992 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
7993 | ||
7994 | val = min(nic_rep_thresh, host_rep_thresh); | |
7995 | tw32(RCVBDI_STD_THRESH, val); | |
7996 | ||
7997 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) | |
7998 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); | |
7999 | ||
8000 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) || | |
8001 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
8002 | return; | |
8003 | ||
8004 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8005 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; | |
8006 | else | |
8007 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717; | |
8008 | ||
8009 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
8010 | ||
8011 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
8012 | tw32(RCVBDI_JUMBO_THRESH, val); | |
8013 | ||
8014 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) | |
8015 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); | |
8016 | } | |
8017 | ||
1da177e4 | 8018 | /* tp->lock is held. */ |
8e7a22e3 | 8019 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
8020 | { |
8021 | u32 val, rdmac_mode; | |
8022 | int i, err, limit; | |
8fea32b9 | 8023 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
8024 | |
8025 | tg3_disable_ints(tp); | |
8026 | ||
8027 | tg3_stop_fw(tp); | |
8028 | ||
8029 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
8030 | ||
859a5887 | 8031 | if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) |
e6de8ad1 | 8032 | tg3_abort_hw(tp, 1); |
1da177e4 | 8033 | |
699c0193 MC |
8034 | /* Enable MAC control of LPI */ |
8035 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
8036 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
8037 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
8038 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
8039 | ||
8040 | tw32_f(TG3_CPMU_EEE_CTRL, | |
8041 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
8042 | ||
a386b901 MC |
8043 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
8044 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
8045 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
8046 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
8047 | ||
8048 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8049 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
8050 | ||
8051 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
8052 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; | |
8053 | ||
8054 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
8055 | ||
8056 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8057 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8058 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8059 | ||
8060 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8061 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8062 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8063 | } |
8064 | ||
603f1173 | 8065 | if (reset_phy) |
d4d2c558 MC |
8066 | tg3_phy_reset(tp); |
8067 | ||
1da177e4 LT |
8068 | err = tg3_chip_reset(tp); |
8069 | if (err) | |
8070 | return err; | |
8071 | ||
8072 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8073 | ||
bcb37f6c | 8074 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8075 | val = tr32(TG3_CPMU_CTRL); |
8076 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8077 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8078 | |
8079 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8080 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8081 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8082 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8083 | ||
8084 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8085 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8086 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8087 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8088 | ||
8089 | val = tr32(TG3_CPMU_HST_ACC); | |
8090 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
8091 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
8092 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
8093 | } |
8094 | ||
33466d93 MC |
8095 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8096 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
8097 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
8098 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
8099 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
8100 | |
8101 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
8102 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
8103 | ||
8104 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 8105 | |
f40386c8 MC |
8106 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8107 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
8108 | } |
8109 | ||
614b0590 MC |
8110 | if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) { |
8111 | u32 grc_mode = tr32(GRC_MODE); | |
8112 | ||
8113 | /* Access the lower 1K of PL PCIE block registers. */ | |
8114 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8115 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
8116 | ||
8117 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
8118 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
8119 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
8120 | ||
8121 | tw32(GRC_MODE, grc_mode); | |
8122 | } | |
8123 | ||
5093eedc MC |
8124 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
8125 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
8126 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 8127 | |
5093eedc MC |
8128 | /* Access the lower 1K of PL PCIE block registers. */ |
8129 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8130 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 8131 | |
5093eedc MC |
8132 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
8133 | TG3_PCIE_PL_LO_PHYCTL5); | |
8134 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
8135 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 8136 | |
5093eedc MC |
8137 | tw32(GRC_MODE, grc_mode); |
8138 | } | |
a977dbe8 MC |
8139 | |
8140 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8141 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8142 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8143 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
8144 | } |
8145 | ||
1da177e4 LT |
8146 | /* This works around an issue with Athlon chipsets on |
8147 | * B3 tigon3 silicon. This bit has no effect on any | |
8148 | * other revision. But do not set this on PCI Express | |
795d01c5 | 8149 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 8150 | */ |
795d01c5 MC |
8151 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { |
8152 | if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
8153 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
8154 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8155 | } | |
1da177e4 LT |
8156 | |
8157 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
8158 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
8159 | val = tr32(TG3PCI_PCISTATE); | |
8160 | val |= PCISTATE_RETRY_SAME_DMA; | |
8161 | tw32(TG3PCI_PCISTATE, val); | |
8162 | } | |
8163 | ||
0d3031d9 MC |
8164 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
8165 | /* Allow reads and writes to the | |
8166 | * APE register and memory space. | |
8167 | */ | |
8168 | val = tr32(TG3PCI_PCISTATE); | |
8169 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
8170 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8171 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
8172 | tw32(TG3PCI_PCISTATE, val); |
8173 | } | |
8174 | ||
1da177e4 LT |
8175 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
8176 | /* Enable some hw fixes. */ | |
8177 | val = tr32(TG3PCI_MSI_DATA); | |
8178 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8179 | tw32(TG3PCI_MSI_DATA, val); | |
8180 | } | |
8181 | ||
8182 | /* Descriptor ring init may make accesses to the | |
8183 | * NIC SRAM area to setup the TX descriptors, so we | |
8184 | * can only do this after the hardware has been | |
8185 | * successfully reset. | |
8186 | */ | |
32d8c572 MC |
8187 | err = tg3_init_rings(tp); |
8188 | if (err) | |
8189 | return err; | |
1da177e4 | 8190 | |
1407deb1 | 8191 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
cbf9ca6c MC |
8192 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
8193 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
8194 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
8195 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
cbf9ca6c MC |
8196 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
8197 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8198 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
8199 | /* This value is determined during the probe time DMA |
8200 | * engine test, tg3_test_dma. | |
8201 | */ | |
8202 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8203 | } | |
1da177e4 LT |
8204 | |
8205 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8206 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8207 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8208 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8209 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
8210 | |
8211 | /* Pseudo-header checksum is done by hardware logic and not | |
8212 | * the offload processers, so make the chip do the pseudo- | |
8213 | * header checksums on receive. For transmit it is more | |
8214 | * convenient to do the pseudo-header checksum in software | |
8215 | * as Linux does that on transmit for us in all cases. | |
8216 | */ | |
8217 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
8218 | |
8219 | tw32(GRC_MODE, | |
8220 | tp->grc_mode | | |
8221 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8222 | ||
8223 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8224 | val = tr32(GRC_MISC_CFG); | |
8225 | val &= ~0xff; | |
8226 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8227 | tw32(GRC_MISC_CFG, val); | |
8228 | ||
8229 | /* Initialize MBUF/DESC pool. */ | |
cbf46853 | 8230 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
1da177e4 LT |
8231 | /* Do nothing. */ |
8232 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8233 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8234 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8235 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8236 | else | |
8237 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8238 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8239 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
859a5887 | 8240 | } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
1da177e4 LT |
8241 | int fw_len; |
8242 | ||
077f849d | 8243 | fw_len = tp->fw_len; |
1da177e4 LT |
8244 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8245 | tw32(BUFMGR_MB_POOL_ADDR, | |
8246 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8247 | tw32(BUFMGR_MB_POOL_SIZE, | |
8248 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8249 | } | |
1da177e4 | 8250 | |
0f893dc6 | 8251 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8252 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8253 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8254 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8255 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8256 | tw32(BUFMGR_MB_HIGH_WATER, | |
8257 | tp->bufmgr_config.mbuf_high_water); | |
8258 | } else { | |
8259 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8260 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8261 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8262 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8263 | tw32(BUFMGR_MB_HIGH_WATER, | |
8264 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8265 | } | |
8266 | tw32(BUFMGR_DMA_LOW_WATER, | |
8267 | tp->bufmgr_config.dma_low_water); | |
8268 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8269 | tp->bufmgr_config.dma_high_water); | |
8270 | ||
d309a46e MC |
8271 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8272 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8273 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
8274 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8275 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
8276 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
8277 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 8278 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
8279 | for (i = 0; i < 2000; i++) { |
8280 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8281 | break; | |
8282 | udelay(10); | |
8283 | } | |
8284 | if (i >= 2000) { | |
05dbe005 | 8285 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8286 | return -ENODEV; |
8287 | } | |
8288 | ||
eb07a940 MC |
8289 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
8290 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 8291 | |
eb07a940 | 8292 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
8293 | |
8294 | /* Initialize TG3_BDINFO's at: | |
8295 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8296 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8297 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8298 | * | |
8299 | * like so: | |
8300 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8301 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8302 | * ring attribute flags | |
8303 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8304 | * | |
8305 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8306 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8307 | * | |
8308 | * The size of each ring is fixed in the firmware, but the location is | |
8309 | * configurable. | |
8310 | */ | |
8311 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8312 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8313 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8314 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
0a58d668 | 8315 | if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
87668d35 MC |
8316 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8317 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8318 | |
fdb72b38 MC |
8319 | /* Disable the mini ring */ |
8320 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
1da177e4 LT |
8321 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8322 | BDINFO_FLAGS_DISABLED); | |
8323 | ||
fdb72b38 MC |
8324 | /* Program the jumbo buffer descriptor ring control |
8325 | * blocks on those devices that have them. | |
8326 | */ | |
bb18bb94 | 8327 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
4d163b75 MC |
8328 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
8329 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) { | |
1da177e4 | 8330 | |
0f893dc6 | 8331 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { |
1da177e4 | 8332 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8333 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8334 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8335 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
8336 | val = TG3_RX_JMB_RING_SIZE(tp) << |
8337 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 8338 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 8339 | val | BDINFO_FLAGS_USE_EXT_RECV); |
a50d0796 MC |
8340 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) || |
8341 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
87668d35 MC |
8342 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8343 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8344 | } else { |
8345 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8346 | BDINFO_FLAGS_DISABLED); | |
8347 | } | |
8348 | ||
1407deb1 | 8349 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
7cb32cf2 | 8350 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
de9f5230 | 8351 | val = TG3_RX_STD_MAX_SIZE_5700; |
7cb32cf2 | 8352 | else |
de9f5230 | 8353 | val = TG3_RX_STD_MAX_SIZE_5717; |
7cb32cf2 MC |
8354 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8355 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8356 | } else | |
04380d40 | 8357 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 8358 | } else |
de9f5230 | 8359 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8360 | |
8361 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8362 | |
411da640 | 8363 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8364 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8365 | |
411da640 | 8366 | tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? |
21f581a5 | 8367 | tp->rx_jumbo_pending : 0; |
66711e66 | 8368 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8369 | |
2d31ecaf MC |
8370 | tg3_rings_reset(tp); |
8371 | ||
1da177e4 | 8372 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8373 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8374 | |
8375 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8376 | tw32(MAC_RX_MTU_SIZE, |
8377 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8378 | |
8379 | /* The slot time is changed by tg3_setup_phy if we | |
8380 | * run at gigabit with half duplex. | |
8381 | */ | |
f2096f94 MC |
8382 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
8383 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8384 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
8385 | ||
8386 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8387 | val |= tr32(MAC_TX_LENGTHS) & | |
8388 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
8389 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
8390 | ||
8391 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
8392 | |
8393 | /* Receive rules. */ | |
8394 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8395 | tw32(RCVLPC_CONFIG, 0x0181); | |
8396 | ||
8397 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8398 | * the RCVLPC_STATE_ENABLE mask. | |
8399 | */ | |
8400 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8401 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8402 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8403 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8404 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8405 | |
deabaac8 | 8406 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8407 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8408 | ||
57e6983c | 8409 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8410 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8411 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8412 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8413 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8414 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8415 | ||
c5908939 MC |
8416 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8417 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
1da177e4 | 8418 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && |
c13e3713 | 8419 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8420 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8421 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
8422 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { | |
8423 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8424 | } | |
8425 | } | |
8426 | ||
85e94ced MC |
8427 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) |
8428 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8429 | ||
1da177e4 | 8430 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
027455ad MC |
8431 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8432 | ||
e849cdc3 MC |
8433 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
8434 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
027455ad MC |
8435 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8436 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8437 | |
f2096f94 MC |
8438 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
8439 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
8440 | ||
41a8a7ee MC |
8441 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8442 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8443 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8444 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
1407deb1 | 8445 | (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
41a8a7ee | 8446 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
d78b59f5 MC |
8447 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8448 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b4495ed8 MC |
8449 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8450 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8451 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8452 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8453 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8454 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8455 | } |
41a8a7ee MC |
8456 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8457 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8458 | } | |
8459 | ||
d78b59f5 MC |
8460 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8461 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
8462 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
8463 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8464 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8465 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8466 | } | |
8467 | ||
1da177e4 | 8468 | /* Receive/send statistics. */ |
1661394e MC |
8469 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
8470 | val = tr32(RCVLPC_STATS_ENABLE); | |
8471 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8472 | tw32(RCVLPC_STATS_ENABLE, val); | |
8473 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
8474 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
1da177e4 LT |
8475 | val = tr32(RCVLPC_STATS_ENABLE); |
8476 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8477 | tw32(RCVLPC_STATS_ENABLE, val); | |
8478 | } else { | |
8479 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8480 | } | |
8481 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8482 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8483 | tw32(SNDDATAI_STATSCTRL, | |
8484 | (SNDDATAI_SCTRL_ENABLE | | |
8485 | SNDDATAI_SCTRL_FASTUPD)); | |
8486 | ||
8487 | /* Setup host coalescing engine. */ | |
8488 | tw32(HOSTCC_MODE, 0); | |
8489 | for (i = 0; i < 2000; i++) { | |
8490 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8491 | break; | |
8492 | udelay(10); | |
8493 | } | |
8494 | ||
d244c892 | 8495 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8496 | |
1da177e4 LT |
8497 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8498 | /* Status/statistics block address. See tg3_timer, | |
8499 | * the tg3_periodic_fetch_stats call there, and | |
8500 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8501 | */ | |
1da177e4 LT |
8502 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8503 | ((u64) tp->stats_mapping >> 32)); | |
8504 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8505 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8506 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8507 | |
1da177e4 | 8508 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8509 | |
8510 | /* Clear statistics and status block memory areas */ | |
8511 | for (i = NIC_SRAM_STATS_BLK; | |
8512 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8513 | i += sizeof(u32)) { | |
8514 | tg3_write_mem(tp, i, 0); | |
8515 | udelay(40); | |
8516 | } | |
1da177e4 LT |
8517 | } |
8518 | ||
8519 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8520 | ||
8521 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8522 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
8523 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8524 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
8525 | ||
f07e9af3 MC |
8526 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
8527 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
8528 | /* reset to prevent losing 1st rx packet intermittently */ |
8529 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8530 | udelay(10); | |
8531 | } | |
8532 | ||
3bda1258 | 8533 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
d2394e6b | 8534 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
8535 | else |
8536 | tp->mac_mode = 0; | |
8537 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
1da177e4 | 8538 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; |
e8f3f6ca | 8539 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
f07e9af3 | 8540 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
8541 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
8542 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8543 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8544 | udelay(40); | |
8545 | ||
314fba34 | 8546 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
9d26e213 | 8547 | * If TG3_FLG2_IS_NIC is zero, we should read the |
314fba34 MC |
8548 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8549 | * whether used as inputs or outputs, are set by boot code after | |
8550 | * reset. | |
8551 | */ | |
9d26e213 | 8552 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { |
314fba34 MC |
8553 | u32 gpio_mask; |
8554 | ||
9d26e213 MC |
8555 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8556 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8557 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8558 | |
8559 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8560 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8561 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8562 | ||
af36e6b6 MC |
8563 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8564 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8565 | ||
aaf84465 | 8566 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8567 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8568 | ||
8569 | /* GPIO1 must be driven high for eeprom write protect */ | |
9d26e213 MC |
8570 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) |
8571 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
8572 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8573 | } |
1da177e4 LT |
8574 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8575 | udelay(100); | |
8576 | ||
0583d521 MC |
8577 | if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && |
8578 | tp->irq_cnt > 1) { | |
baf8a94a MC |
8579 | val = tr32(MSGINT_MODE); |
8580 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8581 | tw32(MSGINT_MODE, val); | |
8582 | } | |
8583 | ||
1da177e4 LT |
8584 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8585 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
8586 | udelay(40); | |
8587 | } | |
8588 | ||
8589 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8590 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8591 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8592 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8593 | WDMAC_MODE_LNGREAD_ENAB); | |
8594 | ||
c5908939 MC |
8595 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8596 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
29ea095f | 8597 | if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && |
1da177e4 LT |
8598 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8599 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8600 | /* nothing */ | |
8601 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
c5908939 | 8602 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { |
1da177e4 LT |
8603 | val |= WDMAC_MODE_RX_ACCEL; |
8604 | } | |
8605 | } | |
8606 | ||
d9ab5ad1 | 8607 | /* Enable host coalescing bug fix */ |
321d32a0 | 8608 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
f51f3562 | 8609 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8610 | |
788a035e MC |
8611 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8612 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8613 | ||
1da177e4 LT |
8614 | tw32_f(WDMAC_MODE, val); |
8615 | udelay(40); | |
8616 | ||
9974a356 MC |
8617 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
8618 | u16 pcix_cmd; | |
8619 | ||
8620 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8621 | &pcix_cmd); | |
1da177e4 | 8622 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8623 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8624 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8625 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8626 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8627 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8628 | } |
9974a356 MC |
8629 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8630 | pcix_cmd); | |
1da177e4 LT |
8631 | } |
8632 | ||
8633 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8634 | udelay(40); | |
8635 | ||
8636 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
8637 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8638 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
9936bcf6 MC |
8639 | |
8640 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8641 | tw32(SNDDATAC_MODE, | |
8642 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8643 | else | |
8644 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8645 | ||
1da177e4 LT |
8646 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8647 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 8648 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
de9f5230 | 8649 | if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) |
7cb32cf2 MC |
8650 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
8651 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 8652 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
1da177e4 LT |
8653 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
8654 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
baf8a94a | 8655 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
19cfaecc | 8656 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
baf8a94a MC |
8657 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8658 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8659 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8660 | ||
8661 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8662 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8663 | if (err) | |
8664 | return err; | |
8665 | } | |
8666 | ||
1da177e4 LT |
8667 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
8668 | err = tg3_load_tso_firmware(tp); | |
8669 | if (err) | |
8670 | return err; | |
8671 | } | |
1da177e4 LT |
8672 | |
8673 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 8674 | |
b1d05210 MC |
8675 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
8676 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
8677 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
8678 | |
8679 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8680 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
8681 | tp->tx_mode &= ~val; | |
8682 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
8683 | } | |
8684 | ||
1da177e4 LT |
8685 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
8686 | udelay(100); | |
8687 | ||
baf8a94a MC |
8688 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { |
8689 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8690 | u8 *ent = (u8 *)&val; | |
8691 | ||
8692 | /* Setup the indirection table */ | |
8693 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8694 | int idx = i % sizeof(val); | |
8695 | ||
5efeeea1 | 8696 | ent[idx] = i % (tp->irq_cnt - 1); |
baf8a94a MC |
8697 | if (idx == sizeof(val) - 1) { |
8698 | tw32(reg, val); | |
8699 | reg += 4; | |
8700 | } | |
8701 | } | |
8702 | ||
8703 | /* Setup the "secret" hash key. */ | |
8704 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8705 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8706 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8707 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8708 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8709 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8710 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8711 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8712 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8713 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8714 | } | |
8715 | ||
1da177e4 | 8716 | tp->rx_mode = RX_MODE_ENABLE; |
321d32a0 | 8717 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
af36e6b6 MC |
8718 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8719 | ||
baf8a94a MC |
8720 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
8721 | tp->rx_mode |= RX_MODE_RSS_ENABLE | | |
8722 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8723 | RX_MODE_RSS_IPV6_HASH_EN | | |
8724 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8725 | RX_MODE_RSS_IPV4_HASH_EN | | |
8726 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8727 | ||
1da177e4 LT |
8728 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8729 | udelay(10); | |
8730 | ||
1da177e4 LT |
8731 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8732 | ||
8733 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 8734 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
8735 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8736 | udelay(10); | |
8737 | } | |
8738 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8739 | udelay(10); | |
8740 | ||
f07e9af3 | 8741 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 8742 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 8743 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
8744 | /* Set drive transmission level to 1.2V */ |
8745 | /* only if the signal pre-emphasis bit is not set */ | |
8746 | val = tr32(MAC_SERDES_CFG); | |
8747 | val &= 0xfffff000; | |
8748 | val |= 0x880; | |
8749 | tw32(MAC_SERDES_CFG, val); | |
8750 | } | |
8751 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8752 | tw32(MAC_SERDES_CFG, 0x616000); | |
8753 | } | |
8754 | ||
8755 | /* Prevent chip from dropping frames when flow control | |
8756 | * is enabled. | |
8757 | */ | |
666bc831 MC |
8758 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8759 | val = 1; | |
8760 | else | |
8761 | val = 2; | |
8762 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
8763 | |
8764 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 8765 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 LT |
8766 | /* Use hardware link auto-negotiation */ |
8767 | tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; | |
8768 | } | |
8769 | ||
f07e9af3 | 8770 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
d4d2c558 MC |
8771 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { |
8772 | u32 tmp; | |
8773 | ||
8774 | tmp = tr32(SERDES_RX_CTRL); | |
8775 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8776 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8777 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8778 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8779 | } | |
8780 | ||
dd477003 | 8781 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
80096068 MC |
8782 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
8783 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
8784 | tp->link_config.speed = tp->link_config.orig_speed; |
8785 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8786 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8787 | } | |
1da177e4 | 8788 | |
dd477003 MC |
8789 | err = tg3_setup_phy(tp, 0); |
8790 | if (err) | |
8791 | return err; | |
1da177e4 | 8792 | |
f07e9af3 MC |
8793 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
8794 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
8795 | u32 tmp; |
8796 | ||
8797 | /* Clear CRC stats. */ | |
8798 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8799 | tg3_writephy(tp, MII_TG3_TEST1, | |
8800 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 8801 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 8802 | } |
1da177e4 LT |
8803 | } |
8804 | } | |
8805 | ||
8806 | __tg3_set_rx_mode(tp->dev); | |
8807 | ||
8808 | /* Initialize receive rules. */ | |
8809 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8810 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8811 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8812 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8813 | ||
4cf78e4f | 8814 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
a4e2b347 | 8815 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
1da177e4 LT |
8816 | limit = 8; |
8817 | else | |
8818 | limit = 16; | |
8819 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
8820 | limit -= 4; | |
8821 | switch (limit) { | |
8822 | case 16: | |
8823 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8824 | case 15: | |
8825 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8826 | case 14: | |
8827 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8828 | case 13: | |
8829 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8830 | case 12: | |
8831 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8832 | case 11: | |
8833 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8834 | case 10: | |
8835 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8836 | case 9: | |
8837 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8838 | case 8: | |
8839 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8840 | case 7: | |
8841 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8842 | case 6: | |
8843 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8844 | case 5: | |
8845 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8846 | case 4: | |
8847 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8848 | case 3: | |
8849 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8850 | case 2: | |
8851 | case 1: | |
8852 | ||
8853 | default: | |
8854 | break; | |
855e1111 | 8855 | } |
1da177e4 | 8856 | |
9ce768ea MC |
8857 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
8858 | /* Write our heartbeat update interval to APE. */ | |
8859 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8860 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 8861 | |
1da177e4 LT |
8862 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
8863 | ||
1da177e4 LT |
8864 | return 0; |
8865 | } | |
8866 | ||
8867 | /* Called at device open time to get the chip ready for | |
8868 | * packet processing. Invoked with tp->lock held. | |
8869 | */ | |
8e7a22e3 | 8870 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 8871 | { |
1da177e4 LT |
8872 | tg3_switch_clocks(tp); |
8873 | ||
8874 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8875 | ||
2f751b67 | 8876 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
8877 | } |
8878 | ||
8879 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8880 | do { u32 __val = tr32(REG); \ | |
8881 | (PSTAT)->low += __val; \ | |
8882 | if ((PSTAT)->low < __val) \ | |
8883 | (PSTAT)->high += 1; \ | |
8884 | } while (0) | |
8885 | ||
8886 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8887 | { | |
8888 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8889 | ||
8890 | if (!netif_carrier_ok(tp->dev)) | |
8891 | return; | |
8892 | ||
8893 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
8894 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
8895 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
8896 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
8897 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
8898 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
8899 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
8900 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
8901 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
8902 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
8903 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
8904 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
8905 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
8906 | ||
8907 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
8908 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
8909 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
8910 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
8911 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
8912 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
8913 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
8914 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
8915 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
8916 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
8917 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
8918 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
8919 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
8920 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
8921 | |
8922 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
4d958473 MC |
8923 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) { |
8924 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
8925 | } else { | |
8926 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
8927 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
8928 | if (val) { | |
8929 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
8930 | sp->rx_discards.low += val; | |
8931 | if (sp->rx_discards.low < val) | |
8932 | sp->rx_discards.high += 1; | |
8933 | } | |
8934 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
8935 | } | |
463d305b | 8936 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
8937 | } |
8938 | ||
8939 | static void tg3_timer(unsigned long __opaque) | |
8940 | { | |
8941 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 8942 | |
f475f163 MC |
8943 | if (tp->irq_sync) |
8944 | goto restart_timer; | |
8945 | ||
f47c11ee | 8946 | spin_lock(&tp->lock); |
1da177e4 | 8947 | |
fac9b83e DM |
8948 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { |
8949 | /* All of this garbage is because when using non-tagged | |
8950 | * IRQ status the mailbox/status_block protocol the chip | |
8951 | * uses with the cpu is race prone. | |
8952 | */ | |
898a56f8 | 8953 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
8954 | tw32(GRC_LOCAL_CTRL, |
8955 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
8956 | } else { | |
8957 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 8958 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 8959 | } |
1da177e4 | 8960 | |
fac9b83e DM |
8961 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
8962 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | |
f47c11ee | 8963 | spin_unlock(&tp->lock); |
fac9b83e DM |
8964 | schedule_work(&tp->reset_task); |
8965 | return; | |
8966 | } | |
1da177e4 LT |
8967 | } |
8968 | ||
1da177e4 LT |
8969 | /* This part only runs once per second. */ |
8970 | if (!--tp->timer_counter) { | |
fac9b83e DM |
8971 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
8972 | tg3_periodic_fetch_stats(tp); | |
8973 | ||
52b02d04 MC |
8974 | if (tp->setlpicnt && !--tp->setlpicnt) { |
8975 | u32 val = tr32(TG3_CPMU_EEE_MODE); | |
8976 | tw32(TG3_CPMU_EEE_MODE, | |
8977 | val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
8978 | } | |
8979 | ||
1da177e4 LT |
8980 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
8981 | u32 mac_stat; | |
8982 | int phy_event; | |
8983 | ||
8984 | mac_stat = tr32(MAC_STATUS); | |
8985 | ||
8986 | phy_event = 0; | |
f07e9af3 | 8987 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
8988 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
8989 | phy_event = 1; | |
8990 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
8991 | phy_event = 1; | |
8992 | ||
8993 | if (phy_event) | |
8994 | tg3_setup_phy(tp, 0); | |
8995 | } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { | |
8996 | u32 mac_stat = tr32(MAC_STATUS); | |
8997 | int need_setup = 0; | |
8998 | ||
8999 | if (netif_carrier_ok(tp->dev) && | |
9000 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
9001 | need_setup = 1; | |
9002 | } | |
be98da6a | 9003 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
9004 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
9005 | MAC_STATUS_SIGNAL_DET))) { | |
9006 | need_setup = 1; | |
9007 | } | |
9008 | if (need_setup) { | |
3d3ebe74 MC |
9009 | if (!tp->serdes_counter) { |
9010 | tw32_f(MAC_MODE, | |
9011 | (tp->mac_mode & | |
9012 | ~MAC_MODE_PORT_MODE_MASK)); | |
9013 | udelay(40); | |
9014 | tw32_f(MAC_MODE, tp->mac_mode); | |
9015 | udelay(40); | |
9016 | } | |
1da177e4 LT |
9017 | tg3_setup_phy(tp, 0); |
9018 | } | |
f07e9af3 | 9019 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
2138c002 | 9020 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
747e8f8b | 9021 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 9022 | } |
1da177e4 LT |
9023 | |
9024 | tp->timer_counter = tp->timer_multiplier; | |
9025 | } | |
9026 | ||
130b8e4d MC |
9027 | /* Heartbeat is only sent once every 2 seconds. |
9028 | * | |
9029 | * The heartbeat is to tell the ASF firmware that the host | |
9030 | * driver is still alive. In the event that the OS crashes, | |
9031 | * ASF needs to reset the hardware to free up the FIFO space | |
9032 | * that may be filled with rx packets destined for the host. | |
9033 | * If the FIFO is full, ASF will no longer function properly. | |
9034 | * | |
9035 | * Unintended resets have been reported on real time kernels | |
9036 | * where the timer doesn't run on time. Netpoll will also have | |
9037 | * same problem. | |
9038 | * | |
9039 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
9040 | * to check the ring condition when the heartbeat is expiring | |
9041 | * before doing the reset. This will prevent most unintended | |
9042 | * resets. | |
9043 | */ | |
1da177e4 | 9044 | if (!--tp->asf_counter) { |
bc7959b2 MC |
9045 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
9046 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
9047 | tg3_wait_for_event_ack(tp); |
9048 | ||
bbadf503 | 9049 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 9050 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 9051 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
9052 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
9053 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
9054 | |
9055 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
9056 | } |
9057 | tp->asf_counter = tp->asf_multiplier; | |
9058 | } | |
9059 | ||
f47c11ee | 9060 | spin_unlock(&tp->lock); |
1da177e4 | 9061 | |
f475f163 | 9062 | restart_timer: |
1da177e4 LT |
9063 | tp->timer.expires = jiffies + tp->timer_offset; |
9064 | add_timer(&tp->timer); | |
9065 | } | |
9066 | ||
4f125f42 | 9067 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 9068 | { |
7d12e780 | 9069 | irq_handler_t fn; |
fcfa0a32 | 9070 | unsigned long flags; |
4f125f42 MC |
9071 | char *name; |
9072 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
9073 | ||
9074 | if (tp->irq_cnt == 1) | |
9075 | name = tp->dev->name; | |
9076 | else { | |
9077 | name = &tnapi->irq_lbl[0]; | |
9078 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
9079 | name[IFNAMSIZ-1] = 0; | |
9080 | } | |
fcfa0a32 | 9081 | |
679563f4 | 9082 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { |
fcfa0a32 MC |
9083 | fn = tg3_msi; |
9084 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
9085 | fn = tg3_msi_1shot; | |
ab392d2d | 9086 | flags = 0; |
fcfa0a32 MC |
9087 | } else { |
9088 | fn = tg3_interrupt; | |
9089 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
9090 | fn = tg3_interrupt_tagged; | |
ab392d2d | 9091 | flags = IRQF_SHARED; |
fcfa0a32 | 9092 | } |
4f125f42 MC |
9093 | |
9094 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
9095 | } |
9096 | ||
7938109f MC |
9097 | static int tg3_test_interrupt(struct tg3 *tp) |
9098 | { | |
09943a18 | 9099 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 9100 | struct net_device *dev = tp->dev; |
b16250e3 | 9101 | int err, i, intr_ok = 0; |
f6eb9b1f | 9102 | u32 val; |
7938109f | 9103 | |
d4bc3927 MC |
9104 | if (!netif_running(dev)) |
9105 | return -ENODEV; | |
9106 | ||
7938109f MC |
9107 | tg3_disable_ints(tp); |
9108 | ||
4f125f42 | 9109 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 9110 | |
f6eb9b1f MC |
9111 | /* |
9112 | * Turn off MSI one shot mode. Otherwise this test has no | |
9113 | * observable way to know whether the interrupt was delivered. | |
9114 | */ | |
1407deb1 | 9115 | if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
f6eb9b1f MC |
9116 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
9117 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; | |
9118 | tw32(MSGINT_MODE, val); | |
9119 | } | |
9120 | ||
4f125f42 | 9121 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 9122 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
9123 | if (err) |
9124 | return err; | |
9125 | ||
898a56f8 | 9126 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
9127 | tg3_enable_ints(tp); |
9128 | ||
9129 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 9130 | tnapi->coal_now); |
7938109f MC |
9131 | |
9132 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
9133 | u32 int_mbox, misc_host_ctrl; |
9134 | ||
898a56f8 | 9135 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
9136 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
9137 | ||
9138 | if ((int_mbox != 0) || | |
9139 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
9140 | intr_ok = 1; | |
7938109f | 9141 | break; |
b16250e3 MC |
9142 | } |
9143 | ||
7938109f MC |
9144 | msleep(10); |
9145 | } | |
9146 | ||
9147 | tg3_disable_ints(tp); | |
9148 | ||
4f125f42 | 9149 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 9150 | |
4f125f42 | 9151 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9152 | |
9153 | if (err) | |
9154 | return err; | |
9155 | ||
f6eb9b1f MC |
9156 | if (intr_ok) { |
9157 | /* Reenable MSI one shot mode. */ | |
1407deb1 | 9158 | if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
f6eb9b1f MC |
9159 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
9160 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; | |
9161 | tw32(MSGINT_MODE, val); | |
9162 | } | |
7938109f | 9163 | return 0; |
f6eb9b1f | 9164 | } |
7938109f MC |
9165 | |
9166 | return -EIO; | |
9167 | } | |
9168 | ||
9169 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
9170 | * successfully restored | |
9171 | */ | |
9172 | static int tg3_test_msi(struct tg3 *tp) | |
9173 | { | |
7938109f MC |
9174 | int err; |
9175 | u16 pci_cmd; | |
9176 | ||
9177 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) | |
9178 | return 0; | |
9179 | ||
9180 | /* Turn off SERR reporting in case MSI terminates with Master | |
9181 | * Abort. | |
9182 | */ | |
9183 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
9184 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
9185 | pci_cmd & ~PCI_COMMAND_SERR); | |
9186 | ||
9187 | err = tg3_test_interrupt(tp); | |
9188 | ||
9189 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
9190 | ||
9191 | if (!err) | |
9192 | return 0; | |
9193 | ||
9194 | /* other failures */ | |
9195 | if (err != -EIO) | |
9196 | return err; | |
9197 | ||
9198 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
9199 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
9200 | "to INTx mode. Please report this failure to the PCI " | |
9201 | "maintainer and include system chipset information\n"); | |
7938109f | 9202 | |
4f125f42 | 9203 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 9204 | |
7938109f MC |
9205 | pci_disable_msi(tp->pdev); |
9206 | ||
9207 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
dc8bf1b1 | 9208 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 9209 | |
4f125f42 | 9210 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9211 | if (err) |
9212 | return err; | |
9213 | ||
9214 | /* Need to reset the chip because the MSI cycle may have terminated | |
9215 | * with Master Abort. | |
9216 | */ | |
f47c11ee | 9217 | tg3_full_lock(tp, 1); |
7938109f | 9218 | |
944d980e | 9219 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 9220 | err = tg3_init_hw(tp, 1); |
7938109f | 9221 | |
f47c11ee | 9222 | tg3_full_unlock(tp); |
7938109f MC |
9223 | |
9224 | if (err) | |
4f125f42 | 9225 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
9226 | |
9227 | return err; | |
9228 | } | |
9229 | ||
9e9fd12d MC |
9230 | static int tg3_request_firmware(struct tg3 *tp) |
9231 | { | |
9232 | const __be32 *fw_data; | |
9233 | ||
9234 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
9235 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
9236 | tp->fw_needed); | |
9e9fd12d MC |
9237 | return -ENOENT; |
9238 | } | |
9239 | ||
9240 | fw_data = (void *)tp->fw->data; | |
9241 | ||
9242 | /* Firmware blob starts with version numbers, followed by | |
9243 | * start address and _full_ length including BSS sections | |
9244 | * (which must be longer than the actual data, of course | |
9245 | */ | |
9246 | ||
9247 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9248 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
9249 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
9250 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
9251 | release_firmware(tp->fw); |
9252 | tp->fw = NULL; | |
9253 | return -EINVAL; | |
9254 | } | |
9255 | ||
9256 | /* We no longer need firmware; we have it. */ | |
9257 | tp->fw_needed = NULL; | |
9258 | return 0; | |
9259 | } | |
9260 | ||
679563f4 MC |
9261 | static bool tg3_enable_msix(struct tg3 *tp) |
9262 | { | |
9263 | int i, rc, cpus = num_online_cpus(); | |
9264 | struct msix_entry msix_ent[tp->irq_max]; | |
9265 | ||
9266 | if (cpus == 1) | |
9267 | /* Just fallback to the simpler MSI mode. */ | |
9268 | return false; | |
9269 | ||
9270 | /* | |
9271 | * We want as many rx rings enabled as there are cpus. | |
9272 | * The first MSIX vector only deals with link interrupts, etc, | |
9273 | * so we add one to the number of vectors we are requesting. | |
9274 | */ | |
9275 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9276 | ||
9277 | for (i = 0; i < tp->irq_max; i++) { | |
9278 | msix_ent[i].entry = i; | |
9279 | msix_ent[i].vector = 0; | |
9280 | } | |
9281 | ||
9282 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9283 | if (rc < 0) { |
9284 | return false; | |
9285 | } else if (rc != 0) { | |
679563f4 MC |
9286 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9287 | return false; | |
05dbe005 JP |
9288 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9289 | tp->irq_cnt, rc); | |
679563f4 MC |
9290 | tp->irq_cnt = rc; |
9291 | } | |
9292 | ||
9293 | for (i = 0; i < tp->irq_max; i++) | |
9294 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9295 | ||
2ddaad39 BH |
9296 | netif_set_real_num_tx_queues(tp->dev, 1); |
9297 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9298 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9299 | pci_disable_msix(tp->pdev); | |
9300 | return false; | |
9301 | } | |
b92b9040 MC |
9302 | |
9303 | if (tp->irq_cnt > 1) { | |
2430b031 | 9304 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS; |
d78b59f5 MC |
9305 | |
9306 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9307 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b92b9040 MC |
9308 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS; |
9309 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); | |
9310 | } | |
9311 | } | |
2430b031 | 9312 | |
679563f4 MC |
9313 | return true; |
9314 | } | |
9315 | ||
07b0173c MC |
9316 | static void tg3_ints_init(struct tg3 *tp) |
9317 | { | |
679563f4 MC |
9318 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) && |
9319 | !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
07b0173c MC |
9320 | /* All MSI supporting chips should support tagged |
9321 | * status. Assert that this is the case. | |
9322 | */ | |
5129c3a3 MC |
9323 | netdev_warn(tp->dev, |
9324 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9325 | goto defcfg; |
07b0173c | 9326 | } |
4f125f42 | 9327 | |
679563f4 MC |
9328 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9329 | tp->tg3_flags2 |= TG3_FLG2_USING_MSIX; | |
9330 | else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) && | |
9331 | pci_enable_msi(tp->pdev) == 0) | |
9332 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | |
9333 | ||
9334 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { | |
9335 | u32 msi_mode = tr32(MSGINT_MODE); | |
0583d521 MC |
9336 | if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && |
9337 | tp->irq_cnt > 1) | |
baf8a94a | 9338 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
679563f4 MC |
9339 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9340 | } | |
9341 | defcfg: | |
9342 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { | |
9343 | tp->irq_cnt = 1; | |
9344 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9345 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9346 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9347 | } |
07b0173c MC |
9348 | } |
9349 | ||
9350 | static void tg3_ints_fini(struct tg3 *tp) | |
9351 | { | |
679563f4 MC |
9352 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) |
9353 | pci_disable_msix(tp->pdev); | |
9354 | else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | |
9355 | pci_disable_msi(tp->pdev); | |
9356 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX; | |
774ee752 | 9357 | tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS); |
07b0173c MC |
9358 | } |
9359 | ||
1da177e4 LT |
9360 | static int tg3_open(struct net_device *dev) |
9361 | { | |
9362 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 9363 | int i, err; |
1da177e4 | 9364 | |
9e9fd12d MC |
9365 | if (tp->fw_needed) { |
9366 | err = tg3_request_firmware(tp); | |
9367 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9368 | if (err) | |
9369 | return err; | |
9370 | } else if (err) { | |
05dbe005 | 9371 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
9e9fd12d MC |
9372 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
9373 | } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
05dbe005 | 9374 | netdev_notice(tp->dev, "TSO capability restored\n"); |
9e9fd12d MC |
9375 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
9376 | } | |
9377 | } | |
9378 | ||
c49a1561 MC |
9379 | netif_carrier_off(tp->dev); |
9380 | ||
c866b7ea | 9381 | err = tg3_power_up(tp); |
2f751b67 | 9382 | if (err) |
bc1c7567 | 9383 | return err; |
2f751b67 MC |
9384 | |
9385 | tg3_full_lock(tp, 0); | |
bc1c7567 | 9386 | |
1da177e4 LT |
9387 | tg3_disable_ints(tp); |
9388 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
9389 | ||
f47c11ee | 9390 | tg3_full_unlock(tp); |
1da177e4 | 9391 | |
679563f4 MC |
9392 | /* |
9393 | * Setup interrupts first so we know how | |
9394 | * many NAPI resources to allocate | |
9395 | */ | |
9396 | tg3_ints_init(tp); | |
9397 | ||
1da177e4 LT |
9398 | /* The placement of this call is tied |
9399 | * to the setup and use of Host TX descriptors. | |
9400 | */ | |
9401 | err = tg3_alloc_consistent(tp); | |
9402 | if (err) | |
679563f4 | 9403 | goto err_out1; |
88b06bc2 | 9404 | |
66cfd1bd MC |
9405 | tg3_napi_init(tp); |
9406 | ||
fed97810 | 9407 | tg3_napi_enable(tp); |
1da177e4 | 9408 | |
4f125f42 MC |
9409 | for (i = 0; i < tp->irq_cnt; i++) { |
9410 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9411 | err = tg3_request_irq(tp, i); | |
9412 | if (err) { | |
9413 | for (i--; i >= 0; i--) | |
9414 | free_irq(tnapi->irq_vec, tnapi); | |
9415 | break; | |
9416 | } | |
9417 | } | |
1da177e4 | 9418 | |
07b0173c | 9419 | if (err) |
679563f4 | 9420 | goto err_out2; |
bea3348e | 9421 | |
f47c11ee | 9422 | tg3_full_lock(tp, 0); |
1da177e4 | 9423 | |
8e7a22e3 | 9424 | err = tg3_init_hw(tp, 1); |
1da177e4 | 9425 | if (err) { |
944d980e | 9426 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
9427 | tg3_free_rings(tp); |
9428 | } else { | |
fac9b83e DM |
9429 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) |
9430 | tp->timer_offset = HZ; | |
9431 | else | |
9432 | tp->timer_offset = HZ / 10; | |
9433 | ||
9434 | BUG_ON(tp->timer_offset > HZ); | |
9435 | tp->timer_counter = tp->timer_multiplier = | |
9436 | (HZ / tp->timer_offset); | |
9437 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 9438 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
9439 | |
9440 | init_timer(&tp->timer); | |
9441 | tp->timer.expires = jiffies + tp->timer_offset; | |
9442 | tp->timer.data = (unsigned long) tp; | |
9443 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
9444 | } |
9445 | ||
f47c11ee | 9446 | tg3_full_unlock(tp); |
1da177e4 | 9447 | |
07b0173c | 9448 | if (err) |
679563f4 | 9449 | goto err_out3; |
1da177e4 | 9450 | |
7938109f MC |
9451 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { |
9452 | err = tg3_test_msi(tp); | |
fac9b83e | 9453 | |
7938109f | 9454 | if (err) { |
f47c11ee | 9455 | tg3_full_lock(tp, 0); |
944d980e | 9456 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 9457 | tg3_free_rings(tp); |
f47c11ee | 9458 | tg3_full_unlock(tp); |
7938109f | 9459 | |
679563f4 | 9460 | goto err_out2; |
7938109f | 9461 | } |
fcfa0a32 | 9462 | |
1407deb1 | 9463 | if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
c885e824 | 9464 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
f6eb9b1f | 9465 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 9466 | |
f6eb9b1f MC |
9467 | tw32(PCIE_TRANSACTION_CFG, |
9468 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 9469 | } |
7938109f MC |
9470 | } |
9471 | ||
b02fd9e3 MC |
9472 | tg3_phy_start(tp); |
9473 | ||
f47c11ee | 9474 | tg3_full_lock(tp, 0); |
1da177e4 | 9475 | |
7938109f MC |
9476 | add_timer(&tp->timer); |
9477 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
1da177e4 LT |
9478 | tg3_enable_ints(tp); |
9479 | ||
f47c11ee | 9480 | tg3_full_unlock(tp); |
1da177e4 | 9481 | |
fe5f5787 | 9482 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
9483 | |
9484 | return 0; | |
07b0173c | 9485 | |
679563f4 | 9486 | err_out3: |
4f125f42 MC |
9487 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9488 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9489 | free_irq(tnapi->irq_vec, tnapi); | |
9490 | } | |
07b0173c | 9491 | |
679563f4 | 9492 | err_out2: |
fed97810 | 9493 | tg3_napi_disable(tp); |
66cfd1bd | 9494 | tg3_napi_fini(tp); |
07b0173c | 9495 | tg3_free_consistent(tp); |
679563f4 MC |
9496 | |
9497 | err_out1: | |
9498 | tg3_ints_fini(tp); | |
07b0173c | 9499 | return err; |
1da177e4 LT |
9500 | } |
9501 | ||
511d2224 ED |
9502 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
9503 | struct rtnl_link_stats64 *); | |
1da177e4 LT |
9504 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); |
9505 | ||
9506 | static int tg3_close(struct net_device *dev) | |
9507 | { | |
4f125f42 | 9508 | int i; |
1da177e4 LT |
9509 | struct tg3 *tp = netdev_priv(dev); |
9510 | ||
fed97810 | 9511 | tg3_napi_disable(tp); |
28e53bdd | 9512 | cancel_work_sync(&tp->reset_task); |
7faa006f | 9513 | |
fe5f5787 | 9514 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
9515 | |
9516 | del_timer_sync(&tp->timer); | |
9517 | ||
24bb4fb6 MC |
9518 | tg3_phy_stop(tp); |
9519 | ||
f47c11ee | 9520 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9521 | |
9522 | tg3_disable_ints(tp); | |
9523 | ||
944d980e | 9524 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9525 | tg3_free_rings(tp); |
5cf64b8a | 9526 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
1da177e4 | 9527 | |
f47c11ee | 9528 | tg3_full_unlock(tp); |
1da177e4 | 9529 | |
4f125f42 MC |
9530 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9531 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9532 | free_irq(tnapi->irq_vec, tnapi); | |
9533 | } | |
07b0173c MC |
9534 | |
9535 | tg3_ints_fini(tp); | |
1da177e4 | 9536 | |
511d2224 ED |
9537 | tg3_get_stats64(tp->dev, &tp->net_stats_prev); |
9538 | ||
1da177e4 LT |
9539 | memcpy(&tp->estats_prev, tg3_get_estats(tp), |
9540 | sizeof(tp->estats_prev)); | |
9541 | ||
66cfd1bd MC |
9542 | tg3_napi_fini(tp); |
9543 | ||
1da177e4 LT |
9544 | tg3_free_consistent(tp); |
9545 | ||
c866b7ea | 9546 | tg3_power_down(tp); |
bc1c7567 MC |
9547 | |
9548 | netif_carrier_off(tp->dev); | |
9549 | ||
1da177e4 LT |
9550 | return 0; |
9551 | } | |
9552 | ||
511d2224 | 9553 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
9554 | { |
9555 | return ((u64)val->high << 32) | ((u64)val->low); | |
9556 | } | |
9557 | ||
511d2224 | 9558 | static u64 calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
9559 | { |
9560 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9561 | ||
f07e9af3 | 9562 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
9563 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
9564 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9565 | u32 val; |
9566 | ||
f47c11ee | 9567 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9568 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9569 | tg3_writephy(tp, MII_TG3_TEST1, | |
9570 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9571 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
9572 | } else |
9573 | val = 0; | |
f47c11ee | 9574 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9575 | |
9576 | tp->phy_crc_errors += val; | |
9577 | ||
9578 | return tp->phy_crc_errors; | |
9579 | } | |
9580 | ||
9581 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9582 | } | |
9583 | ||
9584 | #define ESTAT_ADD(member) \ | |
9585 | estats->member = old_estats->member + \ | |
511d2224 | 9586 | get_stat64(&hw_stats->member) |
1da177e4 LT |
9587 | |
9588 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9589 | { | |
9590 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9591 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9592 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9593 | ||
9594 | if (!hw_stats) | |
9595 | return old_estats; | |
9596 | ||
9597 | ESTAT_ADD(rx_octets); | |
9598 | ESTAT_ADD(rx_fragments); | |
9599 | ESTAT_ADD(rx_ucast_packets); | |
9600 | ESTAT_ADD(rx_mcast_packets); | |
9601 | ESTAT_ADD(rx_bcast_packets); | |
9602 | ESTAT_ADD(rx_fcs_errors); | |
9603 | ESTAT_ADD(rx_align_errors); | |
9604 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9605 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9606 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9607 | ESTAT_ADD(rx_xoff_entered); | |
9608 | ESTAT_ADD(rx_frame_too_long_errors); | |
9609 | ESTAT_ADD(rx_jabbers); | |
9610 | ESTAT_ADD(rx_undersize_packets); | |
9611 | ESTAT_ADD(rx_in_length_errors); | |
9612 | ESTAT_ADD(rx_out_length_errors); | |
9613 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9614 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9615 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9616 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9617 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9618 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9619 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9620 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9621 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9622 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9623 | ||
9624 | ESTAT_ADD(tx_octets); | |
9625 | ESTAT_ADD(tx_collisions); | |
9626 | ESTAT_ADD(tx_xon_sent); | |
9627 | ESTAT_ADD(tx_xoff_sent); | |
9628 | ESTAT_ADD(tx_flow_control); | |
9629 | ESTAT_ADD(tx_mac_errors); | |
9630 | ESTAT_ADD(tx_single_collisions); | |
9631 | ESTAT_ADD(tx_mult_collisions); | |
9632 | ESTAT_ADD(tx_deferred); | |
9633 | ESTAT_ADD(tx_excessive_collisions); | |
9634 | ESTAT_ADD(tx_late_collisions); | |
9635 | ESTAT_ADD(tx_collide_2times); | |
9636 | ESTAT_ADD(tx_collide_3times); | |
9637 | ESTAT_ADD(tx_collide_4times); | |
9638 | ESTAT_ADD(tx_collide_5times); | |
9639 | ESTAT_ADD(tx_collide_6times); | |
9640 | ESTAT_ADD(tx_collide_7times); | |
9641 | ESTAT_ADD(tx_collide_8times); | |
9642 | ESTAT_ADD(tx_collide_9times); | |
9643 | ESTAT_ADD(tx_collide_10times); | |
9644 | ESTAT_ADD(tx_collide_11times); | |
9645 | ESTAT_ADD(tx_collide_12times); | |
9646 | ESTAT_ADD(tx_collide_13times); | |
9647 | ESTAT_ADD(tx_collide_14times); | |
9648 | ESTAT_ADD(tx_collide_15times); | |
9649 | ESTAT_ADD(tx_ucast_packets); | |
9650 | ESTAT_ADD(tx_mcast_packets); | |
9651 | ESTAT_ADD(tx_bcast_packets); | |
9652 | ESTAT_ADD(tx_carrier_sense_errors); | |
9653 | ESTAT_ADD(tx_discards); | |
9654 | ESTAT_ADD(tx_errors); | |
9655 | ||
9656 | ESTAT_ADD(dma_writeq_full); | |
9657 | ESTAT_ADD(dma_write_prioq_full); | |
9658 | ESTAT_ADD(rxbds_empty); | |
9659 | ESTAT_ADD(rx_discards); | |
9660 | ESTAT_ADD(rx_errors); | |
9661 | ESTAT_ADD(rx_threshold_hit); | |
9662 | ||
9663 | ESTAT_ADD(dma_readq_full); | |
9664 | ESTAT_ADD(dma_read_prioq_full); | |
9665 | ESTAT_ADD(tx_comp_queue_full); | |
9666 | ||
9667 | ESTAT_ADD(ring_set_send_prod_index); | |
9668 | ESTAT_ADD(ring_status_update); | |
9669 | ESTAT_ADD(nic_irqs); | |
9670 | ESTAT_ADD(nic_avoided_irqs); | |
9671 | ESTAT_ADD(nic_tx_threshold_hit); | |
9672 | ||
9673 | return estats; | |
9674 | } | |
9675 | ||
511d2224 ED |
9676 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
9677 | struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
9678 | { |
9679 | struct tg3 *tp = netdev_priv(dev); | |
511d2224 | 9680 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
9681 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
9682 | ||
9683 | if (!hw_stats) | |
9684 | return old_stats; | |
9685 | ||
9686 | stats->rx_packets = old_stats->rx_packets + | |
9687 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9688 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9689 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9690 | |
1da177e4 LT |
9691 | stats->tx_packets = old_stats->tx_packets + |
9692 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9693 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9694 | get_stat64(&hw_stats->tx_bcast_packets); | |
9695 | ||
9696 | stats->rx_bytes = old_stats->rx_bytes + | |
9697 | get_stat64(&hw_stats->rx_octets); | |
9698 | stats->tx_bytes = old_stats->tx_bytes + | |
9699 | get_stat64(&hw_stats->tx_octets); | |
9700 | ||
9701 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9702 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9703 | stats->tx_errors = old_stats->tx_errors + |
9704 | get_stat64(&hw_stats->tx_errors) + | |
9705 | get_stat64(&hw_stats->tx_mac_errors) + | |
9706 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9707 | get_stat64(&hw_stats->tx_discards); | |
9708 | ||
9709 | stats->multicast = old_stats->multicast + | |
9710 | get_stat64(&hw_stats->rx_mcast_packets); | |
9711 | stats->collisions = old_stats->collisions + | |
9712 | get_stat64(&hw_stats->tx_collisions); | |
9713 | ||
9714 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9715 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9716 | get_stat64(&hw_stats->rx_undersize_packets); | |
9717 | ||
9718 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9719 | get_stat64(&hw_stats->rxbds_empty); | |
9720 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9721 | get_stat64(&hw_stats->rx_align_errors); | |
9722 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9723 | get_stat64(&hw_stats->tx_discards); | |
9724 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9725 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9726 | ||
9727 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9728 | calc_crc_errors(tp); | |
9729 | ||
4f63b877 JL |
9730 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
9731 | get_stat64(&hw_stats->rx_discards); | |
9732 | ||
b0057c51 ED |
9733 | stats->rx_dropped = tp->rx_dropped; |
9734 | ||
1da177e4 LT |
9735 | return stats; |
9736 | } | |
9737 | ||
9738 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9739 | { | |
9740 | u32 reg; | |
9741 | u32 tmp; | |
9742 | int j, k; | |
9743 | ||
9744 | reg = 0xffffffff; | |
9745 | ||
9746 | for (j = 0; j < len; j++) { | |
9747 | reg ^= buf[j]; | |
9748 | ||
9749 | for (k = 0; k < 8; k++) { | |
9750 | tmp = reg & 0x01; | |
9751 | ||
9752 | reg >>= 1; | |
9753 | ||
859a5887 | 9754 | if (tmp) |
1da177e4 | 9755 | reg ^= 0xedb88320; |
1da177e4 LT |
9756 | } |
9757 | } | |
9758 | ||
9759 | return ~reg; | |
9760 | } | |
9761 | ||
9762 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9763 | { | |
9764 | /* accept or reject all multicast frames */ | |
9765 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9766 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9767 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9768 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9769 | } | |
9770 | ||
9771 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9772 | { | |
9773 | struct tg3 *tp = netdev_priv(dev); | |
9774 | u32 rx_mode; | |
9775 | ||
9776 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9777 | RX_MODE_KEEP_VLAN_TAG); | |
9778 | ||
bf933c80 | 9779 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
1da177e4 LT |
9780 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
9781 | * flag clear. | |
9782 | */ | |
1da177e4 LT |
9783 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
9784 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9785 | #endif | |
9786 | ||
9787 | if (dev->flags & IFF_PROMISC) { | |
9788 | /* Promiscuous mode. */ | |
9789 | rx_mode |= RX_MODE_PROMISC; | |
9790 | } else if (dev->flags & IFF_ALLMULTI) { | |
9791 | /* Accept all multicast. */ | |
de6f31eb | 9792 | tg3_set_multi(tp, 1); |
4cd24eaf | 9793 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 9794 | /* Reject all multicast. */ |
de6f31eb | 9795 | tg3_set_multi(tp, 0); |
1da177e4 LT |
9796 | } else { |
9797 | /* Accept one or more multicast(s). */ | |
22bedad3 | 9798 | struct netdev_hw_addr *ha; |
1da177e4 LT |
9799 | u32 mc_filter[4] = { 0, }; |
9800 | u32 regidx; | |
9801 | u32 bit; | |
9802 | u32 crc; | |
9803 | ||
22bedad3 JP |
9804 | netdev_for_each_mc_addr(ha, dev) { |
9805 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
9806 | bit = ~crc & 0x7f; |
9807 | regidx = (bit & 0x60) >> 5; | |
9808 | bit &= 0x1f; | |
9809 | mc_filter[regidx] |= (1 << bit); | |
9810 | } | |
9811 | ||
9812 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9813 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9814 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9815 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9816 | } | |
9817 | ||
9818 | if (rx_mode != tp->rx_mode) { | |
9819 | tp->rx_mode = rx_mode; | |
9820 | tw32_f(MAC_RX_MODE, rx_mode); | |
9821 | udelay(10); | |
9822 | } | |
9823 | } | |
9824 | ||
9825 | static void tg3_set_rx_mode(struct net_device *dev) | |
9826 | { | |
9827 | struct tg3 *tp = netdev_priv(dev); | |
9828 | ||
e75f7c90 MC |
9829 | if (!netif_running(dev)) |
9830 | return; | |
9831 | ||
f47c11ee | 9832 | tg3_full_lock(tp, 0); |
1da177e4 | 9833 | __tg3_set_rx_mode(dev); |
f47c11ee | 9834 | tg3_full_unlock(tp); |
1da177e4 LT |
9835 | } |
9836 | ||
1da177e4 LT |
9837 | static int tg3_get_regs_len(struct net_device *dev) |
9838 | { | |
97bd8e49 | 9839 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
9840 | } |
9841 | ||
9842 | static void tg3_get_regs(struct net_device *dev, | |
9843 | struct ethtool_regs *regs, void *_p) | |
9844 | { | |
1da177e4 | 9845 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
9846 | |
9847 | regs->version = 0; | |
9848 | ||
97bd8e49 | 9849 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 9850 | |
80096068 | 9851 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9852 | return; |
9853 | ||
f47c11ee | 9854 | tg3_full_lock(tp, 0); |
1da177e4 | 9855 | |
97bd8e49 | 9856 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 9857 | |
f47c11ee | 9858 | tg3_full_unlock(tp); |
1da177e4 LT |
9859 | } |
9860 | ||
9861 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9862 | { | |
9863 | struct tg3 *tp = netdev_priv(dev); | |
9864 | ||
9865 | return tp->nvram_size; | |
9866 | } | |
9867 | ||
1da177e4 LT |
9868 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
9869 | { | |
9870 | struct tg3 *tp = netdev_priv(dev); | |
9871 | int ret; | |
9872 | u8 *pd; | |
b9fc7dc5 | 9873 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 9874 | __be32 val; |
1da177e4 | 9875 | |
df259d8c MC |
9876 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
9877 | return -EINVAL; | |
9878 | ||
80096068 | 9879 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9880 | return -EAGAIN; |
9881 | ||
1da177e4 LT |
9882 | offset = eeprom->offset; |
9883 | len = eeprom->len; | |
9884 | eeprom->len = 0; | |
9885 | ||
9886 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9887 | ||
9888 | if (offset & 3) { | |
9889 | /* adjustments to start on required 4 byte boundary */ | |
9890 | b_offset = offset & 3; | |
9891 | b_count = 4 - b_offset; | |
9892 | if (b_count > len) { | |
9893 | /* i.e. offset=1 len=2 */ | |
9894 | b_count = len; | |
9895 | } | |
a9dc529d | 9896 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
9897 | if (ret) |
9898 | return ret; | |
be98da6a | 9899 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
9900 | len -= b_count; |
9901 | offset += b_count; | |
c6cdf436 | 9902 | eeprom->len += b_count; |
1da177e4 LT |
9903 | } |
9904 | ||
25985edc | 9905 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
9906 | pd = &data[eeprom->len]; |
9907 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 9908 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
9909 | if (ret) { |
9910 | eeprom->len += i; | |
9911 | return ret; | |
9912 | } | |
1da177e4 LT |
9913 | memcpy(pd + i, &val, 4); |
9914 | } | |
9915 | eeprom->len += i; | |
9916 | ||
9917 | if (len & 3) { | |
9918 | /* read last bytes not ending on 4 byte boundary */ | |
9919 | pd = &data[eeprom->len]; | |
9920 | b_count = len & 3; | |
9921 | b_offset = offset + len - b_count; | |
a9dc529d | 9922 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
9923 | if (ret) |
9924 | return ret; | |
b9fc7dc5 | 9925 | memcpy(pd, &val, b_count); |
1da177e4 LT |
9926 | eeprom->len += b_count; |
9927 | } | |
9928 | return 0; | |
9929 | } | |
9930 | ||
6aa20a22 | 9931 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
9932 | |
9933 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9934 | { | |
9935 | struct tg3 *tp = netdev_priv(dev); | |
9936 | int ret; | |
b9fc7dc5 | 9937 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 9938 | u8 *buf; |
a9dc529d | 9939 | __be32 start, end; |
1da177e4 | 9940 | |
80096068 | 9941 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9942 | return -EAGAIN; |
9943 | ||
df259d8c MC |
9944 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
9945 | eeprom->magic != TG3_EEPROM_MAGIC) | |
1da177e4 LT |
9946 | return -EINVAL; |
9947 | ||
9948 | offset = eeprom->offset; | |
9949 | len = eeprom->len; | |
9950 | ||
9951 | if ((b_offset = (offset & 3))) { | |
9952 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 9953 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
9954 | if (ret) |
9955 | return ret; | |
1da177e4 LT |
9956 | len += b_offset; |
9957 | offset &= ~3; | |
1c8594b4 MC |
9958 | if (len < 4) |
9959 | len = 4; | |
1da177e4 LT |
9960 | } |
9961 | ||
9962 | odd_len = 0; | |
1c8594b4 | 9963 | if (len & 3) { |
1da177e4 LT |
9964 | /* adjustments to end on required 4 byte boundary */ |
9965 | odd_len = 1; | |
9966 | len = (len + 3) & ~3; | |
a9dc529d | 9967 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
9968 | if (ret) |
9969 | return ret; | |
1da177e4 LT |
9970 | } |
9971 | ||
9972 | buf = data; | |
9973 | if (b_offset || odd_len) { | |
9974 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 9975 | if (!buf) |
1da177e4 LT |
9976 | return -ENOMEM; |
9977 | if (b_offset) | |
9978 | memcpy(buf, &start, 4); | |
9979 | if (odd_len) | |
9980 | memcpy(buf+len-4, &end, 4); | |
9981 | memcpy(buf + b_offset, data, eeprom->len); | |
9982 | } | |
9983 | ||
9984 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
9985 | ||
9986 | if (buf != data) | |
9987 | kfree(buf); | |
9988 | ||
9989 | return ret; | |
9990 | } | |
9991 | ||
9992 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9993 | { | |
b02fd9e3 MC |
9994 | struct tg3 *tp = netdev_priv(dev); |
9995 | ||
9996 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
3f0e3ad7 | 9997 | struct phy_device *phydev; |
f07e9af3 | 9998 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 9999 | return -EAGAIN; |
3f0e3ad7 MC |
10000 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10001 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 10002 | } |
6aa20a22 | 10003 | |
1da177e4 LT |
10004 | cmd->supported = (SUPPORTED_Autoneg); |
10005 | ||
f07e9af3 | 10006 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
10007 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
10008 | SUPPORTED_1000baseT_Full); | |
10009 | ||
f07e9af3 | 10010 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
10011 | cmd->supported |= (SUPPORTED_100baseT_Half | |
10012 | SUPPORTED_100baseT_Full | | |
10013 | SUPPORTED_10baseT_Half | | |
10014 | SUPPORTED_10baseT_Full | | |
3bebab59 | 10015 | SUPPORTED_TP); |
ef348144 KK |
10016 | cmd->port = PORT_TP; |
10017 | } else { | |
1da177e4 | 10018 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
10019 | cmd->port = PORT_FIBRE; |
10020 | } | |
6aa20a22 | 10021 | |
1da177e4 LT |
10022 | cmd->advertising = tp->link_config.advertising; |
10023 | if (netif_running(dev)) { | |
10024 | cmd->speed = tp->link_config.active_speed; | |
10025 | cmd->duplex = tp->link_config.active_duplex; | |
64c22182 MC |
10026 | } else { |
10027 | cmd->speed = SPEED_INVALID; | |
10028 | cmd->duplex = DUPLEX_INVALID; | |
1da177e4 | 10029 | } |
882e9793 | 10030 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 10031 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
10032 | cmd->autoneg = tp->link_config.autoneg; |
10033 | cmd->maxtxpkt = 0; | |
10034 | cmd->maxrxpkt = 0; | |
10035 | return 0; | |
10036 | } | |
6aa20a22 | 10037 | |
1da177e4 LT |
10038 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
10039 | { | |
10040 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10041 | |
b02fd9e3 | 10042 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 10043 | struct phy_device *phydev; |
f07e9af3 | 10044 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10045 | return -EAGAIN; |
3f0e3ad7 MC |
10046 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10047 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
10048 | } |
10049 | ||
7e5856bd MC |
10050 | if (cmd->autoneg != AUTONEG_ENABLE && |
10051 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 10052 | return -EINVAL; |
7e5856bd MC |
10053 | |
10054 | if (cmd->autoneg == AUTONEG_DISABLE && | |
10055 | cmd->duplex != DUPLEX_FULL && | |
10056 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 10057 | return -EINVAL; |
1da177e4 | 10058 | |
7e5856bd MC |
10059 | if (cmd->autoneg == AUTONEG_ENABLE) { |
10060 | u32 mask = ADVERTISED_Autoneg | | |
10061 | ADVERTISED_Pause | | |
10062 | ADVERTISED_Asym_Pause; | |
10063 | ||
f07e9af3 | 10064 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
10065 | mask |= ADVERTISED_1000baseT_Half | |
10066 | ADVERTISED_1000baseT_Full; | |
10067 | ||
f07e9af3 | 10068 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
10069 | mask |= ADVERTISED_100baseT_Half | |
10070 | ADVERTISED_100baseT_Full | | |
10071 | ADVERTISED_10baseT_Half | | |
10072 | ADVERTISED_10baseT_Full | | |
10073 | ADVERTISED_TP; | |
10074 | else | |
10075 | mask |= ADVERTISED_FIBRE; | |
10076 | ||
10077 | if (cmd->advertising & ~mask) | |
10078 | return -EINVAL; | |
10079 | ||
10080 | mask &= (ADVERTISED_1000baseT_Half | | |
10081 | ADVERTISED_1000baseT_Full | | |
10082 | ADVERTISED_100baseT_Half | | |
10083 | ADVERTISED_100baseT_Full | | |
10084 | ADVERTISED_10baseT_Half | | |
10085 | ADVERTISED_10baseT_Full); | |
10086 | ||
10087 | cmd->advertising &= mask; | |
10088 | } else { | |
f07e9af3 | 10089 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
7e5856bd MC |
10090 | if (cmd->speed != SPEED_1000) |
10091 | return -EINVAL; | |
10092 | ||
10093 | if (cmd->duplex != DUPLEX_FULL) | |
10094 | return -EINVAL; | |
10095 | } else { | |
10096 | if (cmd->speed != SPEED_100 && | |
10097 | cmd->speed != SPEED_10) | |
10098 | return -EINVAL; | |
10099 | } | |
10100 | } | |
10101 | ||
f47c11ee | 10102 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10103 | |
10104 | tp->link_config.autoneg = cmd->autoneg; | |
10105 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
10106 | tp->link_config.advertising = (cmd->advertising | |
10107 | ADVERTISED_Autoneg); | |
1da177e4 LT |
10108 | tp->link_config.speed = SPEED_INVALID; |
10109 | tp->link_config.duplex = DUPLEX_INVALID; | |
10110 | } else { | |
10111 | tp->link_config.advertising = 0; | |
10112 | tp->link_config.speed = cmd->speed; | |
10113 | tp->link_config.duplex = cmd->duplex; | |
b02fd9e3 | 10114 | } |
6aa20a22 | 10115 | |
24fcad6b MC |
10116 | tp->link_config.orig_speed = tp->link_config.speed; |
10117 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
10118 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
10119 | ||
1da177e4 LT |
10120 | if (netif_running(dev)) |
10121 | tg3_setup_phy(tp, 1); | |
10122 | ||
f47c11ee | 10123 | tg3_full_unlock(tp); |
6aa20a22 | 10124 | |
1da177e4 LT |
10125 | return 0; |
10126 | } | |
6aa20a22 | 10127 | |
1da177e4 LT |
10128 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
10129 | { | |
10130 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10131 | |
1da177e4 LT |
10132 | strcpy(info->driver, DRV_MODULE_NAME); |
10133 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 10134 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
10135 | strcpy(info->bus_info, pci_name(tp->pdev)); |
10136 | } | |
6aa20a22 | 10137 | |
1da177e4 LT |
10138 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10139 | { | |
10140 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10141 | |
12dac075 RW |
10142 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
10143 | device_can_wakeup(&tp->pdev->dev)) | |
a85feb8c GZ |
10144 | wol->supported = WAKE_MAGIC; |
10145 | else | |
10146 | wol->supported = 0; | |
1da177e4 | 10147 | wol->wolopts = 0; |
05ac4cb7 MC |
10148 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && |
10149 | device_can_wakeup(&tp->pdev->dev)) | |
1da177e4 LT |
10150 | wol->wolopts = WAKE_MAGIC; |
10151 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
10152 | } | |
6aa20a22 | 10153 | |
1da177e4 LT |
10154 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10155 | { | |
10156 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 10157 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 10158 | |
1da177e4 LT |
10159 | if (wol->wolopts & ~WAKE_MAGIC) |
10160 | return -EINVAL; | |
10161 | if ((wol->wolopts & WAKE_MAGIC) && | |
12dac075 | 10162 | !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 10163 | return -EINVAL; |
6aa20a22 | 10164 | |
f2dc0d18 RW |
10165 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
10166 | ||
f47c11ee | 10167 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 10168 | if (device_may_wakeup(dp)) |
1da177e4 | 10169 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
f2dc0d18 | 10170 | else |
1da177e4 | 10171 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; |
f47c11ee | 10172 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10173 | |
f2dc0d18 | 10174 | |
1da177e4 LT |
10175 | return 0; |
10176 | } | |
6aa20a22 | 10177 | |
1da177e4 LT |
10178 | static u32 tg3_get_msglevel(struct net_device *dev) |
10179 | { | |
10180 | struct tg3 *tp = netdev_priv(dev); | |
10181 | return tp->msg_enable; | |
10182 | } | |
6aa20a22 | 10183 | |
1da177e4 LT |
10184 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
10185 | { | |
10186 | struct tg3 *tp = netdev_priv(dev); | |
10187 | tp->msg_enable = value; | |
10188 | } | |
6aa20a22 | 10189 | |
1da177e4 LT |
10190 | static int tg3_nway_reset(struct net_device *dev) |
10191 | { | |
10192 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10193 | int r; |
6aa20a22 | 10194 | |
1da177e4 LT |
10195 | if (!netif_running(dev)) |
10196 | return -EAGAIN; | |
10197 | ||
f07e9af3 | 10198 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10199 | return -EINVAL; |
10200 | ||
b02fd9e3 | 10201 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
f07e9af3 | 10202 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10203 | return -EAGAIN; |
3f0e3ad7 | 10204 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10205 | } else { |
10206 | u32 bmcr; | |
10207 | ||
10208 | spin_lock_bh(&tp->lock); | |
10209 | r = -EINVAL; | |
10210 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10211 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10212 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10213 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10214 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10215 | BMCR_ANENABLE); | |
10216 | r = 0; | |
10217 | } | |
10218 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10219 | } |
6aa20a22 | 10220 | |
1da177e4 LT |
10221 | return r; |
10222 | } | |
6aa20a22 | 10223 | |
1da177e4 LT |
10224 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10225 | { | |
10226 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10227 | |
2c49a44d | 10228 | ering->rx_max_pending = tp->rx_std_ring_mask; |
1da177e4 | 10229 | ering->rx_mini_max_pending = 0; |
4f81c32b | 10230 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
2c49a44d | 10231 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10232 | else |
10233 | ering->rx_jumbo_max_pending = 0; | |
10234 | ||
10235 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10236 | |
10237 | ering->rx_pending = tp->rx_pending; | |
10238 | ering->rx_mini_pending = 0; | |
4f81c32b MC |
10239 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
10240 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
10241 | else | |
10242 | ering->rx_jumbo_pending = 0; | |
10243 | ||
f3f3f27e | 10244 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10245 | } |
6aa20a22 | 10246 | |
1da177e4 LT |
10247 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10248 | { | |
10249 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10250 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10251 | |
2c49a44d MC |
10252 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10253 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10254 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10255 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
7f62ad5d | 10256 | ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && |
bc3a9254 | 10257 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10258 | return -EINVAL; |
6aa20a22 | 10259 | |
bbe832c0 | 10260 | if (netif_running(dev)) { |
b02fd9e3 | 10261 | tg3_phy_stop(tp); |
1da177e4 | 10262 | tg3_netif_stop(tp); |
bbe832c0 MC |
10263 | irq_sync = 1; |
10264 | } | |
1da177e4 | 10265 | |
bbe832c0 | 10266 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10267 | |
1da177e4 LT |
10268 | tp->rx_pending = ering->rx_pending; |
10269 | ||
10270 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | |
10271 | tp->rx_pending > 63) | |
10272 | tp->rx_pending = 63; | |
10273 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10274 | |
6fd45cb8 | 10275 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10276 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10277 | |
10278 | if (netif_running(dev)) { | |
944d980e | 10279 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10280 | err = tg3_restart_hw(tp, 1); |
10281 | if (!err) | |
10282 | tg3_netif_start(tp); | |
1da177e4 LT |
10283 | } |
10284 | ||
f47c11ee | 10285 | tg3_full_unlock(tp); |
6aa20a22 | 10286 | |
b02fd9e3 MC |
10287 | if (irq_sync && !err) |
10288 | tg3_phy_start(tp); | |
10289 | ||
b9ec6c1b | 10290 | return err; |
1da177e4 | 10291 | } |
6aa20a22 | 10292 | |
1da177e4 LT |
10293 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10294 | { | |
10295 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10296 | |
1da177e4 | 10297 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; |
8d018621 | 10298 | |
e18ce346 | 10299 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10300 | epause->rx_pause = 1; |
10301 | else | |
10302 | epause->rx_pause = 0; | |
10303 | ||
e18ce346 | 10304 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10305 | epause->tx_pause = 1; |
10306 | else | |
10307 | epause->tx_pause = 0; | |
1da177e4 | 10308 | } |
6aa20a22 | 10309 | |
1da177e4 LT |
10310 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10311 | { | |
10312 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10313 | int err = 0; |
6aa20a22 | 10314 | |
b02fd9e3 | 10315 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
2712168f MC |
10316 | u32 newadv; |
10317 | struct phy_device *phydev; | |
1da177e4 | 10318 | |
2712168f | 10319 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10320 | |
2712168f MC |
10321 | if (!(phydev->supported & SUPPORTED_Pause) || |
10322 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10323 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10324 | return -EINVAL; |
1da177e4 | 10325 | |
2712168f MC |
10326 | tp->link_config.flowctrl = 0; |
10327 | if (epause->rx_pause) { | |
10328 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10329 | ||
10330 | if (epause->tx_pause) { | |
10331 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10332 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10333 | } else |
2712168f MC |
10334 | newadv = ADVERTISED_Pause | |
10335 | ADVERTISED_Asym_Pause; | |
10336 | } else if (epause->tx_pause) { | |
10337 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10338 | newadv = ADVERTISED_Asym_Pause; | |
10339 | } else | |
10340 | newadv = 0; | |
10341 | ||
10342 | if (epause->autoneg) | |
10343 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
10344 | else | |
10345 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
10346 | ||
f07e9af3 | 10347 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10348 | u32 oldadv = phydev->advertising & |
10349 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10350 | if (oldadv != newadv) { | |
10351 | phydev->advertising &= | |
10352 | ~(ADVERTISED_Pause | | |
10353 | ADVERTISED_Asym_Pause); | |
10354 | phydev->advertising |= newadv; | |
10355 | if (phydev->autoneg) { | |
10356 | /* | |
10357 | * Always renegotiate the link to | |
10358 | * inform our link partner of our | |
10359 | * flow control settings, even if the | |
10360 | * flow control is forced. Let | |
10361 | * tg3_adjust_link() do the final | |
10362 | * flow control setup. | |
10363 | */ | |
10364 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10365 | } |
b02fd9e3 | 10366 | } |
b02fd9e3 | 10367 | |
2712168f | 10368 | if (!epause->autoneg) |
b02fd9e3 | 10369 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
10370 | } else { |
10371 | tp->link_config.orig_advertising &= | |
10372 | ~(ADVERTISED_Pause | | |
10373 | ADVERTISED_Asym_Pause); | |
10374 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
10375 | } |
10376 | } else { | |
10377 | int irq_sync = 0; | |
10378 | ||
10379 | if (netif_running(dev)) { | |
10380 | tg3_netif_stop(tp); | |
10381 | irq_sync = 1; | |
10382 | } | |
10383 | ||
10384 | tg3_full_lock(tp, irq_sync); | |
10385 | ||
10386 | if (epause->autoneg) | |
10387 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
10388 | else | |
10389 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
10390 | if (epause->rx_pause) | |
e18ce346 | 10391 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10392 | else |
e18ce346 | 10393 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10394 | if (epause->tx_pause) |
e18ce346 | 10395 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10396 | else |
e18ce346 | 10397 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10398 | |
10399 | if (netif_running(dev)) { | |
10400 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10401 | err = tg3_restart_hw(tp, 1); | |
10402 | if (!err) | |
10403 | tg3_netif_start(tp); | |
10404 | } | |
10405 | ||
10406 | tg3_full_unlock(tp); | |
10407 | } | |
6aa20a22 | 10408 | |
b9ec6c1b | 10409 | return err; |
1da177e4 | 10410 | } |
6aa20a22 | 10411 | |
de6f31eb | 10412 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10413 | { |
b9f2c044 JG |
10414 | switch (sset) { |
10415 | case ETH_SS_TEST: | |
10416 | return TG3_NUM_TEST; | |
10417 | case ETH_SS_STATS: | |
10418 | return TG3_NUM_STATS; | |
10419 | default: | |
10420 | return -EOPNOTSUPP; | |
10421 | } | |
4cafd3f5 MC |
10422 | } |
10423 | ||
de6f31eb | 10424 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10425 | { |
10426 | switch (stringset) { | |
10427 | case ETH_SS_STATS: | |
10428 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10429 | break; | |
4cafd3f5 MC |
10430 | case ETH_SS_TEST: |
10431 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10432 | break; | |
1da177e4 LT |
10433 | default: |
10434 | WARN_ON(1); /* we need a WARN() */ | |
10435 | break; | |
10436 | } | |
10437 | } | |
10438 | ||
81b8709c | 10439 | static int tg3_set_phys_id(struct net_device *dev, |
10440 | enum ethtool_phys_id_state state) | |
4009a93d MC |
10441 | { |
10442 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
10443 | |
10444 | if (!netif_running(tp->dev)) | |
10445 | return -EAGAIN; | |
10446 | ||
81b8709c | 10447 | switch (state) { |
10448 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 10449 | return 1; /* cycle on/off once per second */ |
4009a93d | 10450 | |
81b8709c | 10451 | case ETHTOOL_ID_ON: |
10452 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10453 | LED_CTRL_1000MBPS_ON | | |
10454 | LED_CTRL_100MBPS_ON | | |
10455 | LED_CTRL_10MBPS_ON | | |
10456 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10457 | LED_CTRL_TRAFFIC_BLINK | | |
10458 | LED_CTRL_TRAFFIC_LED); | |
10459 | break; | |
6aa20a22 | 10460 | |
81b8709c | 10461 | case ETHTOOL_ID_OFF: |
10462 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10463 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10464 | break; | |
4009a93d | 10465 | |
81b8709c | 10466 | case ETHTOOL_ID_INACTIVE: |
10467 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10468 | break; | |
4009a93d | 10469 | } |
81b8709c | 10470 | |
4009a93d MC |
10471 | return 0; |
10472 | } | |
10473 | ||
de6f31eb | 10474 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10475 | struct ethtool_stats *estats, u64 *tmp_stats) |
10476 | { | |
10477 | struct tg3 *tp = netdev_priv(dev); | |
10478 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10479 | } | |
10480 | ||
c3e94500 MC |
10481 | static __be32 * tg3_vpd_readblock(struct tg3 *tp) |
10482 | { | |
10483 | int i; | |
10484 | __be32 *buf; | |
10485 | u32 offset = 0, len = 0; | |
10486 | u32 magic, val; | |
10487 | ||
10488 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || | |
10489 | tg3_nvram_read(tp, 0, &magic)) | |
10490 | return NULL; | |
10491 | ||
10492 | if (magic == TG3_EEPROM_MAGIC) { | |
10493 | for (offset = TG3_NVM_DIR_START; | |
10494 | offset < TG3_NVM_DIR_END; | |
10495 | offset += TG3_NVM_DIRENT_SIZE) { | |
10496 | if (tg3_nvram_read(tp, offset, &val)) | |
10497 | return NULL; | |
10498 | ||
10499 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
10500 | TG3_NVM_DIRTYPE_EXTVPD) | |
10501 | break; | |
10502 | } | |
10503 | ||
10504 | if (offset != TG3_NVM_DIR_END) { | |
10505 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
10506 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
10507 | return NULL; | |
10508 | ||
10509 | offset = tg3_nvram_logical_addr(tp, offset); | |
10510 | } | |
10511 | } | |
10512 | ||
10513 | if (!offset || !len) { | |
10514 | offset = TG3_NVM_VPD_OFF; | |
10515 | len = TG3_NVM_VPD_LEN; | |
10516 | } | |
10517 | ||
10518 | buf = kmalloc(len, GFP_KERNEL); | |
10519 | if (buf == NULL) | |
10520 | return NULL; | |
10521 | ||
10522 | if (magic == TG3_EEPROM_MAGIC) { | |
10523 | for (i = 0; i < len; i += 4) { | |
10524 | /* The data is in little-endian format in NVRAM. | |
10525 | * Use the big-endian read routines to preserve | |
10526 | * the byte order as it exists in NVRAM. | |
10527 | */ | |
10528 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
10529 | goto error; | |
10530 | } | |
10531 | } else { | |
10532 | u8 *ptr; | |
10533 | ssize_t cnt; | |
10534 | unsigned int pos = 0; | |
10535 | ||
10536 | ptr = (u8 *)&buf[0]; | |
10537 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
10538 | cnt = pci_read_vpd(tp->pdev, pos, | |
10539 | len - pos, ptr); | |
10540 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
10541 | cnt = 0; | |
10542 | else if (cnt < 0) | |
10543 | goto error; | |
10544 | } | |
10545 | if (pos != len) | |
10546 | goto error; | |
10547 | } | |
10548 | ||
10549 | return buf; | |
10550 | ||
10551 | error: | |
10552 | kfree(buf); | |
10553 | return NULL; | |
10554 | } | |
10555 | ||
566f86ad | 10556 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10557 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10558 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10559 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
b16250e3 MC |
10560 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10561 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10562 | |
10563 | static int tg3_test_nvram(struct tg3 *tp) | |
10564 | { | |
b9fc7dc5 | 10565 | u32 csum, magic; |
a9dc529d | 10566 | __be32 *buf; |
ab0049b4 | 10567 | int i, j, k, err = 0, size; |
566f86ad | 10568 | |
df259d8c MC |
10569 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
10570 | return 0; | |
10571 | ||
e4f34110 | 10572 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10573 | return -EIO; |
10574 | ||
1b27777a MC |
10575 | if (magic == TG3_EEPROM_MAGIC) |
10576 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10577 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10578 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10579 | TG3_EEPROM_SB_FORMAT_1) { | |
10580 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10581 | case TG3_EEPROM_SB_REVISION_0: | |
10582 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10583 | break; | |
10584 | case TG3_EEPROM_SB_REVISION_2: | |
10585 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10586 | break; | |
10587 | case TG3_EEPROM_SB_REVISION_3: | |
10588 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10589 | break; | |
10590 | default: | |
10591 | return 0; | |
10592 | } | |
10593 | } else | |
1b27777a | 10594 | return 0; |
b16250e3 MC |
10595 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10596 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10597 | else | |
1b27777a MC |
10598 | return -EIO; |
10599 | ||
10600 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10601 | if (buf == NULL) |
10602 | return -ENOMEM; | |
10603 | ||
1b27777a MC |
10604 | err = -EIO; |
10605 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10606 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10607 | if (err) | |
566f86ad | 10608 | break; |
566f86ad | 10609 | } |
1b27777a | 10610 | if (i < size) |
566f86ad MC |
10611 | goto out; |
10612 | ||
1b27777a | 10613 | /* Selfboot format */ |
a9dc529d | 10614 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10615 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10616 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10617 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10618 | ||
b9fc7dc5 | 10619 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10620 | TG3_EEPROM_SB_REVISION_2) { |
10621 | /* For rev 2, the csum doesn't include the MBA. */ | |
10622 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10623 | csum8 += buf8[i]; | |
10624 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10625 | csum8 += buf8[i]; | |
10626 | } else { | |
10627 | for (i = 0; i < size; i++) | |
10628 | csum8 += buf8[i]; | |
10629 | } | |
1b27777a | 10630 | |
ad96b485 AB |
10631 | if (csum8 == 0) { |
10632 | err = 0; | |
10633 | goto out; | |
10634 | } | |
10635 | ||
10636 | err = -EIO; | |
10637 | goto out; | |
1b27777a | 10638 | } |
566f86ad | 10639 | |
b9fc7dc5 | 10640 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10641 | TG3_EEPROM_MAGIC_HW) { |
10642 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10643 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10644 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10645 | |
10646 | /* Separate the parity bits and the data bytes. */ | |
10647 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10648 | if ((i == 0) || (i == 8)) { | |
10649 | int l; | |
10650 | u8 msk; | |
10651 | ||
10652 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10653 | parity[k++] = buf8[i] & msk; | |
10654 | i++; | |
859a5887 | 10655 | } else if (i == 16) { |
b16250e3 MC |
10656 | int l; |
10657 | u8 msk; | |
10658 | ||
10659 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10660 | parity[k++] = buf8[i] & msk; | |
10661 | i++; | |
10662 | ||
10663 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10664 | parity[k++] = buf8[i] & msk; | |
10665 | i++; | |
10666 | } | |
10667 | data[j++] = buf8[i]; | |
10668 | } | |
10669 | ||
10670 | err = -EIO; | |
10671 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10672 | u8 hw8 = hweight8(data[i]); | |
10673 | ||
10674 | if ((hw8 & 0x1) && parity[i]) | |
10675 | goto out; | |
10676 | else if (!(hw8 & 0x1) && !parity[i]) | |
10677 | goto out; | |
10678 | } | |
10679 | err = 0; | |
10680 | goto out; | |
10681 | } | |
10682 | ||
01c3a392 MC |
10683 | err = -EIO; |
10684 | ||
566f86ad MC |
10685 | /* Bootstrap checksum at offset 0x10 */ |
10686 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 10687 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
10688 | goto out; |
10689 | ||
10690 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10691 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 10692 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 10693 | goto out; |
566f86ad | 10694 | |
c3e94500 MC |
10695 | kfree(buf); |
10696 | ||
10697 | buf = tg3_vpd_readblock(tp); | |
10698 | if (!buf) | |
10699 | return -ENOMEM; | |
d4894f3e MC |
10700 | |
10701 | i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN, | |
10702 | PCI_VPD_LRDT_RO_DATA); | |
10703 | if (i > 0) { | |
10704 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
10705 | if (j < 0) | |
10706 | goto out; | |
10707 | ||
10708 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN) | |
10709 | goto out; | |
10710 | ||
10711 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10712 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
10713 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
10714 | if (j > 0) { | |
10715 | u8 csum8 = 0; | |
10716 | ||
10717 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10718 | ||
10719 | for (i = 0; i <= j; i++) | |
10720 | csum8 += ((u8 *)buf)[i]; | |
10721 | ||
10722 | if (csum8) | |
10723 | goto out; | |
10724 | } | |
10725 | } | |
10726 | ||
566f86ad MC |
10727 | err = 0; |
10728 | ||
10729 | out: | |
10730 | kfree(buf); | |
10731 | return err; | |
10732 | } | |
10733 | ||
ca43007a MC |
10734 | #define TG3_SERDES_TIMEOUT_SEC 2 |
10735 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10736 | ||
10737 | static int tg3_test_link(struct tg3 *tp) | |
10738 | { | |
10739 | int i, max; | |
10740 | ||
10741 | if (!netif_running(tp->dev)) | |
10742 | return -ENODEV; | |
10743 | ||
f07e9af3 | 10744 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
10745 | max = TG3_SERDES_TIMEOUT_SEC; |
10746 | else | |
10747 | max = TG3_COPPER_TIMEOUT_SEC; | |
10748 | ||
10749 | for (i = 0; i < max; i++) { | |
10750 | if (netif_carrier_ok(tp->dev)) | |
10751 | return 0; | |
10752 | ||
10753 | if (msleep_interruptible(1000)) | |
10754 | break; | |
10755 | } | |
10756 | ||
10757 | return -EIO; | |
10758 | } | |
10759 | ||
a71116d1 | 10760 | /* Only test the commonly used registers */ |
30ca3e37 | 10761 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 10762 | { |
b16250e3 | 10763 | int i, is_5705, is_5750; |
a71116d1 MC |
10764 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
10765 | static struct { | |
10766 | u16 offset; | |
10767 | u16 flags; | |
10768 | #define TG3_FL_5705 0x1 | |
10769 | #define TG3_FL_NOT_5705 0x2 | |
10770 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 10771 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
10772 | u32 read_mask; |
10773 | u32 write_mask; | |
10774 | } reg_tbl[] = { | |
10775 | /* MAC Control Registers */ | |
10776 | { MAC_MODE, TG3_FL_NOT_5705, | |
10777 | 0x00000000, 0x00ef6f8c }, | |
10778 | { MAC_MODE, TG3_FL_5705, | |
10779 | 0x00000000, 0x01ef6b8c }, | |
10780 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10781 | 0x03800107, 0x00000000 }, | |
10782 | { MAC_STATUS, TG3_FL_5705, | |
10783 | 0x03800100, 0x00000000 }, | |
10784 | { MAC_ADDR_0_HIGH, 0x0000, | |
10785 | 0x00000000, 0x0000ffff }, | |
10786 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 10787 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
10788 | { MAC_RX_MTU_SIZE, 0x0000, |
10789 | 0x00000000, 0x0000ffff }, | |
10790 | { MAC_TX_MODE, 0x0000, | |
10791 | 0x00000000, 0x00000070 }, | |
10792 | { MAC_TX_LENGTHS, 0x0000, | |
10793 | 0x00000000, 0x00003fff }, | |
10794 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10795 | 0x00000000, 0x000007fc }, | |
10796 | { MAC_RX_MODE, TG3_FL_5705, | |
10797 | 0x00000000, 0x000007dc }, | |
10798 | { MAC_HASH_REG_0, 0x0000, | |
10799 | 0x00000000, 0xffffffff }, | |
10800 | { MAC_HASH_REG_1, 0x0000, | |
10801 | 0x00000000, 0xffffffff }, | |
10802 | { MAC_HASH_REG_2, 0x0000, | |
10803 | 0x00000000, 0xffffffff }, | |
10804 | { MAC_HASH_REG_3, 0x0000, | |
10805 | 0x00000000, 0xffffffff }, | |
10806 | ||
10807 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10808 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10809 | 0x00000000, 0xffffffff }, | |
10810 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10811 | 0x00000000, 0xffffffff }, | |
10812 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10813 | 0x00000000, 0x00000003 }, | |
10814 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10815 | 0x00000000, 0xffffffff }, | |
10816 | { RCVDBDI_STD_BD+0, 0x0000, | |
10817 | 0x00000000, 0xffffffff }, | |
10818 | { RCVDBDI_STD_BD+4, 0x0000, | |
10819 | 0x00000000, 0xffffffff }, | |
10820 | { RCVDBDI_STD_BD+8, 0x0000, | |
10821 | 0x00000000, 0xffff0002 }, | |
10822 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10823 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10824 | |
a71116d1 MC |
10825 | /* Receive BD Initiator Control Registers. */ |
10826 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10827 | 0x00000000, 0xffffffff }, | |
10828 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10829 | 0x00000000, 0x000003ff }, | |
10830 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10831 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10832 | |
a71116d1 MC |
10833 | /* Host Coalescing Control Registers. */ |
10834 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10835 | 0x00000000, 0x00000004 }, | |
10836 | { HOSTCC_MODE, TG3_FL_5705, | |
10837 | 0x00000000, 0x000000f6 }, | |
10838 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10839 | 0x00000000, 0xffffffff }, | |
10840 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10841 | 0x00000000, 0x000003ff }, | |
10842 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10843 | 0x00000000, 0xffffffff }, | |
10844 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10845 | 0x00000000, 0x000003ff }, | |
10846 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10847 | 0x00000000, 0xffffffff }, | |
10848 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10849 | 0x00000000, 0x000000ff }, | |
10850 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10851 | 0x00000000, 0xffffffff }, | |
10852 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10853 | 0x00000000, 0x000000ff }, | |
10854 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10855 | 0x00000000, 0xffffffff }, | |
10856 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10857 | 0x00000000, 0xffffffff }, | |
10858 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10859 | 0x00000000, 0xffffffff }, | |
10860 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10861 | 0x00000000, 0x000000ff }, | |
10862 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10863 | 0x00000000, 0xffffffff }, | |
10864 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10865 | 0x00000000, 0x000000ff }, | |
10866 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10867 | 0x00000000, 0xffffffff }, | |
10868 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10869 | 0x00000000, 0xffffffff }, | |
10870 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10871 | 0x00000000, 0xffffffff }, | |
10872 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10873 | 0x00000000, 0xffffffff }, | |
10874 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10875 | 0x00000000, 0xffffffff }, | |
10876 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10877 | 0xffffffff, 0x00000000 }, | |
10878 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10879 | 0xffffffff, 0x00000000 }, | |
10880 | ||
10881 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 10882 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 10883 | 0x00000000, 0x007fff80 }, |
b16250e3 | 10884 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
10885 | 0x00000000, 0x007fffff }, |
10886 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10887 | 0x00000000, 0x0000003f }, | |
10888 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10889 | 0x00000000, 0x000001ff }, | |
10890 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10891 | 0x00000000, 0x000001ff }, | |
10892 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10893 | 0xffffffff, 0x00000000 }, | |
10894 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10895 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 10896 | |
a71116d1 MC |
10897 | /* Mailbox Registers */ |
10898 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10899 | 0x00000000, 0x000001ff }, | |
10900 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10901 | 0x00000000, 0x000001ff }, | |
10902 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10903 | 0x00000000, 0x000007ff }, | |
10904 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10905 | 0x00000000, 0x000001ff }, | |
10906 | ||
10907 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10908 | }; | |
10909 | ||
b16250e3 MC |
10910 | is_5705 = is_5750 = 0; |
10911 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
a71116d1 | 10912 | is_5705 = 1; |
b16250e3 MC |
10913 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
10914 | is_5750 = 1; | |
10915 | } | |
a71116d1 MC |
10916 | |
10917 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10918 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
10919 | continue; | |
10920 | ||
10921 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
10922 | continue; | |
10923 | ||
10924 | if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
10925 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
10926 | continue; | |
10927 | ||
b16250e3 MC |
10928 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
10929 | continue; | |
10930 | ||
a71116d1 MC |
10931 | offset = (u32) reg_tbl[i].offset; |
10932 | read_mask = reg_tbl[i].read_mask; | |
10933 | write_mask = reg_tbl[i].write_mask; | |
10934 | ||
10935 | /* Save the original register content */ | |
10936 | save_val = tr32(offset); | |
10937 | ||
10938 | /* Determine the read-only value. */ | |
10939 | read_val = save_val & read_mask; | |
10940 | ||
10941 | /* Write zero to the register, then make sure the read-only bits | |
10942 | * are not changed and the read/write bits are all zeros. | |
10943 | */ | |
10944 | tw32(offset, 0); | |
10945 | ||
10946 | val = tr32(offset); | |
10947 | ||
10948 | /* Test the read-only and read/write bits. */ | |
10949 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
10950 | goto out; | |
10951 | ||
10952 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
10953 | * make sure the read-only bits are not changed and the | |
10954 | * read/write bits are all ones. | |
10955 | */ | |
10956 | tw32(offset, read_mask | write_mask); | |
10957 | ||
10958 | val = tr32(offset); | |
10959 | ||
10960 | /* Test the read-only bits. */ | |
10961 | if ((val & read_mask) != read_val) | |
10962 | goto out; | |
10963 | ||
10964 | /* Test the read/write bits. */ | |
10965 | if ((val & write_mask) != write_mask) | |
10966 | goto out; | |
10967 | ||
10968 | tw32(offset, save_val); | |
10969 | } | |
10970 | ||
10971 | return 0; | |
10972 | ||
10973 | out: | |
9f88f29f | 10974 | if (netif_msg_hw(tp)) |
2445e461 MC |
10975 | netdev_err(tp->dev, |
10976 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
10977 | tw32(offset, save_val); |
10978 | return -EIO; | |
10979 | } | |
10980 | ||
7942e1db MC |
10981 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
10982 | { | |
f71e1309 | 10983 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
10984 | int i; |
10985 | u32 j; | |
10986 | ||
e9edda69 | 10987 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
10988 | for (j = 0; j < len; j += 4) { |
10989 | u32 val; | |
10990 | ||
10991 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
10992 | tg3_read_mem(tp, offset + j, &val); | |
10993 | if (val != test_pattern[i]) | |
10994 | return -EIO; | |
10995 | } | |
10996 | } | |
10997 | return 0; | |
10998 | } | |
10999 | ||
11000 | static int tg3_test_memory(struct tg3 *tp) | |
11001 | { | |
11002 | static struct mem_entry { | |
11003 | u32 offset; | |
11004 | u32 len; | |
11005 | } mem_tbl_570x[] = { | |
38690194 | 11006 | { 0x00000000, 0x00b50}, |
7942e1db MC |
11007 | { 0x00002000, 0x1c000}, |
11008 | { 0xffffffff, 0x00000} | |
11009 | }, mem_tbl_5705[] = { | |
11010 | { 0x00000100, 0x0000c}, | |
11011 | { 0x00000200, 0x00008}, | |
7942e1db MC |
11012 | { 0x00004000, 0x00800}, |
11013 | { 0x00006000, 0x01000}, | |
11014 | { 0x00008000, 0x02000}, | |
11015 | { 0x00010000, 0x0e000}, | |
11016 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
11017 | }, mem_tbl_5755[] = { |
11018 | { 0x00000200, 0x00008}, | |
11019 | { 0x00004000, 0x00800}, | |
11020 | { 0x00006000, 0x00800}, | |
11021 | { 0x00008000, 0x02000}, | |
11022 | { 0x00010000, 0x0c000}, | |
11023 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
11024 | }, mem_tbl_5906[] = { |
11025 | { 0x00000200, 0x00008}, | |
11026 | { 0x00004000, 0x00400}, | |
11027 | { 0x00006000, 0x00400}, | |
11028 | { 0x00008000, 0x01000}, | |
11029 | { 0x00010000, 0x01000}, | |
11030 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
11031 | }, mem_tbl_5717[] = { |
11032 | { 0x00000200, 0x00008}, | |
11033 | { 0x00010000, 0x0a000}, | |
11034 | { 0x00020000, 0x13c00}, | |
11035 | { 0xffffffff, 0x00000} | |
11036 | }, mem_tbl_57765[] = { | |
11037 | { 0x00000200, 0x00008}, | |
11038 | { 0x00004000, 0x00800}, | |
11039 | { 0x00006000, 0x09800}, | |
11040 | { 0x00010000, 0x0a000}, | |
11041 | { 0xffffffff, 0x00000} | |
7942e1db MC |
11042 | }; |
11043 | struct mem_entry *mem_tbl; | |
11044 | int err = 0; | |
11045 | int i; | |
11046 | ||
0a58d668 | 11047 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
8b5a6c42 MC |
11048 | mem_tbl = mem_tbl_5717; |
11049 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
11050 | mem_tbl = mem_tbl_57765; | |
11051 | else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
321d32a0 MC |
11052 | mem_tbl = mem_tbl_5755; |
11053 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11054 | mem_tbl = mem_tbl_5906; | |
11055 | else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
11056 | mem_tbl = mem_tbl_5705; | |
11057 | else | |
7942e1db MC |
11058 | mem_tbl = mem_tbl_570x; |
11059 | ||
11060 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
11061 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
11062 | if (err) | |
7942e1db MC |
11063 | break; |
11064 | } | |
6aa20a22 | 11065 | |
7942e1db MC |
11066 | return err; |
11067 | } | |
11068 | ||
9f40dead MC |
11069 | #define TG3_MAC_LOOPBACK 0 |
11070 | #define TG3_PHY_LOOPBACK 1 | |
11071 | ||
4852a861 | 11072 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode) |
c76949a6 | 11073 | { |
9f40dead | 11074 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
fd2ce37f | 11075 | u32 desc_idx, coal_now; |
c76949a6 MC |
11076 | struct sk_buff *skb, *rx_skb; |
11077 | u8 *tx_data; | |
11078 | dma_addr_t map; | |
11079 | int num_pkts, tx_len, rx_len, i, err; | |
11080 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 11081 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 11082 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 11083 | |
c8873405 MC |
11084 | tnapi = &tp->napi[0]; |
11085 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 11086 | if (tp->irq_cnt > 1) { |
1da85aa3 MC |
11087 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
11088 | rnapi = &tp->napi[1]; | |
c8873405 MC |
11089 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
11090 | tnapi = &tp->napi[1]; | |
0c1d0e2b | 11091 | } |
fd2ce37f | 11092 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 11093 | |
9f40dead | 11094 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
c94e3941 MC |
11095 | /* HW errata - mac loopback fails in some cases on 5780. |
11096 | * Normal traffic and PHY loopback are not affected by | |
aba49f24 MC |
11097 | * errata. Also, the MAC loopback test is deprecated for |
11098 | * all newer ASIC revisions. | |
c94e3941 | 11099 | */ |
aba49f24 MC |
11100 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
11101 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) | |
c94e3941 MC |
11102 | return 0; |
11103 | ||
49692ca1 MC |
11104 | mac_mode = tp->mac_mode & |
11105 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
11106 | mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
e8f3f6ca MC |
11107 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
11108 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
f07e9af3 | 11109 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3f7045c1 MC |
11110 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
11111 | else | |
11112 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9f40dead MC |
11113 | tw32(MAC_MODE, mac_mode); |
11114 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | |
3f7045c1 MC |
11115 | u32 val; |
11116 | ||
f07e9af3 | 11117 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd | 11118 | tg3_phy_fet_toggle_apd(tp, false); |
5d64ad34 MC |
11119 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
11120 | } else | |
11121 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 11122 | |
9ef8ca99 MC |
11123 | tg3_phy_toggle_automdix(tp, 0); |
11124 | ||
3f7045c1 | 11125 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 11126 | udelay(40); |
5d64ad34 | 11127 | |
49692ca1 MC |
11128 | mac_mode = tp->mac_mode & |
11129 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
f07e9af3 | 11130 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
1061b7c5 MC |
11131 | tg3_writephy(tp, MII_TG3_FET_PTEST, |
11132 | MII_TG3_FET_PTEST_FRC_TX_LINK | | |
11133 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
11134 | /* The write needs to be flushed for the AC131 */ | |
11135 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
11136 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
5d64ad34 MC |
11137 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
11138 | } else | |
11139 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 11140 | |
c94e3941 | 11141 | /* reset to prevent losing 1st rx packet intermittently */ |
f07e9af3 | 11142 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
c94e3941 MC |
11143 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
11144 | udelay(10); | |
11145 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
11146 | } | |
e8f3f6ca | 11147 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
79eb6904 MC |
11148 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
11149 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
e8f3f6ca | 11150 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
79eb6904 | 11151 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) |
e8f3f6ca | 11152 | mac_mode |= MAC_MODE_LINK_POLARITY; |
ff18ff02 MC |
11153 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
11154 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
11155 | } | |
9f40dead | 11156 | tw32(MAC_MODE, mac_mode); |
49692ca1 MC |
11157 | |
11158 | /* Wait for link */ | |
11159 | for (i = 0; i < 100; i++) { | |
11160 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
11161 | break; | |
11162 | mdelay(1); | |
11163 | } | |
859a5887 | 11164 | } else { |
9f40dead | 11165 | return -EINVAL; |
859a5887 | 11166 | } |
c76949a6 MC |
11167 | |
11168 | err = -EIO; | |
11169 | ||
4852a861 | 11170 | tx_len = pktsz; |
a20e9c62 | 11171 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
11172 | if (!skb) |
11173 | return -ENOMEM; | |
11174 | ||
c76949a6 MC |
11175 | tx_data = skb_put(skb, tx_len); |
11176 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
11177 | memset(tx_data + 6, 0x0, 8); | |
11178 | ||
4852a861 | 11179 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 MC |
11180 | |
11181 | for (i = 14; i < tx_len; i++) | |
11182 | tx_data[i] = (u8) (i & 0xff); | |
11183 | ||
f4188d8a AD |
11184 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
11185 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
11186 | dev_kfree_skb(skb); |
11187 | return -EIO; | |
11188 | } | |
c76949a6 MC |
11189 | |
11190 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 11191 | rnapi->coal_now); |
c76949a6 MC |
11192 | |
11193 | udelay(10); | |
11194 | ||
898a56f8 | 11195 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 11196 | |
c76949a6 MC |
11197 | num_pkts = 0; |
11198 | ||
f4188d8a | 11199 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1); |
c76949a6 | 11200 | |
f3f3f27e | 11201 | tnapi->tx_prod++; |
c76949a6 MC |
11202 | num_pkts++; |
11203 | ||
f3f3f27e MC |
11204 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
11205 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
11206 | |
11207 | udelay(10); | |
11208 | ||
303fc921 MC |
11209 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
11210 | for (i = 0; i < 35; i++) { | |
c76949a6 | 11211 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11212 | coal_now); |
c76949a6 MC |
11213 | |
11214 | udelay(10); | |
11215 | ||
898a56f8 MC |
11216 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
11217 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 11218 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
11219 | (rx_idx == (rx_start_idx + num_pkts))) |
11220 | break; | |
11221 | } | |
11222 | ||
f4188d8a | 11223 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); |
c76949a6 MC |
11224 | dev_kfree_skb(skb); |
11225 | ||
f3f3f27e | 11226 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
11227 | goto out; |
11228 | ||
11229 | if (rx_idx != rx_start_idx + num_pkts) | |
11230 | goto out; | |
11231 | ||
72334482 | 11232 | desc = &rnapi->rx_rcb[rx_start_idx]; |
c76949a6 MC |
11233 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
11234 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 MC |
11235 | |
11236 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
11237 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11238 | goto out; | |
11239 | ||
11240 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; | |
11241 | if (rx_len != tx_len) | |
11242 | goto out; | |
11243 | ||
4852a861 MC |
11244 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
11245 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11246 | goto out; | |
11247 | ||
11248 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; | |
11249 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping); | |
11250 | } else { | |
11251 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
11252 | goto out; | |
11253 | ||
11254 | rx_skb = tpr->rx_jmb_buffers[desc_idx].skb; | |
11255 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], mapping); | |
11256 | } | |
c76949a6 | 11257 | |
c76949a6 MC |
11258 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); |
11259 | ||
11260 | for (i = 14; i < tx_len; i++) { | |
11261 | if (*(rx_skb->data + i) != (u8) (i & 0xff)) | |
11262 | goto out; | |
11263 | } | |
11264 | err = 0; | |
6aa20a22 | 11265 | |
c76949a6 MC |
11266 | /* tg3_free_rings will unmap and free the rx_skb */ |
11267 | out: | |
11268 | return err; | |
11269 | } | |
11270 | ||
9f40dead MC |
11271 | #define TG3_MAC_LOOPBACK_FAILED 1 |
11272 | #define TG3_PHY_LOOPBACK_FAILED 2 | |
11273 | #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \ | |
11274 | TG3_PHY_LOOPBACK_FAILED) | |
11275 | ||
11276 | static int tg3_test_loopback(struct tg3 *tp) | |
11277 | { | |
11278 | int err = 0; | |
ab789046 | 11279 | u32 eee_cap, cpmuctrl = 0; |
9f40dead MC |
11280 | |
11281 | if (!netif_running(tp->dev)) | |
11282 | return TG3_LOOPBACK_FAILED; | |
11283 | ||
ab789046 MC |
11284 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
11285 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11286 | ||
b9ec6c1b | 11287 | err = tg3_reset_hw(tp, 1); |
ab789046 MC |
11288 | if (err) { |
11289 | err = TG3_LOOPBACK_FAILED; | |
11290 | goto done; | |
11291 | } | |
9f40dead | 11292 | |
4a85f098 MC |
11293 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { |
11294 | int i; | |
11295 | ||
11296 | /* Reroute all rx packets to the 1st queue */ | |
11297 | for (i = MAC_RSS_INDIR_TBL_0; | |
11298 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
11299 | tw32(i, 0x0); | |
11300 | } | |
11301 | ||
6833c043 | 11302 | /* Turn off gphy autopowerdown. */ |
f07e9af3 | 11303 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11304 | tg3_phy_toggle_apd(tp, false); |
11305 | ||
321d32a0 | 11306 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
11307 | int i; |
11308 | u32 status; | |
11309 | ||
11310 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
11311 | ||
11312 | /* Wait for up to 40 microseconds to acquire lock. */ | |
11313 | for (i = 0; i < 4; i++) { | |
11314 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
11315 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
11316 | break; | |
11317 | udelay(10); | |
11318 | } | |
11319 | ||
ab789046 MC |
11320 | if (status != CPMU_MUTEX_GNT_DRIVER) { |
11321 | err = TG3_LOOPBACK_FAILED; | |
11322 | goto done; | |
11323 | } | |
9936bcf6 | 11324 | |
b2a5c19c | 11325 | /* Turn off link-based power management. */ |
e875093c | 11326 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
109115e1 MC |
11327 | tw32(TG3_CPMU_CTRL, |
11328 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
11329 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9936bcf6 MC |
11330 | } |
11331 | ||
4852a861 | 11332 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK)) |
9f40dead | 11333 | err |= TG3_MAC_LOOPBACK_FAILED; |
9936bcf6 | 11334 | |
4852a861 MC |
11335 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) && |
11336 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK)) | |
11337 | err |= (TG3_MAC_LOOPBACK_FAILED << 2); | |
11338 | ||
321d32a0 | 11339 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
11340 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
11341 | ||
11342 | /* Release the mutex */ | |
11343 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
11344 | } | |
11345 | ||
f07e9af3 | 11346 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
dd477003 | 11347 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
4852a861 | 11348 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK)) |
9f40dead | 11349 | err |= TG3_PHY_LOOPBACK_FAILED; |
4852a861 MC |
11350 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) && |
11351 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK)) | |
11352 | err |= (TG3_PHY_LOOPBACK_FAILED << 2); | |
9f40dead MC |
11353 | } |
11354 | ||
6833c043 | 11355 | /* Re-enable gphy autopowerdown. */ |
f07e9af3 | 11356 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11357 | tg3_phy_toggle_apd(tp, true); |
11358 | ||
ab789046 MC |
11359 | done: |
11360 | tp->phy_flags |= eee_cap; | |
11361 | ||
9f40dead MC |
11362 | return err; |
11363 | } | |
11364 | ||
4cafd3f5 MC |
11365 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
11366 | u64 *data) | |
11367 | { | |
566f86ad MC |
11368 | struct tg3 *tp = netdev_priv(dev); |
11369 | ||
80096068 | 11370 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11371 | tg3_power_up(tp); |
bc1c7567 | 11372 | |
566f86ad MC |
11373 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
11374 | ||
11375 | if (tg3_test_nvram(tp) != 0) { | |
11376 | etest->flags |= ETH_TEST_FL_FAILED; | |
11377 | data[0] = 1; | |
11378 | } | |
ca43007a MC |
11379 | if (tg3_test_link(tp) != 0) { |
11380 | etest->flags |= ETH_TEST_FL_FAILED; | |
11381 | data[1] = 1; | |
11382 | } | |
a71116d1 | 11383 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 11384 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
11385 | |
11386 | if (netif_running(dev)) { | |
b02fd9e3 | 11387 | tg3_phy_stop(tp); |
a71116d1 | 11388 | tg3_netif_stop(tp); |
bbe832c0 MC |
11389 | irq_sync = 1; |
11390 | } | |
a71116d1 | 11391 | |
bbe832c0 | 11392 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
11393 | |
11394 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 11395 | err = tg3_nvram_lock(tp); |
a71116d1 MC |
11396 | tg3_halt_cpu(tp, RX_CPU_BASE); |
11397 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
11398 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
ec41c7df MC |
11399 | if (!err) |
11400 | tg3_nvram_unlock(tp); | |
a71116d1 | 11401 | |
f07e9af3 | 11402 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
11403 | tg3_phy_reset(tp); |
11404 | ||
a71116d1 MC |
11405 | if (tg3_test_registers(tp) != 0) { |
11406 | etest->flags |= ETH_TEST_FL_FAILED; | |
11407 | data[2] = 1; | |
11408 | } | |
7942e1db MC |
11409 | if (tg3_test_memory(tp) != 0) { |
11410 | etest->flags |= ETH_TEST_FL_FAILED; | |
11411 | data[3] = 1; | |
11412 | } | |
9f40dead | 11413 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 11414 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 11415 | |
f47c11ee DM |
11416 | tg3_full_unlock(tp); |
11417 | ||
d4bc3927 MC |
11418 | if (tg3_test_interrupt(tp) != 0) { |
11419 | etest->flags |= ETH_TEST_FL_FAILED; | |
11420 | data[5] = 1; | |
11421 | } | |
f47c11ee DM |
11422 | |
11423 | tg3_full_lock(tp, 0); | |
d4bc3927 | 11424 | |
a71116d1 MC |
11425 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11426 | if (netif_running(dev)) { | |
11427 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
b02fd9e3 MC |
11428 | err2 = tg3_restart_hw(tp, 1); |
11429 | if (!err2) | |
b9ec6c1b | 11430 | tg3_netif_start(tp); |
a71116d1 | 11431 | } |
f47c11ee DM |
11432 | |
11433 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
11434 | |
11435 | if (irq_sync && !err2) | |
11436 | tg3_phy_start(tp); | |
a71116d1 | 11437 | } |
80096068 | 11438 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11439 | tg3_power_down(tp); |
bc1c7567 | 11440 | |
4cafd3f5 MC |
11441 | } |
11442 | ||
1da177e4 LT |
11443 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
11444 | { | |
11445 | struct mii_ioctl_data *data = if_mii(ifr); | |
11446 | struct tg3 *tp = netdev_priv(dev); | |
11447 | int err; | |
11448 | ||
b02fd9e3 | 11449 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 11450 | struct phy_device *phydev; |
f07e9af3 | 11451 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11452 | return -EAGAIN; |
3f0e3ad7 | 11453 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 11454 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
11455 | } |
11456 | ||
33f401ae | 11457 | switch (cmd) { |
1da177e4 | 11458 | case SIOCGMIIPHY: |
882e9793 | 11459 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
11460 | |
11461 | /* fallthru */ | |
11462 | case SIOCGMIIREG: { | |
11463 | u32 mii_regval; | |
11464 | ||
f07e9af3 | 11465 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11466 | break; /* We have no PHY */ |
11467 | ||
34eea5ac | 11468 | if (!netif_running(dev)) |
bc1c7567 MC |
11469 | return -EAGAIN; |
11470 | ||
f47c11ee | 11471 | spin_lock_bh(&tp->lock); |
1da177e4 | 11472 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 11473 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11474 | |
11475 | data->val_out = mii_regval; | |
11476 | ||
11477 | return err; | |
11478 | } | |
11479 | ||
11480 | case SIOCSMIIREG: | |
f07e9af3 | 11481 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11482 | break; /* We have no PHY */ |
11483 | ||
34eea5ac | 11484 | if (!netif_running(dev)) |
bc1c7567 MC |
11485 | return -EAGAIN; |
11486 | ||
f47c11ee | 11487 | spin_lock_bh(&tp->lock); |
1da177e4 | 11488 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 11489 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11490 | |
11491 | return err; | |
11492 | ||
11493 | default: | |
11494 | /* do nothing */ | |
11495 | break; | |
11496 | } | |
11497 | return -EOPNOTSUPP; | |
11498 | } | |
11499 | ||
15f9850d DM |
11500 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11501 | { | |
11502 | struct tg3 *tp = netdev_priv(dev); | |
11503 | ||
11504 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11505 | return 0; | |
11506 | } | |
11507 | ||
d244c892 MC |
11508 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11509 | { | |
11510 | struct tg3 *tp = netdev_priv(dev); | |
11511 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11512 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11513 | ||
11514 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
11515 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
11516 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11517 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11518 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11519 | } | |
11520 | ||
11521 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11522 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11523 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11524 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11525 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11526 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11527 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11528 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11529 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11530 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11531 | return -EINVAL; | |
11532 | ||
11533 | /* No rx interrupts will be generated if both are zero */ | |
11534 | if ((ec->rx_coalesce_usecs == 0) && | |
11535 | (ec->rx_max_coalesced_frames == 0)) | |
11536 | return -EINVAL; | |
11537 | ||
11538 | /* No tx interrupts will be generated if both are zero */ | |
11539 | if ((ec->tx_coalesce_usecs == 0) && | |
11540 | (ec->tx_max_coalesced_frames == 0)) | |
11541 | return -EINVAL; | |
11542 | ||
11543 | /* Only copy relevant parameters, ignore all others. */ | |
11544 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11545 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11546 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11547 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11548 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11549 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11550 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11551 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11552 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11553 | ||
11554 | if (netif_running(dev)) { | |
11555 | tg3_full_lock(tp, 0); | |
11556 | __tg3_set_coalesce(tp, &tp->coal); | |
11557 | tg3_full_unlock(tp); | |
11558 | } | |
11559 | return 0; | |
11560 | } | |
11561 | ||
7282d491 | 11562 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11563 | .get_settings = tg3_get_settings, |
11564 | .set_settings = tg3_set_settings, | |
11565 | .get_drvinfo = tg3_get_drvinfo, | |
11566 | .get_regs_len = tg3_get_regs_len, | |
11567 | .get_regs = tg3_get_regs, | |
11568 | .get_wol = tg3_get_wol, | |
11569 | .set_wol = tg3_set_wol, | |
11570 | .get_msglevel = tg3_get_msglevel, | |
11571 | .set_msglevel = tg3_set_msglevel, | |
11572 | .nway_reset = tg3_nway_reset, | |
11573 | .get_link = ethtool_op_get_link, | |
11574 | .get_eeprom_len = tg3_get_eeprom_len, | |
11575 | .get_eeprom = tg3_get_eeprom, | |
11576 | .set_eeprom = tg3_set_eeprom, | |
11577 | .get_ringparam = tg3_get_ringparam, | |
11578 | .set_ringparam = tg3_set_ringparam, | |
11579 | .get_pauseparam = tg3_get_pauseparam, | |
11580 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 11581 | .self_test = tg3_self_test, |
1da177e4 | 11582 | .get_strings = tg3_get_strings, |
81b8709c | 11583 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 11584 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11585 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11586 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11587 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11588 | }; |
11589 | ||
11590 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11591 | { | |
1b27777a | 11592 | u32 cursize, val, magic; |
1da177e4 LT |
11593 | |
11594 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11595 | ||
e4f34110 | 11596 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11597 | return; |
11598 | ||
b16250e3 MC |
11599 | if ((magic != TG3_EEPROM_MAGIC) && |
11600 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11601 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11602 | return; |
11603 | ||
11604 | /* | |
11605 | * Size the chip by reading offsets at increasing powers of two. | |
11606 | * When we encounter our validation signature, we know the addressing | |
11607 | * has wrapped around, and thus have our chip size. | |
11608 | */ | |
1b27777a | 11609 | cursize = 0x10; |
1da177e4 LT |
11610 | |
11611 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11612 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11613 | return; |
11614 | ||
1820180b | 11615 | if (val == magic) |
1da177e4 LT |
11616 | break; |
11617 | ||
11618 | cursize <<= 1; | |
11619 | } | |
11620 | ||
11621 | tp->nvram_size = cursize; | |
11622 | } | |
6aa20a22 | 11623 | |
1da177e4 LT |
11624 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11625 | { | |
11626 | u32 val; | |
11627 | ||
df259d8c MC |
11628 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
11629 | tg3_nvram_read(tp, 0, &val) != 0) | |
1b27777a MC |
11630 | return; |
11631 | ||
11632 | /* Selfboot format */ | |
1820180b | 11633 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11634 | tg3_get_eeprom_size(tp); |
11635 | return; | |
11636 | } | |
11637 | ||
6d348f2c | 11638 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 11639 | if (val != 0) { |
6d348f2c MC |
11640 | /* This is confusing. We want to operate on the |
11641 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11642 | * call will read from NVRAM and byteswap the data | |
11643 | * according to the byteswapping settings for all | |
11644 | * other register accesses. This ensures the data we | |
11645 | * want will always reside in the lower 16-bits. | |
11646 | * However, the data in NVRAM is in LE format, which | |
11647 | * means the data from the NVRAM read will always be | |
11648 | * opposite the endianness of the CPU. The 16-bit | |
11649 | * byteswap then brings the data to CPU endianness. | |
11650 | */ | |
11651 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
11652 | return; |
11653 | } | |
11654 | } | |
fd1122a2 | 11655 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
11656 | } |
11657 | ||
11658 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11659 | { | |
11660 | u32 nvcfg1; | |
11661 | ||
11662 | nvcfg1 = tr32(NVRAM_CFG1); | |
11663 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
11664 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
8590a603 | 11665 | } else { |
1da177e4 LT |
11666 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11667 | tw32(NVRAM_CFG1, nvcfg1); | |
11668 | } | |
11669 | ||
4c987487 | 11670 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || |
a4e2b347 | 11671 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 | 11672 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
11673 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
11674 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11675 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11676 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11677 | break; | |
11678 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11679 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11680 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11681 | break; | |
11682 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11683 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11684 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11685 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11686 | break; | |
11687 | case FLASH_VENDOR_ST: | |
11688 | tp->nvram_jedecnum = JEDEC_ST; | |
11689 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
11690 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11691 | break; | |
11692 | case FLASH_VENDOR_SAIFUN: | |
11693 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11694 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11695 | break; | |
11696 | case FLASH_VENDOR_SST_SMALL: | |
11697 | case FLASH_VENDOR_SST_LARGE: | |
11698 | tp->nvram_jedecnum = JEDEC_SST; | |
11699 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11700 | break; | |
1da177e4 | 11701 | } |
8590a603 | 11702 | } else { |
1da177e4 LT |
11703 | tp->nvram_jedecnum = JEDEC_ATMEL; |
11704 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11705 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11706 | } | |
11707 | } | |
11708 | ||
a1b950d5 MC |
11709 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
11710 | { | |
11711 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11712 | case FLASH_5752PAGE_SIZE_256: | |
11713 | tp->nvram_pagesize = 256; | |
11714 | break; | |
11715 | case FLASH_5752PAGE_SIZE_512: | |
11716 | tp->nvram_pagesize = 512; | |
11717 | break; | |
11718 | case FLASH_5752PAGE_SIZE_1K: | |
11719 | tp->nvram_pagesize = 1024; | |
11720 | break; | |
11721 | case FLASH_5752PAGE_SIZE_2K: | |
11722 | tp->nvram_pagesize = 2048; | |
11723 | break; | |
11724 | case FLASH_5752PAGE_SIZE_4K: | |
11725 | tp->nvram_pagesize = 4096; | |
11726 | break; | |
11727 | case FLASH_5752PAGE_SIZE_264: | |
11728 | tp->nvram_pagesize = 264; | |
11729 | break; | |
11730 | case FLASH_5752PAGE_SIZE_528: | |
11731 | tp->nvram_pagesize = 528; | |
11732 | break; | |
11733 | } | |
11734 | } | |
11735 | ||
361b4ac2 MC |
11736 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
11737 | { | |
11738 | u32 nvcfg1; | |
11739 | ||
11740 | nvcfg1 = tr32(NVRAM_CFG1); | |
11741 | ||
e6af301b MC |
11742 | /* NVRAM protection for TPM */ |
11743 | if (nvcfg1 & (1 << 27)) | |
f66a29b0 | 11744 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
e6af301b | 11745 | |
361b4ac2 | 11746 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
11747 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
11748 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11749 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11750 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11751 | break; | |
11752 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11753 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11754 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11755 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11756 | break; | |
11757 | case FLASH_5752VENDOR_ST_M45PE10: | |
11758 | case FLASH_5752VENDOR_ST_M45PE20: | |
11759 | case FLASH_5752VENDOR_ST_M45PE40: | |
11760 | tp->nvram_jedecnum = JEDEC_ST; | |
11761 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11762 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11763 | break; | |
361b4ac2 MC |
11764 | } |
11765 | ||
11766 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | |
a1b950d5 | 11767 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 11768 | } else { |
361b4ac2 MC |
11769 | /* For eeprom, set pagesize to maximum eeprom size */ |
11770 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11771 | ||
11772 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11773 | tw32(NVRAM_CFG1, nvcfg1); | |
11774 | } | |
11775 | } | |
11776 | ||
d3c7b886 MC |
11777 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
11778 | { | |
989a9d23 | 11779 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
11780 | |
11781 | nvcfg1 = tr32(NVRAM_CFG1); | |
11782 | ||
11783 | /* NVRAM protection for TPM */ | |
989a9d23 | 11784 | if (nvcfg1 & (1 << 27)) { |
f66a29b0 | 11785 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
989a9d23 MC |
11786 | protect = 1; |
11787 | } | |
d3c7b886 | 11788 | |
989a9d23 MC |
11789 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
11790 | switch (nvcfg1) { | |
8590a603 MC |
11791 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
11792 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11793 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11794 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11795 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11796 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11797 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11798 | tp->nvram_pagesize = 264; | |
11799 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11800 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11801 | tp->nvram_size = (protect ? 0x3e200 : | |
11802 | TG3_NVRAM_SIZE_512KB); | |
11803 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11804 | tp->nvram_size = (protect ? 0x1f200 : | |
11805 | TG3_NVRAM_SIZE_256KB); | |
11806 | else | |
11807 | tp->nvram_size = (protect ? 0x1f200 : | |
11808 | TG3_NVRAM_SIZE_128KB); | |
11809 | break; | |
11810 | case FLASH_5752VENDOR_ST_M45PE10: | |
11811 | case FLASH_5752VENDOR_ST_M45PE20: | |
11812 | case FLASH_5752VENDOR_ST_M45PE40: | |
11813 | tp->nvram_jedecnum = JEDEC_ST; | |
11814 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11815 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11816 | tp->nvram_pagesize = 256; | |
11817 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11818 | tp->nvram_size = (protect ? | |
11819 | TG3_NVRAM_SIZE_64KB : | |
11820 | TG3_NVRAM_SIZE_128KB); | |
11821 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
11822 | tp->nvram_size = (protect ? | |
11823 | TG3_NVRAM_SIZE_64KB : | |
11824 | TG3_NVRAM_SIZE_256KB); | |
11825 | else | |
11826 | tp->nvram_size = (protect ? | |
11827 | TG3_NVRAM_SIZE_128KB : | |
11828 | TG3_NVRAM_SIZE_512KB); | |
11829 | break; | |
d3c7b886 MC |
11830 | } |
11831 | } | |
11832 | ||
1b27777a MC |
11833 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
11834 | { | |
11835 | u32 nvcfg1; | |
11836 | ||
11837 | nvcfg1 = tr32(NVRAM_CFG1); | |
11838 | ||
11839 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
11840 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
11841 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11842 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
11843 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11844 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11845 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11846 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
1b27777a | 11847 | |
8590a603 MC |
11848 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11849 | tw32(NVRAM_CFG1, nvcfg1); | |
11850 | break; | |
11851 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11852 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11853 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11854 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11855 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11856 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11857 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11858 | tp->nvram_pagesize = 264; | |
11859 | break; | |
11860 | case FLASH_5752VENDOR_ST_M45PE10: | |
11861 | case FLASH_5752VENDOR_ST_M45PE20: | |
11862 | case FLASH_5752VENDOR_ST_M45PE40: | |
11863 | tp->nvram_jedecnum = JEDEC_ST; | |
11864 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11865 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11866 | tp->nvram_pagesize = 256; | |
11867 | break; | |
1b27777a MC |
11868 | } |
11869 | } | |
11870 | ||
6b91fa02 MC |
11871 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
11872 | { | |
11873 | u32 nvcfg1, protect = 0; | |
11874 | ||
11875 | nvcfg1 = tr32(NVRAM_CFG1); | |
11876 | ||
11877 | /* NVRAM protection for TPM */ | |
11878 | if (nvcfg1 & (1 << 27)) { | |
f66a29b0 | 11879 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
6b91fa02 MC |
11880 | protect = 1; |
11881 | } | |
11882 | ||
11883 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11884 | switch (nvcfg1) { | |
8590a603 MC |
11885 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
11886 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11887 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11888 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11889 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11890 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11891 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11892 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11893 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11894 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11895 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11896 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
11897 | tp->nvram_pagesize = 256; | |
11898 | break; | |
11899 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11900 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11901 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11902 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11903 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11904 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11905 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11906 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11907 | tp->nvram_jedecnum = JEDEC_ST; | |
11908 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11909 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11910 | tp->nvram_pagesize = 256; | |
11911 | break; | |
6b91fa02 MC |
11912 | } |
11913 | ||
11914 | if (protect) { | |
11915 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
11916 | } else { | |
11917 | switch (nvcfg1) { | |
8590a603 MC |
11918 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
11919 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11920 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11921 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11922 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
11923 | break; | |
11924 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11925 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11926 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11927 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11928 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11929 | break; | |
11930 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11931 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11932 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11933 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11934 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11935 | break; | |
11936 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11937 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11938 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11939 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11940 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11941 | break; | |
6b91fa02 MC |
11942 | } |
11943 | } | |
11944 | } | |
11945 | ||
b5d3772c MC |
11946 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
11947 | { | |
11948 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11949 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11950 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11951 | } | |
11952 | ||
321d32a0 MC |
11953 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
11954 | { | |
11955 | u32 nvcfg1; | |
11956 | ||
11957 | nvcfg1 = tr32(NVRAM_CFG1); | |
11958 | ||
11959 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11960 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11961 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11962 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11963 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11964 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11965 | ||
11966 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11967 | tw32(NVRAM_CFG1, nvcfg1); | |
11968 | return; | |
11969 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11970 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11971 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11972 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11973 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11974 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11975 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11976 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11977 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11978 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11979 | ||
11980 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11981 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11982 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11983 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11984 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11985 | break; | |
11986 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11987 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11988 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11989 | break; | |
11990 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11991 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11992 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11993 | break; | |
11994 | } | |
11995 | break; | |
11996 | case FLASH_5752VENDOR_ST_M45PE10: | |
11997 | case FLASH_5752VENDOR_ST_M45PE20: | |
11998 | case FLASH_5752VENDOR_ST_M45PE40: | |
11999 | tp->nvram_jedecnum = JEDEC_ST; | |
12000 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12001 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
12002 | ||
12003 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12004 | case FLASH_5752VENDOR_ST_M45PE10: | |
12005 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12006 | break; | |
12007 | case FLASH_5752VENDOR_ST_M45PE20: | |
12008 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12009 | break; | |
12010 | case FLASH_5752VENDOR_ST_M45PE40: | |
12011 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12012 | break; | |
12013 | } | |
12014 | break; | |
12015 | default: | |
df259d8c | 12016 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; |
321d32a0 MC |
12017 | return; |
12018 | } | |
12019 | ||
a1b950d5 MC |
12020 | tg3_nvram_get_pagesize(tp, nvcfg1); |
12021 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
321d32a0 | 12022 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; |
a1b950d5 MC |
12023 | } |
12024 | ||
12025 | ||
12026 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
12027 | { | |
12028 | u32 nvcfg1; | |
12029 | ||
12030 | nvcfg1 = tr32(NVRAM_CFG1); | |
12031 | ||
12032 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12033 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
12034 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
12035 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12036 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12037 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12038 | ||
12039 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12040 | tw32(NVRAM_CFG1, nvcfg1); | |
12041 | return; | |
12042 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
12043 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
12044 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
12045 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12046 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12047 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12048 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
12049 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12050 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12051 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
12052 | ||
12053 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12054 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
12055 | /* Detect size with tg3_nvram_get_size() */ |
12056 | break; | |
a1b950d5 MC |
12057 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
12058 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12059 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12060 | break; | |
12061 | default: | |
12062 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12063 | break; | |
12064 | } | |
321d32a0 | 12065 | break; |
a1b950d5 MC |
12066 | case FLASH_5717VENDOR_ST_M_M25PE10: |
12067 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
12068 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
12069 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
12070 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12071 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12072 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12073 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12074 | case FLASH_5717VENDOR_ST_25USPT: | |
12075 | case FLASH_5717VENDOR_ST_45USPT: | |
12076 | tp->nvram_jedecnum = JEDEC_ST; | |
12077 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12078 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
12079 | ||
12080 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12081 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 12082 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
12083 | /* Detect size with tg3_nvram_get_size() */ |
12084 | break; | |
12085 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
12086 | case FLASH_5717VENDOR_ST_A_M45PE20: |
12087 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12088 | break; | |
12089 | default: | |
12090 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12091 | break; | |
12092 | } | |
321d32a0 | 12093 | break; |
a1b950d5 MC |
12094 | default: |
12095 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
12096 | return; | |
321d32a0 | 12097 | } |
a1b950d5 MC |
12098 | |
12099 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12100 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
12101 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
321d32a0 MC |
12102 | } |
12103 | ||
9b91b5f1 MC |
12104 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
12105 | { | |
12106 | u32 nvcfg1, nvmpinstrp; | |
12107 | ||
12108 | nvcfg1 = tr32(NVRAM_CFG1); | |
12109 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
12110 | ||
12111 | switch (nvmpinstrp) { | |
12112 | case FLASH_5720_EEPROM_HD: | |
12113 | case FLASH_5720_EEPROM_LD: | |
12114 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12115 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12116 | ||
12117 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12118 | tw32(NVRAM_CFG1, nvcfg1); | |
12119 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
12120 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12121 | else | |
12122 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
12123 | return; | |
12124 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
12125 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
12126 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
12127 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12128 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12129 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12130 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12131 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12132 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12133 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12134 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12135 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
12136 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12137 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12138 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
12139 | ||
12140 | switch (nvmpinstrp) { | |
12141 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12142 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12143 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12144 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12145 | break; | |
12146 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12147 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12148 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12149 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12150 | break; | |
12151 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12152 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12153 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12154 | break; | |
12155 | default: | |
12156 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12157 | break; | |
12158 | } | |
12159 | break; | |
12160 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
12161 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
12162 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
12163 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
12164 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12165 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12166 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12167 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12168 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12169 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12170 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12171 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12172 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12173 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12174 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12175 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12176 | case FLASH_5720VENDOR_ST_25USPT: | |
12177 | case FLASH_5720VENDOR_ST_45USPT: | |
12178 | tp->nvram_jedecnum = JEDEC_ST; | |
12179 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12180 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
12181 | ||
12182 | switch (nvmpinstrp) { | |
12183 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12184 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12185 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12186 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12187 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12188 | break; | |
12189 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12190 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12191 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12192 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12193 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12194 | break; | |
12195 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12196 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12197 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12198 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12199 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12200 | break; | |
12201 | default: | |
12202 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12203 | break; | |
12204 | } | |
12205 | break; | |
12206 | default: | |
12207 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
12208 | return; | |
12209 | } | |
12210 | ||
12211 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12212 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
12213 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
12214 | } | |
12215 | ||
1da177e4 LT |
12216 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
12217 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
12218 | { | |
1da177e4 LT |
12219 | tw32_f(GRC_EEPROM_ADDR, |
12220 | (EEPROM_ADDR_FSM_RESET | | |
12221 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
12222 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
12223 | ||
9d57f01c | 12224 | msleep(1); |
1da177e4 LT |
12225 | |
12226 | /* Enable seeprom accesses. */ | |
12227 | tw32_f(GRC_LOCAL_CTRL, | |
12228 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
12229 | udelay(100); | |
12230 | ||
12231 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12232 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
12233 | tp->tg3_flags |= TG3_FLAG_NVRAM; | |
12234 | ||
ec41c7df | 12235 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
12236 | netdev_warn(tp->dev, |
12237 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 12238 | __func__); |
ec41c7df MC |
12239 | return; |
12240 | } | |
e6af301b | 12241 | tg3_enable_nvram_access(tp); |
1da177e4 | 12242 | |
989a9d23 MC |
12243 | tp->nvram_size = 0; |
12244 | ||
361b4ac2 MC |
12245 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
12246 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
12247 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
12248 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 12249 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
12250 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
12251 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 12252 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
12253 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
12254 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
12255 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12256 | tg3_get_5906_nvram_info(tp); | |
b703df6f MC |
12257 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12258 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 | 12259 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
12260 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12261 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 12262 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
12263 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
12264 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
12265 | else |
12266 | tg3_get_nvram_info(tp); | |
12267 | ||
989a9d23 MC |
12268 | if (tp->nvram_size == 0) |
12269 | tg3_get_nvram_size(tp); | |
1da177e4 | 12270 | |
e6af301b | 12271 | tg3_disable_nvram_access(tp); |
381291b7 | 12272 | tg3_nvram_unlock(tp); |
1da177e4 LT |
12273 | |
12274 | } else { | |
12275 | tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); | |
12276 | ||
12277 | tg3_get_eeprom_size(tp); | |
12278 | } | |
12279 | } | |
12280 | ||
1da177e4 LT |
12281 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
12282 | u32 offset, u32 len, u8 *buf) | |
12283 | { | |
12284 | int i, j, rc = 0; | |
12285 | u32 val; | |
12286 | ||
12287 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 12288 | u32 addr; |
a9dc529d | 12289 | __be32 data; |
1da177e4 LT |
12290 | |
12291 | addr = offset + i; | |
12292 | ||
12293 | memcpy(&data, buf + i, 4); | |
12294 | ||
62cedd11 MC |
12295 | /* |
12296 | * The SEEPROM interface expects the data to always be opposite | |
12297 | * the native endian format. We accomplish this by reversing | |
12298 | * all the operations that would have been performed on the | |
12299 | * data from a call to tg3_nvram_read_be32(). | |
12300 | */ | |
12301 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
12302 | |
12303 | val = tr32(GRC_EEPROM_ADDR); | |
12304 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
12305 | ||
12306 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
12307 | EEPROM_ADDR_READ); | |
12308 | tw32(GRC_EEPROM_ADDR, val | | |
12309 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
12310 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
12311 | EEPROM_ADDR_START | | |
12312 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 12313 | |
9d57f01c | 12314 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
12315 | val = tr32(GRC_EEPROM_ADDR); |
12316 | ||
12317 | if (val & EEPROM_ADDR_COMPLETE) | |
12318 | break; | |
9d57f01c | 12319 | msleep(1); |
1da177e4 LT |
12320 | } |
12321 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
12322 | rc = -EBUSY; | |
12323 | break; | |
12324 | } | |
12325 | } | |
12326 | ||
12327 | return rc; | |
12328 | } | |
12329 | ||
12330 | /* offset and length are dword aligned */ | |
12331 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
12332 | u8 *buf) | |
12333 | { | |
12334 | int ret = 0; | |
12335 | u32 pagesize = tp->nvram_pagesize; | |
12336 | u32 pagemask = pagesize - 1; | |
12337 | u32 nvram_cmd; | |
12338 | u8 *tmp; | |
12339 | ||
12340 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
12341 | if (tmp == NULL) | |
12342 | return -ENOMEM; | |
12343 | ||
12344 | while (len) { | |
12345 | int j; | |
e6af301b | 12346 | u32 phy_addr, page_off, size; |
1da177e4 LT |
12347 | |
12348 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 12349 | |
1da177e4 | 12350 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
12351 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
12352 | (__be32 *) (tmp + j)); | |
12353 | if (ret) | |
1da177e4 LT |
12354 | break; |
12355 | } | |
12356 | if (ret) | |
12357 | break; | |
12358 | ||
c6cdf436 | 12359 | page_off = offset & pagemask; |
1da177e4 LT |
12360 | size = pagesize; |
12361 | if (len < size) | |
12362 | size = len; | |
12363 | ||
12364 | len -= size; | |
12365 | ||
12366 | memcpy(tmp + page_off, buf, size); | |
12367 | ||
12368 | offset = offset + (pagesize - page_off); | |
12369 | ||
e6af301b | 12370 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
12371 | |
12372 | /* | |
12373 | * Before we can erase the flash page, we need | |
12374 | * to issue a special "write enable" command. | |
12375 | */ | |
12376 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12377 | ||
12378 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12379 | break; | |
12380 | ||
12381 | /* Erase the target page */ | |
12382 | tw32(NVRAM_ADDR, phy_addr); | |
12383 | ||
12384 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
12385 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
12386 | ||
c6cdf436 | 12387 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
12388 | break; |
12389 | ||
12390 | /* Issue another write enable to start the write. */ | |
12391 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12392 | ||
12393 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12394 | break; | |
12395 | ||
12396 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 12397 | __be32 data; |
1da177e4 | 12398 | |
b9fc7dc5 | 12399 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 12400 | |
b9fc7dc5 | 12401 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
12402 | |
12403 | tw32(NVRAM_ADDR, phy_addr + j); | |
12404 | ||
12405 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12406 | NVRAM_CMD_WR; | |
12407 | ||
12408 | if (j == 0) | |
12409 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12410 | else if (j == (pagesize - 4)) | |
12411 | nvram_cmd |= NVRAM_CMD_LAST; | |
12412 | ||
12413 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12414 | break; | |
12415 | } | |
12416 | if (ret) | |
12417 | break; | |
12418 | } | |
12419 | ||
12420 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12421 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12422 | ||
12423 | kfree(tmp); | |
12424 | ||
12425 | return ret; | |
12426 | } | |
12427 | ||
12428 | /* offset and length are dword aligned */ | |
12429 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12430 | u8 *buf) | |
12431 | { | |
12432 | int i, ret = 0; | |
12433 | ||
12434 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
12435 | u32 page_off, phy_addr, nvram_cmd; |
12436 | __be32 data; | |
1da177e4 LT |
12437 | |
12438 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 12439 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 12440 | |
c6cdf436 | 12441 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 12442 | |
1820180b | 12443 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
12444 | |
12445 | tw32(NVRAM_ADDR, phy_addr); | |
12446 | ||
12447 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12448 | ||
c6cdf436 | 12449 | if (page_off == 0 || i == 0) |
1da177e4 | 12450 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 12451 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
12452 | nvram_cmd |= NVRAM_CMD_LAST; |
12453 | ||
12454 | if (i == (len - 4)) | |
12455 | nvram_cmd |= NVRAM_CMD_LAST; | |
12456 | ||
321d32a0 MC |
12457 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
12458 | !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
4c987487 MC |
12459 | (tp->nvram_jedecnum == JEDEC_ST) && |
12460 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
12461 | |
12462 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12463 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12464 | NVRAM_CMD_DONE))) | |
12465 | ||
12466 | break; | |
12467 | } | |
12468 | if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12469 | /* We always do complete word writes to eeprom. */ | |
12470 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12471 | } | |
12472 | ||
12473 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12474 | break; | |
12475 | } | |
12476 | return ret; | |
12477 | } | |
12478 | ||
12479 | /* offset and length are dword aligned */ | |
12480 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12481 | { | |
12482 | int ret; | |
12483 | ||
1da177e4 | 12484 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
314fba34 MC |
12485 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
12486 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
12487 | udelay(40); |
12488 | } | |
12489 | ||
12490 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { | |
12491 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
859a5887 | 12492 | } else { |
1da177e4 LT |
12493 | u32 grc_mode; |
12494 | ||
ec41c7df MC |
12495 | ret = tg3_nvram_lock(tp); |
12496 | if (ret) | |
12497 | return ret; | |
1da177e4 | 12498 | |
e6af301b MC |
12499 | tg3_enable_nvram_access(tp); |
12500 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 12501 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) |
1da177e4 | 12502 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
12503 | |
12504 | grc_mode = tr32(GRC_MODE); | |
12505 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12506 | ||
12507 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || | |
12508 | !(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12509 | ||
12510 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
12511 | buf); | |
859a5887 | 12512 | } else { |
1da177e4 LT |
12513 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
12514 | buf); | |
12515 | } | |
12516 | ||
12517 | grc_mode = tr32(GRC_MODE); | |
12518 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12519 | ||
e6af301b | 12520 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
12521 | tg3_nvram_unlock(tp); |
12522 | } | |
12523 | ||
12524 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
314fba34 | 12525 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
12526 | udelay(40); |
12527 | } | |
12528 | ||
12529 | return ret; | |
12530 | } | |
12531 | ||
12532 | struct subsys_tbl_ent { | |
12533 | u16 subsys_vendor, subsys_devid; | |
12534 | u32 phy_id; | |
12535 | }; | |
12536 | ||
24daf2b0 | 12537 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 12538 | /* Broadcom boards. */ |
24daf2b0 | 12539 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12540 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12541 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12542 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12543 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12544 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
12545 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12546 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12547 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12548 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12549 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12550 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12551 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12552 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12553 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12554 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12555 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12556 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12557 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12558 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 12559 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12560 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
12561 | |
12562 | /* 3com boards. */ | |
24daf2b0 | 12563 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12564 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12565 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12566 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12567 | { TG3PCI_SUBVENDOR_ID_3COM, |
12568 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12569 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 12570 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12571 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12572 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12573 | |
12574 | /* DELL boards. */ | |
24daf2b0 | 12575 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12576 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12577 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12578 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12579 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12580 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 12581 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12582 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
12583 | |
12584 | /* Compaq boards. */ | |
24daf2b0 | 12585 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12586 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12587 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12588 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12589 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
12590 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12591 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 12592 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12593 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12594 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12595 | |
12596 | /* IBM boards. */ | |
24daf2b0 MC |
12597 | { TG3PCI_SUBVENDOR_ID_IBM, |
12598 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
12599 | }; |
12600 | ||
24daf2b0 | 12601 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
12602 | { |
12603 | int i; | |
12604 | ||
12605 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12606 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12607 | tp->pdev->subsystem_vendor) && | |
12608 | (subsys_id_to_phy_id[i].subsys_devid == | |
12609 | tp->pdev->subsystem_device)) | |
12610 | return &subsys_id_to_phy_id[i]; | |
12611 | } | |
12612 | return NULL; | |
12613 | } | |
12614 | ||
7d0c41ef | 12615 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 12616 | { |
1da177e4 | 12617 | u32 val; |
caf636c7 MC |
12618 | u16 pmcsr; |
12619 | ||
12620 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
12621 | * so need make sure we're in D0. | |
12622 | */ | |
12623 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
12624 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
12625 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
12626 | msleep(1); | |
7d0c41ef MC |
12627 | |
12628 | /* Make sure register accesses (indirect or otherwise) | |
12629 | * will function correctly. | |
12630 | */ | |
12631 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12632 | tp->misc_host_ctrl); | |
1da177e4 | 12633 | |
f49639e6 DM |
12634 | /* The memory arbiter has to be enabled in order for SRAM accesses |
12635 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
12636 | * sure it is enabled, but other entities such as system netboot | |
12637 | * code might disable it. | |
12638 | */ | |
12639 | val = tr32(MEMARB_MODE); | |
12640 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
12641 | ||
79eb6904 | 12642 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12643 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12644 | ||
a85feb8c GZ |
12645 | /* Assume an onboard device and WOL capable by default. */ |
12646 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; | |
72b845e0 | 12647 | |
b5d3772c | 12648 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12649 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
b5d3772c | 12650 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12651 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12652 | } | |
0527ba35 MC |
12653 | val = tr32(VCPU_CFGSHDW); |
12654 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
8ed5d97e | 12655 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; |
0527ba35 | 12656 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
2023276e | 12657 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) |
0527ba35 | 12658 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
05ac4cb7 | 12659 | goto done; |
b5d3772c MC |
12660 | } |
12661 | ||
1da177e4 LT |
12662 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
12663 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12664 | u32 nic_cfg, led_cfg; | |
a9daf367 | 12665 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 12666 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
12667 | |
12668 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12669 | tp->nic_sram_data_cfg = nic_cfg; | |
12670 | ||
12671 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12672 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
12673 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && | |
12674 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && | |
12675 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) && | |
12676 | (ver > 0) && (ver < 0x100)) | |
12677 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12678 | ||
a9daf367 MC |
12679 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
12680 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12681 | ||
1da177e4 LT |
12682 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
12683 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12684 | eeprom_phy_serdes = 1; | |
12685 | ||
12686 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12687 | if (nic_phy_id != 0) { | |
12688 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12689 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12690 | ||
12691 | eeprom_phy_id = (id1 >> 16) << 10; | |
12692 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12693 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12694 | } else | |
12695 | eeprom_phy_id = 0; | |
12696 | ||
7d0c41ef | 12697 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 12698 | if (eeprom_phy_serdes) { |
a50d0796 | 12699 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
f07e9af3 | 12700 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 12701 | else |
f07e9af3 | 12702 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 12703 | } |
7d0c41ef | 12704 | |
cbf46853 | 12705 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12706 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
12707 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 12708 | else |
1da177e4 LT |
12709 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
12710 | ||
12711 | switch (led_cfg) { | |
12712 | default: | |
12713 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12714 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12715 | break; | |
12716 | ||
12717 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12718 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12719 | break; | |
12720 | ||
12721 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12722 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
12723 | |
12724 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12725 | * read on some older 5700/5701 bootcode. | |
12726 | */ | |
12727 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12728 | ASIC_REV_5700 || | |
12729 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12730 | ASIC_REV_5701) | |
12731 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12732 | ||
1da177e4 LT |
12733 | break; |
12734 | ||
12735 | case SHASTA_EXT_LED_SHARED: | |
12736 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12737 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12738 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12739 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12740 | LED_CTRL_MODE_PHY_2); | |
12741 | break; | |
12742 | ||
12743 | case SHASTA_EXT_LED_MAC: | |
12744 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12745 | break; | |
12746 | ||
12747 | case SHASTA_EXT_LED_COMBO: | |
12748 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12749 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12750 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12751 | LED_CTRL_MODE_PHY_2); | |
12752 | break; | |
12753 | ||
855e1111 | 12754 | } |
1da177e4 LT |
12755 | |
12756 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12757 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12758 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12759 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12760 | ||
b2a5c19c MC |
12761 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
12762 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 12763 | |
9d26e213 | 12764 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
1da177e4 | 12765 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12766 | if ((tp->pdev->subsystem_vendor == |
12767 | PCI_VENDOR_ID_ARIMA) && | |
12768 | (tp->pdev->subsystem_device == 0x205a || | |
12769 | tp->pdev->subsystem_device == 0x2063)) | |
12770 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
12771 | } else { | |
f49639e6 | 12772 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12773 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12774 | } | |
1da177e4 LT |
12775 | |
12776 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
12777 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
cbf46853 | 12778 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12779 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
12780 | } | |
b2b98d4a MC |
12781 | |
12782 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
12783 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
0d3031d9 | 12784 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; |
b2b98d4a | 12785 | |
f07e9af3 | 12786 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c GZ |
12787 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
12788 | tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; | |
1da177e4 | 12789 | |
12dac075 | 12790 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
05ac4cb7 | 12791 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) |
0527ba35 MC |
12792 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
12793 | ||
1da177e4 | 12794 | if (cfg2 & (1 << 17)) |
f07e9af3 | 12795 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
12796 | |
12797 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
12798 | /* bootcode if bit 18 is set */ | |
12799 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 12800 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 12801 | |
1407deb1 | 12802 | if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) || |
2e1e3291 MC |
12803 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
12804 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) && | |
6833c043 | 12805 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 12806 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 12807 | |
8c69b1e7 MC |
12808 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
12809 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
1407deb1 | 12810 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
8ed5d97e MC |
12811 | u32 cfg3; |
12812 | ||
12813 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
12814 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
12815 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
12816 | } | |
a9daf367 | 12817 | |
14417063 MC |
12818 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
12819 | tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE; | |
a9daf367 MC |
12820 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
12821 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; | |
12822 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
12823 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; | |
1da177e4 | 12824 | } |
05ac4cb7 | 12825 | done: |
43067ed8 RW |
12826 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
12827 | device_set_wakeup_enable(&tp->pdev->dev, | |
05ac4cb7 | 12828 | tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
43067ed8 RW |
12829 | else |
12830 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
12831 | } |
12832 | ||
b2a5c19c MC |
12833 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
12834 | { | |
12835 | int i; | |
12836 | u32 val; | |
12837 | ||
12838 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
12839 | tw32(OTP_CTRL, cmd); | |
12840 | ||
12841 | /* Wait for up to 1 ms for command to execute. */ | |
12842 | for (i = 0; i < 100; i++) { | |
12843 | val = tr32(OTP_STATUS); | |
12844 | if (val & OTP_STATUS_CMD_DONE) | |
12845 | break; | |
12846 | udelay(10); | |
12847 | } | |
12848 | ||
12849 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
12850 | } | |
12851 | ||
12852 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
12853 | * configuration is a 32-bit value that straddles the alignment boundary. | |
12854 | * We do two 32-bit reads and then shift and merge the results. | |
12855 | */ | |
12856 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
12857 | { | |
12858 | u32 bhalf_otp, thalf_otp; | |
12859 | ||
12860 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
12861 | ||
12862 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
12863 | return 0; | |
12864 | ||
12865 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
12866 | ||
12867 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12868 | return 0; | |
12869 | ||
12870 | thalf_otp = tr32(OTP_READ_DATA); | |
12871 | ||
12872 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
12873 | ||
12874 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12875 | return 0; | |
12876 | ||
12877 | bhalf_otp = tr32(OTP_READ_DATA); | |
12878 | ||
12879 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
12880 | } | |
12881 | ||
e256f8a3 MC |
12882 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
12883 | { | |
12884 | u32 adv = ADVERTISED_Autoneg | | |
12885 | ADVERTISED_Pause; | |
12886 | ||
12887 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
12888 | adv |= ADVERTISED_1000baseT_Half | | |
12889 | ADVERTISED_1000baseT_Full; | |
12890 | ||
12891 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
12892 | adv |= ADVERTISED_100baseT_Half | | |
12893 | ADVERTISED_100baseT_Full | | |
12894 | ADVERTISED_10baseT_Half | | |
12895 | ADVERTISED_10baseT_Full | | |
12896 | ADVERTISED_TP; | |
12897 | else | |
12898 | adv |= ADVERTISED_FIBRE; | |
12899 | ||
12900 | tp->link_config.advertising = adv; | |
12901 | tp->link_config.speed = SPEED_INVALID; | |
12902 | tp->link_config.duplex = DUPLEX_INVALID; | |
12903 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
12904 | tp->link_config.active_speed = SPEED_INVALID; | |
12905 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
12906 | tp->link_config.orig_speed = SPEED_INVALID; | |
12907 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
12908 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
12909 | } | |
12910 | ||
7d0c41ef MC |
12911 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
12912 | { | |
12913 | u32 hw_phy_id_1, hw_phy_id_2; | |
12914 | u32 hw_phy_id, hw_phy_id_masked; | |
12915 | int err; | |
1da177e4 | 12916 | |
e256f8a3 MC |
12917 | /* flow control autonegotiation is default behavior */ |
12918 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
12919 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
12920 | ||
b02fd9e3 MC |
12921 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
12922 | return tg3_phy_init(tp); | |
12923 | ||
1da177e4 | 12924 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 12925 | * firmware access to the PHY hardware. |
1da177e4 LT |
12926 | */ |
12927 | err = 0; | |
0d3031d9 MC |
12928 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || |
12929 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
79eb6904 | 12930 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
12931 | } else { |
12932 | /* Now read the physical PHY_ID from the chip and verify | |
12933 | * that it is sane. If it doesn't look good, we fall back | |
12934 | * to either the hard-coded table based PHY_ID and failing | |
12935 | * that the value found in the eeprom area. | |
12936 | */ | |
12937 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
12938 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
12939 | ||
12940 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
12941 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
12942 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
12943 | ||
79eb6904 | 12944 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
12945 | } |
12946 | ||
79eb6904 | 12947 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 12948 | tp->phy_id = hw_phy_id; |
79eb6904 | 12949 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 12950 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 12951 | else |
f07e9af3 | 12952 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 12953 | } else { |
79eb6904 | 12954 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
12955 | /* Do nothing, phy ID already set up in |
12956 | * tg3_get_eeprom_hw_cfg(). | |
12957 | */ | |
1da177e4 LT |
12958 | } else { |
12959 | struct subsys_tbl_ent *p; | |
12960 | ||
12961 | /* No eeprom signature? Try the hardcoded | |
12962 | * subsys device table. | |
12963 | */ | |
24daf2b0 | 12964 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
12965 | if (!p) |
12966 | return -ENODEV; | |
12967 | ||
12968 | tp->phy_id = p->phy_id; | |
12969 | if (!tp->phy_id || | |
79eb6904 | 12970 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 12971 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
12972 | } |
12973 | } | |
12974 | ||
a6b68dab MC |
12975 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
12976 | ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
12977 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || | |
12978 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
12979 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
12980 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
12981 | ||
e256f8a3 MC |
12982 | tg3_phy_init_link_config(tp); |
12983 | ||
f07e9af3 | 12984 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
0d3031d9 | 12985 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && |
1da177e4 | 12986 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
3600d918 | 12987 | u32 bmsr, adv_reg, tg3_ctrl, mask; |
1da177e4 LT |
12988 | |
12989 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
12990 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
12991 | (bmsr & BMSR_LSTATUS)) | |
12992 | goto skip_phy_reset; | |
6aa20a22 | 12993 | |
1da177e4 LT |
12994 | err = tg3_phy_reset(tp); |
12995 | if (err) | |
12996 | return err; | |
12997 | ||
12998 | adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
12999 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
13000 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
13001 | tg3_ctrl = 0; | |
f07e9af3 | 13002 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
13003 | tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | |
13004 | MII_TG3_CTRL_ADV_1000_FULL); | |
13005 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
13006 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
13007 | tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER | | |
13008 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
13009 | } | |
13010 | ||
3600d918 MC |
13011 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
13012 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
13013 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
13014 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
1da177e4 LT |
13015 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); |
13016 | ||
f07e9af3 | 13017 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
13018 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); |
13019 | ||
13020 | tg3_writephy(tp, MII_BMCR, | |
13021 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13022 | } | |
13023 | tg3_phy_set_wirespeed(tp); | |
13024 | ||
13025 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
f07e9af3 | 13026 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
13027 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); |
13028 | } | |
13029 | ||
13030 | skip_phy_reset: | |
79eb6904 | 13031 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
13032 | err = tg3_init_5401phy_dsp(tp); |
13033 | if (err) | |
13034 | return err; | |
1da177e4 | 13035 | |
1da177e4 LT |
13036 | err = tg3_init_5401phy_dsp(tp); |
13037 | } | |
13038 | ||
1da177e4 LT |
13039 | return err; |
13040 | } | |
13041 | ||
184b8904 | 13042 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 13043 | { |
a4a8bb15 | 13044 | u8 *vpd_data; |
4181b2c8 | 13045 | unsigned int block_end, rosize, len; |
184b8904 | 13046 | int j, i = 0; |
a4a8bb15 | 13047 | |
c3e94500 | 13048 | vpd_data = (u8 *)tg3_vpd_readblock(tp); |
a4a8bb15 MC |
13049 | if (!vpd_data) |
13050 | goto out_no_vpd; | |
1da177e4 | 13051 | |
4181b2c8 MC |
13052 | i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN, |
13053 | PCI_VPD_LRDT_RO_DATA); | |
13054 | if (i < 0) | |
13055 | goto out_not_found; | |
1da177e4 | 13056 | |
4181b2c8 MC |
13057 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
13058 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
13059 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 13060 | |
4181b2c8 MC |
13061 | if (block_end > TG3_NVM_VPD_LEN) |
13062 | goto out_not_found; | |
af2c6a4a | 13063 | |
184b8904 MC |
13064 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13065 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
13066 | if (j > 0) { | |
13067 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13068 | ||
13069 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13070 | if (j + len > block_end || len != 4 || | |
13071 | memcmp(&vpd_data[j], "1028", 4)) | |
13072 | goto partno; | |
13073 | ||
13074 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13075 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
13076 | if (j < 0) | |
13077 | goto partno; | |
13078 | ||
13079 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13080 | ||
13081 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13082 | if (j + len > block_end) | |
13083 | goto partno; | |
13084 | ||
13085 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
13086 | strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1); | |
13087 | } | |
13088 | ||
13089 | partno: | |
4181b2c8 MC |
13090 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13091 | PCI_VPD_RO_KEYWORD_PARTNO); | |
13092 | if (i < 0) | |
13093 | goto out_not_found; | |
af2c6a4a | 13094 | |
4181b2c8 | 13095 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 13096 | |
4181b2c8 MC |
13097 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
13098 | if (len > TG3_BPN_SIZE || | |
13099 | (len + i) > TG3_NVM_VPD_LEN) | |
13100 | goto out_not_found; | |
1da177e4 | 13101 | |
4181b2c8 | 13102 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 13103 | |
1da177e4 | 13104 | out_not_found: |
a4a8bb15 | 13105 | kfree(vpd_data); |
37a949c5 | 13106 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
13107 | return; |
13108 | ||
13109 | out_no_vpd: | |
37a949c5 MC |
13110 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13111 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
13112 | strcpy(tp->board_part_number, "BCM5717"); | |
13113 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
13114 | strcpy(tp->board_part_number, "BCM5718"); | |
13115 | else | |
13116 | goto nomatch; | |
13117 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
13118 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
13119 | strcpy(tp->board_part_number, "BCM57780"); | |
13120 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
13121 | strcpy(tp->board_part_number, "BCM57760"); | |
13122 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
13123 | strcpy(tp->board_part_number, "BCM57790"); | |
13124 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
13125 | strcpy(tp->board_part_number, "BCM57788"); | |
13126 | else | |
13127 | goto nomatch; | |
13128 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13129 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
13130 | strcpy(tp->board_part_number, "BCM57761"); | |
13131 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
13132 | strcpy(tp->board_part_number, "BCM57765"); | |
13133 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
13134 | strcpy(tp->board_part_number, "BCM57781"); | |
13135 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
13136 | strcpy(tp->board_part_number, "BCM57785"); | |
13137 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
13138 | strcpy(tp->board_part_number, "BCM57791"); | |
13139 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13140 | strcpy(tp->board_part_number, "BCM57795"); | |
13141 | else | |
13142 | goto nomatch; | |
13143 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
b5d3772c | 13144 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
13145 | } else { |
13146 | nomatch: | |
b5d3772c | 13147 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 13148 | } |
1da177e4 LT |
13149 | } |
13150 | ||
9c8a620e MC |
13151 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
13152 | { | |
13153 | u32 val; | |
13154 | ||
e4f34110 | 13155 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 13156 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 13157 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
13158 | val != 0) |
13159 | return 0; | |
13160 | ||
13161 | return 1; | |
13162 | } | |
13163 | ||
acd9c119 MC |
13164 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
13165 | { | |
ff3a7cb2 | 13166 | u32 val, offset, start, ver_offset; |
75f9936e | 13167 | int i, dst_off; |
ff3a7cb2 | 13168 | bool newver = false; |
acd9c119 MC |
13169 | |
13170 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
13171 | tg3_nvram_read(tp, 0x4, &start)) | |
13172 | return; | |
13173 | ||
13174 | offset = tg3_nvram_logical_addr(tp, offset); | |
13175 | ||
ff3a7cb2 | 13176 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
13177 | return; |
13178 | ||
ff3a7cb2 MC |
13179 | if ((val & 0xfc000000) == 0x0c000000) { |
13180 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
13181 | return; |
13182 | ||
ff3a7cb2 MC |
13183 | if (val == 0) |
13184 | newver = true; | |
13185 | } | |
13186 | ||
75f9936e MC |
13187 | dst_off = strlen(tp->fw_ver); |
13188 | ||
ff3a7cb2 | 13189 | if (newver) { |
75f9936e MC |
13190 | if (TG3_VER_SIZE - dst_off < 16 || |
13191 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
13192 | return; |
13193 | ||
13194 | offset = offset + ver_offset - start; | |
13195 | for (i = 0; i < 16; i += 4) { | |
13196 | __be32 v; | |
13197 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13198 | return; | |
13199 | ||
75f9936e | 13200 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
13201 | } |
13202 | } else { | |
13203 | u32 major, minor; | |
13204 | ||
13205 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13206 | return; | |
13207 | ||
13208 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13209 | TG3_NVM_BCVER_MAJSFT; | |
13210 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
13211 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
13212 | "v%d.%02d", major, minor); | |
acd9c119 MC |
13213 | } |
13214 | } | |
13215 | ||
a6f6cb1c MC |
13216 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
13217 | { | |
13218 | u32 val, major, minor; | |
13219 | ||
13220 | /* Use native endian representation */ | |
13221 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13222 | return; | |
13223 | ||
13224 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13225 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13226 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13227 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13228 | ||
13229 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13230 | } | |
13231 | ||
dfe00d7d MC |
13232 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
13233 | { | |
13234 | u32 offset, major, minor, build; | |
13235 | ||
75f9936e | 13236 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
13237 | |
13238 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13239 | return; | |
13240 | ||
13241 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13242 | case TG3_EEPROM_SB_REVISION_0: | |
13243 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13244 | break; | |
13245 | case TG3_EEPROM_SB_REVISION_2: | |
13246 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13247 | break; | |
13248 | case TG3_EEPROM_SB_REVISION_3: | |
13249 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13250 | break; | |
a4153d40 MC |
13251 | case TG3_EEPROM_SB_REVISION_4: |
13252 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13253 | break; | |
13254 | case TG3_EEPROM_SB_REVISION_5: | |
13255 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13256 | break; | |
bba226ac MC |
13257 | case TG3_EEPROM_SB_REVISION_6: |
13258 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13259 | break; | |
dfe00d7d MC |
13260 | default: |
13261 | return; | |
13262 | } | |
13263 | ||
e4f34110 | 13264 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
13265 | return; |
13266 | ||
13267 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13268 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13269 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13270 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13271 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13272 | ||
13273 | if (minor > 99 || build > 26) | |
13274 | return; | |
13275 | ||
75f9936e MC |
13276 | offset = strlen(tp->fw_ver); |
13277 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13278 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
13279 | |
13280 | if (build > 0) { | |
75f9936e MC |
13281 | offset = strlen(tp->fw_ver); |
13282 | if (offset < TG3_VER_SIZE - 1) | |
13283 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
13284 | } |
13285 | } | |
13286 | ||
acd9c119 | 13287 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
13288 | { |
13289 | u32 val, offset, start; | |
acd9c119 | 13290 | int i, vlen; |
9c8a620e MC |
13291 | |
13292 | for (offset = TG3_NVM_DIR_START; | |
13293 | offset < TG3_NVM_DIR_END; | |
13294 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 13295 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
13296 | return; |
13297 | ||
9c8a620e MC |
13298 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
13299 | break; | |
13300 | } | |
13301 | ||
13302 | if (offset == TG3_NVM_DIR_END) | |
13303 | return; | |
13304 | ||
13305 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
13306 | start = 0x08000000; | |
e4f34110 | 13307 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
13308 | return; |
13309 | ||
e4f34110 | 13310 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 13311 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 13312 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
13313 | return; |
13314 | ||
13315 | offset += val - start; | |
13316 | ||
acd9c119 | 13317 | vlen = strlen(tp->fw_ver); |
9c8a620e | 13318 | |
acd9c119 MC |
13319 | tp->fw_ver[vlen++] = ','; |
13320 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
13321 | |
13322 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
13323 | __be32 v; |
13324 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
13325 | return; |
13326 | ||
b9fc7dc5 | 13327 | offset += sizeof(v); |
c4e6575c | 13328 | |
acd9c119 MC |
13329 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
13330 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 13331 | break; |
c4e6575c | 13332 | } |
9c8a620e | 13333 | |
acd9c119 MC |
13334 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
13335 | vlen += sizeof(v); | |
c4e6575c | 13336 | } |
acd9c119 MC |
13337 | } |
13338 | ||
7fd76445 MC |
13339 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
13340 | { | |
13341 | int vlen; | |
13342 | u32 apedata; | |
ecc79648 | 13343 | char *fwtype; |
7fd76445 MC |
13344 | |
13345 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || | |
13346 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
13347 | return; | |
13348 | ||
13349 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13350 | if (apedata != APE_SEG_SIG_MAGIC) | |
13351 | return; | |
13352 | ||
13353 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13354 | if (!(apedata & APE_FW_STATUS_READY)) | |
13355 | return; | |
13356 | ||
13357 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13358 | ||
dc6d0744 MC |
13359 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
13360 | tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI; | |
ecc79648 | 13361 | fwtype = "NCSI"; |
dc6d0744 | 13362 | } else { |
ecc79648 | 13363 | fwtype = "DASH"; |
dc6d0744 | 13364 | } |
ecc79648 | 13365 | |
7fd76445 MC |
13366 | vlen = strlen(tp->fw_ver); |
13367 | ||
ecc79648 MC |
13368 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
13369 | fwtype, | |
7fd76445 MC |
13370 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
13371 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13372 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13373 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13374 | } | |
13375 | ||
acd9c119 MC |
13376 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
13377 | { | |
13378 | u32 val; | |
75f9936e | 13379 | bool vpd_vers = false; |
acd9c119 | 13380 | |
75f9936e MC |
13381 | if (tp->fw_ver[0] != 0) |
13382 | vpd_vers = true; | |
df259d8c | 13383 | |
75f9936e MC |
13384 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { |
13385 | strcat(tp->fw_ver, "sb"); | |
df259d8c MC |
13386 | return; |
13387 | } | |
13388 | ||
acd9c119 MC |
13389 | if (tg3_nvram_read(tp, 0, &val)) |
13390 | return; | |
13391 | ||
13392 | if (val == TG3_EEPROM_MAGIC) | |
13393 | tg3_read_bc_ver(tp); | |
13394 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13395 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13396 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13397 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13398 | else |
13399 | return; | |
13400 | ||
13401 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
75f9936e MC |
13402 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers) |
13403 | goto done; | |
acd9c119 MC |
13404 | |
13405 | tg3_read_mgmtfw_ver(tp); | |
9c8a620e | 13406 | |
75f9936e | 13407 | done: |
9c8a620e | 13408 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13409 | } |
13410 | ||
7544b097 MC |
13411 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
13412 | ||
7cb32cf2 MC |
13413 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13414 | { | |
de9f5230 MC |
13415 | if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) |
13416 | return TG3_RX_RET_MAX_SIZE_5717; | |
7cb32cf2 MC |
13417 | else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
13418 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
de9f5230 | 13419 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 13420 | else |
de9f5230 | 13421 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
13422 | } |
13423 | ||
4143470c | 13424 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
13425 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
13426 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13427 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13428 | { }, | |
13429 | }; | |
13430 | ||
1da177e4 LT |
13431 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
13432 | { | |
1da177e4 | 13433 | u32 misc_ctrl_reg; |
1da177e4 LT |
13434 | u32 pci_state_reg, grc_misc_cfg; |
13435 | u32 val; | |
13436 | u16 pci_cmd; | |
5e7dfd0f | 13437 | int err; |
1da177e4 | 13438 | |
1da177e4 LT |
13439 | /* Force memory write invalidate off. If we leave it on, |
13440 | * then on 5700_BX chips we have to enable a workaround. | |
13441 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13442 | * to match the cacheline size. The Broadcom driver have this | |
13443 | * workaround but turns MWI off all the times so never uses | |
13444 | * it. This seems to suggest that the workaround is insufficient. | |
13445 | */ | |
13446 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13447 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13448 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13449 | ||
13450 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
13451 | * has the register indirect write enable bit set before | |
13452 | * we try to access any of the MMIO registers. It is also | |
13453 | * critical that the PCI-X hw workaround situation is decided | |
13454 | * before that as well. | |
13455 | */ | |
13456 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13457 | &misc_ctrl_reg); | |
13458 | ||
13459 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13460 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
13461 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
13462 | u32 prod_id_asic_rev; | |
13463 | ||
5001e2f6 MC |
13464 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
13465 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
d78b59f5 MC |
13466 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
13467 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
f6eb9b1f MC |
13468 | pci_read_config_dword(tp->pdev, |
13469 | TG3PCI_GEN2_PRODID_ASICREV, | |
13470 | &prod_id_asic_rev); | |
b703df6f MC |
13471 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
13472 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13473 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13474 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13475 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
13476 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13477 | pci_read_config_dword(tp->pdev, | |
13478 | TG3PCI_GEN15_PRODID_ASICREV, | |
13479 | &prod_id_asic_rev); | |
f6eb9b1f MC |
13480 | else |
13481 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13482 | &prod_id_asic_rev); | |
13483 | ||
321d32a0 | 13484 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 13485 | } |
1da177e4 | 13486 | |
ff645bec MC |
13487 | /* Wrong chip ID in 5752 A0. This code can be removed later |
13488 | * as A0 is not in production. | |
13489 | */ | |
13490 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13491 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13492 | ||
6892914f MC |
13493 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
13494 | * we need to disable memory and use config. cycles | |
13495 | * only to access all registers. The 5702/03 chips | |
13496 | * can mistakenly decode the special cycles from the | |
13497 | * ICH chipsets as memory write cycles, causing corruption | |
13498 | * of register and memory space. Only certain ICH bridges | |
13499 | * will drive special cycles with non-zero data during the | |
13500 | * address phase which can fall within the 5703's address | |
13501 | * range. This is not an ICH bug as the PCI spec allows | |
13502 | * non-zero address during special cycles. However, only | |
13503 | * these ICH bridges are known to drive non-zero addresses | |
13504 | * during special cycles. | |
13505 | * | |
13506 | * Since special cycles do not cross PCI bridges, we only | |
13507 | * enable this workaround if the 5703 is on the secondary | |
13508 | * bus of these ICH bridges. | |
13509 | */ | |
13510 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13511 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13512 | static struct tg3_dev_id { | |
13513 | u32 vendor; | |
13514 | u32 device; | |
13515 | u32 rev; | |
13516 | } ich_chipsets[] = { | |
13517 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13518 | PCI_ANY_ID }, | |
13519 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13520 | PCI_ANY_ID }, | |
13521 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13522 | 0xa }, | |
13523 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13524 | PCI_ANY_ID }, | |
13525 | { }, | |
13526 | }; | |
13527 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13528 | struct pci_dev *bridge = NULL; | |
13529 | ||
13530 | while (pci_id->vendor != 0) { | |
13531 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13532 | bridge); | |
13533 | if (!bridge) { | |
13534 | pci_id++; | |
13535 | continue; | |
13536 | } | |
13537 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 13538 | if (bridge->revision > pci_id->rev) |
6892914f MC |
13539 | continue; |
13540 | } | |
13541 | if (bridge->subordinate && | |
13542 | (bridge->subordinate->number == | |
13543 | tp->pdev->bus->number)) { | |
13544 | ||
13545 | tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND; | |
13546 | pci_dev_put(bridge); | |
13547 | break; | |
13548 | } | |
13549 | } | |
13550 | } | |
13551 | ||
41588ba1 MC |
13552 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { |
13553 | static struct tg3_dev_id { | |
13554 | u32 vendor; | |
13555 | u32 device; | |
13556 | } bridge_chipsets[] = { | |
13557 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13558 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13559 | { }, | |
13560 | }; | |
13561 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13562 | struct pci_dev *bridge = NULL; | |
13563 | ||
13564 | while (pci_id->vendor != 0) { | |
13565 | bridge = pci_get_device(pci_id->vendor, | |
13566 | pci_id->device, | |
13567 | bridge); | |
13568 | if (!bridge) { | |
13569 | pci_id++; | |
13570 | continue; | |
13571 | } | |
13572 | if (bridge->subordinate && | |
13573 | (bridge->subordinate->number <= | |
13574 | tp->pdev->bus->number) && | |
13575 | (bridge->subordinate->subordinate >= | |
13576 | tp->pdev->bus->number)) { | |
13577 | tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; | |
13578 | pci_dev_put(bridge); | |
13579 | break; | |
13580 | } | |
13581 | } | |
13582 | } | |
13583 | ||
4a29cc2e MC |
13584 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
13585 | * DMA addresses > 40-bit. This bridge may have other additional | |
13586 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13587 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13588 | * DMA workaround. | |
13589 | */ | |
a4e2b347 MC |
13590 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
13591 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
13592 | tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; | |
4a29cc2e | 13593 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; |
4cf78e4f | 13594 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 13595 | } else { |
4a29cc2e MC |
13596 | struct pci_dev *bridge = NULL; |
13597 | ||
13598 | do { | |
13599 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13600 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13601 | bridge); | |
13602 | if (bridge && bridge->subordinate && | |
13603 | (bridge->subordinate->number <= | |
13604 | tp->pdev->bus->number) && | |
13605 | (bridge->subordinate->subordinate >= | |
13606 | tp->pdev->bus->number)) { | |
13607 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
13608 | pci_dev_put(bridge); | |
13609 | break; | |
13610 | } | |
13611 | } while (bridge); | |
13612 | } | |
4cf78e4f | 13613 | |
1da177e4 LT |
13614 | /* Initialize misc host control in PCI block. */ |
13615 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
13616 | MISC_HOST_CTRL_CHIPREV); | |
13617 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13618 | tp->misc_host_ctrl); | |
13619 | ||
f6eb9b1f MC |
13620 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
13621 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
d78b59f5 MC |
13622 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13623 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
7544b097 MC |
13624 | tp->pdev_peer = tg3_find_peer(tp); |
13625 | ||
c885e824 | 13626 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
d78b59f5 MC |
13627 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13628 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
0a58d668 MC |
13629 | tp->tg3_flags3 |= TG3_FLG3_5717_PLUS; |
13630 | ||
13631 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
13632 | (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) | |
1407deb1 | 13633 | tp->tg3_flags3 |= TG3_FLG3_57765_PLUS; |
c885e824 | 13634 | |
321d32a0 MC |
13635 | /* Intentionally exclude ASIC_REV_5906 */ |
13636 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 13637 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 13638 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 13639 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 13640 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13641 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
1407deb1 | 13642 | (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) |
321d32a0 MC |
13643 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; |
13644 | ||
13645 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13646 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 13647 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
321d32a0 | 13648 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
a4e2b347 | 13649 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
6708e5cc JL |
13650 | tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; |
13651 | ||
eb07a940 | 13652 | |
1b440c56 JL |
13653 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || |
13654 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
13655 | tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; | |
13656 | ||
027455ad MC |
13657 | /* 5700 B0 chips do not support checksumming correctly due |
13658 | * to hardware bugs. | |
13659 | */ | |
dc668910 MM |
13660 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { |
13661 | u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
7fe876af | 13662 | |
027455ad | 13663 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
7fe876af ED |
13664 | features |= NETIF_F_IPV6_CSUM; |
13665 | tp->dev->features |= features; | |
dc668910 MM |
13666 | tp->dev->hw_features |= features; |
13667 | tp->dev->vlan_features |= features; | |
027455ad MC |
13668 | } |
13669 | ||
507399f1 | 13670 | /* Determine TSO capabilities */ |
2866d956 | 13671 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
4d163b75 | 13672 | ; /* Do nothing. HW bug. */ |
1407deb1 | 13673 | else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) |
e849cdc3 MC |
13674 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; |
13675 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
13676 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
507399f1 MC |
13677 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; |
13678 | else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
13679 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; | |
13680 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && | |
13681 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
13682 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; | |
13683 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13684 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13685 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
13686 | tp->tg3_flags2 |= TG3_FLG2_TSO_BUG; | |
13687 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | |
13688 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13689 | else | |
13690 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13691 | } | |
13692 | ||
13693 | tp->irq_max = 1; | |
13694 | ||
5a6f3074 | 13695 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7544b097 MC |
13696 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; |
13697 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
13698 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13699 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13700 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13701 | tp->pdev_peer == tp->pdev)) | |
13702 | tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; | |
13703 | ||
321d32a0 | 13704 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
b5d3772c | 13705 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
fcfa0a32 | 13706 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; |
52c0fd83 | 13707 | } |
4f125f42 | 13708 | |
1407deb1 | 13709 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
507399f1 MC |
13710 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; |
13711 | tp->irq_max = TG3_IRQ_MAX_VECS; | |
13712 | } | |
f6eb9b1f | 13713 | } |
0e1406dd | 13714 | |
615774fe | 13715 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
a50d0796 | 13716 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
615774fe MC |
13717 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
13718 | tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG; | |
13719 | else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) { | |
13720 | tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG; | |
13721 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | |
0e1406dd | 13722 | } |
f6eb9b1f | 13723 | |
0a58d668 | 13724 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
de9f5230 MC |
13725 | tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP; |
13726 | ||
1407deb1 | 13727 | if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
2866d956 | 13728 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) |
b703df6f MC |
13729 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; |
13730 | ||
f51f3562 | 13731 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
c6cdf436 MC |
13732 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
13733 | (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG)) | |
8f666b07 | 13734 | tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; |
0f893dc6 | 13735 | |
52f4490c MC |
13736 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13737 | &pci_state_reg); | |
13738 | ||
5e7dfd0f MC |
13739 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); |
13740 | if (tp->pcie_cap != 0) { | |
13741 | u16 lnkctl; | |
13742 | ||
1da177e4 | 13743 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
5f5c51e3 | 13744 | |
cf79003d | 13745 | tp->pcie_readrq = 4096; |
d78b59f5 MC |
13746 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13747 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
b4495ed8 | 13748 | tp->pcie_readrq = 2048; |
cf79003d MC |
13749 | |
13750 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
5f5c51e3 | 13751 | |
5e7dfd0f MC |
13752 | pci_read_config_word(tp->pdev, |
13753 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
13754 | &lnkctl); | |
13755 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
13756 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
c7835a77 | 13757 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; |
5e7dfd0f | 13758 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 13759 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
13760 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
13761 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
5e7dfd0f | 13762 | tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; |
614b0590 MC |
13763 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
13764 | tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN; | |
c7835a77 | 13765 | } |
52f4490c | 13766 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
fcb389df | 13767 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
52f4490c MC |
13768 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
13769 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
13770 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
13771 | if (!tp->pcix_cap) { | |
2445e461 MC |
13772 | dev_err(&tp->pdev->dev, |
13773 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
13774 | return -EIO; |
13775 | } | |
13776 | ||
13777 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
13778 | tp->tg3_flags |= TG3_FLAG_PCIX_MODE; | |
13779 | } | |
1da177e4 | 13780 | |
399de50b MC |
13781 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
13782 | * reordering to the mailbox registers done by the host | |
13783 | * controller can cause major troubles. We read back from | |
13784 | * every mailbox register write to force the writes to be | |
13785 | * posted to the chip in order. | |
13786 | */ | |
4143470c | 13787 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
399de50b MC |
13788 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) |
13789 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
13790 | ||
69fc4053 MC |
13791 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
13792 | &tp->pci_cacheline_sz); | |
13793 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13794 | &tp->pci_lat_timer); | |
1da177e4 LT |
13795 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
13796 | tp->pci_lat_timer < 64) { | |
13797 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
13798 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
13799 | tp->pci_lat_timer); | |
1da177e4 LT |
13800 | } |
13801 | ||
52f4490c MC |
13802 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
13803 | /* 5700 BX chips need to have their TX producer index | |
13804 | * mailboxes written twice to workaround a bug. | |
13805 | */ | |
13806 | tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; | |
1da177e4 | 13807 | |
52f4490c | 13808 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
13809 | * |
13810 | * The workaround is to use indirect register accesses | |
13811 | * for all chip writes not to mailbox registers. | |
13812 | */ | |
52f4490c | 13813 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
1da177e4 | 13814 | u32 pm_reg; |
1da177e4 LT |
13815 | |
13816 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13817 | ||
13818 | /* The chip can have it's power management PCI config | |
13819 | * space registers clobbered due to this bug. | |
13820 | * So explicitly force the chip into D0 here. | |
13821 | */ | |
9974a356 MC |
13822 | pci_read_config_dword(tp->pdev, |
13823 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13824 | &pm_reg); |
13825 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
13826 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
13827 | pci_write_config_dword(tp->pdev, |
13828 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13829 | pm_reg); |
13830 | ||
13831 | /* Also, force SERR#/PERR# in PCI command. */ | |
13832 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13833 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
13834 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13835 | } | |
13836 | } | |
13837 | ||
1da177e4 LT |
13838 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
13839 | tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; | |
13840 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
13841 | tp->tg3_flags |= TG3_FLAG_PCI_32BIT; | |
13842 | ||
13843 | /* Chip-specific fixup from Broadcom driver */ | |
13844 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
13845 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
13846 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
13847 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
13848 | } | |
13849 | ||
1ee582d8 | 13850 | /* Default fast path register access methods */ |
20094930 | 13851 | tp->read32 = tg3_read32; |
1ee582d8 | 13852 | tp->write32 = tg3_write32; |
09ee929c | 13853 | tp->read32_mbox = tg3_read32; |
20094930 | 13854 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
13855 | tp->write32_tx_mbox = tg3_write32; |
13856 | tp->write32_rx_mbox = tg3_write32; | |
13857 | ||
13858 | /* Various workaround register access methods */ | |
13859 | if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) | |
13860 | tp->write32 = tg3_write_indirect_reg32; | |
98efd8a6 MC |
13861 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
13862 | ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
13863 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
13864 | /* | |
13865 | * Back to back register writes can cause problems on these | |
13866 | * chips, the workaround is to read back all reg writes | |
13867 | * except those to mailbox regs. | |
13868 | * | |
13869 | * See tg3_write_indirect_reg32(). | |
13870 | */ | |
1ee582d8 | 13871 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
13872 | } |
13873 | ||
1ee582d8 MC |
13874 | if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || |
13875 | (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { | |
13876 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
13877 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
13878 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
13879 | } | |
20094930 | 13880 | |
6892914f MC |
13881 | if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { |
13882 | tp->read32 = tg3_read_indirect_reg32; | |
13883 | tp->write32 = tg3_write_indirect_reg32; | |
13884 | tp->read32_mbox = tg3_read_indirect_mbox; | |
13885 | tp->write32_mbox = tg3_write_indirect_mbox; | |
13886 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
13887 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
13888 | ||
13889 | iounmap(tp->regs); | |
22abe310 | 13890 | tp->regs = NULL; |
6892914f MC |
13891 | |
13892 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13893 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
13894 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13895 | } | |
b5d3772c MC |
13896 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
13897 | tp->read32_mbox = tg3_read32_mbox_5906; | |
13898 | tp->write32_mbox = tg3_write32_mbox_5906; | |
13899 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
13900 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
13901 | } | |
6892914f | 13902 | |
bbadf503 MC |
13903 | if (tp->write32 == tg3_write_indirect_reg32 || |
13904 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13905 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
f49639e6 | 13906 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
bbadf503 MC |
13907 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; |
13908 | ||
7d0c41ef | 13909 | /* Get eeprom hw config before calling tg3_set_power_state(). |
9d26e213 | 13910 | * In particular, the TG3_FLG2_IS_NIC flag must be |
7d0c41ef MC |
13911 | * determined before calling tg3_set_power_state() so that |
13912 | * we know whether or not to switch out of Vaux power. | |
13913 | * When the flag is set, it means that GPIO1 is used for eeprom | |
13914 | * write protect and also implies that it is a LOM where GPIOs | |
13915 | * are not used to switch power. | |
6aa20a22 | 13916 | */ |
7d0c41ef MC |
13917 | tg3_get_eeprom_hw_cfg(tp); |
13918 | ||
0d3031d9 MC |
13919 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
13920 | /* Allow reads and writes to the | |
13921 | * APE register and memory space. | |
13922 | */ | |
13923 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
13924 | PCISTATE_ALLOW_APE_SHMEM_WR | |
13925 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
13926 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13927 | pci_state_reg); | |
13928 | } | |
13929 | ||
9936bcf6 | 13930 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 13931 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 13932 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13933 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
1407deb1 | 13934 | (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) |
d30cdd28 MC |
13935 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; |
13936 | ||
c866b7ea | 13937 | /* Set up tp->grc_local_ctrl before calling tg_power_up(). |
314fba34 MC |
13938 | * GPIO1 driven high will bring 5700's external PHY out of reset. |
13939 | * It is also used as eeprom write protect on LOMs. | |
13940 | */ | |
13941 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
13942 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13943 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | |
13944 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
13945 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
13946 | /* Unused GPIO3 must be driven as output on 5752 because there |
13947 | * are no pull-up resistors on unused GPIO pins. | |
13948 | */ | |
13949 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
13950 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 13951 | |
321d32a0 | 13952 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd MC |
13953 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
13954 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
af36e6b6 MC |
13955 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
13956 | ||
8d519ab2 MC |
13957 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
13958 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
13959 | /* Turn off the debug UART. */ |
13960 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
13961 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
13962 | /* Keep VMain power. */ | |
13963 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
13964 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
13965 | } | |
13966 | ||
1da177e4 | 13967 | /* Force the chip into D0. */ |
c866b7ea | 13968 | err = tg3_power_up(tp); |
1da177e4 | 13969 | if (err) { |
2445e461 | 13970 | dev_err(&tp->pdev->dev, "Transition to D0 failed\n"); |
1da177e4 LT |
13971 | return err; |
13972 | } | |
13973 | ||
1da177e4 LT |
13974 | /* Derive initial jumbo mode from MTU assigned in |
13975 | * ether_setup() via the alloc_etherdev() call | |
13976 | */ | |
0f893dc6 | 13977 | if (tp->dev->mtu > ETH_DATA_LEN && |
a4e2b347 | 13978 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
0f893dc6 | 13979 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
1da177e4 LT |
13980 | |
13981 | /* Determine WakeOnLan speed to use. */ | |
13982 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13983 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
13984 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
13985 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
13986 | tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); | |
13987 | } else { | |
13988 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | |
13989 | } | |
13990 | ||
7f97a4bd | 13991 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 13992 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 13993 | |
1da177e4 LT |
13994 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
13995 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13996 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
13997 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
747e8f8b | 13998 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
13999 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
14000 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
14001 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
14002 | |
14003 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
14004 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 14005 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 14006 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 14007 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 14008 | |
321d32a0 | 14009 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
f07e9af3 | 14010 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 14011 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 14012 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
1407deb1 | 14013 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
c424cb24 | 14014 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 14015 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
14016 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
14017 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
14018 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
14019 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 14020 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 14021 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 14022 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 14023 | } else |
f07e9af3 | 14024 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 14025 | } |
1da177e4 | 14026 | |
b2a5c19c MC |
14027 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14028 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
14029 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
14030 | if (tp->phy_otp == 0) | |
14031 | tp->phy_otp = TG3_OTP_DEFAULT; | |
14032 | } | |
14033 | ||
f51f3562 | 14034 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) |
8ef21428 MC |
14035 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
14036 | else | |
14037 | tp->mi_mode = MAC_MI_MODE_BASE; | |
14038 | ||
1da177e4 | 14039 | tp->coalesce_mode = 0; |
1da177e4 LT |
14040 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
14041 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
14042 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
14043 | ||
4d958473 MC |
14044 | /* Set these bits to enable statistics workaround. */ |
14045 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14046 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
14047 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
14048 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
14049 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
14050 | } | |
14051 | ||
321d32a0 MC |
14052 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
14053 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
57e6983c MC |
14054 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; |
14055 | ||
158d7abd MC |
14056 | err = tg3_mdio_init(tp); |
14057 | if (err) | |
14058 | return err; | |
1da177e4 LT |
14059 | |
14060 | /* Initialize data/descriptor byte/word swapping. */ | |
14061 | val = tr32(GRC_MODE); | |
f2096f94 MC |
14062 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
14063 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
14064 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
14065 | GRC_MODE_B2HRX_ENABLE | | |
14066 | GRC_MODE_HTX2B_ENABLE | | |
14067 | GRC_MODE_HOST_STACKUP); | |
14068 | else | |
14069 | val &= GRC_MODE_HOST_STACKUP; | |
14070 | ||
1da177e4 LT |
14071 | tw32(GRC_MODE, val | tp->grc_mode); |
14072 | ||
14073 | tg3_switch_clocks(tp); | |
14074 | ||
14075 | /* Clear this out for sanity. */ | |
14076 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14077 | ||
14078 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
14079 | &pci_state_reg); | |
14080 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
14081 | (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { | |
14082 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
14083 | ||
14084 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
14085 | chiprevid == CHIPREV_ID_5701_B0 || | |
14086 | chiprevid == CHIPREV_ID_5701_B2 || | |
14087 | chiprevid == CHIPREV_ID_5701_B5) { | |
14088 | void __iomem *sram_base; | |
14089 | ||
14090 | /* Write some dummy words into the SRAM status block | |
14091 | * area, see if it reads back correctly. If the return | |
14092 | * value is bad, force enable the PCIX workaround. | |
14093 | */ | |
14094 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
14095 | ||
14096 | writel(0x00000000, sram_base); | |
14097 | writel(0x00000000, sram_base + 4); | |
14098 | writel(0xffffffff, sram_base + 4); | |
14099 | if (readl(sram_base) != 0x00000000) | |
14100 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
14101 | } | |
14102 | } | |
14103 | ||
14104 | udelay(50); | |
14105 | tg3_nvram_init(tp); | |
14106 | ||
14107 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
14108 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
14109 | ||
1da177e4 LT |
14110 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
14111 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
14112 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
14113 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | |
14114 | ||
fac9b83e DM |
14115 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && |
14116 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | |
14117 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | |
14118 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
14119 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
14120 | HOSTCC_MODE_CLRTICK_TXBD); | |
14121 | ||
14122 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
14123 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14124 | tp->misc_host_ctrl); | |
14125 | } | |
14126 | ||
3bda1258 MC |
14127 | /* Preserve the APE MAC_MODE bits */ |
14128 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
d2394e6b | 14129 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
14130 | else |
14131 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
14132 | ||
1da177e4 LT |
14133 | /* these are limited to 10/100 only */ |
14134 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14135 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14136 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14137 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14138 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
14139 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
14140 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
14141 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14142 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
14143 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
14144 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 14145 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
14146 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
14147 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
14148 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
14149 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
14150 | |
14151 | err = tg3_phy_probe(tp); | |
14152 | if (err) { | |
2445e461 | 14153 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 14154 | /* ... but do not return immediately ... */ |
b02fd9e3 | 14155 | tg3_mdio_fini(tp); |
1da177e4 LT |
14156 | } |
14157 | ||
184b8904 | 14158 | tg3_read_vpd(tp); |
c4e6575c | 14159 | tg3_read_fw_ver(tp); |
1da177e4 | 14160 | |
f07e9af3 MC |
14161 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
14162 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
14163 | } else { |
14164 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 14165 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 14166 | else |
f07e9af3 | 14167 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
14168 | } |
14169 | ||
14170 | /* 5700 {AX,BX} chips have a broken status block link | |
14171 | * change bit implementation, so we must use the | |
14172 | * status register in those cases. | |
14173 | */ | |
14174 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
14175 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
14176 | else | |
14177 | tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; | |
14178 | ||
14179 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
14180 | * have to force the link status polling mechanism based | |
14181 | * upon subsystem IDs. | |
14182 | */ | |
14183 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 14184 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
14185 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
14186 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
14187 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
1da177e4 LT |
14188 | } |
14189 | ||
14190 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 14191 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
14192 | tp->tg3_flags |= TG3_FLAG_POLL_SERDES; |
14193 | else | |
14194 | tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; | |
14195 | ||
bf933c80 | 14196 | tp->rx_offset = NET_IP_ALIGN; |
d2757fc4 | 14197 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 14198 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
d2757fc4 | 14199 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { |
bf933c80 | 14200 | tp->rx_offset = 0; |
d2757fc4 | 14201 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 14202 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
14203 | #endif |
14204 | } | |
1da177e4 | 14205 | |
2c49a44d MC |
14206 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
14207 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
14208 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
14209 | ||
2c49a44d | 14210 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
14211 | |
14212 | /* Increment the rx prod index on the rx std ring by at most | |
14213 | * 8 for these chips to workaround hw errata. | |
14214 | */ | |
14215 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14216 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14217 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14218 | tp->rx_std_max_post = 8; | |
14219 | ||
8ed5d97e MC |
14220 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) |
14221 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
14222 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14223 | ||
1da177e4 LT |
14224 | return err; |
14225 | } | |
14226 | ||
49b6e95f | 14227 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14228 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
14229 | { | |
14230 | struct net_device *dev = tp->dev; | |
14231 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 14232 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 14233 | const unsigned char *addr; |
49b6e95f DM |
14234 | int len; |
14235 | ||
14236 | addr = of_get_property(dp, "local-mac-address", &len); | |
14237 | if (addr && len == 6) { | |
14238 | memcpy(dev->dev_addr, addr, 6); | |
14239 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14240 | return 0; | |
1da177e4 LT |
14241 | } |
14242 | return -ENODEV; | |
14243 | } | |
14244 | ||
14245 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14246 | { | |
14247 | struct net_device *dev = tp->dev; | |
14248 | ||
14249 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 14250 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
14251 | return 0; |
14252 | } | |
14253 | #endif | |
14254 | ||
14255 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14256 | { | |
14257 | struct net_device *dev = tp->dev; | |
14258 | u32 hi, lo, mac_offset; | |
008652b3 | 14259 | int addr_ok = 0; |
1da177e4 | 14260 | |
49b6e95f | 14261 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14262 | if (!tg3_get_macaddr_sparc(tp)) |
14263 | return 0; | |
14264 | #endif | |
14265 | ||
14266 | mac_offset = 0x7c; | |
f49639e6 | 14267 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
a4e2b347 | 14268 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
14269 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
14270 | mac_offset = 0xcc; | |
14271 | if (tg3_nvram_lock(tp)) | |
14272 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14273 | else | |
14274 | tg3_nvram_unlock(tp); | |
0a58d668 | 14275 | } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
a50d0796 | 14276 | if (PCI_FUNC(tp->pdev->devfn) & 1) |
a1b950d5 | 14277 | mac_offset = 0xcc; |
a50d0796 MC |
14278 | if (PCI_FUNC(tp->pdev->devfn) > 1) |
14279 | mac_offset += 0x18c; | |
a1b950d5 | 14280 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 14281 | mac_offset = 0x10; |
1da177e4 LT |
14282 | |
14283 | /* First try to get it from MAC address mailbox. */ | |
14284 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14285 | if ((hi >> 16) == 0x484b) { | |
14286 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14287 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14288 | ||
14289 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14290 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14291 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14292 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14293 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 14294 | |
008652b3 MC |
14295 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
14296 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14297 | } | |
14298 | if (!addr_ok) { | |
14299 | /* Next, try NVRAM. */ | |
df259d8c MC |
14300 | if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && |
14301 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && | |
6d348f2c | 14302 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
14303 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
14304 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
14305 | } |
14306 | /* Finally just fetch it out of the MAC control regs. */ | |
14307 | else { | |
14308 | hi = tr32(MAC_ADDR_0_HIGH); | |
14309 | lo = tr32(MAC_ADDR_0_LOW); | |
14310 | ||
14311 | dev->dev_addr[5] = lo & 0xff; | |
14312 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14313 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14314 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14315 | dev->dev_addr[1] = hi & 0xff; | |
14316 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14317 | } | |
1da177e4 LT |
14318 | } |
14319 | ||
14320 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 14321 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14322 | if (!tg3_get_default_macaddr_sparc(tp)) |
14323 | return 0; | |
14324 | #endif | |
14325 | return -EINVAL; | |
14326 | } | |
2ff43697 | 14327 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
14328 | return 0; |
14329 | } | |
14330 | ||
59e6b434 DM |
14331 | #define BOUNDARY_SINGLE_CACHELINE 1 |
14332 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14333 | ||
14334 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14335 | { | |
14336 | int cacheline_size; | |
14337 | u8 byte; | |
14338 | int goal; | |
14339 | ||
14340 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14341 | if (byte == 0) | |
14342 | cacheline_size = 1024; | |
14343 | else | |
14344 | cacheline_size = (int) byte * 4; | |
14345 | ||
14346 | /* On 5703 and later chips, the boundary bits have no | |
14347 | * effect. | |
14348 | */ | |
14349 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14350 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
14351 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
14352 | goto out; | |
14353 | ||
14354 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14355 | goal = BOUNDARY_MULTI_CACHELINE; | |
14356 | #else | |
14357 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14358 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14359 | #else | |
14360 | goal = 0; | |
14361 | #endif | |
14362 | #endif | |
14363 | ||
1407deb1 | 14364 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
cbf9ca6c MC |
14365 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
14366 | goto out; | |
14367 | } | |
14368 | ||
59e6b434 DM |
14369 | if (!goal) |
14370 | goto out; | |
14371 | ||
14372 | /* PCI controllers on most RISC systems tend to disconnect | |
14373 | * when a device tries to burst across a cache-line boundary. | |
14374 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14375 | * | |
14376 | * Unfortunately, for PCI-E there are only limited | |
14377 | * write-side controls for this, and thus for reads | |
14378 | * we will still get the disconnects. We'll also waste | |
14379 | * these PCI cycles for both read and write for chips | |
14380 | * other than 5700 and 5701 which do not implement the | |
14381 | * boundary bits. | |
14382 | */ | |
14383 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
14384 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
14385 | switch (cacheline_size) { | |
14386 | case 16: | |
14387 | case 32: | |
14388 | case 64: | |
14389 | case 128: | |
14390 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14391 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14392 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14393 | } else { | |
14394 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14395 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14396 | } | |
14397 | break; | |
14398 | ||
14399 | case 256: | |
14400 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14401 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14402 | break; | |
14403 | ||
14404 | default: | |
14405 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14406 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14407 | break; | |
855e1111 | 14408 | } |
59e6b434 DM |
14409 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
14410 | switch (cacheline_size) { | |
14411 | case 16: | |
14412 | case 32: | |
14413 | case 64: | |
14414 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14415 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14416 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14417 | break; | |
14418 | } | |
14419 | /* fallthrough */ | |
14420 | case 128: | |
14421 | default: | |
14422 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14423 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14424 | break; | |
855e1111 | 14425 | } |
59e6b434 DM |
14426 | } else { |
14427 | switch (cacheline_size) { | |
14428 | case 16: | |
14429 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14430 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14431 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14432 | break; | |
14433 | } | |
14434 | /* fallthrough */ | |
14435 | case 32: | |
14436 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14437 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14438 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14439 | break; | |
14440 | } | |
14441 | /* fallthrough */ | |
14442 | case 64: | |
14443 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14444 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14445 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14446 | break; | |
14447 | } | |
14448 | /* fallthrough */ | |
14449 | case 128: | |
14450 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14451 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14452 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14453 | break; | |
14454 | } | |
14455 | /* fallthrough */ | |
14456 | case 256: | |
14457 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14458 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14459 | break; | |
14460 | case 512: | |
14461 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14462 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14463 | break; | |
14464 | case 1024: | |
14465 | default: | |
14466 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14467 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14468 | break; | |
855e1111 | 14469 | } |
59e6b434 DM |
14470 | } |
14471 | ||
14472 | out: | |
14473 | return val; | |
14474 | } | |
14475 | ||
1da177e4 LT |
14476 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
14477 | { | |
14478 | struct tg3_internal_buffer_desc test_desc; | |
14479 | u32 sram_dma_descs; | |
14480 | int i, ret; | |
14481 | ||
14482 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14483 | ||
14484 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14485 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14486 | tw32(RDMAC_STATUS, 0); | |
14487 | tw32(WDMAC_STATUS, 0); | |
14488 | ||
14489 | tw32(BUFMGR_MODE, 0); | |
14490 | tw32(FTQ_RESET, 0); | |
14491 | ||
14492 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14493 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14494 | test_desc.nic_mbuf = 0x00002100; | |
14495 | test_desc.len = size; | |
14496 | ||
14497 | /* | |
14498 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14499 | * the *second* time the tg3 driver was getting loaded after an | |
14500 | * initial scan. | |
14501 | * | |
14502 | * Broadcom tells me: | |
14503 | * ...the DMA engine is connected to the GRC block and a DMA | |
14504 | * reset may affect the GRC block in some unpredictable way... | |
14505 | * The behavior of resets to individual blocks has not been tested. | |
14506 | * | |
14507 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14508 | */ | |
14509 | if (to_device) { | |
14510 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14511 | ||
14512 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14513 | udelay(40); | |
14514 | } else { | |
14515 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14516 | ||
14517 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14518 | udelay(40); | |
14519 | } | |
14520 | test_desc.flags = 0x00000005; | |
14521 | ||
14522 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14523 | u32 val; | |
14524 | ||
14525 | val = *(((u32 *)&test_desc) + i); | |
14526 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14527 | sram_dma_descs + (i * sizeof(u32))); | |
14528 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14529 | } | |
14530 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14531 | ||
859a5887 | 14532 | if (to_device) |
1da177e4 | 14533 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 14534 | else |
1da177e4 | 14535 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
14536 | |
14537 | ret = -ENODEV; | |
14538 | for (i = 0; i < 40; i++) { | |
14539 | u32 val; | |
14540 | ||
14541 | if (to_device) | |
14542 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14543 | else | |
14544 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14545 | if ((val & 0xffff) == sram_dma_descs) { | |
14546 | ret = 0; | |
14547 | break; | |
14548 | } | |
14549 | ||
14550 | udelay(100); | |
14551 | } | |
14552 | ||
14553 | return ret; | |
14554 | } | |
14555 | ||
ded7340d | 14556 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 14557 | |
4143470c | 14558 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
14559 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
14560 | { }, | |
14561 | }; | |
14562 | ||
1da177e4 LT |
14563 | static int __devinit tg3_test_dma(struct tg3 *tp) |
14564 | { | |
14565 | dma_addr_t buf_dma; | |
59e6b434 | 14566 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 14567 | int ret = 0; |
1da177e4 | 14568 | |
4bae65c8 MC |
14569 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
14570 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
14571 | if (!buf) { |
14572 | ret = -ENOMEM; | |
14573 | goto out_nofree; | |
14574 | } | |
14575 | ||
14576 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14577 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14578 | ||
59e6b434 | 14579 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 14580 | |
1407deb1 | 14581 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) |
cbf9ca6c MC |
14582 | goto out; |
14583 | ||
1da177e4 LT |
14584 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
14585 | /* DMA read watermark not used on PCIE */ | |
14586 | tp->dma_rwctrl |= 0x00180000; | |
14587 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
85e94ced MC |
14588 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
14589 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
14590 | tp->dma_rwctrl |= 0x003f0000; |
14591 | else | |
14592 | tp->dma_rwctrl |= 0x003f000f; | |
14593 | } else { | |
14594 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14595 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14596 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 14597 | u32 read_water = 0x7; |
1da177e4 | 14598 | |
4a29cc2e MC |
14599 | /* If the 5704 is behind the EPB bridge, we can |
14600 | * do the less restrictive ONE_DMA workaround for | |
14601 | * better performance. | |
14602 | */ | |
14603 | if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && | |
14604 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14605 | tp->dma_rwctrl |= 0x8000; | |
14606 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
14607 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
14608 | ||
49afdeb6 MC |
14609 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
14610 | read_water = 4; | |
59e6b434 | 14611 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
14612 | tp->dma_rwctrl |= |
14613 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14614 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14615 | (1 << 23); | |
4cf78e4f MC |
14616 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
14617 | /* 5780 always in PCIX mode */ | |
14618 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
14619 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
14620 | /* 5714 always in PCIX mode */ | |
14621 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
14622 | } else { |
14623 | tp->dma_rwctrl |= 0x001b000f; | |
14624 | } | |
14625 | } | |
14626 | ||
14627 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14628 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14629 | tp->dma_rwctrl &= 0xfffffff0; | |
14630 | ||
14631 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14632 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14633 | /* Remove this if it causes problems for some boards. */ | |
14634 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14635 | ||
14636 | /* On 5700/5701 chips, we need to set this bit. | |
14637 | * Otherwise the chip will issue cacheline transactions | |
14638 | * to streamable DMA memory with not all the byte | |
14639 | * enables turned on. This is an error on several | |
14640 | * RISC PCI controllers, in particular sparc64. | |
14641 | * | |
14642 | * On 5703/5704 chips, this bit has been reassigned | |
14643 | * a different meaning. In particular, it is used | |
14644 | * on those chips to enable a PCI-X workaround. | |
14645 | */ | |
14646 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14647 | } | |
14648 | ||
14649 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14650 | ||
14651 | #if 0 | |
14652 | /* Unneeded, already done by tg3_get_invariants. */ | |
14653 | tg3_switch_clocks(tp); | |
14654 | #endif | |
14655 | ||
1da177e4 LT |
14656 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14657 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14658 | goto out; | |
14659 | ||
59e6b434 DM |
14660 | /* It is best to perform DMA test with maximum write burst size |
14661 | * to expose the 5700/5701 write DMA bug. | |
14662 | */ | |
14663 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14664 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14665 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14666 | ||
1da177e4 LT |
14667 | while (1) { |
14668 | u32 *p = buf, i; | |
14669 | ||
14670 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14671 | p[i] = i; | |
14672 | ||
14673 | /* Send the buffer to the chip. */ | |
14674 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
14675 | if (ret) { | |
2445e461 MC |
14676 | dev_err(&tp->pdev->dev, |
14677 | "%s: Buffer write failed. err = %d\n", | |
14678 | __func__, ret); | |
1da177e4 LT |
14679 | break; |
14680 | } | |
14681 | ||
14682 | #if 0 | |
14683 | /* validate data reached card RAM correctly. */ | |
14684 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14685 | u32 val; | |
14686 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
14687 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
14688 | dev_err(&tp->pdev->dev, |
14689 | "%s: Buffer corrupted on device! " | |
14690 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
14691 | /* ret = -ENODEV here? */ |
14692 | } | |
14693 | p[i] = 0; | |
14694 | } | |
14695 | #endif | |
14696 | /* Now read it back. */ | |
14697 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
14698 | if (ret) { | |
5129c3a3 MC |
14699 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
14700 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
14701 | break; |
14702 | } | |
14703 | ||
14704 | /* Verify it. */ | |
14705 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14706 | if (p[i] == i) | |
14707 | continue; | |
14708 | ||
59e6b434 DM |
14709 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14710 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14711 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
14712 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
14713 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14714 | break; | |
14715 | } else { | |
2445e461 MC |
14716 | dev_err(&tp->pdev->dev, |
14717 | "%s: Buffer corrupted on read back! " | |
14718 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
14719 | ret = -ENODEV; |
14720 | goto out; | |
14721 | } | |
14722 | } | |
14723 | ||
14724 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14725 | /* Success. */ | |
14726 | ret = 0; | |
14727 | break; | |
14728 | } | |
14729 | } | |
59e6b434 DM |
14730 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14731 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
6d1cfbab | 14732 | |
59e6b434 | 14733 | /* DMA test passed without adjusting DMA boundary, |
6d1cfbab MC |
14734 | * now look for chipsets that are known to expose the |
14735 | * DMA bug without failing the test. | |
59e6b434 | 14736 | */ |
4143470c | 14737 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
14738 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
14739 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 14740 | } else { |
6d1cfbab MC |
14741 | /* Safe to use the calculated DMA boundary. */ |
14742 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 14743 | } |
6d1cfbab | 14744 | |
59e6b434 DM |
14745 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
14746 | } | |
1da177e4 LT |
14747 | |
14748 | out: | |
4bae65c8 | 14749 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
14750 | out_nofree: |
14751 | return ret; | |
14752 | } | |
14753 | ||
1da177e4 LT |
14754 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
14755 | { | |
1407deb1 | 14756 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
666bc831 MC |
14757 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14758 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14759 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14760 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14761 | tp->bufmgr_config.mbuf_high_water = | |
14762 | DEFAULT_MB_HIGH_WATER_57765; | |
14763 | ||
14764 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14765 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14766 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14767 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14768 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14769 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
14770 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
fdfec172 MC |
14771 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14772 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14773 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14774 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14775 | tp->bufmgr_config.mbuf_high_water = | |
14776 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
14777 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14778 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14779 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14780 | tp->bufmgr_config.mbuf_high_water = | |
14781 | DEFAULT_MB_HIGH_WATER_5906; | |
14782 | } | |
fdfec172 MC |
14783 | |
14784 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14785 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
14786 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14787 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
14788 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14789 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
14790 | } else { | |
14791 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14792 | DEFAULT_MB_RDMA_LOW_WATER; | |
14793 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14794 | DEFAULT_MB_MACRX_LOW_WATER; | |
14795 | tp->bufmgr_config.mbuf_high_water = | |
14796 | DEFAULT_MB_HIGH_WATER; | |
14797 | ||
14798 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14799 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
14800 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14801 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
14802 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14803 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
14804 | } | |
1da177e4 LT |
14805 | |
14806 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
14807 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
14808 | } | |
14809 | ||
14810 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
14811 | { | |
79eb6904 MC |
14812 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
14813 | case TG3_PHY_ID_BCM5400: return "5400"; | |
14814 | case TG3_PHY_ID_BCM5401: return "5401"; | |
14815 | case TG3_PHY_ID_BCM5411: return "5411"; | |
14816 | case TG3_PHY_ID_BCM5701: return "5701"; | |
14817 | case TG3_PHY_ID_BCM5703: return "5703"; | |
14818 | case TG3_PHY_ID_BCM5704: return "5704"; | |
14819 | case TG3_PHY_ID_BCM5705: return "5705"; | |
14820 | case TG3_PHY_ID_BCM5750: return "5750"; | |
14821 | case TG3_PHY_ID_BCM5752: return "5752"; | |
14822 | case TG3_PHY_ID_BCM5714: return "5714"; | |
14823 | case TG3_PHY_ID_BCM5780: return "5780"; | |
14824 | case TG3_PHY_ID_BCM5755: return "5755"; | |
14825 | case TG3_PHY_ID_BCM5787: return "5787"; | |
14826 | case TG3_PHY_ID_BCM5784: return "5784"; | |
14827 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
14828 | case TG3_PHY_ID_BCM5906: return "5906"; | |
14829 | case TG3_PHY_ID_BCM5761: return "5761"; | |
14830 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
14831 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
14832 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 14833 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 14834 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 14835 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
14836 | case 0: return "serdes"; |
14837 | default: return "unknown"; | |
855e1111 | 14838 | } |
1da177e4 LT |
14839 | } |
14840 | ||
f9804ddb MC |
14841 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
14842 | { | |
14843 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
14844 | strcpy(str, "PCI Express"); | |
14845 | return str; | |
14846 | } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
14847 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
14848 | ||
14849 | strcpy(str, "PCIX:"); | |
14850 | ||
14851 | if ((clock_ctrl == 7) || | |
14852 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
14853 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
14854 | strcat(str, "133MHz"); | |
14855 | else if (clock_ctrl == 0) | |
14856 | strcat(str, "33MHz"); | |
14857 | else if (clock_ctrl == 2) | |
14858 | strcat(str, "50MHz"); | |
14859 | else if (clock_ctrl == 4) | |
14860 | strcat(str, "66MHz"); | |
14861 | else if (clock_ctrl == 6) | |
14862 | strcat(str, "100MHz"); | |
f9804ddb MC |
14863 | } else { |
14864 | strcpy(str, "PCI:"); | |
14865 | if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) | |
14866 | strcat(str, "66MHz"); | |
14867 | else | |
14868 | strcat(str, "33MHz"); | |
14869 | } | |
14870 | if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) | |
14871 | strcat(str, ":32-bit"); | |
14872 | else | |
14873 | strcat(str, ":64-bit"); | |
14874 | return str; | |
14875 | } | |
14876 | ||
8c2dc7e1 | 14877 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
14878 | { |
14879 | struct pci_dev *peer; | |
14880 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14881 | ||
14882 | for (func = 0; func < 8; func++) { | |
14883 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14884 | if (peer && peer != tp->pdev) | |
14885 | break; | |
14886 | pci_dev_put(peer); | |
14887 | } | |
16fe9d74 MC |
14888 | /* 5704 can be configured in single-port mode, set peer to |
14889 | * tp->pdev in that case. | |
14890 | */ | |
14891 | if (!peer) { | |
14892 | peer = tp->pdev; | |
14893 | return peer; | |
14894 | } | |
1da177e4 LT |
14895 | |
14896 | /* | |
14897 | * We don't need to keep the refcount elevated; there's no way | |
14898 | * to remove one half of this device without removing the other | |
14899 | */ | |
14900 | pci_dev_put(peer); | |
14901 | ||
14902 | return peer; | |
14903 | } | |
14904 | ||
15f9850d DM |
14905 | static void __devinit tg3_init_coal(struct tg3 *tp) |
14906 | { | |
14907 | struct ethtool_coalesce *ec = &tp->coal; | |
14908 | ||
14909 | memset(ec, 0, sizeof(*ec)); | |
14910 | ec->cmd = ETHTOOL_GCOALESCE; | |
14911 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
14912 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
14913 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
14914 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
14915 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
14916 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
14917 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
14918 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
14919 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
14920 | ||
14921 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
14922 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
14923 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
14924 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
14925 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
14926 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
14927 | } | |
d244c892 MC |
14928 | |
14929 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
14930 | ec->rx_coalesce_usecs_irq = 0; | |
14931 | ec->tx_coalesce_usecs_irq = 0; | |
14932 | ec->stats_block_coalesce_usecs = 0; | |
14933 | } | |
15f9850d DM |
14934 | } |
14935 | ||
7c7d64b8 SH |
14936 | static const struct net_device_ops tg3_netdev_ops = { |
14937 | .ndo_open = tg3_open, | |
14938 | .ndo_stop = tg3_close, | |
00829823 | 14939 | .ndo_start_xmit = tg3_start_xmit, |
511d2224 | 14940 | .ndo_get_stats64 = tg3_get_stats64, |
00829823 SH |
14941 | .ndo_validate_addr = eth_validate_addr, |
14942 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14943 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14944 | .ndo_do_ioctl = tg3_ioctl, | |
14945 | .ndo_tx_timeout = tg3_tx_timeout, | |
14946 | .ndo_change_mtu = tg3_change_mtu, | |
dc668910 | 14947 | .ndo_fix_features = tg3_fix_features, |
00829823 SH |
14948 | #ifdef CONFIG_NET_POLL_CONTROLLER |
14949 | .ndo_poll_controller = tg3_poll_controller, | |
14950 | #endif | |
14951 | }; | |
14952 | ||
14953 | static const struct net_device_ops tg3_netdev_ops_dma_bug = { | |
14954 | .ndo_open = tg3_open, | |
14955 | .ndo_stop = tg3_close, | |
14956 | .ndo_start_xmit = tg3_start_xmit_dma_bug, | |
511d2224 | 14957 | .ndo_get_stats64 = tg3_get_stats64, |
7c7d64b8 SH |
14958 | .ndo_validate_addr = eth_validate_addr, |
14959 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14960 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14961 | .ndo_do_ioctl = tg3_ioctl, | |
14962 | .ndo_tx_timeout = tg3_tx_timeout, | |
14963 | .ndo_change_mtu = tg3_change_mtu, | |
7c7d64b8 SH |
14964 | #ifdef CONFIG_NET_POLL_CONTROLLER |
14965 | .ndo_poll_controller = tg3_poll_controller, | |
14966 | #endif | |
14967 | }; | |
14968 | ||
1da177e4 LT |
14969 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
14970 | const struct pci_device_id *ent) | |
14971 | { | |
1da177e4 LT |
14972 | struct net_device *dev; |
14973 | struct tg3 *tp; | |
646c9edd MC |
14974 | int i, err, pm_cap; |
14975 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 14976 | char str[40]; |
72f2afb8 | 14977 | u64 dma_mask, persist_dma_mask; |
dc668910 | 14978 | u32 hw_features = 0; |
1da177e4 | 14979 | |
05dbe005 | 14980 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
14981 | |
14982 | err = pci_enable_device(pdev); | |
14983 | if (err) { | |
2445e461 | 14984 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
14985 | return err; |
14986 | } | |
14987 | ||
1da177e4 LT |
14988 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
14989 | if (err) { | |
2445e461 | 14990 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
14991 | goto err_out_disable_pdev; |
14992 | } | |
14993 | ||
14994 | pci_set_master(pdev); | |
14995 | ||
14996 | /* Find power-management capability. */ | |
14997 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
14998 | if (pm_cap == 0) { | |
2445e461 MC |
14999 | dev_err(&pdev->dev, |
15000 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
15001 | err = -EIO; |
15002 | goto err_out_free_res; | |
15003 | } | |
15004 | ||
fe5f5787 | 15005 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 15006 | if (!dev) { |
2445e461 | 15007 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 LT |
15008 | err = -ENOMEM; |
15009 | goto err_out_free_res; | |
15010 | } | |
15011 | ||
1da177e4 LT |
15012 | SET_NETDEV_DEV(dev, &pdev->dev); |
15013 | ||
1da177e4 | 15014 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
1da177e4 LT |
15015 | |
15016 | tp = netdev_priv(dev); | |
15017 | tp->pdev = pdev; | |
15018 | tp->dev = dev; | |
15019 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
15020 | tp->rx_mode = TG3_DEF_RX_MODE; |
15021 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 15022 | |
1da177e4 LT |
15023 | if (tg3_debug > 0) |
15024 | tp->msg_enable = tg3_debug; | |
15025 | else | |
15026 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
15027 | ||
15028 | /* The word/byte swap controls here control register access byte | |
15029 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
15030 | * setting below. | |
15031 | */ | |
15032 | tp->misc_host_ctrl = | |
15033 | MISC_HOST_CTRL_MASK_PCI_INT | | |
15034 | MISC_HOST_CTRL_WORD_SWAP | | |
15035 | MISC_HOST_CTRL_INDIR_ACCESS | | |
15036 | MISC_HOST_CTRL_PCISTATE_RW; | |
15037 | ||
15038 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
15039 | * on descriptor entries, anything which isn't packet data. | |
15040 | * | |
15041 | * The StrongARM chips on the board (one for tx, one for rx) | |
15042 | * are running in big-endian mode. | |
15043 | */ | |
15044 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
15045 | GRC_MODE_WSWAP_NONFRM_DATA); | |
15046 | #ifdef __BIG_ENDIAN | |
15047 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
15048 | #endif | |
15049 | spin_lock_init(&tp->lock); | |
1da177e4 | 15050 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 15051 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 15052 | |
d5fe488a | 15053 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 15054 | if (!tp->regs) { |
ab96b241 | 15055 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
15056 | err = -ENOMEM; |
15057 | goto err_out_free_dev; | |
15058 | } | |
15059 | ||
1da177e4 LT |
15060 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
15061 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 15062 | |
1da177e4 | 15063 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 15064 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
1da177e4 | 15065 | dev->irq = pdev->irq; |
1da177e4 LT |
15066 | |
15067 | err = tg3_get_invariants(tp); | |
15068 | if (err) { | |
ab96b241 MC |
15069 | dev_err(&pdev->dev, |
15070 | "Problem fetching invariants of chip, aborting\n"); | |
1da177e4 LT |
15071 | goto err_out_iounmap; |
15072 | } | |
15073 | ||
615774fe | 15074 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && |
0a58d668 | 15075 | !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
00829823 SH |
15076 | dev->netdev_ops = &tg3_netdev_ops; |
15077 | else | |
15078 | dev->netdev_ops = &tg3_netdev_ops_dma_bug; | |
15079 | ||
15080 | ||
4a29cc2e MC |
15081 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
15082 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
15083 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
15084 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
15085 | * do DMA address check in tg3_start_xmit(). | |
15086 | */ | |
4a29cc2e | 15087 | if (tp->tg3_flags2 & TG3_FLG2_IS_5788) |
284901a9 | 15088 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
4a29cc2e | 15089 | else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { |
50cf156a | 15090 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 15091 | #ifdef CONFIG_HIGHMEM |
6a35528a | 15092 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 15093 | #endif |
4a29cc2e | 15094 | } else |
6a35528a | 15095 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
15096 | |
15097 | /* Configure DMA attributes. */ | |
284901a9 | 15098 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
15099 | err = pci_set_dma_mask(pdev, dma_mask); |
15100 | if (!err) { | |
15101 | dev->features |= NETIF_F_HIGHDMA; | |
15102 | err = pci_set_consistent_dma_mask(pdev, | |
15103 | persist_dma_mask); | |
15104 | if (err < 0) { | |
ab96b241 MC |
15105 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
15106 | "DMA for consistent allocations\n"); | |
72f2afb8 MC |
15107 | goto err_out_iounmap; |
15108 | } | |
15109 | } | |
15110 | } | |
284901a9 YH |
15111 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
15112 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 15113 | if (err) { |
ab96b241 MC |
15114 | dev_err(&pdev->dev, |
15115 | "No usable DMA configuration, aborting\n"); | |
72f2afb8 MC |
15116 | goto err_out_iounmap; |
15117 | } | |
15118 | } | |
15119 | ||
fdfec172 | 15120 | tg3_init_bufmgr_config(tp); |
1da177e4 | 15121 | |
507399f1 MC |
15122 | /* Selectively allow TSO based on operating conditions */ |
15123 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || | |
15124 | (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) | |
1da177e4 | 15125 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
507399f1 MC |
15126 | else { |
15127 | tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG); | |
15128 | tp->fw_needed = NULL; | |
1da177e4 | 15129 | } |
507399f1 MC |
15130 | |
15131 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
15132 | tp->fw_needed = FIRMWARE_TG3; | |
1da177e4 | 15133 | |
4e3a7aaa MC |
15134 | /* TSO is on by default on chips that support hardware TSO. |
15135 | * Firmware TSO on older chips gives lower performance, so it | |
15136 | * is off by default, but can be enabled using ethtool. | |
15137 | */ | |
e849cdc3 | 15138 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) && |
dc668910 MM |
15139 | (dev->features & NETIF_F_IP_CSUM)) |
15140 | hw_features |= NETIF_F_TSO; | |
e849cdc3 MC |
15141 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || |
15142 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) { | |
dc668910 MM |
15143 | if (dev->features & NETIF_F_IPV6_CSUM) |
15144 | hw_features |= NETIF_F_TSO6; | |
e849cdc3 MC |
15145 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
15146 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
15147 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15148 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 15149 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 MM |
15150 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
15151 | hw_features |= NETIF_F_TSO_ECN; | |
b0026624 | 15152 | } |
1da177e4 | 15153 | |
dc668910 MM |
15154 | dev->hw_features |= hw_features; |
15155 | dev->features |= hw_features; | |
15156 | dev->vlan_features |= hw_features; | |
15157 | ||
1da177e4 LT |
15158 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
15159 | !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
15160 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
15161 | tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; | |
15162 | tp->rx_pending = 63; | |
15163 | } | |
15164 | ||
1da177e4 LT |
15165 | err = tg3_get_device_address(tp); |
15166 | if (err) { | |
ab96b241 MC |
15167 | dev_err(&pdev->dev, |
15168 | "Could not obtain valid ethernet address, aborting\n"); | |
026a6c21 | 15169 | goto err_out_iounmap; |
1da177e4 LT |
15170 | } |
15171 | ||
c88864df | 15172 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
63532394 | 15173 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); |
79ea13ce | 15174 | if (!tp->aperegs) { |
ab96b241 MC |
15175 | dev_err(&pdev->dev, |
15176 | "Cannot map APE registers, aborting\n"); | |
c88864df | 15177 | err = -ENOMEM; |
026a6c21 | 15178 | goto err_out_iounmap; |
c88864df MC |
15179 | } |
15180 | ||
15181 | tg3_ape_lock_init(tp); | |
7fd76445 MC |
15182 | |
15183 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
15184 | tg3_read_dash_ver(tp); | |
c88864df MC |
15185 | } |
15186 | ||
1da177e4 LT |
15187 | /* |
15188 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15189 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15190 | * pending DMA on the PCI bus at that point. | |
15191 | */ | |
15192 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15193 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 15194 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 15195 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
15196 | } |
15197 | ||
15198 | err = tg3_test_dma(tp); | |
15199 | if (err) { | |
ab96b241 | 15200 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 15201 | goto err_out_apeunmap; |
1da177e4 LT |
15202 | } |
15203 | ||
78f90dcf MC |
15204 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
15205 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15206 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 15207 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
15208 | struct tg3_napi *tnapi = &tp->napi[i]; |
15209 | ||
15210 | tnapi->tp = tp; | |
15211 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15212 | ||
15213 | tnapi->int_mbox = intmbx; | |
15214 | if (i < 4) | |
15215 | intmbx += 0x8; | |
15216 | else | |
15217 | intmbx += 0x4; | |
15218 | ||
15219 | tnapi->consmbox = rcvmbx; | |
15220 | tnapi->prodmbox = sndmbx; | |
15221 | ||
66cfd1bd | 15222 | if (i) |
78f90dcf | 15223 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 15224 | else |
78f90dcf | 15225 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf MC |
15226 | |
15227 | if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)) | |
15228 | break; | |
15229 | ||
15230 | /* | |
15231 | * If we support MSIX, we'll be using RSS. If we're using | |
15232 | * RSS, the first vector only handles link interrupts and the | |
15233 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15234 | * mailbox values for the next iteration. The values we setup | |
15235 | * above are still useful for the single vectored mode. | |
15236 | */ | |
15237 | if (!i) | |
15238 | continue; | |
15239 | ||
15240 | rcvmbx += 0x8; | |
15241 | ||
15242 | if (sndmbx & 0x4) | |
15243 | sndmbx -= 0x4; | |
15244 | else | |
15245 | sndmbx += 0xc; | |
15246 | } | |
15247 | ||
15f9850d DM |
15248 | tg3_init_coal(tp); |
15249 | ||
c49a1561 MC |
15250 | pci_set_drvdata(pdev, dev); |
15251 | ||
1da177e4 LT |
15252 | err = register_netdev(dev); |
15253 | if (err) { | |
ab96b241 | 15254 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 15255 | goto err_out_apeunmap; |
1da177e4 LT |
15256 | } |
15257 | ||
05dbe005 JP |
15258 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
15259 | tp->board_part_number, | |
15260 | tp->pci_chip_rev_id, | |
15261 | tg3_bus_string(tp, str), | |
15262 | dev->dev_addr); | |
1da177e4 | 15263 | |
f07e9af3 | 15264 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
15265 | struct phy_device *phydev; |
15266 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
15267 | netdev_info(dev, |
15268 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 15269 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
15270 | } else { |
15271 | char *ethtype; | |
15272 | ||
15273 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15274 | ethtype = "10/100Base-TX"; | |
15275 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15276 | ethtype = "1000Base-SX"; | |
15277 | else | |
15278 | ethtype = "10/100/1000Base-T"; | |
15279 | ||
5129c3a3 | 15280 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
f07e9af3 MC |
15281 | "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype, |
15282 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0); | |
15283 | } | |
05dbe005 JP |
15284 | |
15285 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 15286 | (dev->features & NETIF_F_RXCSUM) != 0, |
05dbe005 | 15287 | (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, |
f07e9af3 | 15288 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
05dbe005 JP |
15289 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, |
15290 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); | |
15291 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", | |
15292 | tp->dma_rwctrl, | |
15293 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15294 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 LT |
15295 | |
15296 | return 0; | |
15297 | ||
0d3031d9 MC |
15298 | err_out_apeunmap: |
15299 | if (tp->aperegs) { | |
15300 | iounmap(tp->aperegs); | |
15301 | tp->aperegs = NULL; | |
15302 | } | |
15303 | ||
1da177e4 | 15304 | err_out_iounmap: |
6892914f MC |
15305 | if (tp->regs) { |
15306 | iounmap(tp->regs); | |
22abe310 | 15307 | tp->regs = NULL; |
6892914f | 15308 | } |
1da177e4 LT |
15309 | |
15310 | err_out_free_dev: | |
15311 | free_netdev(dev); | |
15312 | ||
15313 | err_out_free_res: | |
15314 | pci_release_regions(pdev); | |
15315 | ||
15316 | err_out_disable_pdev: | |
15317 | pci_disable_device(pdev); | |
15318 | pci_set_drvdata(pdev, NULL); | |
15319 | return err; | |
15320 | } | |
15321 | ||
15322 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15323 | { | |
15324 | struct net_device *dev = pci_get_drvdata(pdev); | |
15325 | ||
15326 | if (dev) { | |
15327 | struct tg3 *tp = netdev_priv(dev); | |
15328 | ||
077f849d JSR |
15329 | if (tp->fw) |
15330 | release_firmware(tp->fw); | |
15331 | ||
23f333a2 | 15332 | cancel_work_sync(&tp->reset_task); |
158d7abd | 15333 | |
b02fd9e3 MC |
15334 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
15335 | tg3_phy_fini(tp); | |
158d7abd | 15336 | tg3_mdio_fini(tp); |
b02fd9e3 | 15337 | } |
158d7abd | 15338 | |
1da177e4 | 15339 | unregister_netdev(dev); |
0d3031d9 MC |
15340 | if (tp->aperegs) { |
15341 | iounmap(tp->aperegs); | |
15342 | tp->aperegs = NULL; | |
15343 | } | |
6892914f MC |
15344 | if (tp->regs) { |
15345 | iounmap(tp->regs); | |
22abe310 | 15346 | tp->regs = NULL; |
6892914f | 15347 | } |
1da177e4 LT |
15348 | free_netdev(dev); |
15349 | pci_release_regions(pdev); | |
15350 | pci_disable_device(pdev); | |
15351 | pci_set_drvdata(pdev, NULL); | |
15352 | } | |
15353 | } | |
15354 | ||
aa6027ca | 15355 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 15356 | static int tg3_suspend(struct device *device) |
1da177e4 | 15357 | { |
c866b7ea | 15358 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15359 | struct net_device *dev = pci_get_drvdata(pdev); |
15360 | struct tg3 *tp = netdev_priv(dev); | |
15361 | int err; | |
15362 | ||
15363 | if (!netif_running(dev)) | |
15364 | return 0; | |
15365 | ||
23f333a2 | 15366 | flush_work_sync(&tp->reset_task); |
b02fd9e3 | 15367 | tg3_phy_stop(tp); |
1da177e4 LT |
15368 | tg3_netif_stop(tp); |
15369 | ||
15370 | del_timer_sync(&tp->timer); | |
15371 | ||
f47c11ee | 15372 | tg3_full_lock(tp, 1); |
1da177e4 | 15373 | tg3_disable_ints(tp); |
f47c11ee | 15374 | tg3_full_unlock(tp); |
1da177e4 LT |
15375 | |
15376 | netif_device_detach(dev); | |
15377 | ||
f47c11ee | 15378 | tg3_full_lock(tp, 0); |
944d980e | 15379 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
6a9eba15 | 15380 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
f47c11ee | 15381 | tg3_full_unlock(tp); |
1da177e4 | 15382 | |
c866b7ea | 15383 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15384 | if (err) { |
b02fd9e3 MC |
15385 | int err2; |
15386 | ||
f47c11ee | 15387 | tg3_full_lock(tp, 0); |
1da177e4 | 15388 | |
6a9eba15 | 15389 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b02fd9e3 MC |
15390 | err2 = tg3_restart_hw(tp, 1); |
15391 | if (err2) | |
b9ec6c1b | 15392 | goto out; |
1da177e4 LT |
15393 | |
15394 | tp->timer.expires = jiffies + tp->timer_offset; | |
15395 | add_timer(&tp->timer); | |
15396 | ||
15397 | netif_device_attach(dev); | |
15398 | tg3_netif_start(tp); | |
15399 | ||
b9ec6c1b | 15400 | out: |
f47c11ee | 15401 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15402 | |
15403 | if (!err2) | |
15404 | tg3_phy_start(tp); | |
1da177e4 LT |
15405 | } |
15406 | ||
15407 | return err; | |
15408 | } | |
15409 | ||
c866b7ea | 15410 | static int tg3_resume(struct device *device) |
1da177e4 | 15411 | { |
c866b7ea | 15412 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15413 | struct net_device *dev = pci_get_drvdata(pdev); |
15414 | struct tg3 *tp = netdev_priv(dev); | |
15415 | int err; | |
15416 | ||
15417 | if (!netif_running(dev)) | |
15418 | return 0; | |
15419 | ||
1da177e4 LT |
15420 | netif_device_attach(dev); |
15421 | ||
f47c11ee | 15422 | tg3_full_lock(tp, 0); |
1da177e4 | 15423 | |
6a9eba15 | 15424 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b9ec6c1b MC |
15425 | err = tg3_restart_hw(tp, 1); |
15426 | if (err) | |
15427 | goto out; | |
1da177e4 LT |
15428 | |
15429 | tp->timer.expires = jiffies + tp->timer_offset; | |
15430 | add_timer(&tp->timer); | |
15431 | ||
1da177e4 LT |
15432 | tg3_netif_start(tp); |
15433 | ||
b9ec6c1b | 15434 | out: |
f47c11ee | 15435 | tg3_full_unlock(tp); |
1da177e4 | 15436 | |
b02fd9e3 MC |
15437 | if (!err) |
15438 | tg3_phy_start(tp); | |
15439 | ||
b9ec6c1b | 15440 | return err; |
1da177e4 LT |
15441 | } |
15442 | ||
c866b7ea | 15443 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15444 | #define TG3_PM_OPS (&tg3_pm_ops) |
15445 | ||
15446 | #else | |
15447 | ||
15448 | #define TG3_PM_OPS NULL | |
15449 | ||
15450 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 15451 | |
1da177e4 LT |
15452 | static struct pci_driver tg3_driver = { |
15453 | .name = DRV_MODULE_NAME, | |
15454 | .id_table = tg3_pci_tbl, | |
15455 | .probe = tg3_init_one, | |
15456 | .remove = __devexit_p(tg3_remove_one), | |
aa6027ca | 15457 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
15458 | }; |
15459 | ||
15460 | static int __init tg3_init(void) | |
15461 | { | |
29917620 | 15462 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
15463 | } |
15464 | ||
15465 | static void __exit tg3_cleanup(void) | |
15466 | { | |
15467 | pci_unregister_driver(&tg3_driver); | |
15468 | } | |
15469 | ||
15470 | module_init(tg3_init); | |
15471 | module_exit(tg3_cleanup); |