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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
b86fb2cf | 7 | * Copyright (C) 2005-2011 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 LT |
28 | #include <linux/init.h> |
29 | #include <linux/ioport.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/ethtool.h> | |
3110f5f5 | 35 | #include <linux/mdio.h> |
1da177e4 | 36 | #include <linux/mii.h> |
158d7abd | 37 | #include <linux/phy.h> |
a9daf367 | 38 | #include <linux/brcmphy.h> |
1da177e4 LT |
39 | #include <linux/if_vlan.h> |
40 | #include <linux/ip.h> | |
41 | #include <linux/tcp.h> | |
42 | #include <linux/workqueue.h> | |
61487480 | 43 | #include <linux/prefetch.h> |
f9a5f7d3 | 44 | #include <linux/dma-mapping.h> |
077f849d | 45 | #include <linux/firmware.h> |
1da177e4 LT |
46 | |
47 | #include <net/checksum.h> | |
c9bdd4b5 | 48 | #include <net/ip.h> |
1da177e4 LT |
49 | |
50 | #include <asm/system.h> | |
27fd9de8 | 51 | #include <linux/io.h> |
1da177e4 | 52 | #include <asm/byteorder.h> |
27fd9de8 | 53 | #include <linux/uaccess.h> |
1da177e4 | 54 | |
49b6e95f | 55 | #ifdef CONFIG_SPARC |
1da177e4 | 56 | #include <asm/idprom.h> |
49b6e95f | 57 | #include <asm/prom.h> |
1da177e4 LT |
58 | #endif |
59 | ||
63532394 MC |
60 | #define BAR_0 0 |
61 | #define BAR_2 2 | |
62 | ||
1da177e4 LT |
63 | #include "tg3.h" |
64 | ||
65 | #define DRV_MODULE_NAME "tg3" | |
6867c843 | 66 | #define TG3_MAJ_NUM 3 |
b86fb2cf | 67 | #define TG3_MIN_NUM 117 |
6867c843 MC |
68 | #define DRV_MODULE_VERSION \ |
69 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
b86fb2cf | 70 | #define DRV_MODULE_RELDATE "January 25, 2011" |
1da177e4 LT |
71 | |
72 | #define TG3_DEF_MAC_MODE 0 | |
73 | #define TG3_DEF_RX_MODE 0 | |
74 | #define TG3_DEF_TX_MODE 0 | |
75 | #define TG3_DEF_MSG_ENABLE \ | |
76 | (NETIF_MSG_DRV | \ | |
77 | NETIF_MSG_PROBE | \ | |
78 | NETIF_MSG_LINK | \ | |
79 | NETIF_MSG_TIMER | \ | |
80 | NETIF_MSG_IFDOWN | \ | |
81 | NETIF_MSG_IFUP | \ | |
82 | NETIF_MSG_RX_ERR | \ | |
83 | NETIF_MSG_TX_ERR) | |
84 | ||
85 | /* length of time before we decide the hardware is borked, | |
86 | * and dev->tx_timeout() should be called to fix the problem | |
87 | */ | |
88 | #define TG3_TX_TIMEOUT (5 * HZ) | |
89 | ||
90 | /* hardware minimum and maximum for a single frame's data payload */ | |
91 | #define TG3_MIN_MTU 60 | |
92 | #define TG3_MAX_MTU(tp) \ | |
8f666b07 | 93 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
94 | |
95 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
96 | * You can't change the ring sizes, but you can change where you place | |
97 | * them in the NIC onboard memory. | |
98 | */ | |
7cb32cf2 | 99 | #define TG3_RX_STD_RING_SIZE(tp) \ |
de9f5230 MC |
100 | ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ |
101 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) | |
1da177e4 | 102 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 103 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
de9f5230 MC |
104 | ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ |
105 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) | |
1da177e4 | 106 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
c6cdf436 | 107 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
108 | |
109 | /* Do not place this n-ring entries value into the tp struct itself, | |
110 | * we really want to expose these constants to GCC so that modulo et | |
111 | * al. operations are done with shifts and masks instead of with | |
112 | * hw multiply/modulo instructions. Another solution would be to | |
113 | * replace things like '% foo' with '& (foo - 1)'. | |
114 | */ | |
1da177e4 LT |
115 | |
116 | #define TG3_TX_RING_SIZE 512 | |
117 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
118 | ||
2c49a44d MC |
119 | #define TG3_RX_STD_RING_BYTES(tp) \ |
120 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
121 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
122 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
123 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 124 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
125 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
126 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
127 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
128 | ||
287be12e MC |
129 | #define TG3_DMA_BYTE_ENAB 64 |
130 | ||
131 | #define TG3_RX_STD_DMA_SZ 1536 | |
132 | #define TG3_RX_JMB_DMA_SZ 9046 | |
133 | ||
134 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
135 | ||
136 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
137 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 138 | |
2c49a44d MC |
139 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
140 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 141 | |
2c49a44d MC |
142 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
143 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 144 | |
d2757fc4 MC |
145 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
146 | * that are at least dword aligned when used in PCIX mode. The driver | |
147 | * works around this bug by double copying the packet. This workaround | |
148 | * is built into the normal double copy length check for efficiency. | |
149 | * | |
150 | * However, the double copy is only necessary on those architectures | |
151 | * where unaligned memory accesses are inefficient. For those architectures | |
152 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
153 | * the 5701 in the normal rx path. Doing so saves a device structure | |
154 | * dereference by hardcoding the double copy threshold in place. | |
155 | */ | |
156 | #define TG3_RX_COPY_THRESHOLD 256 | |
157 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
158 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
159 | #else | |
160 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
161 | #endif | |
162 | ||
1da177e4 | 163 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 164 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
1da177e4 | 165 | |
ad829268 MC |
166 | #define TG3_RAW_IP_ALIGN 2 |
167 | ||
c6cdf436 MC |
168 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
169 | ||
077f849d JSR |
170 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
171 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
172 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
173 | ||
1da177e4 | 174 | static char version[] __devinitdata = |
05dbe005 | 175 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
176 | |
177 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
178 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
179 | MODULE_LICENSE("GPL"); | |
180 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
181 | MODULE_FIRMWARE(FIRMWARE_TG3); |
182 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
183 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
184 | ||
1da177e4 LT |
185 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
186 | module_param(tg3_debug, int, 0); | |
187 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
188 | ||
a3aa1884 | 189 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
190 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
191 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
192 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
193 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
194 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
195 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
196 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
197 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
198 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
199 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
200 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
201 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
202 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
203 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
204 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
205 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
206 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
207 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
208 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
209 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
210 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
211 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 212 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 213 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 214 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
215 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
ba1f3c76 | 262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
13185217 HK |
263 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
264 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
265 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
266 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
267 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
268 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
269 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
270 | {} | |
1da177e4 LT |
271 | }; |
272 | ||
273 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
274 | ||
50da859d | 275 | static const struct { |
1da177e4 | 276 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 277 | } ethtool_stats_keys[] = { |
1da177e4 LT |
278 | { "rx_octets" }, |
279 | { "rx_fragments" }, | |
280 | { "rx_ucast_packets" }, | |
281 | { "rx_mcast_packets" }, | |
282 | { "rx_bcast_packets" }, | |
283 | { "rx_fcs_errors" }, | |
284 | { "rx_align_errors" }, | |
285 | { "rx_xon_pause_rcvd" }, | |
286 | { "rx_xoff_pause_rcvd" }, | |
287 | { "rx_mac_ctrl_rcvd" }, | |
288 | { "rx_xoff_entered" }, | |
289 | { "rx_frame_too_long_errors" }, | |
290 | { "rx_jabbers" }, | |
291 | { "rx_undersize_packets" }, | |
292 | { "rx_in_length_errors" }, | |
293 | { "rx_out_length_errors" }, | |
294 | { "rx_64_or_less_octet_packets" }, | |
295 | { "rx_65_to_127_octet_packets" }, | |
296 | { "rx_128_to_255_octet_packets" }, | |
297 | { "rx_256_to_511_octet_packets" }, | |
298 | { "rx_512_to_1023_octet_packets" }, | |
299 | { "rx_1024_to_1522_octet_packets" }, | |
300 | { "rx_1523_to_2047_octet_packets" }, | |
301 | { "rx_2048_to_4095_octet_packets" }, | |
302 | { "rx_4096_to_8191_octet_packets" }, | |
303 | { "rx_8192_to_9022_octet_packets" }, | |
304 | ||
305 | { "tx_octets" }, | |
306 | { "tx_collisions" }, | |
307 | ||
308 | { "tx_xon_sent" }, | |
309 | { "tx_xoff_sent" }, | |
310 | { "tx_flow_control" }, | |
311 | { "tx_mac_errors" }, | |
312 | { "tx_single_collisions" }, | |
313 | { "tx_mult_collisions" }, | |
314 | { "tx_deferred" }, | |
315 | { "tx_excessive_collisions" }, | |
316 | { "tx_late_collisions" }, | |
317 | { "tx_collide_2times" }, | |
318 | { "tx_collide_3times" }, | |
319 | { "tx_collide_4times" }, | |
320 | { "tx_collide_5times" }, | |
321 | { "tx_collide_6times" }, | |
322 | { "tx_collide_7times" }, | |
323 | { "tx_collide_8times" }, | |
324 | { "tx_collide_9times" }, | |
325 | { "tx_collide_10times" }, | |
326 | { "tx_collide_11times" }, | |
327 | { "tx_collide_12times" }, | |
328 | { "tx_collide_13times" }, | |
329 | { "tx_collide_14times" }, | |
330 | { "tx_collide_15times" }, | |
331 | { "tx_ucast_packets" }, | |
332 | { "tx_mcast_packets" }, | |
333 | { "tx_bcast_packets" }, | |
334 | { "tx_carrier_sense_errors" }, | |
335 | { "tx_discards" }, | |
336 | { "tx_errors" }, | |
337 | ||
338 | { "dma_writeq_full" }, | |
339 | { "dma_write_prioq_full" }, | |
340 | { "rxbds_empty" }, | |
341 | { "rx_discards" }, | |
4d958473 | 342 | { "mbuf_lwm_thresh_hit" }, |
1da177e4 LT |
343 | { "rx_errors" }, |
344 | { "rx_threshold_hit" }, | |
345 | ||
346 | { "dma_readq_full" }, | |
347 | { "dma_read_prioq_full" }, | |
348 | { "tx_comp_queue_full" }, | |
349 | ||
350 | { "ring_set_send_prod_index" }, | |
351 | { "ring_status_update" }, | |
352 | { "nic_irqs" }, | |
353 | { "nic_avoided_irqs" }, | |
354 | { "nic_tx_threshold_hit" } | |
355 | }; | |
356 | ||
48fa55a0 MC |
357 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
358 | ||
359 | ||
50da859d | 360 | static const struct { |
4cafd3f5 | 361 | const char string[ETH_GSTRING_LEN]; |
48fa55a0 | 362 | } ethtool_test_keys[] = { |
4cafd3f5 MC |
363 | { "nvram test (online) " }, |
364 | { "link test (online) " }, | |
365 | { "register test (offline)" }, | |
366 | { "memory test (offline)" }, | |
367 | { "loopback test (offline)" }, | |
368 | { "interrupt test (offline)" }, | |
369 | }; | |
370 | ||
48fa55a0 MC |
371 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
372 | ||
373 | ||
b401e9e2 MC |
374 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
375 | { | |
376 | writel(val, tp->regs + off); | |
377 | } | |
378 | ||
379 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
380 | { | |
de6f31eb | 381 | return readl(tp->regs + off); |
b401e9e2 MC |
382 | } |
383 | ||
0d3031d9 MC |
384 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
385 | { | |
386 | writel(val, tp->aperegs + off); | |
387 | } | |
388 | ||
389 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
390 | { | |
de6f31eb | 391 | return readl(tp->aperegs + off); |
0d3031d9 MC |
392 | } |
393 | ||
1da177e4 LT |
394 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
395 | { | |
6892914f MC |
396 | unsigned long flags; |
397 | ||
398 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
399 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
400 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 401 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
402 | } |
403 | ||
404 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
405 | { | |
406 | writel(val, tp->regs + off); | |
407 | readl(tp->regs + off); | |
1da177e4 LT |
408 | } |
409 | ||
6892914f | 410 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 411 | { |
6892914f MC |
412 | unsigned long flags; |
413 | u32 val; | |
414 | ||
415 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
416 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
417 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
418 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
419 | return val; | |
420 | } | |
421 | ||
422 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
423 | { | |
424 | unsigned long flags; | |
425 | ||
426 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
427 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
428 | TG3_64BIT_REG_LOW, val); | |
429 | return; | |
430 | } | |
66711e66 | 431 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
432 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
433 | TG3_64BIT_REG_LOW, val); | |
434 | return; | |
1da177e4 | 435 | } |
6892914f MC |
436 | |
437 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
438 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
439 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
440 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
441 | ||
442 | /* In indirect mode when disabling interrupts, we also need | |
443 | * to clear the interrupt bit in the GRC local ctrl register. | |
444 | */ | |
445 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
446 | (val == 0x1)) { | |
447 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
448 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
449 | } | |
450 | } | |
451 | ||
452 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
453 | { | |
454 | unsigned long flags; | |
455 | u32 val; | |
456 | ||
457 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
458 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
459 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
460 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
461 | return val; | |
462 | } | |
463 | ||
b401e9e2 MC |
464 | /* usec_wait specifies the wait time in usec when writing to certain registers |
465 | * where it is unsafe to read back the register without some delay. | |
466 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
467 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
468 | */ | |
469 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 470 | { |
b401e9e2 MC |
471 | if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || |
472 | (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
473 | /* Non-posted methods */ | |
474 | tp->write32(tp, off, val); | |
475 | else { | |
476 | /* Posted method */ | |
477 | tg3_write32(tp, off, val); | |
478 | if (usec_wait) | |
479 | udelay(usec_wait); | |
480 | tp->read32(tp, off); | |
481 | } | |
482 | /* Wait again after the read for the posted method to guarantee that | |
483 | * the wait time is met. | |
484 | */ | |
485 | if (usec_wait) | |
486 | udelay(usec_wait); | |
1da177e4 LT |
487 | } |
488 | ||
09ee929c MC |
489 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
490 | { | |
491 | tp->write32_mbox(tp, off, val); | |
6892914f MC |
492 | if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && |
493 | !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
494 | tp->read32_mbox(tp, off); | |
09ee929c MC |
495 | } |
496 | ||
20094930 | 497 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
498 | { |
499 | void __iomem *mbox = tp->regs + off; | |
500 | writel(val, mbox); | |
501 | if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) | |
502 | writel(val, mbox); | |
503 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
504 | readl(mbox); | |
505 | } | |
506 | ||
b5d3772c MC |
507 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
508 | { | |
de6f31eb | 509 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
510 | } |
511 | ||
512 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
513 | { | |
514 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
515 | } | |
516 | ||
c6cdf436 | 517 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 518 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
519 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
520 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
521 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 522 | |
c6cdf436 MC |
523 | #define tw32(reg, val) tp->write32(tp, reg, val) |
524 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
525 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
526 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
527 | |
528 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
529 | { | |
6892914f MC |
530 | unsigned long flags; |
531 | ||
b5d3772c MC |
532 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
533 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
534 | return; | |
535 | ||
6892914f | 536 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
537 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
538 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
539 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 540 | |
bbadf503 MC |
541 | /* Always leave this as zero. */ |
542 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
543 | } else { | |
544 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
545 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 546 | |
bbadf503 MC |
547 | /* Always leave this as zero. */ |
548 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
549 | } | |
550 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
551 | } |
552 | ||
1da177e4 LT |
553 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
554 | { | |
6892914f MC |
555 | unsigned long flags; |
556 | ||
b5d3772c MC |
557 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
558 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
559 | *val = 0; | |
560 | return; | |
561 | } | |
562 | ||
6892914f | 563 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
564 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
565 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
566 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 567 | |
bbadf503 MC |
568 | /* Always leave this as zero. */ |
569 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
570 | } else { | |
571 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
572 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
573 | ||
574 | /* Always leave this as zero. */ | |
575 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
576 | } | |
6892914f | 577 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
578 | } |
579 | ||
0d3031d9 MC |
580 | static void tg3_ape_lock_init(struct tg3 *tp) |
581 | { | |
582 | int i; | |
f92d9dc1 MC |
583 | u32 regbase; |
584 | ||
585 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
586 | regbase = TG3_APE_LOCK_GRANT; | |
587 | else | |
588 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
589 | |
590 | /* Make sure the driver hasn't any stale locks. */ | |
591 | for (i = 0; i < 8; i++) | |
f92d9dc1 | 592 | tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER); |
0d3031d9 MC |
593 | } |
594 | ||
595 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
596 | { | |
597 | int i, off; | |
598 | int ret = 0; | |
f92d9dc1 | 599 | u32 status, req, gnt; |
0d3031d9 MC |
600 | |
601 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
602 | return 0; | |
603 | ||
604 | switch (locknum) { | |
33f401ae MC |
605 | case TG3_APE_LOCK_GRC: |
606 | case TG3_APE_LOCK_MEM: | |
607 | break; | |
608 | default: | |
609 | return -EINVAL; | |
0d3031d9 MC |
610 | } |
611 | ||
f92d9dc1 MC |
612 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
613 | req = TG3_APE_LOCK_REQ; | |
614 | gnt = TG3_APE_LOCK_GRANT; | |
615 | } else { | |
616 | req = TG3_APE_PER_LOCK_REQ; | |
617 | gnt = TG3_APE_PER_LOCK_GRANT; | |
618 | } | |
619 | ||
0d3031d9 MC |
620 | off = 4 * locknum; |
621 | ||
f92d9dc1 | 622 | tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER); |
0d3031d9 MC |
623 | |
624 | /* Wait for up to 1 millisecond to acquire lock. */ | |
625 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 626 | status = tg3_ape_read32(tp, gnt + off); |
0d3031d9 MC |
627 | if (status == APE_LOCK_GRANT_DRIVER) |
628 | break; | |
629 | udelay(10); | |
630 | } | |
631 | ||
632 | if (status != APE_LOCK_GRANT_DRIVER) { | |
633 | /* Revoke the lock request. */ | |
f92d9dc1 | 634 | tg3_ape_write32(tp, gnt + off, |
0d3031d9 MC |
635 | APE_LOCK_GRANT_DRIVER); |
636 | ||
637 | ret = -EBUSY; | |
638 | } | |
639 | ||
640 | return ret; | |
641 | } | |
642 | ||
643 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
644 | { | |
f92d9dc1 | 645 | u32 gnt; |
0d3031d9 MC |
646 | |
647 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
648 | return; | |
649 | ||
650 | switch (locknum) { | |
33f401ae MC |
651 | case TG3_APE_LOCK_GRC: |
652 | case TG3_APE_LOCK_MEM: | |
653 | break; | |
654 | default: | |
655 | return; | |
0d3031d9 MC |
656 | } |
657 | ||
f92d9dc1 MC |
658 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
659 | gnt = TG3_APE_LOCK_GRANT; | |
660 | else | |
661 | gnt = TG3_APE_PER_LOCK_GRANT; | |
662 | ||
663 | tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER); | |
0d3031d9 MC |
664 | } |
665 | ||
1da177e4 LT |
666 | static void tg3_disable_ints(struct tg3 *tp) |
667 | { | |
89aeb3bc MC |
668 | int i; |
669 | ||
1da177e4 LT |
670 | tw32(TG3PCI_MISC_HOST_CTRL, |
671 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
672 | for (i = 0; i < tp->irq_max; i++) |
673 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
674 | } |
675 | ||
1da177e4 LT |
676 | static void tg3_enable_ints(struct tg3 *tp) |
677 | { | |
89aeb3bc | 678 | int i; |
89aeb3bc | 679 | |
bbe832c0 MC |
680 | tp->irq_sync = 0; |
681 | wmb(); | |
682 | ||
1da177e4 LT |
683 | tw32(TG3PCI_MISC_HOST_CTRL, |
684 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 685 | |
f89f38b8 | 686 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
687 | for (i = 0; i < tp->irq_cnt; i++) { |
688 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 689 | |
898a56f8 | 690 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
89aeb3bc MC |
691 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) |
692 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
f19af9c2 | 693 | |
f89f38b8 | 694 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 695 | } |
f19af9c2 MC |
696 | |
697 | /* Force an initial interrupt */ | |
698 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
699 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) | |
700 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
701 | else | |
f89f38b8 MC |
702 | tw32(HOSTCC_MODE, tp->coal_now); |
703 | ||
704 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
705 | } |
706 | ||
17375d25 | 707 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 708 | { |
17375d25 | 709 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 710 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
711 | unsigned int work_exists = 0; |
712 | ||
713 | /* check for phy events */ | |
714 | if (!(tp->tg3_flags & | |
715 | (TG3_FLAG_USE_LINKCHG_REG | | |
716 | TG3_FLAG_POLL_SERDES))) { | |
717 | if (sblk->status & SD_STATUS_LINK_CHG) | |
718 | work_exists = 1; | |
719 | } | |
720 | /* check for RX/TX work to do */ | |
f3f3f27e | 721 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 722 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
723 | work_exists = 1; |
724 | ||
725 | return work_exists; | |
726 | } | |
727 | ||
17375d25 | 728 | /* tg3_int_reenable |
04237ddd MC |
729 | * similar to tg3_enable_ints, but it accurately determines whether there |
730 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 731 | * which reenables interrupts |
1da177e4 | 732 | */ |
17375d25 | 733 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 734 | { |
17375d25 MC |
735 | struct tg3 *tp = tnapi->tp; |
736 | ||
898a56f8 | 737 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
738 | mmiowb(); |
739 | ||
fac9b83e DM |
740 | /* When doing tagged status, this work check is unnecessary. |
741 | * The last_tag we write above tells the chip which piece of | |
742 | * work we've completed. | |
743 | */ | |
744 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
17375d25 | 745 | tg3_has_work(tnapi)) |
04237ddd | 746 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 747 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
748 | } |
749 | ||
1da177e4 LT |
750 | static void tg3_switch_clocks(struct tg3 *tp) |
751 | { | |
f6eb9b1f | 752 | u32 clock_ctrl; |
1da177e4 LT |
753 | u32 orig_clock_ctrl; |
754 | ||
795d01c5 MC |
755 | if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
756 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
4cf78e4f MC |
757 | return; |
758 | ||
f6eb9b1f MC |
759 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
760 | ||
1da177e4 LT |
761 | orig_clock_ctrl = clock_ctrl; |
762 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
763 | CLOCK_CTRL_CLKRUN_OENABLE | | |
764 | 0x1f); | |
765 | tp->pci_clock_ctrl = clock_ctrl; | |
766 | ||
767 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
768 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
b401e9e2 MC |
769 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
770 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
771 | } |
772 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
773 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
774 | clock_ctrl | | |
775 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
776 | 40); | |
777 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
778 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
779 | 40); | |
1da177e4 | 780 | } |
b401e9e2 | 781 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
782 | } |
783 | ||
784 | #define PHY_BUSY_LOOPS 5000 | |
785 | ||
786 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
787 | { | |
788 | u32 frame_val; | |
789 | unsigned int loops; | |
790 | int ret; | |
791 | ||
792 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
793 | tw32_f(MAC_MI_MODE, | |
794 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
795 | udelay(80); | |
796 | } | |
797 | ||
798 | *val = 0x0; | |
799 | ||
882e9793 | 800 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
801 | MI_COM_PHY_ADDR_MASK); |
802 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
803 | MI_COM_REG_ADDR_MASK); | |
804 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 805 | |
1da177e4 LT |
806 | tw32_f(MAC_MI_COM, frame_val); |
807 | ||
808 | loops = PHY_BUSY_LOOPS; | |
809 | while (loops != 0) { | |
810 | udelay(10); | |
811 | frame_val = tr32(MAC_MI_COM); | |
812 | ||
813 | if ((frame_val & MI_COM_BUSY) == 0) { | |
814 | udelay(5); | |
815 | frame_val = tr32(MAC_MI_COM); | |
816 | break; | |
817 | } | |
818 | loops -= 1; | |
819 | } | |
820 | ||
821 | ret = -EBUSY; | |
822 | if (loops != 0) { | |
823 | *val = frame_val & MI_COM_DATA_MASK; | |
824 | ret = 0; | |
825 | } | |
826 | ||
827 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
828 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
829 | udelay(80); | |
830 | } | |
831 | ||
832 | return ret; | |
833 | } | |
834 | ||
835 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
836 | { | |
837 | u32 frame_val; | |
838 | unsigned int loops; | |
839 | int ret; | |
840 | ||
f07e9af3 | 841 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
b5d3772c MC |
842 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) |
843 | return 0; | |
844 | ||
1da177e4 LT |
845 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
846 | tw32_f(MAC_MI_MODE, | |
847 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
848 | udelay(80); | |
849 | } | |
850 | ||
882e9793 | 851 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
852 | MI_COM_PHY_ADDR_MASK); |
853 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
854 | MI_COM_REG_ADDR_MASK); | |
855 | frame_val |= (val & MI_COM_DATA_MASK); | |
856 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 857 | |
1da177e4 LT |
858 | tw32_f(MAC_MI_COM, frame_val); |
859 | ||
860 | loops = PHY_BUSY_LOOPS; | |
861 | while (loops != 0) { | |
862 | udelay(10); | |
863 | frame_val = tr32(MAC_MI_COM); | |
864 | if ((frame_val & MI_COM_BUSY) == 0) { | |
865 | udelay(5); | |
866 | frame_val = tr32(MAC_MI_COM); | |
867 | break; | |
868 | } | |
869 | loops -= 1; | |
870 | } | |
871 | ||
872 | ret = -EBUSY; | |
873 | if (loops != 0) | |
874 | ret = 0; | |
875 | ||
876 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
877 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
878 | udelay(80); | |
879 | } | |
880 | ||
881 | return ret; | |
882 | } | |
883 | ||
95e2869a MC |
884 | static int tg3_bmcr_reset(struct tg3 *tp) |
885 | { | |
886 | u32 phy_control; | |
887 | int limit, err; | |
888 | ||
889 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
890 | * clears or we time out. | |
891 | */ | |
892 | phy_control = BMCR_RESET; | |
893 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
894 | if (err != 0) | |
895 | return -EBUSY; | |
896 | ||
897 | limit = 5000; | |
898 | while (limit--) { | |
899 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
900 | if (err != 0) | |
901 | return -EBUSY; | |
902 | ||
903 | if ((phy_control & BMCR_RESET) == 0) { | |
904 | udelay(40); | |
905 | break; | |
906 | } | |
907 | udelay(10); | |
908 | } | |
d4675b52 | 909 | if (limit < 0) |
95e2869a MC |
910 | return -EBUSY; |
911 | ||
912 | return 0; | |
913 | } | |
914 | ||
158d7abd MC |
915 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
916 | { | |
3d16543d | 917 | struct tg3 *tp = bp->priv; |
158d7abd MC |
918 | u32 val; |
919 | ||
24bb4fb6 | 920 | spin_lock_bh(&tp->lock); |
158d7abd MC |
921 | |
922 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
923 | val = -EIO; |
924 | ||
925 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
926 | |
927 | return val; | |
928 | } | |
929 | ||
930 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
931 | { | |
3d16543d | 932 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 933 | u32 ret = 0; |
158d7abd | 934 | |
24bb4fb6 | 935 | spin_lock_bh(&tp->lock); |
158d7abd MC |
936 | |
937 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 938 | ret = -EIO; |
158d7abd | 939 | |
24bb4fb6 MC |
940 | spin_unlock_bh(&tp->lock); |
941 | ||
942 | return ret; | |
158d7abd MC |
943 | } |
944 | ||
945 | static int tg3_mdio_reset(struct mii_bus *bp) | |
946 | { | |
947 | return 0; | |
948 | } | |
949 | ||
9c61d6bc | 950 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
951 | { |
952 | u32 val; | |
fcb389df | 953 | struct phy_device *phydev; |
a9daf367 | 954 | |
3f0e3ad7 | 955 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 956 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
957 | case PHY_ID_BCM50610: |
958 | case PHY_ID_BCM50610M: | |
fcb389df MC |
959 | val = MAC_PHYCFG2_50610_LED_MODES; |
960 | break; | |
6a443a0f | 961 | case PHY_ID_BCMAC131: |
fcb389df MC |
962 | val = MAC_PHYCFG2_AC131_LED_MODES; |
963 | break; | |
6a443a0f | 964 | case PHY_ID_RTL8211C: |
fcb389df MC |
965 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
966 | break; | |
6a443a0f | 967 | case PHY_ID_RTL8201E: |
fcb389df MC |
968 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
969 | break; | |
970 | default: | |
a9daf367 | 971 | return; |
fcb389df MC |
972 | } |
973 | ||
974 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
975 | tw32(MAC_PHYCFG2, val); | |
976 | ||
977 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
978 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
979 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
980 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
981 | tw32(MAC_PHYCFG1, val); |
982 | ||
983 | return; | |
984 | } | |
985 | ||
14417063 | 986 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) |
fcb389df MC |
987 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
988 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
989 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
990 | MAC_PHYCFG2_ACT_MASK_MASK | | |
991 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
992 | MAC_PHYCFG2_INBAND_ENABLE; | |
993 | ||
994 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 995 | |
bb85fbb6 MC |
996 | val = tr32(MAC_PHYCFG1); |
997 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
998 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
14417063 | 999 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
1000 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1001 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
1002 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1003 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
1004 | } | |
bb85fbb6 MC |
1005 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1006 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1007 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1008 | |
a9daf367 MC |
1009 | val = tr32(MAC_EXT_RGMII_MODE); |
1010 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1011 | MAC_RGMII_MODE_RX_QUALITY | | |
1012 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1013 | MAC_RGMII_MODE_RX_ENG_DET | | |
1014 | MAC_RGMII_MODE_TX_ENABLE | | |
1015 | MAC_RGMII_MODE_TX_LOWPWR | | |
1016 | MAC_RGMII_MODE_TX_RESET); | |
14417063 | 1017 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
1018 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1019 | val |= MAC_RGMII_MODE_RX_INT_B | | |
1020 | MAC_RGMII_MODE_RX_QUALITY | | |
1021 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1022 | MAC_RGMII_MODE_RX_ENG_DET; | |
1023 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1024 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
1025 | MAC_RGMII_MODE_TX_LOWPWR | | |
1026 | MAC_RGMII_MODE_TX_RESET; | |
1027 | } | |
1028 | tw32(MAC_EXT_RGMII_MODE, val); | |
1029 | } | |
1030 | ||
158d7abd MC |
1031 | static void tg3_mdio_start(struct tg3 *tp) |
1032 | { | |
158d7abd MC |
1033 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1034 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1035 | udelay(80); | |
a9daf367 | 1036 | |
9ea4818d MC |
1037 | if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && |
1038 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1039 | tg3_mdio_config_5785(tp); | |
1040 | } | |
1041 | ||
1042 | static int tg3_mdio_init(struct tg3 *tp) | |
1043 | { | |
1044 | int i; | |
1045 | u32 reg; | |
1046 | struct phy_device *phydev; | |
1047 | ||
0a58d668 | 1048 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
9c7df915 | 1049 | u32 is_serdes; |
882e9793 | 1050 | |
9c7df915 | 1051 | tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1; |
882e9793 | 1052 | |
d1ec96af MC |
1053 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1054 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1055 | else | |
1056 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1057 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1058 | if (is_serdes) |
1059 | tp->phy_addr += 7; | |
1060 | } else | |
3f0e3ad7 | 1061 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1062 | |
158d7abd MC |
1063 | tg3_mdio_start(tp); |
1064 | ||
1065 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || | |
1066 | (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)) | |
1067 | return 0; | |
1068 | ||
298cf9be LB |
1069 | tp->mdio_bus = mdiobus_alloc(); |
1070 | if (tp->mdio_bus == NULL) | |
1071 | return -ENOMEM; | |
158d7abd | 1072 | |
298cf9be LB |
1073 | tp->mdio_bus->name = "tg3 mdio bus"; |
1074 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1075 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1076 | tp->mdio_bus->priv = tp; |
1077 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1078 | tp->mdio_bus->read = &tg3_mdio_read; | |
1079 | tp->mdio_bus->write = &tg3_mdio_write; | |
1080 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1081 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1082 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1083 | |
1084 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1085 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1086 | |
1087 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1088 | * Unfortunately, it does not ensure the PHY is powered up before | |
1089 | * accessing the PHY ID registers. A chip reset is the | |
1090 | * quickest way to bring the device back to an operational state.. | |
1091 | */ | |
1092 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1093 | tg3_bmcr_reset(tp); | |
1094 | ||
298cf9be | 1095 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1096 | if (i) { |
ab96b241 | 1097 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1098 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1099 | return i; |
1100 | } | |
158d7abd | 1101 | |
3f0e3ad7 | 1102 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1103 | |
9c61d6bc | 1104 | if (!phydev || !phydev->drv) { |
ab96b241 | 1105 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1106 | mdiobus_unregister(tp->mdio_bus); |
1107 | mdiobus_free(tp->mdio_bus); | |
1108 | return -ENODEV; | |
1109 | } | |
1110 | ||
1111 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1112 | case PHY_ID_BCM57780: |
321d32a0 | 1113 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1114 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1115 | break; |
6a443a0f MC |
1116 | case PHY_ID_BCM50610: |
1117 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1118 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1119 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1120 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1121 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
14417063 | 1122 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE) |
a9daf367 MC |
1123 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
1124 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1125 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1126 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1127 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
fcb389df | 1128 | /* fallthru */ |
6a443a0f | 1129 | case PHY_ID_RTL8211C: |
fcb389df | 1130 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1131 | break; |
6a443a0f MC |
1132 | case PHY_ID_RTL8201E: |
1133 | case PHY_ID_BCMAC131: | |
a9daf367 | 1134 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1135 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1136 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1137 | break; |
1138 | } | |
1139 | ||
9c61d6bc MC |
1140 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; |
1141 | ||
1142 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1143 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1144 | |
1145 | return 0; | |
158d7abd MC |
1146 | } |
1147 | ||
1148 | static void tg3_mdio_fini(struct tg3 *tp) | |
1149 | { | |
1150 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
1151 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; | |
298cf9be LB |
1152 | mdiobus_unregister(tp->mdio_bus); |
1153 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1154 | } |
1155 | } | |
1156 | ||
ddfc87bf MC |
1157 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
1158 | { | |
1159 | int err; | |
1160 | ||
1161 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1162 | if (err) | |
1163 | goto done; | |
1164 | ||
1165 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1166 | if (err) | |
1167 | goto done; | |
1168 | ||
1169 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1170 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1171 | if (err) | |
1172 | goto done; | |
1173 | ||
1174 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
1175 | ||
1176 | done: | |
1177 | return err; | |
1178 | } | |
1179 | ||
1180 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
1181 | { | |
1182 | int err; | |
1183 | ||
1184 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1185 | if (err) | |
1186 | goto done; | |
1187 | ||
1188 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1189 | if (err) | |
1190 | goto done; | |
1191 | ||
1192 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1193 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1194 | if (err) | |
1195 | goto done; | |
1196 | ||
1197 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
1198 | ||
1199 | done: | |
1200 | return err; | |
1201 | } | |
1202 | ||
4ba526ce MC |
1203 | /* tp->lock is held. */ |
1204 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1205 | { | |
1206 | u32 val; | |
1207 | ||
1208 | val = tr32(GRC_RX_CPU_EVENT); | |
1209 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1210 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1211 | ||
1212 | tp->last_event_jiffies = jiffies; | |
1213 | } | |
1214 | ||
1215 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1216 | ||
95e2869a MC |
1217 | /* tp->lock is held. */ |
1218 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1219 | { | |
1220 | int i; | |
4ba526ce MC |
1221 | unsigned int delay_cnt; |
1222 | long time_remain; | |
1223 | ||
1224 | /* If enough time has passed, no wait is necessary. */ | |
1225 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1226 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1227 | (long)jiffies; | |
1228 | if (time_remain < 0) | |
1229 | return; | |
1230 | ||
1231 | /* Check if we can shorten the wait time. */ | |
1232 | delay_cnt = jiffies_to_usecs(time_remain); | |
1233 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1234 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1235 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1236 | |
4ba526ce | 1237 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1238 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1239 | break; | |
4ba526ce | 1240 | udelay(8); |
95e2869a MC |
1241 | } |
1242 | } | |
1243 | ||
1244 | /* tp->lock is held. */ | |
1245 | static void tg3_ump_link_report(struct tg3 *tp) | |
1246 | { | |
1247 | u32 reg; | |
1248 | u32 val; | |
1249 | ||
1250 | if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
1251 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
1252 | return; | |
1253 | ||
1254 | tg3_wait_for_event_ack(tp); | |
1255 | ||
1256 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1257 | ||
1258 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1259 | ||
1260 | val = 0; | |
1261 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1262 | val = reg << 16; | |
1263 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1264 | val |= (reg & 0xffff); | |
1265 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1266 | ||
1267 | val = 0; | |
1268 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1269 | val = reg << 16; | |
1270 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1271 | val |= (reg & 0xffff); | |
1272 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1273 | ||
1274 | val = 0; | |
f07e9af3 | 1275 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1276 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1277 | val = reg << 16; | |
1278 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1279 | val |= (reg & 0xffff); | |
1280 | } | |
1281 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1282 | ||
1283 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1284 | val = reg << 16; | |
1285 | else | |
1286 | val = 0; | |
1287 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1288 | ||
4ba526ce | 1289 | tg3_generate_fw_event(tp); |
95e2869a MC |
1290 | } |
1291 | ||
1292 | static void tg3_link_report(struct tg3 *tp) | |
1293 | { | |
1294 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1295 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1296 | tg3_ump_link_report(tp); |
1297 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1298 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1299 | (tp->link_config.active_speed == SPEED_1000 ? | |
1300 | 1000 : | |
1301 | (tp->link_config.active_speed == SPEED_100 ? | |
1302 | 100 : 10)), | |
1303 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1304 | "full" : "half")); | |
1305 | ||
1306 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1307 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1308 | "on" : "off", | |
1309 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1310 | "on" : "off"); | |
95e2869a MC |
1311 | tg3_ump_link_report(tp); |
1312 | } | |
1313 | } | |
1314 | ||
1315 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1316 | { | |
1317 | u16 miireg; | |
1318 | ||
e18ce346 | 1319 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1320 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1321 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1322 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1323 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1324 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1325 | else | |
1326 | miireg = 0; | |
1327 | ||
1328 | return miireg; | |
1329 | } | |
1330 | ||
1331 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1332 | { | |
1333 | u16 miireg; | |
1334 | ||
e18ce346 | 1335 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1336 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1337 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1338 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1339 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1340 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1341 | else | |
1342 | miireg = 0; | |
1343 | ||
1344 | return miireg; | |
1345 | } | |
1346 | ||
95e2869a MC |
1347 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1348 | { | |
1349 | u8 cap = 0; | |
1350 | ||
1351 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1352 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1353 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1354 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1355 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1356 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1357 | } else { |
1358 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1359 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1360 | } |
1361 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1362 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1363 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1364 | } |
1365 | ||
1366 | return cap; | |
1367 | } | |
1368 | ||
f51f3562 | 1369 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1370 | { |
b02fd9e3 | 1371 | u8 autoneg; |
f51f3562 | 1372 | u8 flowctrl = 0; |
95e2869a MC |
1373 | u32 old_rx_mode = tp->rx_mode; |
1374 | u32 old_tx_mode = tp->tx_mode; | |
1375 | ||
b02fd9e3 | 1376 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
3f0e3ad7 | 1377 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1378 | else |
1379 | autoneg = tp->link_config.autoneg; | |
1380 | ||
1381 | if (autoneg == AUTONEG_ENABLE && | |
95e2869a | 1382 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { |
f07e9af3 | 1383 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1384 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1385 | else |
bc02ff95 | 1386 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1387 | } else |
1388 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1389 | |
f51f3562 | 1390 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1391 | |
e18ce346 | 1392 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1393 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1394 | else | |
1395 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1396 | ||
f51f3562 | 1397 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1398 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1399 | |
e18ce346 | 1400 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1401 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1402 | else | |
1403 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1404 | ||
f51f3562 | 1405 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1406 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1407 | } |
1408 | ||
b02fd9e3 MC |
1409 | static void tg3_adjust_link(struct net_device *dev) |
1410 | { | |
1411 | u8 oldflowctrl, linkmesg = 0; | |
1412 | u32 mac_mode, lcl_adv, rmt_adv; | |
1413 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1414 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1415 | |
24bb4fb6 | 1416 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1417 | |
1418 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1419 | MAC_MODE_HALF_DUPLEX); | |
1420 | ||
1421 | oldflowctrl = tp->link_config.active_flowctrl; | |
1422 | ||
1423 | if (phydev->link) { | |
1424 | lcl_adv = 0; | |
1425 | rmt_adv = 0; | |
1426 | ||
1427 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1428 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1429 | else if (phydev->speed == SPEED_1000 || |
1430 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1431 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1432 | else |
1433 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1434 | |
1435 | if (phydev->duplex == DUPLEX_HALF) | |
1436 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1437 | else { | |
1438 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1439 | tp->link_config.flowctrl); | |
1440 | ||
1441 | if (phydev->pause) | |
1442 | rmt_adv = LPA_PAUSE_CAP; | |
1443 | if (phydev->asym_pause) | |
1444 | rmt_adv |= LPA_PAUSE_ASYM; | |
1445 | } | |
1446 | ||
1447 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1448 | } else | |
1449 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1450 | ||
1451 | if (mac_mode != tp->mac_mode) { | |
1452 | tp->mac_mode = mac_mode; | |
1453 | tw32_f(MAC_MODE, tp->mac_mode); | |
1454 | udelay(40); | |
1455 | } | |
1456 | ||
fcb389df MC |
1457 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1458 | if (phydev->speed == SPEED_10) | |
1459 | tw32(MAC_MI_STAT, | |
1460 | MAC_MI_STAT_10MBPS_MODE | | |
1461 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1462 | else | |
1463 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1464 | } | |
1465 | ||
b02fd9e3 MC |
1466 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1467 | tw32(MAC_TX_LENGTHS, | |
1468 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1469 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1470 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1471 | else | |
1472 | tw32(MAC_TX_LENGTHS, | |
1473 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1474 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1475 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1476 | ||
1477 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1478 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1479 | phydev->speed != tp->link_config.active_speed || | |
1480 | phydev->duplex != tp->link_config.active_duplex || | |
1481 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1482 | linkmesg = 1; |
b02fd9e3 MC |
1483 | |
1484 | tp->link_config.active_speed = phydev->speed; | |
1485 | tp->link_config.active_duplex = phydev->duplex; | |
1486 | ||
24bb4fb6 | 1487 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1488 | |
1489 | if (linkmesg) | |
1490 | tg3_link_report(tp); | |
1491 | } | |
1492 | ||
1493 | static int tg3_phy_init(struct tg3 *tp) | |
1494 | { | |
1495 | struct phy_device *phydev; | |
1496 | ||
f07e9af3 | 1497 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1498 | return 0; |
1499 | ||
1500 | /* Bring the PHY back to a known state. */ | |
1501 | tg3_bmcr_reset(tp); | |
1502 | ||
3f0e3ad7 | 1503 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1504 | |
1505 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1506 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1507 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1508 | if (IS_ERR(phydev)) { |
ab96b241 | 1509 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1510 | return PTR_ERR(phydev); |
1511 | } | |
1512 | ||
b02fd9e3 | 1513 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1514 | switch (phydev->interface) { |
1515 | case PHY_INTERFACE_MODE_GMII: | |
1516 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1517 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1518 | phydev->supported &= (PHY_GBIT_FEATURES | |
1519 | SUPPORTED_Pause | | |
1520 | SUPPORTED_Asym_Pause); | |
1521 | break; | |
1522 | } | |
1523 | /* fallthru */ | |
9c61d6bc MC |
1524 | case PHY_INTERFACE_MODE_MII: |
1525 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1526 | SUPPORTED_Pause | | |
1527 | SUPPORTED_Asym_Pause); | |
1528 | break; | |
1529 | default: | |
3f0e3ad7 | 1530 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1531 | return -EINVAL; |
1532 | } | |
1533 | ||
f07e9af3 | 1534 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1535 | |
1536 | phydev->advertising = phydev->supported; | |
1537 | ||
b02fd9e3 MC |
1538 | return 0; |
1539 | } | |
1540 | ||
1541 | static void tg3_phy_start(struct tg3 *tp) | |
1542 | { | |
1543 | struct phy_device *phydev; | |
1544 | ||
f07e9af3 | 1545 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1546 | return; |
1547 | ||
3f0e3ad7 | 1548 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1549 | |
80096068 MC |
1550 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1551 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
b02fd9e3 MC |
1552 | phydev->speed = tp->link_config.orig_speed; |
1553 | phydev->duplex = tp->link_config.orig_duplex; | |
1554 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1555 | phydev->advertising = tp->link_config.orig_advertising; | |
1556 | } | |
1557 | ||
1558 | phy_start(phydev); | |
1559 | ||
1560 | phy_start_aneg(phydev); | |
1561 | } | |
1562 | ||
1563 | static void tg3_phy_stop(struct tg3 *tp) | |
1564 | { | |
f07e9af3 | 1565 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1566 | return; |
1567 | ||
3f0e3ad7 | 1568 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1569 | } |
1570 | ||
1571 | static void tg3_phy_fini(struct tg3 *tp) | |
1572 | { | |
f07e9af3 | 1573 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1574 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1575 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1576 | } |
1577 | } | |
1578 | ||
52b02d04 MC |
1579 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) |
1580 | { | |
1581 | int err; | |
1582 | ||
1583 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1584 | if (!err) | |
1585 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
1586 | ||
1587 | return err; | |
1588 | } | |
1589 | ||
6ee7c0a0 | 1590 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) |
b2a5c19c | 1591 | { |
6ee7c0a0 MC |
1592 | int err; |
1593 | ||
1594 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1595 | if (!err) | |
1596 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1597 | ||
1598 | return err; | |
b2a5c19c MC |
1599 | } |
1600 | ||
7f97a4bd MC |
1601 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1602 | { | |
1603 | u32 phytest; | |
1604 | ||
1605 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1606 | u32 phy; | |
1607 | ||
1608 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1609 | phytest | MII_TG3_FET_SHADOW_EN); | |
1610 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1611 | if (enable) | |
1612 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1613 | else | |
1614 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1615 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1616 | } | |
1617 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1618 | } | |
1619 | } | |
1620 | ||
6833c043 MC |
1621 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1622 | { | |
1623 | u32 reg; | |
1624 | ||
ecf1410b | 1625 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
0a58d668 | 1626 | ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
f07e9af3 | 1627 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1628 | return; |
1629 | ||
f07e9af3 | 1630 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1631 | tg3_phy_fet_toggle_apd(tp, enable); |
1632 | return; | |
1633 | } | |
1634 | ||
6833c043 MC |
1635 | reg = MII_TG3_MISC_SHDW_WREN | |
1636 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1637 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1638 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1639 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1640 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1641 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1642 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1643 | ||
1644 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1645 | ||
1646 | ||
1647 | reg = MII_TG3_MISC_SHDW_WREN | | |
1648 | MII_TG3_MISC_SHDW_APD_SEL | | |
1649 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1650 | if (enable) | |
1651 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1652 | ||
1653 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1654 | } | |
1655 | ||
9ef8ca99 MC |
1656 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1657 | { | |
1658 | u32 phy; | |
1659 | ||
1660 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
f07e9af3 | 1661 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
1662 | return; |
1663 | ||
f07e9af3 | 1664 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
1665 | u32 ephy; |
1666 | ||
535ef6e1 MC |
1667 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1668 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1669 | ||
1670 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1671 | ephy | MII_TG3_FET_SHADOW_EN); | |
1672 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1673 | if (enable) |
535ef6e1 | 1674 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1675 | else |
535ef6e1 MC |
1676 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1677 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1678 | } |
535ef6e1 | 1679 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1680 | } |
1681 | } else { | |
1682 | phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | | |
1683 | MII_TG3_AUXCTL_SHDWSEL_MISC; | |
1684 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) && | |
1685 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) { | |
1686 | if (enable) | |
1687 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1688 | else | |
1689 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1690 | phy |= MII_TG3_AUXCTL_MISC_WREN; | |
1691 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1692 | } | |
1693 | } | |
1694 | } | |
1695 | ||
1da177e4 LT |
1696 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1697 | { | |
1698 | u32 val; | |
1699 | ||
f07e9af3 | 1700 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
1701 | return; |
1702 | ||
1703 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) && | |
1704 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) | |
1705 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1706 | (val | (1 << 15) | (1 << 4))); | |
1707 | } | |
1708 | ||
b2a5c19c MC |
1709 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1710 | { | |
1711 | u32 otp, phy; | |
1712 | ||
1713 | if (!tp->phy_otp) | |
1714 | return; | |
1715 | ||
1716 | otp = tp->phy_otp; | |
1717 | ||
1718 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1719 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1720 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1721 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1722 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1723 | ||
1724 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1725 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1726 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1727 | ||
1728 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1729 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1730 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1731 | ||
1732 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1733 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1734 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1735 | ||
1736 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1737 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1738 | ||
1739 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1740 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1741 | ||
1742 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1743 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1744 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1745 | ||
1746 | /* Turn off SM_DSP clock. */ | |
1747 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1748 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1749 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1750 | } | |
1751 | ||
52b02d04 MC |
1752 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
1753 | { | |
1754 | u32 val; | |
1755 | ||
1756 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
1757 | return; | |
1758 | ||
1759 | tp->setlpicnt = 0; | |
1760 | ||
1761 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
1762 | current_link_up == 1 && | |
a6b68dab MC |
1763 | tp->link_config.active_duplex == DUPLEX_FULL && |
1764 | (tp->link_config.active_speed == SPEED_100 || | |
1765 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
1766 | u32 eeectl; |
1767 | ||
1768 | if (tp->link_config.active_speed == SPEED_1000) | |
1769 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
1770 | else | |
1771 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
1772 | ||
1773 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
1774 | ||
3110f5f5 MC |
1775 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
1776 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 1777 | |
21a00ab2 MC |
1778 | switch (val) { |
1779 | case TG3_CL45_D7_EEERES_STAT_LP_1000T: | |
1780 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { | |
1781 | case ASIC_REV_5717: | |
1782 | case ASIC_REV_5719: | |
1783 | case ASIC_REV_57765: | |
1784 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1785 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1786 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1787 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1788 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
1789 | ||
1790 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | |
1791 | ||
1792 | /* Turn off SM_DSP clock. */ | |
1793 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1794 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1795 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
1796 | } | |
1797 | /* Fallthrough */ | |
1798 | case TG3_CL45_D7_EEERES_STAT_LP_100TX: | |
52b02d04 | 1799 | tp->setlpicnt = 2; |
21a00ab2 | 1800 | } |
52b02d04 MC |
1801 | } |
1802 | ||
1803 | if (!tp->setlpicnt) { | |
1804 | val = tr32(TG3_CPMU_EEE_MODE); | |
1805 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
1806 | } | |
1807 | } | |
1808 | ||
1da177e4 LT |
1809 | static int tg3_wait_macro_done(struct tg3 *tp) |
1810 | { | |
1811 | int limit = 100; | |
1812 | ||
1813 | while (limit--) { | |
1814 | u32 tmp32; | |
1815 | ||
f08aa1a8 | 1816 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
1817 | if ((tmp32 & 0x1000) == 0) |
1818 | break; | |
1819 | } | |
1820 | } | |
d4675b52 | 1821 | if (limit < 0) |
1da177e4 LT |
1822 | return -EBUSY; |
1823 | ||
1824 | return 0; | |
1825 | } | |
1826 | ||
1827 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1828 | { | |
1829 | static const u32 test_pat[4][6] = { | |
1830 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1831 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1832 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1833 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1834 | }; | |
1835 | int chan; | |
1836 | ||
1837 | for (chan = 0; chan < 4; chan++) { | |
1838 | int i; | |
1839 | ||
1840 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1841 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1842 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1843 | |
1844 | for (i = 0; i < 6; i++) | |
1845 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1846 | test_pat[chan][i]); | |
1847 | ||
f08aa1a8 | 1848 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1849 | if (tg3_wait_macro_done(tp)) { |
1850 | *resetp = 1; | |
1851 | return -EBUSY; | |
1852 | } | |
1853 | ||
1854 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1855 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1856 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
1857 | if (tg3_wait_macro_done(tp)) { |
1858 | *resetp = 1; | |
1859 | return -EBUSY; | |
1860 | } | |
1861 | ||
f08aa1a8 | 1862 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
1863 | if (tg3_wait_macro_done(tp)) { |
1864 | *resetp = 1; | |
1865 | return -EBUSY; | |
1866 | } | |
1867 | ||
1868 | for (i = 0; i < 6; i += 2) { | |
1869 | u32 low, high; | |
1870 | ||
1871 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1872 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1873 | tg3_wait_macro_done(tp)) { | |
1874 | *resetp = 1; | |
1875 | return -EBUSY; | |
1876 | } | |
1877 | low &= 0x7fff; | |
1878 | high &= 0x000f; | |
1879 | if (low != test_pat[chan][i] || | |
1880 | high != test_pat[chan][i+1]) { | |
1881 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1882 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1883 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1884 | ||
1885 | return -EBUSY; | |
1886 | } | |
1887 | } | |
1888 | } | |
1889 | ||
1890 | return 0; | |
1891 | } | |
1892 | ||
1893 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1894 | { | |
1895 | int chan; | |
1896 | ||
1897 | for (chan = 0; chan < 4; chan++) { | |
1898 | int i; | |
1899 | ||
1900 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1901 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1902 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1903 | for (i = 0; i < 6; i++) |
1904 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 1905 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1906 | if (tg3_wait_macro_done(tp)) |
1907 | return -EBUSY; | |
1908 | } | |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
1913 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1914 | { | |
1915 | u32 reg32, phy9_orig; | |
1916 | int retries, do_phy_reset, err; | |
1917 | ||
1918 | retries = 10; | |
1919 | do_phy_reset = 1; | |
1920 | do { | |
1921 | if (do_phy_reset) { | |
1922 | err = tg3_bmcr_reset(tp); | |
1923 | if (err) | |
1924 | return err; | |
1925 | do_phy_reset = 0; | |
1926 | } | |
1927 | ||
1928 | /* Disable transmitter and interrupt. */ | |
1929 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1930 | continue; | |
1931 | ||
1932 | reg32 |= 0x3000; | |
1933 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1934 | ||
1935 | /* Set full-duplex, 1000 mbps. */ | |
1936 | tg3_writephy(tp, MII_BMCR, | |
1937 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1938 | ||
1939 | /* Set to master mode. */ | |
1940 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1941 | continue; | |
1942 | ||
1943 | tg3_writephy(tp, MII_TG3_CTRL, | |
1944 | (MII_TG3_CTRL_AS_MASTER | | |
1945 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1946 | ||
1947 | /* Enable SM_DSP_CLOCK and 6dB. */ | |
1948 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1949 | ||
1950 | /* Block the PHY control access. */ | |
6ee7c0a0 | 1951 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
1952 | |
1953 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
1954 | if (!err) | |
1955 | break; | |
1956 | } while (--retries); | |
1957 | ||
1958 | err = tg3_phy_reset_chanpat(tp); | |
1959 | if (err) | |
1960 | return err; | |
1961 | ||
6ee7c0a0 | 1962 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
1963 | |
1964 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 1965 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 LT |
1966 | |
1967 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1968 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
1969 | /* Set Extended packet length bit for jumbo frames */ | |
1970 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); | |
859a5887 | 1971 | } else { |
1da177e4 LT |
1972 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
1973 | } | |
1974 | ||
1975 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
1976 | ||
1977 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
1978 | reg32 &= ~0x3000; | |
1979 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1980 | } else if (!err) | |
1981 | err = -EBUSY; | |
1982 | ||
1983 | return err; | |
1984 | } | |
1985 | ||
1986 | /* This will reset the tigon3 PHY if there is no valid | |
1987 | * link unless the FORCE argument is non-zero. | |
1988 | */ | |
1989 | static int tg3_phy_reset(struct tg3 *tp) | |
1990 | { | |
f833c4c1 | 1991 | u32 val, cpmuctrl; |
1da177e4 LT |
1992 | int err; |
1993 | ||
60189ddf | 1994 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
1995 | val = tr32(GRC_MISC_CFG); |
1996 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
1997 | udelay(40); | |
1998 | } | |
f833c4c1 MC |
1999 | err = tg3_readphy(tp, MII_BMSR, &val); |
2000 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
2001 | if (err != 0) |
2002 | return -EBUSY; | |
2003 | ||
c8e1e82b MC |
2004 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
2005 | netif_carrier_off(tp->dev); | |
2006 | tg3_link_report(tp); | |
2007 | } | |
2008 | ||
1da177e4 LT |
2009 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2010 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2011 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2012 | err = tg3_phy_reset_5703_4_5(tp); | |
2013 | if (err) | |
2014 | return err; | |
2015 | goto out; | |
2016 | } | |
2017 | ||
b2a5c19c MC |
2018 | cpmuctrl = 0; |
2019 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2020 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2021 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2022 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2023 | tw32(TG3_CPMU_CTRL, | |
2024 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2025 | } | |
2026 | ||
1da177e4 LT |
2027 | err = tg3_bmcr_reset(tp); |
2028 | if (err) | |
2029 | return err; | |
2030 | ||
b2a5c19c | 2031 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2032 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2033 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2034 | |
2035 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2036 | } | |
2037 | ||
bcb37f6c MC |
2038 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2039 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2040 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2041 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2042 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2043 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2044 | udelay(40); | |
2045 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2046 | } | |
2047 | } | |
2048 | ||
0a58d668 | 2049 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
f07e9af3 | 2050 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2051 | return 0; |
2052 | ||
b2a5c19c MC |
2053 | tg3_phy_apply_otp(tp); |
2054 | ||
f07e9af3 | 2055 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2056 | tg3_phy_toggle_apd(tp, true); |
2057 | else | |
2058 | tg3_phy_toggle_apd(tp, false); | |
2059 | ||
1da177e4 | 2060 | out: |
f07e9af3 | 2061 | if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) { |
1da177e4 | 2062 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
6ee7c0a0 MC |
2063 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2064 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1da177e4 LT |
2065 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
2066 | } | |
f07e9af3 | 2067 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2068 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2069 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2070 | } |
f07e9af3 | 2071 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1da177e4 | 2072 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
6ee7c0a0 MC |
2073 | tg3_phydsp_write(tp, 0x000a, 0x310b); |
2074 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2075 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
1da177e4 | 2076 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
f07e9af3 | 2077 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
c424cb24 MC |
2078 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
2079 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
f07e9af3 | 2080 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { |
c1d2a196 MC |
2081 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); |
2082 | tg3_writephy(tp, MII_TG3_TEST1, | |
2083 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2084 | } else | |
2085 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
c424cb24 MC |
2086 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
2087 | } | |
1da177e4 LT |
2088 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2089 | /* support jumbo frames */ | |
79eb6904 | 2090 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
2091 | /* Cannot do read-modify-write on 5401 */ |
2092 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
8f666b07 | 2093 | } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 LT |
2094 | /* Set bit 14 with read-modify-write to preserve other bits */ |
2095 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) && | |
f833c4c1 MC |
2096 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) |
2097 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000); | |
1da177e4 LT |
2098 | } |
2099 | ||
2100 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2101 | * jumbo frames transmission. | |
2102 | */ | |
8f666b07 | 2103 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
f833c4c1 | 2104 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2105 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2106 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2107 | } |
2108 | ||
715116a1 | 2109 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2110 | /* adjust output voltage */ |
535ef6e1 | 2111 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2112 | } |
2113 | ||
9ef8ca99 | 2114 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2115 | tg3_phy_set_wirespeed(tp); |
2116 | return 0; | |
2117 | } | |
2118 | ||
2119 | static void tg3_frob_aux_power(struct tg3 *tp) | |
2120 | { | |
683644b7 | 2121 | bool need_vaux = false; |
1da177e4 | 2122 | |
334355aa MC |
2123 | /* The GPIOs do something completely different on 57765. */ |
2124 | if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 || | |
a50d0796 | 2125 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
334355aa | 2126 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
1da177e4 LT |
2127 | return; |
2128 | ||
683644b7 MC |
2129 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
2130 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
d78b59f5 MC |
2131 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2132 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) && | |
683644b7 | 2133 | tp->pdev_peer != tp->pdev) { |
8c2dc7e1 MC |
2134 | struct net_device *dev_peer; |
2135 | ||
2136 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2137 | |
bc1c7567 | 2138 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2139 | if (dev_peer) { |
2140 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2141 | ||
2142 | if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) | |
2143 | return; | |
2144 | ||
2145 | if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) || | |
2146 | (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
2147 | need_vaux = true; | |
2148 | } | |
1da177e4 LT |
2149 | } |
2150 | ||
683644b7 MC |
2151 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) || |
2152 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
2153 | need_vaux = true; | |
2154 | ||
2155 | if (need_vaux) { | |
1da177e4 LT |
2156 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2157 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
b401e9e2 MC |
2158 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2159 | (GRC_LCLCTRL_GPIO_OE0 | | |
2160 | GRC_LCLCTRL_GPIO_OE1 | | |
2161 | GRC_LCLCTRL_GPIO_OE2 | | |
2162 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2163 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2164 | 100); | |
8d519ab2 MC |
2165 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
2166 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
2167 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ |
2168 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2169 | GRC_LCLCTRL_GPIO_OE1 | | |
2170 | GRC_LCLCTRL_GPIO_OE2 | | |
2171 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2172 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2173 | tp->grc_local_ctrl; | |
2174 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2175 | ||
2176 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2177 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2178 | ||
2179 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2180 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1da177e4 LT |
2181 | } else { |
2182 | u32 no_gpio2; | |
dc56b7d4 | 2183 | u32 grc_local_ctrl = 0; |
1da177e4 | 2184 | |
dc56b7d4 MC |
2185 | /* Workaround to prevent overdrawing Amps. */ |
2186 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2187 | ASIC_REV_5714) { | |
2188 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
b401e9e2 MC |
2189 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2190 | grc_local_ctrl, 100); | |
dc56b7d4 MC |
2191 | } |
2192 | ||
1da177e4 LT |
2193 | /* On 5753 and variants, GPIO2 cannot be used. */ |
2194 | no_gpio2 = tp->nic_sram_data_cfg & | |
2195 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2196 | ||
dc56b7d4 | 2197 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | |
1da177e4 LT |
2198 | GRC_LCLCTRL_GPIO_OE1 | |
2199 | GRC_LCLCTRL_GPIO_OE2 | | |
2200 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2201 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2202 | if (no_gpio2) { | |
2203 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2204 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2205 | } | |
b401e9e2 MC |
2206 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2207 | grc_local_ctrl, 100); | |
1da177e4 LT |
2208 | |
2209 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2210 | ||
b401e9e2 MC |
2211 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2212 | grc_local_ctrl, 100); | |
1da177e4 LT |
2213 | |
2214 | if (!no_gpio2) { | |
2215 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
b401e9e2 MC |
2216 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2217 | grc_local_ctrl, 100); | |
1da177e4 LT |
2218 | } |
2219 | } | |
2220 | } else { | |
2221 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2222 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
b401e9e2 MC |
2223 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2224 | (GRC_LCLCTRL_GPIO_OE1 | | |
2225 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 | 2226 | |
b401e9e2 MC |
2227 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2228 | GRC_LCLCTRL_GPIO_OE1, 100); | |
1da177e4 | 2229 | |
b401e9e2 MC |
2230 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2231 | (GRC_LCLCTRL_GPIO_OE1 | | |
2232 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 LT |
2233 | } |
2234 | } | |
2235 | } | |
2236 | ||
e8f3f6ca MC |
2237 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2238 | { | |
2239 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2240 | return 1; | |
79eb6904 | 2241 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2242 | if (speed != SPEED_10) |
2243 | return 1; | |
2244 | } else if (speed == SPEED_10) | |
2245 | return 1; | |
2246 | ||
2247 | return 0; | |
2248 | } | |
2249 | ||
1da177e4 LT |
2250 | static int tg3_setup_phy(struct tg3 *, int); |
2251 | ||
2252 | #define RESET_KIND_SHUTDOWN 0 | |
2253 | #define RESET_KIND_INIT 1 | |
2254 | #define RESET_KIND_SUSPEND 2 | |
2255 | ||
2256 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2257 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2258 | ||
0a459aac | 2259 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2260 | { |
ce057f01 MC |
2261 | u32 val; |
2262 | ||
f07e9af3 | 2263 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2264 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2265 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2266 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2267 | ||
2268 | sg_dig_ctrl |= | |
2269 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2270 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2271 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2272 | } | |
3f7045c1 | 2273 | return; |
5129724a | 2274 | } |
3f7045c1 | 2275 | |
60189ddf | 2276 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2277 | tg3_bmcr_reset(tp); |
2278 | val = tr32(GRC_MISC_CFG); | |
2279 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2280 | udelay(40); | |
2281 | return; | |
f07e9af3 | 2282 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2283 | u32 phytest; |
2284 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2285 | u32 phy; | |
2286 | ||
2287 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2288 | tg3_writephy(tp, MII_BMCR, | |
2289 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2290 | ||
2291 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2292 | phytest | MII_TG3_FET_SHADOW_EN); | |
2293 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2294 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2295 | tg3_writephy(tp, | |
2296 | MII_TG3_FET_SHDW_AUXMODE4, | |
2297 | phy); | |
2298 | } | |
2299 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2300 | } | |
2301 | return; | |
0a459aac | 2302 | } else if (do_low_power) { |
715116a1 MC |
2303 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2304 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac MC |
2305 | |
2306 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
2307 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL | | |
2308 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2309 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2310 | MII_TG3_AUXCTL_PCTL_VREG_11V); | |
715116a1 | 2311 | } |
3f7045c1 | 2312 | |
15c3b696 MC |
2313 | /* The PHY should not be powered down on some chips because |
2314 | * of bugs. | |
2315 | */ | |
2316 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2317 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2318 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
f07e9af3 | 2319 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
15c3b696 | 2320 | return; |
ce057f01 | 2321 | |
bcb37f6c MC |
2322 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2323 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2324 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2325 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2326 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2327 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2328 | } | |
2329 | ||
15c3b696 MC |
2330 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2331 | } | |
2332 | ||
ffbcfed4 MC |
2333 | /* tp->lock is held. */ |
2334 | static int tg3_nvram_lock(struct tg3 *tp) | |
2335 | { | |
2336 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2337 | int i; | |
2338 | ||
2339 | if (tp->nvram_lock_cnt == 0) { | |
2340 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2341 | for (i = 0; i < 8000; i++) { | |
2342 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2343 | break; | |
2344 | udelay(20); | |
2345 | } | |
2346 | if (i == 8000) { | |
2347 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2348 | return -ENODEV; | |
2349 | } | |
2350 | } | |
2351 | tp->nvram_lock_cnt++; | |
2352 | } | |
2353 | return 0; | |
2354 | } | |
2355 | ||
2356 | /* tp->lock is held. */ | |
2357 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2358 | { | |
2359 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2360 | if (tp->nvram_lock_cnt > 0) | |
2361 | tp->nvram_lock_cnt--; | |
2362 | if (tp->nvram_lock_cnt == 0) | |
2363 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2364 | } | |
2365 | } | |
2366 | ||
2367 | /* tp->lock is held. */ | |
2368 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2369 | { | |
2370 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2371 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2372 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2373 | ||
2374 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2375 | } | |
2376 | } | |
2377 | ||
2378 | /* tp->lock is held. */ | |
2379 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2380 | { | |
2381 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2382 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2383 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2384 | ||
2385 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2386 | } | |
2387 | } | |
2388 | ||
2389 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2390 | u32 offset, u32 *val) | |
2391 | { | |
2392 | u32 tmp; | |
2393 | int i; | |
2394 | ||
2395 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2396 | return -EINVAL; | |
2397 | ||
2398 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2399 | EEPROM_ADDR_DEVID_MASK | | |
2400 | EEPROM_ADDR_READ); | |
2401 | tw32(GRC_EEPROM_ADDR, | |
2402 | tmp | | |
2403 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2404 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2405 | EEPROM_ADDR_ADDR_MASK) | | |
2406 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2407 | ||
2408 | for (i = 0; i < 1000; i++) { | |
2409 | tmp = tr32(GRC_EEPROM_ADDR); | |
2410 | ||
2411 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2412 | break; | |
2413 | msleep(1); | |
2414 | } | |
2415 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2416 | return -EBUSY; | |
2417 | ||
62cedd11 MC |
2418 | tmp = tr32(GRC_EEPROM_DATA); |
2419 | ||
2420 | /* | |
2421 | * The data will always be opposite the native endian | |
2422 | * format. Perform a blind byteswap to compensate. | |
2423 | */ | |
2424 | *val = swab32(tmp); | |
2425 | ||
ffbcfed4 MC |
2426 | return 0; |
2427 | } | |
2428 | ||
2429 | #define NVRAM_CMD_TIMEOUT 10000 | |
2430 | ||
2431 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2432 | { | |
2433 | int i; | |
2434 | ||
2435 | tw32(NVRAM_CMD, nvram_cmd); | |
2436 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2437 | udelay(10); | |
2438 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2439 | udelay(10); | |
2440 | break; | |
2441 | } | |
2442 | } | |
2443 | ||
2444 | if (i == NVRAM_CMD_TIMEOUT) | |
2445 | return -EBUSY; | |
2446 | ||
2447 | return 0; | |
2448 | } | |
2449 | ||
2450 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2451 | { | |
2452 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2453 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2454 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2455 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2456 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2457 | ||
2458 | addr = ((addr / tp->nvram_pagesize) << | |
2459 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2460 | (addr % tp->nvram_pagesize); | |
2461 | ||
2462 | return addr; | |
2463 | } | |
2464 | ||
2465 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2466 | { | |
2467 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2468 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2469 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2470 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2471 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2472 | ||
2473 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2474 | tp->nvram_pagesize) + | |
2475 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2476 | ||
2477 | return addr; | |
2478 | } | |
2479 | ||
e4f34110 MC |
2480 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2481 | * the byteswapping settings for all other register accesses. | |
2482 | * tg3 devices are BE devices, so on a BE machine, the data | |
2483 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2484 | * machine, the 32-bit value will be byteswapped. | |
2485 | */ | |
ffbcfed4 MC |
2486 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2487 | { | |
2488 | int ret; | |
2489 | ||
2490 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | |
2491 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
2492 | ||
2493 | offset = tg3_nvram_phys_addr(tp, offset); | |
2494 | ||
2495 | if (offset > NVRAM_ADDR_MSK) | |
2496 | return -EINVAL; | |
2497 | ||
2498 | ret = tg3_nvram_lock(tp); | |
2499 | if (ret) | |
2500 | return ret; | |
2501 | ||
2502 | tg3_enable_nvram_access(tp); | |
2503 | ||
2504 | tw32(NVRAM_ADDR, offset); | |
2505 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2506 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2507 | ||
2508 | if (ret == 0) | |
e4f34110 | 2509 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2510 | |
2511 | tg3_disable_nvram_access(tp); | |
2512 | ||
2513 | tg3_nvram_unlock(tp); | |
2514 | ||
2515 | return ret; | |
2516 | } | |
2517 | ||
a9dc529d MC |
2518 | /* Ensures NVRAM data is in bytestream format. */ |
2519 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2520 | { |
2521 | u32 v; | |
a9dc529d | 2522 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2523 | if (!res) |
a9dc529d | 2524 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2525 | return res; |
2526 | } | |
2527 | ||
3f007891 MC |
2528 | /* tp->lock is held. */ |
2529 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2530 | { | |
2531 | u32 addr_high, addr_low; | |
2532 | int i; | |
2533 | ||
2534 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2535 | tp->dev->dev_addr[1]); | |
2536 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2537 | (tp->dev->dev_addr[3] << 16) | | |
2538 | (tp->dev->dev_addr[4] << 8) | | |
2539 | (tp->dev->dev_addr[5] << 0)); | |
2540 | for (i = 0; i < 4; i++) { | |
2541 | if (i == 1 && skip_mac_1) | |
2542 | continue; | |
2543 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2544 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2545 | } | |
2546 | ||
2547 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2548 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2549 | for (i = 0; i < 12; i++) { | |
2550 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2551 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2552 | } | |
2553 | } | |
2554 | ||
2555 | addr_high = (tp->dev->dev_addr[0] + | |
2556 | tp->dev->dev_addr[1] + | |
2557 | tp->dev->dev_addr[2] + | |
2558 | tp->dev->dev_addr[3] + | |
2559 | tp->dev->dev_addr[4] + | |
2560 | tp->dev->dev_addr[5]) & | |
2561 | TX_BACKOFF_SEED_MASK; | |
2562 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2563 | } | |
2564 | ||
c866b7ea | 2565 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 2566 | { |
c866b7ea RW |
2567 | /* |
2568 | * Make sure register accesses (indirect or otherwise) will function | |
2569 | * correctly. | |
1da177e4 LT |
2570 | */ |
2571 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
2572 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
2573 | } | |
1da177e4 | 2574 | |
c866b7ea RW |
2575 | static int tg3_power_up(struct tg3 *tp) |
2576 | { | |
2577 | tg3_enable_register_access(tp); | |
8c6bda1a | 2578 | |
c866b7ea | 2579 | pci_set_power_state(tp->pdev, PCI_D0); |
1da177e4 | 2580 | |
c866b7ea RW |
2581 | /* Switch out of Vaux if it is a NIC */ |
2582 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
2583 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); | |
1da177e4 | 2584 | |
c866b7ea RW |
2585 | return 0; |
2586 | } | |
1da177e4 | 2587 | |
c866b7ea RW |
2588 | static int tg3_power_down_prepare(struct tg3 *tp) |
2589 | { | |
2590 | u32 misc_host_ctrl; | |
2591 | bool device_should_wake, do_low_power; | |
2592 | ||
2593 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
2594 | |
2595 | /* Restore the CLKREQ setting. */ | |
2596 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2597 | u16 lnkctl; | |
2598 | ||
2599 | pci_read_config_word(tp->pdev, | |
2600 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2601 | &lnkctl); | |
2602 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2603 | pci_write_config_word(tp->pdev, | |
2604 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2605 | lnkctl); | |
2606 | } | |
2607 | ||
1da177e4 LT |
2608 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2609 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2610 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2611 | ||
c866b7ea | 2612 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
05ac4cb7 MC |
2613 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
2614 | ||
dd477003 | 2615 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
0a459aac | 2616 | do_low_power = false; |
f07e9af3 | 2617 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 2618 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 2619 | struct phy_device *phydev; |
0a459aac | 2620 | u32 phyid, advertising; |
b02fd9e3 | 2621 | |
3f0e3ad7 | 2622 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 2623 | |
80096068 | 2624 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 MC |
2625 | |
2626 | tp->link_config.orig_speed = phydev->speed; | |
2627 | tp->link_config.orig_duplex = phydev->duplex; | |
2628 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2629 | tp->link_config.orig_advertising = phydev->advertising; | |
2630 | ||
2631 | advertising = ADVERTISED_TP | | |
2632 | ADVERTISED_Pause | | |
2633 | ADVERTISED_Autoneg | | |
2634 | ADVERTISED_10baseT_Half; | |
2635 | ||
2636 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
05ac4cb7 | 2637 | device_should_wake) { |
b02fd9e3 MC |
2638 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) |
2639 | advertising |= | |
2640 | ADVERTISED_100baseT_Half | | |
2641 | ADVERTISED_100baseT_Full | | |
2642 | ADVERTISED_10baseT_Full; | |
2643 | else | |
2644 | advertising |= ADVERTISED_10baseT_Full; | |
2645 | } | |
2646 | ||
2647 | phydev->advertising = advertising; | |
2648 | ||
2649 | phy_start_aneg(phydev); | |
0a459aac MC |
2650 | |
2651 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
2652 | if (phyid != PHY_ID_BCMAC131) { |
2653 | phyid &= PHY_BCM_OUI_MASK; | |
2654 | if (phyid == PHY_BCM_OUI_1 || | |
2655 | phyid == PHY_BCM_OUI_2 || | |
2656 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
2657 | do_low_power = true; |
2658 | } | |
b02fd9e3 | 2659 | } |
dd477003 | 2660 | } else { |
2023276e | 2661 | do_low_power = true; |
0a459aac | 2662 | |
80096068 MC |
2663 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
2664 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
2665 | tp->link_config.orig_speed = tp->link_config.speed; |
2666 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2667 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2668 | } | |
1da177e4 | 2669 | |
f07e9af3 | 2670 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
dd477003 MC |
2671 | tp->link_config.speed = SPEED_10; |
2672 | tp->link_config.duplex = DUPLEX_HALF; | |
2673 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2674 | tg3_setup_phy(tp, 0); | |
2675 | } | |
1da177e4 LT |
2676 | } |
2677 | ||
b5d3772c MC |
2678 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2679 | u32 val; | |
2680 | ||
2681 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2682 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2683 | } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
6921d201 MC |
2684 | int i; |
2685 | u32 val; | |
2686 | ||
2687 | for (i = 0; i < 200; i++) { | |
2688 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2689 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2690 | break; | |
2691 | msleep(1); | |
2692 | } | |
2693 | } | |
a85feb8c GZ |
2694 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
2695 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2696 | WOL_DRV_STATE_SHUTDOWN | | |
2697 | WOL_DRV_WOL | | |
2698 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2699 | |
05ac4cb7 | 2700 | if (device_should_wake) { |
1da177e4 LT |
2701 | u32 mac_mode; |
2702 | ||
f07e9af3 | 2703 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
0a459aac | 2704 | if (do_low_power) { |
dd477003 MC |
2705 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); |
2706 | udelay(40); | |
2707 | } | |
1da177e4 | 2708 | |
f07e9af3 | 2709 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
2710 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
2711 | else | |
2712 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2713 | |
e8f3f6ca MC |
2714 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2715 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2716 | ASIC_REV_5700) { | |
2717 | u32 speed = (tp->tg3_flags & | |
2718 | TG3_FLAG_WOL_SPEED_100MB) ? | |
2719 | SPEED_100 : SPEED_10; | |
2720 | if (tg3_5700_link_polarity(tp, speed)) | |
2721 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2722 | else | |
2723 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2724 | } | |
1da177e4 LT |
2725 | } else { |
2726 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2727 | } | |
2728 | ||
cbf46853 | 2729 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) |
1da177e4 LT |
2730 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2731 | ||
05ac4cb7 MC |
2732 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
2733 | if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
2734 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && | |
2735 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2736 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))) | |
2737 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
1da177e4 | 2738 | |
d2394e6b MC |
2739 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
2740 | mac_mode |= MAC_MODE_APE_TX_EN | | |
2741 | MAC_MODE_APE_RX_EN | | |
2742 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 2743 | |
1da177e4 LT |
2744 | tw32_f(MAC_MODE, mac_mode); |
2745 | udelay(100); | |
2746 | ||
2747 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2748 | udelay(10); | |
2749 | } | |
2750 | ||
2751 | if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && | |
2752 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2753 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2754 | u32 base_val; | |
2755 | ||
2756 | base_val = tp->pci_clock_ctrl; | |
2757 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2758 | CLOCK_CTRL_TXCLK_DISABLE); | |
2759 | ||
b401e9e2 MC |
2760 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2761 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
d7b0a857 | 2762 | } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
795d01c5 | 2763 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
d7b0a857 | 2764 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { |
4cf78e4f | 2765 | /* do nothing */ |
85e94ced | 2766 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
1da177e4 LT |
2767 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { |
2768 | u32 newbits1, newbits2; | |
2769 | ||
2770 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2771 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2772 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2773 | CLOCK_CTRL_TXCLK_DISABLE | | |
2774 | CLOCK_CTRL_ALTCLK); | |
2775 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2776 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
2777 | newbits1 = CLOCK_CTRL_625_CORE; | |
2778 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2779 | } else { | |
2780 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2781 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2782 | } | |
2783 | ||
b401e9e2 MC |
2784 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2785 | 40); | |
1da177e4 | 2786 | |
b401e9e2 MC |
2787 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2788 | 40); | |
1da177e4 LT |
2789 | |
2790 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
2791 | u32 newbits3; | |
2792 | ||
2793 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2794 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2795 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2796 | CLOCK_CTRL_TXCLK_DISABLE | | |
2797 | CLOCK_CTRL_44MHZ_CORE); | |
2798 | } else { | |
2799 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2800 | } | |
2801 | ||
b401e9e2 MC |
2802 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
2803 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
2804 | } |
2805 | } | |
2806 | ||
05ac4cb7 | 2807 | if (!(device_should_wake) && |
22435849 | 2808 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
0a459aac | 2809 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 2810 | |
1da177e4 LT |
2811 | tg3_frob_aux_power(tp); |
2812 | ||
2813 | /* Workaround for unstable PLL clock */ | |
2814 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2815 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2816 | u32 val = tr32(0x7d00); | |
2817 | ||
2818 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2819 | tw32(0x7d00, val); | |
6921d201 | 2820 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
ec41c7df MC |
2821 | int err; |
2822 | ||
2823 | err = tg3_nvram_lock(tp); | |
1da177e4 | 2824 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
2825 | if (!err) |
2826 | tg3_nvram_unlock(tp); | |
6921d201 | 2827 | } |
1da177e4 LT |
2828 | } |
2829 | ||
bbadf503 MC |
2830 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
2831 | ||
c866b7ea RW |
2832 | return 0; |
2833 | } | |
12dac075 | 2834 | |
c866b7ea RW |
2835 | static void tg3_power_down(struct tg3 *tp) |
2836 | { | |
2837 | tg3_power_down_prepare(tp); | |
1da177e4 | 2838 | |
c866b7ea RW |
2839 | pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
2840 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
1da177e4 LT |
2841 | } |
2842 | ||
1da177e4 LT |
2843 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
2844 | { | |
2845 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2846 | case MII_TG3_AUX_STAT_10HALF: | |
2847 | *speed = SPEED_10; | |
2848 | *duplex = DUPLEX_HALF; | |
2849 | break; | |
2850 | ||
2851 | case MII_TG3_AUX_STAT_10FULL: | |
2852 | *speed = SPEED_10; | |
2853 | *duplex = DUPLEX_FULL; | |
2854 | break; | |
2855 | ||
2856 | case MII_TG3_AUX_STAT_100HALF: | |
2857 | *speed = SPEED_100; | |
2858 | *duplex = DUPLEX_HALF; | |
2859 | break; | |
2860 | ||
2861 | case MII_TG3_AUX_STAT_100FULL: | |
2862 | *speed = SPEED_100; | |
2863 | *duplex = DUPLEX_FULL; | |
2864 | break; | |
2865 | ||
2866 | case MII_TG3_AUX_STAT_1000HALF: | |
2867 | *speed = SPEED_1000; | |
2868 | *duplex = DUPLEX_HALF; | |
2869 | break; | |
2870 | ||
2871 | case MII_TG3_AUX_STAT_1000FULL: | |
2872 | *speed = SPEED_1000; | |
2873 | *duplex = DUPLEX_FULL; | |
2874 | break; | |
2875 | ||
2876 | default: | |
f07e9af3 | 2877 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
2878 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
2879 | SPEED_10; | |
2880 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2881 | DUPLEX_HALF; | |
2882 | break; | |
2883 | } | |
1da177e4 LT |
2884 | *speed = SPEED_INVALID; |
2885 | *duplex = DUPLEX_INVALID; | |
2886 | break; | |
855e1111 | 2887 | } |
1da177e4 LT |
2888 | } |
2889 | ||
2890 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
2891 | { | |
2892 | u32 new_adv; | |
2893 | int i; | |
2894 | ||
80096068 | 2895 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1da177e4 LT |
2896 | /* Entering low power mode. Disable gigabit and |
2897 | * 100baseT advertisements. | |
2898 | */ | |
2899 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2900 | ||
2901 | new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2902 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
2903 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2904 | new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); | |
2905 | ||
2906 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2907 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
f07e9af3 | 2908 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
1da177e4 LT |
2909 | tp->link_config.advertising &= |
2910 | ~(ADVERTISED_1000baseT_Half | | |
2911 | ADVERTISED_1000baseT_Full); | |
2912 | ||
ba4d07a8 | 2913 | new_adv = ADVERTISE_CSMA; |
1da177e4 LT |
2914 | if (tp->link_config.advertising & ADVERTISED_10baseT_Half) |
2915 | new_adv |= ADVERTISE_10HALF; | |
2916 | if (tp->link_config.advertising & ADVERTISED_10baseT_Full) | |
2917 | new_adv |= ADVERTISE_10FULL; | |
2918 | if (tp->link_config.advertising & ADVERTISED_100baseT_Half) | |
2919 | new_adv |= ADVERTISE_100HALF; | |
2920 | if (tp->link_config.advertising & ADVERTISED_100baseT_Full) | |
2921 | new_adv |= ADVERTISE_100FULL; | |
ba4d07a8 MC |
2922 | |
2923 | new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2924 | ||
1da177e4 LT |
2925 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2926 | ||
2927 | if (tp->link_config.advertising & | |
2928 | (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { | |
2929 | new_adv = 0; | |
2930 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
2931 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2932 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
2933 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
f07e9af3 | 2934 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) && |
1da177e4 LT |
2935 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
2936 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) | |
2937 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2938 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2939 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2940 | } else { | |
2941 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2942 | } | |
2943 | } else { | |
ba4d07a8 MC |
2944 | new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); |
2945 | new_adv |= ADVERTISE_CSMA; | |
2946 | ||
1da177e4 LT |
2947 | /* Asking for a specific link mode. */ |
2948 | if (tp->link_config.speed == SPEED_1000) { | |
1da177e4 LT |
2949 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2950 | ||
2951 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2952 | new_adv = MII_TG3_CTRL_ADV_1000_FULL; | |
2953 | else | |
2954 | new_adv = MII_TG3_CTRL_ADV_1000_HALF; | |
2955 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2956 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2957 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2958 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
1da177e4 | 2959 | } else { |
1da177e4 LT |
2960 | if (tp->link_config.speed == SPEED_100) { |
2961 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2962 | new_adv |= ADVERTISE_100FULL; | |
2963 | else | |
2964 | new_adv |= ADVERTISE_100HALF; | |
2965 | } else { | |
2966 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2967 | new_adv |= ADVERTISE_10FULL; | |
2968 | else | |
2969 | new_adv |= ADVERTISE_10HALF; | |
2970 | } | |
2971 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
ba4d07a8 MC |
2972 | |
2973 | new_adv = 0; | |
1da177e4 | 2974 | } |
ba4d07a8 MC |
2975 | |
2976 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
1da177e4 LT |
2977 | } |
2978 | ||
52b02d04 | 2979 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { |
a6b68dab | 2980 | u32 val; |
52b02d04 MC |
2981 | |
2982 | tw32(TG3_CPMU_EEE_MODE, | |
2983 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
2984 | ||
2985 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
2986 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
2987 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
2988 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
2989 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
2990 | ||
21a00ab2 MC |
2991 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
2992 | case ASIC_REV_5717: | |
2993 | case ASIC_REV_57765: | |
2994 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
2995 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
2996 | MII_TG3_DSP_CH34TP2_HIBW01); | |
2997 | /* Fall through */ | |
2998 | case ASIC_REV_5719: | |
2999 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
3000 | MII_TG3_DSP_TAP26_RMRXSTO | | |
3001 | MII_TG3_DSP_TAP26_OPCSINPT; | |
3002 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
3003 | } | |
52b02d04 | 3004 | |
a6b68dab | 3005 | val = 0; |
52b02d04 MC |
3006 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { |
3007 | /* Advertise 100-BaseTX EEE ability */ | |
3008 | if (tp->link_config.advertising & | |
3110f5f5 MC |
3009 | ADVERTISED_100baseT_Full) |
3010 | val |= MDIO_AN_EEE_ADV_100TX; | |
52b02d04 MC |
3011 | /* Advertise 1000-BaseT EEE ability */ |
3012 | if (tp->link_config.advertising & | |
3110f5f5 MC |
3013 | ADVERTISED_1000baseT_Full) |
3014 | val |= MDIO_AN_EEE_ADV_1000T; | |
52b02d04 | 3015 | } |
3110f5f5 | 3016 | tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); |
52b02d04 MC |
3017 | |
3018 | /* Turn off SM_DSP clock. */ | |
3019 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
3020 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
3021 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
3022 | } | |
3023 | ||
1da177e4 LT |
3024 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
3025 | tp->link_config.speed != SPEED_INVALID) { | |
3026 | u32 bmcr, orig_bmcr; | |
3027 | ||
3028 | tp->link_config.active_speed = tp->link_config.speed; | |
3029 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3030 | ||
3031 | bmcr = 0; | |
3032 | switch (tp->link_config.speed) { | |
3033 | default: | |
3034 | case SPEED_10: | |
3035 | break; | |
3036 | ||
3037 | case SPEED_100: | |
3038 | bmcr |= BMCR_SPEED100; | |
3039 | break; | |
3040 | ||
3041 | case SPEED_1000: | |
3042 | bmcr |= TG3_BMCR_SPEED1000; | |
3043 | break; | |
855e1111 | 3044 | } |
1da177e4 LT |
3045 | |
3046 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3047 | bmcr |= BMCR_FULLDPLX; | |
3048 | ||
3049 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3050 | (bmcr != orig_bmcr)) { | |
3051 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3052 | for (i = 0; i < 1500; i++) { | |
3053 | u32 tmp; | |
3054 | ||
3055 | udelay(10); | |
3056 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3057 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3058 | continue; | |
3059 | if (!(tmp & BMSR_LSTATUS)) { | |
3060 | udelay(40); | |
3061 | break; | |
3062 | } | |
3063 | } | |
3064 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3065 | udelay(40); | |
3066 | } | |
3067 | } else { | |
3068 | tg3_writephy(tp, MII_BMCR, | |
3069 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3070 | } | |
3071 | } | |
3072 | ||
3073 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3074 | { | |
3075 | int err; | |
3076 | ||
3077 | /* Turn off tap power management. */ | |
3078 | /* Set Extended packet length bit */ | |
3079 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
3080 | ||
6ee7c0a0 MC |
3081 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3082 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3083 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3084 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3085 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3086 | |
3087 | udelay(40); | |
3088 | ||
3089 | return err; | |
3090 | } | |
3091 | ||
3600d918 | 3092 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 3093 | { |
3600d918 MC |
3094 | u32 adv_reg, all_mask = 0; |
3095 | ||
3096 | if (mask & ADVERTISED_10baseT_Half) | |
3097 | all_mask |= ADVERTISE_10HALF; | |
3098 | if (mask & ADVERTISED_10baseT_Full) | |
3099 | all_mask |= ADVERTISE_10FULL; | |
3100 | if (mask & ADVERTISED_100baseT_Half) | |
3101 | all_mask |= ADVERTISE_100HALF; | |
3102 | if (mask & ADVERTISED_100baseT_Full) | |
3103 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
3104 | |
3105 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
3106 | return 0; | |
3107 | ||
1da177e4 LT |
3108 | if ((adv_reg & all_mask) != all_mask) |
3109 | return 0; | |
f07e9af3 | 3110 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
3111 | u32 tg3_ctrl; |
3112 | ||
3600d918 MC |
3113 | all_mask = 0; |
3114 | if (mask & ADVERTISED_1000baseT_Half) | |
3115 | all_mask |= ADVERTISE_1000HALF; | |
3116 | if (mask & ADVERTISED_1000baseT_Full) | |
3117 | all_mask |= ADVERTISE_1000FULL; | |
3118 | ||
1da177e4 LT |
3119 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) |
3120 | return 0; | |
3121 | ||
1da177e4 LT |
3122 | if ((tg3_ctrl & all_mask) != all_mask) |
3123 | return 0; | |
3124 | } | |
3125 | return 1; | |
3126 | } | |
3127 | ||
ef167e27 MC |
3128 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
3129 | { | |
3130 | u32 curadv, reqadv; | |
3131 | ||
3132 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3133 | return 1; | |
3134 | ||
3135 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3136 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3137 | ||
3138 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3139 | if (curadv != reqadv) | |
3140 | return 0; | |
3141 | ||
3142 | if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) | |
3143 | tg3_readphy(tp, MII_LPA, rmtadv); | |
3144 | } else { | |
3145 | /* Reprogram the advertisement register, even if it | |
3146 | * does not affect the current link. If the link | |
3147 | * gets renegotiated in the future, we can save an | |
3148 | * additional renegotiation cycle by advertising | |
3149 | * it correctly in the first place. | |
3150 | */ | |
3151 | if (curadv != reqadv) { | |
3152 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3153 | ADVERTISE_PAUSE_ASYM); | |
3154 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3155 | } | |
3156 | } | |
3157 | ||
3158 | return 1; | |
3159 | } | |
3160 | ||
1da177e4 LT |
3161 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3162 | { | |
3163 | int current_link_up; | |
f833c4c1 | 3164 | u32 bmsr, val; |
ef167e27 | 3165 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3166 | u16 current_speed; |
3167 | u8 current_duplex; | |
3168 | int i, err; | |
3169 | ||
3170 | tw32(MAC_EVENT, 0); | |
3171 | ||
3172 | tw32_f(MAC_STATUS, | |
3173 | (MAC_STATUS_SYNC_CHANGED | | |
3174 | MAC_STATUS_CFG_CHANGED | | |
3175 | MAC_STATUS_MI_COMPLETION | | |
3176 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3177 | udelay(40); | |
3178 | ||
8ef21428 MC |
3179 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3180 | tw32_f(MAC_MI_MODE, | |
3181 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3182 | udelay(80); | |
3183 | } | |
1da177e4 LT |
3184 | |
3185 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); | |
3186 | ||
3187 | /* Some third-party PHYs need to be reset on link going | |
3188 | * down. | |
3189 | */ | |
3190 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3191 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3192 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3193 | netif_carrier_ok(tp->dev)) { | |
3194 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3195 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3196 | !(bmsr & BMSR_LSTATUS)) | |
3197 | force_reset = 1; | |
3198 | } | |
3199 | if (force_reset) | |
3200 | tg3_phy_reset(tp); | |
3201 | ||
79eb6904 | 3202 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3203 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3204 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
3205 | !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) | |
3206 | bmsr = 0; | |
3207 | ||
3208 | if (!(bmsr & BMSR_LSTATUS)) { | |
3209 | err = tg3_init_5401phy_dsp(tp); | |
3210 | if (err) | |
3211 | return err; | |
3212 | ||
3213 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3214 | for (i = 0; i < 1000; i++) { | |
3215 | udelay(10); | |
3216 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3217 | (bmsr & BMSR_LSTATUS)) { | |
3218 | udelay(40); | |
3219 | break; | |
3220 | } | |
3221 | } | |
3222 | ||
79eb6904 MC |
3223 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3224 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3225 | !(bmsr & BMSR_LSTATUS) && |
3226 | tp->link_config.active_speed == SPEED_1000) { | |
3227 | err = tg3_phy_reset(tp); | |
3228 | if (!err) | |
3229 | err = tg3_init_5401phy_dsp(tp); | |
3230 | if (err) | |
3231 | return err; | |
3232 | } | |
3233 | } | |
3234 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3235 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3236 | /* 5701 {A0,B0} CRC bug workaround */ | |
3237 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
3238 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
3239 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3240 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
3241 | } |
3242 | ||
3243 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
3244 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
3245 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 3246 | |
f07e9af3 | 3247 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 3248 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 3249 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
3250 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3251 | ||
3252 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3253 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3254 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3255 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3256 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3257 | else | |
3258 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3259 | } | |
3260 | ||
3261 | current_link_up = 0; | |
3262 | current_speed = SPEED_INVALID; | |
3263 | current_duplex = DUPLEX_INVALID; | |
3264 | ||
f07e9af3 | 3265 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
1da177e4 LT |
3266 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007); |
3267 | tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); | |
3268 | if (!(val & (1 << 10))) { | |
3269 | val |= (1 << 10); | |
3270 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
3271 | goto relink; | |
3272 | } | |
3273 | } | |
3274 | ||
3275 | bmsr = 0; | |
3276 | for (i = 0; i < 100; i++) { | |
3277 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3278 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3279 | (bmsr & BMSR_LSTATUS)) | |
3280 | break; | |
3281 | udelay(40); | |
3282 | } | |
3283 | ||
3284 | if (bmsr & BMSR_LSTATUS) { | |
3285 | u32 aux_stat, bmcr; | |
3286 | ||
3287 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3288 | for (i = 0; i < 2000; i++) { | |
3289 | udelay(10); | |
3290 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3291 | aux_stat) | |
3292 | break; | |
3293 | } | |
3294 | ||
3295 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3296 | ¤t_speed, | |
3297 | ¤t_duplex); | |
3298 | ||
3299 | bmcr = 0; | |
3300 | for (i = 0; i < 200; i++) { | |
3301 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3302 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3303 | continue; | |
3304 | if (bmcr && bmcr != 0x7fff) | |
3305 | break; | |
3306 | udelay(10); | |
3307 | } | |
3308 | ||
ef167e27 MC |
3309 | lcl_adv = 0; |
3310 | rmt_adv = 0; | |
1da177e4 | 3311 | |
ef167e27 MC |
3312 | tp->link_config.active_speed = current_speed; |
3313 | tp->link_config.active_duplex = current_duplex; | |
3314 | ||
3315 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3316 | if ((bmcr & BMCR_ANENABLE) && | |
3317 | tg3_copper_is_advertising_all(tp, | |
3318 | tp->link_config.advertising)) { | |
3319 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3320 | &rmt_adv)) | |
3321 | current_link_up = 1; | |
1da177e4 LT |
3322 | } |
3323 | } else { | |
3324 | if (!(bmcr & BMCR_ANENABLE) && | |
3325 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3326 | tp->link_config.duplex == current_duplex && |
3327 | tp->link_config.flowctrl == | |
3328 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3329 | current_link_up = 1; |
1da177e4 LT |
3330 | } |
3331 | } | |
3332 | ||
ef167e27 MC |
3333 | if (current_link_up == 1 && |
3334 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3335 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3336 | } |
3337 | ||
1da177e4 | 3338 | relink: |
80096068 | 3339 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
3340 | tg3_phy_copper_begin(tp); |
3341 | ||
f833c4c1 MC |
3342 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3343 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3344 | (bmsr & BMSR_LSTATUS)) | |
1da177e4 LT |
3345 | current_link_up = 1; |
3346 | } | |
3347 | ||
3348 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3349 | if (current_link_up == 1) { | |
3350 | if (tp->link_config.active_speed == SPEED_100 || | |
3351 | tp->link_config.active_speed == SPEED_10) | |
3352 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3353 | else | |
3354 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 3355 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
3356 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
3357 | else | |
1da177e4 LT |
3358 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3359 | ||
3360 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3361 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3362 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3363 | ||
1da177e4 | 3364 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3365 | if (current_link_up == 1 && |
3366 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3367 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3368 | else |
3369 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3370 | } |
3371 | ||
3372 | /* ??? Without this setting Netgear GA302T PHY does not | |
3373 | * ??? send/receive packets... | |
3374 | */ | |
79eb6904 | 3375 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
3376 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
3377 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3378 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3379 | udelay(80); | |
3380 | } | |
3381 | ||
3382 | tw32_f(MAC_MODE, tp->mac_mode); | |
3383 | udelay(40); | |
3384 | ||
52b02d04 MC |
3385 | tg3_phy_eee_adjust(tp, current_link_up); |
3386 | ||
1da177e4 LT |
3387 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
3388 | /* Polled via timer. */ | |
3389 | tw32_f(MAC_EVENT, 0); | |
3390 | } else { | |
3391 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3392 | } | |
3393 | udelay(40); | |
3394 | ||
3395 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3396 | current_link_up == 1 && | |
3397 | tp->link_config.active_speed == SPEED_1000 && | |
3398 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || | |
3399 | (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { | |
3400 | udelay(120); | |
3401 | tw32_f(MAC_STATUS, | |
3402 | (MAC_STATUS_SYNC_CHANGED | | |
3403 | MAC_STATUS_CFG_CHANGED)); | |
3404 | udelay(40); | |
3405 | tg3_write_mem(tp, | |
3406 | NIC_SRAM_FIRMWARE_MBOX, | |
3407 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3408 | } | |
3409 | ||
5e7dfd0f MC |
3410 | /* Prevent send BD corruption. */ |
3411 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
3412 | u16 oldlnkctl, newlnkctl; | |
3413 | ||
3414 | pci_read_config_word(tp->pdev, | |
3415 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3416 | &oldlnkctl); | |
3417 | if (tp->link_config.active_speed == SPEED_100 || | |
3418 | tp->link_config.active_speed == SPEED_10) | |
3419 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3420 | else | |
3421 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3422 | if (newlnkctl != oldlnkctl) | |
3423 | pci_write_config_word(tp->pdev, | |
3424 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3425 | newlnkctl); | |
3426 | } | |
3427 | ||
1da177e4 LT |
3428 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3429 | if (current_link_up) | |
3430 | netif_carrier_on(tp->dev); | |
3431 | else | |
3432 | netif_carrier_off(tp->dev); | |
3433 | tg3_link_report(tp); | |
3434 | } | |
3435 | ||
3436 | return 0; | |
3437 | } | |
3438 | ||
3439 | struct tg3_fiber_aneginfo { | |
3440 | int state; | |
3441 | #define ANEG_STATE_UNKNOWN 0 | |
3442 | #define ANEG_STATE_AN_ENABLE 1 | |
3443 | #define ANEG_STATE_RESTART_INIT 2 | |
3444 | #define ANEG_STATE_RESTART 3 | |
3445 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3446 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3447 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3448 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3449 | #define ANEG_STATE_ACK_DETECT 8 | |
3450 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3451 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3452 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3453 | #define ANEG_STATE_IDLE_DETECT 12 | |
3454 | #define ANEG_STATE_LINK_OK 13 | |
3455 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3456 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3457 | ||
3458 | u32 flags; | |
3459 | #define MR_AN_ENABLE 0x00000001 | |
3460 | #define MR_RESTART_AN 0x00000002 | |
3461 | #define MR_AN_COMPLETE 0x00000004 | |
3462 | #define MR_PAGE_RX 0x00000008 | |
3463 | #define MR_NP_LOADED 0x00000010 | |
3464 | #define MR_TOGGLE_TX 0x00000020 | |
3465 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3466 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3467 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3468 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3469 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3470 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3471 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3472 | #define MR_TOGGLE_RX 0x00002000 | |
3473 | #define MR_NP_RX 0x00004000 | |
3474 | ||
3475 | #define MR_LINK_OK 0x80000000 | |
3476 | ||
3477 | unsigned long link_time, cur_time; | |
3478 | ||
3479 | u32 ability_match_cfg; | |
3480 | int ability_match_count; | |
3481 | ||
3482 | char ability_match, idle_match, ack_match; | |
3483 | ||
3484 | u32 txconfig, rxconfig; | |
3485 | #define ANEG_CFG_NP 0x00000080 | |
3486 | #define ANEG_CFG_ACK 0x00000040 | |
3487 | #define ANEG_CFG_RF2 0x00000020 | |
3488 | #define ANEG_CFG_RF1 0x00000010 | |
3489 | #define ANEG_CFG_PS2 0x00000001 | |
3490 | #define ANEG_CFG_PS1 0x00008000 | |
3491 | #define ANEG_CFG_HD 0x00004000 | |
3492 | #define ANEG_CFG_FD 0x00002000 | |
3493 | #define ANEG_CFG_INVAL 0x00001f06 | |
3494 | ||
3495 | }; | |
3496 | #define ANEG_OK 0 | |
3497 | #define ANEG_DONE 1 | |
3498 | #define ANEG_TIMER_ENAB 2 | |
3499 | #define ANEG_FAILED -1 | |
3500 | ||
3501 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3502 | ||
3503 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3504 | struct tg3_fiber_aneginfo *ap) | |
3505 | { | |
5be73b47 | 3506 | u16 flowctrl; |
1da177e4 LT |
3507 | unsigned long delta; |
3508 | u32 rx_cfg_reg; | |
3509 | int ret; | |
3510 | ||
3511 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3512 | ap->rxconfig = 0; | |
3513 | ap->link_time = 0; | |
3514 | ap->cur_time = 0; | |
3515 | ap->ability_match_cfg = 0; | |
3516 | ap->ability_match_count = 0; | |
3517 | ap->ability_match = 0; | |
3518 | ap->idle_match = 0; | |
3519 | ap->ack_match = 0; | |
3520 | } | |
3521 | ap->cur_time++; | |
3522 | ||
3523 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3524 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3525 | ||
3526 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3527 | ap->ability_match_cfg = rx_cfg_reg; | |
3528 | ap->ability_match = 0; | |
3529 | ap->ability_match_count = 0; | |
3530 | } else { | |
3531 | if (++ap->ability_match_count > 1) { | |
3532 | ap->ability_match = 1; | |
3533 | ap->ability_match_cfg = rx_cfg_reg; | |
3534 | } | |
3535 | } | |
3536 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3537 | ap->ack_match = 1; | |
3538 | else | |
3539 | ap->ack_match = 0; | |
3540 | ||
3541 | ap->idle_match = 0; | |
3542 | } else { | |
3543 | ap->idle_match = 1; | |
3544 | ap->ability_match_cfg = 0; | |
3545 | ap->ability_match_count = 0; | |
3546 | ap->ability_match = 0; | |
3547 | ap->ack_match = 0; | |
3548 | ||
3549 | rx_cfg_reg = 0; | |
3550 | } | |
3551 | ||
3552 | ap->rxconfig = rx_cfg_reg; | |
3553 | ret = ANEG_OK; | |
3554 | ||
33f401ae | 3555 | switch (ap->state) { |
1da177e4 LT |
3556 | case ANEG_STATE_UNKNOWN: |
3557 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3558 | ap->state = ANEG_STATE_AN_ENABLE; | |
3559 | ||
3560 | /* fallthru */ | |
3561 | case ANEG_STATE_AN_ENABLE: | |
3562 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3563 | if (ap->flags & MR_AN_ENABLE) { | |
3564 | ap->link_time = 0; | |
3565 | ap->cur_time = 0; | |
3566 | ap->ability_match_cfg = 0; | |
3567 | ap->ability_match_count = 0; | |
3568 | ap->ability_match = 0; | |
3569 | ap->idle_match = 0; | |
3570 | ap->ack_match = 0; | |
3571 | ||
3572 | ap->state = ANEG_STATE_RESTART_INIT; | |
3573 | } else { | |
3574 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3575 | } | |
3576 | break; | |
3577 | ||
3578 | case ANEG_STATE_RESTART_INIT: | |
3579 | ap->link_time = ap->cur_time; | |
3580 | ap->flags &= ~(MR_NP_LOADED); | |
3581 | ap->txconfig = 0; | |
3582 | tw32(MAC_TX_AUTO_NEG, 0); | |
3583 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3584 | tw32_f(MAC_MODE, tp->mac_mode); | |
3585 | udelay(40); | |
3586 | ||
3587 | ret = ANEG_TIMER_ENAB; | |
3588 | ap->state = ANEG_STATE_RESTART; | |
3589 | ||
3590 | /* fallthru */ | |
3591 | case ANEG_STATE_RESTART: | |
3592 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 3593 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 3594 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 3595 | else |
1da177e4 | 3596 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
3597 | break; |
3598 | ||
3599 | case ANEG_STATE_DISABLE_LINK_OK: | |
3600 | ret = ANEG_DONE; | |
3601 | break; | |
3602 | ||
3603 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3604 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3605 | ap->txconfig = ANEG_CFG_FD; |
3606 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3607 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3608 | ap->txconfig |= ANEG_CFG_PS1; | |
3609 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3610 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3611 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3612 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3613 | tw32_f(MAC_MODE, tp->mac_mode); | |
3614 | udelay(40); | |
3615 | ||
3616 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3617 | break; | |
3618 | ||
3619 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 3620 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 3621 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
3622 | break; |
3623 | ||
3624 | case ANEG_STATE_ACK_DETECT_INIT: | |
3625 | ap->txconfig |= ANEG_CFG_ACK; | |
3626 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3627 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3628 | tw32_f(MAC_MODE, tp->mac_mode); | |
3629 | udelay(40); | |
3630 | ||
3631 | ap->state = ANEG_STATE_ACK_DETECT; | |
3632 | ||
3633 | /* fallthru */ | |
3634 | case ANEG_STATE_ACK_DETECT: | |
3635 | if (ap->ack_match != 0) { | |
3636 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3637 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3638 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3639 | } else { | |
3640 | ap->state = ANEG_STATE_AN_ENABLE; | |
3641 | } | |
3642 | } else if (ap->ability_match != 0 && | |
3643 | ap->rxconfig == 0) { | |
3644 | ap->state = ANEG_STATE_AN_ENABLE; | |
3645 | } | |
3646 | break; | |
3647 | ||
3648 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3649 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3650 | ret = ANEG_FAILED; | |
3651 | break; | |
3652 | } | |
3653 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3654 | MR_LP_ADV_HALF_DUPLEX | | |
3655 | MR_LP_ADV_SYM_PAUSE | | |
3656 | MR_LP_ADV_ASYM_PAUSE | | |
3657 | MR_LP_ADV_REMOTE_FAULT1 | | |
3658 | MR_LP_ADV_REMOTE_FAULT2 | | |
3659 | MR_LP_ADV_NEXT_PAGE | | |
3660 | MR_TOGGLE_RX | | |
3661 | MR_NP_RX); | |
3662 | if (ap->rxconfig & ANEG_CFG_FD) | |
3663 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3664 | if (ap->rxconfig & ANEG_CFG_HD) | |
3665 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3666 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3667 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3668 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3669 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3670 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3671 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3672 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3673 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3674 | if (ap->rxconfig & ANEG_CFG_NP) | |
3675 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3676 | ||
3677 | ap->link_time = ap->cur_time; | |
3678 | ||
3679 | ap->flags ^= (MR_TOGGLE_TX); | |
3680 | if (ap->rxconfig & 0x0008) | |
3681 | ap->flags |= MR_TOGGLE_RX; | |
3682 | if (ap->rxconfig & ANEG_CFG_NP) | |
3683 | ap->flags |= MR_NP_RX; | |
3684 | ap->flags |= MR_PAGE_RX; | |
3685 | ||
3686 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3687 | ret = ANEG_TIMER_ENAB; | |
3688 | break; | |
3689 | ||
3690 | case ANEG_STATE_COMPLETE_ACK: | |
3691 | if (ap->ability_match != 0 && | |
3692 | ap->rxconfig == 0) { | |
3693 | ap->state = ANEG_STATE_AN_ENABLE; | |
3694 | break; | |
3695 | } | |
3696 | delta = ap->cur_time - ap->link_time; | |
3697 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3698 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3699 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3700 | } else { | |
3701 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3702 | !(ap->flags & MR_NP_RX)) { | |
3703 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3704 | } else { | |
3705 | ret = ANEG_FAILED; | |
3706 | } | |
3707 | } | |
3708 | } | |
3709 | break; | |
3710 | ||
3711 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3712 | ap->link_time = ap->cur_time; | |
3713 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3714 | tw32_f(MAC_MODE, tp->mac_mode); | |
3715 | udelay(40); | |
3716 | ||
3717 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3718 | ret = ANEG_TIMER_ENAB; | |
3719 | break; | |
3720 | ||
3721 | case ANEG_STATE_IDLE_DETECT: | |
3722 | if (ap->ability_match != 0 && | |
3723 | ap->rxconfig == 0) { | |
3724 | ap->state = ANEG_STATE_AN_ENABLE; | |
3725 | break; | |
3726 | } | |
3727 | delta = ap->cur_time - ap->link_time; | |
3728 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3729 | /* XXX another gem from the Broadcom driver :( */ | |
3730 | ap->state = ANEG_STATE_LINK_OK; | |
3731 | } | |
3732 | break; | |
3733 | ||
3734 | case ANEG_STATE_LINK_OK: | |
3735 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3736 | ret = ANEG_DONE; | |
3737 | break; | |
3738 | ||
3739 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3740 | /* ??? unimplemented */ | |
3741 | break; | |
3742 | ||
3743 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3744 | /* ??? unimplemented */ | |
3745 | break; | |
3746 | ||
3747 | default: | |
3748 | ret = ANEG_FAILED; | |
3749 | break; | |
855e1111 | 3750 | } |
1da177e4 LT |
3751 | |
3752 | return ret; | |
3753 | } | |
3754 | ||
5be73b47 | 3755 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3756 | { |
3757 | int res = 0; | |
3758 | struct tg3_fiber_aneginfo aninfo; | |
3759 | int status = ANEG_FAILED; | |
3760 | unsigned int tick; | |
3761 | u32 tmp; | |
3762 | ||
3763 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3764 | ||
3765 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3766 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3767 | udelay(40); | |
3768 | ||
3769 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3770 | udelay(40); | |
3771 | ||
3772 | memset(&aninfo, 0, sizeof(aninfo)); | |
3773 | aninfo.flags |= MR_AN_ENABLE; | |
3774 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3775 | aninfo.cur_time = 0; | |
3776 | tick = 0; | |
3777 | while (++tick < 195000) { | |
3778 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3779 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3780 | break; | |
3781 | ||
3782 | udelay(1); | |
3783 | } | |
3784 | ||
3785 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3786 | tw32_f(MAC_MODE, tp->mac_mode); | |
3787 | udelay(40); | |
3788 | ||
5be73b47 MC |
3789 | *txflags = aninfo.txconfig; |
3790 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3791 | |
3792 | if (status == ANEG_DONE && | |
3793 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3794 | MR_LP_ADV_FULL_DUPLEX))) | |
3795 | res = 1; | |
3796 | ||
3797 | return res; | |
3798 | } | |
3799 | ||
3800 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3801 | { | |
3802 | u32 mac_status = tr32(MAC_STATUS); | |
3803 | int i; | |
3804 | ||
3805 | /* Reset when initting first time or we have a link. */ | |
3806 | if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && | |
3807 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3808 | return; | |
3809 | ||
3810 | /* Set PLL lock range. */ | |
3811 | tg3_writephy(tp, 0x16, 0x8007); | |
3812 | ||
3813 | /* SW reset */ | |
3814 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3815 | ||
3816 | /* Wait for reset to complete. */ | |
3817 | /* XXX schedule_timeout() ... */ | |
3818 | for (i = 0; i < 500; i++) | |
3819 | udelay(10); | |
3820 | ||
3821 | /* Config mode; select PMA/Ch 1 regs. */ | |
3822 | tg3_writephy(tp, 0x10, 0x8411); | |
3823 | ||
3824 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3825 | tg3_writephy(tp, 0x11, 0x0a10); | |
3826 | ||
3827 | tg3_writephy(tp, 0x18, 0x00a0); | |
3828 | tg3_writephy(tp, 0x16, 0x41ff); | |
3829 | ||
3830 | /* Assert and deassert POR. */ | |
3831 | tg3_writephy(tp, 0x13, 0x0400); | |
3832 | udelay(40); | |
3833 | tg3_writephy(tp, 0x13, 0x0000); | |
3834 | ||
3835 | tg3_writephy(tp, 0x11, 0x0a50); | |
3836 | udelay(40); | |
3837 | tg3_writephy(tp, 0x11, 0x0a10); | |
3838 | ||
3839 | /* Wait for signal to stabilize */ | |
3840 | /* XXX schedule_timeout() ... */ | |
3841 | for (i = 0; i < 15000; i++) | |
3842 | udelay(10); | |
3843 | ||
3844 | /* Deselect the channel register so we can read the PHYID | |
3845 | * later. | |
3846 | */ | |
3847 | tg3_writephy(tp, 0x10, 0x8011); | |
3848 | } | |
3849 | ||
3850 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3851 | { | |
82cd3d11 | 3852 | u16 flowctrl; |
1da177e4 LT |
3853 | u32 sg_dig_ctrl, sg_dig_status; |
3854 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3855 | int workaround, port_a; | |
3856 | int current_link_up; | |
3857 | ||
3858 | serdes_cfg = 0; | |
3859 | expected_sg_dig_ctrl = 0; | |
3860 | workaround = 0; | |
3861 | port_a = 1; | |
3862 | current_link_up = 0; | |
3863 | ||
3864 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3865 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3866 | workaround = 1; | |
3867 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3868 | port_a = 0; | |
3869 | ||
3870 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3871 | /* preserve bits 20-23 for voltage regulator */ | |
3872 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3873 | } | |
3874 | ||
3875 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3876 | ||
3877 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 3878 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
3879 | if (workaround) { |
3880 | u32 val = serdes_cfg; | |
3881 | ||
3882 | if (port_a) | |
3883 | val |= 0xc010000; | |
3884 | else | |
3885 | val |= 0x4010000; | |
3886 | tw32_f(MAC_SERDES_CFG, val); | |
3887 | } | |
c98f6e3b MC |
3888 | |
3889 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
3890 | } |
3891 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3892 | tg3_setup_flow_control(tp, 0, 0); | |
3893 | current_link_up = 1; | |
3894 | } | |
3895 | goto out; | |
3896 | } | |
3897 | ||
3898 | /* Want auto-negotiation. */ | |
c98f6e3b | 3899 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 3900 | |
82cd3d11 MC |
3901 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
3902 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3903 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3904 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3905 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
3906 | |
3907 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 3908 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
3909 | tp->serdes_counter && |
3910 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3911 | MAC_STATUS_RCVD_CFG)) == | |
3912 | MAC_STATUS_PCS_SYNCED)) { | |
3913 | tp->serdes_counter--; | |
3914 | current_link_up = 1; | |
3915 | goto out; | |
3916 | } | |
3917 | restart_autoneg: | |
1da177e4 LT |
3918 | if (workaround) |
3919 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 3920 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
3921 | udelay(5); |
3922 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3923 | ||
3d3ebe74 | 3924 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 3925 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
3926 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
3927 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 3928 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
3929 | mac_status = tr32(MAC_STATUS); |
3930 | ||
c98f6e3b | 3931 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 3932 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
3933 | u32 local_adv = 0, remote_adv = 0; |
3934 | ||
3935 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3936 | local_adv |= ADVERTISE_1000XPAUSE; | |
3937 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3938 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 3939 | |
c98f6e3b | 3940 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 3941 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 3942 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 3943 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
3944 | |
3945 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3946 | current_link_up = 1; | |
3d3ebe74 | 3947 | tp->serdes_counter = 0; |
f07e9af3 | 3948 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 3949 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
3950 | if (tp->serdes_counter) |
3951 | tp->serdes_counter--; | |
1da177e4 LT |
3952 | else { |
3953 | if (workaround) { | |
3954 | u32 val = serdes_cfg; | |
3955 | ||
3956 | if (port_a) | |
3957 | val |= 0xc010000; | |
3958 | else | |
3959 | val |= 0x4010000; | |
3960 | ||
3961 | tw32_f(MAC_SERDES_CFG, val); | |
3962 | } | |
3963 | ||
c98f6e3b | 3964 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
3965 | udelay(40); |
3966 | ||
3967 | /* Link parallel detection - link is up */ | |
3968 | /* only if we have PCS_SYNC and not */ | |
3969 | /* receiving config code words */ | |
3970 | mac_status = tr32(MAC_STATUS); | |
3971 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
3972 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
3973 | tg3_setup_flow_control(tp, 0, 0); | |
3974 | current_link_up = 1; | |
f07e9af3 MC |
3975 | tp->phy_flags |= |
3976 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
3977 | tp->serdes_counter = |
3978 | SERDES_PARALLEL_DET_TIMEOUT; | |
3979 | } else | |
3980 | goto restart_autoneg; | |
1da177e4 LT |
3981 | } |
3982 | } | |
3d3ebe74 MC |
3983 | } else { |
3984 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 3985 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
3986 | } |
3987 | ||
3988 | out: | |
3989 | return current_link_up; | |
3990 | } | |
3991 | ||
3992 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
3993 | { | |
3994 | int current_link_up = 0; | |
3995 | ||
5cf64b8a | 3996 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 3997 | goto out; |
1da177e4 LT |
3998 | |
3999 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 4000 | u32 txflags, rxflags; |
1da177e4 | 4001 | int i; |
6aa20a22 | 4002 | |
5be73b47 MC |
4003 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
4004 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 4005 | |
5be73b47 MC |
4006 | if (txflags & ANEG_CFG_PS1) |
4007 | local_adv |= ADVERTISE_1000XPAUSE; | |
4008 | if (txflags & ANEG_CFG_PS2) | |
4009 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4010 | ||
4011 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4012 | remote_adv |= LPA_1000XPAUSE; | |
4013 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4014 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
4015 | |
4016 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4017 | ||
1da177e4 LT |
4018 | current_link_up = 1; |
4019 | } | |
4020 | for (i = 0; i < 30; i++) { | |
4021 | udelay(20); | |
4022 | tw32_f(MAC_STATUS, | |
4023 | (MAC_STATUS_SYNC_CHANGED | | |
4024 | MAC_STATUS_CFG_CHANGED)); | |
4025 | udelay(40); | |
4026 | if ((tr32(MAC_STATUS) & | |
4027 | (MAC_STATUS_SYNC_CHANGED | | |
4028 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4029 | break; | |
4030 | } | |
4031 | ||
4032 | mac_status = tr32(MAC_STATUS); | |
4033 | if (current_link_up == 0 && | |
4034 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4035 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4036 | current_link_up = 1; | |
4037 | } else { | |
5be73b47 MC |
4038 | tg3_setup_flow_control(tp, 0, 0); |
4039 | ||
1da177e4 LT |
4040 | /* Forcing 1000FD link up. */ |
4041 | current_link_up = 1; | |
1da177e4 LT |
4042 | |
4043 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4044 | udelay(40); | |
e8f3f6ca MC |
4045 | |
4046 | tw32_f(MAC_MODE, tp->mac_mode); | |
4047 | udelay(40); | |
1da177e4 LT |
4048 | } |
4049 | ||
4050 | out: | |
4051 | return current_link_up; | |
4052 | } | |
4053 | ||
4054 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4055 | { | |
4056 | u32 orig_pause_cfg; | |
4057 | u16 orig_active_speed; | |
4058 | u8 orig_active_duplex; | |
4059 | u32 mac_status; | |
4060 | int current_link_up; | |
4061 | int i; | |
4062 | ||
8d018621 | 4063 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4064 | orig_active_speed = tp->link_config.active_speed; |
4065 | orig_active_duplex = tp->link_config.active_duplex; | |
4066 | ||
4067 | if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && | |
4068 | netif_carrier_ok(tp->dev) && | |
4069 | (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { | |
4070 | mac_status = tr32(MAC_STATUS); | |
4071 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4072 | MAC_STATUS_SIGNAL_DET | | |
4073 | MAC_STATUS_CFG_CHANGED | | |
4074 | MAC_STATUS_RCVD_CFG); | |
4075 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4076 | MAC_STATUS_SIGNAL_DET)) { | |
4077 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4078 | MAC_STATUS_CFG_CHANGED)); | |
4079 | return 0; | |
4080 | } | |
4081 | } | |
4082 | ||
4083 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4084 | ||
4085 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4086 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4087 | tw32_f(MAC_MODE, tp->mac_mode); | |
4088 | udelay(40); | |
4089 | ||
79eb6904 | 4090 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
4091 | tg3_init_bcm8002(tp); |
4092 | ||
4093 | /* Enable link change event even when serdes polling. */ | |
4094 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4095 | udelay(40); | |
4096 | ||
4097 | current_link_up = 0; | |
4098 | mac_status = tr32(MAC_STATUS); | |
4099 | ||
4100 | if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) | |
4101 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
4102 | else | |
4103 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4104 | ||
898a56f8 | 4105 | tp->napi[0].hw_status->status = |
1da177e4 | 4106 | (SD_STATUS_UPDATED | |
898a56f8 | 4107 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4108 | |
4109 | for (i = 0; i < 100; i++) { | |
4110 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4111 | MAC_STATUS_CFG_CHANGED)); | |
4112 | udelay(5); | |
4113 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4114 | MAC_STATUS_CFG_CHANGED | |
4115 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4116 | break; |
4117 | } | |
4118 | ||
4119 | mac_status = tr32(MAC_STATUS); | |
4120 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4121 | current_link_up = 0; | |
3d3ebe74 MC |
4122 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4123 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4124 | tw32_f(MAC_MODE, (tp->mac_mode | |
4125 | MAC_MODE_SEND_CONFIGS)); | |
4126 | udelay(1); | |
4127 | tw32_f(MAC_MODE, tp->mac_mode); | |
4128 | } | |
4129 | } | |
4130 | ||
4131 | if (current_link_up == 1) { | |
4132 | tp->link_config.active_speed = SPEED_1000; | |
4133 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4134 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4135 | LED_CTRL_LNKLED_OVERRIDE | | |
4136 | LED_CTRL_1000MBPS_ON)); | |
4137 | } else { | |
4138 | tp->link_config.active_speed = SPEED_INVALID; | |
4139 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4140 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4141 | LED_CTRL_LNKLED_OVERRIDE | | |
4142 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4143 | } | |
4144 | ||
4145 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4146 | if (current_link_up) | |
4147 | netif_carrier_on(tp->dev); | |
4148 | else | |
4149 | netif_carrier_off(tp->dev); | |
4150 | tg3_link_report(tp); | |
4151 | } else { | |
8d018621 | 4152 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4153 | if (orig_pause_cfg != now_pause_cfg || |
4154 | orig_active_speed != tp->link_config.active_speed || | |
4155 | orig_active_duplex != tp->link_config.active_duplex) | |
4156 | tg3_link_report(tp); | |
4157 | } | |
4158 | ||
4159 | return 0; | |
4160 | } | |
4161 | ||
747e8f8b MC |
4162 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4163 | { | |
4164 | int current_link_up, err = 0; | |
4165 | u32 bmsr, bmcr; | |
4166 | u16 current_speed; | |
4167 | u8 current_duplex; | |
ef167e27 | 4168 | u32 local_adv, remote_adv; |
747e8f8b MC |
4169 | |
4170 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4171 | tw32_f(MAC_MODE, tp->mac_mode); | |
4172 | udelay(40); | |
4173 | ||
4174 | tw32(MAC_EVENT, 0); | |
4175 | ||
4176 | tw32_f(MAC_STATUS, | |
4177 | (MAC_STATUS_SYNC_CHANGED | | |
4178 | MAC_STATUS_CFG_CHANGED | | |
4179 | MAC_STATUS_MI_COMPLETION | | |
4180 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4181 | udelay(40); | |
4182 | ||
4183 | if (force_reset) | |
4184 | tg3_phy_reset(tp); | |
4185 | ||
4186 | current_link_up = 0; | |
4187 | current_speed = SPEED_INVALID; | |
4188 | current_duplex = DUPLEX_INVALID; | |
4189 | ||
4190 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4191 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4192 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4193 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4194 | bmsr |= BMSR_LSTATUS; | |
4195 | else | |
4196 | bmsr &= ~BMSR_LSTATUS; | |
4197 | } | |
747e8f8b MC |
4198 | |
4199 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4200 | ||
4201 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 4202 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4203 | /* do nothing, just check for link up at the end */ |
4204 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4205 | u32 adv, new_adv; | |
4206 | ||
4207 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4208 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4209 | ADVERTISE_1000XPAUSE | | |
4210 | ADVERTISE_1000XPSE_ASYM | | |
4211 | ADVERTISE_SLCT); | |
4212 | ||
ba4d07a8 | 4213 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4214 | |
4215 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4216 | new_adv |= ADVERTISE_1000XHALF; | |
4217 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4218 | new_adv |= ADVERTISE_1000XFULL; | |
4219 | ||
4220 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4221 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4222 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4223 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4224 | ||
4225 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4226 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 4227 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4228 | |
4229 | return err; | |
4230 | } | |
4231 | } else { | |
4232 | u32 new_bmcr; | |
4233 | ||
4234 | bmcr &= ~BMCR_SPEED1000; | |
4235 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4236 | ||
4237 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4238 | new_bmcr |= BMCR_FULLDPLX; | |
4239 | ||
4240 | if (new_bmcr != bmcr) { | |
4241 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4242 | * to be set on write. | |
4243 | */ | |
4244 | new_bmcr |= BMCR_SPEED1000; | |
4245 | ||
4246 | /* Force a linkdown */ | |
4247 | if (netif_carrier_ok(tp->dev)) { | |
4248 | u32 adv; | |
4249 | ||
4250 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4251 | adv &= ~(ADVERTISE_1000XFULL | | |
4252 | ADVERTISE_1000XHALF | | |
4253 | ADVERTISE_SLCT); | |
4254 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4255 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4256 | BMCR_ANRESTART | | |
4257 | BMCR_ANENABLE); | |
4258 | udelay(10); | |
4259 | netif_carrier_off(tp->dev); | |
4260 | } | |
4261 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4262 | bmcr = new_bmcr; | |
4263 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4264 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4265 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4266 | ASIC_REV_5714) { | |
4267 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4268 | bmsr |= BMSR_LSTATUS; | |
4269 | else | |
4270 | bmsr &= ~BMSR_LSTATUS; | |
4271 | } | |
f07e9af3 | 4272 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4273 | } |
4274 | } | |
4275 | ||
4276 | if (bmsr & BMSR_LSTATUS) { | |
4277 | current_speed = SPEED_1000; | |
4278 | current_link_up = 1; | |
4279 | if (bmcr & BMCR_FULLDPLX) | |
4280 | current_duplex = DUPLEX_FULL; | |
4281 | else | |
4282 | current_duplex = DUPLEX_HALF; | |
4283 | ||
ef167e27 MC |
4284 | local_adv = 0; |
4285 | remote_adv = 0; | |
4286 | ||
747e8f8b | 4287 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4288 | u32 common; |
747e8f8b MC |
4289 | |
4290 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4291 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4292 | common = local_adv & remote_adv; | |
4293 | if (common & (ADVERTISE_1000XHALF | | |
4294 | ADVERTISE_1000XFULL)) { | |
4295 | if (common & ADVERTISE_1000XFULL) | |
4296 | current_duplex = DUPLEX_FULL; | |
4297 | else | |
4298 | current_duplex = DUPLEX_HALF; | |
57d8b880 MC |
4299 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
4300 | /* Link is up via parallel detect */ | |
859a5887 | 4301 | } else { |
747e8f8b | 4302 | current_link_up = 0; |
859a5887 | 4303 | } |
747e8f8b MC |
4304 | } |
4305 | } | |
4306 | ||
ef167e27 MC |
4307 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4308 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4309 | ||
747e8f8b MC |
4310 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4311 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4312 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4313 | ||
4314 | tw32_f(MAC_MODE, tp->mac_mode); | |
4315 | udelay(40); | |
4316 | ||
4317 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4318 | ||
4319 | tp->link_config.active_speed = current_speed; | |
4320 | tp->link_config.active_duplex = current_duplex; | |
4321 | ||
4322 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4323 | if (current_link_up) | |
4324 | netif_carrier_on(tp->dev); | |
4325 | else { | |
4326 | netif_carrier_off(tp->dev); | |
f07e9af3 | 4327 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4328 | } |
4329 | tg3_link_report(tp); | |
4330 | } | |
4331 | return err; | |
4332 | } | |
4333 | ||
4334 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4335 | { | |
3d3ebe74 | 4336 | if (tp->serdes_counter) { |
747e8f8b | 4337 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4338 | tp->serdes_counter--; |
747e8f8b MC |
4339 | return; |
4340 | } | |
c6cdf436 | 4341 | |
747e8f8b MC |
4342 | if (!netif_carrier_ok(tp->dev) && |
4343 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4344 | u32 bmcr; | |
4345 | ||
4346 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4347 | if (bmcr & BMCR_ANENABLE) { | |
4348 | u32 phy1, phy2; | |
4349 | ||
4350 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
4351 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
4352 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
4353 | |
4354 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4355 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4356 | MII_TG3_DSP_EXP1_INT_STAT); | |
4357 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4358 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4359 | |
4360 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4361 | /* We have signal detect and not receiving | |
4362 | * config code words, link is up by parallel | |
4363 | * detection. | |
4364 | */ | |
4365 | ||
4366 | bmcr &= ~BMCR_ANENABLE; | |
4367 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4368 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 4369 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4370 | } |
4371 | } | |
859a5887 MC |
4372 | } else if (netif_carrier_ok(tp->dev) && |
4373 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 4374 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4375 | u32 phy2; |
4376 | ||
4377 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4378 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4379 | MII_TG3_DSP_EXP1_INT_STAT); | |
4380 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4381 | if (phy2 & 0x20) { |
4382 | u32 bmcr; | |
4383 | ||
4384 | /* Config code words received, turn on autoneg. */ | |
4385 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4386 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4387 | ||
f07e9af3 | 4388 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4389 | |
4390 | } | |
4391 | } | |
4392 | } | |
4393 | ||
1da177e4 LT |
4394 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4395 | { | |
f2096f94 | 4396 | u32 val; |
1da177e4 LT |
4397 | int err; |
4398 | ||
f07e9af3 | 4399 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 4400 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 4401 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 4402 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 4403 | else |
1da177e4 | 4404 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 4405 | |
bcb37f6c | 4406 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
f2096f94 | 4407 | u32 scale; |
aa6c91fe MC |
4408 | |
4409 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4410 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4411 | scale = 65; | |
4412 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4413 | scale = 6; | |
4414 | else | |
4415 | scale = 12; | |
4416 | ||
4417 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4418 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4419 | tw32(GRC_MISC_CFG, val); | |
4420 | } | |
4421 | ||
f2096f94 MC |
4422 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
4423 | (6 << TX_LENGTHS_IPG_SHIFT); | |
4424 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
4425 | val |= tr32(MAC_TX_LENGTHS) & | |
4426 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
4427 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
4428 | ||
1da177e4 LT |
4429 | if (tp->link_config.active_speed == SPEED_1000 && |
4430 | tp->link_config.active_duplex == DUPLEX_HALF) | |
f2096f94 MC |
4431 | tw32(MAC_TX_LENGTHS, val | |
4432 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 | 4433 | else |
f2096f94 MC |
4434 | tw32(MAC_TX_LENGTHS, val | |
4435 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
1da177e4 LT |
4436 | |
4437 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4438 | if (netif_carrier_ok(tp->dev)) { | |
4439 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4440 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4441 | } else { |
4442 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4443 | } | |
4444 | } | |
4445 | ||
8ed5d97e | 4446 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { |
f2096f94 | 4447 | val = tr32(PCIE_PWR_MGMT_THRESH); |
8ed5d97e MC |
4448 | if (!netif_carrier_ok(tp->dev)) |
4449 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4450 | tp->pwrmgmt_thresh; | |
4451 | else | |
4452 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4453 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4454 | } | |
4455 | ||
1da177e4 LT |
4456 | return err; |
4457 | } | |
4458 | ||
66cfd1bd MC |
4459 | static inline int tg3_irq_sync(struct tg3 *tp) |
4460 | { | |
4461 | return tp->irq_sync; | |
4462 | } | |
4463 | ||
97bd8e49 MC |
4464 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
4465 | { | |
4466 | int i; | |
4467 | ||
4468 | dst = (u32 *)((u8 *)dst + off); | |
4469 | for (i = 0; i < len; i += sizeof(u32)) | |
4470 | *dst++ = tr32(off + i); | |
4471 | } | |
4472 | ||
4473 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) | |
4474 | { | |
4475 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); | |
4476 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); | |
4477 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); | |
4478 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); | |
4479 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); | |
4480 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); | |
4481 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); | |
4482 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); | |
4483 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); | |
4484 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); | |
4485 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); | |
4486 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); | |
4487 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); | |
4488 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); | |
4489 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); | |
4490 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); | |
4491 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); | |
4492 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); | |
4493 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); | |
4494 | ||
4495 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) | |
4496 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); | |
4497 | ||
4498 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); | |
4499 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); | |
4500 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); | |
4501 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); | |
4502 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); | |
4503 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); | |
4504 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); | |
4505 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); | |
4506 | ||
4507 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4508 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); | |
4509 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); | |
4510 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); | |
4511 | } | |
4512 | ||
4513 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); | |
4514 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); | |
4515 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); | |
4516 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); | |
4517 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); | |
4518 | ||
4519 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
4520 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); | |
4521 | } | |
4522 | ||
4523 | static void tg3_dump_state(struct tg3 *tp) | |
4524 | { | |
4525 | int i; | |
4526 | u32 *regs; | |
4527 | ||
4528 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); | |
4529 | if (!regs) { | |
4530 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); | |
4531 | return; | |
4532 | } | |
4533 | ||
4534 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
4535 | /* Read up to but not including private PCI registers */ | |
4536 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) | |
4537 | regs[i / sizeof(u32)] = tr32(i); | |
4538 | } else | |
4539 | tg3_dump_legacy_regs(tp, regs); | |
4540 | ||
4541 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { | |
4542 | if (!regs[i + 0] && !regs[i + 1] && | |
4543 | !regs[i + 2] && !regs[i + 3]) | |
4544 | continue; | |
4545 | ||
4546 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", | |
4547 | i * 4, | |
4548 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); | |
4549 | } | |
4550 | ||
4551 | kfree(regs); | |
4552 | ||
4553 | for (i = 0; i < tp->irq_cnt; i++) { | |
4554 | struct tg3_napi *tnapi = &tp->napi[i]; | |
4555 | ||
4556 | /* SW status block */ | |
4557 | netdev_err(tp->dev, | |
4558 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
4559 | i, | |
4560 | tnapi->hw_status->status, | |
4561 | tnapi->hw_status->status_tag, | |
4562 | tnapi->hw_status->rx_jumbo_consumer, | |
4563 | tnapi->hw_status->rx_consumer, | |
4564 | tnapi->hw_status->rx_mini_consumer, | |
4565 | tnapi->hw_status->idx[0].rx_producer, | |
4566 | tnapi->hw_status->idx[0].tx_consumer); | |
4567 | ||
4568 | netdev_err(tp->dev, | |
4569 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", | |
4570 | i, | |
4571 | tnapi->last_tag, tnapi->last_irq_tag, | |
4572 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, | |
4573 | tnapi->rx_rcb_ptr, | |
4574 | tnapi->prodring.rx_std_prod_idx, | |
4575 | tnapi->prodring.rx_std_cons_idx, | |
4576 | tnapi->prodring.rx_jmb_prod_idx, | |
4577 | tnapi->prodring.rx_jmb_cons_idx); | |
4578 | } | |
4579 | } | |
4580 | ||
df3e6548 MC |
4581 | /* This is called whenever we suspect that the system chipset is re- |
4582 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4583 | * is bogus tx completions. We try to recover by setting the | |
4584 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4585 | * in the workqueue. | |
4586 | */ | |
4587 | static void tg3_tx_recover(struct tg3 *tp) | |
4588 | { | |
4589 | BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || | |
4590 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4591 | ||
5129c3a3 MC |
4592 | netdev_warn(tp->dev, |
4593 | "The system may be re-ordering memory-mapped I/O " | |
4594 | "cycles to the network device, attempting to recover. " | |
4595 | "Please report the problem to the driver maintainer " | |
4596 | "and include system chipset information.\n"); | |
df3e6548 MC |
4597 | |
4598 | spin_lock(&tp->lock); | |
df3e6548 | 4599 | tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; |
df3e6548 MC |
4600 | spin_unlock(&tp->lock); |
4601 | } | |
4602 | ||
f3f3f27e | 4603 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 4604 | { |
f65aac16 MC |
4605 | /* Tell compiler to fetch tx indices from memory. */ |
4606 | barrier(); | |
f3f3f27e MC |
4607 | return tnapi->tx_pending - |
4608 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4609 | } |
4610 | ||
1da177e4 LT |
4611 | /* Tigon3 never reports partial packet sends. So we do not |
4612 | * need special logic to handle SKBs that have not had all | |
4613 | * of their frags sent yet, like SunGEM does. | |
4614 | */ | |
17375d25 | 4615 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4616 | { |
17375d25 | 4617 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4618 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4619 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
4620 | struct netdev_queue *txq; |
4621 | int index = tnapi - tp->napi; | |
4622 | ||
19cfaecc | 4623 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 MC |
4624 | index--; |
4625 | ||
4626 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
4627 | |
4628 | while (sw_idx != hw_idx) { | |
f4188d8a | 4629 | struct ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4630 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4631 | int i, tx_bug = 0; |
4632 | ||
4633 | if (unlikely(skb == NULL)) { | |
4634 | tg3_tx_recover(tp); | |
4635 | return; | |
4636 | } | |
1da177e4 | 4637 | |
f4188d8a | 4638 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 4639 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4640 | skb_headlen(skb), |
4641 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4642 | |
4643 | ri->skb = NULL; | |
4644 | ||
4645 | sw_idx = NEXT_TX(sw_idx); | |
4646 | ||
4647 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4648 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4649 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4650 | tx_bug = 1; | |
f4188d8a AD |
4651 | |
4652 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 4653 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4654 | skb_shinfo(skb)->frags[i].size, |
4655 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4656 | sw_idx = NEXT_TX(sw_idx); |
4657 | } | |
4658 | ||
f47c11ee | 4659 | dev_kfree_skb(skb); |
df3e6548 MC |
4660 | |
4661 | if (unlikely(tx_bug)) { | |
4662 | tg3_tx_recover(tp); | |
4663 | return; | |
4664 | } | |
1da177e4 LT |
4665 | } |
4666 | ||
f3f3f27e | 4667 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4668 | |
1b2a7205 MC |
4669 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4670 | * before checking for netif_queue_stopped(). Without the | |
4671 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4672 | * will miss it and cause the queue to be stopped forever. | |
4673 | */ | |
4674 | smp_mb(); | |
4675 | ||
fe5f5787 | 4676 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 4677 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
4678 | __netif_tx_lock(txq, smp_processor_id()); |
4679 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 4680 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
4681 | netif_tx_wake_queue(txq); |
4682 | __netif_tx_unlock(txq); | |
51b91468 | 4683 | } |
1da177e4 LT |
4684 | } |
4685 | ||
2b2cdb65 MC |
4686 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
4687 | { | |
4688 | if (!ri->skb) | |
4689 | return; | |
4690 | ||
4e5e4f0d | 4691 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 MC |
4692 | map_sz, PCI_DMA_FROMDEVICE); |
4693 | dev_kfree_skb_any(ri->skb); | |
4694 | ri->skb = NULL; | |
4695 | } | |
4696 | ||
1da177e4 LT |
4697 | /* Returns size of skb allocated or < 0 on error. |
4698 | * | |
4699 | * We only need to fill in the address because the other members | |
4700 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4701 | * | |
4702 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4703 | * posting buffers we only dirty the first cache line of the RX | |
4704 | * descriptor (containing the address). Whereas for the RX status | |
4705 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4706 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4707 | */ | |
86b21e59 | 4708 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 4709 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
4710 | { |
4711 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 4712 | struct ring_info *map; |
1da177e4 LT |
4713 | struct sk_buff *skb; |
4714 | dma_addr_t mapping; | |
4715 | int skb_size, dest_idx; | |
4716 | ||
1da177e4 LT |
4717 | switch (opaque_key) { |
4718 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4719 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
4720 | desc = &tpr->rx_std[dest_idx]; |
4721 | map = &tpr->rx_std_buffers[dest_idx]; | |
287be12e | 4722 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4723 | break; |
4724 | ||
4725 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4726 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 4727 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4728 | map = &tpr->rx_jmb_buffers[dest_idx]; |
287be12e | 4729 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4730 | break; |
4731 | ||
4732 | default: | |
4733 | return -EINVAL; | |
855e1111 | 4734 | } |
1da177e4 LT |
4735 | |
4736 | /* Do not overwrite any of the map or rp information | |
4737 | * until we are sure we can commit to a new buffer. | |
4738 | * | |
4739 | * Callers depend upon this behavior and assume that | |
4740 | * we leave everything unchanged if we fail. | |
4741 | */ | |
287be12e | 4742 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4743 | if (skb == NULL) |
4744 | return -ENOMEM; | |
4745 | ||
1da177e4 LT |
4746 | skb_reserve(skb, tp->rx_offset); |
4747 | ||
287be12e | 4748 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 4749 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
4750 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
4751 | dev_kfree_skb(skb); | |
4752 | return -EIO; | |
4753 | } | |
1da177e4 LT |
4754 | |
4755 | map->skb = skb; | |
4e5e4f0d | 4756 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 4757 | |
1da177e4 LT |
4758 | desc->addr_hi = ((u64)mapping >> 32); |
4759 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4760 | ||
4761 | return skb_size; | |
4762 | } | |
4763 | ||
4764 | /* We only need to move over in the address because the other | |
4765 | * members of the RX descriptor are invariant. See notes above | |
4766 | * tg3_alloc_rx_skb for full details. | |
4767 | */ | |
a3896167 MC |
4768 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
4769 | struct tg3_rx_prodring_set *dpr, | |
4770 | u32 opaque_key, int src_idx, | |
4771 | u32 dest_idx_unmasked) | |
1da177e4 | 4772 | { |
17375d25 | 4773 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4774 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4775 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 4776 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 4777 | int dest_idx; |
1da177e4 LT |
4778 | |
4779 | switch (opaque_key) { | |
4780 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4781 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
4782 | dest_desc = &dpr->rx_std[dest_idx]; |
4783 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4784 | src_desc = &spr->rx_std[src_idx]; | |
4785 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4786 | break; |
4787 | ||
4788 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4789 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
4790 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
4791 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
4792 | src_desc = &spr->rx_jmb[src_idx].std; | |
4793 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
4794 | break; |
4795 | ||
4796 | default: | |
4797 | return; | |
855e1111 | 4798 | } |
1da177e4 LT |
4799 | |
4800 | dest_map->skb = src_map->skb; | |
4e5e4f0d FT |
4801 | dma_unmap_addr_set(dest_map, mapping, |
4802 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
4803 | dest_desc->addr_hi = src_desc->addr_hi; |
4804 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
4805 | |
4806 | /* Ensure that the update to the skb happens after the physical | |
4807 | * addresses have been transferred to the new BD location. | |
4808 | */ | |
4809 | smp_wmb(); | |
4810 | ||
1da177e4 LT |
4811 | src_map->skb = NULL; |
4812 | } | |
4813 | ||
1da177e4 LT |
4814 | /* The RX ring scheme is composed of multiple rings which post fresh |
4815 | * buffers to the chip, and one special ring the chip uses to report | |
4816 | * status back to the host. | |
4817 | * | |
4818 | * The special ring reports the status of received packets to the | |
4819 | * host. The chip does not write into the original descriptor the | |
4820 | * RX buffer was obtained from. The chip simply takes the original | |
4821 | * descriptor as provided by the host, updates the status and length | |
4822 | * field, then writes this into the next status ring entry. | |
4823 | * | |
4824 | * Each ring the host uses to post buffers to the chip is described | |
4825 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4826 | * it is first placed into the on-chip ram. When the packet's length | |
4827 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4828 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4829 | * which is within the range of the new packet's length is chosen. | |
4830 | * | |
4831 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4832 | * sense from a cache coherency perspective. If only the host writes | |
4833 | * to the buffer post rings, and only the chip writes to the rx status | |
4834 | * rings, then cache lines never move beyond shared-modified state. | |
4835 | * If both the host and chip were to write into the same ring, cache line | |
4836 | * eviction could occur since both entities want it in an exclusive state. | |
4837 | */ | |
17375d25 | 4838 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 4839 | { |
17375d25 | 4840 | struct tg3 *tp = tnapi->tp; |
f92905de | 4841 | u32 work_mask, rx_std_posted = 0; |
4361935a | 4842 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 4843 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 4844 | u16 hw_idx; |
1da177e4 | 4845 | int received; |
8fea32b9 | 4846 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 4847 | |
8d9d7cfc | 4848 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
4849 | /* |
4850 | * We need to order the read of hw_idx and the read of | |
4851 | * the opaque cookie. | |
4852 | */ | |
4853 | rmb(); | |
1da177e4 LT |
4854 | work_mask = 0; |
4855 | received = 0; | |
4361935a MC |
4856 | std_prod_idx = tpr->rx_std_prod_idx; |
4857 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 4858 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 4859 | struct ring_info *ri; |
72334482 | 4860 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
4861 | unsigned int len; |
4862 | struct sk_buff *skb; | |
4863 | dma_addr_t dma_addr; | |
4864 | u32 opaque_key, desc_idx, *post_ptr; | |
4865 | ||
4866 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4867 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4868 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 4869 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 4870 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4871 | skb = ri->skb; |
4361935a | 4872 | post_ptr = &std_prod_idx; |
f92905de | 4873 | rx_std_posted++; |
1da177e4 | 4874 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 4875 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 4876 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4877 | skb = ri->skb; |
4361935a | 4878 | post_ptr = &jmb_prod_idx; |
21f581a5 | 4879 | } else |
1da177e4 | 4880 | goto next_pkt_nopost; |
1da177e4 LT |
4881 | |
4882 | work_mask |= opaque_key; | |
4883 | ||
4884 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4885 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4886 | drop_it: | |
a3896167 | 4887 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4888 | desc_idx, *post_ptr); |
4889 | drop_it_no_recycle: | |
4890 | /* Other statistics kept track of by card. */ | |
b0057c51 | 4891 | tp->rx_dropped++; |
1da177e4 LT |
4892 | goto next_pkt; |
4893 | } | |
4894 | ||
ad829268 MC |
4895 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
4896 | ETH_FCS_LEN; | |
1da177e4 | 4897 | |
d2757fc4 | 4898 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
4899 | int skb_size; |
4900 | ||
86b21e59 | 4901 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, |
afc081f8 | 4902 | *post_ptr); |
1da177e4 LT |
4903 | if (skb_size < 0) |
4904 | goto drop_it; | |
4905 | ||
287be12e | 4906 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
4907 | PCI_DMA_FROMDEVICE); |
4908 | ||
61e800cf MC |
4909 | /* Ensure that the update to the skb happens |
4910 | * after the usage of the old DMA mapping. | |
4911 | */ | |
4912 | smp_wmb(); | |
4913 | ||
4914 | ri->skb = NULL; | |
4915 | ||
1da177e4 LT |
4916 | skb_put(skb, len); |
4917 | } else { | |
4918 | struct sk_buff *copy_skb; | |
4919 | ||
a3896167 | 4920 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4921 | desc_idx, *post_ptr); |
4922 | ||
bf933c80 | 4923 | copy_skb = netdev_alloc_skb(tp->dev, len + |
9dc7a113 | 4924 | TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4925 | if (copy_skb == NULL) |
4926 | goto drop_it_no_recycle; | |
4927 | ||
bf933c80 | 4928 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4929 | skb_put(copy_skb, len); |
4930 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 4931 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
4932 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
4933 | ||
4934 | /* We'll reuse the original ring buffer. */ | |
4935 | skb = copy_skb; | |
4936 | } | |
4937 | ||
dc668910 | 4938 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
1da177e4 LT |
4939 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
4940 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4941 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4942 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4943 | else | |
bc8acf2c | 4944 | skb_checksum_none_assert(skb); |
1da177e4 LT |
4945 | |
4946 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
4947 | |
4948 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4949 | skb->protocol != htons(ETH_P_8021Q)) { | |
4950 | dev_kfree_skb(skb); | |
b0057c51 | 4951 | goto drop_it_no_recycle; |
f7b493e0 MC |
4952 | } |
4953 | ||
9dc7a113 | 4954 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
4955 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
4956 | __vlan_hwaccel_put_tag(skb, | |
4957 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 4958 | |
bf933c80 | 4959 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 4960 | |
1da177e4 LT |
4961 | received++; |
4962 | budget--; | |
4963 | ||
4964 | next_pkt: | |
4965 | (*post_ptr)++; | |
f92905de MC |
4966 | |
4967 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
4968 | tpr->rx_std_prod_idx = std_prod_idx & |
4969 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
4970 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
4971 | tpr->rx_std_prod_idx); | |
f92905de MC |
4972 | work_mask &= ~RXD_OPAQUE_RING_STD; |
4973 | rx_std_posted = 0; | |
4974 | } | |
1da177e4 | 4975 | next_pkt_nopost: |
483ba50b | 4976 | sw_idx++; |
7cb32cf2 | 4977 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
4978 | |
4979 | /* Refresh hw_idx to see if there is new work */ | |
4980 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 4981 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
4982 | rmb(); |
4983 | } | |
1da177e4 LT |
4984 | } |
4985 | ||
4986 | /* ACK the status ring. */ | |
72334482 MC |
4987 | tnapi->rx_rcb_ptr = sw_idx; |
4988 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
4989 | |
4990 | /* Refill RX ring(s). */ | |
e4af1af9 | 4991 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { |
b196c7e4 | 4992 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
4993 | tpr->rx_std_prod_idx = std_prod_idx & |
4994 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
4995 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
4996 | tpr->rx_std_prod_idx); | |
4997 | } | |
4998 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
4999 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
5000 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
5001 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
5002 | tpr->rx_jmb_prod_idx); | |
5003 | } | |
5004 | mmiowb(); | |
5005 | } else if (work_mask) { | |
5006 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
5007 | * updated before the producer indices can be updated. | |
5008 | */ | |
5009 | smp_wmb(); | |
5010 | ||
2c49a44d MC |
5011 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
5012 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 5013 | |
e4af1af9 MC |
5014 | if (tnapi != &tp->napi[1]) |
5015 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 5016 | } |
1da177e4 LT |
5017 | |
5018 | return received; | |
5019 | } | |
5020 | ||
35f2d7d0 | 5021 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 5022 | { |
1da177e4 LT |
5023 | /* handle link change and other phy events */ |
5024 | if (!(tp->tg3_flags & | |
5025 | (TG3_FLAG_USE_LINKCHG_REG | | |
5026 | TG3_FLAG_POLL_SERDES))) { | |
35f2d7d0 MC |
5027 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
5028 | ||
1da177e4 LT |
5029 | if (sblk->status & SD_STATUS_LINK_CHG) { |
5030 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 5031 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 5032 | spin_lock(&tp->lock); |
dd477003 MC |
5033 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
5034 | tw32_f(MAC_STATUS, | |
5035 | (MAC_STATUS_SYNC_CHANGED | | |
5036 | MAC_STATUS_CFG_CHANGED | | |
5037 | MAC_STATUS_MI_COMPLETION | | |
5038 | MAC_STATUS_LNKSTATE_CHANGED)); | |
5039 | udelay(40); | |
5040 | } else | |
5041 | tg3_setup_phy(tp, 0); | |
f47c11ee | 5042 | spin_unlock(&tp->lock); |
1da177e4 LT |
5043 | } |
5044 | } | |
35f2d7d0 MC |
5045 | } |
5046 | ||
f89f38b8 MC |
5047 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
5048 | struct tg3_rx_prodring_set *dpr, | |
5049 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
5050 | { |
5051 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 5052 | int i, err = 0; |
b196c7e4 MC |
5053 | |
5054 | while (1) { | |
5055 | src_prod_idx = spr->rx_std_prod_idx; | |
5056 | ||
5057 | /* Make sure updates to the rx_std_buffers[] entries and the | |
5058 | * standard producer index are seen in the correct order. | |
5059 | */ | |
5060 | smp_rmb(); | |
5061 | ||
5062 | if (spr->rx_std_cons_idx == src_prod_idx) | |
5063 | break; | |
5064 | ||
5065 | if (spr->rx_std_cons_idx < src_prod_idx) | |
5066 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
5067 | else | |
2c49a44d MC |
5068 | cpycnt = tp->rx_std_ring_mask + 1 - |
5069 | spr->rx_std_cons_idx; | |
b196c7e4 | 5070 | |
2c49a44d MC |
5071 | cpycnt = min(cpycnt, |
5072 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
5073 | |
5074 | si = spr->rx_std_cons_idx; | |
5075 | di = dpr->rx_std_prod_idx; | |
5076 | ||
e92967bf MC |
5077 | for (i = di; i < di + cpycnt; i++) { |
5078 | if (dpr->rx_std_buffers[i].skb) { | |
5079 | cpycnt = i - di; | |
f89f38b8 | 5080 | err = -ENOSPC; |
e92967bf MC |
5081 | break; |
5082 | } | |
5083 | } | |
5084 | ||
5085 | if (!cpycnt) | |
5086 | break; | |
5087 | ||
5088 | /* Ensure that updates to the rx_std_buffers ring and the | |
5089 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5090 | * ordered correctly WRT the skb check above. | |
5091 | */ | |
5092 | smp_rmb(); | |
5093 | ||
b196c7e4 MC |
5094 | memcpy(&dpr->rx_std_buffers[di], |
5095 | &spr->rx_std_buffers[si], | |
5096 | cpycnt * sizeof(struct ring_info)); | |
5097 | ||
5098 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5099 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5100 | sbd = &spr->rx_std[si]; | |
5101 | dbd = &dpr->rx_std[di]; | |
5102 | dbd->addr_hi = sbd->addr_hi; | |
5103 | dbd->addr_lo = sbd->addr_lo; | |
5104 | } | |
5105 | ||
2c49a44d MC |
5106 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
5107 | tp->rx_std_ring_mask; | |
5108 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
5109 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
5110 | } |
5111 | ||
5112 | while (1) { | |
5113 | src_prod_idx = spr->rx_jmb_prod_idx; | |
5114 | ||
5115 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
5116 | * the jumbo producer index are seen in the correct order. | |
5117 | */ | |
5118 | smp_rmb(); | |
5119 | ||
5120 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
5121 | break; | |
5122 | ||
5123 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
5124 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
5125 | else | |
2c49a44d MC |
5126 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
5127 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
5128 | |
5129 | cpycnt = min(cpycnt, | |
2c49a44d | 5130 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
5131 | |
5132 | si = spr->rx_jmb_cons_idx; | |
5133 | di = dpr->rx_jmb_prod_idx; | |
5134 | ||
e92967bf MC |
5135 | for (i = di; i < di + cpycnt; i++) { |
5136 | if (dpr->rx_jmb_buffers[i].skb) { | |
5137 | cpycnt = i - di; | |
f89f38b8 | 5138 | err = -ENOSPC; |
e92967bf MC |
5139 | break; |
5140 | } | |
5141 | } | |
5142 | ||
5143 | if (!cpycnt) | |
5144 | break; | |
5145 | ||
5146 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
5147 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5148 | * ordered correctly WRT the skb check above. | |
5149 | */ | |
5150 | smp_rmb(); | |
5151 | ||
b196c7e4 MC |
5152 | memcpy(&dpr->rx_jmb_buffers[di], |
5153 | &spr->rx_jmb_buffers[si], | |
5154 | cpycnt * sizeof(struct ring_info)); | |
5155 | ||
5156 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5157 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5158 | sbd = &spr->rx_jmb[si].std; | |
5159 | dbd = &dpr->rx_jmb[di].std; | |
5160 | dbd->addr_hi = sbd->addr_hi; | |
5161 | dbd->addr_lo = sbd->addr_lo; | |
5162 | } | |
5163 | ||
2c49a44d MC |
5164 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
5165 | tp->rx_jmb_ring_mask; | |
5166 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5167 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 5168 | } |
f89f38b8 MC |
5169 | |
5170 | return err; | |
b196c7e4 MC |
5171 | } |
5172 | ||
35f2d7d0 MC |
5173 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
5174 | { | |
5175 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
5176 | |
5177 | /* run TX completion thread */ | |
f3f3f27e | 5178 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 5179 | tg3_tx(tnapi); |
6f535763 | 5180 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) |
4fd7ab59 | 5181 | return work_done; |
1da177e4 LT |
5182 | } |
5183 | ||
1da177e4 LT |
5184 | /* run RX thread, within the bounds set by NAPI. |
5185 | * All RX "locking" is done by ensuring outside | |
bea3348e | 5186 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 5187 | */ |
8d9d7cfc | 5188 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 5189 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 5190 | |
b196c7e4 | 5191 | if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 5192 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 5193 | int i, err = 0; |
e4af1af9 MC |
5194 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
5195 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 5196 | |
e4af1af9 | 5197 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 5198 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 5199 | &tp->napi[i].prodring); |
b196c7e4 MC |
5200 | |
5201 | wmb(); | |
5202 | ||
e4af1af9 MC |
5203 | if (std_prod_idx != dpr->rx_std_prod_idx) |
5204 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5205 | dpr->rx_std_prod_idx); | |
b196c7e4 | 5206 | |
e4af1af9 MC |
5207 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
5208 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5209 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
5210 | |
5211 | mmiowb(); | |
f89f38b8 MC |
5212 | |
5213 | if (err) | |
5214 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
5215 | } |
5216 | ||
6f535763 DM |
5217 | return work_done; |
5218 | } | |
5219 | ||
35f2d7d0 MC |
5220 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5221 | { | |
5222 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5223 | struct tg3 *tp = tnapi->tp; | |
5224 | int work_done = 0; | |
5225 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5226 | ||
5227 | while (1) { | |
5228 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5229 | ||
5230 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5231 | goto tx_recovery; | |
5232 | ||
5233 | if (unlikely(work_done >= budget)) | |
5234 | break; | |
5235 | ||
c6cdf436 | 5236 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5237 | * to tell the hw how much work has been processed, |
5238 | * so we must read it before checking for more work. | |
5239 | */ | |
5240 | tnapi->last_tag = sblk->status_tag; | |
5241 | tnapi->last_irq_tag = tnapi->last_tag; | |
5242 | rmb(); | |
5243 | ||
5244 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5245 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5246 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5247 | napi_complete(napi); |
5248 | /* Reenable interrupts. */ | |
5249 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5250 | mmiowb(); | |
5251 | break; | |
5252 | } | |
5253 | } | |
5254 | ||
5255 | return work_done; | |
5256 | ||
5257 | tx_recovery: | |
5258 | /* work_done is guaranteed to be less than budget. */ | |
5259 | napi_complete(napi); | |
5260 | schedule_work(&tp->reset_task); | |
5261 | return work_done; | |
5262 | } | |
5263 | ||
e64de4e6 MC |
5264 | static void tg3_process_error(struct tg3 *tp) |
5265 | { | |
5266 | u32 val; | |
5267 | bool real_error = false; | |
5268 | ||
5269 | if (tp->tg3_flags & TG3_FLAG_ERROR_PROCESSED) | |
5270 | return; | |
5271 | ||
5272 | /* Check Flow Attention register */ | |
5273 | val = tr32(HOSTCC_FLOW_ATTN); | |
5274 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { | |
5275 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); | |
5276 | real_error = true; | |
5277 | } | |
5278 | ||
5279 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { | |
5280 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); | |
5281 | real_error = true; | |
5282 | } | |
5283 | ||
5284 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { | |
5285 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); | |
5286 | real_error = true; | |
5287 | } | |
5288 | ||
5289 | if (!real_error) | |
5290 | return; | |
5291 | ||
5292 | tg3_dump_state(tp); | |
5293 | ||
5294 | tp->tg3_flags |= TG3_FLAG_ERROR_PROCESSED; | |
5295 | schedule_work(&tp->reset_task); | |
5296 | } | |
5297 | ||
6f535763 DM |
5298 | static int tg3_poll(struct napi_struct *napi, int budget) |
5299 | { | |
8ef0442f MC |
5300 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
5301 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 5302 | int work_done = 0; |
898a56f8 | 5303 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
5304 | |
5305 | while (1) { | |
e64de4e6 MC |
5306 | if (sblk->status & SD_STATUS_ERROR) |
5307 | tg3_process_error(tp); | |
5308 | ||
35f2d7d0 MC |
5309 | tg3_poll_link(tp); |
5310 | ||
17375d25 | 5311 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 DM |
5312 | |
5313 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5314 | goto tx_recovery; | |
5315 | ||
5316 | if (unlikely(work_done >= budget)) | |
5317 | break; | |
5318 | ||
4fd7ab59 | 5319 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { |
17375d25 | 5320 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
5321 | * to tell the hw how much work has been processed, |
5322 | * so we must read it before checking for more work. | |
5323 | */ | |
898a56f8 MC |
5324 | tnapi->last_tag = sblk->status_tag; |
5325 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
5326 | rmb(); |
5327 | } else | |
5328 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 5329 | |
17375d25 | 5330 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 5331 | napi_complete(napi); |
17375d25 | 5332 | tg3_int_reenable(tnapi); |
6f535763 DM |
5333 | break; |
5334 | } | |
1da177e4 LT |
5335 | } |
5336 | ||
bea3348e | 5337 | return work_done; |
6f535763 DM |
5338 | |
5339 | tx_recovery: | |
4fd7ab59 | 5340 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 5341 | napi_complete(napi); |
6f535763 | 5342 | schedule_work(&tp->reset_task); |
4fd7ab59 | 5343 | return work_done; |
1da177e4 LT |
5344 | } |
5345 | ||
66cfd1bd MC |
5346 | static void tg3_napi_disable(struct tg3 *tp) |
5347 | { | |
5348 | int i; | |
5349 | ||
5350 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
5351 | napi_disable(&tp->napi[i].napi); | |
5352 | } | |
5353 | ||
5354 | static void tg3_napi_enable(struct tg3 *tp) | |
5355 | { | |
5356 | int i; | |
5357 | ||
5358 | for (i = 0; i < tp->irq_cnt; i++) | |
5359 | napi_enable(&tp->napi[i].napi); | |
5360 | } | |
5361 | ||
5362 | static void tg3_napi_init(struct tg3 *tp) | |
5363 | { | |
5364 | int i; | |
5365 | ||
5366 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
5367 | for (i = 1; i < tp->irq_cnt; i++) | |
5368 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
5369 | } | |
5370 | ||
5371 | static void tg3_napi_fini(struct tg3 *tp) | |
5372 | { | |
5373 | int i; | |
5374 | ||
5375 | for (i = 0; i < tp->irq_cnt; i++) | |
5376 | netif_napi_del(&tp->napi[i].napi); | |
5377 | } | |
5378 | ||
5379 | static inline void tg3_netif_stop(struct tg3 *tp) | |
5380 | { | |
5381 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5382 | tg3_napi_disable(tp); | |
5383 | netif_tx_disable(tp->dev); | |
5384 | } | |
5385 | ||
5386 | static inline void tg3_netif_start(struct tg3 *tp) | |
5387 | { | |
5388 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
5389 | * appropriate so long as all callers are assured to | |
5390 | * have free tx slots (such as after tg3_init_hw) | |
5391 | */ | |
5392 | netif_tx_wake_all_queues(tp->dev); | |
5393 | ||
5394 | tg3_napi_enable(tp); | |
5395 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
5396 | tg3_enable_ints(tp); | |
5397 | } | |
5398 | ||
f47c11ee DM |
5399 | static void tg3_irq_quiesce(struct tg3 *tp) |
5400 | { | |
4f125f42 MC |
5401 | int i; |
5402 | ||
f47c11ee DM |
5403 | BUG_ON(tp->irq_sync); |
5404 | ||
5405 | tp->irq_sync = 1; | |
5406 | smp_mb(); | |
5407 | ||
4f125f42 MC |
5408 | for (i = 0; i < tp->irq_cnt; i++) |
5409 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
5410 | } |
5411 | ||
f47c11ee DM |
5412 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
5413 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5414 | * with as well. Most of the time, this is not necessary except when | |
5415 | * shutting down the device. | |
5416 | */ | |
5417 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5418 | { | |
46966545 | 5419 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
5420 | if (irq_sync) |
5421 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
5422 | } |
5423 | ||
5424 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5425 | { | |
f47c11ee DM |
5426 | spin_unlock_bh(&tp->lock); |
5427 | } | |
5428 | ||
fcfa0a32 MC |
5429 | /* One-shot MSI handler - Chip automatically disables interrupt |
5430 | * after sending MSI so driver doesn't have to do it. | |
5431 | */ | |
7d12e780 | 5432 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 5433 | { |
09943a18 MC |
5434 | struct tg3_napi *tnapi = dev_id; |
5435 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 5436 | |
898a56f8 | 5437 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5438 | if (tnapi->rx_rcb) |
5439 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
5440 | |
5441 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 5442 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
5443 | |
5444 | return IRQ_HANDLED; | |
5445 | } | |
5446 | ||
88b06bc2 MC |
5447 | /* MSI ISR - No need to check for interrupt sharing and no need to |
5448 | * flush status block and interrupt mailbox. PCI ordering rules | |
5449 | * guarantee that MSI will arrive after the status block. | |
5450 | */ | |
7d12e780 | 5451 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 5452 | { |
09943a18 MC |
5453 | struct tg3_napi *tnapi = dev_id; |
5454 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 5455 | |
898a56f8 | 5456 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5457 | if (tnapi->rx_rcb) |
5458 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 5459 | /* |
fac9b83e | 5460 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 5461 | * chip-internal interrupt pending events. |
fac9b83e | 5462 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
5463 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
5464 | * event coalescing. | |
5465 | */ | |
5466 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 5467 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 5468 | napi_schedule(&tnapi->napi); |
61487480 | 5469 | |
88b06bc2 MC |
5470 | return IRQ_RETVAL(1); |
5471 | } | |
5472 | ||
7d12e780 | 5473 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 5474 | { |
09943a18 MC |
5475 | struct tg3_napi *tnapi = dev_id; |
5476 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5477 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
5478 | unsigned int handled = 1; |
5479 | ||
1da177e4 LT |
5480 | /* In INTx mode, it is possible for the interrupt to arrive at |
5481 | * the CPU before the status block posted prior to the interrupt. | |
5482 | * Reading the PCI State register will confirm whether the | |
5483 | * interrupt is ours and will flush the status block. | |
5484 | */ | |
d18edcb2 MC |
5485 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
5486 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
5487 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5488 | handled = 0; | |
f47c11ee | 5489 | goto out; |
fac9b83e | 5490 | } |
d18edcb2 MC |
5491 | } |
5492 | ||
5493 | /* | |
5494 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5495 | * chip-internal interrupt pending events. | |
5496 | * Writing non-zero to intr-mbox-0 additional tells the | |
5497 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5498 | * event coalescing. | |
c04cb347 MC |
5499 | * |
5500 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5501 | * spurious interrupts. The flush impacts performance but | |
5502 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5503 | */ |
c04cb347 | 5504 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
5505 | if (tg3_irq_sync(tp)) |
5506 | goto out; | |
5507 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 5508 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 5509 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 5510 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
5511 | } else { |
5512 | /* No work, shared interrupt perhaps? re-enable | |
5513 | * interrupts, and flush that PCI write | |
5514 | */ | |
5515 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5516 | 0x00000000); | |
fac9b83e | 5517 | } |
f47c11ee | 5518 | out: |
fac9b83e DM |
5519 | return IRQ_RETVAL(handled); |
5520 | } | |
5521 | ||
7d12e780 | 5522 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 5523 | { |
09943a18 MC |
5524 | struct tg3_napi *tnapi = dev_id; |
5525 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5526 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
5527 | unsigned int handled = 1; |
5528 | ||
fac9b83e DM |
5529 | /* In INTx mode, it is possible for the interrupt to arrive at |
5530 | * the CPU before the status block posted prior to the interrupt. | |
5531 | * Reading the PCI State register will confirm whether the | |
5532 | * interrupt is ours and will flush the status block. | |
5533 | */ | |
898a56f8 | 5534 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
d18edcb2 MC |
5535 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || |
5536 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5537 | handled = 0; | |
f47c11ee | 5538 | goto out; |
1da177e4 | 5539 | } |
d18edcb2 MC |
5540 | } |
5541 | ||
5542 | /* | |
5543 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5544 | * chip-internal interrupt pending events. | |
5545 | * writing non-zero to intr-mbox-0 additional tells the | |
5546 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5547 | * event coalescing. | |
c04cb347 MC |
5548 | * |
5549 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5550 | * spurious interrupts. The flush impacts performance but | |
5551 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5552 | */ |
c04cb347 | 5553 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
5554 | |
5555 | /* | |
5556 | * In a shared interrupt configuration, sometimes other devices' | |
5557 | * interrupts will scream. We record the current status tag here | |
5558 | * so that the above check can report that the screaming interrupts | |
5559 | * are unhandled. Eventually they will be silenced. | |
5560 | */ | |
898a56f8 | 5561 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 5562 | |
d18edcb2 MC |
5563 | if (tg3_irq_sync(tp)) |
5564 | goto out; | |
624f8e50 | 5565 | |
72334482 | 5566 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 5567 | |
09943a18 | 5568 | napi_schedule(&tnapi->napi); |
624f8e50 | 5569 | |
f47c11ee | 5570 | out: |
1da177e4 LT |
5571 | return IRQ_RETVAL(handled); |
5572 | } | |
5573 | ||
7938109f | 5574 | /* ISR for interrupt test */ |
7d12e780 | 5575 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 5576 | { |
09943a18 MC |
5577 | struct tg3_napi *tnapi = dev_id; |
5578 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5579 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 5580 | |
f9804ddb MC |
5581 | if ((sblk->status & SD_STATUS_UPDATED) || |
5582 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 5583 | tg3_disable_ints(tp); |
7938109f MC |
5584 | return IRQ_RETVAL(1); |
5585 | } | |
5586 | return IRQ_RETVAL(0); | |
5587 | } | |
5588 | ||
8e7a22e3 | 5589 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 5590 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 5591 | |
b9ec6c1b MC |
5592 | /* Restart hardware after configuration changes, self-test, etc. |
5593 | * Invoked with tp->lock held. | |
5594 | */ | |
5595 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
5596 | __releases(tp->lock) |
5597 | __acquires(tp->lock) | |
b9ec6c1b MC |
5598 | { |
5599 | int err; | |
5600 | ||
5601 | err = tg3_init_hw(tp, reset_phy); | |
5602 | if (err) { | |
5129c3a3 MC |
5603 | netdev_err(tp->dev, |
5604 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
5605 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
5606 | tg3_full_unlock(tp); | |
5607 | del_timer_sync(&tp->timer); | |
5608 | tp->irq_sync = 0; | |
fed97810 | 5609 | tg3_napi_enable(tp); |
b9ec6c1b MC |
5610 | dev_close(tp->dev); |
5611 | tg3_full_lock(tp, 0); | |
5612 | } | |
5613 | return err; | |
5614 | } | |
5615 | ||
1da177e4 LT |
5616 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5617 | static void tg3_poll_controller(struct net_device *dev) | |
5618 | { | |
4f125f42 | 5619 | int i; |
88b06bc2 MC |
5620 | struct tg3 *tp = netdev_priv(dev); |
5621 | ||
4f125f42 | 5622 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 5623 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
5624 | } |
5625 | #endif | |
5626 | ||
c4028958 | 5627 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 5628 | { |
c4028958 | 5629 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 5630 | int err; |
1da177e4 LT |
5631 | unsigned int restart_timer; |
5632 | ||
7faa006f | 5633 | tg3_full_lock(tp, 0); |
7faa006f MC |
5634 | |
5635 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
5636 | tg3_full_unlock(tp); |
5637 | return; | |
5638 | } | |
5639 | ||
5640 | tg3_full_unlock(tp); | |
5641 | ||
b02fd9e3 MC |
5642 | tg3_phy_stop(tp); |
5643 | ||
1da177e4 LT |
5644 | tg3_netif_stop(tp); |
5645 | ||
f47c11ee | 5646 | tg3_full_lock(tp, 1); |
1da177e4 LT |
5647 | |
5648 | restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; | |
5649 | tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; | |
5650 | ||
df3e6548 MC |
5651 | if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { |
5652 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
5653 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
5654 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
5655 | tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; | |
5656 | } | |
5657 | ||
944d980e | 5658 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
5659 | err = tg3_init_hw(tp, 1); |
5660 | if (err) | |
b9ec6c1b | 5661 | goto out; |
1da177e4 LT |
5662 | |
5663 | tg3_netif_start(tp); | |
5664 | ||
1da177e4 LT |
5665 | if (restart_timer) |
5666 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 5667 | |
b9ec6c1b | 5668 | out: |
7faa006f | 5669 | tg3_full_unlock(tp); |
b02fd9e3 MC |
5670 | |
5671 | if (!err) | |
5672 | tg3_phy_start(tp); | |
1da177e4 LT |
5673 | } |
5674 | ||
5675 | static void tg3_tx_timeout(struct net_device *dev) | |
5676 | { | |
5677 | struct tg3 *tp = netdev_priv(dev); | |
5678 | ||
b0408751 | 5679 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 5680 | netdev_err(dev, "transmit timed out, resetting\n"); |
97bd8e49 | 5681 | tg3_dump_state(tp); |
b0408751 | 5682 | } |
1da177e4 LT |
5683 | |
5684 | schedule_work(&tp->reset_task); | |
5685 | } | |
5686 | ||
c58ec932 MC |
5687 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5688 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5689 | { | |
5690 | u32 base = (u32) mapping & 0xffffffff; | |
5691 | ||
807540ba | 5692 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
5693 | } |
5694 | ||
72f2afb8 MC |
5695 | /* Test for DMA addresses > 40-bit */ |
5696 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5697 | int len) | |
5698 | { | |
5699 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
6728a8e2 | 5700 | if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) |
807540ba | 5701 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
5702 | return 0; |
5703 | #else | |
5704 | return 0; | |
5705 | #endif | |
5706 | } | |
5707 | ||
f3f3f27e | 5708 | static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32); |
1da177e4 | 5709 | |
72f2afb8 | 5710 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 MC |
5711 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
5712 | struct sk_buff *skb, u32 last_plus_one, | |
5713 | u32 *start, u32 base_flags, u32 mss) | |
1da177e4 | 5714 | { |
24f4efd4 | 5715 | struct tg3 *tp = tnapi->tp; |
41588ba1 | 5716 | struct sk_buff *new_skb; |
c58ec932 | 5717 | dma_addr_t new_addr = 0; |
1da177e4 | 5718 | u32 entry = *start; |
c58ec932 | 5719 | int i, ret = 0; |
1da177e4 | 5720 | |
41588ba1 MC |
5721 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
5722 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5723 | else { | |
5724 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5725 | ||
5726 | new_skb = skb_copy_expand(skb, | |
5727 | skb_headroom(skb) + more_headroom, | |
5728 | skb_tailroom(skb), GFP_ATOMIC); | |
5729 | } | |
5730 | ||
1da177e4 | 5731 | if (!new_skb) { |
c58ec932 MC |
5732 | ret = -1; |
5733 | } else { | |
5734 | /* New SKB is guaranteed to be linear. */ | |
5735 | entry = *start; | |
f4188d8a AD |
5736 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
5737 | PCI_DMA_TODEVICE); | |
5738 | /* Make sure the mapping succeeded */ | |
5739 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
5740 | ret = -1; | |
5741 | dev_kfree_skb(new_skb); | |
5742 | new_skb = NULL; | |
90079ce8 | 5743 | |
c58ec932 MC |
5744 | /* Make sure new skb does not cross any 4G boundaries. |
5745 | * Drop the packet if it does. | |
5746 | */ | |
f4188d8a AD |
5747 | } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5748 | tg3_4g_overflow_test(new_addr, new_skb->len)) { | |
5749 | pci_unmap_single(tp->pdev, new_addr, new_skb->len, | |
5750 | PCI_DMA_TODEVICE); | |
c58ec932 MC |
5751 | ret = -1; |
5752 | dev_kfree_skb(new_skb); | |
5753 | new_skb = NULL; | |
5754 | } else { | |
f3f3f27e | 5755 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, |
c58ec932 MC |
5756 | base_flags, 1 | (mss << 1)); |
5757 | *start = NEXT_TX(entry); | |
5758 | } | |
1da177e4 LT |
5759 | } |
5760 | ||
1da177e4 LT |
5761 | /* Now clean up the sw ring entries. */ |
5762 | i = 0; | |
5763 | while (entry != last_plus_one) { | |
f4188d8a AD |
5764 | int len; |
5765 | ||
f3f3f27e | 5766 | if (i == 0) |
f4188d8a | 5767 | len = skb_headlen(skb); |
f3f3f27e | 5768 | else |
f4188d8a AD |
5769 | len = skb_shinfo(skb)->frags[i-1].size; |
5770 | ||
5771 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 5772 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
5773 | mapping), |
5774 | len, PCI_DMA_TODEVICE); | |
5775 | if (i == 0) { | |
5776 | tnapi->tx_buffers[entry].skb = new_skb; | |
4e5e4f0d | 5777 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
5778 | new_addr); |
5779 | } else { | |
f3f3f27e | 5780 | tnapi->tx_buffers[entry].skb = NULL; |
f4188d8a | 5781 | } |
1da177e4 LT |
5782 | entry = NEXT_TX(entry); |
5783 | i++; | |
5784 | } | |
5785 | ||
5786 | dev_kfree_skb(skb); | |
5787 | ||
c58ec932 | 5788 | return ret; |
1da177e4 LT |
5789 | } |
5790 | ||
f3f3f27e | 5791 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, |
1da177e4 LT |
5792 | dma_addr_t mapping, int len, u32 flags, |
5793 | u32 mss_and_is_end) | |
5794 | { | |
f3f3f27e | 5795 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; |
1da177e4 LT |
5796 | int is_end = (mss_and_is_end & 0x1); |
5797 | u32 mss = (mss_and_is_end >> 1); | |
5798 | u32 vlan_tag = 0; | |
5799 | ||
5800 | if (is_end) | |
5801 | flags |= TXD_FLAG_END; | |
5802 | if (flags & TXD_FLAG_VLAN) { | |
5803 | vlan_tag = flags >> 16; | |
5804 | flags &= 0xffff; | |
5805 | } | |
5806 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5807 | ||
5808 | txd->addr_hi = ((u64) mapping >> 32); | |
5809 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5810 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5811 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5812 | } | |
5813 | ||
5a6f3074 | 5814 | /* hard_start_xmit for devices that don't have any bugs and |
e849cdc3 | 5815 | * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only. |
5a6f3074 | 5816 | */ |
61357325 SH |
5817 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, |
5818 | struct net_device *dev) | |
5a6f3074 MC |
5819 | { |
5820 | struct tg3 *tp = netdev_priv(dev); | |
5a6f3074 | 5821 | u32 len, entry, base_flags, mss; |
90079ce8 | 5822 | dma_addr_t mapping; |
fe5f5787 MC |
5823 | struct tg3_napi *tnapi; |
5824 | struct netdev_queue *txq; | |
f4188d8a AD |
5825 | unsigned int i, last; |
5826 | ||
fe5f5787 MC |
5827 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5828 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 5829 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 | 5830 | tnapi++; |
5a6f3074 | 5831 | |
00b70504 | 5832 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5833 | * and TX reclaim runs via tp->napi.poll inside of a software |
5a6f3074 MC |
5834 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5835 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5836 | */ | |
f3f3f27e | 5837 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
fe5f5787 MC |
5838 | if (!netif_tx_queue_stopped(txq)) { |
5839 | netif_tx_stop_queue(txq); | |
5a6f3074 MC |
5840 | |
5841 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
5842 | netdev_err(dev, |
5843 | "BUG! Tx Ring full when queue awake!\n"); | |
5a6f3074 | 5844 | } |
5a6f3074 MC |
5845 | return NETDEV_TX_BUSY; |
5846 | } | |
5847 | ||
f3f3f27e | 5848 | entry = tnapi->tx_prod; |
5a6f3074 | 5849 | base_flags = 0; |
be98da6a MC |
5850 | mss = skb_shinfo(skb)->gso_size; |
5851 | if (mss) { | |
5a6f3074 | 5852 | int tcp_opt_len, ip_tcp_len; |
f6eb9b1f | 5853 | u32 hdrlen; |
5a6f3074 MC |
5854 | |
5855 | if (skb_header_cloned(skb) && | |
5856 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5857 | dev_kfree_skb(skb); | |
5858 | goto out_unlock; | |
5859 | } | |
5860 | ||
02e96080 | 5861 | if (skb_is_gso_v6(skb)) { |
f6eb9b1f | 5862 | hdrlen = skb_headlen(skb) - ETH_HLEN; |
02e96080 | 5863 | } else { |
eddc9ec5 ACM |
5864 | struct iphdr *iph = ip_hdr(skb); |
5865 | ||
ab6a5bb6 | 5866 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5867 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
b0026624 | 5868 | |
eddc9ec5 ACM |
5869 | iph->check = 0; |
5870 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
f6eb9b1f | 5871 | hdrlen = ip_tcp_len + tcp_opt_len; |
b0026624 | 5872 | } |
5a6f3074 | 5873 | |
e849cdc3 | 5874 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
f6eb9b1f MC |
5875 | mss |= (hdrlen & 0xc) << 12; |
5876 | if (hdrlen & 0x10) | |
5877 | base_flags |= 0x00000010; | |
5878 | base_flags |= (hdrlen & 0x3e0) << 5; | |
5879 | } else | |
5880 | mss |= hdrlen << 9; | |
5881 | ||
5a6f3074 MC |
5882 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5883 | TXD_FLAG_CPU_POST_DMA); | |
5884 | ||
aa8223c7 | 5885 | tcp_hdr(skb)->check = 0; |
5a6f3074 | 5886 | |
859a5887 | 5887 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
5a6f3074 | 5888 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
859a5887 MC |
5889 | } |
5890 | ||
eab6d18d | 5891 | if (vlan_tx_tag_present(skb)) |
5a6f3074 MC |
5892 | base_flags |= (TXD_FLAG_VLAN | |
5893 | (vlan_tx_tag_get(skb) << 16)); | |
5a6f3074 | 5894 | |
f4188d8a AD |
5895 | len = skb_headlen(skb); |
5896 | ||
5897 | /* Queue skb data, a.k.a. the main skb fragment. */ | |
5898 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5899 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
5900 | dev_kfree_skb(skb); |
5901 | goto out_unlock; | |
5902 | } | |
5903 | ||
f3f3f27e | 5904 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 5905 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
fe5f5787 | 5906 | |
b703df6f | 5907 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
8fc2f995 | 5908 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
f6eb9b1f MC |
5909 | base_flags |= TXD_FLAG_JMB_PKT; |
5910 | ||
f3f3f27e | 5911 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
5a6f3074 MC |
5912 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5913 | ||
5914 | entry = NEXT_TX(entry); | |
5915 | ||
5916 | /* Now loop through additional data fragments, and queue them. */ | |
5917 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5a6f3074 MC |
5918 | last = skb_shinfo(skb)->nr_frags - 1; |
5919 | for (i = 0; i <= last; i++) { | |
5920 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5921 | ||
5922 | len = frag->size; | |
f4188d8a AD |
5923 | mapping = pci_map_page(tp->pdev, |
5924 | frag->page, | |
5925 | frag->page_offset, | |
5926 | len, PCI_DMA_TODEVICE); | |
5927 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
5928 | goto dma_error; | |
5929 | ||
f3f3f27e | 5930 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 5931 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a | 5932 | mapping); |
5a6f3074 | 5933 | |
f3f3f27e | 5934 | tg3_set_txd(tnapi, entry, mapping, len, |
5a6f3074 MC |
5935 | base_flags, (i == last) | (mss << 1)); |
5936 | ||
5937 | entry = NEXT_TX(entry); | |
5938 | } | |
5939 | } | |
5940 | ||
5941 | /* Packets are ready, update Tx producer idx local and on card. */ | |
f3f3f27e | 5942 | tw32_tx_mbox(tnapi->prodmbox, entry); |
5a6f3074 | 5943 | |
f3f3f27e MC |
5944 | tnapi->tx_prod = entry; |
5945 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
fe5f5787 | 5946 | netif_tx_stop_queue(txq); |
f65aac16 MC |
5947 | |
5948 | /* netif_tx_stop_queue() must be done before checking | |
5949 | * checking tx index in tg3_tx_avail() below, because in | |
5950 | * tg3_tx(), we update tx index before checking for | |
5951 | * netif_tx_queue_stopped(). | |
5952 | */ | |
5953 | smp_mb(); | |
f3f3f27e | 5954 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
fe5f5787 | 5955 | netif_tx_wake_queue(txq); |
5a6f3074 MC |
5956 | } |
5957 | ||
5958 | out_unlock: | |
cdd0db05 | 5959 | mmiowb(); |
5a6f3074 MC |
5960 | |
5961 | return NETDEV_TX_OK; | |
f4188d8a AD |
5962 | |
5963 | dma_error: | |
5964 | last = i; | |
5965 | entry = tnapi->tx_prod; | |
5966 | tnapi->tx_buffers[entry].skb = NULL; | |
5967 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 5968 | dma_unmap_addr(&tnapi->tx_buffers[entry], mapping), |
f4188d8a AD |
5969 | skb_headlen(skb), |
5970 | PCI_DMA_TODEVICE); | |
5971 | for (i = 0; i <= last; i++) { | |
5972 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5973 | entry = NEXT_TX(entry); | |
5974 | ||
5975 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 5976 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
5977 | mapping), |
5978 | frag->size, PCI_DMA_TODEVICE); | |
5979 | } | |
5980 | ||
5981 | dev_kfree_skb(skb); | |
5982 | return NETDEV_TX_OK; | |
5a6f3074 MC |
5983 | } |
5984 | ||
61357325 SH |
5985 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *, |
5986 | struct net_device *); | |
52c0fd83 MC |
5987 | |
5988 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5989 | * TSO header is greater than 80 bytes. | |
5990 | */ | |
5991 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5992 | { | |
5993 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 5994 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
5995 | |
5996 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 5997 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 5998 | netif_stop_queue(tp->dev); |
f65aac16 MC |
5999 | |
6000 | /* netif_tx_stop_queue() must be done before checking | |
6001 | * checking tx index in tg3_tx_avail() below, because in | |
6002 | * tg3_tx(), we update tx index before checking for | |
6003 | * netif_tx_queue_stopped(). | |
6004 | */ | |
6005 | smp_mb(); | |
f3f3f27e | 6006 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
6007 | return NETDEV_TX_BUSY; |
6008 | ||
6009 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
6010 | } |
6011 | ||
6012 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 6013 | if (IS_ERR(segs)) |
52c0fd83 MC |
6014 | goto tg3_tso_bug_end; |
6015 | ||
6016 | do { | |
6017 | nskb = segs; | |
6018 | segs = segs->next; | |
6019 | nskb->next = NULL; | |
6020 | tg3_start_xmit_dma_bug(nskb, tp->dev); | |
6021 | } while (segs); | |
6022 | ||
6023 | tg3_tso_bug_end: | |
6024 | dev_kfree_skb(skb); | |
6025 | ||
6026 | return NETDEV_TX_OK; | |
6027 | } | |
52c0fd83 | 6028 | |
5a6f3074 MC |
6029 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
6030 | * support TG3_FLG2_HW_TSO_1 or firmware TSO only. | |
6031 | */ | |
61357325 SH |
6032 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb, |
6033 | struct net_device *dev) | |
1da177e4 LT |
6034 | { |
6035 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 LT |
6036 | u32 len, entry, base_flags, mss; |
6037 | int would_hit_hwbug; | |
90079ce8 | 6038 | dma_addr_t mapping; |
24f4efd4 MC |
6039 | struct tg3_napi *tnapi; |
6040 | struct netdev_queue *txq; | |
f4188d8a AD |
6041 | unsigned int i, last; |
6042 | ||
24f4efd4 MC |
6043 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
6044 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 6045 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
24f4efd4 | 6046 | tnapi++; |
1da177e4 | 6047 | |
00b70504 | 6048 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 6049 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
6050 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
6051 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 6052 | */ |
f3f3f27e | 6053 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
6054 | if (!netif_tx_queue_stopped(txq)) { |
6055 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
6056 | |
6057 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
6058 | netdev_err(dev, |
6059 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 6060 | } |
1da177e4 LT |
6061 | return NETDEV_TX_BUSY; |
6062 | } | |
6063 | ||
f3f3f27e | 6064 | entry = tnapi->tx_prod; |
1da177e4 | 6065 | base_flags = 0; |
84fa7933 | 6066 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 6067 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 6068 | |
be98da6a MC |
6069 | mss = skb_shinfo(skb)->gso_size; |
6070 | if (mss) { | |
eddc9ec5 | 6071 | struct iphdr *iph; |
34195c3d | 6072 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
6073 | |
6074 | if (skb_header_cloned(skb) && | |
6075 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
6076 | dev_kfree_skb(skb); | |
6077 | goto out_unlock; | |
6078 | } | |
6079 | ||
34195c3d | 6080 | iph = ip_hdr(skb); |
ab6a5bb6 | 6081 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 6082 | |
02e96080 | 6083 | if (skb_is_gso_v6(skb)) { |
34195c3d MC |
6084 | hdr_len = skb_headlen(skb) - ETH_HLEN; |
6085 | } else { | |
6086 | u32 ip_tcp_len; | |
6087 | ||
6088 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
6089 | hdr_len = ip_tcp_len + tcp_opt_len; | |
6090 | ||
6091 | iph->check = 0; | |
6092 | iph->tot_len = htons(mss + hdr_len); | |
6093 | } | |
6094 | ||
52c0fd83 | 6095 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
7f62ad5d | 6096 | (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) |
de6f31eb | 6097 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 6098 | |
1da177e4 LT |
6099 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
6100 | TXD_FLAG_CPU_POST_DMA); | |
6101 | ||
1da177e4 | 6102 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { |
aa8223c7 | 6103 | tcp_hdr(skb)->check = 0; |
1da177e4 | 6104 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
6105 | } else |
6106 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6107 | iph->daddr, 0, | |
6108 | IPPROTO_TCP, | |
6109 | 0); | |
1da177e4 | 6110 | |
615774fe MC |
6111 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
6112 | mss |= (hdr_len & 0xc) << 12; | |
6113 | if (hdr_len & 0x10) | |
6114 | base_flags |= 0x00000010; | |
6115 | base_flags |= (hdr_len & 0x3e0) << 5; | |
6116 | } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) | |
92c6b8d1 MC |
6117 | mss |= hdr_len << 9; |
6118 | else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) || | |
6119 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
eddc9ec5 | 6120 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6121 | int tsflags; |
6122 | ||
eddc9ec5 | 6123 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6124 | mss |= (tsflags << 11); |
6125 | } | |
6126 | } else { | |
eddc9ec5 | 6127 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
6128 | int tsflags; |
6129 | ||
eddc9ec5 | 6130 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
6131 | base_flags |= tsflags << 12; |
6132 | } | |
6133 | } | |
6134 | } | |
bf933c80 | 6135 | |
eab6d18d | 6136 | if (vlan_tx_tag_present(skb)) |
1da177e4 LT |
6137 | base_flags |= (TXD_FLAG_VLAN | |
6138 | (vlan_tx_tag_get(skb) << 16)); | |
1da177e4 | 6139 | |
b703df6f | 6140 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
8fc2f995 | 6141 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
615774fe MC |
6142 | base_flags |= TXD_FLAG_JMB_PKT; |
6143 | ||
f4188d8a AD |
6144 | len = skb_headlen(skb); |
6145 | ||
6146 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
6147 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
6148 | dev_kfree_skb(skb); |
6149 | goto out_unlock; | |
6150 | } | |
6151 | ||
f3f3f27e | 6152 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 6153 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
6154 | |
6155 | would_hit_hwbug = 0; | |
6156 | ||
92c6b8d1 MC |
6157 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8) |
6158 | would_hit_hwbug = 1; | |
6159 | ||
0e1406dd MC |
6160 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
6161 | tg3_4g_overflow_test(mapping, len)) | |
6162 | would_hit_hwbug = 1; | |
6163 | ||
6164 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && | |
6165 | tg3_40bit_overflow_test(tp, mapping, len)) | |
41588ba1 | 6166 | would_hit_hwbug = 1; |
0e1406dd MC |
6167 | |
6168 | if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) | |
c58ec932 | 6169 | would_hit_hwbug = 1; |
1da177e4 | 6170 | |
f3f3f27e | 6171 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
1da177e4 LT |
6172 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
6173 | ||
6174 | entry = NEXT_TX(entry); | |
6175 | ||
6176 | /* Now loop through additional data fragments, and queue them. */ | |
6177 | if (skb_shinfo(skb)->nr_frags > 0) { | |
1da177e4 LT |
6178 | last = skb_shinfo(skb)->nr_frags - 1; |
6179 | for (i = 0; i <= last; i++) { | |
6180 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6181 | ||
6182 | len = frag->size; | |
f4188d8a AD |
6183 | mapping = pci_map_page(tp->pdev, |
6184 | frag->page, | |
6185 | frag->page_offset, | |
6186 | len, PCI_DMA_TODEVICE); | |
1da177e4 | 6187 | |
f3f3f27e | 6188 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6189 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
6190 | mapping); |
6191 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
6192 | goto dma_error; | |
1da177e4 | 6193 | |
92c6b8d1 MC |
6194 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && |
6195 | len <= 8) | |
6196 | would_hit_hwbug = 1; | |
6197 | ||
0e1406dd MC |
6198 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
6199 | tg3_4g_overflow_test(mapping, len)) | |
c58ec932 | 6200 | would_hit_hwbug = 1; |
1da177e4 | 6201 | |
0e1406dd MC |
6202 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && |
6203 | tg3_40bit_overflow_test(tp, mapping, len)) | |
72f2afb8 MC |
6204 | would_hit_hwbug = 1; |
6205 | ||
1da177e4 | 6206 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
f3f3f27e | 6207 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6208 | base_flags, (i == last)|(mss << 1)); |
6209 | else | |
f3f3f27e | 6210 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6211 | base_flags, (i == last)); |
6212 | ||
6213 | entry = NEXT_TX(entry); | |
6214 | } | |
6215 | } | |
6216 | ||
6217 | if (would_hit_hwbug) { | |
6218 | u32 last_plus_one = entry; | |
6219 | u32 start; | |
1da177e4 | 6220 | |
c58ec932 MC |
6221 | start = entry - 1 - skb_shinfo(skb)->nr_frags; |
6222 | start &= (TG3_TX_RING_SIZE - 1); | |
1da177e4 LT |
6223 | |
6224 | /* If the workaround fails due to memory/mapping | |
6225 | * failure, silently drop this packet. | |
6226 | */ | |
24f4efd4 | 6227 | if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one, |
c58ec932 | 6228 | &start, base_flags, mss)) |
1da177e4 LT |
6229 | goto out_unlock; |
6230 | ||
6231 | entry = start; | |
6232 | } | |
6233 | ||
6234 | /* Packets are ready, update Tx producer idx local and on card. */ | |
24f4efd4 | 6235 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 6236 | |
f3f3f27e MC |
6237 | tnapi->tx_prod = entry; |
6238 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 6239 | netif_tx_stop_queue(txq); |
f65aac16 MC |
6240 | |
6241 | /* netif_tx_stop_queue() must be done before checking | |
6242 | * checking tx index in tg3_tx_avail() below, because in | |
6243 | * tg3_tx(), we update tx index before checking for | |
6244 | * netif_tx_queue_stopped(). | |
6245 | */ | |
6246 | smp_mb(); | |
f3f3f27e | 6247 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 6248 | netif_tx_wake_queue(txq); |
51b91468 | 6249 | } |
1da177e4 LT |
6250 | |
6251 | out_unlock: | |
cdd0db05 | 6252 | mmiowb(); |
1da177e4 LT |
6253 | |
6254 | return NETDEV_TX_OK; | |
f4188d8a AD |
6255 | |
6256 | dma_error: | |
6257 | last = i; | |
6258 | entry = tnapi->tx_prod; | |
6259 | tnapi->tx_buffers[entry].skb = NULL; | |
6260 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 6261 | dma_unmap_addr(&tnapi->tx_buffers[entry], mapping), |
f4188d8a AD |
6262 | skb_headlen(skb), |
6263 | PCI_DMA_TODEVICE); | |
6264 | for (i = 0; i <= last; i++) { | |
6265 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6266 | entry = NEXT_TX(entry); | |
6267 | ||
6268 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6269 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
6270 | mapping), |
6271 | frag->size, PCI_DMA_TODEVICE); | |
6272 | } | |
6273 | ||
6274 | dev_kfree_skb(skb); | |
6275 | return NETDEV_TX_OK; | |
1da177e4 LT |
6276 | } |
6277 | ||
dc668910 MM |
6278 | static u32 tg3_fix_features(struct net_device *dev, u32 features) |
6279 | { | |
6280 | struct tg3 *tp = netdev_priv(dev); | |
6281 | ||
6282 | if (dev->mtu > ETH_DATA_LEN && (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
6283 | features &= ~NETIF_F_ALL_TSO; | |
6284 | ||
6285 | return features; | |
6286 | } | |
6287 | ||
1da177e4 LT |
6288 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
6289 | int new_mtu) | |
6290 | { | |
6291 | dev->mtu = new_mtu; | |
6292 | ||
ef7f5ec0 | 6293 | if (new_mtu > ETH_DATA_LEN) { |
a4e2b347 | 6294 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { |
dc668910 | 6295 | netdev_update_features(dev); |
ef7f5ec0 | 6296 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
859a5887 | 6297 | } else { |
ef7f5ec0 | 6298 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
859a5887 | 6299 | } |
ef7f5ec0 | 6300 | } else { |
dc668910 | 6301 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { |
ef7f5ec0 | 6302 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
dc668910 MM |
6303 | netdev_update_features(dev); |
6304 | } | |
0f893dc6 | 6305 | tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; |
ef7f5ec0 | 6306 | } |
1da177e4 LT |
6307 | } |
6308 | ||
6309 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
6310 | { | |
6311 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 6312 | int err; |
1da177e4 LT |
6313 | |
6314 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
6315 | return -EINVAL; | |
6316 | ||
6317 | if (!netif_running(dev)) { | |
6318 | /* We'll just catch it later when the | |
6319 | * device is up'd. | |
6320 | */ | |
6321 | tg3_set_mtu(dev, tp, new_mtu); | |
6322 | return 0; | |
6323 | } | |
6324 | ||
b02fd9e3 MC |
6325 | tg3_phy_stop(tp); |
6326 | ||
1da177e4 | 6327 | tg3_netif_stop(tp); |
f47c11ee DM |
6328 | |
6329 | tg3_full_lock(tp, 1); | |
1da177e4 | 6330 | |
944d980e | 6331 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
6332 | |
6333 | tg3_set_mtu(dev, tp, new_mtu); | |
6334 | ||
b9ec6c1b | 6335 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 6336 | |
b9ec6c1b MC |
6337 | if (!err) |
6338 | tg3_netif_start(tp); | |
1da177e4 | 6339 | |
f47c11ee | 6340 | tg3_full_unlock(tp); |
1da177e4 | 6341 | |
b02fd9e3 MC |
6342 | if (!err) |
6343 | tg3_phy_start(tp); | |
6344 | ||
b9ec6c1b | 6345 | return err; |
1da177e4 LT |
6346 | } |
6347 | ||
21f581a5 MC |
6348 | static void tg3_rx_prodring_free(struct tg3 *tp, |
6349 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6350 | { |
1da177e4 LT |
6351 | int i; |
6352 | ||
8fea32b9 | 6353 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 6354 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 6355 | i = (i + 1) & tp->rx_std_ring_mask) |
b196c7e4 MC |
6356 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6357 | tp->rx_pkt_map_sz); | |
6358 | ||
6359 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
6360 | for (i = tpr->rx_jmb_cons_idx; | |
6361 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 6362 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
b196c7e4 MC |
6363 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6364 | TG3_RX_JMB_MAP_SZ); | |
6365 | } | |
6366 | } | |
6367 | ||
2b2cdb65 | 6368 | return; |
b196c7e4 | 6369 | } |
1da177e4 | 6370 | |
2c49a44d | 6371 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
2b2cdb65 MC |
6372 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6373 | tp->rx_pkt_map_sz); | |
1da177e4 | 6374 | |
48035728 MC |
6375 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
6376 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
2c49a44d | 6377 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
2b2cdb65 MC |
6378 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6379 | TG3_RX_JMB_MAP_SZ); | |
1da177e4 LT |
6380 | } |
6381 | } | |
6382 | ||
c6cdf436 | 6383 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
6384 | * |
6385 | * The chip has been shut down and the driver detached from | |
6386 | * the networking, so no interrupts or new tx packets will | |
6387 | * end up in the driver. tp->{tx,}lock are held and thus | |
6388 | * we may not sleep. | |
6389 | */ | |
21f581a5 MC |
6390 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
6391 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6392 | { |
287be12e | 6393 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 6394 | |
b196c7e4 MC |
6395 | tpr->rx_std_cons_idx = 0; |
6396 | tpr->rx_std_prod_idx = 0; | |
6397 | tpr->rx_jmb_cons_idx = 0; | |
6398 | tpr->rx_jmb_prod_idx = 0; | |
6399 | ||
8fea32b9 | 6400 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
6401 | memset(&tpr->rx_std_buffers[0], 0, |
6402 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 6403 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 6404 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 6405 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
6406 | goto done; |
6407 | } | |
6408 | ||
1da177e4 | 6409 | /* Zero out all descriptors. */ |
2c49a44d | 6410 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 6411 | |
287be12e | 6412 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
a4e2b347 | 6413 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && |
287be12e MC |
6414 | tp->dev->mtu > ETH_DATA_LEN) |
6415 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6416 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 6417 | |
1da177e4 LT |
6418 | /* Initialize invariants of the rings, we only set this |
6419 | * stuff once. This works because the card does not | |
6420 | * write into the rx buffer posting rings. | |
6421 | */ | |
2c49a44d | 6422 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
6423 | struct tg3_rx_buffer_desc *rxd; |
6424 | ||
21f581a5 | 6425 | rxd = &tpr->rx_std[i]; |
287be12e | 6426 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
6427 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
6428 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6429 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6430 | } | |
6431 | ||
1da177e4 LT |
6432 | /* Now allocate fresh SKBs for each rx ring. */ |
6433 | for (i = 0; i < tp->rx_pending; i++) { | |
86b21e59 | 6434 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
6435 | netdev_warn(tp->dev, |
6436 | "Using a smaller RX standard ring. Only " | |
6437 | "%d out of %d buffers were allocated " | |
6438 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 6439 | if (i == 0) |
cf7a7298 | 6440 | goto initfail; |
32d8c572 | 6441 | tp->rx_pending = i; |
1da177e4 | 6442 | break; |
32d8c572 | 6443 | } |
1da177e4 LT |
6444 | } |
6445 | ||
48035728 MC |
6446 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) || |
6447 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
cf7a7298 MC |
6448 | goto done; |
6449 | ||
2c49a44d | 6450 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 6451 | |
0d86df80 MC |
6452 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)) |
6453 | goto done; | |
cf7a7298 | 6454 | |
2c49a44d | 6455 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
6456 | struct tg3_rx_buffer_desc *rxd; |
6457 | ||
6458 | rxd = &tpr->rx_jmb[i].std; | |
6459 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6460 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6461 | RXD_FLAG_JUMBO; | |
6462 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6463 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6464 | } | |
6465 | ||
6466 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6467 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
5129c3a3 MC |
6468 | netdev_warn(tp->dev, |
6469 | "Using a smaller RX jumbo ring. Only %d " | |
6470 | "out of %d buffers were allocated " | |
6471 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
6472 | if (i == 0) |
6473 | goto initfail; | |
6474 | tp->rx_jumbo_pending = i; | |
6475 | break; | |
1da177e4 LT |
6476 | } |
6477 | } | |
cf7a7298 MC |
6478 | |
6479 | done: | |
32d8c572 | 6480 | return 0; |
cf7a7298 MC |
6481 | |
6482 | initfail: | |
21f581a5 | 6483 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 6484 | return -ENOMEM; |
1da177e4 LT |
6485 | } |
6486 | ||
21f581a5 MC |
6487 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
6488 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6489 | { |
21f581a5 MC |
6490 | kfree(tpr->rx_std_buffers); |
6491 | tpr->rx_std_buffers = NULL; | |
6492 | kfree(tpr->rx_jmb_buffers); | |
6493 | tpr->rx_jmb_buffers = NULL; | |
6494 | if (tpr->rx_std) { | |
4bae65c8 MC |
6495 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
6496 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 6497 | tpr->rx_std = NULL; |
1da177e4 | 6498 | } |
21f581a5 | 6499 | if (tpr->rx_jmb) { |
4bae65c8 MC |
6500 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
6501 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 6502 | tpr->rx_jmb = NULL; |
1da177e4 | 6503 | } |
cf7a7298 MC |
6504 | } |
6505 | ||
21f581a5 MC |
6506 | static int tg3_rx_prodring_init(struct tg3 *tp, |
6507 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 6508 | { |
2c49a44d MC |
6509 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
6510 | GFP_KERNEL); | |
21f581a5 | 6511 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
6512 | return -ENOMEM; |
6513 | ||
4bae65c8 MC |
6514 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
6515 | TG3_RX_STD_RING_BYTES(tp), | |
6516 | &tpr->rx_std_mapping, | |
6517 | GFP_KERNEL); | |
21f581a5 | 6518 | if (!tpr->rx_std) |
cf7a7298 MC |
6519 | goto err_out; |
6520 | ||
48035728 MC |
6521 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
6522 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
2c49a44d | 6523 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
6524 | GFP_KERNEL); |
6525 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
6526 | goto err_out; |
6527 | ||
4bae65c8 MC |
6528 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
6529 | TG3_RX_JMB_RING_BYTES(tp), | |
6530 | &tpr->rx_jmb_mapping, | |
6531 | GFP_KERNEL); | |
21f581a5 | 6532 | if (!tpr->rx_jmb) |
cf7a7298 MC |
6533 | goto err_out; |
6534 | } | |
6535 | ||
6536 | return 0; | |
6537 | ||
6538 | err_out: | |
21f581a5 | 6539 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
6540 | return -ENOMEM; |
6541 | } | |
6542 | ||
6543 | /* Free up pending packets in all rx/tx rings. | |
6544 | * | |
6545 | * The chip has been shut down and the driver detached from | |
6546 | * the networking, so no interrupts or new tx packets will | |
6547 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6548 | * in an interrupt context and thus may sleep. | |
6549 | */ | |
6550 | static void tg3_free_rings(struct tg3 *tp) | |
6551 | { | |
f77a6a8e | 6552 | int i, j; |
cf7a7298 | 6553 | |
f77a6a8e MC |
6554 | for (j = 0; j < tp->irq_cnt; j++) { |
6555 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 6556 | |
8fea32b9 | 6557 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 6558 | |
0c1d0e2b MC |
6559 | if (!tnapi->tx_buffers) |
6560 | continue; | |
6561 | ||
f77a6a8e | 6562 | for (i = 0; i < TG3_TX_RING_SIZE; ) { |
f4188d8a | 6563 | struct ring_info *txp; |
f77a6a8e | 6564 | struct sk_buff *skb; |
f4188d8a | 6565 | unsigned int k; |
cf7a7298 | 6566 | |
f77a6a8e MC |
6567 | txp = &tnapi->tx_buffers[i]; |
6568 | skb = txp->skb; | |
cf7a7298 | 6569 | |
f77a6a8e MC |
6570 | if (skb == NULL) { |
6571 | i++; | |
6572 | continue; | |
6573 | } | |
cf7a7298 | 6574 | |
f4188d8a | 6575 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 6576 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6577 | skb_headlen(skb), |
6578 | PCI_DMA_TODEVICE); | |
f77a6a8e | 6579 | txp->skb = NULL; |
cf7a7298 | 6580 | |
f4188d8a AD |
6581 | i++; |
6582 | ||
6583 | for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { | |
6584 | txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; | |
6585 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6586 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6587 | skb_shinfo(skb)->frags[k].size, |
6588 | PCI_DMA_TODEVICE); | |
6589 | i++; | |
6590 | } | |
f77a6a8e MC |
6591 | |
6592 | dev_kfree_skb_any(skb); | |
6593 | } | |
2b2cdb65 | 6594 | } |
cf7a7298 MC |
6595 | } |
6596 | ||
6597 | /* Initialize tx/rx rings for packet processing. | |
6598 | * | |
6599 | * The chip has been shut down and the driver detached from | |
6600 | * the networking, so no interrupts or new tx packets will | |
6601 | * end up in the driver. tp->{tx,}lock are held and thus | |
6602 | * we may not sleep. | |
6603 | */ | |
6604 | static int tg3_init_rings(struct tg3 *tp) | |
6605 | { | |
f77a6a8e | 6606 | int i; |
72334482 | 6607 | |
cf7a7298 MC |
6608 | /* Free up all the SKBs. */ |
6609 | tg3_free_rings(tp); | |
6610 | ||
f77a6a8e MC |
6611 | for (i = 0; i < tp->irq_cnt; i++) { |
6612 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6613 | ||
6614 | tnapi->last_tag = 0; | |
6615 | tnapi->last_irq_tag = 0; | |
6616 | tnapi->hw_status->status = 0; | |
6617 | tnapi->hw_status->status_tag = 0; | |
6618 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 6619 | |
f77a6a8e MC |
6620 | tnapi->tx_prod = 0; |
6621 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
6622 | if (tnapi->tx_ring) |
6623 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
6624 | |
6625 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
6626 | if (tnapi->rx_rcb) |
6627 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 6628 | |
8fea32b9 | 6629 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 6630 | tg3_free_rings(tp); |
2b2cdb65 | 6631 | return -ENOMEM; |
e4af1af9 | 6632 | } |
f77a6a8e | 6633 | } |
72334482 | 6634 | |
2b2cdb65 | 6635 | return 0; |
cf7a7298 MC |
6636 | } |
6637 | ||
6638 | /* | |
6639 | * Must not be invoked with interrupt sources disabled and | |
6640 | * the hardware shutdown down. | |
6641 | */ | |
6642 | static void tg3_free_consistent(struct tg3 *tp) | |
6643 | { | |
f77a6a8e | 6644 | int i; |
898a56f8 | 6645 | |
f77a6a8e MC |
6646 | for (i = 0; i < tp->irq_cnt; i++) { |
6647 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6648 | ||
6649 | if (tnapi->tx_ring) { | |
4bae65c8 | 6650 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
6651 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
6652 | tnapi->tx_ring = NULL; | |
6653 | } | |
6654 | ||
6655 | kfree(tnapi->tx_buffers); | |
6656 | tnapi->tx_buffers = NULL; | |
6657 | ||
6658 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
6659 | dma_free_coherent(&tp->pdev->dev, |
6660 | TG3_RX_RCB_RING_BYTES(tp), | |
6661 | tnapi->rx_rcb, | |
6662 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
6663 | tnapi->rx_rcb = NULL; |
6664 | } | |
6665 | ||
8fea32b9 MC |
6666 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
6667 | ||
f77a6a8e | 6668 | if (tnapi->hw_status) { |
4bae65c8 MC |
6669 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
6670 | tnapi->hw_status, | |
6671 | tnapi->status_mapping); | |
f77a6a8e MC |
6672 | tnapi->hw_status = NULL; |
6673 | } | |
1da177e4 | 6674 | } |
f77a6a8e | 6675 | |
1da177e4 | 6676 | if (tp->hw_stats) { |
4bae65c8 MC |
6677 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
6678 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
6679 | tp->hw_stats = NULL; |
6680 | } | |
6681 | } | |
6682 | ||
6683 | /* | |
6684 | * Must not be invoked with interrupt sources disabled and | |
6685 | * the hardware shutdown down. Can sleep. | |
6686 | */ | |
6687 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6688 | { | |
f77a6a8e | 6689 | int i; |
898a56f8 | 6690 | |
4bae65c8 MC |
6691 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
6692 | sizeof(struct tg3_hw_stats), | |
6693 | &tp->stats_mapping, | |
6694 | GFP_KERNEL); | |
f77a6a8e | 6695 | if (!tp->hw_stats) |
1da177e4 LT |
6696 | goto err_out; |
6697 | ||
f77a6a8e | 6698 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 6699 | |
f77a6a8e MC |
6700 | for (i = 0; i < tp->irq_cnt; i++) { |
6701 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 6702 | struct tg3_hw_status *sblk; |
1da177e4 | 6703 | |
4bae65c8 MC |
6704 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
6705 | TG3_HW_STATUS_SIZE, | |
6706 | &tnapi->status_mapping, | |
6707 | GFP_KERNEL); | |
f77a6a8e MC |
6708 | if (!tnapi->hw_status) |
6709 | goto err_out; | |
898a56f8 | 6710 | |
f77a6a8e | 6711 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
6712 | sblk = tnapi->hw_status; |
6713 | ||
8fea32b9 MC |
6714 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
6715 | goto err_out; | |
6716 | ||
19cfaecc MC |
6717 | /* If multivector TSS is enabled, vector 0 does not handle |
6718 | * tx interrupts. Don't allocate any resources for it. | |
6719 | */ | |
6720 | if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) || | |
6721 | (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) { | |
6722 | tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * | |
6723 | TG3_TX_RING_SIZE, | |
6724 | GFP_KERNEL); | |
6725 | if (!tnapi->tx_buffers) | |
6726 | goto err_out; | |
6727 | ||
4bae65c8 MC |
6728 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
6729 | TG3_TX_RING_BYTES, | |
6730 | &tnapi->tx_desc_mapping, | |
6731 | GFP_KERNEL); | |
19cfaecc MC |
6732 | if (!tnapi->tx_ring) |
6733 | goto err_out; | |
6734 | } | |
6735 | ||
8d9d7cfc MC |
6736 | /* |
6737 | * When RSS is enabled, the status block format changes | |
6738 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6739 | * and "rx_mini_consumer" members get mapped to the | |
6740 | * other three rx return ring producer indexes. | |
6741 | */ | |
6742 | switch (i) { | |
6743 | default: | |
6744 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6745 | break; | |
6746 | case 2: | |
6747 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6748 | break; | |
6749 | case 3: | |
6750 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6751 | break; | |
6752 | case 4: | |
6753 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6754 | break; | |
6755 | } | |
72334482 | 6756 | |
0c1d0e2b MC |
6757 | /* |
6758 | * If multivector RSS is enabled, vector 0 does not handle | |
6759 | * rx or tx interrupts. Don't allocate any resources for it. | |
6760 | */ | |
6761 | if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) | |
6762 | continue; | |
6763 | ||
4bae65c8 MC |
6764 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
6765 | TG3_RX_RCB_RING_BYTES(tp), | |
6766 | &tnapi->rx_rcb_mapping, | |
6767 | GFP_KERNEL); | |
f77a6a8e MC |
6768 | if (!tnapi->rx_rcb) |
6769 | goto err_out; | |
72334482 | 6770 | |
f77a6a8e | 6771 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 6772 | } |
1da177e4 LT |
6773 | |
6774 | return 0; | |
6775 | ||
6776 | err_out: | |
6777 | tg3_free_consistent(tp); | |
6778 | return -ENOMEM; | |
6779 | } | |
6780 | ||
6781 | #define MAX_WAIT_CNT 1000 | |
6782 | ||
6783 | /* To stop a block, clear the enable bit and poll till it | |
6784 | * clears. tp->lock is held. | |
6785 | */ | |
b3b7d6be | 6786 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
6787 | { |
6788 | unsigned int i; | |
6789 | u32 val; | |
6790 | ||
6791 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
6792 | switch (ofs) { | |
6793 | case RCVLSC_MODE: | |
6794 | case DMAC_MODE: | |
6795 | case MBFREE_MODE: | |
6796 | case BUFMGR_MODE: | |
6797 | case MEMARB_MODE: | |
6798 | /* We can't enable/disable these bits of the | |
6799 | * 5705/5750, just say success. | |
6800 | */ | |
6801 | return 0; | |
6802 | ||
6803 | default: | |
6804 | break; | |
855e1111 | 6805 | } |
1da177e4 LT |
6806 | } |
6807 | ||
6808 | val = tr32(ofs); | |
6809 | val &= ~enable_bit; | |
6810 | tw32_f(ofs, val); | |
6811 | ||
6812 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6813 | udelay(100); | |
6814 | val = tr32(ofs); | |
6815 | if ((val & enable_bit) == 0) | |
6816 | break; | |
6817 | } | |
6818 | ||
b3b7d6be | 6819 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
6820 | dev_err(&tp->pdev->dev, |
6821 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
6822 | ofs, enable_bit); | |
1da177e4 LT |
6823 | return -ENODEV; |
6824 | } | |
6825 | ||
6826 | return 0; | |
6827 | } | |
6828 | ||
6829 | /* tp->lock is held. */ | |
b3b7d6be | 6830 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
6831 | { |
6832 | int i, err; | |
6833 | ||
6834 | tg3_disable_ints(tp); | |
6835 | ||
6836 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6837 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6838 | udelay(10); | |
6839 | ||
b3b7d6be DM |
6840 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
6841 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6842 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6843 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6844 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6845 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6846 | ||
6847 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6848 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6849 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6850 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6851 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6852 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6853 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
6854 | |
6855 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6856 | tw32_f(MAC_MODE, tp->mac_mode); | |
6857 | udelay(40); | |
6858 | ||
6859 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6860 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6861 | ||
6862 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6863 | udelay(100); | |
6864 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6865 | break; | |
6866 | } | |
6867 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
6868 | dev_err(&tp->pdev->dev, |
6869 | "%s timed out, TX_MODE_ENABLE will not clear " | |
6870 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 6871 | err |= -ENODEV; |
1da177e4 LT |
6872 | } |
6873 | ||
e6de8ad1 | 6874 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
6875 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
6876 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
6877 | |
6878 | tw32(FTQ_RESET, 0xffffffff); | |
6879 | tw32(FTQ_RESET, 0x00000000); | |
6880 | ||
b3b7d6be DM |
6881 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
6882 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 6883 | |
f77a6a8e MC |
6884 | for (i = 0; i < tp->irq_cnt; i++) { |
6885 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6886 | if (tnapi->hw_status) | |
6887 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6888 | } | |
1da177e4 LT |
6889 | if (tp->hw_stats) |
6890 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6891 | ||
1da177e4 LT |
6892 | return err; |
6893 | } | |
6894 | ||
0d3031d9 MC |
6895 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
6896 | { | |
6897 | int i; | |
6898 | u32 apedata; | |
6899 | ||
dc6d0744 MC |
6900 | /* NCSI does not support APE events */ |
6901 | if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI) | |
6902 | return; | |
6903 | ||
0d3031d9 MC |
6904 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); |
6905 | if (apedata != APE_SEG_SIG_MAGIC) | |
6906 | return; | |
6907 | ||
6908 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 6909 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
6910 | return; |
6911 | ||
6912 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6913 | for (i = 0; i < 10; i++) { | |
6914 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6915 | return; | |
6916 | ||
6917 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6918 | ||
6919 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6920 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6921 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6922 | ||
6923 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6924 | ||
6925 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6926 | break; | |
6927 | ||
6928 | udelay(100); | |
6929 | } | |
6930 | ||
6931 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6932 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6933 | } | |
6934 | ||
6935 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6936 | { | |
6937 | u32 event; | |
6938 | u32 apedata; | |
6939 | ||
6940 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
6941 | return; | |
6942 | ||
6943 | switch (kind) { | |
33f401ae MC |
6944 | case RESET_KIND_INIT: |
6945 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6946 | APE_HOST_SEG_SIG_MAGIC); | |
6947 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6948 | APE_HOST_SEG_LEN_MAGIC); | |
6949 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6950 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6951 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6867c843 | 6952 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); |
33f401ae MC |
6953 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, |
6954 | APE_HOST_BEHAV_NO_PHYLOCK); | |
dc6d0744 MC |
6955 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, |
6956 | TG3_APE_HOST_DRVR_STATE_START); | |
33f401ae MC |
6957 | |
6958 | event = APE_EVENT_STATUS_STATE_START; | |
6959 | break; | |
6960 | case RESET_KIND_SHUTDOWN: | |
6961 | /* With the interface we are currently using, | |
6962 | * APE does not track driver state. Wiping | |
6963 | * out the HOST SEGMENT SIGNATURE forces | |
6964 | * the APE to assume OS absent status. | |
6965 | */ | |
6966 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
b2aee154 | 6967 | |
dc6d0744 MC |
6968 | if (device_may_wakeup(&tp->pdev->dev) && |
6969 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) { | |
6970 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
6971 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
6972 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
6973 | } else | |
6974 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
6975 | ||
6976 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
6977 | ||
33f401ae MC |
6978 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
6979 | break; | |
6980 | case RESET_KIND_SUSPEND: | |
6981 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
6982 | break; | |
6983 | default: | |
6984 | return; | |
0d3031d9 MC |
6985 | } |
6986 | ||
6987 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
6988 | ||
6989 | tg3_ape_send_event(tp, event); | |
6990 | } | |
6991 | ||
1da177e4 LT |
6992 | /* tp->lock is held. */ |
6993 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
6994 | { | |
f49639e6 DM |
6995 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
6996 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 LT |
6997 | |
6998 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6999 | switch (kind) { | |
7000 | case RESET_KIND_INIT: | |
7001 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7002 | DRV_STATE_START); | |
7003 | break; | |
7004 | ||
7005 | case RESET_KIND_SHUTDOWN: | |
7006 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7007 | DRV_STATE_UNLOAD); | |
7008 | break; | |
7009 | ||
7010 | case RESET_KIND_SUSPEND: | |
7011 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7012 | DRV_STATE_SUSPEND); | |
7013 | break; | |
7014 | ||
7015 | default: | |
7016 | break; | |
855e1111 | 7017 | } |
1da177e4 | 7018 | } |
0d3031d9 MC |
7019 | |
7020 | if (kind == RESET_KIND_INIT || | |
7021 | kind == RESET_KIND_SUSPEND) | |
7022 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
7023 | } |
7024 | ||
7025 | /* tp->lock is held. */ | |
7026 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
7027 | { | |
7028 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
7029 | switch (kind) { | |
7030 | case RESET_KIND_INIT: | |
7031 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7032 | DRV_STATE_START_DONE); | |
7033 | break; | |
7034 | ||
7035 | case RESET_KIND_SHUTDOWN: | |
7036 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7037 | DRV_STATE_UNLOAD_DONE); | |
7038 | break; | |
7039 | ||
7040 | default: | |
7041 | break; | |
855e1111 | 7042 | } |
1da177e4 | 7043 | } |
0d3031d9 MC |
7044 | |
7045 | if (kind == RESET_KIND_SHUTDOWN) | |
7046 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
7047 | } |
7048 | ||
7049 | /* tp->lock is held. */ | |
7050 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
7051 | { | |
7052 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
7053 | switch (kind) { | |
7054 | case RESET_KIND_INIT: | |
7055 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7056 | DRV_STATE_START); | |
7057 | break; | |
7058 | ||
7059 | case RESET_KIND_SHUTDOWN: | |
7060 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7061 | DRV_STATE_UNLOAD); | |
7062 | break; | |
7063 | ||
7064 | case RESET_KIND_SUSPEND: | |
7065 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
7066 | DRV_STATE_SUSPEND); | |
7067 | break; | |
7068 | ||
7069 | default: | |
7070 | break; | |
855e1111 | 7071 | } |
1da177e4 LT |
7072 | } |
7073 | } | |
7074 | ||
7a6f4369 MC |
7075 | static int tg3_poll_fw(struct tg3 *tp) |
7076 | { | |
7077 | int i; | |
7078 | u32 val; | |
7079 | ||
b5d3772c | 7080 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
7081 | /* Wait up to 20ms for init done. */ |
7082 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
7083 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
7084 | return 0; | |
0ccead18 | 7085 | udelay(100); |
b5d3772c MC |
7086 | } |
7087 | return -ENODEV; | |
7088 | } | |
7089 | ||
7a6f4369 MC |
7090 | /* Wait for firmware initialization to complete. */ |
7091 | for (i = 0; i < 100000; i++) { | |
7092 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
7093 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
7094 | break; | |
7095 | udelay(10); | |
7096 | } | |
7097 | ||
7098 | /* Chip might not be fitted with firmware. Some Sun onboard | |
7099 | * parts are configured like that. So don't signal the timeout | |
7100 | * of the above loop as an error, but do report the lack of | |
7101 | * running firmware once. | |
7102 | */ | |
7103 | if (i >= 100000 && | |
7104 | !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { | |
7105 | tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED; | |
7106 | ||
05dbe005 | 7107 | netdev_info(tp->dev, "No firmware running\n"); |
7a6f4369 MC |
7108 | } |
7109 | ||
6b10c165 MC |
7110 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
7111 | /* The 57765 A0 needs a little more | |
7112 | * time to do some important work. | |
7113 | */ | |
7114 | mdelay(10); | |
7115 | } | |
7116 | ||
7a6f4369 MC |
7117 | return 0; |
7118 | } | |
7119 | ||
ee6a99b5 MC |
7120 | /* Save PCI command register before chip reset */ |
7121 | static void tg3_save_pci_state(struct tg3 *tp) | |
7122 | { | |
8a6eac90 | 7123 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
7124 | } |
7125 | ||
7126 | /* Restore PCI state after chip reset */ | |
7127 | static void tg3_restore_pci_state(struct tg3 *tp) | |
7128 | { | |
7129 | u32 val; | |
7130 | ||
7131 | /* Re-enable indirect register accesses. */ | |
7132 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
7133 | tp->misc_host_ctrl); | |
7134 | ||
7135 | /* Set MAX PCI retry to zero. */ | |
7136 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
7137 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
7138 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) | |
7139 | val |= PCISTATE_RETRY_SAME_DMA; | |
0d3031d9 MC |
7140 | /* Allow reads and writes to the APE register and memory space. */ |
7141 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
7142 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
7143 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7144 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
7145 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
7146 | ||
8a6eac90 | 7147 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 7148 | |
fcb389df MC |
7149 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
7150 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
cf79003d | 7151 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
fcb389df MC |
7152 | else { |
7153 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
7154 | tp->pci_cacheline_sz); | |
7155 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
7156 | tp->pci_lat_timer); | |
7157 | } | |
114342f2 | 7158 | } |
5f5c51e3 | 7159 | |
ee6a99b5 | 7160 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
52f4490c | 7161 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
9974a356 MC |
7162 | u16 pcix_cmd; |
7163 | ||
7164 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7165 | &pcix_cmd); | |
7166 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7167 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7168 | pcix_cmd); | |
7169 | } | |
ee6a99b5 MC |
7170 | |
7171 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
ee6a99b5 MC |
7172 | |
7173 | /* Chip reset on 5780 will reset MSI enable bit, | |
7174 | * so need to restore it. | |
7175 | */ | |
7176 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7177 | u16 ctrl; | |
7178 | ||
7179 | pci_read_config_word(tp->pdev, | |
7180 | tp->msi_cap + PCI_MSI_FLAGS, | |
7181 | &ctrl); | |
7182 | pci_write_config_word(tp->pdev, | |
7183 | tp->msi_cap + PCI_MSI_FLAGS, | |
7184 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7185 | val = tr32(MSGINT_MODE); | |
7186 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7187 | } | |
7188 | } | |
7189 | } | |
7190 | ||
1da177e4 LT |
7191 | static void tg3_stop_fw(struct tg3 *); |
7192 | ||
7193 | /* tp->lock is held. */ | |
7194 | static int tg3_chip_reset(struct tg3 *tp) | |
7195 | { | |
7196 | u32 val; | |
1ee582d8 | 7197 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7198 | int i, err; |
1da177e4 | 7199 | |
f49639e6 DM |
7200 | tg3_nvram_lock(tp); |
7201 | ||
77b483f1 MC |
7202 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7203 | ||
f49639e6 DM |
7204 | /* No matching tg3_nvram_unlock() after this because |
7205 | * chip reset below will undo the nvram lock. | |
7206 | */ | |
7207 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7208 | |
ee6a99b5 MC |
7209 | /* GRC_MISC_CFG core clock reset will clear the memory |
7210 | * enable bit in PCI register 4 and the MSI enable bit | |
7211 | * on some chips, so we save relevant registers here. | |
7212 | */ | |
7213 | tg3_save_pci_state(tp); | |
7214 | ||
d9ab5ad1 | 7215 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
321d32a0 | 7216 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) |
d9ab5ad1 MC |
7217 | tw32(GRC_FASTBOOT_PC, 0); |
7218 | ||
1da177e4 LT |
7219 | /* |
7220 | * We must avoid the readl() that normally takes place. | |
7221 | * It locks machines, causes machine checks, and other | |
7222 | * fun things. So, temporarily disable the 5701 | |
7223 | * hardware workaround, while we do the reset. | |
7224 | */ | |
1ee582d8 MC |
7225 | write_op = tp->write32; |
7226 | if (write_op == tg3_write_flush_reg32) | |
7227 | tp->write32 = tg3_write32; | |
1da177e4 | 7228 | |
d18edcb2 MC |
7229 | /* Prevent the irq handler from reading or writing PCI registers |
7230 | * during chip reset when the memory enable bit in the PCI command | |
7231 | * register may be cleared. The chip does not generate interrupt | |
7232 | * at this time, but the irq handler may still be called due to irq | |
7233 | * sharing or irqpoll. | |
7234 | */ | |
7235 | tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; | |
f77a6a8e MC |
7236 | for (i = 0; i < tp->irq_cnt; i++) { |
7237 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7238 | if (tnapi->hw_status) { | |
7239 | tnapi->hw_status->status = 0; | |
7240 | tnapi->hw_status->status_tag = 0; | |
7241 | } | |
7242 | tnapi->last_tag = 0; | |
7243 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7244 | } |
d18edcb2 | 7245 | smp_mb(); |
4f125f42 MC |
7246 | |
7247 | for (i = 0; i < tp->irq_cnt; i++) | |
7248 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7249 | |
255ca311 MC |
7250 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7251 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7252 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7253 | } | |
7254 | ||
1da177e4 LT |
7255 | /* do the reset */ |
7256 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7257 | ||
7258 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
88075d91 MC |
7259 | /* Force PCIe 1.0a mode */ |
7260 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
1407deb1 | 7261 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
88075d91 MC |
7262 | tr32(TG3_PCIE_PHY_TSTCTL) == |
7263 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7264 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7265 | ||
1da177e4 LT |
7266 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7267 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7268 | val |= (1 << 29); | |
7269 | } | |
7270 | } | |
7271 | ||
b5d3772c MC |
7272 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7273 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7274 | tw32(GRC_VCPU_EXT_CTRL, | |
7275 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7276 | } | |
7277 | ||
f37500d3 MC |
7278 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
7279 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
7280 | !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) | |
1da177e4 | 7281 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7282 | |
1da177e4 LT |
7283 | tw32(GRC_MISC_CFG, val); |
7284 | ||
1ee582d8 MC |
7285 | /* restore 5701 hardware bug workaround write method */ |
7286 | tp->write32 = write_op; | |
1da177e4 LT |
7287 | |
7288 | /* Unfortunately, we have to delay before the PCI read back. | |
7289 | * Some 575X chips even will not respond to a PCI cfg access | |
7290 | * when the reset command is given to the chip. | |
7291 | * | |
7292 | * How do these hardware designers expect things to work | |
7293 | * properly if the PCI write is posted for a long period | |
7294 | * of time? It is always necessary to have some method by | |
7295 | * which a register read back can occur to push the write | |
7296 | * out which does the reset. | |
7297 | * | |
7298 | * For most tg3 variants the trick below was working. | |
7299 | * Ho hum... | |
7300 | */ | |
7301 | udelay(120); | |
7302 | ||
7303 | /* Flush PCI posted writes. The normal MMIO registers | |
7304 | * are inaccessible at this time so this is the only | |
7305 | * way to make this reliably (actually, this is no longer | |
7306 | * the case, see above). I tried to use indirect | |
7307 | * register read/write but this upset some 5701 variants. | |
7308 | */ | |
7309 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7310 | ||
7311 | udelay(120); | |
7312 | ||
5e7dfd0f | 7313 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { |
e7126997 MC |
7314 | u16 val16; |
7315 | ||
1da177e4 LT |
7316 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7317 | int i; | |
7318 | u32 cfg_val; | |
7319 | ||
7320 | /* Wait for link training to complete. */ | |
7321 | for (i = 0; i < 5000; i++) | |
7322 | udelay(100); | |
7323 | ||
7324 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7325 | pci_write_config_dword(tp->pdev, 0xc4, | |
7326 | cfg_val | (1 << 15)); | |
7327 | } | |
5e7dfd0f | 7328 | |
e7126997 MC |
7329 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7330 | pci_read_config_word(tp->pdev, | |
7331 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
7332 | &val16); | |
7333 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7334 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7335 | /* | |
7336 | * Older PCIe devices only support the 128 byte | |
7337 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7338 | */ |
6de34cb9 | 7339 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) |
e7126997 | 7340 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f MC |
7341 | pci_write_config_word(tp->pdev, |
7342 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
e7126997 | 7343 | val16); |
5e7dfd0f | 7344 | |
cf79003d | 7345 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
5e7dfd0f MC |
7346 | |
7347 | /* Clear error status */ | |
7348 | pci_write_config_word(tp->pdev, | |
7349 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
7350 | PCI_EXP_DEVSTA_CED | | |
7351 | PCI_EXP_DEVSTA_NFED | | |
7352 | PCI_EXP_DEVSTA_FED | | |
7353 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7354 | } |
7355 | ||
ee6a99b5 | 7356 | tg3_restore_pci_state(tp); |
1da177e4 | 7357 | |
e64de4e6 MC |
7358 | tp->tg3_flags &= ~(TG3_FLAG_CHIP_RESETTING | |
7359 | TG3_FLAG_ERROR_PROCESSED); | |
d18edcb2 | 7360 | |
ee6a99b5 MC |
7361 | val = 0; |
7362 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
4cf78e4f | 7363 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7364 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7365 | |
7366 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7367 | tg3_stop_fw(tp); | |
7368 | tw32(0x5000, 0x400); | |
7369 | } | |
7370 | ||
7371 | tw32(GRC_MODE, tp->grc_mode); | |
7372 | ||
7373 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7374 | val = tr32(0xc4); |
1da177e4 LT |
7375 | |
7376 | tw32(0xc4, val | (1 << 15)); | |
7377 | } | |
7378 | ||
7379 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7380 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7381 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7382 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7383 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7384 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7385 | } | |
7386 | ||
d2394e6b MC |
7387 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7388 | tp->mac_mode = MAC_MODE_APE_TX_EN | | |
7389 | MAC_MODE_APE_RX_EN | | |
7390 | MAC_MODE_TDE_ENABLE; | |
7391 | ||
f07e9af3 | 7392 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
d2394e6b MC |
7393 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; |
7394 | val = tp->mac_mode; | |
f07e9af3 | 7395 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
d2394e6b MC |
7396 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
7397 | val = tp->mac_mode; | |
1da177e4 | 7398 | } else |
d2394e6b MC |
7399 | val = 0; |
7400 | ||
7401 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
7402 | udelay(40); |
7403 | ||
77b483f1 MC |
7404 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7405 | ||
7a6f4369 MC |
7406 | err = tg3_poll_fw(tp); |
7407 | if (err) | |
7408 | return err; | |
1da177e4 | 7409 | |
0a9140cf MC |
7410 | tg3_mdio_start(tp); |
7411 | ||
1da177e4 | 7412 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
f6eb9b1f MC |
7413 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7414 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
1407deb1 | 7415 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
ab0049b4 | 7416 | val = tr32(0x7c00); |
1da177e4 LT |
7417 | |
7418 | tw32(0x7c00, val | (1 << 25)); | |
7419 | } | |
7420 | ||
d78b59f5 MC |
7421 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
7422 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
7423 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
7424 | } | |
7425 | ||
1da177e4 LT |
7426 | /* Reprobe ASF enable state. */ |
7427 | tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; | |
7428 | tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; | |
7429 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
7430 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7431 | u32 nic_cfg; | |
7432 | ||
7433 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7434 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
7435 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
4ba526ce | 7436 | tp->last_event_jiffies = jiffies; |
cbf46853 | 7437 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
7438 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
7439 | } | |
7440 | } | |
7441 | ||
7442 | return 0; | |
7443 | } | |
7444 | ||
7445 | /* tp->lock is held. */ | |
7446 | static void tg3_stop_fw(struct tg3 *tp) | |
7447 | { | |
0d3031d9 MC |
7448 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
7449 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
7450 | /* Wait for RX cpu to ACK the previous event. */ |
7451 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7452 | |
7453 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
7454 | |
7455 | tg3_generate_fw_event(tp); | |
1da177e4 | 7456 | |
7c5026aa MC |
7457 | /* Wait for RX cpu to ACK this event. */ |
7458 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7459 | } |
7460 | } | |
7461 | ||
7462 | /* tp->lock is held. */ | |
944d980e | 7463 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7464 | { |
7465 | int err; | |
7466 | ||
7467 | tg3_stop_fw(tp); | |
7468 | ||
944d980e | 7469 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7470 | |
b3b7d6be | 7471 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7472 | err = tg3_chip_reset(tp); |
7473 | ||
daba2a63 MC |
7474 | __tg3_set_mac_addr(tp, 0); |
7475 | ||
944d980e MC |
7476 | tg3_write_sig_legacy(tp, kind); |
7477 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
7478 | |
7479 | if (err) | |
7480 | return err; | |
7481 | ||
7482 | return 0; | |
7483 | } | |
7484 | ||
1da177e4 LT |
7485 | #define RX_CPU_SCRATCH_BASE 0x30000 |
7486 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7487 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7488 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7489 | ||
7490 | /* tp->lock is held. */ | |
7491 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7492 | { | |
7493 | int i; | |
7494 | ||
5d9428de ES |
7495 | BUG_ON(offset == TX_CPU_BASE && |
7496 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)); | |
1da177e4 | 7497 | |
b5d3772c MC |
7498 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7499 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7500 | ||
7501 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7502 | return 0; | |
7503 | } | |
1da177e4 LT |
7504 | if (offset == RX_CPU_BASE) { |
7505 | for (i = 0; i < 10000; i++) { | |
7506 | tw32(offset + CPU_STATE, 0xffffffff); | |
7507 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7508 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7509 | break; | |
7510 | } | |
7511 | ||
7512 | tw32(offset + CPU_STATE, 0xffffffff); | |
7513 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7514 | udelay(10); | |
7515 | } else { | |
7516 | for (i = 0; i < 10000; i++) { | |
7517 | tw32(offset + CPU_STATE, 0xffffffff); | |
7518 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7519 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7520 | break; | |
7521 | } | |
7522 | } | |
7523 | ||
7524 | if (i >= 10000) { | |
05dbe005 JP |
7525 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
7526 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
1da177e4 LT |
7527 | return -ENODEV; |
7528 | } | |
ec41c7df MC |
7529 | |
7530 | /* Clear firmware's nvram arbitration. */ | |
7531 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
7532 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
1da177e4 LT |
7533 | return 0; |
7534 | } | |
7535 | ||
7536 | struct fw_info { | |
077f849d JSR |
7537 | unsigned int fw_base; |
7538 | unsigned int fw_len; | |
7539 | const __be32 *fw_data; | |
1da177e4 LT |
7540 | }; |
7541 | ||
7542 | /* tp->lock is held. */ | |
7543 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7544 | int cpu_scratch_size, struct fw_info *info) | |
7545 | { | |
ec41c7df | 7546 | int err, lock_err, i; |
1da177e4 LT |
7547 | void (*write_op)(struct tg3 *, u32, u32); |
7548 | ||
7549 | if (cpu_base == TX_CPU_BASE && | |
7550 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
5129c3a3 MC |
7551 | netdev_err(tp->dev, |
7552 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
05dbe005 | 7553 | __func__); |
1da177e4 LT |
7554 | return -EINVAL; |
7555 | } | |
7556 | ||
7557 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
7558 | write_op = tg3_write_mem; | |
7559 | else | |
7560 | write_op = tg3_write_indirect_reg32; | |
7561 | ||
1b628151 MC |
7562 | /* It is possible that bootcode is still loading at this point. |
7563 | * Get the nvram lock first before halting the cpu. | |
7564 | */ | |
ec41c7df | 7565 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 7566 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
7567 | if (!lock_err) |
7568 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
7569 | if (err) |
7570 | goto out; | |
7571 | ||
7572 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7573 | write_op(tp, cpu_scratch_base + i, 0); | |
7574 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7575 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 7576 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 7577 | write_op(tp, (cpu_scratch_base + |
077f849d | 7578 | (info->fw_base & 0xffff) + |
1da177e4 | 7579 | (i * sizeof(u32))), |
077f849d | 7580 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
7581 | |
7582 | err = 0; | |
7583 | ||
7584 | out: | |
1da177e4 LT |
7585 | return err; |
7586 | } | |
7587 | ||
7588 | /* tp->lock is held. */ | |
7589 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7590 | { | |
7591 | struct fw_info info; | |
077f849d | 7592 | const __be32 *fw_data; |
1da177e4 LT |
7593 | int err, i; |
7594 | ||
077f849d JSR |
7595 | fw_data = (void *)tp->fw->data; |
7596 | ||
7597 | /* Firmware blob starts with version numbers, followed by | |
7598 | start address and length. We are setting complete length. | |
7599 | length = end_address_of_bss - start_address_of_text. | |
7600 | Remainder is the blob to be loaded contiguously | |
7601 | from start address. */ | |
7602 | ||
7603 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7604 | info.fw_len = tp->fw->size - 12; | |
7605 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
7606 | |
7607 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7608 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7609 | &info); | |
7610 | if (err) | |
7611 | return err; | |
7612 | ||
7613 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7614 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7615 | &info); | |
7616 | if (err) | |
7617 | return err; | |
7618 | ||
7619 | /* Now startup only the RX cpu. */ | |
7620 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 7621 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7622 | |
7623 | for (i = 0; i < 5; i++) { | |
077f849d | 7624 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
7625 | break; |
7626 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7627 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7628 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7629 | udelay(1000); |
7630 | } | |
7631 | if (i >= 5) { | |
5129c3a3 MC |
7632 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
7633 | "should be %08x\n", __func__, | |
05dbe005 | 7634 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); |
1da177e4 LT |
7635 | return -ENODEV; |
7636 | } | |
7637 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7638 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7639 | ||
7640 | return 0; | |
7641 | } | |
7642 | ||
1da177e4 | 7643 | /* 5705 needs a special version of the TSO firmware. */ |
1da177e4 LT |
7644 | |
7645 | /* tp->lock is held. */ | |
7646 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7647 | { | |
7648 | struct fw_info info; | |
077f849d | 7649 | const __be32 *fw_data; |
1da177e4 LT |
7650 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
7651 | int err, i; | |
7652 | ||
7653 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
7654 | return 0; | |
7655 | ||
077f849d JSR |
7656 | fw_data = (void *)tp->fw->data; |
7657 | ||
7658 | /* Firmware blob starts with version numbers, followed by | |
7659 | start address and length. We are setting complete length. | |
7660 | length = end_address_of_bss - start_address_of_text. | |
7661 | Remainder is the blob to be loaded contiguously | |
7662 | from start address. */ | |
7663 | ||
7664 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7665 | cpu_scratch_size = tp->fw_len; | |
7666 | info.fw_len = tp->fw->size - 12; | |
7667 | info.fw_data = &fw_data[3]; | |
7668 | ||
1da177e4 | 7669 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7670 | cpu_base = RX_CPU_BASE; |
7671 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 7672 | } else { |
1da177e4 LT |
7673 | cpu_base = TX_CPU_BASE; |
7674 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7675 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7676 | } | |
7677 | ||
7678 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7679 | cpu_scratch_base, cpu_scratch_size, | |
7680 | &info); | |
7681 | if (err) | |
7682 | return err; | |
7683 | ||
7684 | /* Now startup the cpu. */ | |
7685 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 7686 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7687 | |
7688 | for (i = 0; i < 5; i++) { | |
077f849d | 7689 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
7690 | break; |
7691 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7692 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7693 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7694 | udelay(1000); |
7695 | } | |
7696 | if (i >= 5) { | |
5129c3a3 MC |
7697 | netdev_err(tp->dev, |
7698 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
05dbe005 | 7699 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); |
1da177e4 LT |
7700 | return -ENODEV; |
7701 | } | |
7702 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7703 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7704 | return 0; | |
7705 | } | |
7706 | ||
1da177e4 | 7707 | |
1da177e4 LT |
7708 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7709 | { | |
7710 | struct tg3 *tp = netdev_priv(dev); | |
7711 | struct sockaddr *addr = p; | |
986e0aeb | 7712 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7713 | |
f9804ddb MC |
7714 | if (!is_valid_ether_addr(addr->sa_data)) |
7715 | return -EINVAL; | |
7716 | ||
1da177e4 LT |
7717 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7718 | ||
e75f7c90 MC |
7719 | if (!netif_running(dev)) |
7720 | return 0; | |
7721 | ||
58712ef9 | 7722 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { |
986e0aeb | 7723 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7724 | |
986e0aeb MC |
7725 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7726 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7727 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7728 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7729 | ||
7730 | /* Skip MAC addr 1 if ASF is using it. */ | |
7731 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7732 | !(addr1_high == 0 && addr1_low == 0)) | |
7733 | skip_mac_1 = 1; | |
58712ef9 | 7734 | } |
986e0aeb MC |
7735 | spin_lock_bh(&tp->lock); |
7736 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7737 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7738 | |
b9ec6c1b | 7739 | return err; |
1da177e4 LT |
7740 | } |
7741 | ||
7742 | /* tp->lock is held. */ | |
7743 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7744 | dma_addr_t mapping, u32 maxlen_flags, | |
7745 | u32 nic_addr) | |
7746 | { | |
7747 | tg3_write_mem(tp, | |
7748 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7749 | ((u64) mapping >> 32)); | |
7750 | tg3_write_mem(tp, | |
7751 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7752 | ((u64) mapping & 0xffffffff)); | |
7753 | tg3_write_mem(tp, | |
7754 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7755 | maxlen_flags); | |
7756 | ||
7757 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7758 | tg3_write_mem(tp, | |
7759 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7760 | nic_addr); | |
7761 | } | |
7762 | ||
7763 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7764 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7765 | { |
b6080e12 MC |
7766 | int i; |
7767 | ||
19cfaecc | 7768 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) { |
b6080e12 MC |
7769 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7770 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7771 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7772 | } else { |
7773 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7774 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7775 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7776 | } |
b6080e12 | 7777 | |
20d7375c | 7778 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { |
19cfaecc MC |
7779 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
7780 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7781 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7782 | } else { | |
b6080e12 MC |
7783 | tw32(HOSTCC_RXCOL_TICKS, 0); |
7784 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7785 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7786 | } |
b6080e12 | 7787 | |
15f9850d DM |
7788 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
7789 | u32 val = ec->stats_block_coalesce_usecs; | |
7790 | ||
b6080e12 MC |
7791 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7792 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7793 | ||
15f9850d DM |
7794 | if (!netif_carrier_ok(tp->dev)) |
7795 | val = 0; | |
7796 | ||
7797 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7798 | } | |
b6080e12 MC |
7799 | |
7800 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7801 | u32 reg; | |
7802 | ||
7803 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7804 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
7805 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
7806 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
7807 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
7808 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc MC |
7809 | |
7810 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7811 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
7812 | tw32(reg, ec->tx_coalesce_usecs); | |
7813 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7814 | tw32(reg, ec->tx_max_coalesced_frames); | |
7815 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7816 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7817 | } | |
b6080e12 MC |
7818 | } |
7819 | ||
7820 | for (; i < tp->irq_max - 1; i++) { | |
7821 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 7822 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 7823 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc MC |
7824 | |
7825 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7826 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7827 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7828 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7829 | } | |
b6080e12 | 7830 | } |
15f9850d | 7831 | } |
1da177e4 | 7832 | |
2d31ecaf MC |
7833 | /* tp->lock is held. */ |
7834 | static void tg3_rings_reset(struct tg3 *tp) | |
7835 | { | |
7836 | int i; | |
f77a6a8e | 7837 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
7838 | struct tg3_napi *tnapi = &tp->napi[0]; |
7839 | ||
7840 | /* Disable all transmit rings but the first. */ | |
7841 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7842 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; | |
0a58d668 | 7843 | else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
3d37728b | 7844 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
b703df6f MC |
7845 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
7846 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
2d31ecaf MC |
7847 | else |
7848 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7849 | ||
7850 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7851 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7852 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7853 | BDINFO_FLAGS_DISABLED); | |
7854 | ||
7855 | ||
7856 | /* Disable all receive return rings but the first. */ | |
0a58d668 | 7857 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
f6eb9b1f MC |
7858 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
7859 | else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
2d31ecaf | 7860 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f MC |
7861 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
7862 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2d31ecaf MC |
7863 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
7864 | else | |
7865 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7866 | ||
7867 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7868 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7869 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7870 | BDINFO_FLAGS_DISABLED); | |
7871 | ||
7872 | /* Disable interrupts */ | |
7873 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
7874 | ||
7875 | /* Zero mailbox registers. */ | |
f77a6a8e | 7876 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) { |
6fd45cb8 | 7877 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
7878 | tp->napi[i].tx_prod = 0; |
7879 | tp->napi[i].tx_cons = 0; | |
c2353a32 MC |
7880 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
7881 | tw32_mailbox(tp->napi[i].prodmbox, 0); | |
f77a6a8e MC |
7882 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
7883 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7884 | } | |
c2353a32 MC |
7885 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) |
7886 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
f77a6a8e MC |
7887 | } else { |
7888 | tp->napi[0].tx_prod = 0; | |
7889 | tp->napi[0].tx_cons = 0; | |
7890 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7891 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7892 | } | |
2d31ecaf MC |
7893 | |
7894 | /* Make sure the NIC-based send BD rings are disabled. */ | |
7895 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7896 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
7897 | for (i = 0; i < 16; i++) | |
7898 | tw32_tx_mbox(mbox + i * 8, 0); | |
7899 | } | |
7900 | ||
7901 | txrcb = NIC_SRAM_SEND_RCB; | |
7902 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7903 | ||
7904 | /* Clear status block in ram. */ | |
7905 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7906 | ||
7907 | /* Set status block DMA address */ | |
7908 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7909 | ((u64) tnapi->status_mapping >> 32)); | |
7910 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7911 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7912 | ||
f77a6a8e MC |
7913 | if (tnapi->tx_ring) { |
7914 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7915 | (TG3_TX_RING_SIZE << | |
7916 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7917 | NIC_SRAM_TX_BUFFER_DESC); | |
7918 | txrcb += TG3_BDINFO_SIZE; | |
7919 | } | |
7920 | ||
7921 | if (tnapi->rx_rcb) { | |
7922 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
7923 | (tp->rx_ret_ring_mask + 1) << |
7924 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
7925 | rxrcb += TG3_BDINFO_SIZE; |
7926 | } | |
7927 | ||
7928 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 7929 | |
f77a6a8e MC |
7930 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
7931 | u64 mapping = (u64)tnapi->status_mapping; | |
7932 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7933 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7934 | ||
7935 | /* Clear status block in ram. */ | |
7936 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7937 | ||
19cfaecc MC |
7938 | if (tnapi->tx_ring) { |
7939 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7940 | (TG3_TX_RING_SIZE << | |
7941 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7942 | NIC_SRAM_TX_BUFFER_DESC); | |
7943 | txrcb += TG3_BDINFO_SIZE; | |
7944 | } | |
f77a6a8e MC |
7945 | |
7946 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 7947 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
7948 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
7949 | ||
7950 | stblk += 8; | |
f77a6a8e MC |
7951 | rxrcb += TG3_BDINFO_SIZE; |
7952 | } | |
2d31ecaf MC |
7953 | } |
7954 | ||
eb07a940 MC |
7955 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
7956 | { | |
7957 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; | |
7958 | ||
7959 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS) || | |
7960 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
7961 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
7962 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
7963 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; | |
7964 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
7965 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | |
7966 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | |
7967 | else | |
7968 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | |
7969 | ||
7970 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); | |
7971 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); | |
7972 | ||
7973 | val = min(nic_rep_thresh, host_rep_thresh); | |
7974 | tw32(RCVBDI_STD_THRESH, val); | |
7975 | ||
7976 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) | |
7977 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); | |
7978 | ||
7979 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) || | |
7980 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
7981 | return; | |
7982 | ||
7983 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7984 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; | |
7985 | else | |
7986 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717; | |
7987 | ||
7988 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); | |
7989 | ||
7990 | val = min(bdcache_maxcnt / 2, host_rep_thresh); | |
7991 | tw32(RCVBDI_JUMBO_THRESH, val); | |
7992 | ||
7993 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) | |
7994 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); | |
7995 | } | |
7996 | ||
1da177e4 | 7997 | /* tp->lock is held. */ |
8e7a22e3 | 7998 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
7999 | { |
8000 | u32 val, rdmac_mode; | |
8001 | int i, err, limit; | |
8fea32b9 | 8002 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
8003 | |
8004 | tg3_disable_ints(tp); | |
8005 | ||
8006 | tg3_stop_fw(tp); | |
8007 | ||
8008 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
8009 | ||
859a5887 | 8010 | if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) |
e6de8ad1 | 8011 | tg3_abort_hw(tp, 1); |
1da177e4 | 8012 | |
699c0193 MC |
8013 | /* Enable MAC control of LPI */ |
8014 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
8015 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
8016 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
8017 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
8018 | ||
8019 | tw32_f(TG3_CPMU_EEE_CTRL, | |
8020 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
8021 | ||
a386b901 MC |
8022 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
8023 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
8024 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
8025 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
8026 | ||
8027 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
8028 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
8029 | ||
8030 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
8031 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; | |
8032 | ||
8033 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
8034 | ||
8035 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
8036 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
8037 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
8038 | ||
8039 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 8040 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 8041 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
8042 | } |
8043 | ||
603f1173 | 8044 | if (reset_phy) |
d4d2c558 MC |
8045 | tg3_phy_reset(tp); |
8046 | ||
1da177e4 LT |
8047 | err = tg3_chip_reset(tp); |
8048 | if (err) | |
8049 | return err; | |
8050 | ||
8051 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
8052 | ||
bcb37f6c | 8053 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
8054 | val = tr32(TG3_CPMU_CTRL); |
8055 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
8056 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
8057 | |
8058 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8059 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8060 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8061 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
8062 | ||
8063 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
8064 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
8065 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
8066 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
8067 | ||
8068 | val = tr32(TG3_CPMU_HST_ACC); | |
8069 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
8070 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
8071 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
8072 | } |
8073 | ||
33466d93 MC |
8074 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
8075 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
8076 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
8077 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
8078 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
8079 | |
8080 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
8081 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
8082 | ||
8083 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 8084 | |
f40386c8 MC |
8085 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8086 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
8087 | } |
8088 | ||
614b0590 MC |
8089 | if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) { |
8090 | u32 grc_mode = tr32(GRC_MODE); | |
8091 | ||
8092 | /* Access the lower 1K of PL PCIE block registers. */ | |
8093 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8094 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
8095 | ||
8096 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
8097 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
8098 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
8099 | ||
8100 | tw32(GRC_MODE, grc_mode); | |
8101 | } | |
8102 | ||
5093eedc MC |
8103 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
8104 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
8105 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 8106 | |
5093eedc MC |
8107 | /* Access the lower 1K of PL PCIE block registers. */ |
8108 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
8109 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 8110 | |
5093eedc MC |
8111 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
8112 | TG3_PCIE_PL_LO_PHYCTL5); | |
8113 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
8114 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 8115 | |
5093eedc MC |
8116 | tw32(GRC_MODE, grc_mode); |
8117 | } | |
a977dbe8 MC |
8118 | |
8119 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
8120 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
8121 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
8122 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
8123 | } |
8124 | ||
1da177e4 LT |
8125 | /* This works around an issue with Athlon chipsets on |
8126 | * B3 tigon3 silicon. This bit has no effect on any | |
8127 | * other revision. But do not set this on PCI Express | |
795d01c5 | 8128 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 8129 | */ |
795d01c5 MC |
8130 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { |
8131 | if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
8132 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
8133 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
8134 | } | |
1da177e4 LT |
8135 | |
8136 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
8137 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
8138 | val = tr32(TG3PCI_PCISTATE); | |
8139 | val |= PCISTATE_RETRY_SAME_DMA; | |
8140 | tw32(TG3PCI_PCISTATE, val); | |
8141 | } | |
8142 | ||
0d3031d9 MC |
8143 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
8144 | /* Allow reads and writes to the | |
8145 | * APE register and memory space. | |
8146 | */ | |
8147 | val = tr32(TG3PCI_PCISTATE); | |
8148 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
8149 | PCISTATE_ALLOW_APE_SHMEM_WR | |
8150 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
8151 | tw32(TG3PCI_PCISTATE, val); |
8152 | } | |
8153 | ||
1da177e4 LT |
8154 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
8155 | /* Enable some hw fixes. */ | |
8156 | val = tr32(TG3PCI_MSI_DATA); | |
8157 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
8158 | tw32(TG3PCI_MSI_DATA, val); | |
8159 | } | |
8160 | ||
8161 | /* Descriptor ring init may make accesses to the | |
8162 | * NIC SRAM area to setup the TX descriptors, so we | |
8163 | * can only do this after the hardware has been | |
8164 | * successfully reset. | |
8165 | */ | |
32d8c572 MC |
8166 | err = tg3_init_rings(tp); |
8167 | if (err) | |
8168 | return err; | |
1da177e4 | 8169 | |
1407deb1 | 8170 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
cbf9ca6c MC |
8171 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
8172 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
8173 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
8174 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
cbf9ca6c MC |
8175 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
8176 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
8177 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
8178 | /* This value is determined during the probe time DMA |
8179 | * engine test, tg3_test_dma. | |
8180 | */ | |
8181 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
8182 | } | |
1da177e4 LT |
8183 | |
8184 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
8185 | GRC_MODE_4X_NIC_SEND_RINGS | | |
8186 | GRC_MODE_NO_TX_PHDR_CSUM | | |
8187 | GRC_MODE_NO_RX_PHDR_CSUM); | |
8188 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
8189 | |
8190 | /* Pseudo-header checksum is done by hardware logic and not | |
8191 | * the offload processers, so make the chip do the pseudo- | |
8192 | * header checksums on receive. For transmit it is more | |
8193 | * convenient to do the pseudo-header checksum in software | |
8194 | * as Linux does that on transmit for us in all cases. | |
8195 | */ | |
8196 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
8197 | |
8198 | tw32(GRC_MODE, | |
8199 | tp->grc_mode | | |
8200 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
8201 | ||
8202 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
8203 | val = tr32(GRC_MISC_CFG); | |
8204 | val &= ~0xff; | |
8205 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
8206 | tw32(GRC_MISC_CFG, val); | |
8207 | ||
8208 | /* Initialize MBUF/DESC pool. */ | |
cbf46853 | 8209 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
1da177e4 LT |
8210 | /* Do nothing. */ |
8211 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8212 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8213 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8214 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8215 | else | |
8216 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8217 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8218 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
859a5887 | 8219 | } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
1da177e4 LT |
8220 | int fw_len; |
8221 | ||
077f849d | 8222 | fw_len = tp->fw_len; |
1da177e4 LT |
8223 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8224 | tw32(BUFMGR_MB_POOL_ADDR, | |
8225 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8226 | tw32(BUFMGR_MB_POOL_SIZE, | |
8227 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8228 | } | |
1da177e4 | 8229 | |
0f893dc6 | 8230 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8231 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8232 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8233 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8234 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8235 | tw32(BUFMGR_MB_HIGH_WATER, | |
8236 | tp->bufmgr_config.mbuf_high_water); | |
8237 | } else { | |
8238 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8239 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8240 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8241 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8242 | tw32(BUFMGR_MB_HIGH_WATER, | |
8243 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8244 | } | |
8245 | tw32(BUFMGR_DMA_LOW_WATER, | |
8246 | tp->bufmgr_config.dma_low_water); | |
8247 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8248 | tp->bufmgr_config.dma_high_water); | |
8249 | ||
d309a46e MC |
8250 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8251 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8252 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
4d958473 MC |
8253 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8254 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
8255 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | |
8256 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | |
d309a46e | 8257 | tw32(BUFMGR_MODE, val); |
1da177e4 LT |
8258 | for (i = 0; i < 2000; i++) { |
8259 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8260 | break; | |
8261 | udelay(10); | |
8262 | } | |
8263 | if (i >= 2000) { | |
05dbe005 | 8264 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8265 | return -ENODEV; |
8266 | } | |
8267 | ||
eb07a940 MC |
8268 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
8269 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
b5d3772c | 8270 | |
eb07a940 | 8271 | tg3_setup_rxbd_thresholds(tp); |
1da177e4 LT |
8272 | |
8273 | /* Initialize TG3_BDINFO's at: | |
8274 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8275 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8276 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8277 | * | |
8278 | * like so: | |
8279 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8280 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8281 | * ring attribute flags | |
8282 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8283 | * | |
8284 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8285 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8286 | * | |
8287 | * The size of each ring is fixed in the firmware, but the location is | |
8288 | * configurable. | |
8289 | */ | |
8290 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8291 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8292 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8293 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
0a58d668 | 8294 | if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
87668d35 MC |
8295 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8296 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8297 | |
fdb72b38 MC |
8298 | /* Disable the mini ring */ |
8299 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
1da177e4 LT |
8300 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8301 | BDINFO_FLAGS_DISABLED); | |
8302 | ||
fdb72b38 MC |
8303 | /* Program the jumbo buffer descriptor ring control |
8304 | * blocks on those devices that have them. | |
8305 | */ | |
bb18bb94 | 8306 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
4d163b75 MC |
8307 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
8308 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) { | |
1da177e4 | 8309 | |
0f893dc6 | 8310 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { |
1da177e4 | 8311 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8312 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8313 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8314 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
8315 | val = TG3_RX_JMB_RING_SIZE(tp) << |
8316 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 8317 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 8318 | val | BDINFO_FLAGS_USE_EXT_RECV); |
a50d0796 MC |
8319 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) || |
8320 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
87668d35 MC |
8321 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8322 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8323 | } else { |
8324 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8325 | BDINFO_FLAGS_DISABLED); | |
8326 | } | |
8327 | ||
1407deb1 | 8328 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
7cb32cf2 | 8329 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
de9f5230 | 8330 | val = TG3_RX_STD_MAX_SIZE_5700; |
7cb32cf2 | 8331 | else |
de9f5230 | 8332 | val = TG3_RX_STD_MAX_SIZE_5717; |
7cb32cf2 MC |
8333 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8334 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8335 | } else | |
04380d40 | 8336 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 8337 | } else |
de9f5230 | 8338 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8339 | |
8340 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8341 | |
411da640 | 8342 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8343 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8344 | |
411da640 | 8345 | tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? |
21f581a5 | 8346 | tp->rx_jumbo_pending : 0; |
66711e66 | 8347 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8348 | |
2d31ecaf MC |
8349 | tg3_rings_reset(tp); |
8350 | ||
1da177e4 | 8351 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8352 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8353 | |
8354 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8355 | tw32(MAC_RX_MTU_SIZE, |
8356 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8357 | |
8358 | /* The slot time is changed by tg3_setup_phy if we | |
8359 | * run at gigabit with half duplex. | |
8360 | */ | |
f2096f94 MC |
8361 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
8362 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8363 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | |
8364 | ||
8365 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
8366 | val |= tr32(MAC_TX_LENGTHS) & | |
8367 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | |
8368 | TX_LENGTHS_CNT_DWN_VAL_MSK); | |
8369 | ||
8370 | tw32(MAC_TX_LENGTHS, val); | |
1da177e4 LT |
8371 | |
8372 | /* Receive rules. */ | |
8373 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8374 | tw32(RCVLPC_CONFIG, 0x0181); | |
8375 | ||
8376 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8377 | * the RCVLPC_STATE_ENABLE mask. | |
8378 | */ | |
8379 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8380 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8381 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8382 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8383 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8384 | |
deabaac8 | 8385 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8386 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8387 | ||
57e6983c | 8388 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8389 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8390 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8391 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8392 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8393 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8394 | ||
c5908939 MC |
8395 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8396 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
1da177e4 | 8397 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && |
c13e3713 | 8398 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8399 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8400 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
8401 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { | |
8402 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8403 | } | |
8404 | } | |
8405 | ||
85e94ced MC |
8406 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) |
8407 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8408 | ||
1da177e4 | 8409 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
027455ad MC |
8410 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8411 | ||
e849cdc3 MC |
8412 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
8413 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
027455ad MC |
8414 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8415 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8416 | |
f2096f94 MC |
8417 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
8418 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | |
8419 | ||
41a8a7ee MC |
8420 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8421 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8422 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8423 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
1407deb1 | 8424 | (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
41a8a7ee | 8425 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
d78b59f5 MC |
8426 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8427 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b4495ed8 MC |
8428 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8429 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8430 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8431 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8432 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8433 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8434 | } |
41a8a7ee MC |
8435 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8436 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8437 | } | |
8438 | ||
d78b59f5 MC |
8439 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8440 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
8441 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
8442 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8443 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8444 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8445 | } | |
8446 | ||
1da177e4 | 8447 | /* Receive/send statistics. */ |
1661394e MC |
8448 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
8449 | val = tr32(RCVLPC_STATS_ENABLE); | |
8450 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8451 | tw32(RCVLPC_STATS_ENABLE, val); | |
8452 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
8453 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
1da177e4 LT |
8454 | val = tr32(RCVLPC_STATS_ENABLE); |
8455 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8456 | tw32(RCVLPC_STATS_ENABLE, val); | |
8457 | } else { | |
8458 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8459 | } | |
8460 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8461 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8462 | tw32(SNDDATAI_STATSCTRL, | |
8463 | (SNDDATAI_SCTRL_ENABLE | | |
8464 | SNDDATAI_SCTRL_FASTUPD)); | |
8465 | ||
8466 | /* Setup host coalescing engine. */ | |
8467 | tw32(HOSTCC_MODE, 0); | |
8468 | for (i = 0; i < 2000; i++) { | |
8469 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8470 | break; | |
8471 | udelay(10); | |
8472 | } | |
8473 | ||
d244c892 | 8474 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8475 | |
1da177e4 LT |
8476 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8477 | /* Status/statistics block address. See tg3_timer, | |
8478 | * the tg3_periodic_fetch_stats call there, and | |
8479 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8480 | */ | |
1da177e4 LT |
8481 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8482 | ((u64) tp->stats_mapping >> 32)); | |
8483 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8484 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8485 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8486 | |
1da177e4 | 8487 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8488 | |
8489 | /* Clear statistics and status block memory areas */ | |
8490 | for (i = NIC_SRAM_STATS_BLK; | |
8491 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8492 | i += sizeof(u32)) { | |
8493 | tg3_write_mem(tp, i, 0); | |
8494 | udelay(40); | |
8495 | } | |
1da177e4 LT |
8496 | } |
8497 | ||
8498 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8499 | ||
8500 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8501 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
8502 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8503 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
8504 | ||
f07e9af3 MC |
8505 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
8506 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
8507 | /* reset to prevent losing 1st rx packet intermittently */ |
8508 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8509 | udelay(10); | |
8510 | } | |
8511 | ||
3bda1258 | 8512 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
d2394e6b | 8513 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
8514 | else |
8515 | tp->mac_mode = 0; | |
8516 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
1da177e4 | 8517 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; |
e8f3f6ca | 8518 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
f07e9af3 | 8519 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
8520 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
8521 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8522 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8523 | udelay(40); | |
8524 | ||
314fba34 | 8525 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
9d26e213 | 8526 | * If TG3_FLG2_IS_NIC is zero, we should read the |
314fba34 MC |
8527 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8528 | * whether used as inputs or outputs, are set by boot code after | |
8529 | * reset. | |
8530 | */ | |
9d26e213 | 8531 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { |
314fba34 MC |
8532 | u32 gpio_mask; |
8533 | ||
9d26e213 MC |
8534 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8535 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8536 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8537 | |
8538 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8539 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8540 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8541 | ||
af36e6b6 MC |
8542 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8543 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8544 | ||
aaf84465 | 8545 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8546 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8547 | ||
8548 | /* GPIO1 must be driven high for eeprom write protect */ | |
9d26e213 MC |
8549 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) |
8550 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
8551 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8552 | } |
1da177e4 LT |
8553 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8554 | udelay(100); | |
8555 | ||
0583d521 MC |
8556 | if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && |
8557 | tp->irq_cnt > 1) { | |
baf8a94a MC |
8558 | val = tr32(MSGINT_MODE); |
8559 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8560 | tw32(MSGINT_MODE, val); | |
8561 | } | |
8562 | ||
1da177e4 LT |
8563 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8564 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
8565 | udelay(40); | |
8566 | } | |
8567 | ||
8568 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8569 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8570 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8571 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8572 | WDMAC_MODE_LNGREAD_ENAB); | |
8573 | ||
c5908939 MC |
8574 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8575 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
29ea095f | 8576 | if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && |
1da177e4 LT |
8577 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8578 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8579 | /* nothing */ | |
8580 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
c5908939 | 8581 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { |
1da177e4 LT |
8582 | val |= WDMAC_MODE_RX_ACCEL; |
8583 | } | |
8584 | } | |
8585 | ||
d9ab5ad1 | 8586 | /* Enable host coalescing bug fix */ |
321d32a0 | 8587 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
f51f3562 | 8588 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8589 | |
788a035e MC |
8590 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8591 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8592 | ||
1da177e4 LT |
8593 | tw32_f(WDMAC_MODE, val); |
8594 | udelay(40); | |
8595 | ||
9974a356 MC |
8596 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
8597 | u16 pcix_cmd; | |
8598 | ||
8599 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8600 | &pcix_cmd); | |
1da177e4 | 8601 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8602 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8603 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8604 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8605 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8606 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8607 | } |
9974a356 MC |
8608 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8609 | pcix_cmd); | |
1da177e4 LT |
8610 | } |
8611 | ||
8612 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8613 | udelay(40); | |
8614 | ||
8615 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
8616 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8617 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
9936bcf6 MC |
8618 | |
8619 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8620 | tw32(SNDDATAC_MODE, | |
8621 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8622 | else | |
8623 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8624 | ||
1da177e4 LT |
8625 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8626 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 8627 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
de9f5230 | 8628 | if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) |
7cb32cf2 MC |
8629 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
8630 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 8631 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
1da177e4 LT |
8632 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
8633 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
baf8a94a | 8634 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
19cfaecc | 8635 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
baf8a94a MC |
8636 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8637 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8638 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8639 | ||
8640 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8641 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8642 | if (err) | |
8643 | return err; | |
8644 | } | |
8645 | ||
1da177e4 LT |
8646 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
8647 | err = tg3_load_tso_firmware(tp); | |
8648 | if (err) | |
8649 | return err; | |
8650 | } | |
1da177e4 LT |
8651 | |
8652 | tp->tx_mode = TX_MODE_ENABLE; | |
f2096f94 | 8653 | |
b1d05210 MC |
8654 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
8655 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
8656 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
f2096f94 MC |
8657 | |
8658 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
8659 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | |
8660 | tp->tx_mode &= ~val; | |
8661 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | |
8662 | } | |
8663 | ||
1da177e4 LT |
8664 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
8665 | udelay(100); | |
8666 | ||
baf8a94a MC |
8667 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { |
8668 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8669 | u8 *ent = (u8 *)&val; | |
8670 | ||
8671 | /* Setup the indirection table */ | |
8672 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8673 | int idx = i % sizeof(val); | |
8674 | ||
5efeeea1 | 8675 | ent[idx] = i % (tp->irq_cnt - 1); |
baf8a94a MC |
8676 | if (idx == sizeof(val) - 1) { |
8677 | tw32(reg, val); | |
8678 | reg += 4; | |
8679 | } | |
8680 | } | |
8681 | ||
8682 | /* Setup the "secret" hash key. */ | |
8683 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8684 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8685 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8686 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8687 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8688 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8689 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8690 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8691 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8692 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8693 | } | |
8694 | ||
1da177e4 | 8695 | tp->rx_mode = RX_MODE_ENABLE; |
321d32a0 | 8696 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
af36e6b6 MC |
8697 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8698 | ||
baf8a94a MC |
8699 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
8700 | tp->rx_mode |= RX_MODE_RSS_ENABLE | | |
8701 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8702 | RX_MODE_RSS_IPV6_HASH_EN | | |
8703 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8704 | RX_MODE_RSS_IPV4_HASH_EN | | |
8705 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8706 | ||
1da177e4 LT |
8707 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8708 | udelay(10); | |
8709 | ||
1da177e4 LT |
8710 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8711 | ||
8712 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 8713 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
8714 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8715 | udelay(10); | |
8716 | } | |
8717 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8718 | udelay(10); | |
8719 | ||
f07e9af3 | 8720 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 8721 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 8722 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
8723 | /* Set drive transmission level to 1.2V */ |
8724 | /* only if the signal pre-emphasis bit is not set */ | |
8725 | val = tr32(MAC_SERDES_CFG); | |
8726 | val &= 0xfffff000; | |
8727 | val |= 0x880; | |
8728 | tw32(MAC_SERDES_CFG, val); | |
8729 | } | |
8730 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8731 | tw32(MAC_SERDES_CFG, 0x616000); | |
8732 | } | |
8733 | ||
8734 | /* Prevent chip from dropping frames when flow control | |
8735 | * is enabled. | |
8736 | */ | |
666bc831 MC |
8737 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8738 | val = 1; | |
8739 | else | |
8740 | val = 2; | |
8741 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
8742 | |
8743 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 8744 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 LT |
8745 | /* Use hardware link auto-negotiation */ |
8746 | tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; | |
8747 | } | |
8748 | ||
f07e9af3 | 8749 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
d4d2c558 MC |
8750 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { |
8751 | u32 tmp; | |
8752 | ||
8753 | tmp = tr32(SERDES_RX_CTRL); | |
8754 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8755 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8756 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8757 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8758 | } | |
8759 | ||
dd477003 | 8760 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
80096068 MC |
8761 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
8762 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
8763 | tp->link_config.speed = tp->link_config.orig_speed; |
8764 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8765 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8766 | } | |
1da177e4 | 8767 | |
dd477003 MC |
8768 | err = tg3_setup_phy(tp, 0); |
8769 | if (err) | |
8770 | return err; | |
1da177e4 | 8771 | |
f07e9af3 MC |
8772 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
8773 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
8774 | u32 tmp; |
8775 | ||
8776 | /* Clear CRC stats. */ | |
8777 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8778 | tg3_writephy(tp, MII_TG3_TEST1, | |
8779 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 8780 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 8781 | } |
1da177e4 LT |
8782 | } |
8783 | } | |
8784 | ||
8785 | __tg3_set_rx_mode(tp->dev); | |
8786 | ||
8787 | /* Initialize receive rules. */ | |
8788 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8789 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8790 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8791 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8792 | ||
4cf78e4f | 8793 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
a4e2b347 | 8794 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
1da177e4 LT |
8795 | limit = 8; |
8796 | else | |
8797 | limit = 16; | |
8798 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
8799 | limit -= 4; | |
8800 | switch (limit) { | |
8801 | case 16: | |
8802 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8803 | case 15: | |
8804 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8805 | case 14: | |
8806 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8807 | case 13: | |
8808 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8809 | case 12: | |
8810 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8811 | case 11: | |
8812 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8813 | case 10: | |
8814 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8815 | case 9: | |
8816 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8817 | case 8: | |
8818 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8819 | case 7: | |
8820 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8821 | case 6: | |
8822 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8823 | case 5: | |
8824 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8825 | case 4: | |
8826 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8827 | case 3: | |
8828 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8829 | case 2: | |
8830 | case 1: | |
8831 | ||
8832 | default: | |
8833 | break; | |
855e1111 | 8834 | } |
1da177e4 | 8835 | |
9ce768ea MC |
8836 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
8837 | /* Write our heartbeat update interval to APE. */ | |
8838 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8839 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 8840 | |
1da177e4 LT |
8841 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
8842 | ||
1da177e4 LT |
8843 | return 0; |
8844 | } | |
8845 | ||
8846 | /* Called at device open time to get the chip ready for | |
8847 | * packet processing. Invoked with tp->lock held. | |
8848 | */ | |
8e7a22e3 | 8849 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 8850 | { |
1da177e4 LT |
8851 | tg3_switch_clocks(tp); |
8852 | ||
8853 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8854 | ||
2f751b67 | 8855 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
8856 | } |
8857 | ||
8858 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8859 | do { u32 __val = tr32(REG); \ | |
8860 | (PSTAT)->low += __val; \ | |
8861 | if ((PSTAT)->low < __val) \ | |
8862 | (PSTAT)->high += 1; \ | |
8863 | } while (0) | |
8864 | ||
8865 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8866 | { | |
8867 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8868 | ||
8869 | if (!netif_carrier_ok(tp->dev)) | |
8870 | return; | |
8871 | ||
8872 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
8873 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
8874 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
8875 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
8876 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
8877 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
8878 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
8879 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
8880 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
8881 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
8882 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
8883 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
8884 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
8885 | ||
8886 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
8887 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
8888 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
8889 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
8890 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
8891 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
8892 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
8893 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
8894 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
8895 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
8896 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
8897 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
8898 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
8899 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
8900 | |
8901 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
4d958473 MC |
8902 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) { |
8903 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
8904 | } else { | |
8905 | u32 val = tr32(HOSTCC_FLOW_ATTN); | |
8906 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | |
8907 | if (val) { | |
8908 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | |
8909 | sp->rx_discards.low += val; | |
8910 | if (sp->rx_discards.low < val) | |
8911 | sp->rx_discards.high += 1; | |
8912 | } | |
8913 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | |
8914 | } | |
463d305b | 8915 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
1da177e4 LT |
8916 | } |
8917 | ||
8918 | static void tg3_timer(unsigned long __opaque) | |
8919 | { | |
8920 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 8921 | |
f475f163 MC |
8922 | if (tp->irq_sync) |
8923 | goto restart_timer; | |
8924 | ||
f47c11ee | 8925 | spin_lock(&tp->lock); |
1da177e4 | 8926 | |
fac9b83e DM |
8927 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { |
8928 | /* All of this garbage is because when using non-tagged | |
8929 | * IRQ status the mailbox/status_block protocol the chip | |
8930 | * uses with the cpu is race prone. | |
8931 | */ | |
898a56f8 | 8932 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
8933 | tw32(GRC_LOCAL_CTRL, |
8934 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
8935 | } else { | |
8936 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 8937 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 8938 | } |
1da177e4 | 8939 | |
fac9b83e DM |
8940 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
8941 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | |
f47c11ee | 8942 | spin_unlock(&tp->lock); |
fac9b83e DM |
8943 | schedule_work(&tp->reset_task); |
8944 | return; | |
8945 | } | |
1da177e4 LT |
8946 | } |
8947 | ||
1da177e4 LT |
8948 | /* This part only runs once per second. */ |
8949 | if (!--tp->timer_counter) { | |
fac9b83e DM |
8950 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
8951 | tg3_periodic_fetch_stats(tp); | |
8952 | ||
52b02d04 MC |
8953 | if (tp->setlpicnt && !--tp->setlpicnt) { |
8954 | u32 val = tr32(TG3_CPMU_EEE_MODE); | |
8955 | tw32(TG3_CPMU_EEE_MODE, | |
8956 | val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
8957 | } | |
8958 | ||
1da177e4 LT |
8959 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
8960 | u32 mac_stat; | |
8961 | int phy_event; | |
8962 | ||
8963 | mac_stat = tr32(MAC_STATUS); | |
8964 | ||
8965 | phy_event = 0; | |
f07e9af3 | 8966 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
8967 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
8968 | phy_event = 1; | |
8969 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
8970 | phy_event = 1; | |
8971 | ||
8972 | if (phy_event) | |
8973 | tg3_setup_phy(tp, 0); | |
8974 | } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { | |
8975 | u32 mac_stat = tr32(MAC_STATUS); | |
8976 | int need_setup = 0; | |
8977 | ||
8978 | if (netif_carrier_ok(tp->dev) && | |
8979 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
8980 | need_setup = 1; | |
8981 | } | |
be98da6a | 8982 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
8983 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
8984 | MAC_STATUS_SIGNAL_DET))) { | |
8985 | need_setup = 1; | |
8986 | } | |
8987 | if (need_setup) { | |
3d3ebe74 MC |
8988 | if (!tp->serdes_counter) { |
8989 | tw32_f(MAC_MODE, | |
8990 | (tp->mac_mode & | |
8991 | ~MAC_MODE_PORT_MODE_MASK)); | |
8992 | udelay(40); | |
8993 | tw32_f(MAC_MODE, tp->mac_mode); | |
8994 | udelay(40); | |
8995 | } | |
1da177e4 LT |
8996 | tg3_setup_phy(tp, 0); |
8997 | } | |
f07e9af3 | 8998 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
2138c002 | 8999 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
747e8f8b | 9000 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 9001 | } |
1da177e4 LT |
9002 | |
9003 | tp->timer_counter = tp->timer_multiplier; | |
9004 | } | |
9005 | ||
130b8e4d MC |
9006 | /* Heartbeat is only sent once every 2 seconds. |
9007 | * | |
9008 | * The heartbeat is to tell the ASF firmware that the host | |
9009 | * driver is still alive. In the event that the OS crashes, | |
9010 | * ASF needs to reset the hardware to free up the FIFO space | |
9011 | * that may be filled with rx packets destined for the host. | |
9012 | * If the FIFO is full, ASF will no longer function properly. | |
9013 | * | |
9014 | * Unintended resets have been reported on real time kernels | |
9015 | * where the timer doesn't run on time. Netpoll will also have | |
9016 | * same problem. | |
9017 | * | |
9018 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
9019 | * to check the ring condition when the heartbeat is expiring | |
9020 | * before doing the reset. This will prevent most unintended | |
9021 | * resets. | |
9022 | */ | |
1da177e4 | 9023 | if (!--tp->asf_counter) { |
bc7959b2 MC |
9024 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
9025 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
9026 | tg3_wait_for_event_ack(tp); |
9027 | ||
bbadf503 | 9028 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 9029 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 9030 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
9031 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
9032 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
9033 | |
9034 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
9035 | } |
9036 | tp->asf_counter = tp->asf_multiplier; | |
9037 | } | |
9038 | ||
f47c11ee | 9039 | spin_unlock(&tp->lock); |
1da177e4 | 9040 | |
f475f163 | 9041 | restart_timer: |
1da177e4 LT |
9042 | tp->timer.expires = jiffies + tp->timer_offset; |
9043 | add_timer(&tp->timer); | |
9044 | } | |
9045 | ||
4f125f42 | 9046 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 9047 | { |
7d12e780 | 9048 | irq_handler_t fn; |
fcfa0a32 | 9049 | unsigned long flags; |
4f125f42 MC |
9050 | char *name; |
9051 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
9052 | ||
9053 | if (tp->irq_cnt == 1) | |
9054 | name = tp->dev->name; | |
9055 | else { | |
9056 | name = &tnapi->irq_lbl[0]; | |
9057 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
9058 | name[IFNAMSIZ-1] = 0; | |
9059 | } | |
fcfa0a32 | 9060 | |
679563f4 | 9061 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { |
fcfa0a32 MC |
9062 | fn = tg3_msi; |
9063 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
9064 | fn = tg3_msi_1shot; | |
ab392d2d | 9065 | flags = 0; |
fcfa0a32 MC |
9066 | } else { |
9067 | fn = tg3_interrupt; | |
9068 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
9069 | fn = tg3_interrupt_tagged; | |
ab392d2d | 9070 | flags = IRQF_SHARED; |
fcfa0a32 | 9071 | } |
4f125f42 MC |
9072 | |
9073 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
9074 | } |
9075 | ||
7938109f MC |
9076 | static int tg3_test_interrupt(struct tg3 *tp) |
9077 | { | |
09943a18 | 9078 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 9079 | struct net_device *dev = tp->dev; |
b16250e3 | 9080 | int err, i, intr_ok = 0; |
f6eb9b1f | 9081 | u32 val; |
7938109f | 9082 | |
d4bc3927 MC |
9083 | if (!netif_running(dev)) |
9084 | return -ENODEV; | |
9085 | ||
7938109f MC |
9086 | tg3_disable_ints(tp); |
9087 | ||
4f125f42 | 9088 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 9089 | |
f6eb9b1f MC |
9090 | /* |
9091 | * Turn off MSI one shot mode. Otherwise this test has no | |
9092 | * observable way to know whether the interrupt was delivered. | |
9093 | */ | |
1407deb1 | 9094 | if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
f6eb9b1f MC |
9095 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
9096 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; | |
9097 | tw32(MSGINT_MODE, val); | |
9098 | } | |
9099 | ||
4f125f42 | 9100 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 9101 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
9102 | if (err) |
9103 | return err; | |
9104 | ||
898a56f8 | 9105 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
9106 | tg3_enable_ints(tp); |
9107 | ||
9108 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 9109 | tnapi->coal_now); |
7938109f MC |
9110 | |
9111 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
9112 | u32 int_mbox, misc_host_ctrl; |
9113 | ||
898a56f8 | 9114 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
9115 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
9116 | ||
9117 | if ((int_mbox != 0) || | |
9118 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
9119 | intr_ok = 1; | |
7938109f | 9120 | break; |
b16250e3 MC |
9121 | } |
9122 | ||
7938109f MC |
9123 | msleep(10); |
9124 | } | |
9125 | ||
9126 | tg3_disable_ints(tp); | |
9127 | ||
4f125f42 | 9128 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 9129 | |
4f125f42 | 9130 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9131 | |
9132 | if (err) | |
9133 | return err; | |
9134 | ||
f6eb9b1f MC |
9135 | if (intr_ok) { |
9136 | /* Reenable MSI one shot mode. */ | |
1407deb1 | 9137 | if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
f6eb9b1f MC |
9138 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
9139 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; | |
9140 | tw32(MSGINT_MODE, val); | |
9141 | } | |
7938109f | 9142 | return 0; |
f6eb9b1f | 9143 | } |
7938109f MC |
9144 | |
9145 | return -EIO; | |
9146 | } | |
9147 | ||
9148 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
9149 | * successfully restored | |
9150 | */ | |
9151 | static int tg3_test_msi(struct tg3 *tp) | |
9152 | { | |
7938109f MC |
9153 | int err; |
9154 | u16 pci_cmd; | |
9155 | ||
9156 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) | |
9157 | return 0; | |
9158 | ||
9159 | /* Turn off SERR reporting in case MSI terminates with Master | |
9160 | * Abort. | |
9161 | */ | |
9162 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
9163 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
9164 | pci_cmd & ~PCI_COMMAND_SERR); | |
9165 | ||
9166 | err = tg3_test_interrupt(tp); | |
9167 | ||
9168 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
9169 | ||
9170 | if (!err) | |
9171 | return 0; | |
9172 | ||
9173 | /* other failures */ | |
9174 | if (err != -EIO) | |
9175 | return err; | |
9176 | ||
9177 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
9178 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
9179 | "to INTx mode. Please report this failure to the PCI " | |
9180 | "maintainer and include system chipset information\n"); | |
7938109f | 9181 | |
4f125f42 | 9182 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 9183 | |
7938109f MC |
9184 | pci_disable_msi(tp->pdev); |
9185 | ||
9186 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
dc8bf1b1 | 9187 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 9188 | |
4f125f42 | 9189 | err = tg3_request_irq(tp, 0); |
7938109f MC |
9190 | if (err) |
9191 | return err; | |
9192 | ||
9193 | /* Need to reset the chip because the MSI cycle may have terminated | |
9194 | * with Master Abort. | |
9195 | */ | |
f47c11ee | 9196 | tg3_full_lock(tp, 1); |
7938109f | 9197 | |
944d980e | 9198 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 9199 | err = tg3_init_hw(tp, 1); |
7938109f | 9200 | |
f47c11ee | 9201 | tg3_full_unlock(tp); |
7938109f MC |
9202 | |
9203 | if (err) | |
4f125f42 | 9204 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
9205 | |
9206 | return err; | |
9207 | } | |
9208 | ||
9e9fd12d MC |
9209 | static int tg3_request_firmware(struct tg3 *tp) |
9210 | { | |
9211 | const __be32 *fw_data; | |
9212 | ||
9213 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
9214 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
9215 | tp->fw_needed); | |
9e9fd12d MC |
9216 | return -ENOENT; |
9217 | } | |
9218 | ||
9219 | fw_data = (void *)tp->fw->data; | |
9220 | ||
9221 | /* Firmware blob starts with version numbers, followed by | |
9222 | * start address and _full_ length including BSS sections | |
9223 | * (which must be longer than the actual data, of course | |
9224 | */ | |
9225 | ||
9226 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9227 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
9228 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
9229 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
9230 | release_firmware(tp->fw); |
9231 | tp->fw = NULL; | |
9232 | return -EINVAL; | |
9233 | } | |
9234 | ||
9235 | /* We no longer need firmware; we have it. */ | |
9236 | tp->fw_needed = NULL; | |
9237 | return 0; | |
9238 | } | |
9239 | ||
679563f4 MC |
9240 | static bool tg3_enable_msix(struct tg3 *tp) |
9241 | { | |
9242 | int i, rc, cpus = num_online_cpus(); | |
9243 | struct msix_entry msix_ent[tp->irq_max]; | |
9244 | ||
9245 | if (cpus == 1) | |
9246 | /* Just fallback to the simpler MSI mode. */ | |
9247 | return false; | |
9248 | ||
9249 | /* | |
9250 | * We want as many rx rings enabled as there are cpus. | |
9251 | * The first MSIX vector only deals with link interrupts, etc, | |
9252 | * so we add one to the number of vectors we are requesting. | |
9253 | */ | |
9254 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9255 | ||
9256 | for (i = 0; i < tp->irq_max; i++) { | |
9257 | msix_ent[i].entry = i; | |
9258 | msix_ent[i].vector = 0; | |
9259 | } | |
9260 | ||
9261 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9262 | if (rc < 0) { |
9263 | return false; | |
9264 | } else if (rc != 0) { | |
679563f4 MC |
9265 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9266 | return false; | |
05dbe005 JP |
9267 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9268 | tp->irq_cnt, rc); | |
679563f4 MC |
9269 | tp->irq_cnt = rc; |
9270 | } | |
9271 | ||
9272 | for (i = 0; i < tp->irq_max; i++) | |
9273 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9274 | ||
2ddaad39 BH |
9275 | netif_set_real_num_tx_queues(tp->dev, 1); |
9276 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9277 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9278 | pci_disable_msix(tp->pdev); | |
9279 | return false; | |
9280 | } | |
b92b9040 MC |
9281 | |
9282 | if (tp->irq_cnt > 1) { | |
2430b031 | 9283 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS; |
d78b59f5 MC |
9284 | |
9285 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9286 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b92b9040 MC |
9287 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS; |
9288 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); | |
9289 | } | |
9290 | } | |
2430b031 | 9291 | |
679563f4 MC |
9292 | return true; |
9293 | } | |
9294 | ||
07b0173c MC |
9295 | static void tg3_ints_init(struct tg3 *tp) |
9296 | { | |
679563f4 MC |
9297 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) && |
9298 | !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
07b0173c MC |
9299 | /* All MSI supporting chips should support tagged |
9300 | * status. Assert that this is the case. | |
9301 | */ | |
5129c3a3 MC |
9302 | netdev_warn(tp->dev, |
9303 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9304 | goto defcfg; |
07b0173c | 9305 | } |
4f125f42 | 9306 | |
679563f4 MC |
9307 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9308 | tp->tg3_flags2 |= TG3_FLG2_USING_MSIX; | |
9309 | else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) && | |
9310 | pci_enable_msi(tp->pdev) == 0) | |
9311 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | |
9312 | ||
9313 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { | |
9314 | u32 msi_mode = tr32(MSGINT_MODE); | |
0583d521 MC |
9315 | if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && |
9316 | tp->irq_cnt > 1) | |
baf8a94a | 9317 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
679563f4 MC |
9318 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9319 | } | |
9320 | defcfg: | |
9321 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { | |
9322 | tp->irq_cnt = 1; | |
9323 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9324 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9325 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9326 | } |
07b0173c MC |
9327 | } |
9328 | ||
9329 | static void tg3_ints_fini(struct tg3 *tp) | |
9330 | { | |
679563f4 MC |
9331 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) |
9332 | pci_disable_msix(tp->pdev); | |
9333 | else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | |
9334 | pci_disable_msi(tp->pdev); | |
9335 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX; | |
774ee752 | 9336 | tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS); |
07b0173c MC |
9337 | } |
9338 | ||
1da177e4 LT |
9339 | static int tg3_open(struct net_device *dev) |
9340 | { | |
9341 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 9342 | int i, err; |
1da177e4 | 9343 | |
9e9fd12d MC |
9344 | if (tp->fw_needed) { |
9345 | err = tg3_request_firmware(tp); | |
9346 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9347 | if (err) | |
9348 | return err; | |
9349 | } else if (err) { | |
05dbe005 | 9350 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
9e9fd12d MC |
9351 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
9352 | } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
05dbe005 | 9353 | netdev_notice(tp->dev, "TSO capability restored\n"); |
9e9fd12d MC |
9354 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
9355 | } | |
9356 | } | |
9357 | ||
c49a1561 MC |
9358 | netif_carrier_off(tp->dev); |
9359 | ||
c866b7ea | 9360 | err = tg3_power_up(tp); |
2f751b67 | 9361 | if (err) |
bc1c7567 | 9362 | return err; |
2f751b67 MC |
9363 | |
9364 | tg3_full_lock(tp, 0); | |
bc1c7567 | 9365 | |
1da177e4 LT |
9366 | tg3_disable_ints(tp); |
9367 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
9368 | ||
f47c11ee | 9369 | tg3_full_unlock(tp); |
1da177e4 | 9370 | |
679563f4 MC |
9371 | /* |
9372 | * Setup interrupts first so we know how | |
9373 | * many NAPI resources to allocate | |
9374 | */ | |
9375 | tg3_ints_init(tp); | |
9376 | ||
1da177e4 LT |
9377 | /* The placement of this call is tied |
9378 | * to the setup and use of Host TX descriptors. | |
9379 | */ | |
9380 | err = tg3_alloc_consistent(tp); | |
9381 | if (err) | |
679563f4 | 9382 | goto err_out1; |
88b06bc2 | 9383 | |
66cfd1bd MC |
9384 | tg3_napi_init(tp); |
9385 | ||
fed97810 | 9386 | tg3_napi_enable(tp); |
1da177e4 | 9387 | |
4f125f42 MC |
9388 | for (i = 0; i < tp->irq_cnt; i++) { |
9389 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9390 | err = tg3_request_irq(tp, i); | |
9391 | if (err) { | |
9392 | for (i--; i >= 0; i--) | |
9393 | free_irq(tnapi->irq_vec, tnapi); | |
9394 | break; | |
9395 | } | |
9396 | } | |
1da177e4 | 9397 | |
07b0173c | 9398 | if (err) |
679563f4 | 9399 | goto err_out2; |
bea3348e | 9400 | |
f47c11ee | 9401 | tg3_full_lock(tp, 0); |
1da177e4 | 9402 | |
8e7a22e3 | 9403 | err = tg3_init_hw(tp, 1); |
1da177e4 | 9404 | if (err) { |
944d980e | 9405 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
9406 | tg3_free_rings(tp); |
9407 | } else { | |
fac9b83e DM |
9408 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) |
9409 | tp->timer_offset = HZ; | |
9410 | else | |
9411 | tp->timer_offset = HZ / 10; | |
9412 | ||
9413 | BUG_ON(tp->timer_offset > HZ); | |
9414 | tp->timer_counter = tp->timer_multiplier = | |
9415 | (HZ / tp->timer_offset); | |
9416 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 9417 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
9418 | |
9419 | init_timer(&tp->timer); | |
9420 | tp->timer.expires = jiffies + tp->timer_offset; | |
9421 | tp->timer.data = (unsigned long) tp; | |
9422 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
9423 | } |
9424 | ||
f47c11ee | 9425 | tg3_full_unlock(tp); |
1da177e4 | 9426 | |
07b0173c | 9427 | if (err) |
679563f4 | 9428 | goto err_out3; |
1da177e4 | 9429 | |
7938109f MC |
9430 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { |
9431 | err = tg3_test_msi(tp); | |
fac9b83e | 9432 | |
7938109f | 9433 | if (err) { |
f47c11ee | 9434 | tg3_full_lock(tp, 0); |
944d980e | 9435 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 9436 | tg3_free_rings(tp); |
f47c11ee | 9437 | tg3_full_unlock(tp); |
7938109f | 9438 | |
679563f4 | 9439 | goto err_out2; |
7938109f | 9440 | } |
fcfa0a32 | 9441 | |
1407deb1 | 9442 | if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
c885e824 | 9443 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
f6eb9b1f | 9444 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 9445 | |
f6eb9b1f MC |
9446 | tw32(PCIE_TRANSACTION_CFG, |
9447 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 9448 | } |
7938109f MC |
9449 | } |
9450 | ||
b02fd9e3 MC |
9451 | tg3_phy_start(tp); |
9452 | ||
f47c11ee | 9453 | tg3_full_lock(tp, 0); |
1da177e4 | 9454 | |
7938109f MC |
9455 | add_timer(&tp->timer); |
9456 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
1da177e4 LT |
9457 | tg3_enable_ints(tp); |
9458 | ||
f47c11ee | 9459 | tg3_full_unlock(tp); |
1da177e4 | 9460 | |
fe5f5787 | 9461 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
9462 | |
9463 | return 0; | |
07b0173c | 9464 | |
679563f4 | 9465 | err_out3: |
4f125f42 MC |
9466 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9467 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9468 | free_irq(tnapi->irq_vec, tnapi); | |
9469 | } | |
07b0173c | 9470 | |
679563f4 | 9471 | err_out2: |
fed97810 | 9472 | tg3_napi_disable(tp); |
66cfd1bd | 9473 | tg3_napi_fini(tp); |
07b0173c | 9474 | tg3_free_consistent(tp); |
679563f4 MC |
9475 | |
9476 | err_out1: | |
9477 | tg3_ints_fini(tp); | |
07b0173c | 9478 | return err; |
1da177e4 LT |
9479 | } |
9480 | ||
511d2224 ED |
9481 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
9482 | struct rtnl_link_stats64 *); | |
1da177e4 LT |
9483 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); |
9484 | ||
9485 | static int tg3_close(struct net_device *dev) | |
9486 | { | |
4f125f42 | 9487 | int i; |
1da177e4 LT |
9488 | struct tg3 *tp = netdev_priv(dev); |
9489 | ||
fed97810 | 9490 | tg3_napi_disable(tp); |
28e53bdd | 9491 | cancel_work_sync(&tp->reset_task); |
7faa006f | 9492 | |
fe5f5787 | 9493 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
9494 | |
9495 | del_timer_sync(&tp->timer); | |
9496 | ||
24bb4fb6 MC |
9497 | tg3_phy_stop(tp); |
9498 | ||
f47c11ee | 9499 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9500 | |
9501 | tg3_disable_ints(tp); | |
9502 | ||
944d980e | 9503 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9504 | tg3_free_rings(tp); |
5cf64b8a | 9505 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
1da177e4 | 9506 | |
f47c11ee | 9507 | tg3_full_unlock(tp); |
1da177e4 | 9508 | |
4f125f42 MC |
9509 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9510 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9511 | free_irq(tnapi->irq_vec, tnapi); | |
9512 | } | |
07b0173c MC |
9513 | |
9514 | tg3_ints_fini(tp); | |
1da177e4 | 9515 | |
511d2224 ED |
9516 | tg3_get_stats64(tp->dev, &tp->net_stats_prev); |
9517 | ||
1da177e4 LT |
9518 | memcpy(&tp->estats_prev, tg3_get_estats(tp), |
9519 | sizeof(tp->estats_prev)); | |
9520 | ||
66cfd1bd MC |
9521 | tg3_napi_fini(tp); |
9522 | ||
1da177e4 LT |
9523 | tg3_free_consistent(tp); |
9524 | ||
c866b7ea | 9525 | tg3_power_down(tp); |
bc1c7567 MC |
9526 | |
9527 | netif_carrier_off(tp->dev); | |
9528 | ||
1da177e4 LT |
9529 | return 0; |
9530 | } | |
9531 | ||
511d2224 | 9532 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
9533 | { |
9534 | return ((u64)val->high << 32) | ((u64)val->low); | |
9535 | } | |
9536 | ||
511d2224 | 9537 | static u64 calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
9538 | { |
9539 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9540 | ||
f07e9af3 | 9541 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
9542 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
9543 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9544 | u32 val; |
9545 | ||
f47c11ee | 9546 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9547 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9548 | tg3_writephy(tp, MII_TG3_TEST1, | |
9549 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9550 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
9551 | } else |
9552 | val = 0; | |
f47c11ee | 9553 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9554 | |
9555 | tp->phy_crc_errors += val; | |
9556 | ||
9557 | return tp->phy_crc_errors; | |
9558 | } | |
9559 | ||
9560 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9561 | } | |
9562 | ||
9563 | #define ESTAT_ADD(member) \ | |
9564 | estats->member = old_estats->member + \ | |
511d2224 | 9565 | get_stat64(&hw_stats->member) |
1da177e4 LT |
9566 | |
9567 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9568 | { | |
9569 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9570 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9571 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9572 | ||
9573 | if (!hw_stats) | |
9574 | return old_estats; | |
9575 | ||
9576 | ESTAT_ADD(rx_octets); | |
9577 | ESTAT_ADD(rx_fragments); | |
9578 | ESTAT_ADD(rx_ucast_packets); | |
9579 | ESTAT_ADD(rx_mcast_packets); | |
9580 | ESTAT_ADD(rx_bcast_packets); | |
9581 | ESTAT_ADD(rx_fcs_errors); | |
9582 | ESTAT_ADD(rx_align_errors); | |
9583 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9584 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9585 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9586 | ESTAT_ADD(rx_xoff_entered); | |
9587 | ESTAT_ADD(rx_frame_too_long_errors); | |
9588 | ESTAT_ADD(rx_jabbers); | |
9589 | ESTAT_ADD(rx_undersize_packets); | |
9590 | ESTAT_ADD(rx_in_length_errors); | |
9591 | ESTAT_ADD(rx_out_length_errors); | |
9592 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9593 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9594 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9595 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9596 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9597 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9598 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9599 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9600 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9601 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9602 | ||
9603 | ESTAT_ADD(tx_octets); | |
9604 | ESTAT_ADD(tx_collisions); | |
9605 | ESTAT_ADD(tx_xon_sent); | |
9606 | ESTAT_ADD(tx_xoff_sent); | |
9607 | ESTAT_ADD(tx_flow_control); | |
9608 | ESTAT_ADD(tx_mac_errors); | |
9609 | ESTAT_ADD(tx_single_collisions); | |
9610 | ESTAT_ADD(tx_mult_collisions); | |
9611 | ESTAT_ADD(tx_deferred); | |
9612 | ESTAT_ADD(tx_excessive_collisions); | |
9613 | ESTAT_ADD(tx_late_collisions); | |
9614 | ESTAT_ADD(tx_collide_2times); | |
9615 | ESTAT_ADD(tx_collide_3times); | |
9616 | ESTAT_ADD(tx_collide_4times); | |
9617 | ESTAT_ADD(tx_collide_5times); | |
9618 | ESTAT_ADD(tx_collide_6times); | |
9619 | ESTAT_ADD(tx_collide_7times); | |
9620 | ESTAT_ADD(tx_collide_8times); | |
9621 | ESTAT_ADD(tx_collide_9times); | |
9622 | ESTAT_ADD(tx_collide_10times); | |
9623 | ESTAT_ADD(tx_collide_11times); | |
9624 | ESTAT_ADD(tx_collide_12times); | |
9625 | ESTAT_ADD(tx_collide_13times); | |
9626 | ESTAT_ADD(tx_collide_14times); | |
9627 | ESTAT_ADD(tx_collide_15times); | |
9628 | ESTAT_ADD(tx_ucast_packets); | |
9629 | ESTAT_ADD(tx_mcast_packets); | |
9630 | ESTAT_ADD(tx_bcast_packets); | |
9631 | ESTAT_ADD(tx_carrier_sense_errors); | |
9632 | ESTAT_ADD(tx_discards); | |
9633 | ESTAT_ADD(tx_errors); | |
9634 | ||
9635 | ESTAT_ADD(dma_writeq_full); | |
9636 | ESTAT_ADD(dma_write_prioq_full); | |
9637 | ESTAT_ADD(rxbds_empty); | |
9638 | ESTAT_ADD(rx_discards); | |
9639 | ESTAT_ADD(rx_errors); | |
9640 | ESTAT_ADD(rx_threshold_hit); | |
9641 | ||
9642 | ESTAT_ADD(dma_readq_full); | |
9643 | ESTAT_ADD(dma_read_prioq_full); | |
9644 | ESTAT_ADD(tx_comp_queue_full); | |
9645 | ||
9646 | ESTAT_ADD(ring_set_send_prod_index); | |
9647 | ESTAT_ADD(ring_status_update); | |
9648 | ESTAT_ADD(nic_irqs); | |
9649 | ESTAT_ADD(nic_avoided_irqs); | |
9650 | ESTAT_ADD(nic_tx_threshold_hit); | |
9651 | ||
9652 | return estats; | |
9653 | } | |
9654 | ||
511d2224 ED |
9655 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
9656 | struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
9657 | { |
9658 | struct tg3 *tp = netdev_priv(dev); | |
511d2224 | 9659 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
9660 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
9661 | ||
9662 | if (!hw_stats) | |
9663 | return old_stats; | |
9664 | ||
9665 | stats->rx_packets = old_stats->rx_packets + | |
9666 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9667 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9668 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9669 | |
1da177e4 LT |
9670 | stats->tx_packets = old_stats->tx_packets + |
9671 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9672 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9673 | get_stat64(&hw_stats->tx_bcast_packets); | |
9674 | ||
9675 | stats->rx_bytes = old_stats->rx_bytes + | |
9676 | get_stat64(&hw_stats->rx_octets); | |
9677 | stats->tx_bytes = old_stats->tx_bytes + | |
9678 | get_stat64(&hw_stats->tx_octets); | |
9679 | ||
9680 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9681 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9682 | stats->tx_errors = old_stats->tx_errors + |
9683 | get_stat64(&hw_stats->tx_errors) + | |
9684 | get_stat64(&hw_stats->tx_mac_errors) + | |
9685 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9686 | get_stat64(&hw_stats->tx_discards); | |
9687 | ||
9688 | stats->multicast = old_stats->multicast + | |
9689 | get_stat64(&hw_stats->rx_mcast_packets); | |
9690 | stats->collisions = old_stats->collisions + | |
9691 | get_stat64(&hw_stats->tx_collisions); | |
9692 | ||
9693 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9694 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9695 | get_stat64(&hw_stats->rx_undersize_packets); | |
9696 | ||
9697 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9698 | get_stat64(&hw_stats->rxbds_empty); | |
9699 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9700 | get_stat64(&hw_stats->rx_align_errors); | |
9701 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9702 | get_stat64(&hw_stats->tx_discards); | |
9703 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9704 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9705 | ||
9706 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9707 | calc_crc_errors(tp); | |
9708 | ||
4f63b877 JL |
9709 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
9710 | get_stat64(&hw_stats->rx_discards); | |
9711 | ||
b0057c51 ED |
9712 | stats->rx_dropped = tp->rx_dropped; |
9713 | ||
1da177e4 LT |
9714 | return stats; |
9715 | } | |
9716 | ||
9717 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9718 | { | |
9719 | u32 reg; | |
9720 | u32 tmp; | |
9721 | int j, k; | |
9722 | ||
9723 | reg = 0xffffffff; | |
9724 | ||
9725 | for (j = 0; j < len; j++) { | |
9726 | reg ^= buf[j]; | |
9727 | ||
9728 | for (k = 0; k < 8; k++) { | |
9729 | tmp = reg & 0x01; | |
9730 | ||
9731 | reg >>= 1; | |
9732 | ||
859a5887 | 9733 | if (tmp) |
1da177e4 | 9734 | reg ^= 0xedb88320; |
1da177e4 LT |
9735 | } |
9736 | } | |
9737 | ||
9738 | return ~reg; | |
9739 | } | |
9740 | ||
9741 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9742 | { | |
9743 | /* accept or reject all multicast frames */ | |
9744 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9745 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9746 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9747 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9748 | } | |
9749 | ||
9750 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9751 | { | |
9752 | struct tg3 *tp = netdev_priv(dev); | |
9753 | u32 rx_mode; | |
9754 | ||
9755 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9756 | RX_MODE_KEEP_VLAN_TAG); | |
9757 | ||
bf933c80 | 9758 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
1da177e4 LT |
9759 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
9760 | * flag clear. | |
9761 | */ | |
1da177e4 LT |
9762 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
9763 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9764 | #endif | |
9765 | ||
9766 | if (dev->flags & IFF_PROMISC) { | |
9767 | /* Promiscuous mode. */ | |
9768 | rx_mode |= RX_MODE_PROMISC; | |
9769 | } else if (dev->flags & IFF_ALLMULTI) { | |
9770 | /* Accept all multicast. */ | |
de6f31eb | 9771 | tg3_set_multi(tp, 1); |
4cd24eaf | 9772 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 9773 | /* Reject all multicast. */ |
de6f31eb | 9774 | tg3_set_multi(tp, 0); |
1da177e4 LT |
9775 | } else { |
9776 | /* Accept one or more multicast(s). */ | |
22bedad3 | 9777 | struct netdev_hw_addr *ha; |
1da177e4 LT |
9778 | u32 mc_filter[4] = { 0, }; |
9779 | u32 regidx; | |
9780 | u32 bit; | |
9781 | u32 crc; | |
9782 | ||
22bedad3 JP |
9783 | netdev_for_each_mc_addr(ha, dev) { |
9784 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
9785 | bit = ~crc & 0x7f; |
9786 | regidx = (bit & 0x60) >> 5; | |
9787 | bit &= 0x1f; | |
9788 | mc_filter[regidx] |= (1 << bit); | |
9789 | } | |
9790 | ||
9791 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9792 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9793 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9794 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9795 | } | |
9796 | ||
9797 | if (rx_mode != tp->rx_mode) { | |
9798 | tp->rx_mode = rx_mode; | |
9799 | tw32_f(MAC_RX_MODE, rx_mode); | |
9800 | udelay(10); | |
9801 | } | |
9802 | } | |
9803 | ||
9804 | static void tg3_set_rx_mode(struct net_device *dev) | |
9805 | { | |
9806 | struct tg3 *tp = netdev_priv(dev); | |
9807 | ||
e75f7c90 MC |
9808 | if (!netif_running(dev)) |
9809 | return; | |
9810 | ||
f47c11ee | 9811 | tg3_full_lock(tp, 0); |
1da177e4 | 9812 | __tg3_set_rx_mode(dev); |
f47c11ee | 9813 | tg3_full_unlock(tp); |
1da177e4 LT |
9814 | } |
9815 | ||
1da177e4 LT |
9816 | static int tg3_get_regs_len(struct net_device *dev) |
9817 | { | |
97bd8e49 | 9818 | return TG3_REG_BLK_SIZE; |
1da177e4 LT |
9819 | } |
9820 | ||
9821 | static void tg3_get_regs(struct net_device *dev, | |
9822 | struct ethtool_regs *regs, void *_p) | |
9823 | { | |
1da177e4 | 9824 | struct tg3 *tp = netdev_priv(dev); |
1da177e4 LT |
9825 | |
9826 | regs->version = 0; | |
9827 | ||
97bd8e49 | 9828 | memset(_p, 0, TG3_REG_BLK_SIZE); |
1da177e4 | 9829 | |
80096068 | 9830 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9831 | return; |
9832 | ||
f47c11ee | 9833 | tg3_full_lock(tp, 0); |
1da177e4 | 9834 | |
97bd8e49 | 9835 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
1da177e4 | 9836 | |
f47c11ee | 9837 | tg3_full_unlock(tp); |
1da177e4 LT |
9838 | } |
9839 | ||
9840 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9841 | { | |
9842 | struct tg3 *tp = netdev_priv(dev); | |
9843 | ||
9844 | return tp->nvram_size; | |
9845 | } | |
9846 | ||
1da177e4 LT |
9847 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
9848 | { | |
9849 | struct tg3 *tp = netdev_priv(dev); | |
9850 | int ret; | |
9851 | u8 *pd; | |
b9fc7dc5 | 9852 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 9853 | __be32 val; |
1da177e4 | 9854 | |
df259d8c MC |
9855 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
9856 | return -EINVAL; | |
9857 | ||
80096068 | 9858 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9859 | return -EAGAIN; |
9860 | ||
1da177e4 LT |
9861 | offset = eeprom->offset; |
9862 | len = eeprom->len; | |
9863 | eeprom->len = 0; | |
9864 | ||
9865 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9866 | ||
9867 | if (offset & 3) { | |
9868 | /* adjustments to start on required 4 byte boundary */ | |
9869 | b_offset = offset & 3; | |
9870 | b_count = 4 - b_offset; | |
9871 | if (b_count > len) { | |
9872 | /* i.e. offset=1 len=2 */ | |
9873 | b_count = len; | |
9874 | } | |
a9dc529d | 9875 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
9876 | if (ret) |
9877 | return ret; | |
be98da6a | 9878 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
9879 | len -= b_count; |
9880 | offset += b_count; | |
c6cdf436 | 9881 | eeprom->len += b_count; |
1da177e4 LT |
9882 | } |
9883 | ||
25985edc | 9884 | /* read bytes up to the last 4 byte boundary */ |
1da177e4 LT |
9885 | pd = &data[eeprom->len]; |
9886 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 9887 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
9888 | if (ret) { |
9889 | eeprom->len += i; | |
9890 | return ret; | |
9891 | } | |
1da177e4 LT |
9892 | memcpy(pd + i, &val, 4); |
9893 | } | |
9894 | eeprom->len += i; | |
9895 | ||
9896 | if (len & 3) { | |
9897 | /* read last bytes not ending on 4 byte boundary */ | |
9898 | pd = &data[eeprom->len]; | |
9899 | b_count = len & 3; | |
9900 | b_offset = offset + len - b_count; | |
a9dc529d | 9901 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
9902 | if (ret) |
9903 | return ret; | |
b9fc7dc5 | 9904 | memcpy(pd, &val, b_count); |
1da177e4 LT |
9905 | eeprom->len += b_count; |
9906 | } | |
9907 | return 0; | |
9908 | } | |
9909 | ||
6aa20a22 | 9910 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
9911 | |
9912 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9913 | { | |
9914 | struct tg3 *tp = netdev_priv(dev); | |
9915 | int ret; | |
b9fc7dc5 | 9916 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 9917 | u8 *buf; |
a9dc529d | 9918 | __be32 start, end; |
1da177e4 | 9919 | |
80096068 | 9920 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9921 | return -EAGAIN; |
9922 | ||
df259d8c MC |
9923 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
9924 | eeprom->magic != TG3_EEPROM_MAGIC) | |
1da177e4 LT |
9925 | return -EINVAL; |
9926 | ||
9927 | offset = eeprom->offset; | |
9928 | len = eeprom->len; | |
9929 | ||
9930 | if ((b_offset = (offset & 3))) { | |
9931 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 9932 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
9933 | if (ret) |
9934 | return ret; | |
1da177e4 LT |
9935 | len += b_offset; |
9936 | offset &= ~3; | |
1c8594b4 MC |
9937 | if (len < 4) |
9938 | len = 4; | |
1da177e4 LT |
9939 | } |
9940 | ||
9941 | odd_len = 0; | |
1c8594b4 | 9942 | if (len & 3) { |
1da177e4 LT |
9943 | /* adjustments to end on required 4 byte boundary */ |
9944 | odd_len = 1; | |
9945 | len = (len + 3) & ~3; | |
a9dc529d | 9946 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
9947 | if (ret) |
9948 | return ret; | |
1da177e4 LT |
9949 | } |
9950 | ||
9951 | buf = data; | |
9952 | if (b_offset || odd_len) { | |
9953 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 9954 | if (!buf) |
1da177e4 LT |
9955 | return -ENOMEM; |
9956 | if (b_offset) | |
9957 | memcpy(buf, &start, 4); | |
9958 | if (odd_len) | |
9959 | memcpy(buf+len-4, &end, 4); | |
9960 | memcpy(buf + b_offset, data, eeprom->len); | |
9961 | } | |
9962 | ||
9963 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
9964 | ||
9965 | if (buf != data) | |
9966 | kfree(buf); | |
9967 | ||
9968 | return ret; | |
9969 | } | |
9970 | ||
9971 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9972 | { | |
b02fd9e3 MC |
9973 | struct tg3 *tp = netdev_priv(dev); |
9974 | ||
9975 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
3f0e3ad7 | 9976 | struct phy_device *phydev; |
f07e9af3 | 9977 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 9978 | return -EAGAIN; |
3f0e3ad7 MC |
9979 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9980 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 9981 | } |
6aa20a22 | 9982 | |
1da177e4 LT |
9983 | cmd->supported = (SUPPORTED_Autoneg); |
9984 | ||
f07e9af3 | 9985 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
9986 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
9987 | SUPPORTED_1000baseT_Full); | |
9988 | ||
f07e9af3 | 9989 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
9990 | cmd->supported |= (SUPPORTED_100baseT_Half | |
9991 | SUPPORTED_100baseT_Full | | |
9992 | SUPPORTED_10baseT_Half | | |
9993 | SUPPORTED_10baseT_Full | | |
3bebab59 | 9994 | SUPPORTED_TP); |
ef348144 KK |
9995 | cmd->port = PORT_TP; |
9996 | } else { | |
1da177e4 | 9997 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
9998 | cmd->port = PORT_FIBRE; |
9999 | } | |
6aa20a22 | 10000 | |
1da177e4 LT |
10001 | cmd->advertising = tp->link_config.advertising; |
10002 | if (netif_running(dev)) { | |
10003 | cmd->speed = tp->link_config.active_speed; | |
10004 | cmd->duplex = tp->link_config.active_duplex; | |
64c22182 MC |
10005 | } else { |
10006 | cmd->speed = SPEED_INVALID; | |
10007 | cmd->duplex = DUPLEX_INVALID; | |
1da177e4 | 10008 | } |
882e9793 | 10009 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 10010 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
10011 | cmd->autoneg = tp->link_config.autoneg; |
10012 | cmd->maxtxpkt = 0; | |
10013 | cmd->maxrxpkt = 0; | |
10014 | return 0; | |
10015 | } | |
6aa20a22 | 10016 | |
1da177e4 LT |
10017 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
10018 | { | |
10019 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10020 | |
b02fd9e3 | 10021 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 10022 | struct phy_device *phydev; |
f07e9af3 | 10023 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10024 | return -EAGAIN; |
3f0e3ad7 MC |
10025 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10026 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
10027 | } |
10028 | ||
7e5856bd MC |
10029 | if (cmd->autoneg != AUTONEG_ENABLE && |
10030 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 10031 | return -EINVAL; |
7e5856bd MC |
10032 | |
10033 | if (cmd->autoneg == AUTONEG_DISABLE && | |
10034 | cmd->duplex != DUPLEX_FULL && | |
10035 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 10036 | return -EINVAL; |
1da177e4 | 10037 | |
7e5856bd MC |
10038 | if (cmd->autoneg == AUTONEG_ENABLE) { |
10039 | u32 mask = ADVERTISED_Autoneg | | |
10040 | ADVERTISED_Pause | | |
10041 | ADVERTISED_Asym_Pause; | |
10042 | ||
f07e9af3 | 10043 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
10044 | mask |= ADVERTISED_1000baseT_Half | |
10045 | ADVERTISED_1000baseT_Full; | |
10046 | ||
f07e9af3 | 10047 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
10048 | mask |= ADVERTISED_100baseT_Half | |
10049 | ADVERTISED_100baseT_Full | | |
10050 | ADVERTISED_10baseT_Half | | |
10051 | ADVERTISED_10baseT_Full | | |
10052 | ADVERTISED_TP; | |
10053 | else | |
10054 | mask |= ADVERTISED_FIBRE; | |
10055 | ||
10056 | if (cmd->advertising & ~mask) | |
10057 | return -EINVAL; | |
10058 | ||
10059 | mask &= (ADVERTISED_1000baseT_Half | | |
10060 | ADVERTISED_1000baseT_Full | | |
10061 | ADVERTISED_100baseT_Half | | |
10062 | ADVERTISED_100baseT_Full | | |
10063 | ADVERTISED_10baseT_Half | | |
10064 | ADVERTISED_10baseT_Full); | |
10065 | ||
10066 | cmd->advertising &= mask; | |
10067 | } else { | |
f07e9af3 | 10068 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
7e5856bd MC |
10069 | if (cmd->speed != SPEED_1000) |
10070 | return -EINVAL; | |
10071 | ||
10072 | if (cmd->duplex != DUPLEX_FULL) | |
10073 | return -EINVAL; | |
10074 | } else { | |
10075 | if (cmd->speed != SPEED_100 && | |
10076 | cmd->speed != SPEED_10) | |
10077 | return -EINVAL; | |
10078 | } | |
10079 | } | |
10080 | ||
f47c11ee | 10081 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10082 | |
10083 | tp->link_config.autoneg = cmd->autoneg; | |
10084 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
10085 | tp->link_config.advertising = (cmd->advertising | |
10086 | ADVERTISED_Autoneg); | |
1da177e4 LT |
10087 | tp->link_config.speed = SPEED_INVALID; |
10088 | tp->link_config.duplex = DUPLEX_INVALID; | |
10089 | } else { | |
10090 | tp->link_config.advertising = 0; | |
10091 | tp->link_config.speed = cmd->speed; | |
10092 | tp->link_config.duplex = cmd->duplex; | |
b02fd9e3 | 10093 | } |
6aa20a22 | 10094 | |
24fcad6b MC |
10095 | tp->link_config.orig_speed = tp->link_config.speed; |
10096 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
10097 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
10098 | ||
1da177e4 LT |
10099 | if (netif_running(dev)) |
10100 | tg3_setup_phy(tp, 1); | |
10101 | ||
f47c11ee | 10102 | tg3_full_unlock(tp); |
6aa20a22 | 10103 | |
1da177e4 LT |
10104 | return 0; |
10105 | } | |
6aa20a22 | 10106 | |
1da177e4 LT |
10107 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
10108 | { | |
10109 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10110 | |
1da177e4 LT |
10111 | strcpy(info->driver, DRV_MODULE_NAME); |
10112 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 10113 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
10114 | strcpy(info->bus_info, pci_name(tp->pdev)); |
10115 | } | |
6aa20a22 | 10116 | |
1da177e4 LT |
10117 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10118 | { | |
10119 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10120 | |
12dac075 RW |
10121 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
10122 | device_can_wakeup(&tp->pdev->dev)) | |
a85feb8c GZ |
10123 | wol->supported = WAKE_MAGIC; |
10124 | else | |
10125 | wol->supported = 0; | |
1da177e4 | 10126 | wol->wolopts = 0; |
05ac4cb7 MC |
10127 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && |
10128 | device_can_wakeup(&tp->pdev->dev)) | |
1da177e4 LT |
10129 | wol->wolopts = WAKE_MAGIC; |
10130 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
10131 | } | |
6aa20a22 | 10132 | |
1da177e4 LT |
10133 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
10134 | { | |
10135 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 10136 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 10137 | |
1da177e4 LT |
10138 | if (wol->wolopts & ~WAKE_MAGIC) |
10139 | return -EINVAL; | |
10140 | if ((wol->wolopts & WAKE_MAGIC) && | |
12dac075 | 10141 | !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 10142 | return -EINVAL; |
6aa20a22 | 10143 | |
f2dc0d18 RW |
10144 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
10145 | ||
f47c11ee | 10146 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 10147 | if (device_may_wakeup(dp)) |
1da177e4 | 10148 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
f2dc0d18 | 10149 | else |
1da177e4 | 10150 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; |
f47c11ee | 10151 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10152 | |
f2dc0d18 | 10153 | |
1da177e4 LT |
10154 | return 0; |
10155 | } | |
6aa20a22 | 10156 | |
1da177e4 LT |
10157 | static u32 tg3_get_msglevel(struct net_device *dev) |
10158 | { | |
10159 | struct tg3 *tp = netdev_priv(dev); | |
10160 | return tp->msg_enable; | |
10161 | } | |
6aa20a22 | 10162 | |
1da177e4 LT |
10163 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
10164 | { | |
10165 | struct tg3 *tp = netdev_priv(dev); | |
10166 | tp->msg_enable = value; | |
10167 | } | |
6aa20a22 | 10168 | |
1da177e4 LT |
10169 | static int tg3_nway_reset(struct net_device *dev) |
10170 | { | |
10171 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10172 | int r; |
6aa20a22 | 10173 | |
1da177e4 LT |
10174 | if (!netif_running(dev)) |
10175 | return -EAGAIN; | |
10176 | ||
f07e9af3 | 10177 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10178 | return -EINVAL; |
10179 | ||
b02fd9e3 | 10180 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
f07e9af3 | 10181 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10182 | return -EAGAIN; |
3f0e3ad7 | 10183 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10184 | } else { |
10185 | u32 bmcr; | |
10186 | ||
10187 | spin_lock_bh(&tp->lock); | |
10188 | r = -EINVAL; | |
10189 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10190 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10191 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10192 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10193 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10194 | BMCR_ANENABLE); | |
10195 | r = 0; | |
10196 | } | |
10197 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10198 | } |
6aa20a22 | 10199 | |
1da177e4 LT |
10200 | return r; |
10201 | } | |
6aa20a22 | 10202 | |
1da177e4 LT |
10203 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10204 | { | |
10205 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10206 | |
2c49a44d | 10207 | ering->rx_max_pending = tp->rx_std_ring_mask; |
1da177e4 | 10208 | ering->rx_mini_max_pending = 0; |
4f81c32b | 10209 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
2c49a44d | 10210 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10211 | else |
10212 | ering->rx_jumbo_max_pending = 0; | |
10213 | ||
10214 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10215 | |
10216 | ering->rx_pending = tp->rx_pending; | |
10217 | ering->rx_mini_pending = 0; | |
4f81c32b MC |
10218 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
10219 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
10220 | else | |
10221 | ering->rx_jumbo_pending = 0; | |
10222 | ||
f3f3f27e | 10223 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10224 | } |
6aa20a22 | 10225 | |
1da177e4 LT |
10226 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10227 | { | |
10228 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10229 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10230 | |
2c49a44d MC |
10231 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10232 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10233 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10234 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
7f62ad5d | 10235 | ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && |
bc3a9254 | 10236 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10237 | return -EINVAL; |
6aa20a22 | 10238 | |
bbe832c0 | 10239 | if (netif_running(dev)) { |
b02fd9e3 | 10240 | tg3_phy_stop(tp); |
1da177e4 | 10241 | tg3_netif_stop(tp); |
bbe832c0 MC |
10242 | irq_sync = 1; |
10243 | } | |
1da177e4 | 10244 | |
bbe832c0 | 10245 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10246 | |
1da177e4 LT |
10247 | tp->rx_pending = ering->rx_pending; |
10248 | ||
10249 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | |
10250 | tp->rx_pending > 63) | |
10251 | tp->rx_pending = 63; | |
10252 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10253 | |
6fd45cb8 | 10254 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10255 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10256 | |
10257 | if (netif_running(dev)) { | |
944d980e | 10258 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10259 | err = tg3_restart_hw(tp, 1); |
10260 | if (!err) | |
10261 | tg3_netif_start(tp); | |
1da177e4 LT |
10262 | } |
10263 | ||
f47c11ee | 10264 | tg3_full_unlock(tp); |
6aa20a22 | 10265 | |
b02fd9e3 MC |
10266 | if (irq_sync && !err) |
10267 | tg3_phy_start(tp); | |
10268 | ||
b9ec6c1b | 10269 | return err; |
1da177e4 | 10270 | } |
6aa20a22 | 10271 | |
1da177e4 LT |
10272 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10273 | { | |
10274 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10275 | |
1da177e4 | 10276 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; |
8d018621 | 10277 | |
e18ce346 | 10278 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10279 | epause->rx_pause = 1; |
10280 | else | |
10281 | epause->rx_pause = 0; | |
10282 | ||
e18ce346 | 10283 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10284 | epause->tx_pause = 1; |
10285 | else | |
10286 | epause->tx_pause = 0; | |
1da177e4 | 10287 | } |
6aa20a22 | 10288 | |
1da177e4 LT |
10289 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10290 | { | |
10291 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10292 | int err = 0; |
6aa20a22 | 10293 | |
b02fd9e3 | 10294 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
2712168f MC |
10295 | u32 newadv; |
10296 | struct phy_device *phydev; | |
1da177e4 | 10297 | |
2712168f | 10298 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10299 | |
2712168f MC |
10300 | if (!(phydev->supported & SUPPORTED_Pause) || |
10301 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10302 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10303 | return -EINVAL; |
1da177e4 | 10304 | |
2712168f MC |
10305 | tp->link_config.flowctrl = 0; |
10306 | if (epause->rx_pause) { | |
10307 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10308 | ||
10309 | if (epause->tx_pause) { | |
10310 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10311 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10312 | } else |
2712168f MC |
10313 | newadv = ADVERTISED_Pause | |
10314 | ADVERTISED_Asym_Pause; | |
10315 | } else if (epause->tx_pause) { | |
10316 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10317 | newadv = ADVERTISED_Asym_Pause; | |
10318 | } else | |
10319 | newadv = 0; | |
10320 | ||
10321 | if (epause->autoneg) | |
10322 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
10323 | else | |
10324 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
10325 | ||
f07e9af3 | 10326 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10327 | u32 oldadv = phydev->advertising & |
10328 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10329 | if (oldadv != newadv) { | |
10330 | phydev->advertising &= | |
10331 | ~(ADVERTISED_Pause | | |
10332 | ADVERTISED_Asym_Pause); | |
10333 | phydev->advertising |= newadv; | |
10334 | if (phydev->autoneg) { | |
10335 | /* | |
10336 | * Always renegotiate the link to | |
10337 | * inform our link partner of our | |
10338 | * flow control settings, even if the | |
10339 | * flow control is forced. Let | |
10340 | * tg3_adjust_link() do the final | |
10341 | * flow control setup. | |
10342 | */ | |
10343 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10344 | } |
b02fd9e3 | 10345 | } |
b02fd9e3 | 10346 | |
2712168f | 10347 | if (!epause->autoneg) |
b02fd9e3 | 10348 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
10349 | } else { |
10350 | tp->link_config.orig_advertising &= | |
10351 | ~(ADVERTISED_Pause | | |
10352 | ADVERTISED_Asym_Pause); | |
10353 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
10354 | } |
10355 | } else { | |
10356 | int irq_sync = 0; | |
10357 | ||
10358 | if (netif_running(dev)) { | |
10359 | tg3_netif_stop(tp); | |
10360 | irq_sync = 1; | |
10361 | } | |
10362 | ||
10363 | tg3_full_lock(tp, irq_sync); | |
10364 | ||
10365 | if (epause->autoneg) | |
10366 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
10367 | else | |
10368 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
10369 | if (epause->rx_pause) | |
e18ce346 | 10370 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10371 | else |
e18ce346 | 10372 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10373 | if (epause->tx_pause) |
e18ce346 | 10374 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10375 | else |
e18ce346 | 10376 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10377 | |
10378 | if (netif_running(dev)) { | |
10379 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10380 | err = tg3_restart_hw(tp, 1); | |
10381 | if (!err) | |
10382 | tg3_netif_start(tp); | |
10383 | } | |
10384 | ||
10385 | tg3_full_unlock(tp); | |
10386 | } | |
6aa20a22 | 10387 | |
b9ec6c1b | 10388 | return err; |
1da177e4 | 10389 | } |
6aa20a22 | 10390 | |
de6f31eb | 10391 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10392 | { |
b9f2c044 JG |
10393 | switch (sset) { |
10394 | case ETH_SS_TEST: | |
10395 | return TG3_NUM_TEST; | |
10396 | case ETH_SS_STATS: | |
10397 | return TG3_NUM_STATS; | |
10398 | default: | |
10399 | return -EOPNOTSUPP; | |
10400 | } | |
4cafd3f5 MC |
10401 | } |
10402 | ||
de6f31eb | 10403 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10404 | { |
10405 | switch (stringset) { | |
10406 | case ETH_SS_STATS: | |
10407 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10408 | break; | |
4cafd3f5 MC |
10409 | case ETH_SS_TEST: |
10410 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10411 | break; | |
1da177e4 LT |
10412 | default: |
10413 | WARN_ON(1); /* we need a WARN() */ | |
10414 | break; | |
10415 | } | |
10416 | } | |
10417 | ||
81b8709c | 10418 | static int tg3_set_phys_id(struct net_device *dev, |
10419 | enum ethtool_phys_id_state state) | |
4009a93d MC |
10420 | { |
10421 | struct tg3 *tp = netdev_priv(dev); | |
4009a93d MC |
10422 | |
10423 | if (!netif_running(tp->dev)) | |
10424 | return -EAGAIN; | |
10425 | ||
81b8709c | 10426 | switch (state) { |
10427 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 10428 | return 1; /* cycle on/off once per second */ |
4009a93d | 10429 | |
81b8709c | 10430 | case ETHTOOL_ID_ON: |
10431 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10432 | LED_CTRL_1000MBPS_ON | | |
10433 | LED_CTRL_100MBPS_ON | | |
10434 | LED_CTRL_10MBPS_ON | | |
10435 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10436 | LED_CTRL_TRAFFIC_BLINK | | |
10437 | LED_CTRL_TRAFFIC_LED); | |
10438 | break; | |
6aa20a22 | 10439 | |
81b8709c | 10440 | case ETHTOOL_ID_OFF: |
10441 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10442 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10443 | break; | |
4009a93d | 10444 | |
81b8709c | 10445 | case ETHTOOL_ID_INACTIVE: |
10446 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10447 | break; | |
4009a93d | 10448 | } |
81b8709c | 10449 | |
4009a93d MC |
10450 | return 0; |
10451 | } | |
10452 | ||
de6f31eb | 10453 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10454 | struct ethtool_stats *estats, u64 *tmp_stats) |
10455 | { | |
10456 | struct tg3 *tp = netdev_priv(dev); | |
10457 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10458 | } | |
10459 | ||
c3e94500 MC |
10460 | static __be32 * tg3_vpd_readblock(struct tg3 *tp) |
10461 | { | |
10462 | int i; | |
10463 | __be32 *buf; | |
10464 | u32 offset = 0, len = 0; | |
10465 | u32 magic, val; | |
10466 | ||
10467 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || | |
10468 | tg3_nvram_read(tp, 0, &magic)) | |
10469 | return NULL; | |
10470 | ||
10471 | if (magic == TG3_EEPROM_MAGIC) { | |
10472 | for (offset = TG3_NVM_DIR_START; | |
10473 | offset < TG3_NVM_DIR_END; | |
10474 | offset += TG3_NVM_DIRENT_SIZE) { | |
10475 | if (tg3_nvram_read(tp, offset, &val)) | |
10476 | return NULL; | |
10477 | ||
10478 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == | |
10479 | TG3_NVM_DIRTYPE_EXTVPD) | |
10480 | break; | |
10481 | } | |
10482 | ||
10483 | if (offset != TG3_NVM_DIR_END) { | |
10484 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; | |
10485 | if (tg3_nvram_read(tp, offset + 4, &offset)) | |
10486 | return NULL; | |
10487 | ||
10488 | offset = tg3_nvram_logical_addr(tp, offset); | |
10489 | } | |
10490 | } | |
10491 | ||
10492 | if (!offset || !len) { | |
10493 | offset = TG3_NVM_VPD_OFF; | |
10494 | len = TG3_NVM_VPD_LEN; | |
10495 | } | |
10496 | ||
10497 | buf = kmalloc(len, GFP_KERNEL); | |
10498 | if (buf == NULL) | |
10499 | return NULL; | |
10500 | ||
10501 | if (magic == TG3_EEPROM_MAGIC) { | |
10502 | for (i = 0; i < len; i += 4) { | |
10503 | /* The data is in little-endian format in NVRAM. | |
10504 | * Use the big-endian read routines to preserve | |
10505 | * the byte order as it exists in NVRAM. | |
10506 | */ | |
10507 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) | |
10508 | goto error; | |
10509 | } | |
10510 | } else { | |
10511 | u8 *ptr; | |
10512 | ssize_t cnt; | |
10513 | unsigned int pos = 0; | |
10514 | ||
10515 | ptr = (u8 *)&buf[0]; | |
10516 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { | |
10517 | cnt = pci_read_vpd(tp->pdev, pos, | |
10518 | len - pos, ptr); | |
10519 | if (cnt == -ETIMEDOUT || cnt == -EINTR) | |
10520 | cnt = 0; | |
10521 | else if (cnt < 0) | |
10522 | goto error; | |
10523 | } | |
10524 | if (pos != len) | |
10525 | goto error; | |
10526 | } | |
10527 | ||
10528 | return buf; | |
10529 | ||
10530 | error: | |
10531 | kfree(buf); | |
10532 | return NULL; | |
10533 | } | |
10534 | ||
566f86ad | 10535 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10536 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10537 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10538 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
b16250e3 MC |
10539 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10540 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10541 | |
10542 | static int tg3_test_nvram(struct tg3 *tp) | |
10543 | { | |
b9fc7dc5 | 10544 | u32 csum, magic; |
a9dc529d | 10545 | __be32 *buf; |
ab0049b4 | 10546 | int i, j, k, err = 0, size; |
566f86ad | 10547 | |
df259d8c MC |
10548 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
10549 | return 0; | |
10550 | ||
e4f34110 | 10551 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10552 | return -EIO; |
10553 | ||
1b27777a MC |
10554 | if (magic == TG3_EEPROM_MAGIC) |
10555 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10556 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10557 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10558 | TG3_EEPROM_SB_FORMAT_1) { | |
10559 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10560 | case TG3_EEPROM_SB_REVISION_0: | |
10561 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10562 | break; | |
10563 | case TG3_EEPROM_SB_REVISION_2: | |
10564 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10565 | break; | |
10566 | case TG3_EEPROM_SB_REVISION_3: | |
10567 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10568 | break; | |
10569 | default: | |
10570 | return 0; | |
10571 | } | |
10572 | } else | |
1b27777a | 10573 | return 0; |
b16250e3 MC |
10574 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10575 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10576 | else | |
1b27777a MC |
10577 | return -EIO; |
10578 | ||
10579 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10580 | if (buf == NULL) |
10581 | return -ENOMEM; | |
10582 | ||
1b27777a MC |
10583 | err = -EIO; |
10584 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10585 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10586 | if (err) | |
566f86ad | 10587 | break; |
566f86ad | 10588 | } |
1b27777a | 10589 | if (i < size) |
566f86ad MC |
10590 | goto out; |
10591 | ||
1b27777a | 10592 | /* Selfboot format */ |
a9dc529d | 10593 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10594 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10595 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10596 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10597 | ||
b9fc7dc5 | 10598 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10599 | TG3_EEPROM_SB_REVISION_2) { |
10600 | /* For rev 2, the csum doesn't include the MBA. */ | |
10601 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10602 | csum8 += buf8[i]; | |
10603 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10604 | csum8 += buf8[i]; | |
10605 | } else { | |
10606 | for (i = 0; i < size; i++) | |
10607 | csum8 += buf8[i]; | |
10608 | } | |
1b27777a | 10609 | |
ad96b485 AB |
10610 | if (csum8 == 0) { |
10611 | err = 0; | |
10612 | goto out; | |
10613 | } | |
10614 | ||
10615 | err = -EIO; | |
10616 | goto out; | |
1b27777a | 10617 | } |
566f86ad | 10618 | |
b9fc7dc5 | 10619 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10620 | TG3_EEPROM_MAGIC_HW) { |
10621 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10622 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10623 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10624 | |
10625 | /* Separate the parity bits and the data bytes. */ | |
10626 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10627 | if ((i == 0) || (i == 8)) { | |
10628 | int l; | |
10629 | u8 msk; | |
10630 | ||
10631 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10632 | parity[k++] = buf8[i] & msk; | |
10633 | i++; | |
859a5887 | 10634 | } else if (i == 16) { |
b16250e3 MC |
10635 | int l; |
10636 | u8 msk; | |
10637 | ||
10638 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10639 | parity[k++] = buf8[i] & msk; | |
10640 | i++; | |
10641 | ||
10642 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10643 | parity[k++] = buf8[i] & msk; | |
10644 | i++; | |
10645 | } | |
10646 | data[j++] = buf8[i]; | |
10647 | } | |
10648 | ||
10649 | err = -EIO; | |
10650 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10651 | u8 hw8 = hweight8(data[i]); | |
10652 | ||
10653 | if ((hw8 & 0x1) && parity[i]) | |
10654 | goto out; | |
10655 | else if (!(hw8 & 0x1) && !parity[i]) | |
10656 | goto out; | |
10657 | } | |
10658 | err = 0; | |
10659 | goto out; | |
10660 | } | |
10661 | ||
01c3a392 MC |
10662 | err = -EIO; |
10663 | ||
566f86ad MC |
10664 | /* Bootstrap checksum at offset 0x10 */ |
10665 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 10666 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
10667 | goto out; |
10668 | ||
10669 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10670 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 10671 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 10672 | goto out; |
566f86ad | 10673 | |
c3e94500 MC |
10674 | kfree(buf); |
10675 | ||
10676 | buf = tg3_vpd_readblock(tp); | |
10677 | if (!buf) | |
10678 | return -ENOMEM; | |
d4894f3e MC |
10679 | |
10680 | i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN, | |
10681 | PCI_VPD_LRDT_RO_DATA); | |
10682 | if (i > 0) { | |
10683 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
10684 | if (j < 0) | |
10685 | goto out; | |
10686 | ||
10687 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN) | |
10688 | goto out; | |
10689 | ||
10690 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10691 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
10692 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
10693 | if (j > 0) { | |
10694 | u8 csum8 = 0; | |
10695 | ||
10696 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10697 | ||
10698 | for (i = 0; i <= j; i++) | |
10699 | csum8 += ((u8 *)buf)[i]; | |
10700 | ||
10701 | if (csum8) | |
10702 | goto out; | |
10703 | } | |
10704 | } | |
10705 | ||
566f86ad MC |
10706 | err = 0; |
10707 | ||
10708 | out: | |
10709 | kfree(buf); | |
10710 | return err; | |
10711 | } | |
10712 | ||
ca43007a MC |
10713 | #define TG3_SERDES_TIMEOUT_SEC 2 |
10714 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10715 | ||
10716 | static int tg3_test_link(struct tg3 *tp) | |
10717 | { | |
10718 | int i, max; | |
10719 | ||
10720 | if (!netif_running(tp->dev)) | |
10721 | return -ENODEV; | |
10722 | ||
f07e9af3 | 10723 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
10724 | max = TG3_SERDES_TIMEOUT_SEC; |
10725 | else | |
10726 | max = TG3_COPPER_TIMEOUT_SEC; | |
10727 | ||
10728 | for (i = 0; i < max; i++) { | |
10729 | if (netif_carrier_ok(tp->dev)) | |
10730 | return 0; | |
10731 | ||
10732 | if (msleep_interruptible(1000)) | |
10733 | break; | |
10734 | } | |
10735 | ||
10736 | return -EIO; | |
10737 | } | |
10738 | ||
a71116d1 | 10739 | /* Only test the commonly used registers */ |
30ca3e37 | 10740 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 10741 | { |
b16250e3 | 10742 | int i, is_5705, is_5750; |
a71116d1 MC |
10743 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
10744 | static struct { | |
10745 | u16 offset; | |
10746 | u16 flags; | |
10747 | #define TG3_FL_5705 0x1 | |
10748 | #define TG3_FL_NOT_5705 0x2 | |
10749 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 10750 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
10751 | u32 read_mask; |
10752 | u32 write_mask; | |
10753 | } reg_tbl[] = { | |
10754 | /* MAC Control Registers */ | |
10755 | { MAC_MODE, TG3_FL_NOT_5705, | |
10756 | 0x00000000, 0x00ef6f8c }, | |
10757 | { MAC_MODE, TG3_FL_5705, | |
10758 | 0x00000000, 0x01ef6b8c }, | |
10759 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10760 | 0x03800107, 0x00000000 }, | |
10761 | { MAC_STATUS, TG3_FL_5705, | |
10762 | 0x03800100, 0x00000000 }, | |
10763 | { MAC_ADDR_0_HIGH, 0x0000, | |
10764 | 0x00000000, 0x0000ffff }, | |
10765 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 10766 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
10767 | { MAC_RX_MTU_SIZE, 0x0000, |
10768 | 0x00000000, 0x0000ffff }, | |
10769 | { MAC_TX_MODE, 0x0000, | |
10770 | 0x00000000, 0x00000070 }, | |
10771 | { MAC_TX_LENGTHS, 0x0000, | |
10772 | 0x00000000, 0x00003fff }, | |
10773 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10774 | 0x00000000, 0x000007fc }, | |
10775 | { MAC_RX_MODE, TG3_FL_5705, | |
10776 | 0x00000000, 0x000007dc }, | |
10777 | { MAC_HASH_REG_0, 0x0000, | |
10778 | 0x00000000, 0xffffffff }, | |
10779 | { MAC_HASH_REG_1, 0x0000, | |
10780 | 0x00000000, 0xffffffff }, | |
10781 | { MAC_HASH_REG_2, 0x0000, | |
10782 | 0x00000000, 0xffffffff }, | |
10783 | { MAC_HASH_REG_3, 0x0000, | |
10784 | 0x00000000, 0xffffffff }, | |
10785 | ||
10786 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10787 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10788 | 0x00000000, 0xffffffff }, | |
10789 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10790 | 0x00000000, 0xffffffff }, | |
10791 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10792 | 0x00000000, 0x00000003 }, | |
10793 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10794 | 0x00000000, 0xffffffff }, | |
10795 | { RCVDBDI_STD_BD+0, 0x0000, | |
10796 | 0x00000000, 0xffffffff }, | |
10797 | { RCVDBDI_STD_BD+4, 0x0000, | |
10798 | 0x00000000, 0xffffffff }, | |
10799 | { RCVDBDI_STD_BD+8, 0x0000, | |
10800 | 0x00000000, 0xffff0002 }, | |
10801 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10802 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10803 | |
a71116d1 MC |
10804 | /* Receive BD Initiator Control Registers. */ |
10805 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10806 | 0x00000000, 0xffffffff }, | |
10807 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10808 | 0x00000000, 0x000003ff }, | |
10809 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10810 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10811 | |
a71116d1 MC |
10812 | /* Host Coalescing Control Registers. */ |
10813 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10814 | 0x00000000, 0x00000004 }, | |
10815 | { HOSTCC_MODE, TG3_FL_5705, | |
10816 | 0x00000000, 0x000000f6 }, | |
10817 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10818 | 0x00000000, 0xffffffff }, | |
10819 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10820 | 0x00000000, 0x000003ff }, | |
10821 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10822 | 0x00000000, 0xffffffff }, | |
10823 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10824 | 0x00000000, 0x000003ff }, | |
10825 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10826 | 0x00000000, 0xffffffff }, | |
10827 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10828 | 0x00000000, 0x000000ff }, | |
10829 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10830 | 0x00000000, 0xffffffff }, | |
10831 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10832 | 0x00000000, 0x000000ff }, | |
10833 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10834 | 0x00000000, 0xffffffff }, | |
10835 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10836 | 0x00000000, 0xffffffff }, | |
10837 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10838 | 0x00000000, 0xffffffff }, | |
10839 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10840 | 0x00000000, 0x000000ff }, | |
10841 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10842 | 0x00000000, 0xffffffff }, | |
10843 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10844 | 0x00000000, 0x000000ff }, | |
10845 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10846 | 0x00000000, 0xffffffff }, | |
10847 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10848 | 0x00000000, 0xffffffff }, | |
10849 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10850 | 0x00000000, 0xffffffff }, | |
10851 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10852 | 0x00000000, 0xffffffff }, | |
10853 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10854 | 0x00000000, 0xffffffff }, | |
10855 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10856 | 0xffffffff, 0x00000000 }, | |
10857 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10858 | 0xffffffff, 0x00000000 }, | |
10859 | ||
10860 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 10861 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 10862 | 0x00000000, 0x007fff80 }, |
b16250e3 | 10863 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
10864 | 0x00000000, 0x007fffff }, |
10865 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10866 | 0x00000000, 0x0000003f }, | |
10867 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10868 | 0x00000000, 0x000001ff }, | |
10869 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10870 | 0x00000000, 0x000001ff }, | |
10871 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10872 | 0xffffffff, 0x00000000 }, | |
10873 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10874 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 10875 | |
a71116d1 MC |
10876 | /* Mailbox Registers */ |
10877 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10878 | 0x00000000, 0x000001ff }, | |
10879 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10880 | 0x00000000, 0x000001ff }, | |
10881 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10882 | 0x00000000, 0x000007ff }, | |
10883 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10884 | 0x00000000, 0x000001ff }, | |
10885 | ||
10886 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10887 | }; | |
10888 | ||
b16250e3 MC |
10889 | is_5705 = is_5750 = 0; |
10890 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
a71116d1 | 10891 | is_5705 = 1; |
b16250e3 MC |
10892 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
10893 | is_5750 = 1; | |
10894 | } | |
a71116d1 MC |
10895 | |
10896 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10897 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
10898 | continue; | |
10899 | ||
10900 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
10901 | continue; | |
10902 | ||
10903 | if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
10904 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
10905 | continue; | |
10906 | ||
b16250e3 MC |
10907 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
10908 | continue; | |
10909 | ||
a71116d1 MC |
10910 | offset = (u32) reg_tbl[i].offset; |
10911 | read_mask = reg_tbl[i].read_mask; | |
10912 | write_mask = reg_tbl[i].write_mask; | |
10913 | ||
10914 | /* Save the original register content */ | |
10915 | save_val = tr32(offset); | |
10916 | ||
10917 | /* Determine the read-only value. */ | |
10918 | read_val = save_val & read_mask; | |
10919 | ||
10920 | /* Write zero to the register, then make sure the read-only bits | |
10921 | * are not changed and the read/write bits are all zeros. | |
10922 | */ | |
10923 | tw32(offset, 0); | |
10924 | ||
10925 | val = tr32(offset); | |
10926 | ||
10927 | /* Test the read-only and read/write bits. */ | |
10928 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
10929 | goto out; | |
10930 | ||
10931 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
10932 | * make sure the read-only bits are not changed and the | |
10933 | * read/write bits are all ones. | |
10934 | */ | |
10935 | tw32(offset, read_mask | write_mask); | |
10936 | ||
10937 | val = tr32(offset); | |
10938 | ||
10939 | /* Test the read-only bits. */ | |
10940 | if ((val & read_mask) != read_val) | |
10941 | goto out; | |
10942 | ||
10943 | /* Test the read/write bits. */ | |
10944 | if ((val & write_mask) != write_mask) | |
10945 | goto out; | |
10946 | ||
10947 | tw32(offset, save_val); | |
10948 | } | |
10949 | ||
10950 | return 0; | |
10951 | ||
10952 | out: | |
9f88f29f | 10953 | if (netif_msg_hw(tp)) |
2445e461 MC |
10954 | netdev_err(tp->dev, |
10955 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
10956 | tw32(offset, save_val); |
10957 | return -EIO; | |
10958 | } | |
10959 | ||
7942e1db MC |
10960 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
10961 | { | |
f71e1309 | 10962 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
10963 | int i; |
10964 | u32 j; | |
10965 | ||
e9edda69 | 10966 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
10967 | for (j = 0; j < len; j += 4) { |
10968 | u32 val; | |
10969 | ||
10970 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
10971 | tg3_read_mem(tp, offset + j, &val); | |
10972 | if (val != test_pattern[i]) | |
10973 | return -EIO; | |
10974 | } | |
10975 | } | |
10976 | return 0; | |
10977 | } | |
10978 | ||
10979 | static int tg3_test_memory(struct tg3 *tp) | |
10980 | { | |
10981 | static struct mem_entry { | |
10982 | u32 offset; | |
10983 | u32 len; | |
10984 | } mem_tbl_570x[] = { | |
38690194 | 10985 | { 0x00000000, 0x00b50}, |
7942e1db MC |
10986 | { 0x00002000, 0x1c000}, |
10987 | { 0xffffffff, 0x00000} | |
10988 | }, mem_tbl_5705[] = { | |
10989 | { 0x00000100, 0x0000c}, | |
10990 | { 0x00000200, 0x00008}, | |
7942e1db MC |
10991 | { 0x00004000, 0x00800}, |
10992 | { 0x00006000, 0x01000}, | |
10993 | { 0x00008000, 0x02000}, | |
10994 | { 0x00010000, 0x0e000}, | |
10995 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
10996 | }, mem_tbl_5755[] = { |
10997 | { 0x00000200, 0x00008}, | |
10998 | { 0x00004000, 0x00800}, | |
10999 | { 0x00006000, 0x00800}, | |
11000 | { 0x00008000, 0x02000}, | |
11001 | { 0x00010000, 0x0c000}, | |
11002 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
11003 | }, mem_tbl_5906[] = { |
11004 | { 0x00000200, 0x00008}, | |
11005 | { 0x00004000, 0x00400}, | |
11006 | { 0x00006000, 0x00400}, | |
11007 | { 0x00008000, 0x01000}, | |
11008 | { 0x00010000, 0x01000}, | |
11009 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
11010 | }, mem_tbl_5717[] = { |
11011 | { 0x00000200, 0x00008}, | |
11012 | { 0x00010000, 0x0a000}, | |
11013 | { 0x00020000, 0x13c00}, | |
11014 | { 0xffffffff, 0x00000} | |
11015 | }, mem_tbl_57765[] = { | |
11016 | { 0x00000200, 0x00008}, | |
11017 | { 0x00004000, 0x00800}, | |
11018 | { 0x00006000, 0x09800}, | |
11019 | { 0x00010000, 0x0a000}, | |
11020 | { 0xffffffff, 0x00000} | |
7942e1db MC |
11021 | }; |
11022 | struct mem_entry *mem_tbl; | |
11023 | int err = 0; | |
11024 | int i; | |
11025 | ||
0a58d668 | 11026 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
8b5a6c42 MC |
11027 | mem_tbl = mem_tbl_5717; |
11028 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
11029 | mem_tbl = mem_tbl_57765; | |
11030 | else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
321d32a0 MC |
11031 | mem_tbl = mem_tbl_5755; |
11032 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
11033 | mem_tbl = mem_tbl_5906; | |
11034 | else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
11035 | mem_tbl = mem_tbl_5705; | |
11036 | else | |
7942e1db MC |
11037 | mem_tbl = mem_tbl_570x; |
11038 | ||
11039 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
11040 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
11041 | if (err) | |
7942e1db MC |
11042 | break; |
11043 | } | |
6aa20a22 | 11044 | |
7942e1db MC |
11045 | return err; |
11046 | } | |
11047 | ||
9f40dead MC |
11048 | #define TG3_MAC_LOOPBACK 0 |
11049 | #define TG3_PHY_LOOPBACK 1 | |
11050 | ||
4852a861 | 11051 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode) |
c76949a6 | 11052 | { |
9f40dead | 11053 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
fd2ce37f | 11054 | u32 desc_idx, coal_now; |
c76949a6 MC |
11055 | struct sk_buff *skb, *rx_skb; |
11056 | u8 *tx_data; | |
11057 | dma_addr_t map; | |
11058 | int num_pkts, tx_len, rx_len, i, err; | |
11059 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 11060 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 11061 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 11062 | |
c8873405 MC |
11063 | tnapi = &tp->napi[0]; |
11064 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 11065 | if (tp->irq_cnt > 1) { |
1da85aa3 MC |
11066 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
11067 | rnapi = &tp->napi[1]; | |
c8873405 MC |
11068 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
11069 | tnapi = &tp->napi[1]; | |
0c1d0e2b | 11070 | } |
fd2ce37f | 11071 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 11072 | |
9f40dead | 11073 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
c94e3941 MC |
11074 | /* HW errata - mac loopback fails in some cases on 5780. |
11075 | * Normal traffic and PHY loopback are not affected by | |
aba49f24 MC |
11076 | * errata. Also, the MAC loopback test is deprecated for |
11077 | * all newer ASIC revisions. | |
c94e3941 | 11078 | */ |
aba49f24 MC |
11079 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
11080 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) | |
c94e3941 MC |
11081 | return 0; |
11082 | ||
49692ca1 MC |
11083 | mac_mode = tp->mac_mode & |
11084 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
11085 | mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
e8f3f6ca MC |
11086 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
11087 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
f07e9af3 | 11088 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3f7045c1 MC |
11089 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
11090 | else | |
11091 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9f40dead MC |
11092 | tw32(MAC_MODE, mac_mode); |
11093 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | |
3f7045c1 MC |
11094 | u32 val; |
11095 | ||
f07e9af3 | 11096 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd | 11097 | tg3_phy_fet_toggle_apd(tp, false); |
5d64ad34 MC |
11098 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
11099 | } else | |
11100 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 11101 | |
9ef8ca99 MC |
11102 | tg3_phy_toggle_automdix(tp, 0); |
11103 | ||
3f7045c1 | 11104 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 11105 | udelay(40); |
5d64ad34 | 11106 | |
49692ca1 MC |
11107 | mac_mode = tp->mac_mode & |
11108 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
f07e9af3 | 11109 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
1061b7c5 MC |
11110 | tg3_writephy(tp, MII_TG3_FET_PTEST, |
11111 | MII_TG3_FET_PTEST_FRC_TX_LINK | | |
11112 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
11113 | /* The write needs to be flushed for the AC131 */ | |
11114 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
11115 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
5d64ad34 MC |
11116 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
11117 | } else | |
11118 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 11119 | |
c94e3941 | 11120 | /* reset to prevent losing 1st rx packet intermittently */ |
f07e9af3 | 11121 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
c94e3941 MC |
11122 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
11123 | udelay(10); | |
11124 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
11125 | } | |
e8f3f6ca | 11126 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
79eb6904 MC |
11127 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
11128 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
e8f3f6ca | 11129 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
79eb6904 | 11130 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) |
e8f3f6ca | 11131 | mac_mode |= MAC_MODE_LINK_POLARITY; |
ff18ff02 MC |
11132 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
11133 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
11134 | } | |
9f40dead | 11135 | tw32(MAC_MODE, mac_mode); |
49692ca1 MC |
11136 | |
11137 | /* Wait for link */ | |
11138 | for (i = 0; i < 100; i++) { | |
11139 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
11140 | break; | |
11141 | mdelay(1); | |
11142 | } | |
859a5887 | 11143 | } else { |
9f40dead | 11144 | return -EINVAL; |
859a5887 | 11145 | } |
c76949a6 MC |
11146 | |
11147 | err = -EIO; | |
11148 | ||
4852a861 | 11149 | tx_len = pktsz; |
a20e9c62 | 11150 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
11151 | if (!skb) |
11152 | return -ENOMEM; | |
11153 | ||
c76949a6 MC |
11154 | tx_data = skb_put(skb, tx_len); |
11155 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
11156 | memset(tx_data + 6, 0x0, 8); | |
11157 | ||
4852a861 | 11158 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
c76949a6 MC |
11159 | |
11160 | for (i = 14; i < tx_len; i++) | |
11161 | tx_data[i] = (u8) (i & 0xff); | |
11162 | ||
f4188d8a AD |
11163 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
11164 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
11165 | dev_kfree_skb(skb); |
11166 | return -EIO; | |
11167 | } | |
c76949a6 MC |
11168 | |
11169 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 11170 | rnapi->coal_now); |
c76949a6 MC |
11171 | |
11172 | udelay(10); | |
11173 | ||
898a56f8 | 11174 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 11175 | |
c76949a6 MC |
11176 | num_pkts = 0; |
11177 | ||
f4188d8a | 11178 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1); |
c76949a6 | 11179 | |
f3f3f27e | 11180 | tnapi->tx_prod++; |
c76949a6 MC |
11181 | num_pkts++; |
11182 | ||
f3f3f27e MC |
11183 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
11184 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
11185 | |
11186 | udelay(10); | |
11187 | ||
303fc921 MC |
11188 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
11189 | for (i = 0; i < 35; i++) { | |
c76949a6 | 11190 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11191 | coal_now); |
c76949a6 MC |
11192 | |
11193 | udelay(10); | |
11194 | ||
898a56f8 MC |
11195 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
11196 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 11197 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
11198 | (rx_idx == (rx_start_idx + num_pkts))) |
11199 | break; | |
11200 | } | |
11201 | ||
f4188d8a | 11202 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); |
c76949a6 MC |
11203 | dev_kfree_skb(skb); |
11204 | ||
f3f3f27e | 11205 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
11206 | goto out; |
11207 | ||
11208 | if (rx_idx != rx_start_idx + num_pkts) | |
11209 | goto out; | |
11210 | ||
72334482 | 11211 | desc = &rnapi->rx_rcb[rx_start_idx]; |
c76949a6 MC |
11212 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
11213 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
c76949a6 MC |
11214 | |
11215 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
11216 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11217 | goto out; | |
11218 | ||
11219 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; | |
11220 | if (rx_len != tx_len) | |
11221 | goto out; | |
11222 | ||
4852a861 MC |
11223 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
11224 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11225 | goto out; | |
11226 | ||
11227 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; | |
11228 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping); | |
11229 | } else { | |
11230 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) | |
11231 | goto out; | |
11232 | ||
11233 | rx_skb = tpr->rx_jmb_buffers[desc_idx].skb; | |
11234 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], mapping); | |
11235 | } | |
c76949a6 | 11236 | |
c76949a6 MC |
11237 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); |
11238 | ||
11239 | for (i = 14; i < tx_len; i++) { | |
11240 | if (*(rx_skb->data + i) != (u8) (i & 0xff)) | |
11241 | goto out; | |
11242 | } | |
11243 | err = 0; | |
6aa20a22 | 11244 | |
c76949a6 MC |
11245 | /* tg3_free_rings will unmap and free the rx_skb */ |
11246 | out: | |
11247 | return err; | |
11248 | } | |
11249 | ||
9f40dead MC |
11250 | #define TG3_MAC_LOOPBACK_FAILED 1 |
11251 | #define TG3_PHY_LOOPBACK_FAILED 2 | |
11252 | #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \ | |
11253 | TG3_PHY_LOOPBACK_FAILED) | |
11254 | ||
11255 | static int tg3_test_loopback(struct tg3 *tp) | |
11256 | { | |
11257 | int err = 0; | |
ab789046 | 11258 | u32 eee_cap, cpmuctrl = 0; |
9f40dead MC |
11259 | |
11260 | if (!netif_running(tp->dev)) | |
11261 | return TG3_LOOPBACK_FAILED; | |
11262 | ||
ab789046 MC |
11263 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
11264 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11265 | ||
b9ec6c1b | 11266 | err = tg3_reset_hw(tp, 1); |
ab789046 MC |
11267 | if (err) { |
11268 | err = TG3_LOOPBACK_FAILED; | |
11269 | goto done; | |
11270 | } | |
9f40dead | 11271 | |
4a85f098 MC |
11272 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { |
11273 | int i; | |
11274 | ||
11275 | /* Reroute all rx packets to the 1st queue */ | |
11276 | for (i = MAC_RSS_INDIR_TBL_0; | |
11277 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) | |
11278 | tw32(i, 0x0); | |
11279 | } | |
11280 | ||
6833c043 | 11281 | /* Turn off gphy autopowerdown. */ |
f07e9af3 | 11282 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11283 | tg3_phy_toggle_apd(tp, false); |
11284 | ||
321d32a0 | 11285 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
11286 | int i; |
11287 | u32 status; | |
11288 | ||
11289 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
11290 | ||
11291 | /* Wait for up to 40 microseconds to acquire lock. */ | |
11292 | for (i = 0; i < 4; i++) { | |
11293 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
11294 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
11295 | break; | |
11296 | udelay(10); | |
11297 | } | |
11298 | ||
ab789046 MC |
11299 | if (status != CPMU_MUTEX_GNT_DRIVER) { |
11300 | err = TG3_LOOPBACK_FAILED; | |
11301 | goto done; | |
11302 | } | |
9936bcf6 | 11303 | |
b2a5c19c | 11304 | /* Turn off link-based power management. */ |
e875093c | 11305 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
109115e1 MC |
11306 | tw32(TG3_CPMU_CTRL, |
11307 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
11308 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9936bcf6 MC |
11309 | } |
11310 | ||
4852a861 | 11311 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK)) |
9f40dead | 11312 | err |= TG3_MAC_LOOPBACK_FAILED; |
9936bcf6 | 11313 | |
4852a861 MC |
11314 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) && |
11315 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK)) | |
11316 | err |= (TG3_MAC_LOOPBACK_FAILED << 2); | |
11317 | ||
321d32a0 | 11318 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
11319 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
11320 | ||
11321 | /* Release the mutex */ | |
11322 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
11323 | } | |
11324 | ||
f07e9af3 | 11325 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
dd477003 | 11326 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
4852a861 | 11327 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK)) |
9f40dead | 11328 | err |= TG3_PHY_LOOPBACK_FAILED; |
4852a861 MC |
11329 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) && |
11330 | tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK)) | |
11331 | err |= (TG3_PHY_LOOPBACK_FAILED << 2); | |
9f40dead MC |
11332 | } |
11333 | ||
6833c043 | 11334 | /* Re-enable gphy autopowerdown. */ |
f07e9af3 | 11335 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11336 | tg3_phy_toggle_apd(tp, true); |
11337 | ||
ab789046 MC |
11338 | done: |
11339 | tp->phy_flags |= eee_cap; | |
11340 | ||
9f40dead MC |
11341 | return err; |
11342 | } | |
11343 | ||
4cafd3f5 MC |
11344 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
11345 | u64 *data) | |
11346 | { | |
566f86ad MC |
11347 | struct tg3 *tp = netdev_priv(dev); |
11348 | ||
80096068 | 11349 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11350 | tg3_power_up(tp); |
bc1c7567 | 11351 | |
566f86ad MC |
11352 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
11353 | ||
11354 | if (tg3_test_nvram(tp) != 0) { | |
11355 | etest->flags |= ETH_TEST_FL_FAILED; | |
11356 | data[0] = 1; | |
11357 | } | |
ca43007a MC |
11358 | if (tg3_test_link(tp) != 0) { |
11359 | etest->flags |= ETH_TEST_FL_FAILED; | |
11360 | data[1] = 1; | |
11361 | } | |
a71116d1 | 11362 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 11363 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
11364 | |
11365 | if (netif_running(dev)) { | |
b02fd9e3 | 11366 | tg3_phy_stop(tp); |
a71116d1 | 11367 | tg3_netif_stop(tp); |
bbe832c0 MC |
11368 | irq_sync = 1; |
11369 | } | |
a71116d1 | 11370 | |
bbe832c0 | 11371 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
11372 | |
11373 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 11374 | err = tg3_nvram_lock(tp); |
a71116d1 MC |
11375 | tg3_halt_cpu(tp, RX_CPU_BASE); |
11376 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
11377 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
ec41c7df MC |
11378 | if (!err) |
11379 | tg3_nvram_unlock(tp); | |
a71116d1 | 11380 | |
f07e9af3 | 11381 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
11382 | tg3_phy_reset(tp); |
11383 | ||
a71116d1 MC |
11384 | if (tg3_test_registers(tp) != 0) { |
11385 | etest->flags |= ETH_TEST_FL_FAILED; | |
11386 | data[2] = 1; | |
11387 | } | |
7942e1db MC |
11388 | if (tg3_test_memory(tp) != 0) { |
11389 | etest->flags |= ETH_TEST_FL_FAILED; | |
11390 | data[3] = 1; | |
11391 | } | |
9f40dead | 11392 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 11393 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 11394 | |
f47c11ee DM |
11395 | tg3_full_unlock(tp); |
11396 | ||
d4bc3927 MC |
11397 | if (tg3_test_interrupt(tp) != 0) { |
11398 | etest->flags |= ETH_TEST_FL_FAILED; | |
11399 | data[5] = 1; | |
11400 | } | |
f47c11ee DM |
11401 | |
11402 | tg3_full_lock(tp, 0); | |
d4bc3927 | 11403 | |
a71116d1 MC |
11404 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11405 | if (netif_running(dev)) { | |
11406 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
b02fd9e3 MC |
11407 | err2 = tg3_restart_hw(tp, 1); |
11408 | if (!err2) | |
b9ec6c1b | 11409 | tg3_netif_start(tp); |
a71116d1 | 11410 | } |
f47c11ee DM |
11411 | |
11412 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
11413 | |
11414 | if (irq_sync && !err2) | |
11415 | tg3_phy_start(tp); | |
a71116d1 | 11416 | } |
80096068 | 11417 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11418 | tg3_power_down(tp); |
bc1c7567 | 11419 | |
4cafd3f5 MC |
11420 | } |
11421 | ||
1da177e4 LT |
11422 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
11423 | { | |
11424 | struct mii_ioctl_data *data = if_mii(ifr); | |
11425 | struct tg3 *tp = netdev_priv(dev); | |
11426 | int err; | |
11427 | ||
b02fd9e3 | 11428 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 11429 | struct phy_device *phydev; |
f07e9af3 | 11430 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11431 | return -EAGAIN; |
3f0e3ad7 | 11432 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 11433 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
11434 | } |
11435 | ||
33f401ae | 11436 | switch (cmd) { |
1da177e4 | 11437 | case SIOCGMIIPHY: |
882e9793 | 11438 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
11439 | |
11440 | /* fallthru */ | |
11441 | case SIOCGMIIREG: { | |
11442 | u32 mii_regval; | |
11443 | ||
f07e9af3 | 11444 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11445 | break; /* We have no PHY */ |
11446 | ||
f746a313 MC |
11447 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) || |
11448 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
11449 | !netif_running(dev))) | |
bc1c7567 MC |
11450 | return -EAGAIN; |
11451 | ||
f47c11ee | 11452 | spin_lock_bh(&tp->lock); |
1da177e4 | 11453 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 11454 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11455 | |
11456 | data->val_out = mii_regval; | |
11457 | ||
11458 | return err; | |
11459 | } | |
11460 | ||
11461 | case SIOCSMIIREG: | |
f07e9af3 | 11462 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11463 | break; /* We have no PHY */ |
11464 | ||
f746a313 MC |
11465 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) || |
11466 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
11467 | !netif_running(dev))) | |
bc1c7567 MC |
11468 | return -EAGAIN; |
11469 | ||
f47c11ee | 11470 | spin_lock_bh(&tp->lock); |
1da177e4 | 11471 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 11472 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11473 | |
11474 | return err; | |
11475 | ||
11476 | default: | |
11477 | /* do nothing */ | |
11478 | break; | |
11479 | } | |
11480 | return -EOPNOTSUPP; | |
11481 | } | |
11482 | ||
15f9850d DM |
11483 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11484 | { | |
11485 | struct tg3 *tp = netdev_priv(dev); | |
11486 | ||
11487 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11488 | return 0; | |
11489 | } | |
11490 | ||
d244c892 MC |
11491 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11492 | { | |
11493 | struct tg3 *tp = netdev_priv(dev); | |
11494 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11495 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11496 | ||
11497 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
11498 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
11499 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11500 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11501 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11502 | } | |
11503 | ||
11504 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11505 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11506 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11507 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11508 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11509 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11510 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11511 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11512 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11513 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11514 | return -EINVAL; | |
11515 | ||
11516 | /* No rx interrupts will be generated if both are zero */ | |
11517 | if ((ec->rx_coalesce_usecs == 0) && | |
11518 | (ec->rx_max_coalesced_frames == 0)) | |
11519 | return -EINVAL; | |
11520 | ||
11521 | /* No tx interrupts will be generated if both are zero */ | |
11522 | if ((ec->tx_coalesce_usecs == 0) && | |
11523 | (ec->tx_max_coalesced_frames == 0)) | |
11524 | return -EINVAL; | |
11525 | ||
11526 | /* Only copy relevant parameters, ignore all others. */ | |
11527 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11528 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11529 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11530 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11531 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11532 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11533 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11534 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11535 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11536 | ||
11537 | if (netif_running(dev)) { | |
11538 | tg3_full_lock(tp, 0); | |
11539 | __tg3_set_coalesce(tp, &tp->coal); | |
11540 | tg3_full_unlock(tp); | |
11541 | } | |
11542 | return 0; | |
11543 | } | |
11544 | ||
7282d491 | 11545 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11546 | .get_settings = tg3_get_settings, |
11547 | .set_settings = tg3_set_settings, | |
11548 | .get_drvinfo = tg3_get_drvinfo, | |
11549 | .get_regs_len = tg3_get_regs_len, | |
11550 | .get_regs = tg3_get_regs, | |
11551 | .get_wol = tg3_get_wol, | |
11552 | .set_wol = tg3_set_wol, | |
11553 | .get_msglevel = tg3_get_msglevel, | |
11554 | .set_msglevel = tg3_set_msglevel, | |
11555 | .nway_reset = tg3_nway_reset, | |
11556 | .get_link = ethtool_op_get_link, | |
11557 | .get_eeprom_len = tg3_get_eeprom_len, | |
11558 | .get_eeprom = tg3_get_eeprom, | |
11559 | .set_eeprom = tg3_set_eeprom, | |
11560 | .get_ringparam = tg3_get_ringparam, | |
11561 | .set_ringparam = tg3_set_ringparam, | |
11562 | .get_pauseparam = tg3_get_pauseparam, | |
11563 | .set_pauseparam = tg3_set_pauseparam, | |
4cafd3f5 | 11564 | .self_test = tg3_self_test, |
1da177e4 | 11565 | .get_strings = tg3_get_strings, |
81b8709c | 11566 | .set_phys_id = tg3_set_phys_id, |
1da177e4 | 11567 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11568 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11569 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11570 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11571 | }; |
11572 | ||
11573 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11574 | { | |
1b27777a | 11575 | u32 cursize, val, magic; |
1da177e4 LT |
11576 | |
11577 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11578 | ||
e4f34110 | 11579 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11580 | return; |
11581 | ||
b16250e3 MC |
11582 | if ((magic != TG3_EEPROM_MAGIC) && |
11583 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11584 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11585 | return; |
11586 | ||
11587 | /* | |
11588 | * Size the chip by reading offsets at increasing powers of two. | |
11589 | * When we encounter our validation signature, we know the addressing | |
11590 | * has wrapped around, and thus have our chip size. | |
11591 | */ | |
1b27777a | 11592 | cursize = 0x10; |
1da177e4 LT |
11593 | |
11594 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11595 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11596 | return; |
11597 | ||
1820180b | 11598 | if (val == magic) |
1da177e4 LT |
11599 | break; |
11600 | ||
11601 | cursize <<= 1; | |
11602 | } | |
11603 | ||
11604 | tp->nvram_size = cursize; | |
11605 | } | |
6aa20a22 | 11606 | |
1da177e4 LT |
11607 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11608 | { | |
11609 | u32 val; | |
11610 | ||
df259d8c MC |
11611 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
11612 | tg3_nvram_read(tp, 0, &val) != 0) | |
1b27777a MC |
11613 | return; |
11614 | ||
11615 | /* Selfboot format */ | |
1820180b | 11616 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11617 | tg3_get_eeprom_size(tp); |
11618 | return; | |
11619 | } | |
11620 | ||
6d348f2c | 11621 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 11622 | if (val != 0) { |
6d348f2c MC |
11623 | /* This is confusing. We want to operate on the |
11624 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11625 | * call will read from NVRAM and byteswap the data | |
11626 | * according to the byteswapping settings for all | |
11627 | * other register accesses. This ensures the data we | |
11628 | * want will always reside in the lower 16-bits. | |
11629 | * However, the data in NVRAM is in LE format, which | |
11630 | * means the data from the NVRAM read will always be | |
11631 | * opposite the endianness of the CPU. The 16-bit | |
11632 | * byteswap then brings the data to CPU endianness. | |
11633 | */ | |
11634 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
11635 | return; |
11636 | } | |
11637 | } | |
fd1122a2 | 11638 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
11639 | } |
11640 | ||
11641 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11642 | { | |
11643 | u32 nvcfg1; | |
11644 | ||
11645 | nvcfg1 = tr32(NVRAM_CFG1); | |
11646 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
11647 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
8590a603 | 11648 | } else { |
1da177e4 LT |
11649 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11650 | tw32(NVRAM_CFG1, nvcfg1); | |
11651 | } | |
11652 | ||
4c987487 | 11653 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || |
a4e2b347 | 11654 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 | 11655 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
11656 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
11657 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11658 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11659 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11660 | break; | |
11661 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11662 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11663 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11664 | break; | |
11665 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11666 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11667 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11668 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11669 | break; | |
11670 | case FLASH_VENDOR_ST: | |
11671 | tp->nvram_jedecnum = JEDEC_ST; | |
11672 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
11673 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11674 | break; | |
11675 | case FLASH_VENDOR_SAIFUN: | |
11676 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11677 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11678 | break; | |
11679 | case FLASH_VENDOR_SST_SMALL: | |
11680 | case FLASH_VENDOR_SST_LARGE: | |
11681 | tp->nvram_jedecnum = JEDEC_SST; | |
11682 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11683 | break; | |
1da177e4 | 11684 | } |
8590a603 | 11685 | } else { |
1da177e4 LT |
11686 | tp->nvram_jedecnum = JEDEC_ATMEL; |
11687 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11688 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11689 | } | |
11690 | } | |
11691 | ||
a1b950d5 MC |
11692 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
11693 | { | |
11694 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11695 | case FLASH_5752PAGE_SIZE_256: | |
11696 | tp->nvram_pagesize = 256; | |
11697 | break; | |
11698 | case FLASH_5752PAGE_SIZE_512: | |
11699 | tp->nvram_pagesize = 512; | |
11700 | break; | |
11701 | case FLASH_5752PAGE_SIZE_1K: | |
11702 | tp->nvram_pagesize = 1024; | |
11703 | break; | |
11704 | case FLASH_5752PAGE_SIZE_2K: | |
11705 | tp->nvram_pagesize = 2048; | |
11706 | break; | |
11707 | case FLASH_5752PAGE_SIZE_4K: | |
11708 | tp->nvram_pagesize = 4096; | |
11709 | break; | |
11710 | case FLASH_5752PAGE_SIZE_264: | |
11711 | tp->nvram_pagesize = 264; | |
11712 | break; | |
11713 | case FLASH_5752PAGE_SIZE_528: | |
11714 | tp->nvram_pagesize = 528; | |
11715 | break; | |
11716 | } | |
11717 | } | |
11718 | ||
361b4ac2 MC |
11719 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
11720 | { | |
11721 | u32 nvcfg1; | |
11722 | ||
11723 | nvcfg1 = tr32(NVRAM_CFG1); | |
11724 | ||
e6af301b MC |
11725 | /* NVRAM protection for TPM */ |
11726 | if (nvcfg1 & (1 << 27)) | |
f66a29b0 | 11727 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
e6af301b | 11728 | |
361b4ac2 | 11729 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
11730 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
11731 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11732 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11733 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11734 | break; | |
11735 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11736 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11737 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11738 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11739 | break; | |
11740 | case FLASH_5752VENDOR_ST_M45PE10: | |
11741 | case FLASH_5752VENDOR_ST_M45PE20: | |
11742 | case FLASH_5752VENDOR_ST_M45PE40: | |
11743 | tp->nvram_jedecnum = JEDEC_ST; | |
11744 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11745 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11746 | break; | |
361b4ac2 MC |
11747 | } |
11748 | ||
11749 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | |
a1b950d5 | 11750 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 11751 | } else { |
361b4ac2 MC |
11752 | /* For eeprom, set pagesize to maximum eeprom size */ |
11753 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11754 | ||
11755 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11756 | tw32(NVRAM_CFG1, nvcfg1); | |
11757 | } | |
11758 | } | |
11759 | ||
d3c7b886 MC |
11760 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
11761 | { | |
989a9d23 | 11762 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
11763 | |
11764 | nvcfg1 = tr32(NVRAM_CFG1); | |
11765 | ||
11766 | /* NVRAM protection for TPM */ | |
989a9d23 | 11767 | if (nvcfg1 & (1 << 27)) { |
f66a29b0 | 11768 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
989a9d23 MC |
11769 | protect = 1; |
11770 | } | |
d3c7b886 | 11771 | |
989a9d23 MC |
11772 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
11773 | switch (nvcfg1) { | |
8590a603 MC |
11774 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
11775 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11776 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11777 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11778 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11779 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11780 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11781 | tp->nvram_pagesize = 264; | |
11782 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11783 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11784 | tp->nvram_size = (protect ? 0x3e200 : | |
11785 | TG3_NVRAM_SIZE_512KB); | |
11786 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11787 | tp->nvram_size = (protect ? 0x1f200 : | |
11788 | TG3_NVRAM_SIZE_256KB); | |
11789 | else | |
11790 | tp->nvram_size = (protect ? 0x1f200 : | |
11791 | TG3_NVRAM_SIZE_128KB); | |
11792 | break; | |
11793 | case FLASH_5752VENDOR_ST_M45PE10: | |
11794 | case FLASH_5752VENDOR_ST_M45PE20: | |
11795 | case FLASH_5752VENDOR_ST_M45PE40: | |
11796 | tp->nvram_jedecnum = JEDEC_ST; | |
11797 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11798 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11799 | tp->nvram_pagesize = 256; | |
11800 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11801 | tp->nvram_size = (protect ? | |
11802 | TG3_NVRAM_SIZE_64KB : | |
11803 | TG3_NVRAM_SIZE_128KB); | |
11804 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
11805 | tp->nvram_size = (protect ? | |
11806 | TG3_NVRAM_SIZE_64KB : | |
11807 | TG3_NVRAM_SIZE_256KB); | |
11808 | else | |
11809 | tp->nvram_size = (protect ? | |
11810 | TG3_NVRAM_SIZE_128KB : | |
11811 | TG3_NVRAM_SIZE_512KB); | |
11812 | break; | |
d3c7b886 MC |
11813 | } |
11814 | } | |
11815 | ||
1b27777a MC |
11816 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
11817 | { | |
11818 | u32 nvcfg1; | |
11819 | ||
11820 | nvcfg1 = tr32(NVRAM_CFG1); | |
11821 | ||
11822 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
11823 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
11824 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11825 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
11826 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11827 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11828 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11829 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
1b27777a | 11830 | |
8590a603 MC |
11831 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11832 | tw32(NVRAM_CFG1, nvcfg1); | |
11833 | break; | |
11834 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11835 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11836 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11837 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11838 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11839 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11840 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11841 | tp->nvram_pagesize = 264; | |
11842 | break; | |
11843 | case FLASH_5752VENDOR_ST_M45PE10: | |
11844 | case FLASH_5752VENDOR_ST_M45PE20: | |
11845 | case FLASH_5752VENDOR_ST_M45PE40: | |
11846 | tp->nvram_jedecnum = JEDEC_ST; | |
11847 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11848 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11849 | tp->nvram_pagesize = 256; | |
11850 | break; | |
1b27777a MC |
11851 | } |
11852 | } | |
11853 | ||
6b91fa02 MC |
11854 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
11855 | { | |
11856 | u32 nvcfg1, protect = 0; | |
11857 | ||
11858 | nvcfg1 = tr32(NVRAM_CFG1); | |
11859 | ||
11860 | /* NVRAM protection for TPM */ | |
11861 | if (nvcfg1 & (1 << 27)) { | |
f66a29b0 | 11862 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
6b91fa02 MC |
11863 | protect = 1; |
11864 | } | |
11865 | ||
11866 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11867 | switch (nvcfg1) { | |
8590a603 MC |
11868 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
11869 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11870 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11871 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11872 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11873 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11874 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11875 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11876 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11877 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11878 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11879 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
11880 | tp->nvram_pagesize = 256; | |
11881 | break; | |
11882 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11883 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11884 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11885 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11886 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11887 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11888 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11889 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11890 | tp->nvram_jedecnum = JEDEC_ST; | |
11891 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11892 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11893 | tp->nvram_pagesize = 256; | |
11894 | break; | |
6b91fa02 MC |
11895 | } |
11896 | ||
11897 | if (protect) { | |
11898 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
11899 | } else { | |
11900 | switch (nvcfg1) { | |
8590a603 MC |
11901 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
11902 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11903 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11904 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11905 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
11906 | break; | |
11907 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11908 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11909 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11910 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11911 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11912 | break; | |
11913 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11914 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11915 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11916 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11917 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11918 | break; | |
11919 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11920 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11921 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11922 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11923 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11924 | break; | |
6b91fa02 MC |
11925 | } |
11926 | } | |
11927 | } | |
11928 | ||
b5d3772c MC |
11929 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
11930 | { | |
11931 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11932 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11933 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11934 | } | |
11935 | ||
321d32a0 MC |
11936 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
11937 | { | |
11938 | u32 nvcfg1; | |
11939 | ||
11940 | nvcfg1 = tr32(NVRAM_CFG1); | |
11941 | ||
11942 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11943 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11944 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11945 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11946 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11947 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11948 | ||
11949 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11950 | tw32(NVRAM_CFG1, nvcfg1); | |
11951 | return; | |
11952 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11953 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11954 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11955 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11956 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11957 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11958 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11959 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11960 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11961 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11962 | ||
11963 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11964 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11965 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11966 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11967 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11968 | break; | |
11969 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11970 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11971 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11972 | break; | |
11973 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11974 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11975 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11976 | break; | |
11977 | } | |
11978 | break; | |
11979 | case FLASH_5752VENDOR_ST_M45PE10: | |
11980 | case FLASH_5752VENDOR_ST_M45PE20: | |
11981 | case FLASH_5752VENDOR_ST_M45PE40: | |
11982 | tp->nvram_jedecnum = JEDEC_ST; | |
11983 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11984 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11985 | ||
11986 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11987 | case FLASH_5752VENDOR_ST_M45PE10: | |
11988 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11989 | break; | |
11990 | case FLASH_5752VENDOR_ST_M45PE20: | |
11991 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11992 | break; | |
11993 | case FLASH_5752VENDOR_ST_M45PE40: | |
11994 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11995 | break; | |
11996 | } | |
11997 | break; | |
11998 | default: | |
df259d8c | 11999 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; |
321d32a0 MC |
12000 | return; |
12001 | } | |
12002 | ||
a1b950d5 MC |
12003 | tg3_nvram_get_pagesize(tp, nvcfg1); |
12004 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
321d32a0 | 12005 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; |
a1b950d5 MC |
12006 | } |
12007 | ||
12008 | ||
12009 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
12010 | { | |
12011 | u32 nvcfg1; | |
12012 | ||
12013 | nvcfg1 = tr32(NVRAM_CFG1); | |
12014 | ||
12015 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12016 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
12017 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
12018 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12019 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12020 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12021 | ||
12022 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12023 | tw32(NVRAM_CFG1, nvcfg1); | |
12024 | return; | |
12025 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
12026 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
12027 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
12028 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
12029 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
12030 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12031 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
12032 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12033 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12034 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
12035 | ||
12036 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12037 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
66ee33bf MC |
12038 | /* Detect size with tg3_nvram_get_size() */ |
12039 | break; | |
a1b950d5 MC |
12040 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
12041 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
12042 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12043 | break; | |
12044 | default: | |
12045 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12046 | break; | |
12047 | } | |
321d32a0 | 12048 | break; |
a1b950d5 MC |
12049 | case FLASH_5717VENDOR_ST_M_M25PE10: |
12050 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
12051 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
12052 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
12053 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
12054 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
12055 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
12056 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
12057 | case FLASH_5717VENDOR_ST_25USPT: | |
12058 | case FLASH_5717VENDOR_ST_45USPT: | |
12059 | tp->nvram_jedecnum = JEDEC_ST; | |
12060 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12061 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
12062 | ||
12063 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
12064 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
a1b950d5 | 12065 | case FLASH_5717VENDOR_ST_M_M45PE20: |
66ee33bf MC |
12066 | /* Detect size with tg3_nvram_get_size() */ |
12067 | break; | |
12068 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
a1b950d5 MC |
12069 | case FLASH_5717VENDOR_ST_A_M45PE20: |
12070 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12071 | break; | |
12072 | default: | |
12073 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12074 | break; | |
12075 | } | |
321d32a0 | 12076 | break; |
a1b950d5 MC |
12077 | default: |
12078 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
12079 | return; | |
321d32a0 | 12080 | } |
a1b950d5 MC |
12081 | |
12082 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12083 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
12084 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
321d32a0 MC |
12085 | } |
12086 | ||
9b91b5f1 MC |
12087 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
12088 | { | |
12089 | u32 nvcfg1, nvmpinstrp; | |
12090 | ||
12091 | nvcfg1 = tr32(NVRAM_CFG1); | |
12092 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
12093 | ||
12094 | switch (nvmpinstrp) { | |
12095 | case FLASH_5720_EEPROM_HD: | |
12096 | case FLASH_5720_EEPROM_LD: | |
12097 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12098 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12099 | ||
12100 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
12101 | tw32(NVRAM_CFG1, nvcfg1); | |
12102 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
12103 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
12104 | else | |
12105 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
12106 | return; | |
12107 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
12108 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
12109 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
12110 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12111 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12112 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12113 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12114 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12115 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12116 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12117 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12118 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
12119 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
12120 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12121 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
12122 | ||
12123 | switch (nvmpinstrp) { | |
12124 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
12125 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
12126 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
12127 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12128 | break; | |
12129 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
12130 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
12131 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
12132 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12133 | break; | |
12134 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
12135 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
12136 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12137 | break; | |
12138 | default: | |
12139 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12140 | break; | |
12141 | } | |
12142 | break; | |
12143 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
12144 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
12145 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
12146 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
12147 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12148 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12149 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12150 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12151 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12152 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12153 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12154 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12155 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12156 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12157 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12158 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12159 | case FLASH_5720VENDOR_ST_25USPT: | |
12160 | case FLASH_5720VENDOR_ST_45USPT: | |
12161 | tp->nvram_jedecnum = JEDEC_ST; | |
12162 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
12163 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
12164 | ||
12165 | switch (nvmpinstrp) { | |
12166 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
12167 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
12168 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
12169 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
12170 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
12171 | break; | |
12172 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
12173 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
12174 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
12175 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
12176 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
12177 | break; | |
12178 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
12179 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
12180 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
12181 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
12182 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
12183 | break; | |
12184 | default: | |
12185 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
12186 | break; | |
12187 | } | |
12188 | break; | |
12189 | default: | |
12190 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
12191 | return; | |
12192 | } | |
12193 | ||
12194 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12195 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
12196 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
12197 | } | |
12198 | ||
1da177e4 LT |
12199 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
12200 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
12201 | { | |
1da177e4 LT |
12202 | tw32_f(GRC_EEPROM_ADDR, |
12203 | (EEPROM_ADDR_FSM_RESET | | |
12204 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
12205 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
12206 | ||
9d57f01c | 12207 | msleep(1); |
1da177e4 LT |
12208 | |
12209 | /* Enable seeprom accesses. */ | |
12210 | tw32_f(GRC_LOCAL_CTRL, | |
12211 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
12212 | udelay(100); | |
12213 | ||
12214 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12215 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
12216 | tp->tg3_flags |= TG3_FLAG_NVRAM; | |
12217 | ||
ec41c7df | 12218 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
12219 | netdev_warn(tp->dev, |
12220 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 12221 | __func__); |
ec41c7df MC |
12222 | return; |
12223 | } | |
e6af301b | 12224 | tg3_enable_nvram_access(tp); |
1da177e4 | 12225 | |
989a9d23 MC |
12226 | tp->nvram_size = 0; |
12227 | ||
361b4ac2 MC |
12228 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
12229 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
12230 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
12231 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 12232 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
12233 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
12234 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 12235 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
12236 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
12237 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
12238 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12239 | tg3_get_5906_nvram_info(tp); | |
b703df6f MC |
12240 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12241 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 | 12242 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
12243 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12244 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 12245 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
12246 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
12247 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
12248 | else |
12249 | tg3_get_nvram_info(tp); | |
12250 | ||
989a9d23 MC |
12251 | if (tp->nvram_size == 0) |
12252 | tg3_get_nvram_size(tp); | |
1da177e4 | 12253 | |
e6af301b | 12254 | tg3_disable_nvram_access(tp); |
381291b7 | 12255 | tg3_nvram_unlock(tp); |
1da177e4 LT |
12256 | |
12257 | } else { | |
12258 | tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); | |
12259 | ||
12260 | tg3_get_eeprom_size(tp); | |
12261 | } | |
12262 | } | |
12263 | ||
1da177e4 LT |
12264 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
12265 | u32 offset, u32 len, u8 *buf) | |
12266 | { | |
12267 | int i, j, rc = 0; | |
12268 | u32 val; | |
12269 | ||
12270 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 12271 | u32 addr; |
a9dc529d | 12272 | __be32 data; |
1da177e4 LT |
12273 | |
12274 | addr = offset + i; | |
12275 | ||
12276 | memcpy(&data, buf + i, 4); | |
12277 | ||
62cedd11 MC |
12278 | /* |
12279 | * The SEEPROM interface expects the data to always be opposite | |
12280 | * the native endian format. We accomplish this by reversing | |
12281 | * all the operations that would have been performed on the | |
12282 | * data from a call to tg3_nvram_read_be32(). | |
12283 | */ | |
12284 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
12285 | |
12286 | val = tr32(GRC_EEPROM_ADDR); | |
12287 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
12288 | ||
12289 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
12290 | EEPROM_ADDR_READ); | |
12291 | tw32(GRC_EEPROM_ADDR, val | | |
12292 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
12293 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
12294 | EEPROM_ADDR_START | | |
12295 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 12296 | |
9d57f01c | 12297 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
12298 | val = tr32(GRC_EEPROM_ADDR); |
12299 | ||
12300 | if (val & EEPROM_ADDR_COMPLETE) | |
12301 | break; | |
9d57f01c | 12302 | msleep(1); |
1da177e4 LT |
12303 | } |
12304 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
12305 | rc = -EBUSY; | |
12306 | break; | |
12307 | } | |
12308 | } | |
12309 | ||
12310 | return rc; | |
12311 | } | |
12312 | ||
12313 | /* offset and length are dword aligned */ | |
12314 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
12315 | u8 *buf) | |
12316 | { | |
12317 | int ret = 0; | |
12318 | u32 pagesize = tp->nvram_pagesize; | |
12319 | u32 pagemask = pagesize - 1; | |
12320 | u32 nvram_cmd; | |
12321 | u8 *tmp; | |
12322 | ||
12323 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
12324 | if (tmp == NULL) | |
12325 | return -ENOMEM; | |
12326 | ||
12327 | while (len) { | |
12328 | int j; | |
e6af301b | 12329 | u32 phy_addr, page_off, size; |
1da177e4 LT |
12330 | |
12331 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 12332 | |
1da177e4 | 12333 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
12334 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
12335 | (__be32 *) (tmp + j)); | |
12336 | if (ret) | |
1da177e4 LT |
12337 | break; |
12338 | } | |
12339 | if (ret) | |
12340 | break; | |
12341 | ||
c6cdf436 | 12342 | page_off = offset & pagemask; |
1da177e4 LT |
12343 | size = pagesize; |
12344 | if (len < size) | |
12345 | size = len; | |
12346 | ||
12347 | len -= size; | |
12348 | ||
12349 | memcpy(tmp + page_off, buf, size); | |
12350 | ||
12351 | offset = offset + (pagesize - page_off); | |
12352 | ||
e6af301b | 12353 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
12354 | |
12355 | /* | |
12356 | * Before we can erase the flash page, we need | |
12357 | * to issue a special "write enable" command. | |
12358 | */ | |
12359 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12360 | ||
12361 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12362 | break; | |
12363 | ||
12364 | /* Erase the target page */ | |
12365 | tw32(NVRAM_ADDR, phy_addr); | |
12366 | ||
12367 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
12368 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
12369 | ||
c6cdf436 | 12370 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
12371 | break; |
12372 | ||
12373 | /* Issue another write enable to start the write. */ | |
12374 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12375 | ||
12376 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12377 | break; | |
12378 | ||
12379 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 12380 | __be32 data; |
1da177e4 | 12381 | |
b9fc7dc5 | 12382 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 12383 | |
b9fc7dc5 | 12384 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
12385 | |
12386 | tw32(NVRAM_ADDR, phy_addr + j); | |
12387 | ||
12388 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12389 | NVRAM_CMD_WR; | |
12390 | ||
12391 | if (j == 0) | |
12392 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12393 | else if (j == (pagesize - 4)) | |
12394 | nvram_cmd |= NVRAM_CMD_LAST; | |
12395 | ||
12396 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12397 | break; | |
12398 | } | |
12399 | if (ret) | |
12400 | break; | |
12401 | } | |
12402 | ||
12403 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12404 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12405 | ||
12406 | kfree(tmp); | |
12407 | ||
12408 | return ret; | |
12409 | } | |
12410 | ||
12411 | /* offset and length are dword aligned */ | |
12412 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12413 | u8 *buf) | |
12414 | { | |
12415 | int i, ret = 0; | |
12416 | ||
12417 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
12418 | u32 page_off, phy_addr, nvram_cmd; |
12419 | __be32 data; | |
1da177e4 LT |
12420 | |
12421 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 12422 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 12423 | |
c6cdf436 | 12424 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 12425 | |
1820180b | 12426 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
12427 | |
12428 | tw32(NVRAM_ADDR, phy_addr); | |
12429 | ||
12430 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12431 | ||
c6cdf436 | 12432 | if (page_off == 0 || i == 0) |
1da177e4 | 12433 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 12434 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
12435 | nvram_cmd |= NVRAM_CMD_LAST; |
12436 | ||
12437 | if (i == (len - 4)) | |
12438 | nvram_cmd |= NVRAM_CMD_LAST; | |
12439 | ||
321d32a0 MC |
12440 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
12441 | !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
4c987487 MC |
12442 | (tp->nvram_jedecnum == JEDEC_ST) && |
12443 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
12444 | |
12445 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12446 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12447 | NVRAM_CMD_DONE))) | |
12448 | ||
12449 | break; | |
12450 | } | |
12451 | if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12452 | /* We always do complete word writes to eeprom. */ | |
12453 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12454 | } | |
12455 | ||
12456 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12457 | break; | |
12458 | } | |
12459 | return ret; | |
12460 | } | |
12461 | ||
12462 | /* offset and length are dword aligned */ | |
12463 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12464 | { | |
12465 | int ret; | |
12466 | ||
1da177e4 | 12467 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
314fba34 MC |
12468 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
12469 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
12470 | udelay(40); |
12471 | } | |
12472 | ||
12473 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { | |
12474 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
859a5887 | 12475 | } else { |
1da177e4 LT |
12476 | u32 grc_mode; |
12477 | ||
ec41c7df MC |
12478 | ret = tg3_nvram_lock(tp); |
12479 | if (ret) | |
12480 | return ret; | |
1da177e4 | 12481 | |
e6af301b MC |
12482 | tg3_enable_nvram_access(tp); |
12483 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 12484 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) |
1da177e4 | 12485 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
12486 | |
12487 | grc_mode = tr32(GRC_MODE); | |
12488 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12489 | ||
12490 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || | |
12491 | !(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12492 | ||
12493 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
12494 | buf); | |
859a5887 | 12495 | } else { |
1da177e4 LT |
12496 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
12497 | buf); | |
12498 | } | |
12499 | ||
12500 | grc_mode = tr32(GRC_MODE); | |
12501 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12502 | ||
e6af301b | 12503 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
12504 | tg3_nvram_unlock(tp); |
12505 | } | |
12506 | ||
12507 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
314fba34 | 12508 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
12509 | udelay(40); |
12510 | } | |
12511 | ||
12512 | return ret; | |
12513 | } | |
12514 | ||
12515 | struct subsys_tbl_ent { | |
12516 | u16 subsys_vendor, subsys_devid; | |
12517 | u32 phy_id; | |
12518 | }; | |
12519 | ||
24daf2b0 | 12520 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 12521 | /* Broadcom boards. */ |
24daf2b0 | 12522 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12523 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12524 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12525 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12526 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12527 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
12528 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12529 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12530 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12531 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12532 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12533 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12534 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12535 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12536 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12537 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12538 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12539 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12540 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12541 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 12542 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12543 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
12544 | |
12545 | /* 3com boards. */ | |
24daf2b0 | 12546 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12547 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12548 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12549 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12550 | { TG3PCI_SUBVENDOR_ID_3COM, |
12551 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12552 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 12553 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12554 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12555 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12556 | |
12557 | /* DELL boards. */ | |
24daf2b0 | 12558 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12559 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12560 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12561 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12562 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12563 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 12564 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12565 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
12566 | |
12567 | /* Compaq boards. */ | |
24daf2b0 | 12568 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12569 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12570 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12571 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12572 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
12573 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12574 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 12575 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12576 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12577 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12578 | |
12579 | /* IBM boards. */ | |
24daf2b0 MC |
12580 | { TG3PCI_SUBVENDOR_ID_IBM, |
12581 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
12582 | }; |
12583 | ||
24daf2b0 | 12584 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
12585 | { |
12586 | int i; | |
12587 | ||
12588 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12589 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12590 | tp->pdev->subsystem_vendor) && | |
12591 | (subsys_id_to_phy_id[i].subsys_devid == | |
12592 | tp->pdev->subsystem_device)) | |
12593 | return &subsys_id_to_phy_id[i]; | |
12594 | } | |
12595 | return NULL; | |
12596 | } | |
12597 | ||
7d0c41ef | 12598 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 12599 | { |
1da177e4 | 12600 | u32 val; |
caf636c7 MC |
12601 | u16 pmcsr; |
12602 | ||
12603 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
12604 | * so need make sure we're in D0. | |
12605 | */ | |
12606 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
12607 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
12608 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
12609 | msleep(1); | |
7d0c41ef MC |
12610 | |
12611 | /* Make sure register accesses (indirect or otherwise) | |
12612 | * will function correctly. | |
12613 | */ | |
12614 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12615 | tp->misc_host_ctrl); | |
1da177e4 | 12616 | |
f49639e6 DM |
12617 | /* The memory arbiter has to be enabled in order for SRAM accesses |
12618 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
12619 | * sure it is enabled, but other entities such as system netboot | |
12620 | * code might disable it. | |
12621 | */ | |
12622 | val = tr32(MEMARB_MODE); | |
12623 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
12624 | ||
79eb6904 | 12625 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12626 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12627 | ||
a85feb8c GZ |
12628 | /* Assume an onboard device and WOL capable by default. */ |
12629 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; | |
72b845e0 | 12630 | |
b5d3772c | 12631 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12632 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
b5d3772c | 12633 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12634 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12635 | } | |
0527ba35 MC |
12636 | val = tr32(VCPU_CFGSHDW); |
12637 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
8ed5d97e | 12638 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; |
0527ba35 | 12639 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
2023276e | 12640 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) |
0527ba35 | 12641 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
05ac4cb7 | 12642 | goto done; |
b5d3772c MC |
12643 | } |
12644 | ||
1da177e4 LT |
12645 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
12646 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12647 | u32 nic_cfg, led_cfg; | |
a9daf367 | 12648 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 12649 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
12650 | |
12651 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12652 | tp->nic_sram_data_cfg = nic_cfg; | |
12653 | ||
12654 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12655 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
12656 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && | |
12657 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && | |
12658 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) && | |
12659 | (ver > 0) && (ver < 0x100)) | |
12660 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12661 | ||
a9daf367 MC |
12662 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
12663 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12664 | ||
1da177e4 LT |
12665 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
12666 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12667 | eeprom_phy_serdes = 1; | |
12668 | ||
12669 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12670 | if (nic_phy_id != 0) { | |
12671 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12672 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12673 | ||
12674 | eeprom_phy_id = (id1 >> 16) << 10; | |
12675 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12676 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12677 | } else | |
12678 | eeprom_phy_id = 0; | |
12679 | ||
7d0c41ef | 12680 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 12681 | if (eeprom_phy_serdes) { |
a50d0796 | 12682 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
f07e9af3 | 12683 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 12684 | else |
f07e9af3 | 12685 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 12686 | } |
7d0c41ef | 12687 | |
cbf46853 | 12688 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12689 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
12690 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 12691 | else |
1da177e4 LT |
12692 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
12693 | ||
12694 | switch (led_cfg) { | |
12695 | default: | |
12696 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12697 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12698 | break; | |
12699 | ||
12700 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12701 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12702 | break; | |
12703 | ||
12704 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12705 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
12706 | |
12707 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12708 | * read on some older 5700/5701 bootcode. | |
12709 | */ | |
12710 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12711 | ASIC_REV_5700 || | |
12712 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12713 | ASIC_REV_5701) | |
12714 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12715 | ||
1da177e4 LT |
12716 | break; |
12717 | ||
12718 | case SHASTA_EXT_LED_SHARED: | |
12719 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12720 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12721 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12722 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12723 | LED_CTRL_MODE_PHY_2); | |
12724 | break; | |
12725 | ||
12726 | case SHASTA_EXT_LED_MAC: | |
12727 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12728 | break; | |
12729 | ||
12730 | case SHASTA_EXT_LED_COMBO: | |
12731 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12732 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12733 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12734 | LED_CTRL_MODE_PHY_2); | |
12735 | break; | |
12736 | ||
855e1111 | 12737 | } |
1da177e4 LT |
12738 | |
12739 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12740 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12741 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12742 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12743 | ||
b2a5c19c MC |
12744 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
12745 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 12746 | |
9d26e213 | 12747 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
1da177e4 | 12748 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12749 | if ((tp->pdev->subsystem_vendor == |
12750 | PCI_VENDOR_ID_ARIMA) && | |
12751 | (tp->pdev->subsystem_device == 0x205a || | |
12752 | tp->pdev->subsystem_device == 0x2063)) | |
12753 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
12754 | } else { | |
f49639e6 | 12755 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12756 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12757 | } | |
1da177e4 LT |
12758 | |
12759 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
12760 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
cbf46853 | 12761 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12762 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
12763 | } | |
b2b98d4a MC |
12764 | |
12765 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
12766 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
0d3031d9 | 12767 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; |
b2b98d4a | 12768 | |
f07e9af3 | 12769 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c GZ |
12770 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
12771 | tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; | |
1da177e4 | 12772 | |
12dac075 | 12773 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
05ac4cb7 | 12774 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) |
0527ba35 MC |
12775 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
12776 | ||
1da177e4 | 12777 | if (cfg2 & (1 << 17)) |
f07e9af3 | 12778 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
12779 | |
12780 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
12781 | /* bootcode if bit 18 is set */ | |
12782 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 12783 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 12784 | |
1407deb1 | 12785 | if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) || |
2e1e3291 MC |
12786 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
12787 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) && | |
6833c043 | 12788 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 12789 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 12790 | |
8c69b1e7 MC |
12791 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
12792 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
1407deb1 | 12793 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
8ed5d97e MC |
12794 | u32 cfg3; |
12795 | ||
12796 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
12797 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
12798 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
12799 | } | |
a9daf367 | 12800 | |
14417063 MC |
12801 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
12802 | tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE; | |
a9daf367 MC |
12803 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
12804 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; | |
12805 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
12806 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; | |
1da177e4 | 12807 | } |
05ac4cb7 | 12808 | done: |
43067ed8 RW |
12809 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
12810 | device_set_wakeup_enable(&tp->pdev->dev, | |
05ac4cb7 | 12811 | tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
43067ed8 RW |
12812 | else |
12813 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
12814 | } |
12815 | ||
b2a5c19c MC |
12816 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
12817 | { | |
12818 | int i; | |
12819 | u32 val; | |
12820 | ||
12821 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
12822 | tw32(OTP_CTRL, cmd); | |
12823 | ||
12824 | /* Wait for up to 1 ms for command to execute. */ | |
12825 | for (i = 0; i < 100; i++) { | |
12826 | val = tr32(OTP_STATUS); | |
12827 | if (val & OTP_STATUS_CMD_DONE) | |
12828 | break; | |
12829 | udelay(10); | |
12830 | } | |
12831 | ||
12832 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
12833 | } | |
12834 | ||
12835 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
12836 | * configuration is a 32-bit value that straddles the alignment boundary. | |
12837 | * We do two 32-bit reads and then shift and merge the results. | |
12838 | */ | |
12839 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
12840 | { | |
12841 | u32 bhalf_otp, thalf_otp; | |
12842 | ||
12843 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
12844 | ||
12845 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
12846 | return 0; | |
12847 | ||
12848 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
12849 | ||
12850 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12851 | return 0; | |
12852 | ||
12853 | thalf_otp = tr32(OTP_READ_DATA); | |
12854 | ||
12855 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
12856 | ||
12857 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12858 | return 0; | |
12859 | ||
12860 | bhalf_otp = tr32(OTP_READ_DATA); | |
12861 | ||
12862 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
12863 | } | |
12864 | ||
e256f8a3 MC |
12865 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
12866 | { | |
12867 | u32 adv = ADVERTISED_Autoneg | | |
12868 | ADVERTISED_Pause; | |
12869 | ||
12870 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
12871 | adv |= ADVERTISED_1000baseT_Half | | |
12872 | ADVERTISED_1000baseT_Full; | |
12873 | ||
12874 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
12875 | adv |= ADVERTISED_100baseT_Half | | |
12876 | ADVERTISED_100baseT_Full | | |
12877 | ADVERTISED_10baseT_Half | | |
12878 | ADVERTISED_10baseT_Full | | |
12879 | ADVERTISED_TP; | |
12880 | else | |
12881 | adv |= ADVERTISED_FIBRE; | |
12882 | ||
12883 | tp->link_config.advertising = adv; | |
12884 | tp->link_config.speed = SPEED_INVALID; | |
12885 | tp->link_config.duplex = DUPLEX_INVALID; | |
12886 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
12887 | tp->link_config.active_speed = SPEED_INVALID; | |
12888 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
12889 | tp->link_config.orig_speed = SPEED_INVALID; | |
12890 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
12891 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
12892 | } | |
12893 | ||
7d0c41ef MC |
12894 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
12895 | { | |
12896 | u32 hw_phy_id_1, hw_phy_id_2; | |
12897 | u32 hw_phy_id, hw_phy_id_masked; | |
12898 | int err; | |
1da177e4 | 12899 | |
e256f8a3 MC |
12900 | /* flow control autonegotiation is default behavior */ |
12901 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
12902 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
12903 | ||
b02fd9e3 MC |
12904 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
12905 | return tg3_phy_init(tp); | |
12906 | ||
1da177e4 | 12907 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 12908 | * firmware access to the PHY hardware. |
1da177e4 LT |
12909 | */ |
12910 | err = 0; | |
0d3031d9 MC |
12911 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || |
12912 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
79eb6904 | 12913 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
12914 | } else { |
12915 | /* Now read the physical PHY_ID from the chip and verify | |
12916 | * that it is sane. If it doesn't look good, we fall back | |
12917 | * to either the hard-coded table based PHY_ID and failing | |
12918 | * that the value found in the eeprom area. | |
12919 | */ | |
12920 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
12921 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
12922 | ||
12923 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
12924 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
12925 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
12926 | ||
79eb6904 | 12927 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
12928 | } |
12929 | ||
79eb6904 | 12930 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 12931 | tp->phy_id = hw_phy_id; |
79eb6904 | 12932 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 12933 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 12934 | else |
f07e9af3 | 12935 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 12936 | } else { |
79eb6904 | 12937 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
12938 | /* Do nothing, phy ID already set up in |
12939 | * tg3_get_eeprom_hw_cfg(). | |
12940 | */ | |
1da177e4 LT |
12941 | } else { |
12942 | struct subsys_tbl_ent *p; | |
12943 | ||
12944 | /* No eeprom signature? Try the hardcoded | |
12945 | * subsys device table. | |
12946 | */ | |
24daf2b0 | 12947 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
12948 | if (!p) |
12949 | return -ENODEV; | |
12950 | ||
12951 | tp->phy_id = p->phy_id; | |
12952 | if (!tp->phy_id || | |
79eb6904 | 12953 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 12954 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
12955 | } |
12956 | } | |
12957 | ||
a6b68dab MC |
12958 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
12959 | ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
12960 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || | |
12961 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
12962 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
12963 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
12964 | ||
e256f8a3 MC |
12965 | tg3_phy_init_link_config(tp); |
12966 | ||
f07e9af3 | 12967 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
0d3031d9 | 12968 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && |
1da177e4 | 12969 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
3600d918 | 12970 | u32 bmsr, adv_reg, tg3_ctrl, mask; |
1da177e4 LT |
12971 | |
12972 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
12973 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
12974 | (bmsr & BMSR_LSTATUS)) | |
12975 | goto skip_phy_reset; | |
6aa20a22 | 12976 | |
1da177e4 LT |
12977 | err = tg3_phy_reset(tp); |
12978 | if (err) | |
12979 | return err; | |
12980 | ||
12981 | adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
12982 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
12983 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
12984 | tg3_ctrl = 0; | |
f07e9af3 | 12985 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
12986 | tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | |
12987 | MII_TG3_CTRL_ADV_1000_FULL); | |
12988 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
12989 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
12990 | tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER | | |
12991 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
12992 | } | |
12993 | ||
3600d918 MC |
12994 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
12995 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
12996 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
12997 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
1da177e4 LT |
12998 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); |
12999 | ||
f07e9af3 | 13000 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
13001 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); |
13002 | ||
13003 | tg3_writephy(tp, MII_BMCR, | |
13004 | BMCR_ANENABLE | BMCR_ANRESTART); | |
13005 | } | |
13006 | tg3_phy_set_wirespeed(tp); | |
13007 | ||
13008 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
f07e9af3 | 13009 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
13010 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); |
13011 | } | |
13012 | ||
13013 | skip_phy_reset: | |
79eb6904 | 13014 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
13015 | err = tg3_init_5401phy_dsp(tp); |
13016 | if (err) | |
13017 | return err; | |
1da177e4 | 13018 | |
1da177e4 LT |
13019 | err = tg3_init_5401phy_dsp(tp); |
13020 | } | |
13021 | ||
1da177e4 LT |
13022 | return err; |
13023 | } | |
13024 | ||
184b8904 | 13025 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 13026 | { |
a4a8bb15 | 13027 | u8 *vpd_data; |
4181b2c8 | 13028 | unsigned int block_end, rosize, len; |
184b8904 | 13029 | int j, i = 0; |
a4a8bb15 | 13030 | |
c3e94500 | 13031 | vpd_data = (u8 *)tg3_vpd_readblock(tp); |
a4a8bb15 MC |
13032 | if (!vpd_data) |
13033 | goto out_no_vpd; | |
1da177e4 | 13034 | |
4181b2c8 MC |
13035 | i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN, |
13036 | PCI_VPD_LRDT_RO_DATA); | |
13037 | if (i < 0) | |
13038 | goto out_not_found; | |
1da177e4 | 13039 | |
4181b2c8 MC |
13040 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
13041 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
13042 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 13043 | |
4181b2c8 MC |
13044 | if (block_end > TG3_NVM_VPD_LEN) |
13045 | goto out_not_found; | |
af2c6a4a | 13046 | |
184b8904 MC |
13047 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13048 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
13049 | if (j > 0) { | |
13050 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13051 | ||
13052 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13053 | if (j + len > block_end || len != 4 || | |
13054 | memcmp(&vpd_data[j], "1028", 4)) | |
13055 | goto partno; | |
13056 | ||
13057 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
13058 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
13059 | if (j < 0) | |
13060 | goto partno; | |
13061 | ||
13062 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
13063 | ||
13064 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
13065 | if (j + len > block_end) | |
13066 | goto partno; | |
13067 | ||
13068 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
13069 | strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1); | |
13070 | } | |
13071 | ||
13072 | partno: | |
4181b2c8 MC |
13073 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
13074 | PCI_VPD_RO_KEYWORD_PARTNO); | |
13075 | if (i < 0) | |
13076 | goto out_not_found; | |
af2c6a4a | 13077 | |
4181b2c8 | 13078 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 13079 | |
4181b2c8 MC |
13080 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
13081 | if (len > TG3_BPN_SIZE || | |
13082 | (len + i) > TG3_NVM_VPD_LEN) | |
13083 | goto out_not_found; | |
1da177e4 | 13084 | |
4181b2c8 | 13085 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 13086 | |
1da177e4 | 13087 | out_not_found: |
a4a8bb15 | 13088 | kfree(vpd_data); |
37a949c5 | 13089 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
13090 | return; |
13091 | ||
13092 | out_no_vpd: | |
37a949c5 MC |
13093 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13094 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
13095 | strcpy(tp->board_part_number, "BCM5717"); | |
13096 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
13097 | strcpy(tp->board_part_number, "BCM5718"); | |
13098 | else | |
13099 | goto nomatch; | |
13100 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
13101 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
13102 | strcpy(tp->board_part_number, "BCM57780"); | |
13103 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
13104 | strcpy(tp->board_part_number, "BCM57760"); | |
13105 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
13106 | strcpy(tp->board_part_number, "BCM57790"); | |
13107 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
13108 | strcpy(tp->board_part_number, "BCM57788"); | |
13109 | else | |
13110 | goto nomatch; | |
13111 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
13112 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
13113 | strcpy(tp->board_part_number, "BCM57761"); | |
13114 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
13115 | strcpy(tp->board_part_number, "BCM57765"); | |
13116 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
13117 | strcpy(tp->board_part_number, "BCM57781"); | |
13118 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
13119 | strcpy(tp->board_part_number, "BCM57785"); | |
13120 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
13121 | strcpy(tp->board_part_number, "BCM57791"); | |
13122 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13123 | strcpy(tp->board_part_number, "BCM57795"); | |
13124 | else | |
13125 | goto nomatch; | |
13126 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
b5d3772c | 13127 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
13128 | } else { |
13129 | nomatch: | |
b5d3772c | 13130 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 13131 | } |
1da177e4 LT |
13132 | } |
13133 | ||
9c8a620e MC |
13134 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
13135 | { | |
13136 | u32 val; | |
13137 | ||
e4f34110 | 13138 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 13139 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 13140 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
13141 | val != 0) |
13142 | return 0; | |
13143 | ||
13144 | return 1; | |
13145 | } | |
13146 | ||
acd9c119 MC |
13147 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
13148 | { | |
ff3a7cb2 | 13149 | u32 val, offset, start, ver_offset; |
75f9936e | 13150 | int i, dst_off; |
ff3a7cb2 | 13151 | bool newver = false; |
acd9c119 MC |
13152 | |
13153 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
13154 | tg3_nvram_read(tp, 0x4, &start)) | |
13155 | return; | |
13156 | ||
13157 | offset = tg3_nvram_logical_addr(tp, offset); | |
13158 | ||
ff3a7cb2 | 13159 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
13160 | return; |
13161 | ||
ff3a7cb2 MC |
13162 | if ((val & 0xfc000000) == 0x0c000000) { |
13163 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
13164 | return; |
13165 | ||
ff3a7cb2 MC |
13166 | if (val == 0) |
13167 | newver = true; | |
13168 | } | |
13169 | ||
75f9936e MC |
13170 | dst_off = strlen(tp->fw_ver); |
13171 | ||
ff3a7cb2 | 13172 | if (newver) { |
75f9936e MC |
13173 | if (TG3_VER_SIZE - dst_off < 16 || |
13174 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
13175 | return; |
13176 | ||
13177 | offset = offset + ver_offset - start; | |
13178 | for (i = 0; i < 16; i += 4) { | |
13179 | __be32 v; | |
13180 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13181 | return; | |
13182 | ||
75f9936e | 13183 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
13184 | } |
13185 | } else { | |
13186 | u32 major, minor; | |
13187 | ||
13188 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13189 | return; | |
13190 | ||
13191 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13192 | TG3_NVM_BCVER_MAJSFT; | |
13193 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
13194 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
13195 | "v%d.%02d", major, minor); | |
acd9c119 MC |
13196 | } |
13197 | } | |
13198 | ||
a6f6cb1c MC |
13199 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
13200 | { | |
13201 | u32 val, major, minor; | |
13202 | ||
13203 | /* Use native endian representation */ | |
13204 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13205 | return; | |
13206 | ||
13207 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13208 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13209 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13210 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13211 | ||
13212 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13213 | } | |
13214 | ||
dfe00d7d MC |
13215 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
13216 | { | |
13217 | u32 offset, major, minor, build; | |
13218 | ||
75f9936e | 13219 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
13220 | |
13221 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13222 | return; | |
13223 | ||
13224 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13225 | case TG3_EEPROM_SB_REVISION_0: | |
13226 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13227 | break; | |
13228 | case TG3_EEPROM_SB_REVISION_2: | |
13229 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13230 | break; | |
13231 | case TG3_EEPROM_SB_REVISION_3: | |
13232 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13233 | break; | |
a4153d40 MC |
13234 | case TG3_EEPROM_SB_REVISION_4: |
13235 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13236 | break; | |
13237 | case TG3_EEPROM_SB_REVISION_5: | |
13238 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13239 | break; | |
bba226ac MC |
13240 | case TG3_EEPROM_SB_REVISION_6: |
13241 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13242 | break; | |
dfe00d7d MC |
13243 | default: |
13244 | return; | |
13245 | } | |
13246 | ||
e4f34110 | 13247 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
13248 | return; |
13249 | ||
13250 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13251 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13252 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13253 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13254 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13255 | ||
13256 | if (minor > 99 || build > 26) | |
13257 | return; | |
13258 | ||
75f9936e MC |
13259 | offset = strlen(tp->fw_ver); |
13260 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13261 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
13262 | |
13263 | if (build > 0) { | |
75f9936e MC |
13264 | offset = strlen(tp->fw_ver); |
13265 | if (offset < TG3_VER_SIZE - 1) | |
13266 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
13267 | } |
13268 | } | |
13269 | ||
acd9c119 | 13270 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
13271 | { |
13272 | u32 val, offset, start; | |
acd9c119 | 13273 | int i, vlen; |
9c8a620e MC |
13274 | |
13275 | for (offset = TG3_NVM_DIR_START; | |
13276 | offset < TG3_NVM_DIR_END; | |
13277 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 13278 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
13279 | return; |
13280 | ||
9c8a620e MC |
13281 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
13282 | break; | |
13283 | } | |
13284 | ||
13285 | if (offset == TG3_NVM_DIR_END) | |
13286 | return; | |
13287 | ||
13288 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
13289 | start = 0x08000000; | |
e4f34110 | 13290 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
13291 | return; |
13292 | ||
e4f34110 | 13293 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 13294 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 13295 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
13296 | return; |
13297 | ||
13298 | offset += val - start; | |
13299 | ||
acd9c119 | 13300 | vlen = strlen(tp->fw_ver); |
9c8a620e | 13301 | |
acd9c119 MC |
13302 | tp->fw_ver[vlen++] = ','; |
13303 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
13304 | |
13305 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
13306 | __be32 v; |
13307 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
13308 | return; |
13309 | ||
b9fc7dc5 | 13310 | offset += sizeof(v); |
c4e6575c | 13311 | |
acd9c119 MC |
13312 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
13313 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 13314 | break; |
c4e6575c | 13315 | } |
9c8a620e | 13316 | |
acd9c119 MC |
13317 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
13318 | vlen += sizeof(v); | |
c4e6575c | 13319 | } |
acd9c119 MC |
13320 | } |
13321 | ||
7fd76445 MC |
13322 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
13323 | { | |
13324 | int vlen; | |
13325 | u32 apedata; | |
ecc79648 | 13326 | char *fwtype; |
7fd76445 MC |
13327 | |
13328 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || | |
13329 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
13330 | return; | |
13331 | ||
13332 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13333 | if (apedata != APE_SEG_SIG_MAGIC) | |
13334 | return; | |
13335 | ||
13336 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13337 | if (!(apedata & APE_FW_STATUS_READY)) | |
13338 | return; | |
13339 | ||
13340 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13341 | ||
dc6d0744 MC |
13342 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
13343 | tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI; | |
ecc79648 | 13344 | fwtype = "NCSI"; |
dc6d0744 | 13345 | } else { |
ecc79648 | 13346 | fwtype = "DASH"; |
dc6d0744 | 13347 | } |
ecc79648 | 13348 | |
7fd76445 MC |
13349 | vlen = strlen(tp->fw_ver); |
13350 | ||
ecc79648 MC |
13351 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
13352 | fwtype, | |
7fd76445 MC |
13353 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
13354 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13355 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13356 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13357 | } | |
13358 | ||
acd9c119 MC |
13359 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
13360 | { | |
13361 | u32 val; | |
75f9936e | 13362 | bool vpd_vers = false; |
acd9c119 | 13363 | |
75f9936e MC |
13364 | if (tp->fw_ver[0] != 0) |
13365 | vpd_vers = true; | |
df259d8c | 13366 | |
75f9936e MC |
13367 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { |
13368 | strcat(tp->fw_ver, "sb"); | |
df259d8c MC |
13369 | return; |
13370 | } | |
13371 | ||
acd9c119 MC |
13372 | if (tg3_nvram_read(tp, 0, &val)) |
13373 | return; | |
13374 | ||
13375 | if (val == TG3_EEPROM_MAGIC) | |
13376 | tg3_read_bc_ver(tp); | |
13377 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13378 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13379 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13380 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13381 | else |
13382 | return; | |
13383 | ||
13384 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
75f9936e MC |
13385 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers) |
13386 | goto done; | |
acd9c119 MC |
13387 | |
13388 | tg3_read_mgmtfw_ver(tp); | |
9c8a620e | 13389 | |
75f9936e | 13390 | done: |
9c8a620e | 13391 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13392 | } |
13393 | ||
7544b097 MC |
13394 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
13395 | ||
7cb32cf2 MC |
13396 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13397 | { | |
de9f5230 MC |
13398 | if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) |
13399 | return TG3_RX_RET_MAX_SIZE_5717; | |
7cb32cf2 MC |
13400 | else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
13401 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
de9f5230 | 13402 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 13403 | else |
de9f5230 | 13404 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
13405 | } |
13406 | ||
4143470c | 13407 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
13408 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
13409 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13410 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13411 | { }, | |
13412 | }; | |
13413 | ||
1da177e4 LT |
13414 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
13415 | { | |
1da177e4 | 13416 | u32 misc_ctrl_reg; |
1da177e4 LT |
13417 | u32 pci_state_reg, grc_misc_cfg; |
13418 | u32 val; | |
13419 | u16 pci_cmd; | |
5e7dfd0f | 13420 | int err; |
1da177e4 | 13421 | |
1da177e4 LT |
13422 | /* Force memory write invalidate off. If we leave it on, |
13423 | * then on 5700_BX chips we have to enable a workaround. | |
13424 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13425 | * to match the cacheline size. The Broadcom driver have this | |
13426 | * workaround but turns MWI off all the times so never uses | |
13427 | * it. This seems to suggest that the workaround is insufficient. | |
13428 | */ | |
13429 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13430 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13431 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13432 | ||
13433 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
13434 | * has the register indirect write enable bit set before | |
13435 | * we try to access any of the MMIO registers. It is also | |
13436 | * critical that the PCI-X hw workaround situation is decided | |
13437 | * before that as well. | |
13438 | */ | |
13439 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13440 | &misc_ctrl_reg); | |
13441 | ||
13442 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13443 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
13444 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
13445 | u32 prod_id_asic_rev; | |
13446 | ||
5001e2f6 MC |
13447 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
13448 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
d78b59f5 MC |
13449 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
13450 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
f6eb9b1f MC |
13451 | pci_read_config_dword(tp->pdev, |
13452 | TG3PCI_GEN2_PRODID_ASICREV, | |
13453 | &prod_id_asic_rev); | |
b703df6f MC |
13454 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
13455 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13456 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13457 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13458 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
13459 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13460 | pci_read_config_dword(tp->pdev, | |
13461 | TG3PCI_GEN15_PRODID_ASICREV, | |
13462 | &prod_id_asic_rev); | |
f6eb9b1f MC |
13463 | else |
13464 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13465 | &prod_id_asic_rev); | |
13466 | ||
321d32a0 | 13467 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 13468 | } |
1da177e4 | 13469 | |
ff645bec MC |
13470 | /* Wrong chip ID in 5752 A0. This code can be removed later |
13471 | * as A0 is not in production. | |
13472 | */ | |
13473 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13474 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13475 | ||
6892914f MC |
13476 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
13477 | * we need to disable memory and use config. cycles | |
13478 | * only to access all registers. The 5702/03 chips | |
13479 | * can mistakenly decode the special cycles from the | |
13480 | * ICH chipsets as memory write cycles, causing corruption | |
13481 | * of register and memory space. Only certain ICH bridges | |
13482 | * will drive special cycles with non-zero data during the | |
13483 | * address phase which can fall within the 5703's address | |
13484 | * range. This is not an ICH bug as the PCI spec allows | |
13485 | * non-zero address during special cycles. However, only | |
13486 | * these ICH bridges are known to drive non-zero addresses | |
13487 | * during special cycles. | |
13488 | * | |
13489 | * Since special cycles do not cross PCI bridges, we only | |
13490 | * enable this workaround if the 5703 is on the secondary | |
13491 | * bus of these ICH bridges. | |
13492 | */ | |
13493 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13494 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13495 | static struct tg3_dev_id { | |
13496 | u32 vendor; | |
13497 | u32 device; | |
13498 | u32 rev; | |
13499 | } ich_chipsets[] = { | |
13500 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13501 | PCI_ANY_ID }, | |
13502 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13503 | PCI_ANY_ID }, | |
13504 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13505 | 0xa }, | |
13506 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13507 | PCI_ANY_ID }, | |
13508 | { }, | |
13509 | }; | |
13510 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13511 | struct pci_dev *bridge = NULL; | |
13512 | ||
13513 | while (pci_id->vendor != 0) { | |
13514 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13515 | bridge); | |
13516 | if (!bridge) { | |
13517 | pci_id++; | |
13518 | continue; | |
13519 | } | |
13520 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 13521 | if (bridge->revision > pci_id->rev) |
6892914f MC |
13522 | continue; |
13523 | } | |
13524 | if (bridge->subordinate && | |
13525 | (bridge->subordinate->number == | |
13526 | tp->pdev->bus->number)) { | |
13527 | ||
13528 | tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND; | |
13529 | pci_dev_put(bridge); | |
13530 | break; | |
13531 | } | |
13532 | } | |
13533 | } | |
13534 | ||
41588ba1 MC |
13535 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { |
13536 | static struct tg3_dev_id { | |
13537 | u32 vendor; | |
13538 | u32 device; | |
13539 | } bridge_chipsets[] = { | |
13540 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13541 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13542 | { }, | |
13543 | }; | |
13544 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13545 | struct pci_dev *bridge = NULL; | |
13546 | ||
13547 | while (pci_id->vendor != 0) { | |
13548 | bridge = pci_get_device(pci_id->vendor, | |
13549 | pci_id->device, | |
13550 | bridge); | |
13551 | if (!bridge) { | |
13552 | pci_id++; | |
13553 | continue; | |
13554 | } | |
13555 | if (bridge->subordinate && | |
13556 | (bridge->subordinate->number <= | |
13557 | tp->pdev->bus->number) && | |
13558 | (bridge->subordinate->subordinate >= | |
13559 | tp->pdev->bus->number)) { | |
13560 | tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; | |
13561 | pci_dev_put(bridge); | |
13562 | break; | |
13563 | } | |
13564 | } | |
13565 | } | |
13566 | ||
4a29cc2e MC |
13567 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
13568 | * DMA addresses > 40-bit. This bridge may have other additional | |
13569 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13570 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13571 | * DMA workaround. | |
13572 | */ | |
a4e2b347 MC |
13573 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
13574 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
13575 | tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; | |
4a29cc2e | 13576 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; |
4cf78e4f | 13577 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 13578 | } else { |
4a29cc2e MC |
13579 | struct pci_dev *bridge = NULL; |
13580 | ||
13581 | do { | |
13582 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13583 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13584 | bridge); | |
13585 | if (bridge && bridge->subordinate && | |
13586 | (bridge->subordinate->number <= | |
13587 | tp->pdev->bus->number) && | |
13588 | (bridge->subordinate->subordinate >= | |
13589 | tp->pdev->bus->number)) { | |
13590 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
13591 | pci_dev_put(bridge); | |
13592 | break; | |
13593 | } | |
13594 | } while (bridge); | |
13595 | } | |
4cf78e4f | 13596 | |
1da177e4 LT |
13597 | /* Initialize misc host control in PCI block. */ |
13598 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
13599 | MISC_HOST_CTRL_CHIPREV); | |
13600 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13601 | tp->misc_host_ctrl); | |
13602 | ||
f6eb9b1f MC |
13603 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
13604 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
d78b59f5 MC |
13605 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13606 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
7544b097 MC |
13607 | tp->pdev_peer = tg3_find_peer(tp); |
13608 | ||
c885e824 | 13609 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
d78b59f5 MC |
13610 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13611 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
0a58d668 MC |
13612 | tp->tg3_flags3 |= TG3_FLG3_5717_PLUS; |
13613 | ||
13614 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
13615 | (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) | |
1407deb1 | 13616 | tp->tg3_flags3 |= TG3_FLG3_57765_PLUS; |
c885e824 | 13617 | |
321d32a0 MC |
13618 | /* Intentionally exclude ASIC_REV_5906 */ |
13619 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 13620 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 13621 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 13622 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 13623 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13624 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
1407deb1 | 13625 | (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) |
321d32a0 MC |
13626 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; |
13627 | ||
13628 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13629 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 13630 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
321d32a0 | 13631 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
a4e2b347 | 13632 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
6708e5cc JL |
13633 | tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; |
13634 | ||
eb07a940 | 13635 | |
1b440c56 JL |
13636 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || |
13637 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
13638 | tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; | |
13639 | ||
027455ad MC |
13640 | /* 5700 B0 chips do not support checksumming correctly due |
13641 | * to hardware bugs. | |
13642 | */ | |
dc668910 MM |
13643 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { |
13644 | u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | |
7fe876af | 13645 | |
027455ad | 13646 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
7fe876af ED |
13647 | features |= NETIF_F_IPV6_CSUM; |
13648 | tp->dev->features |= features; | |
dc668910 MM |
13649 | tp->dev->hw_features |= features; |
13650 | tp->dev->vlan_features |= features; | |
027455ad MC |
13651 | } |
13652 | ||
507399f1 | 13653 | /* Determine TSO capabilities */ |
2866d956 | 13654 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
4d163b75 | 13655 | ; /* Do nothing. HW bug. */ |
1407deb1 | 13656 | else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) |
e849cdc3 MC |
13657 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; |
13658 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
13659 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
507399f1 MC |
13660 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; |
13661 | else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
13662 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; | |
13663 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && | |
13664 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
13665 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; | |
13666 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13667 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13668 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
13669 | tp->tg3_flags2 |= TG3_FLG2_TSO_BUG; | |
13670 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | |
13671 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13672 | else | |
13673 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13674 | } | |
13675 | ||
13676 | tp->irq_max = 1; | |
13677 | ||
5a6f3074 | 13678 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7544b097 MC |
13679 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; |
13680 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
13681 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13682 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13683 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13684 | tp->pdev_peer == tp->pdev)) | |
13685 | tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; | |
13686 | ||
321d32a0 | 13687 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
b5d3772c | 13688 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
fcfa0a32 | 13689 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; |
52c0fd83 | 13690 | } |
4f125f42 | 13691 | |
1407deb1 | 13692 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
507399f1 MC |
13693 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; |
13694 | tp->irq_max = TG3_IRQ_MAX_VECS; | |
13695 | } | |
f6eb9b1f | 13696 | } |
0e1406dd | 13697 | |
615774fe | 13698 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
a50d0796 | 13699 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
615774fe MC |
13700 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
13701 | tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG; | |
13702 | else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) { | |
13703 | tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG; | |
13704 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | |
0e1406dd | 13705 | } |
f6eb9b1f | 13706 | |
0a58d668 | 13707 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
de9f5230 MC |
13708 | tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP; |
13709 | ||
1407deb1 | 13710 | if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
2866d956 | 13711 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) |
b703df6f MC |
13712 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; |
13713 | ||
f51f3562 | 13714 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
c6cdf436 MC |
13715 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
13716 | (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG)) | |
8f666b07 | 13717 | tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; |
0f893dc6 | 13718 | |
52f4490c MC |
13719 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13720 | &pci_state_reg); | |
13721 | ||
5e7dfd0f MC |
13722 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); |
13723 | if (tp->pcie_cap != 0) { | |
13724 | u16 lnkctl; | |
13725 | ||
1da177e4 | 13726 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
5f5c51e3 | 13727 | |
cf79003d | 13728 | tp->pcie_readrq = 4096; |
d78b59f5 MC |
13729 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13730 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
b4495ed8 | 13731 | tp->pcie_readrq = 2048; |
cf79003d MC |
13732 | |
13733 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
5f5c51e3 | 13734 | |
5e7dfd0f MC |
13735 | pci_read_config_word(tp->pdev, |
13736 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
13737 | &lnkctl); | |
13738 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
13739 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
c7835a77 | 13740 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; |
5e7dfd0f | 13741 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 13742 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
13743 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
13744 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
5e7dfd0f | 13745 | tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; |
614b0590 MC |
13746 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
13747 | tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN; | |
c7835a77 | 13748 | } |
52f4490c | 13749 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
fcb389df | 13750 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
52f4490c MC |
13751 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
13752 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
13753 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
13754 | if (!tp->pcix_cap) { | |
2445e461 MC |
13755 | dev_err(&tp->pdev->dev, |
13756 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
13757 | return -EIO; |
13758 | } | |
13759 | ||
13760 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
13761 | tp->tg3_flags |= TG3_FLAG_PCIX_MODE; | |
13762 | } | |
1da177e4 | 13763 | |
399de50b MC |
13764 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
13765 | * reordering to the mailbox registers done by the host | |
13766 | * controller can cause major troubles. We read back from | |
13767 | * every mailbox register write to force the writes to be | |
13768 | * posted to the chip in order. | |
13769 | */ | |
4143470c | 13770 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
399de50b MC |
13771 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) |
13772 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
13773 | ||
69fc4053 MC |
13774 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
13775 | &tp->pci_cacheline_sz); | |
13776 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13777 | &tp->pci_lat_timer); | |
1da177e4 LT |
13778 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
13779 | tp->pci_lat_timer < 64) { | |
13780 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
13781 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
13782 | tp->pci_lat_timer); | |
1da177e4 LT |
13783 | } |
13784 | ||
52f4490c MC |
13785 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
13786 | /* 5700 BX chips need to have their TX producer index | |
13787 | * mailboxes written twice to workaround a bug. | |
13788 | */ | |
13789 | tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; | |
1da177e4 | 13790 | |
52f4490c | 13791 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
13792 | * |
13793 | * The workaround is to use indirect register accesses | |
13794 | * for all chip writes not to mailbox registers. | |
13795 | */ | |
52f4490c | 13796 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
1da177e4 | 13797 | u32 pm_reg; |
1da177e4 LT |
13798 | |
13799 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13800 | ||
13801 | /* The chip can have it's power management PCI config | |
13802 | * space registers clobbered due to this bug. | |
13803 | * So explicitly force the chip into D0 here. | |
13804 | */ | |
9974a356 MC |
13805 | pci_read_config_dword(tp->pdev, |
13806 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13807 | &pm_reg); |
13808 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
13809 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
13810 | pci_write_config_dword(tp->pdev, |
13811 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13812 | pm_reg); |
13813 | ||
13814 | /* Also, force SERR#/PERR# in PCI command. */ | |
13815 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13816 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
13817 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13818 | } | |
13819 | } | |
13820 | ||
1da177e4 LT |
13821 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
13822 | tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; | |
13823 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
13824 | tp->tg3_flags |= TG3_FLAG_PCI_32BIT; | |
13825 | ||
13826 | /* Chip-specific fixup from Broadcom driver */ | |
13827 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
13828 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
13829 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
13830 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
13831 | } | |
13832 | ||
1ee582d8 | 13833 | /* Default fast path register access methods */ |
20094930 | 13834 | tp->read32 = tg3_read32; |
1ee582d8 | 13835 | tp->write32 = tg3_write32; |
09ee929c | 13836 | tp->read32_mbox = tg3_read32; |
20094930 | 13837 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
13838 | tp->write32_tx_mbox = tg3_write32; |
13839 | tp->write32_rx_mbox = tg3_write32; | |
13840 | ||
13841 | /* Various workaround register access methods */ | |
13842 | if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) | |
13843 | tp->write32 = tg3_write_indirect_reg32; | |
98efd8a6 MC |
13844 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
13845 | ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
13846 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
13847 | /* | |
13848 | * Back to back register writes can cause problems on these | |
13849 | * chips, the workaround is to read back all reg writes | |
13850 | * except those to mailbox regs. | |
13851 | * | |
13852 | * See tg3_write_indirect_reg32(). | |
13853 | */ | |
1ee582d8 | 13854 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
13855 | } |
13856 | ||
1ee582d8 MC |
13857 | if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || |
13858 | (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { | |
13859 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
13860 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
13861 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
13862 | } | |
20094930 | 13863 | |
6892914f MC |
13864 | if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { |
13865 | tp->read32 = tg3_read_indirect_reg32; | |
13866 | tp->write32 = tg3_write_indirect_reg32; | |
13867 | tp->read32_mbox = tg3_read_indirect_mbox; | |
13868 | tp->write32_mbox = tg3_write_indirect_mbox; | |
13869 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
13870 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
13871 | ||
13872 | iounmap(tp->regs); | |
22abe310 | 13873 | tp->regs = NULL; |
6892914f MC |
13874 | |
13875 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13876 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
13877 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13878 | } | |
b5d3772c MC |
13879 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
13880 | tp->read32_mbox = tg3_read32_mbox_5906; | |
13881 | tp->write32_mbox = tg3_write32_mbox_5906; | |
13882 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
13883 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
13884 | } | |
6892914f | 13885 | |
bbadf503 MC |
13886 | if (tp->write32 == tg3_write_indirect_reg32 || |
13887 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13888 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
f49639e6 | 13889 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
bbadf503 MC |
13890 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; |
13891 | ||
7d0c41ef | 13892 | /* Get eeprom hw config before calling tg3_set_power_state(). |
9d26e213 | 13893 | * In particular, the TG3_FLG2_IS_NIC flag must be |
7d0c41ef MC |
13894 | * determined before calling tg3_set_power_state() so that |
13895 | * we know whether or not to switch out of Vaux power. | |
13896 | * When the flag is set, it means that GPIO1 is used for eeprom | |
13897 | * write protect and also implies that it is a LOM where GPIOs | |
13898 | * are not used to switch power. | |
6aa20a22 | 13899 | */ |
7d0c41ef MC |
13900 | tg3_get_eeprom_hw_cfg(tp); |
13901 | ||
0d3031d9 MC |
13902 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
13903 | /* Allow reads and writes to the | |
13904 | * APE register and memory space. | |
13905 | */ | |
13906 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
13907 | PCISTATE_ALLOW_APE_SHMEM_WR | |
13908 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
13909 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13910 | pci_state_reg); | |
13911 | } | |
13912 | ||
9936bcf6 | 13913 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 13914 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 13915 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13916 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
1407deb1 | 13917 | (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) |
d30cdd28 MC |
13918 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; |
13919 | ||
c866b7ea | 13920 | /* Set up tp->grc_local_ctrl before calling tg_power_up(). |
314fba34 MC |
13921 | * GPIO1 driven high will bring 5700's external PHY out of reset. |
13922 | * It is also used as eeprom write protect on LOMs. | |
13923 | */ | |
13924 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
13925 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13926 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | |
13927 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
13928 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
13929 | /* Unused GPIO3 must be driven as output on 5752 because there |
13930 | * are no pull-up resistors on unused GPIO pins. | |
13931 | */ | |
13932 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
13933 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 13934 | |
321d32a0 | 13935 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd MC |
13936 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
13937 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
af36e6b6 MC |
13938 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
13939 | ||
8d519ab2 MC |
13940 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
13941 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
13942 | /* Turn off the debug UART. */ |
13943 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
13944 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
13945 | /* Keep VMain power. */ | |
13946 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
13947 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
13948 | } | |
13949 | ||
1da177e4 | 13950 | /* Force the chip into D0. */ |
c866b7ea | 13951 | err = tg3_power_up(tp); |
1da177e4 | 13952 | if (err) { |
2445e461 | 13953 | dev_err(&tp->pdev->dev, "Transition to D0 failed\n"); |
1da177e4 LT |
13954 | return err; |
13955 | } | |
13956 | ||
1da177e4 LT |
13957 | /* Derive initial jumbo mode from MTU assigned in |
13958 | * ether_setup() via the alloc_etherdev() call | |
13959 | */ | |
0f893dc6 | 13960 | if (tp->dev->mtu > ETH_DATA_LEN && |
a4e2b347 | 13961 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
0f893dc6 | 13962 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
1da177e4 LT |
13963 | |
13964 | /* Determine WakeOnLan speed to use. */ | |
13965 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13966 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
13967 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
13968 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
13969 | tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); | |
13970 | } else { | |
13971 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | |
13972 | } | |
13973 | ||
7f97a4bd | 13974 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 13975 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 13976 | |
1da177e4 LT |
13977 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
13978 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13979 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
13980 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
747e8f8b | 13981 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
13982 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
13983 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
13984 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
13985 | |
13986 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
13987 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 13988 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 13989 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 13990 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 13991 | |
321d32a0 | 13992 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
f07e9af3 | 13993 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 13994 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 13995 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
1407deb1 | 13996 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
c424cb24 | 13997 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 13998 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
13999 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
14000 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
14001 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
14002 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 14003 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 14004 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 14005 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 14006 | } else |
f07e9af3 | 14007 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 14008 | } |
1da177e4 | 14009 | |
b2a5c19c MC |
14010 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14011 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
14012 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
14013 | if (tp->phy_otp == 0) | |
14014 | tp->phy_otp = TG3_OTP_DEFAULT; | |
14015 | } | |
14016 | ||
f51f3562 | 14017 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) |
8ef21428 MC |
14018 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
14019 | else | |
14020 | tp->mi_mode = MAC_MI_MODE_BASE; | |
14021 | ||
1da177e4 | 14022 | tp->coalesce_mode = 0; |
1da177e4 LT |
14023 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
14024 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
14025 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
14026 | ||
4d958473 MC |
14027 | /* Set these bits to enable statistics workaround. */ |
14028 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | |
14029 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | |
14030 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | |
14031 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | |
14032 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | |
14033 | } | |
14034 | ||
321d32a0 MC |
14035 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
14036 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
57e6983c MC |
14037 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; |
14038 | ||
158d7abd MC |
14039 | err = tg3_mdio_init(tp); |
14040 | if (err) | |
14041 | return err; | |
1da177e4 LT |
14042 | |
14043 | /* Initialize data/descriptor byte/word swapping. */ | |
14044 | val = tr32(GRC_MODE); | |
f2096f94 MC |
14045 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
14046 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | |
14047 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | |
14048 | GRC_MODE_B2HRX_ENABLE | | |
14049 | GRC_MODE_HTX2B_ENABLE | | |
14050 | GRC_MODE_HOST_STACKUP); | |
14051 | else | |
14052 | val &= GRC_MODE_HOST_STACKUP; | |
14053 | ||
1da177e4 LT |
14054 | tw32(GRC_MODE, val | tp->grc_mode); |
14055 | ||
14056 | tg3_switch_clocks(tp); | |
14057 | ||
14058 | /* Clear this out for sanity. */ | |
14059 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14060 | ||
14061 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
14062 | &pci_state_reg); | |
14063 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
14064 | (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { | |
14065 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
14066 | ||
14067 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
14068 | chiprevid == CHIPREV_ID_5701_B0 || | |
14069 | chiprevid == CHIPREV_ID_5701_B2 || | |
14070 | chiprevid == CHIPREV_ID_5701_B5) { | |
14071 | void __iomem *sram_base; | |
14072 | ||
14073 | /* Write some dummy words into the SRAM status block | |
14074 | * area, see if it reads back correctly. If the return | |
14075 | * value is bad, force enable the PCIX workaround. | |
14076 | */ | |
14077 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
14078 | ||
14079 | writel(0x00000000, sram_base); | |
14080 | writel(0x00000000, sram_base + 4); | |
14081 | writel(0xffffffff, sram_base + 4); | |
14082 | if (readl(sram_base) != 0x00000000) | |
14083 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
14084 | } | |
14085 | } | |
14086 | ||
14087 | udelay(50); | |
14088 | tg3_nvram_init(tp); | |
14089 | ||
14090 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
14091 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
14092 | ||
1da177e4 LT |
14093 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
14094 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
14095 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
14096 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | |
14097 | ||
fac9b83e DM |
14098 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && |
14099 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | |
14100 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | |
14101 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
14102 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
14103 | HOSTCC_MODE_CLRTICK_TXBD); | |
14104 | ||
14105 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
14106 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
14107 | tp->misc_host_ctrl); | |
14108 | } | |
14109 | ||
3bda1258 MC |
14110 | /* Preserve the APE MAC_MODE bits */ |
14111 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
d2394e6b | 14112 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
14113 | else |
14114 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
14115 | ||
1da177e4 LT |
14116 | /* these are limited to 10/100 only */ |
14117 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
14118 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
14119 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
14120 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14121 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
14122 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
14123 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
14124 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
14125 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
14126 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
14127 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 14128 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
14129 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
14130 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
14131 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
14132 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
14133 | |
14134 | err = tg3_phy_probe(tp); | |
14135 | if (err) { | |
2445e461 | 14136 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 14137 | /* ... but do not return immediately ... */ |
b02fd9e3 | 14138 | tg3_mdio_fini(tp); |
1da177e4 LT |
14139 | } |
14140 | ||
184b8904 | 14141 | tg3_read_vpd(tp); |
c4e6575c | 14142 | tg3_read_fw_ver(tp); |
1da177e4 | 14143 | |
f07e9af3 MC |
14144 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
14145 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
14146 | } else { |
14147 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 14148 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 14149 | else |
f07e9af3 | 14150 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
14151 | } |
14152 | ||
14153 | /* 5700 {AX,BX} chips have a broken status block link | |
14154 | * change bit implementation, so we must use the | |
14155 | * status register in those cases. | |
14156 | */ | |
14157 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
14158 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
14159 | else | |
14160 | tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; | |
14161 | ||
14162 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
14163 | * have to force the link status polling mechanism based | |
14164 | * upon subsystem IDs. | |
14165 | */ | |
14166 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 14167 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
14168 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
14169 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
14170 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
1da177e4 LT |
14171 | } |
14172 | ||
14173 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 14174 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
14175 | tp->tg3_flags |= TG3_FLAG_POLL_SERDES; |
14176 | else | |
14177 | tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; | |
14178 | ||
bf933c80 | 14179 | tp->rx_offset = NET_IP_ALIGN; |
d2757fc4 | 14180 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 14181 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
d2757fc4 | 14182 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { |
bf933c80 | 14183 | tp->rx_offset = 0; |
d2757fc4 | 14184 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 14185 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
14186 | #endif |
14187 | } | |
1da177e4 | 14188 | |
2c49a44d MC |
14189 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
14190 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
14191 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
14192 | ||
2c49a44d | 14193 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
14194 | |
14195 | /* Increment the rx prod index on the rx std ring by at most | |
14196 | * 8 for these chips to workaround hw errata. | |
14197 | */ | |
14198 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14199 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14200 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14201 | tp->rx_std_max_post = 8; | |
14202 | ||
8ed5d97e MC |
14203 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) |
14204 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
14205 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14206 | ||
1da177e4 LT |
14207 | return err; |
14208 | } | |
14209 | ||
49b6e95f | 14210 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14211 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
14212 | { | |
14213 | struct net_device *dev = tp->dev; | |
14214 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 14215 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 14216 | const unsigned char *addr; |
49b6e95f DM |
14217 | int len; |
14218 | ||
14219 | addr = of_get_property(dp, "local-mac-address", &len); | |
14220 | if (addr && len == 6) { | |
14221 | memcpy(dev->dev_addr, addr, 6); | |
14222 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14223 | return 0; | |
1da177e4 LT |
14224 | } |
14225 | return -ENODEV; | |
14226 | } | |
14227 | ||
14228 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14229 | { | |
14230 | struct net_device *dev = tp->dev; | |
14231 | ||
14232 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 14233 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
14234 | return 0; |
14235 | } | |
14236 | #endif | |
14237 | ||
14238 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14239 | { | |
14240 | struct net_device *dev = tp->dev; | |
14241 | u32 hi, lo, mac_offset; | |
008652b3 | 14242 | int addr_ok = 0; |
1da177e4 | 14243 | |
49b6e95f | 14244 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14245 | if (!tg3_get_macaddr_sparc(tp)) |
14246 | return 0; | |
14247 | #endif | |
14248 | ||
14249 | mac_offset = 0x7c; | |
f49639e6 | 14250 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
a4e2b347 | 14251 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
14252 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
14253 | mac_offset = 0xcc; | |
14254 | if (tg3_nvram_lock(tp)) | |
14255 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14256 | else | |
14257 | tg3_nvram_unlock(tp); | |
0a58d668 | 14258 | } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
a50d0796 | 14259 | if (PCI_FUNC(tp->pdev->devfn) & 1) |
a1b950d5 | 14260 | mac_offset = 0xcc; |
a50d0796 MC |
14261 | if (PCI_FUNC(tp->pdev->devfn) > 1) |
14262 | mac_offset += 0x18c; | |
a1b950d5 | 14263 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 14264 | mac_offset = 0x10; |
1da177e4 LT |
14265 | |
14266 | /* First try to get it from MAC address mailbox. */ | |
14267 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14268 | if ((hi >> 16) == 0x484b) { | |
14269 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14270 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14271 | ||
14272 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14273 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14274 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14275 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14276 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 14277 | |
008652b3 MC |
14278 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
14279 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14280 | } | |
14281 | if (!addr_ok) { | |
14282 | /* Next, try NVRAM. */ | |
df259d8c MC |
14283 | if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && |
14284 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && | |
6d348f2c | 14285 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
14286 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
14287 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
14288 | } |
14289 | /* Finally just fetch it out of the MAC control regs. */ | |
14290 | else { | |
14291 | hi = tr32(MAC_ADDR_0_HIGH); | |
14292 | lo = tr32(MAC_ADDR_0_LOW); | |
14293 | ||
14294 | dev->dev_addr[5] = lo & 0xff; | |
14295 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14296 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14297 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14298 | dev->dev_addr[1] = hi & 0xff; | |
14299 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14300 | } | |
1da177e4 LT |
14301 | } |
14302 | ||
14303 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 14304 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14305 | if (!tg3_get_default_macaddr_sparc(tp)) |
14306 | return 0; | |
14307 | #endif | |
14308 | return -EINVAL; | |
14309 | } | |
2ff43697 | 14310 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
14311 | return 0; |
14312 | } | |
14313 | ||
59e6b434 DM |
14314 | #define BOUNDARY_SINGLE_CACHELINE 1 |
14315 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14316 | ||
14317 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14318 | { | |
14319 | int cacheline_size; | |
14320 | u8 byte; | |
14321 | int goal; | |
14322 | ||
14323 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14324 | if (byte == 0) | |
14325 | cacheline_size = 1024; | |
14326 | else | |
14327 | cacheline_size = (int) byte * 4; | |
14328 | ||
14329 | /* On 5703 and later chips, the boundary bits have no | |
14330 | * effect. | |
14331 | */ | |
14332 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14333 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
14334 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
14335 | goto out; | |
14336 | ||
14337 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14338 | goal = BOUNDARY_MULTI_CACHELINE; | |
14339 | #else | |
14340 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14341 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14342 | #else | |
14343 | goal = 0; | |
14344 | #endif | |
14345 | #endif | |
14346 | ||
1407deb1 | 14347 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
cbf9ca6c MC |
14348 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
14349 | goto out; | |
14350 | } | |
14351 | ||
59e6b434 DM |
14352 | if (!goal) |
14353 | goto out; | |
14354 | ||
14355 | /* PCI controllers on most RISC systems tend to disconnect | |
14356 | * when a device tries to burst across a cache-line boundary. | |
14357 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14358 | * | |
14359 | * Unfortunately, for PCI-E there are only limited | |
14360 | * write-side controls for this, and thus for reads | |
14361 | * we will still get the disconnects. We'll also waste | |
14362 | * these PCI cycles for both read and write for chips | |
14363 | * other than 5700 and 5701 which do not implement the | |
14364 | * boundary bits. | |
14365 | */ | |
14366 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
14367 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
14368 | switch (cacheline_size) { | |
14369 | case 16: | |
14370 | case 32: | |
14371 | case 64: | |
14372 | case 128: | |
14373 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14374 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14375 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14376 | } else { | |
14377 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14378 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14379 | } | |
14380 | break; | |
14381 | ||
14382 | case 256: | |
14383 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14384 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14385 | break; | |
14386 | ||
14387 | default: | |
14388 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14389 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14390 | break; | |
855e1111 | 14391 | } |
59e6b434 DM |
14392 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
14393 | switch (cacheline_size) { | |
14394 | case 16: | |
14395 | case 32: | |
14396 | case 64: | |
14397 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14398 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14399 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14400 | break; | |
14401 | } | |
14402 | /* fallthrough */ | |
14403 | case 128: | |
14404 | default: | |
14405 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14406 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14407 | break; | |
855e1111 | 14408 | } |
59e6b434 DM |
14409 | } else { |
14410 | switch (cacheline_size) { | |
14411 | case 16: | |
14412 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14413 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14414 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14415 | break; | |
14416 | } | |
14417 | /* fallthrough */ | |
14418 | case 32: | |
14419 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14420 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14421 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14422 | break; | |
14423 | } | |
14424 | /* fallthrough */ | |
14425 | case 64: | |
14426 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14427 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14428 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14429 | break; | |
14430 | } | |
14431 | /* fallthrough */ | |
14432 | case 128: | |
14433 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14434 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14435 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14436 | break; | |
14437 | } | |
14438 | /* fallthrough */ | |
14439 | case 256: | |
14440 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14441 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14442 | break; | |
14443 | case 512: | |
14444 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14445 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14446 | break; | |
14447 | case 1024: | |
14448 | default: | |
14449 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14450 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14451 | break; | |
855e1111 | 14452 | } |
59e6b434 DM |
14453 | } |
14454 | ||
14455 | out: | |
14456 | return val; | |
14457 | } | |
14458 | ||
1da177e4 LT |
14459 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
14460 | { | |
14461 | struct tg3_internal_buffer_desc test_desc; | |
14462 | u32 sram_dma_descs; | |
14463 | int i, ret; | |
14464 | ||
14465 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14466 | ||
14467 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14468 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14469 | tw32(RDMAC_STATUS, 0); | |
14470 | tw32(WDMAC_STATUS, 0); | |
14471 | ||
14472 | tw32(BUFMGR_MODE, 0); | |
14473 | tw32(FTQ_RESET, 0); | |
14474 | ||
14475 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14476 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14477 | test_desc.nic_mbuf = 0x00002100; | |
14478 | test_desc.len = size; | |
14479 | ||
14480 | /* | |
14481 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14482 | * the *second* time the tg3 driver was getting loaded after an | |
14483 | * initial scan. | |
14484 | * | |
14485 | * Broadcom tells me: | |
14486 | * ...the DMA engine is connected to the GRC block and a DMA | |
14487 | * reset may affect the GRC block in some unpredictable way... | |
14488 | * The behavior of resets to individual blocks has not been tested. | |
14489 | * | |
14490 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14491 | */ | |
14492 | if (to_device) { | |
14493 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14494 | ||
14495 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14496 | udelay(40); | |
14497 | } else { | |
14498 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14499 | ||
14500 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14501 | udelay(40); | |
14502 | } | |
14503 | test_desc.flags = 0x00000005; | |
14504 | ||
14505 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14506 | u32 val; | |
14507 | ||
14508 | val = *(((u32 *)&test_desc) + i); | |
14509 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14510 | sram_dma_descs + (i * sizeof(u32))); | |
14511 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14512 | } | |
14513 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14514 | ||
859a5887 | 14515 | if (to_device) |
1da177e4 | 14516 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 14517 | else |
1da177e4 | 14518 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
14519 | |
14520 | ret = -ENODEV; | |
14521 | for (i = 0; i < 40; i++) { | |
14522 | u32 val; | |
14523 | ||
14524 | if (to_device) | |
14525 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14526 | else | |
14527 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14528 | if ((val & 0xffff) == sram_dma_descs) { | |
14529 | ret = 0; | |
14530 | break; | |
14531 | } | |
14532 | ||
14533 | udelay(100); | |
14534 | } | |
14535 | ||
14536 | return ret; | |
14537 | } | |
14538 | ||
ded7340d | 14539 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 14540 | |
4143470c | 14541 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
14542 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
14543 | { }, | |
14544 | }; | |
14545 | ||
1da177e4 LT |
14546 | static int __devinit tg3_test_dma(struct tg3 *tp) |
14547 | { | |
14548 | dma_addr_t buf_dma; | |
59e6b434 | 14549 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 14550 | int ret = 0; |
1da177e4 | 14551 | |
4bae65c8 MC |
14552 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
14553 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
14554 | if (!buf) { |
14555 | ret = -ENOMEM; | |
14556 | goto out_nofree; | |
14557 | } | |
14558 | ||
14559 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14560 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14561 | ||
59e6b434 | 14562 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 14563 | |
1407deb1 | 14564 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) |
cbf9ca6c MC |
14565 | goto out; |
14566 | ||
1da177e4 LT |
14567 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
14568 | /* DMA read watermark not used on PCIE */ | |
14569 | tp->dma_rwctrl |= 0x00180000; | |
14570 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
85e94ced MC |
14571 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
14572 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
14573 | tp->dma_rwctrl |= 0x003f0000; |
14574 | else | |
14575 | tp->dma_rwctrl |= 0x003f000f; | |
14576 | } else { | |
14577 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14578 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14579 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 14580 | u32 read_water = 0x7; |
1da177e4 | 14581 | |
4a29cc2e MC |
14582 | /* If the 5704 is behind the EPB bridge, we can |
14583 | * do the less restrictive ONE_DMA workaround for | |
14584 | * better performance. | |
14585 | */ | |
14586 | if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && | |
14587 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14588 | tp->dma_rwctrl |= 0x8000; | |
14589 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
14590 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
14591 | ||
49afdeb6 MC |
14592 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
14593 | read_water = 4; | |
59e6b434 | 14594 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
14595 | tp->dma_rwctrl |= |
14596 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14597 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14598 | (1 << 23); | |
4cf78e4f MC |
14599 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
14600 | /* 5780 always in PCIX mode */ | |
14601 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
14602 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
14603 | /* 5714 always in PCIX mode */ | |
14604 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
14605 | } else { |
14606 | tp->dma_rwctrl |= 0x001b000f; | |
14607 | } | |
14608 | } | |
14609 | ||
14610 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14611 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14612 | tp->dma_rwctrl &= 0xfffffff0; | |
14613 | ||
14614 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14615 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14616 | /* Remove this if it causes problems for some boards. */ | |
14617 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14618 | ||
14619 | /* On 5700/5701 chips, we need to set this bit. | |
14620 | * Otherwise the chip will issue cacheline transactions | |
14621 | * to streamable DMA memory with not all the byte | |
14622 | * enables turned on. This is an error on several | |
14623 | * RISC PCI controllers, in particular sparc64. | |
14624 | * | |
14625 | * On 5703/5704 chips, this bit has been reassigned | |
14626 | * a different meaning. In particular, it is used | |
14627 | * on those chips to enable a PCI-X workaround. | |
14628 | */ | |
14629 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14630 | } | |
14631 | ||
14632 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14633 | ||
14634 | #if 0 | |
14635 | /* Unneeded, already done by tg3_get_invariants. */ | |
14636 | tg3_switch_clocks(tp); | |
14637 | #endif | |
14638 | ||
1da177e4 LT |
14639 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14640 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14641 | goto out; | |
14642 | ||
59e6b434 DM |
14643 | /* It is best to perform DMA test with maximum write burst size |
14644 | * to expose the 5700/5701 write DMA bug. | |
14645 | */ | |
14646 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14647 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14648 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14649 | ||
1da177e4 LT |
14650 | while (1) { |
14651 | u32 *p = buf, i; | |
14652 | ||
14653 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14654 | p[i] = i; | |
14655 | ||
14656 | /* Send the buffer to the chip. */ | |
14657 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
14658 | if (ret) { | |
2445e461 MC |
14659 | dev_err(&tp->pdev->dev, |
14660 | "%s: Buffer write failed. err = %d\n", | |
14661 | __func__, ret); | |
1da177e4 LT |
14662 | break; |
14663 | } | |
14664 | ||
14665 | #if 0 | |
14666 | /* validate data reached card RAM correctly. */ | |
14667 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14668 | u32 val; | |
14669 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
14670 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
14671 | dev_err(&tp->pdev->dev, |
14672 | "%s: Buffer corrupted on device! " | |
14673 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
14674 | /* ret = -ENODEV here? */ |
14675 | } | |
14676 | p[i] = 0; | |
14677 | } | |
14678 | #endif | |
14679 | /* Now read it back. */ | |
14680 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
14681 | if (ret) { | |
5129c3a3 MC |
14682 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
14683 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
14684 | break; |
14685 | } | |
14686 | ||
14687 | /* Verify it. */ | |
14688 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14689 | if (p[i] == i) | |
14690 | continue; | |
14691 | ||
59e6b434 DM |
14692 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14693 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14694 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
14695 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
14696 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14697 | break; | |
14698 | } else { | |
2445e461 MC |
14699 | dev_err(&tp->pdev->dev, |
14700 | "%s: Buffer corrupted on read back! " | |
14701 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
14702 | ret = -ENODEV; |
14703 | goto out; | |
14704 | } | |
14705 | } | |
14706 | ||
14707 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14708 | /* Success. */ | |
14709 | ret = 0; | |
14710 | break; | |
14711 | } | |
14712 | } | |
59e6b434 DM |
14713 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14714 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
6d1cfbab | 14715 | |
59e6b434 | 14716 | /* DMA test passed without adjusting DMA boundary, |
6d1cfbab MC |
14717 | * now look for chipsets that are known to expose the |
14718 | * DMA bug without failing the test. | |
59e6b434 | 14719 | */ |
4143470c | 14720 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
14721 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
14722 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 14723 | } else { |
6d1cfbab MC |
14724 | /* Safe to use the calculated DMA boundary. */ |
14725 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 14726 | } |
6d1cfbab | 14727 | |
59e6b434 DM |
14728 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
14729 | } | |
1da177e4 LT |
14730 | |
14731 | out: | |
4bae65c8 | 14732 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
14733 | out_nofree: |
14734 | return ret; | |
14735 | } | |
14736 | ||
1da177e4 LT |
14737 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
14738 | { | |
1407deb1 | 14739 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
666bc831 MC |
14740 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14741 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14742 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14743 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14744 | tp->bufmgr_config.mbuf_high_water = | |
14745 | DEFAULT_MB_HIGH_WATER_57765; | |
14746 | ||
14747 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14748 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14749 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14750 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14751 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14752 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
14753 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
fdfec172 MC |
14754 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14755 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14756 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14757 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14758 | tp->bufmgr_config.mbuf_high_water = | |
14759 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
14760 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14761 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14762 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14763 | tp->bufmgr_config.mbuf_high_water = | |
14764 | DEFAULT_MB_HIGH_WATER_5906; | |
14765 | } | |
fdfec172 MC |
14766 | |
14767 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14768 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
14769 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14770 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
14771 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14772 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
14773 | } else { | |
14774 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14775 | DEFAULT_MB_RDMA_LOW_WATER; | |
14776 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14777 | DEFAULT_MB_MACRX_LOW_WATER; | |
14778 | tp->bufmgr_config.mbuf_high_water = | |
14779 | DEFAULT_MB_HIGH_WATER; | |
14780 | ||
14781 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14782 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
14783 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14784 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
14785 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14786 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
14787 | } | |
1da177e4 LT |
14788 | |
14789 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
14790 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
14791 | } | |
14792 | ||
14793 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
14794 | { | |
79eb6904 MC |
14795 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
14796 | case TG3_PHY_ID_BCM5400: return "5400"; | |
14797 | case TG3_PHY_ID_BCM5401: return "5401"; | |
14798 | case TG3_PHY_ID_BCM5411: return "5411"; | |
14799 | case TG3_PHY_ID_BCM5701: return "5701"; | |
14800 | case TG3_PHY_ID_BCM5703: return "5703"; | |
14801 | case TG3_PHY_ID_BCM5704: return "5704"; | |
14802 | case TG3_PHY_ID_BCM5705: return "5705"; | |
14803 | case TG3_PHY_ID_BCM5750: return "5750"; | |
14804 | case TG3_PHY_ID_BCM5752: return "5752"; | |
14805 | case TG3_PHY_ID_BCM5714: return "5714"; | |
14806 | case TG3_PHY_ID_BCM5780: return "5780"; | |
14807 | case TG3_PHY_ID_BCM5755: return "5755"; | |
14808 | case TG3_PHY_ID_BCM5787: return "5787"; | |
14809 | case TG3_PHY_ID_BCM5784: return "5784"; | |
14810 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
14811 | case TG3_PHY_ID_BCM5906: return "5906"; | |
14812 | case TG3_PHY_ID_BCM5761: return "5761"; | |
14813 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
14814 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
14815 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 14816 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
6418f2c1 | 14817 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
79eb6904 | 14818 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
14819 | case 0: return "serdes"; |
14820 | default: return "unknown"; | |
855e1111 | 14821 | } |
1da177e4 LT |
14822 | } |
14823 | ||
f9804ddb MC |
14824 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
14825 | { | |
14826 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
14827 | strcpy(str, "PCI Express"); | |
14828 | return str; | |
14829 | } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
14830 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
14831 | ||
14832 | strcpy(str, "PCIX:"); | |
14833 | ||
14834 | if ((clock_ctrl == 7) || | |
14835 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
14836 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
14837 | strcat(str, "133MHz"); | |
14838 | else if (clock_ctrl == 0) | |
14839 | strcat(str, "33MHz"); | |
14840 | else if (clock_ctrl == 2) | |
14841 | strcat(str, "50MHz"); | |
14842 | else if (clock_ctrl == 4) | |
14843 | strcat(str, "66MHz"); | |
14844 | else if (clock_ctrl == 6) | |
14845 | strcat(str, "100MHz"); | |
f9804ddb MC |
14846 | } else { |
14847 | strcpy(str, "PCI:"); | |
14848 | if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) | |
14849 | strcat(str, "66MHz"); | |
14850 | else | |
14851 | strcat(str, "33MHz"); | |
14852 | } | |
14853 | if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) | |
14854 | strcat(str, ":32-bit"); | |
14855 | else | |
14856 | strcat(str, ":64-bit"); | |
14857 | return str; | |
14858 | } | |
14859 | ||
8c2dc7e1 | 14860 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
14861 | { |
14862 | struct pci_dev *peer; | |
14863 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14864 | ||
14865 | for (func = 0; func < 8; func++) { | |
14866 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14867 | if (peer && peer != tp->pdev) | |
14868 | break; | |
14869 | pci_dev_put(peer); | |
14870 | } | |
16fe9d74 MC |
14871 | /* 5704 can be configured in single-port mode, set peer to |
14872 | * tp->pdev in that case. | |
14873 | */ | |
14874 | if (!peer) { | |
14875 | peer = tp->pdev; | |
14876 | return peer; | |
14877 | } | |
1da177e4 LT |
14878 | |
14879 | /* | |
14880 | * We don't need to keep the refcount elevated; there's no way | |
14881 | * to remove one half of this device without removing the other | |
14882 | */ | |
14883 | pci_dev_put(peer); | |
14884 | ||
14885 | return peer; | |
14886 | } | |
14887 | ||
15f9850d DM |
14888 | static void __devinit tg3_init_coal(struct tg3 *tp) |
14889 | { | |
14890 | struct ethtool_coalesce *ec = &tp->coal; | |
14891 | ||
14892 | memset(ec, 0, sizeof(*ec)); | |
14893 | ec->cmd = ETHTOOL_GCOALESCE; | |
14894 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
14895 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
14896 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
14897 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
14898 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
14899 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
14900 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
14901 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
14902 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
14903 | ||
14904 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
14905 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
14906 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
14907 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
14908 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
14909 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
14910 | } | |
d244c892 MC |
14911 | |
14912 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
14913 | ec->rx_coalesce_usecs_irq = 0; | |
14914 | ec->tx_coalesce_usecs_irq = 0; | |
14915 | ec->stats_block_coalesce_usecs = 0; | |
14916 | } | |
15f9850d DM |
14917 | } |
14918 | ||
7c7d64b8 SH |
14919 | static const struct net_device_ops tg3_netdev_ops = { |
14920 | .ndo_open = tg3_open, | |
14921 | .ndo_stop = tg3_close, | |
00829823 | 14922 | .ndo_start_xmit = tg3_start_xmit, |
511d2224 | 14923 | .ndo_get_stats64 = tg3_get_stats64, |
00829823 SH |
14924 | .ndo_validate_addr = eth_validate_addr, |
14925 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14926 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14927 | .ndo_do_ioctl = tg3_ioctl, | |
14928 | .ndo_tx_timeout = tg3_tx_timeout, | |
14929 | .ndo_change_mtu = tg3_change_mtu, | |
dc668910 | 14930 | .ndo_fix_features = tg3_fix_features, |
00829823 SH |
14931 | #ifdef CONFIG_NET_POLL_CONTROLLER |
14932 | .ndo_poll_controller = tg3_poll_controller, | |
14933 | #endif | |
14934 | }; | |
14935 | ||
14936 | static const struct net_device_ops tg3_netdev_ops_dma_bug = { | |
14937 | .ndo_open = tg3_open, | |
14938 | .ndo_stop = tg3_close, | |
14939 | .ndo_start_xmit = tg3_start_xmit_dma_bug, | |
511d2224 | 14940 | .ndo_get_stats64 = tg3_get_stats64, |
7c7d64b8 SH |
14941 | .ndo_validate_addr = eth_validate_addr, |
14942 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14943 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14944 | .ndo_do_ioctl = tg3_ioctl, | |
14945 | .ndo_tx_timeout = tg3_tx_timeout, | |
14946 | .ndo_change_mtu = tg3_change_mtu, | |
7c7d64b8 SH |
14947 | #ifdef CONFIG_NET_POLL_CONTROLLER |
14948 | .ndo_poll_controller = tg3_poll_controller, | |
14949 | #endif | |
14950 | }; | |
14951 | ||
1da177e4 LT |
14952 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
14953 | const struct pci_device_id *ent) | |
14954 | { | |
1da177e4 LT |
14955 | struct net_device *dev; |
14956 | struct tg3 *tp; | |
646c9edd MC |
14957 | int i, err, pm_cap; |
14958 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 14959 | char str[40]; |
72f2afb8 | 14960 | u64 dma_mask, persist_dma_mask; |
dc668910 | 14961 | u32 hw_features = 0; |
1da177e4 | 14962 | |
05dbe005 | 14963 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
14964 | |
14965 | err = pci_enable_device(pdev); | |
14966 | if (err) { | |
2445e461 | 14967 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
14968 | return err; |
14969 | } | |
14970 | ||
1da177e4 LT |
14971 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
14972 | if (err) { | |
2445e461 | 14973 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
14974 | goto err_out_disable_pdev; |
14975 | } | |
14976 | ||
14977 | pci_set_master(pdev); | |
14978 | ||
14979 | /* Find power-management capability. */ | |
14980 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
14981 | if (pm_cap == 0) { | |
2445e461 MC |
14982 | dev_err(&pdev->dev, |
14983 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
14984 | err = -EIO; |
14985 | goto err_out_free_res; | |
14986 | } | |
14987 | ||
fe5f5787 | 14988 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 14989 | if (!dev) { |
2445e461 | 14990 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 LT |
14991 | err = -ENOMEM; |
14992 | goto err_out_free_res; | |
14993 | } | |
14994 | ||
1da177e4 LT |
14995 | SET_NETDEV_DEV(dev, &pdev->dev); |
14996 | ||
1da177e4 | 14997 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
1da177e4 LT |
14998 | |
14999 | tp = netdev_priv(dev); | |
15000 | tp->pdev = pdev; | |
15001 | tp->dev = dev; | |
15002 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
15003 | tp->rx_mode = TG3_DEF_RX_MODE; |
15004 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 15005 | |
1da177e4 LT |
15006 | if (tg3_debug > 0) |
15007 | tp->msg_enable = tg3_debug; | |
15008 | else | |
15009 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
15010 | ||
15011 | /* The word/byte swap controls here control register access byte | |
15012 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
15013 | * setting below. | |
15014 | */ | |
15015 | tp->misc_host_ctrl = | |
15016 | MISC_HOST_CTRL_MASK_PCI_INT | | |
15017 | MISC_HOST_CTRL_WORD_SWAP | | |
15018 | MISC_HOST_CTRL_INDIR_ACCESS | | |
15019 | MISC_HOST_CTRL_PCISTATE_RW; | |
15020 | ||
15021 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
15022 | * on descriptor entries, anything which isn't packet data. | |
15023 | * | |
15024 | * The StrongARM chips on the board (one for tx, one for rx) | |
15025 | * are running in big-endian mode. | |
15026 | */ | |
15027 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
15028 | GRC_MODE_WSWAP_NONFRM_DATA); | |
15029 | #ifdef __BIG_ENDIAN | |
15030 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
15031 | #endif | |
15032 | spin_lock_init(&tp->lock); | |
1da177e4 | 15033 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 15034 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 15035 | |
d5fe488a | 15036 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 15037 | if (!tp->regs) { |
ab96b241 | 15038 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
15039 | err = -ENOMEM; |
15040 | goto err_out_free_dev; | |
15041 | } | |
15042 | ||
1da177e4 LT |
15043 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
15044 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 15045 | |
1da177e4 | 15046 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 15047 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
1da177e4 | 15048 | dev->irq = pdev->irq; |
1da177e4 LT |
15049 | |
15050 | err = tg3_get_invariants(tp); | |
15051 | if (err) { | |
ab96b241 MC |
15052 | dev_err(&pdev->dev, |
15053 | "Problem fetching invariants of chip, aborting\n"); | |
1da177e4 LT |
15054 | goto err_out_iounmap; |
15055 | } | |
15056 | ||
615774fe | 15057 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && |
0a58d668 | 15058 | !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
00829823 SH |
15059 | dev->netdev_ops = &tg3_netdev_ops; |
15060 | else | |
15061 | dev->netdev_ops = &tg3_netdev_ops_dma_bug; | |
15062 | ||
15063 | ||
4a29cc2e MC |
15064 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
15065 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
15066 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
15067 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
15068 | * do DMA address check in tg3_start_xmit(). | |
15069 | */ | |
4a29cc2e | 15070 | if (tp->tg3_flags2 & TG3_FLG2_IS_5788) |
284901a9 | 15071 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
4a29cc2e | 15072 | else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { |
50cf156a | 15073 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 15074 | #ifdef CONFIG_HIGHMEM |
6a35528a | 15075 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 15076 | #endif |
4a29cc2e | 15077 | } else |
6a35528a | 15078 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
15079 | |
15080 | /* Configure DMA attributes. */ | |
284901a9 | 15081 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
15082 | err = pci_set_dma_mask(pdev, dma_mask); |
15083 | if (!err) { | |
15084 | dev->features |= NETIF_F_HIGHDMA; | |
15085 | err = pci_set_consistent_dma_mask(pdev, | |
15086 | persist_dma_mask); | |
15087 | if (err < 0) { | |
ab96b241 MC |
15088 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
15089 | "DMA for consistent allocations\n"); | |
72f2afb8 MC |
15090 | goto err_out_iounmap; |
15091 | } | |
15092 | } | |
15093 | } | |
284901a9 YH |
15094 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
15095 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 15096 | if (err) { |
ab96b241 MC |
15097 | dev_err(&pdev->dev, |
15098 | "No usable DMA configuration, aborting\n"); | |
72f2afb8 MC |
15099 | goto err_out_iounmap; |
15100 | } | |
15101 | } | |
15102 | ||
fdfec172 | 15103 | tg3_init_bufmgr_config(tp); |
1da177e4 | 15104 | |
507399f1 MC |
15105 | /* Selectively allow TSO based on operating conditions */ |
15106 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || | |
15107 | (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) | |
1da177e4 | 15108 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
507399f1 MC |
15109 | else { |
15110 | tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG); | |
15111 | tp->fw_needed = NULL; | |
1da177e4 | 15112 | } |
507399f1 MC |
15113 | |
15114 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
15115 | tp->fw_needed = FIRMWARE_TG3; | |
1da177e4 | 15116 | |
4e3a7aaa MC |
15117 | /* TSO is on by default on chips that support hardware TSO. |
15118 | * Firmware TSO on older chips gives lower performance, so it | |
15119 | * is off by default, but can be enabled using ethtool. | |
15120 | */ | |
e849cdc3 | 15121 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) && |
dc668910 MM |
15122 | (dev->features & NETIF_F_IP_CSUM)) |
15123 | hw_features |= NETIF_F_TSO; | |
e849cdc3 MC |
15124 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || |
15125 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) { | |
dc668910 MM |
15126 | if (dev->features & NETIF_F_IPV6_CSUM) |
15127 | hw_features |= NETIF_F_TSO6; | |
e849cdc3 MC |
15128 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
15129 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
15130 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
15131 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 15132 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
dc668910 MM |
15133 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
15134 | hw_features |= NETIF_F_TSO_ECN; | |
b0026624 | 15135 | } |
1da177e4 | 15136 | |
dc668910 MM |
15137 | dev->hw_features |= hw_features; |
15138 | dev->features |= hw_features; | |
15139 | dev->vlan_features |= hw_features; | |
15140 | ||
1da177e4 LT |
15141 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
15142 | !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
15143 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
15144 | tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; | |
15145 | tp->rx_pending = 63; | |
15146 | } | |
15147 | ||
1da177e4 LT |
15148 | err = tg3_get_device_address(tp); |
15149 | if (err) { | |
ab96b241 MC |
15150 | dev_err(&pdev->dev, |
15151 | "Could not obtain valid ethernet address, aborting\n"); | |
026a6c21 | 15152 | goto err_out_iounmap; |
1da177e4 LT |
15153 | } |
15154 | ||
c88864df | 15155 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
63532394 | 15156 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); |
79ea13ce | 15157 | if (!tp->aperegs) { |
ab96b241 MC |
15158 | dev_err(&pdev->dev, |
15159 | "Cannot map APE registers, aborting\n"); | |
c88864df | 15160 | err = -ENOMEM; |
026a6c21 | 15161 | goto err_out_iounmap; |
c88864df MC |
15162 | } |
15163 | ||
15164 | tg3_ape_lock_init(tp); | |
7fd76445 MC |
15165 | |
15166 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
15167 | tg3_read_dash_ver(tp); | |
c88864df MC |
15168 | } |
15169 | ||
1da177e4 LT |
15170 | /* |
15171 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15172 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15173 | * pending DMA on the PCI bus at that point. | |
15174 | */ | |
15175 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15176 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 15177 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 15178 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
15179 | } |
15180 | ||
15181 | err = tg3_test_dma(tp); | |
15182 | if (err) { | |
ab96b241 | 15183 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 15184 | goto err_out_apeunmap; |
1da177e4 LT |
15185 | } |
15186 | ||
78f90dcf MC |
15187 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
15188 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15189 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 15190 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
15191 | struct tg3_napi *tnapi = &tp->napi[i]; |
15192 | ||
15193 | tnapi->tp = tp; | |
15194 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15195 | ||
15196 | tnapi->int_mbox = intmbx; | |
15197 | if (i < 4) | |
15198 | intmbx += 0x8; | |
15199 | else | |
15200 | intmbx += 0x4; | |
15201 | ||
15202 | tnapi->consmbox = rcvmbx; | |
15203 | tnapi->prodmbox = sndmbx; | |
15204 | ||
66cfd1bd | 15205 | if (i) |
78f90dcf | 15206 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 15207 | else |
78f90dcf | 15208 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf MC |
15209 | |
15210 | if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)) | |
15211 | break; | |
15212 | ||
15213 | /* | |
15214 | * If we support MSIX, we'll be using RSS. If we're using | |
15215 | * RSS, the first vector only handles link interrupts and the | |
15216 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15217 | * mailbox values for the next iteration. The values we setup | |
15218 | * above are still useful for the single vectored mode. | |
15219 | */ | |
15220 | if (!i) | |
15221 | continue; | |
15222 | ||
15223 | rcvmbx += 0x8; | |
15224 | ||
15225 | if (sndmbx & 0x4) | |
15226 | sndmbx -= 0x4; | |
15227 | else | |
15228 | sndmbx += 0xc; | |
15229 | } | |
15230 | ||
15f9850d DM |
15231 | tg3_init_coal(tp); |
15232 | ||
c49a1561 MC |
15233 | pci_set_drvdata(pdev, dev); |
15234 | ||
1da177e4 LT |
15235 | err = register_netdev(dev); |
15236 | if (err) { | |
ab96b241 | 15237 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 15238 | goto err_out_apeunmap; |
1da177e4 LT |
15239 | } |
15240 | ||
05dbe005 JP |
15241 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
15242 | tp->board_part_number, | |
15243 | tp->pci_chip_rev_id, | |
15244 | tg3_bus_string(tp, str), | |
15245 | dev->dev_addr); | |
1da177e4 | 15246 | |
f07e9af3 | 15247 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
15248 | struct phy_device *phydev; |
15249 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
15250 | netdev_info(dev, |
15251 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 15252 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
15253 | } else { |
15254 | char *ethtype; | |
15255 | ||
15256 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15257 | ethtype = "10/100Base-TX"; | |
15258 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15259 | ethtype = "1000Base-SX"; | |
15260 | else | |
15261 | ethtype = "10/100/1000Base-T"; | |
15262 | ||
5129c3a3 | 15263 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
f07e9af3 MC |
15264 | "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype, |
15265 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0); | |
15266 | } | |
05dbe005 JP |
15267 | |
15268 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
dc668910 | 15269 | (dev->features & NETIF_F_RXCSUM) != 0, |
05dbe005 | 15270 | (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, |
f07e9af3 | 15271 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
05dbe005 JP |
15272 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, |
15273 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); | |
15274 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", | |
15275 | tp->dma_rwctrl, | |
15276 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15277 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 LT |
15278 | |
15279 | return 0; | |
15280 | ||
0d3031d9 MC |
15281 | err_out_apeunmap: |
15282 | if (tp->aperegs) { | |
15283 | iounmap(tp->aperegs); | |
15284 | tp->aperegs = NULL; | |
15285 | } | |
15286 | ||
1da177e4 | 15287 | err_out_iounmap: |
6892914f MC |
15288 | if (tp->regs) { |
15289 | iounmap(tp->regs); | |
22abe310 | 15290 | tp->regs = NULL; |
6892914f | 15291 | } |
1da177e4 LT |
15292 | |
15293 | err_out_free_dev: | |
15294 | free_netdev(dev); | |
15295 | ||
15296 | err_out_free_res: | |
15297 | pci_release_regions(pdev); | |
15298 | ||
15299 | err_out_disable_pdev: | |
15300 | pci_disable_device(pdev); | |
15301 | pci_set_drvdata(pdev, NULL); | |
15302 | return err; | |
15303 | } | |
15304 | ||
15305 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15306 | { | |
15307 | struct net_device *dev = pci_get_drvdata(pdev); | |
15308 | ||
15309 | if (dev) { | |
15310 | struct tg3 *tp = netdev_priv(dev); | |
15311 | ||
077f849d JSR |
15312 | if (tp->fw) |
15313 | release_firmware(tp->fw); | |
15314 | ||
23f333a2 | 15315 | cancel_work_sync(&tp->reset_task); |
158d7abd | 15316 | |
b02fd9e3 MC |
15317 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
15318 | tg3_phy_fini(tp); | |
158d7abd | 15319 | tg3_mdio_fini(tp); |
b02fd9e3 | 15320 | } |
158d7abd | 15321 | |
1da177e4 | 15322 | unregister_netdev(dev); |
0d3031d9 MC |
15323 | if (tp->aperegs) { |
15324 | iounmap(tp->aperegs); | |
15325 | tp->aperegs = NULL; | |
15326 | } | |
6892914f MC |
15327 | if (tp->regs) { |
15328 | iounmap(tp->regs); | |
22abe310 | 15329 | tp->regs = NULL; |
6892914f | 15330 | } |
1da177e4 LT |
15331 | free_netdev(dev); |
15332 | pci_release_regions(pdev); | |
15333 | pci_disable_device(pdev); | |
15334 | pci_set_drvdata(pdev, NULL); | |
15335 | } | |
15336 | } | |
15337 | ||
aa6027ca | 15338 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 15339 | static int tg3_suspend(struct device *device) |
1da177e4 | 15340 | { |
c866b7ea | 15341 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15342 | struct net_device *dev = pci_get_drvdata(pdev); |
15343 | struct tg3 *tp = netdev_priv(dev); | |
15344 | int err; | |
15345 | ||
15346 | if (!netif_running(dev)) | |
15347 | return 0; | |
15348 | ||
23f333a2 | 15349 | flush_work_sync(&tp->reset_task); |
b02fd9e3 | 15350 | tg3_phy_stop(tp); |
1da177e4 LT |
15351 | tg3_netif_stop(tp); |
15352 | ||
15353 | del_timer_sync(&tp->timer); | |
15354 | ||
f47c11ee | 15355 | tg3_full_lock(tp, 1); |
1da177e4 | 15356 | tg3_disable_ints(tp); |
f47c11ee | 15357 | tg3_full_unlock(tp); |
1da177e4 LT |
15358 | |
15359 | netif_device_detach(dev); | |
15360 | ||
f47c11ee | 15361 | tg3_full_lock(tp, 0); |
944d980e | 15362 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
6a9eba15 | 15363 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
f47c11ee | 15364 | tg3_full_unlock(tp); |
1da177e4 | 15365 | |
c866b7ea | 15366 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15367 | if (err) { |
b02fd9e3 MC |
15368 | int err2; |
15369 | ||
f47c11ee | 15370 | tg3_full_lock(tp, 0); |
1da177e4 | 15371 | |
6a9eba15 | 15372 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b02fd9e3 MC |
15373 | err2 = tg3_restart_hw(tp, 1); |
15374 | if (err2) | |
b9ec6c1b | 15375 | goto out; |
1da177e4 LT |
15376 | |
15377 | tp->timer.expires = jiffies + tp->timer_offset; | |
15378 | add_timer(&tp->timer); | |
15379 | ||
15380 | netif_device_attach(dev); | |
15381 | tg3_netif_start(tp); | |
15382 | ||
b9ec6c1b | 15383 | out: |
f47c11ee | 15384 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15385 | |
15386 | if (!err2) | |
15387 | tg3_phy_start(tp); | |
1da177e4 LT |
15388 | } |
15389 | ||
15390 | return err; | |
15391 | } | |
15392 | ||
c866b7ea | 15393 | static int tg3_resume(struct device *device) |
1da177e4 | 15394 | { |
c866b7ea | 15395 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15396 | struct net_device *dev = pci_get_drvdata(pdev); |
15397 | struct tg3 *tp = netdev_priv(dev); | |
15398 | int err; | |
15399 | ||
15400 | if (!netif_running(dev)) | |
15401 | return 0; | |
15402 | ||
1da177e4 LT |
15403 | netif_device_attach(dev); |
15404 | ||
f47c11ee | 15405 | tg3_full_lock(tp, 0); |
1da177e4 | 15406 | |
6a9eba15 | 15407 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b9ec6c1b MC |
15408 | err = tg3_restart_hw(tp, 1); |
15409 | if (err) | |
15410 | goto out; | |
1da177e4 LT |
15411 | |
15412 | tp->timer.expires = jiffies + tp->timer_offset; | |
15413 | add_timer(&tp->timer); | |
15414 | ||
1da177e4 LT |
15415 | tg3_netif_start(tp); |
15416 | ||
b9ec6c1b | 15417 | out: |
f47c11ee | 15418 | tg3_full_unlock(tp); |
1da177e4 | 15419 | |
b02fd9e3 MC |
15420 | if (!err) |
15421 | tg3_phy_start(tp); | |
15422 | ||
b9ec6c1b | 15423 | return err; |
1da177e4 LT |
15424 | } |
15425 | ||
c866b7ea | 15426 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15427 | #define TG3_PM_OPS (&tg3_pm_ops) |
15428 | ||
15429 | #else | |
15430 | ||
15431 | #define TG3_PM_OPS NULL | |
15432 | ||
15433 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 15434 | |
1da177e4 LT |
15435 | static struct pci_driver tg3_driver = { |
15436 | .name = DRV_MODULE_NAME, | |
15437 | .id_table = tg3_pci_tbl, | |
15438 | .probe = tg3_init_one, | |
15439 | .remove = __devexit_p(tg3_remove_one), | |
aa6027ca | 15440 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
15441 | }; |
15442 | ||
15443 | static int __init tg3_init(void) | |
15444 | { | |
29917620 | 15445 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
15446 | } |
15447 | ||
15448 | static void __exit tg3_cleanup(void) | |
15449 | { | |
15450 | pci_unregister_driver(&tg3_driver); | |
15451 | } | |
15452 | ||
15453 | module_init(tg3_init); | |
15454 | module_exit(tg3_cleanup); |