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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
0d2a5068 | 7 | * Copyright (C) 2005-2009 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/compiler.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/delay.h> | |
14c85021 | 26 | #include <linux/in.h> |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/ioport.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/mii.h> | |
158d7abd | 35 | #include <linux/phy.h> |
a9daf367 | 36 | #include <linux/brcmphy.h> |
1da177e4 LT |
37 | #include <linux/if_vlan.h> |
38 | #include <linux/ip.h> | |
39 | #include <linux/tcp.h> | |
40 | #include <linux/workqueue.h> | |
61487480 | 41 | #include <linux/prefetch.h> |
f9a5f7d3 | 42 | #include <linux/dma-mapping.h> |
077f849d | 43 | #include <linux/firmware.h> |
1da177e4 LT |
44 | |
45 | #include <net/checksum.h> | |
c9bdd4b5 | 46 | #include <net/ip.h> |
1da177e4 LT |
47 | |
48 | #include <asm/system.h> | |
49 | #include <asm/io.h> | |
50 | #include <asm/byteorder.h> | |
51 | #include <asm/uaccess.h> | |
52 | ||
49b6e95f | 53 | #ifdef CONFIG_SPARC |
1da177e4 | 54 | #include <asm/idprom.h> |
49b6e95f | 55 | #include <asm/prom.h> |
1da177e4 LT |
56 | #endif |
57 | ||
63532394 MC |
58 | #define BAR_0 0 |
59 | #define BAR_2 2 | |
60 | ||
1da177e4 LT |
61 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
62 | #define TG3_VLAN_TAG_USED 1 | |
63 | #else | |
64 | #define TG3_VLAN_TAG_USED 0 | |
65 | #endif | |
66 | ||
1da177e4 LT |
67 | #include "tg3.h" |
68 | ||
69 | #define DRV_MODULE_NAME "tg3" | |
70 | #define PFX DRV_MODULE_NAME ": " | |
123b43e9 MC |
71 | #define DRV_MODULE_VERSION "3.103" |
72 | #define DRV_MODULE_RELDATE "November 2, 2009" | |
1da177e4 LT |
73 | |
74 | #define TG3_DEF_MAC_MODE 0 | |
75 | #define TG3_DEF_RX_MODE 0 | |
76 | #define TG3_DEF_TX_MODE 0 | |
77 | #define TG3_DEF_MSG_ENABLE \ | |
78 | (NETIF_MSG_DRV | \ | |
79 | NETIF_MSG_PROBE | \ | |
80 | NETIF_MSG_LINK | \ | |
81 | NETIF_MSG_TIMER | \ | |
82 | NETIF_MSG_IFDOWN | \ | |
83 | NETIF_MSG_IFUP | \ | |
84 | NETIF_MSG_RX_ERR | \ | |
85 | NETIF_MSG_TX_ERR) | |
86 | ||
87 | /* length of time before we decide the hardware is borked, | |
88 | * and dev->tx_timeout() should be called to fix the problem | |
89 | */ | |
90 | #define TG3_TX_TIMEOUT (5 * HZ) | |
91 | ||
92 | /* hardware minimum and maximum for a single frame's data payload */ | |
93 | #define TG3_MIN_MTU 60 | |
94 | #define TG3_MAX_MTU(tp) \ | |
8f666b07 | 95 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
96 | |
97 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
98 | * You can't change the ring sizes, but you can change where you place | |
99 | * them in the NIC onboard memory. | |
100 | */ | |
101 | #define TG3_RX_RING_SIZE 512 | |
102 | #define TG3_DEF_RX_RING_PENDING 200 | |
103 | #define TG3_RX_JUMBO_RING_SIZE 256 | |
104 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 | |
baf8a94a | 105 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
106 | |
107 | /* Do not place this n-ring entries value into the tp struct itself, | |
108 | * we really want to expose these constants to GCC so that modulo et | |
109 | * al. operations are done with shifts and masks instead of with | |
110 | * hw multiply/modulo instructions. Another solution would be to | |
111 | * replace things like '% foo' with '& (foo - 1)'. | |
112 | */ | |
113 | #define TG3_RX_RCB_RING_SIZE(tp) \ | |
f6eb9b1f | 114 | (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \ |
5ea1c506 | 115 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512) |
1da177e4 LT |
116 | |
117 | #define TG3_TX_RING_SIZE 512 | |
118 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
119 | ||
120 | #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ | |
121 | TG3_RX_RING_SIZE) | |
79ed5ac7 MC |
122 | #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \ |
123 | TG3_RX_JUMBO_RING_SIZE) | |
1da177e4 | 124 | #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \ |
79ed5ac7 | 125 | TG3_RX_RCB_RING_SIZE(tp)) |
1da177e4 LT |
126 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
127 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
128 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
129 | ||
287be12e MC |
130 | #define TG3_DMA_BYTE_ENAB 64 |
131 | ||
132 | #define TG3_RX_STD_DMA_SZ 1536 | |
133 | #define TG3_RX_JMB_DMA_SZ 9046 | |
134 | ||
135 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
136 | ||
137 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
138 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 LT |
139 | |
140 | /* minimum number of free TX descriptors required to wake up TX process */ | |
f3f3f27e | 141 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
1da177e4 | 142 | |
ad829268 MC |
143 | #define TG3_RAW_IP_ALIGN 2 |
144 | ||
1da177e4 LT |
145 | /* number of ETHTOOL_GSTATS u64's */ |
146 | #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64)) | |
147 | ||
4cafd3f5 MC |
148 | #define TG3_NUM_TEST 6 |
149 | ||
077f849d JSR |
150 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
151 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
152 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
153 | ||
1da177e4 LT |
154 | static char version[] __devinitdata = |
155 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | |
156 | ||
157 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
158 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
159 | MODULE_LICENSE("GPL"); | |
160 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
161 | MODULE_FIRMWARE(FIRMWARE_TG3); |
162 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
163 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
164 | ||
679563f4 | 165 | #define TG3_RSS_MIN_NUM_MSIX_VECS 2 |
1da177e4 LT |
166 | |
167 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ | |
168 | module_param(tg3_debug, int, 0); | |
169 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
170 | ||
171 | static struct pci_device_id tg3_pci_tbl[] = { | |
13185217 HK |
172 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
173 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
174 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
175 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
176 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
177 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
178 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
179 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
180 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
181 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
182 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
183 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
184 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
185 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
186 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
187 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
188 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
189 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
190 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
191 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
192 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
193 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
194 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)}, | |
195 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, | |
126a3368 | 196 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 HK |
197 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)}, |
198 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, | |
199 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)}, | |
200 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, | |
201 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
202 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
203 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
204 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
205 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
206 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
207 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
208 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
209 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
210 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 211 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
212 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
213 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
214 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 215 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
13185217 HK |
238 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
239 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
243 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
244 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
245 | {} | |
1da177e4 LT |
246 | }; |
247 | ||
248 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
249 | ||
50da859d | 250 | static const struct { |
1da177e4 LT |
251 | const char string[ETH_GSTRING_LEN]; |
252 | } ethtool_stats_keys[TG3_NUM_STATS] = { | |
253 | { "rx_octets" }, | |
254 | { "rx_fragments" }, | |
255 | { "rx_ucast_packets" }, | |
256 | { "rx_mcast_packets" }, | |
257 | { "rx_bcast_packets" }, | |
258 | { "rx_fcs_errors" }, | |
259 | { "rx_align_errors" }, | |
260 | { "rx_xon_pause_rcvd" }, | |
261 | { "rx_xoff_pause_rcvd" }, | |
262 | { "rx_mac_ctrl_rcvd" }, | |
263 | { "rx_xoff_entered" }, | |
264 | { "rx_frame_too_long_errors" }, | |
265 | { "rx_jabbers" }, | |
266 | { "rx_undersize_packets" }, | |
267 | { "rx_in_length_errors" }, | |
268 | { "rx_out_length_errors" }, | |
269 | { "rx_64_or_less_octet_packets" }, | |
270 | { "rx_65_to_127_octet_packets" }, | |
271 | { "rx_128_to_255_octet_packets" }, | |
272 | { "rx_256_to_511_octet_packets" }, | |
273 | { "rx_512_to_1023_octet_packets" }, | |
274 | { "rx_1024_to_1522_octet_packets" }, | |
275 | { "rx_1523_to_2047_octet_packets" }, | |
276 | { "rx_2048_to_4095_octet_packets" }, | |
277 | { "rx_4096_to_8191_octet_packets" }, | |
278 | { "rx_8192_to_9022_octet_packets" }, | |
279 | ||
280 | { "tx_octets" }, | |
281 | { "tx_collisions" }, | |
282 | ||
283 | { "tx_xon_sent" }, | |
284 | { "tx_xoff_sent" }, | |
285 | { "tx_flow_control" }, | |
286 | { "tx_mac_errors" }, | |
287 | { "tx_single_collisions" }, | |
288 | { "tx_mult_collisions" }, | |
289 | { "tx_deferred" }, | |
290 | { "tx_excessive_collisions" }, | |
291 | { "tx_late_collisions" }, | |
292 | { "tx_collide_2times" }, | |
293 | { "tx_collide_3times" }, | |
294 | { "tx_collide_4times" }, | |
295 | { "tx_collide_5times" }, | |
296 | { "tx_collide_6times" }, | |
297 | { "tx_collide_7times" }, | |
298 | { "tx_collide_8times" }, | |
299 | { "tx_collide_9times" }, | |
300 | { "tx_collide_10times" }, | |
301 | { "tx_collide_11times" }, | |
302 | { "tx_collide_12times" }, | |
303 | { "tx_collide_13times" }, | |
304 | { "tx_collide_14times" }, | |
305 | { "tx_collide_15times" }, | |
306 | { "tx_ucast_packets" }, | |
307 | { "tx_mcast_packets" }, | |
308 | { "tx_bcast_packets" }, | |
309 | { "tx_carrier_sense_errors" }, | |
310 | { "tx_discards" }, | |
311 | { "tx_errors" }, | |
312 | ||
313 | { "dma_writeq_full" }, | |
314 | { "dma_write_prioq_full" }, | |
315 | { "rxbds_empty" }, | |
316 | { "rx_discards" }, | |
317 | { "rx_errors" }, | |
318 | { "rx_threshold_hit" }, | |
319 | ||
320 | { "dma_readq_full" }, | |
321 | { "dma_read_prioq_full" }, | |
322 | { "tx_comp_queue_full" }, | |
323 | ||
324 | { "ring_set_send_prod_index" }, | |
325 | { "ring_status_update" }, | |
326 | { "nic_irqs" }, | |
327 | { "nic_avoided_irqs" }, | |
328 | { "nic_tx_threshold_hit" } | |
329 | }; | |
330 | ||
50da859d | 331 | static const struct { |
4cafd3f5 MC |
332 | const char string[ETH_GSTRING_LEN]; |
333 | } ethtool_test_keys[TG3_NUM_TEST] = { | |
334 | { "nvram test (online) " }, | |
335 | { "link test (online) " }, | |
336 | { "register test (offline)" }, | |
337 | { "memory test (offline)" }, | |
338 | { "loopback test (offline)" }, | |
339 | { "interrupt test (offline)" }, | |
340 | }; | |
341 | ||
b401e9e2 MC |
342 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
343 | { | |
344 | writel(val, tp->regs + off); | |
345 | } | |
346 | ||
347 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
348 | { | |
6aa20a22 | 349 | return (readl(tp->regs + off)); |
b401e9e2 MC |
350 | } |
351 | ||
0d3031d9 MC |
352 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
353 | { | |
354 | writel(val, tp->aperegs + off); | |
355 | } | |
356 | ||
357 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
358 | { | |
359 | return (readl(tp->aperegs + off)); | |
360 | } | |
361 | ||
1da177e4 LT |
362 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
363 | { | |
6892914f MC |
364 | unsigned long flags; |
365 | ||
366 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
367 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
368 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 369 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
370 | } |
371 | ||
372 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
373 | { | |
374 | writel(val, tp->regs + off); | |
375 | readl(tp->regs + off); | |
1da177e4 LT |
376 | } |
377 | ||
6892914f | 378 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 379 | { |
6892914f MC |
380 | unsigned long flags; |
381 | u32 val; | |
382 | ||
383 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
384 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
385 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
386 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
387 | return val; | |
388 | } | |
389 | ||
390 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
391 | { | |
392 | unsigned long flags; | |
393 | ||
394 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
395 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
396 | TG3_64BIT_REG_LOW, val); | |
397 | return; | |
398 | } | |
399 | if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) { | |
400 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + | |
401 | TG3_64BIT_REG_LOW, val); | |
402 | return; | |
1da177e4 | 403 | } |
6892914f MC |
404 | |
405 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
406 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
407 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
408 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
409 | ||
410 | /* In indirect mode when disabling interrupts, we also need | |
411 | * to clear the interrupt bit in the GRC local ctrl register. | |
412 | */ | |
413 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
414 | (val == 0x1)) { | |
415 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
416 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
417 | } | |
418 | } | |
419 | ||
420 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
421 | { | |
422 | unsigned long flags; | |
423 | u32 val; | |
424 | ||
425 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
426 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
427 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
428 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
429 | return val; | |
430 | } | |
431 | ||
b401e9e2 MC |
432 | /* usec_wait specifies the wait time in usec when writing to certain registers |
433 | * where it is unsafe to read back the register without some delay. | |
434 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
435 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
436 | */ | |
437 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 438 | { |
b401e9e2 MC |
439 | if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || |
440 | (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
441 | /* Non-posted methods */ | |
442 | tp->write32(tp, off, val); | |
443 | else { | |
444 | /* Posted method */ | |
445 | tg3_write32(tp, off, val); | |
446 | if (usec_wait) | |
447 | udelay(usec_wait); | |
448 | tp->read32(tp, off); | |
449 | } | |
450 | /* Wait again after the read for the posted method to guarantee that | |
451 | * the wait time is met. | |
452 | */ | |
453 | if (usec_wait) | |
454 | udelay(usec_wait); | |
1da177e4 LT |
455 | } |
456 | ||
09ee929c MC |
457 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
458 | { | |
459 | tp->write32_mbox(tp, off, val); | |
6892914f MC |
460 | if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && |
461 | !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
462 | tp->read32_mbox(tp, off); | |
09ee929c MC |
463 | } |
464 | ||
20094930 | 465 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
466 | { |
467 | void __iomem *mbox = tp->regs + off; | |
468 | writel(val, mbox); | |
469 | if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) | |
470 | writel(val, mbox); | |
471 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
472 | readl(mbox); | |
473 | } | |
474 | ||
b5d3772c MC |
475 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
476 | { | |
477 | return (readl(tp->regs + off + GRCMBOX_BASE)); | |
478 | } | |
479 | ||
480 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
481 | { | |
482 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
483 | } | |
484 | ||
20094930 | 485 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 486 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
20094930 MC |
487 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
488 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
09ee929c | 489 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) |
20094930 MC |
490 | |
491 | #define tw32(reg,val) tp->write32(tp, reg, val) | |
b401e9e2 MC |
492 | #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0) |
493 | #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us)) | |
20094930 | 494 | #define tr32(reg) tp->read32(tp, reg) |
1da177e4 LT |
495 | |
496 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
497 | { | |
6892914f MC |
498 | unsigned long flags; |
499 | ||
b5d3772c MC |
500 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
501 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
502 | return; | |
503 | ||
6892914f | 504 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
505 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
506 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
507 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 508 | |
bbadf503 MC |
509 | /* Always leave this as zero. */ |
510 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
511 | } else { | |
512 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
513 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 514 | |
bbadf503 MC |
515 | /* Always leave this as zero. */ |
516 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
517 | } | |
518 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
519 | } |
520 | ||
1da177e4 LT |
521 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
522 | { | |
6892914f MC |
523 | unsigned long flags; |
524 | ||
b5d3772c MC |
525 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
526 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
527 | *val = 0; | |
528 | return; | |
529 | } | |
530 | ||
6892914f | 531 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
532 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
533 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
534 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 535 | |
bbadf503 MC |
536 | /* Always leave this as zero. */ |
537 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
538 | } else { | |
539 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
540 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
541 | ||
542 | /* Always leave this as zero. */ | |
543 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
544 | } | |
6892914f | 545 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
546 | } |
547 | ||
0d3031d9 MC |
548 | static void tg3_ape_lock_init(struct tg3 *tp) |
549 | { | |
550 | int i; | |
551 | ||
552 | /* Make sure the driver hasn't any stale locks. */ | |
553 | for (i = 0; i < 8; i++) | |
554 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i, | |
555 | APE_LOCK_GRANT_DRIVER); | |
556 | } | |
557 | ||
558 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
559 | { | |
560 | int i, off; | |
561 | int ret = 0; | |
562 | u32 status; | |
563 | ||
564 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
565 | return 0; | |
566 | ||
567 | switch (locknum) { | |
77b483f1 | 568 | case TG3_APE_LOCK_GRC: |
0d3031d9 MC |
569 | case TG3_APE_LOCK_MEM: |
570 | break; | |
571 | default: | |
572 | return -EINVAL; | |
573 | } | |
574 | ||
575 | off = 4 * locknum; | |
576 | ||
577 | tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER); | |
578 | ||
579 | /* Wait for up to 1 millisecond to acquire lock. */ | |
580 | for (i = 0; i < 100; i++) { | |
581 | status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off); | |
582 | if (status == APE_LOCK_GRANT_DRIVER) | |
583 | break; | |
584 | udelay(10); | |
585 | } | |
586 | ||
587 | if (status != APE_LOCK_GRANT_DRIVER) { | |
588 | /* Revoke the lock request. */ | |
589 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, | |
590 | APE_LOCK_GRANT_DRIVER); | |
591 | ||
592 | ret = -EBUSY; | |
593 | } | |
594 | ||
595 | return ret; | |
596 | } | |
597 | ||
598 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
599 | { | |
600 | int off; | |
601 | ||
602 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
603 | return; | |
604 | ||
605 | switch (locknum) { | |
77b483f1 | 606 | case TG3_APE_LOCK_GRC: |
0d3031d9 MC |
607 | case TG3_APE_LOCK_MEM: |
608 | break; | |
609 | default: | |
610 | return; | |
611 | } | |
612 | ||
613 | off = 4 * locknum; | |
614 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER); | |
615 | } | |
616 | ||
1da177e4 LT |
617 | static void tg3_disable_ints(struct tg3 *tp) |
618 | { | |
89aeb3bc MC |
619 | int i; |
620 | ||
1da177e4 LT |
621 | tw32(TG3PCI_MISC_HOST_CTRL, |
622 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
623 | for (i = 0; i < tp->irq_max; i++) |
624 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
625 | } |
626 | ||
1da177e4 LT |
627 | static void tg3_enable_ints(struct tg3 *tp) |
628 | { | |
89aeb3bc MC |
629 | int i; |
630 | u32 coal_now = 0; | |
631 | ||
bbe832c0 MC |
632 | tp->irq_sync = 0; |
633 | wmb(); | |
634 | ||
1da177e4 LT |
635 | tw32(TG3PCI_MISC_HOST_CTRL, |
636 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
637 | |
638 | for (i = 0; i < tp->irq_cnt; i++) { | |
639 | struct tg3_napi *tnapi = &tp->napi[i]; | |
898a56f8 | 640 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
89aeb3bc MC |
641 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) |
642 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
f19af9c2 | 643 | |
89aeb3bc MC |
644 | coal_now |= tnapi->coal_now; |
645 | } | |
f19af9c2 MC |
646 | |
647 | /* Force an initial interrupt */ | |
648 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
649 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) | |
650 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
651 | else | |
652 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
653 | HOSTCC_MODE_ENABLE | coal_now); | |
1da177e4 LT |
654 | } |
655 | ||
17375d25 | 656 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 657 | { |
17375d25 | 658 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 659 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
660 | unsigned int work_exists = 0; |
661 | ||
662 | /* check for phy events */ | |
663 | if (!(tp->tg3_flags & | |
664 | (TG3_FLAG_USE_LINKCHG_REG | | |
665 | TG3_FLAG_POLL_SERDES))) { | |
666 | if (sblk->status & SD_STATUS_LINK_CHG) | |
667 | work_exists = 1; | |
668 | } | |
669 | /* check for RX/TX work to do */ | |
f3f3f27e | 670 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 671 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
672 | work_exists = 1; |
673 | ||
674 | return work_exists; | |
675 | } | |
676 | ||
17375d25 | 677 | /* tg3_int_reenable |
04237ddd MC |
678 | * similar to tg3_enable_ints, but it accurately determines whether there |
679 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 680 | * which reenables interrupts |
1da177e4 | 681 | */ |
17375d25 | 682 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 683 | { |
17375d25 MC |
684 | struct tg3 *tp = tnapi->tp; |
685 | ||
898a56f8 | 686 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
687 | mmiowb(); |
688 | ||
fac9b83e DM |
689 | /* When doing tagged status, this work check is unnecessary. |
690 | * The last_tag we write above tells the chip which piece of | |
691 | * work we've completed. | |
692 | */ | |
693 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
17375d25 | 694 | tg3_has_work(tnapi)) |
04237ddd | 695 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 696 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
697 | } |
698 | ||
fed97810 MC |
699 | static void tg3_napi_disable(struct tg3 *tp) |
700 | { | |
701 | int i; | |
702 | ||
703 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
704 | napi_disable(&tp->napi[i].napi); | |
705 | } | |
706 | ||
707 | static void tg3_napi_enable(struct tg3 *tp) | |
708 | { | |
709 | int i; | |
710 | ||
711 | for (i = 0; i < tp->irq_cnt; i++) | |
712 | napi_enable(&tp->napi[i].napi); | |
713 | } | |
714 | ||
1da177e4 LT |
715 | static inline void tg3_netif_stop(struct tg3 *tp) |
716 | { | |
bbe832c0 | 717 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ |
fed97810 | 718 | tg3_napi_disable(tp); |
1da177e4 LT |
719 | netif_tx_disable(tp->dev); |
720 | } | |
721 | ||
722 | static inline void tg3_netif_start(struct tg3 *tp) | |
723 | { | |
fe5f5787 MC |
724 | /* NOTE: unconditional netif_tx_wake_all_queues is only |
725 | * appropriate so long as all callers are assured to | |
726 | * have free tx slots (such as after tg3_init_hw) | |
1da177e4 | 727 | */ |
fe5f5787 MC |
728 | netif_tx_wake_all_queues(tp->dev); |
729 | ||
fed97810 MC |
730 | tg3_napi_enable(tp); |
731 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
f47c11ee | 732 | tg3_enable_ints(tp); |
1da177e4 LT |
733 | } |
734 | ||
735 | static void tg3_switch_clocks(struct tg3 *tp) | |
736 | { | |
f6eb9b1f | 737 | u32 clock_ctrl; |
1da177e4 LT |
738 | u32 orig_clock_ctrl; |
739 | ||
795d01c5 MC |
740 | if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
741 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
4cf78e4f MC |
742 | return; |
743 | ||
f6eb9b1f MC |
744 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
745 | ||
1da177e4 LT |
746 | orig_clock_ctrl = clock_ctrl; |
747 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
748 | CLOCK_CTRL_CLKRUN_OENABLE | | |
749 | 0x1f); | |
750 | tp->pci_clock_ctrl = clock_ctrl; | |
751 | ||
752 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
753 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
b401e9e2 MC |
754 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
755 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
756 | } |
757 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
758 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
759 | clock_ctrl | | |
760 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
761 | 40); | |
762 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
763 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
764 | 40); | |
1da177e4 | 765 | } |
b401e9e2 | 766 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
767 | } |
768 | ||
769 | #define PHY_BUSY_LOOPS 5000 | |
770 | ||
771 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
772 | { | |
773 | u32 frame_val; | |
774 | unsigned int loops; | |
775 | int ret; | |
776 | ||
777 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
778 | tw32_f(MAC_MI_MODE, | |
779 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
780 | udelay(80); | |
781 | } | |
782 | ||
783 | *val = 0x0; | |
784 | ||
882e9793 | 785 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
786 | MI_COM_PHY_ADDR_MASK); |
787 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
788 | MI_COM_REG_ADDR_MASK); | |
789 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 790 | |
1da177e4 LT |
791 | tw32_f(MAC_MI_COM, frame_val); |
792 | ||
793 | loops = PHY_BUSY_LOOPS; | |
794 | while (loops != 0) { | |
795 | udelay(10); | |
796 | frame_val = tr32(MAC_MI_COM); | |
797 | ||
798 | if ((frame_val & MI_COM_BUSY) == 0) { | |
799 | udelay(5); | |
800 | frame_val = tr32(MAC_MI_COM); | |
801 | break; | |
802 | } | |
803 | loops -= 1; | |
804 | } | |
805 | ||
806 | ret = -EBUSY; | |
807 | if (loops != 0) { | |
808 | *val = frame_val & MI_COM_DATA_MASK; | |
809 | ret = 0; | |
810 | } | |
811 | ||
812 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
813 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
814 | udelay(80); | |
815 | } | |
816 | ||
817 | return ret; | |
818 | } | |
819 | ||
820 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
821 | { | |
822 | u32 frame_val; | |
823 | unsigned int loops; | |
824 | int ret; | |
825 | ||
7f97a4bd | 826 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && |
b5d3772c MC |
827 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) |
828 | return 0; | |
829 | ||
1da177e4 LT |
830 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
831 | tw32_f(MAC_MI_MODE, | |
832 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
833 | udelay(80); | |
834 | } | |
835 | ||
882e9793 | 836 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
837 | MI_COM_PHY_ADDR_MASK); |
838 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
839 | MI_COM_REG_ADDR_MASK); | |
840 | frame_val |= (val & MI_COM_DATA_MASK); | |
841 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 842 | |
1da177e4 LT |
843 | tw32_f(MAC_MI_COM, frame_val); |
844 | ||
845 | loops = PHY_BUSY_LOOPS; | |
846 | while (loops != 0) { | |
847 | udelay(10); | |
848 | frame_val = tr32(MAC_MI_COM); | |
849 | if ((frame_val & MI_COM_BUSY) == 0) { | |
850 | udelay(5); | |
851 | frame_val = tr32(MAC_MI_COM); | |
852 | break; | |
853 | } | |
854 | loops -= 1; | |
855 | } | |
856 | ||
857 | ret = -EBUSY; | |
858 | if (loops != 0) | |
859 | ret = 0; | |
860 | ||
861 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
862 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
863 | udelay(80); | |
864 | } | |
865 | ||
866 | return ret; | |
867 | } | |
868 | ||
95e2869a MC |
869 | static int tg3_bmcr_reset(struct tg3 *tp) |
870 | { | |
871 | u32 phy_control; | |
872 | int limit, err; | |
873 | ||
874 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
875 | * clears or we time out. | |
876 | */ | |
877 | phy_control = BMCR_RESET; | |
878 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
879 | if (err != 0) | |
880 | return -EBUSY; | |
881 | ||
882 | limit = 5000; | |
883 | while (limit--) { | |
884 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
885 | if (err != 0) | |
886 | return -EBUSY; | |
887 | ||
888 | if ((phy_control & BMCR_RESET) == 0) { | |
889 | udelay(40); | |
890 | break; | |
891 | } | |
892 | udelay(10); | |
893 | } | |
d4675b52 | 894 | if (limit < 0) |
95e2869a MC |
895 | return -EBUSY; |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
158d7abd MC |
900 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
901 | { | |
3d16543d | 902 | struct tg3 *tp = bp->priv; |
158d7abd MC |
903 | u32 val; |
904 | ||
24bb4fb6 | 905 | spin_lock_bh(&tp->lock); |
158d7abd MC |
906 | |
907 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
908 | val = -EIO; |
909 | ||
910 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
911 | |
912 | return val; | |
913 | } | |
914 | ||
915 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
916 | { | |
3d16543d | 917 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 918 | u32 ret = 0; |
158d7abd | 919 | |
24bb4fb6 | 920 | spin_lock_bh(&tp->lock); |
158d7abd MC |
921 | |
922 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 923 | ret = -EIO; |
158d7abd | 924 | |
24bb4fb6 MC |
925 | spin_unlock_bh(&tp->lock); |
926 | ||
927 | return ret; | |
158d7abd MC |
928 | } |
929 | ||
930 | static int tg3_mdio_reset(struct mii_bus *bp) | |
931 | { | |
932 | return 0; | |
933 | } | |
934 | ||
9c61d6bc | 935 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
936 | { |
937 | u32 val; | |
fcb389df | 938 | struct phy_device *phydev; |
a9daf367 | 939 | |
3f0e3ad7 | 940 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df MC |
941 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
942 | case TG3_PHY_ID_BCM50610: | |
c73430d0 | 943 | case TG3_PHY_ID_BCM50610M: |
fcb389df MC |
944 | val = MAC_PHYCFG2_50610_LED_MODES; |
945 | break; | |
946 | case TG3_PHY_ID_BCMAC131: | |
947 | val = MAC_PHYCFG2_AC131_LED_MODES; | |
948 | break; | |
949 | case TG3_PHY_ID_RTL8211C: | |
950 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; | |
951 | break; | |
952 | case TG3_PHY_ID_RTL8201E: | |
953 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; | |
954 | break; | |
955 | default: | |
a9daf367 | 956 | return; |
fcb389df MC |
957 | } |
958 | ||
959 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
960 | tw32(MAC_PHYCFG2, val); | |
961 | ||
962 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
963 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
964 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
965 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
966 | tw32(MAC_PHYCFG1, val); |
967 | ||
968 | return; | |
969 | } | |
970 | ||
971 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) | |
972 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | | |
973 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
974 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
975 | MAC_PHYCFG2_ACT_MASK_MASK | | |
976 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
977 | MAC_PHYCFG2_INBAND_ENABLE; | |
978 | ||
979 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 980 | |
bb85fbb6 MC |
981 | val = tr32(MAC_PHYCFG1); |
982 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
983 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
984 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) { | |
a9daf367 MC |
985 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
986 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
987 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
988 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
989 | } | |
bb85fbb6 MC |
990 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
991 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
992 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 993 | |
a9daf367 MC |
994 | val = tr32(MAC_EXT_RGMII_MODE); |
995 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
996 | MAC_RGMII_MODE_RX_QUALITY | | |
997 | MAC_RGMII_MODE_RX_ACTIVITY | | |
998 | MAC_RGMII_MODE_RX_ENG_DET | | |
999 | MAC_RGMII_MODE_TX_ENABLE | | |
1000 | MAC_RGMII_MODE_TX_LOWPWR | | |
1001 | MAC_RGMII_MODE_TX_RESET); | |
fcb389df | 1002 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) { |
a9daf367 MC |
1003 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1004 | val |= MAC_RGMII_MODE_RX_INT_B | | |
1005 | MAC_RGMII_MODE_RX_QUALITY | | |
1006 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1007 | MAC_RGMII_MODE_RX_ENG_DET; | |
1008 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1009 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
1010 | MAC_RGMII_MODE_TX_LOWPWR | | |
1011 | MAC_RGMII_MODE_TX_RESET; | |
1012 | } | |
1013 | tw32(MAC_EXT_RGMII_MODE, val); | |
1014 | } | |
1015 | ||
158d7abd MC |
1016 | static void tg3_mdio_start(struct tg3 *tp) |
1017 | { | |
158d7abd MC |
1018 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1019 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1020 | udelay(80); | |
a9daf367 | 1021 | |
882e9793 MC |
1022 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
1023 | u32 funcnum, is_serdes; | |
1024 | ||
1025 | funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC; | |
1026 | if (funcnum) | |
1027 | tp->phy_addr = 2; | |
1028 | else | |
1029 | tp->phy_addr = 1; | |
1030 | ||
1031 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1032 | if (is_serdes) | |
1033 | tp->phy_addr += 7; | |
1034 | } else | |
3f0e3ad7 | 1035 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1036 | |
9c61d6bc MC |
1037 | if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && |
1038 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1039 | tg3_mdio_config_5785(tp); | |
158d7abd MC |
1040 | } |
1041 | ||
158d7abd MC |
1042 | static int tg3_mdio_init(struct tg3 *tp) |
1043 | { | |
1044 | int i; | |
1045 | u32 reg; | |
a9daf367 | 1046 | struct phy_device *phydev; |
158d7abd MC |
1047 | |
1048 | tg3_mdio_start(tp); | |
1049 | ||
1050 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || | |
1051 | (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)) | |
1052 | return 0; | |
1053 | ||
298cf9be LB |
1054 | tp->mdio_bus = mdiobus_alloc(); |
1055 | if (tp->mdio_bus == NULL) | |
1056 | return -ENOMEM; | |
158d7abd | 1057 | |
298cf9be LB |
1058 | tp->mdio_bus->name = "tg3 mdio bus"; |
1059 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1060 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1061 | tp->mdio_bus->priv = tp; |
1062 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1063 | tp->mdio_bus->read = &tg3_mdio_read; | |
1064 | tp->mdio_bus->write = &tg3_mdio_write; | |
1065 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1066 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1067 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1068 | |
1069 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1070 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1071 | |
1072 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1073 | * Unfortunately, it does not ensure the PHY is powered up before | |
1074 | * accessing the PHY ID registers. A chip reset is the | |
1075 | * quickest way to bring the device back to an operational state.. | |
1076 | */ | |
1077 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1078 | tg3_bmcr_reset(tp); | |
1079 | ||
298cf9be | 1080 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1081 | if (i) { |
158d7abd MC |
1082 | printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n", |
1083 | tp->dev->name, i); | |
9c61d6bc | 1084 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1085 | return i; |
1086 | } | |
158d7abd | 1087 | |
3f0e3ad7 | 1088 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1089 | |
9c61d6bc MC |
1090 | if (!phydev || !phydev->drv) { |
1091 | printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name); | |
1092 | mdiobus_unregister(tp->mdio_bus); | |
1093 | mdiobus_free(tp->mdio_bus); | |
1094 | return -ENODEV; | |
1095 | } | |
1096 | ||
1097 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
321d32a0 MC |
1098 | case TG3_PHY_ID_BCM57780: |
1099 | phydev->interface = PHY_INTERFACE_MODE_GMII; | |
c704dc23 | 1100 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1101 | break; |
a9daf367 | 1102 | case TG3_PHY_ID_BCM50610: |
c73430d0 | 1103 | case TG3_PHY_ID_BCM50610M: |
32e5a8d6 | 1104 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1105 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1106 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1107 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
a9daf367 MC |
1108 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) |
1109 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; | |
1110 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1111 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1112 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1113 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
fcb389df MC |
1114 | /* fallthru */ |
1115 | case TG3_PHY_ID_RTL8211C: | |
1116 | phydev->interface = PHY_INTERFACE_MODE_RGMII; | |
a9daf367 | 1117 | break; |
fcb389df | 1118 | case TG3_PHY_ID_RTL8201E: |
a9daf367 MC |
1119 | case TG3_PHY_ID_BCMAC131: |
1120 | phydev->interface = PHY_INTERFACE_MODE_MII; | |
cdd4e09d | 1121 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
7f97a4bd | 1122 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; |
a9daf367 MC |
1123 | break; |
1124 | } | |
1125 | ||
9c61d6bc MC |
1126 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; |
1127 | ||
1128 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1129 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1130 | |
1131 | return 0; | |
158d7abd MC |
1132 | } |
1133 | ||
1134 | static void tg3_mdio_fini(struct tg3 *tp) | |
1135 | { | |
1136 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
1137 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; | |
298cf9be LB |
1138 | mdiobus_unregister(tp->mdio_bus); |
1139 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1140 | } |
1141 | } | |
1142 | ||
4ba526ce MC |
1143 | /* tp->lock is held. */ |
1144 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1145 | { | |
1146 | u32 val; | |
1147 | ||
1148 | val = tr32(GRC_RX_CPU_EVENT); | |
1149 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1150 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1151 | ||
1152 | tp->last_event_jiffies = jiffies; | |
1153 | } | |
1154 | ||
1155 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1156 | ||
95e2869a MC |
1157 | /* tp->lock is held. */ |
1158 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1159 | { | |
1160 | int i; | |
4ba526ce MC |
1161 | unsigned int delay_cnt; |
1162 | long time_remain; | |
1163 | ||
1164 | /* If enough time has passed, no wait is necessary. */ | |
1165 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1166 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1167 | (long)jiffies; | |
1168 | if (time_remain < 0) | |
1169 | return; | |
1170 | ||
1171 | /* Check if we can shorten the wait time. */ | |
1172 | delay_cnt = jiffies_to_usecs(time_remain); | |
1173 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1174 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1175 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1176 | |
4ba526ce | 1177 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1178 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1179 | break; | |
4ba526ce | 1180 | udelay(8); |
95e2869a MC |
1181 | } |
1182 | } | |
1183 | ||
1184 | /* tp->lock is held. */ | |
1185 | static void tg3_ump_link_report(struct tg3 *tp) | |
1186 | { | |
1187 | u32 reg; | |
1188 | u32 val; | |
1189 | ||
1190 | if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
1191 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
1192 | return; | |
1193 | ||
1194 | tg3_wait_for_event_ack(tp); | |
1195 | ||
1196 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1197 | ||
1198 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1199 | ||
1200 | val = 0; | |
1201 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1202 | val = reg << 16; | |
1203 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1204 | val |= (reg & 0xffff); | |
1205 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1206 | ||
1207 | val = 0; | |
1208 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1209 | val = reg << 16; | |
1210 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1211 | val |= (reg & 0xffff); | |
1212 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1213 | ||
1214 | val = 0; | |
1215 | if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) { | |
1216 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) | |
1217 | val = reg << 16; | |
1218 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1219 | val |= (reg & 0xffff); | |
1220 | } | |
1221 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1222 | ||
1223 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1224 | val = reg << 16; | |
1225 | else | |
1226 | val = 0; | |
1227 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1228 | ||
4ba526ce | 1229 | tg3_generate_fw_event(tp); |
95e2869a MC |
1230 | } |
1231 | ||
1232 | static void tg3_link_report(struct tg3 *tp) | |
1233 | { | |
1234 | if (!netif_carrier_ok(tp->dev)) { | |
1235 | if (netif_msg_link(tp)) | |
1236 | printk(KERN_INFO PFX "%s: Link is down.\n", | |
1237 | tp->dev->name); | |
1238 | tg3_ump_link_report(tp); | |
1239 | } else if (netif_msg_link(tp)) { | |
1240 | printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n", | |
1241 | tp->dev->name, | |
1242 | (tp->link_config.active_speed == SPEED_1000 ? | |
1243 | 1000 : | |
1244 | (tp->link_config.active_speed == SPEED_100 ? | |
1245 | 100 : 10)), | |
1246 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1247 | "full" : "half")); | |
1248 | ||
1249 | printk(KERN_INFO PFX | |
1250 | "%s: Flow control is %s for TX and %s for RX.\n", | |
1251 | tp->dev->name, | |
e18ce346 | 1252 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? |
95e2869a | 1253 | "on" : "off", |
e18ce346 | 1254 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? |
95e2869a MC |
1255 | "on" : "off"); |
1256 | tg3_ump_link_report(tp); | |
1257 | } | |
1258 | } | |
1259 | ||
1260 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1261 | { | |
1262 | u16 miireg; | |
1263 | ||
e18ce346 | 1264 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1265 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1266 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1267 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1268 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1269 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1270 | else | |
1271 | miireg = 0; | |
1272 | ||
1273 | return miireg; | |
1274 | } | |
1275 | ||
1276 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1277 | { | |
1278 | u16 miireg; | |
1279 | ||
e18ce346 | 1280 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1281 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1282 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1283 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1284 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1285 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1286 | else | |
1287 | miireg = 0; | |
1288 | ||
1289 | return miireg; | |
1290 | } | |
1291 | ||
95e2869a MC |
1292 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1293 | { | |
1294 | u8 cap = 0; | |
1295 | ||
1296 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1297 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1298 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1299 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1300 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1301 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1302 | } else { |
1303 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1304 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1305 | } |
1306 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1307 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1308 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1309 | } |
1310 | ||
1311 | return cap; | |
1312 | } | |
1313 | ||
f51f3562 | 1314 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1315 | { |
b02fd9e3 | 1316 | u8 autoneg; |
f51f3562 | 1317 | u8 flowctrl = 0; |
95e2869a MC |
1318 | u32 old_rx_mode = tp->rx_mode; |
1319 | u32 old_tx_mode = tp->tx_mode; | |
1320 | ||
b02fd9e3 | 1321 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
3f0e3ad7 | 1322 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1323 | else |
1324 | autoneg = tp->link_config.autoneg; | |
1325 | ||
1326 | if (autoneg == AUTONEG_ENABLE && | |
95e2869a MC |
1327 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { |
1328 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | |
f51f3562 | 1329 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1330 | else |
bc02ff95 | 1331 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1332 | } else |
1333 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1334 | |
f51f3562 | 1335 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1336 | |
e18ce346 | 1337 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1338 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1339 | else | |
1340 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1341 | ||
f51f3562 | 1342 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1343 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1344 | |
e18ce346 | 1345 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1346 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1347 | else | |
1348 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1349 | ||
f51f3562 | 1350 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1351 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1352 | } |
1353 | ||
b02fd9e3 MC |
1354 | static void tg3_adjust_link(struct net_device *dev) |
1355 | { | |
1356 | u8 oldflowctrl, linkmesg = 0; | |
1357 | u32 mac_mode, lcl_adv, rmt_adv; | |
1358 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1359 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1360 | |
24bb4fb6 | 1361 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1362 | |
1363 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1364 | MAC_MODE_HALF_DUPLEX); | |
1365 | ||
1366 | oldflowctrl = tp->link_config.active_flowctrl; | |
1367 | ||
1368 | if (phydev->link) { | |
1369 | lcl_adv = 0; | |
1370 | rmt_adv = 0; | |
1371 | ||
1372 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1373 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1374 | else if (phydev->speed == SPEED_1000 || |
1375 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1376 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1377 | else |
1378 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1379 | |
1380 | if (phydev->duplex == DUPLEX_HALF) | |
1381 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1382 | else { | |
1383 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1384 | tp->link_config.flowctrl); | |
1385 | ||
1386 | if (phydev->pause) | |
1387 | rmt_adv = LPA_PAUSE_CAP; | |
1388 | if (phydev->asym_pause) | |
1389 | rmt_adv |= LPA_PAUSE_ASYM; | |
1390 | } | |
1391 | ||
1392 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1393 | } else | |
1394 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1395 | ||
1396 | if (mac_mode != tp->mac_mode) { | |
1397 | tp->mac_mode = mac_mode; | |
1398 | tw32_f(MAC_MODE, tp->mac_mode); | |
1399 | udelay(40); | |
1400 | } | |
1401 | ||
fcb389df MC |
1402 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1403 | if (phydev->speed == SPEED_10) | |
1404 | tw32(MAC_MI_STAT, | |
1405 | MAC_MI_STAT_10MBPS_MODE | | |
1406 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1407 | else | |
1408 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1409 | } | |
1410 | ||
b02fd9e3 MC |
1411 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1412 | tw32(MAC_TX_LENGTHS, | |
1413 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1414 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1415 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1416 | else | |
1417 | tw32(MAC_TX_LENGTHS, | |
1418 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1419 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1420 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1421 | ||
1422 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1423 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1424 | phydev->speed != tp->link_config.active_speed || | |
1425 | phydev->duplex != tp->link_config.active_duplex || | |
1426 | oldflowctrl != tp->link_config.active_flowctrl) | |
1427 | linkmesg = 1; | |
1428 | ||
1429 | tp->link_config.active_speed = phydev->speed; | |
1430 | tp->link_config.active_duplex = phydev->duplex; | |
1431 | ||
24bb4fb6 | 1432 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1433 | |
1434 | if (linkmesg) | |
1435 | tg3_link_report(tp); | |
1436 | } | |
1437 | ||
1438 | static int tg3_phy_init(struct tg3 *tp) | |
1439 | { | |
1440 | struct phy_device *phydev; | |
1441 | ||
1442 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) | |
1443 | return 0; | |
1444 | ||
1445 | /* Bring the PHY back to a known state. */ | |
1446 | tg3_bmcr_reset(tp); | |
1447 | ||
3f0e3ad7 | 1448 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1449 | |
1450 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1451 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1452 | phydev->dev_flags, phydev->interface); |
b02fd9e3 MC |
1453 | if (IS_ERR(phydev)) { |
1454 | printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name); | |
1455 | return PTR_ERR(phydev); | |
1456 | } | |
1457 | ||
b02fd9e3 | 1458 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1459 | switch (phydev->interface) { |
1460 | case PHY_INTERFACE_MODE_GMII: | |
1461 | case PHY_INTERFACE_MODE_RGMII: | |
321d32a0 MC |
1462 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { |
1463 | phydev->supported &= (PHY_GBIT_FEATURES | | |
1464 | SUPPORTED_Pause | | |
1465 | SUPPORTED_Asym_Pause); | |
1466 | break; | |
1467 | } | |
1468 | /* fallthru */ | |
9c61d6bc MC |
1469 | case PHY_INTERFACE_MODE_MII: |
1470 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1471 | SUPPORTED_Pause | | |
1472 | SUPPORTED_Asym_Pause); | |
1473 | break; | |
1474 | default: | |
3f0e3ad7 | 1475 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1476 | return -EINVAL; |
1477 | } | |
1478 | ||
1479 | tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED; | |
b02fd9e3 MC |
1480 | |
1481 | phydev->advertising = phydev->supported; | |
1482 | ||
b02fd9e3 MC |
1483 | return 0; |
1484 | } | |
1485 | ||
1486 | static void tg3_phy_start(struct tg3 *tp) | |
1487 | { | |
1488 | struct phy_device *phydev; | |
1489 | ||
1490 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1491 | return; | |
1492 | ||
3f0e3ad7 | 1493 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1494 | |
1495 | if (tp->link_config.phy_is_low_power) { | |
1496 | tp->link_config.phy_is_low_power = 0; | |
1497 | phydev->speed = tp->link_config.orig_speed; | |
1498 | phydev->duplex = tp->link_config.orig_duplex; | |
1499 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1500 | phydev->advertising = tp->link_config.orig_advertising; | |
1501 | } | |
1502 | ||
1503 | phy_start(phydev); | |
1504 | ||
1505 | phy_start_aneg(phydev); | |
1506 | } | |
1507 | ||
1508 | static void tg3_phy_stop(struct tg3 *tp) | |
1509 | { | |
1510 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1511 | return; | |
1512 | ||
3f0e3ad7 | 1513 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1514 | } |
1515 | ||
1516 | static void tg3_phy_fini(struct tg3 *tp) | |
1517 | { | |
1518 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
3f0e3ad7 | 1519 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1520 | tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED; |
1521 | } | |
1522 | } | |
1523 | ||
b2a5c19c MC |
1524 | static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) |
1525 | { | |
1526 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1527 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1528 | } | |
1529 | ||
7f97a4bd MC |
1530 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1531 | { | |
1532 | u32 phytest; | |
1533 | ||
1534 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1535 | u32 phy; | |
1536 | ||
1537 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1538 | phytest | MII_TG3_FET_SHADOW_EN); | |
1539 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1540 | if (enable) | |
1541 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1542 | else | |
1543 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1544 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1545 | } | |
1546 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1547 | } | |
1548 | } | |
1549 | ||
6833c043 MC |
1550 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1551 | { | |
1552 | u32 reg; | |
1553 | ||
7f97a4bd | 1554 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
6833c043 MC |
1555 | return; |
1556 | ||
7f97a4bd MC |
1557 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
1558 | tg3_phy_fet_toggle_apd(tp, enable); | |
1559 | return; | |
1560 | } | |
1561 | ||
6833c043 MC |
1562 | reg = MII_TG3_MISC_SHDW_WREN | |
1563 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1564 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1565 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1566 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1567 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1568 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1569 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1570 | ||
1571 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1572 | ||
1573 | ||
1574 | reg = MII_TG3_MISC_SHDW_WREN | | |
1575 | MII_TG3_MISC_SHDW_APD_SEL | | |
1576 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1577 | if (enable) | |
1578 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1579 | ||
1580 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1581 | } | |
1582 | ||
9ef8ca99 MC |
1583 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1584 | { | |
1585 | u32 phy; | |
1586 | ||
1587 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
1588 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
1589 | return; | |
1590 | ||
7f97a4bd | 1591 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
9ef8ca99 MC |
1592 | u32 ephy; |
1593 | ||
535ef6e1 MC |
1594 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1595 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1596 | ||
1597 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1598 | ephy | MII_TG3_FET_SHADOW_EN); | |
1599 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1600 | if (enable) |
535ef6e1 | 1601 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1602 | else |
535ef6e1 MC |
1603 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1604 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1605 | } |
535ef6e1 | 1606 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1607 | } |
1608 | } else { | |
1609 | phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | | |
1610 | MII_TG3_AUXCTL_SHDWSEL_MISC; | |
1611 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) && | |
1612 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) { | |
1613 | if (enable) | |
1614 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1615 | else | |
1616 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1617 | phy |= MII_TG3_AUXCTL_MISC_WREN; | |
1618 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1619 | } | |
1620 | } | |
1621 | } | |
1622 | ||
1da177e4 LT |
1623 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1624 | { | |
1625 | u32 val; | |
1626 | ||
1627 | if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) | |
1628 | return; | |
1629 | ||
1630 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) && | |
1631 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) | |
1632 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1633 | (val | (1 << 15) | (1 << 4))); | |
1634 | } | |
1635 | ||
b2a5c19c MC |
1636 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1637 | { | |
1638 | u32 otp, phy; | |
1639 | ||
1640 | if (!tp->phy_otp) | |
1641 | return; | |
1642 | ||
1643 | otp = tp->phy_otp; | |
1644 | ||
1645 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1646 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1647 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1648 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1649 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1650 | ||
1651 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1652 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1653 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1654 | ||
1655 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1656 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1657 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1658 | ||
1659 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1660 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1661 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1662 | ||
1663 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1664 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1665 | ||
1666 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1667 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1668 | ||
1669 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1670 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1671 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1672 | ||
1673 | /* Turn off SM_DSP clock. */ | |
1674 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1675 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1676 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1677 | } | |
1678 | ||
1da177e4 LT |
1679 | static int tg3_wait_macro_done(struct tg3 *tp) |
1680 | { | |
1681 | int limit = 100; | |
1682 | ||
1683 | while (limit--) { | |
1684 | u32 tmp32; | |
1685 | ||
1686 | if (!tg3_readphy(tp, 0x16, &tmp32)) { | |
1687 | if ((tmp32 & 0x1000) == 0) | |
1688 | break; | |
1689 | } | |
1690 | } | |
d4675b52 | 1691 | if (limit < 0) |
1da177e4 LT |
1692 | return -EBUSY; |
1693 | ||
1694 | return 0; | |
1695 | } | |
1696 | ||
1697 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1698 | { | |
1699 | static const u32 test_pat[4][6] = { | |
1700 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1701 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1702 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1703 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1704 | }; | |
1705 | int chan; | |
1706 | ||
1707 | for (chan = 0; chan < 4; chan++) { | |
1708 | int i; | |
1709 | ||
1710 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1711 | (chan * 0x2000) | 0x0200); | |
1712 | tg3_writephy(tp, 0x16, 0x0002); | |
1713 | ||
1714 | for (i = 0; i < 6; i++) | |
1715 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1716 | test_pat[chan][i]); | |
1717 | ||
1718 | tg3_writephy(tp, 0x16, 0x0202); | |
1719 | if (tg3_wait_macro_done(tp)) { | |
1720 | *resetp = 1; | |
1721 | return -EBUSY; | |
1722 | } | |
1723 | ||
1724 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1725 | (chan * 0x2000) | 0x0200); | |
1726 | tg3_writephy(tp, 0x16, 0x0082); | |
1727 | if (tg3_wait_macro_done(tp)) { | |
1728 | *resetp = 1; | |
1729 | return -EBUSY; | |
1730 | } | |
1731 | ||
1732 | tg3_writephy(tp, 0x16, 0x0802); | |
1733 | if (tg3_wait_macro_done(tp)) { | |
1734 | *resetp = 1; | |
1735 | return -EBUSY; | |
1736 | } | |
1737 | ||
1738 | for (i = 0; i < 6; i += 2) { | |
1739 | u32 low, high; | |
1740 | ||
1741 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1742 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1743 | tg3_wait_macro_done(tp)) { | |
1744 | *resetp = 1; | |
1745 | return -EBUSY; | |
1746 | } | |
1747 | low &= 0x7fff; | |
1748 | high &= 0x000f; | |
1749 | if (low != test_pat[chan][i] || | |
1750 | high != test_pat[chan][i+1]) { | |
1751 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1752 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1753 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1754 | ||
1755 | return -EBUSY; | |
1756 | } | |
1757 | } | |
1758 | } | |
1759 | ||
1760 | return 0; | |
1761 | } | |
1762 | ||
1763 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1764 | { | |
1765 | int chan; | |
1766 | ||
1767 | for (chan = 0; chan < 4; chan++) { | |
1768 | int i; | |
1769 | ||
1770 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1771 | (chan * 0x2000) | 0x0200); | |
1772 | tg3_writephy(tp, 0x16, 0x0002); | |
1773 | for (i = 0; i < 6; i++) | |
1774 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
1775 | tg3_writephy(tp, 0x16, 0x0202); | |
1776 | if (tg3_wait_macro_done(tp)) | |
1777 | return -EBUSY; | |
1778 | } | |
1779 | ||
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1784 | { | |
1785 | u32 reg32, phy9_orig; | |
1786 | int retries, do_phy_reset, err; | |
1787 | ||
1788 | retries = 10; | |
1789 | do_phy_reset = 1; | |
1790 | do { | |
1791 | if (do_phy_reset) { | |
1792 | err = tg3_bmcr_reset(tp); | |
1793 | if (err) | |
1794 | return err; | |
1795 | do_phy_reset = 0; | |
1796 | } | |
1797 | ||
1798 | /* Disable transmitter and interrupt. */ | |
1799 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1800 | continue; | |
1801 | ||
1802 | reg32 |= 0x3000; | |
1803 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1804 | ||
1805 | /* Set full-duplex, 1000 mbps. */ | |
1806 | tg3_writephy(tp, MII_BMCR, | |
1807 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1808 | ||
1809 | /* Set to master mode. */ | |
1810 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1811 | continue; | |
1812 | ||
1813 | tg3_writephy(tp, MII_TG3_CTRL, | |
1814 | (MII_TG3_CTRL_AS_MASTER | | |
1815 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1816 | ||
1817 | /* Enable SM_DSP_CLOCK and 6dB. */ | |
1818 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1819 | ||
1820 | /* Block the PHY control access. */ | |
1821 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1822 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800); | |
1823 | ||
1824 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
1825 | if (!err) | |
1826 | break; | |
1827 | } while (--retries); | |
1828 | ||
1829 | err = tg3_phy_reset_chanpat(tp); | |
1830 | if (err) | |
1831 | return err; | |
1832 | ||
1833 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1834 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000); | |
1835 | ||
1836 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
1837 | tg3_writephy(tp, 0x16, 0x0000); | |
1838 | ||
1839 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1840 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
1841 | /* Set Extended packet length bit for jumbo frames */ | |
1842 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); | |
1843 | } | |
1844 | else { | |
1845 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1846 | } | |
1847 | ||
1848 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
1849 | ||
1850 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
1851 | reg32 &= ~0x3000; | |
1852 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1853 | } else if (!err) | |
1854 | err = -EBUSY; | |
1855 | ||
1856 | return err; | |
1857 | } | |
1858 | ||
1859 | /* This will reset the tigon3 PHY if there is no valid | |
1860 | * link unless the FORCE argument is non-zero. | |
1861 | */ | |
1862 | static int tg3_phy_reset(struct tg3 *tp) | |
1863 | { | |
b2a5c19c | 1864 | u32 cpmuctrl; |
1da177e4 LT |
1865 | u32 phy_status; |
1866 | int err; | |
1867 | ||
60189ddf MC |
1868 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
1869 | u32 val; | |
1870 | ||
1871 | val = tr32(GRC_MISC_CFG); | |
1872 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
1873 | udelay(40); | |
1874 | } | |
1da177e4 LT |
1875 | err = tg3_readphy(tp, MII_BMSR, &phy_status); |
1876 | err |= tg3_readphy(tp, MII_BMSR, &phy_status); | |
1877 | if (err != 0) | |
1878 | return -EBUSY; | |
1879 | ||
c8e1e82b MC |
1880 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
1881 | netif_carrier_off(tp->dev); | |
1882 | tg3_link_report(tp); | |
1883 | } | |
1884 | ||
1da177e4 LT |
1885 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
1886 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
1887 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
1888 | err = tg3_phy_reset_5703_4_5(tp); | |
1889 | if (err) | |
1890 | return err; | |
1891 | goto out; | |
1892 | } | |
1893 | ||
b2a5c19c MC |
1894 | cpmuctrl = 0; |
1895 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
1896 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
1897 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
1898 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
1899 | tw32(TG3_CPMU_CTRL, | |
1900 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
1901 | } | |
1902 | ||
1da177e4 LT |
1903 | err = tg3_bmcr_reset(tp); |
1904 | if (err) | |
1905 | return err; | |
1906 | ||
b2a5c19c MC |
1907 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
1908 | u32 phy; | |
1909 | ||
1910 | phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; | |
1911 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy); | |
1912 | ||
1913 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
1914 | } | |
1915 | ||
bcb37f6c MC |
1916 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
1917 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
1918 | u32 val; |
1919 | ||
1920 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | |
1921 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
1922 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
1923 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
1924 | udelay(40); | |
1925 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
1926 | } | |
1927 | } | |
1928 | ||
b2a5c19c MC |
1929 | tg3_phy_apply_otp(tp); |
1930 | ||
6833c043 MC |
1931 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) |
1932 | tg3_phy_toggle_apd(tp, true); | |
1933 | else | |
1934 | tg3_phy_toggle_apd(tp, false); | |
1935 | ||
1da177e4 LT |
1936 | out: |
1937 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) { | |
1938 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1939 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1940 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa); | |
1941 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1942 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323); | |
1943 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1944 | } | |
1945 | if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) { | |
1946 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1947 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1948 | } | |
1949 | if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) { | |
1950 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1951 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1952 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b); | |
1953 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1954 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506); | |
1955 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f); | |
1956 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); | |
1957 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1958 | } | |
c424cb24 MC |
1959 | else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) { |
1960 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1961 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
c1d2a196 MC |
1962 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) { |
1963 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
1964 | tg3_writephy(tp, MII_TG3_TEST1, | |
1965 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
1966 | } else | |
1967 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
c424cb24 MC |
1968 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
1969 | } | |
1da177e4 LT |
1970 | /* Set Extended packet length bit (bit 14) on all chips that */ |
1971 | /* support jumbo frames */ | |
1972 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
1973 | /* Cannot do read-modify-write on 5401 */ | |
1974 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
8f666b07 | 1975 | } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 LT |
1976 | u32 phy_reg; |
1977 | ||
1978 | /* Set bit 14 with read-modify-write to preserve other bits */ | |
1979 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) && | |
1980 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg)) | |
1981 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000); | |
1982 | } | |
1983 | ||
1984 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
1985 | * jumbo frames transmission. | |
1986 | */ | |
8f666b07 | 1987 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 LT |
1988 | u32 phy_reg; |
1989 | ||
1990 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) | |
1991 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
1992 | phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC); | |
1993 | } | |
1994 | ||
715116a1 | 1995 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 1996 | /* adjust output voltage */ |
535ef6e1 | 1997 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
1998 | } |
1999 | ||
9ef8ca99 | 2000 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2001 | tg3_phy_set_wirespeed(tp); |
2002 | return 0; | |
2003 | } | |
2004 | ||
2005 | static void tg3_frob_aux_power(struct tg3 *tp) | |
2006 | { | |
2007 | struct tg3 *tp_peer = tp; | |
2008 | ||
9d26e213 | 2009 | if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0) |
1da177e4 LT |
2010 | return; |
2011 | ||
f6eb9b1f MC |
2012 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
2013 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
2014 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
8c2dc7e1 MC |
2015 | struct net_device *dev_peer; |
2016 | ||
2017 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
bc1c7567 | 2018 | /* remove_one() may have been run on the peer. */ |
8c2dc7e1 | 2019 | if (!dev_peer) |
bc1c7567 MC |
2020 | tp_peer = tp; |
2021 | else | |
2022 | tp_peer = netdev_priv(dev_peer); | |
1da177e4 LT |
2023 | } |
2024 | ||
1da177e4 | 2025 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || |
6921d201 MC |
2026 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 || |
2027 | (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || | |
2028 | (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { | |
1da177e4 LT |
2029 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2030 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
b401e9e2 MC |
2031 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2032 | (GRC_LCLCTRL_GPIO_OE0 | | |
2033 | GRC_LCLCTRL_GPIO_OE1 | | |
2034 | GRC_LCLCTRL_GPIO_OE2 | | |
2035 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2036 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2037 | 100); | |
8d519ab2 MC |
2038 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
2039 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
2040 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ |
2041 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2042 | GRC_LCLCTRL_GPIO_OE1 | | |
2043 | GRC_LCLCTRL_GPIO_OE2 | | |
2044 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2045 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2046 | tp->grc_local_ctrl; | |
2047 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2048 | ||
2049 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2050 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2051 | ||
2052 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2053 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1da177e4 LT |
2054 | } else { |
2055 | u32 no_gpio2; | |
dc56b7d4 | 2056 | u32 grc_local_ctrl = 0; |
1da177e4 LT |
2057 | |
2058 | if (tp_peer != tp && | |
2059 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2060 | return; | |
2061 | ||
dc56b7d4 MC |
2062 | /* Workaround to prevent overdrawing Amps. */ |
2063 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2064 | ASIC_REV_5714) { | |
2065 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
b401e9e2 MC |
2066 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2067 | grc_local_ctrl, 100); | |
dc56b7d4 MC |
2068 | } |
2069 | ||
1da177e4 LT |
2070 | /* On 5753 and variants, GPIO2 cannot be used. */ |
2071 | no_gpio2 = tp->nic_sram_data_cfg & | |
2072 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2073 | ||
dc56b7d4 | 2074 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | |
1da177e4 LT |
2075 | GRC_LCLCTRL_GPIO_OE1 | |
2076 | GRC_LCLCTRL_GPIO_OE2 | | |
2077 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2078 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2079 | if (no_gpio2) { | |
2080 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2081 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2082 | } | |
b401e9e2 MC |
2083 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2084 | grc_local_ctrl, 100); | |
1da177e4 LT |
2085 | |
2086 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2087 | ||
b401e9e2 MC |
2088 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2089 | grc_local_ctrl, 100); | |
1da177e4 LT |
2090 | |
2091 | if (!no_gpio2) { | |
2092 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
b401e9e2 MC |
2093 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2094 | grc_local_ctrl, 100); | |
1da177e4 LT |
2095 | } |
2096 | } | |
2097 | } else { | |
2098 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2099 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
2100 | if (tp_peer != tp && | |
2101 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2102 | return; | |
2103 | ||
b401e9e2 MC |
2104 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2105 | (GRC_LCLCTRL_GPIO_OE1 | | |
2106 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 | 2107 | |
b401e9e2 MC |
2108 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2109 | GRC_LCLCTRL_GPIO_OE1, 100); | |
1da177e4 | 2110 | |
b401e9e2 MC |
2111 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2112 | (GRC_LCLCTRL_GPIO_OE1 | | |
2113 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 LT |
2114 | } |
2115 | } | |
2116 | } | |
2117 | ||
e8f3f6ca MC |
2118 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2119 | { | |
2120 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2121 | return 1; | |
2122 | else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) { | |
2123 | if (speed != SPEED_10) | |
2124 | return 1; | |
2125 | } else if (speed == SPEED_10) | |
2126 | return 1; | |
2127 | ||
2128 | return 0; | |
2129 | } | |
2130 | ||
1da177e4 LT |
2131 | static int tg3_setup_phy(struct tg3 *, int); |
2132 | ||
2133 | #define RESET_KIND_SHUTDOWN 0 | |
2134 | #define RESET_KIND_INIT 1 | |
2135 | #define RESET_KIND_SUSPEND 2 | |
2136 | ||
2137 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2138 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2139 | ||
0a459aac | 2140 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2141 | { |
ce057f01 MC |
2142 | u32 val; |
2143 | ||
5129724a MC |
2144 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { |
2145 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2146 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2147 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2148 | ||
2149 | sg_dig_ctrl |= | |
2150 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2151 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2152 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2153 | } | |
3f7045c1 | 2154 | return; |
5129724a | 2155 | } |
3f7045c1 | 2156 | |
60189ddf | 2157 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2158 | tg3_bmcr_reset(tp); |
2159 | val = tr32(GRC_MISC_CFG); | |
2160 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2161 | udelay(40); | |
2162 | return; | |
0e5f784c MC |
2163 | } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
2164 | u32 phytest; | |
2165 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2166 | u32 phy; | |
2167 | ||
2168 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2169 | tg3_writephy(tp, MII_BMCR, | |
2170 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2171 | ||
2172 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2173 | phytest | MII_TG3_FET_SHADOW_EN); | |
2174 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2175 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2176 | tg3_writephy(tp, | |
2177 | MII_TG3_FET_SHDW_AUXMODE4, | |
2178 | phy); | |
2179 | } | |
2180 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2181 | } | |
2182 | return; | |
0a459aac | 2183 | } else if (do_low_power) { |
715116a1 MC |
2184 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2185 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac MC |
2186 | |
2187 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
2188 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL | | |
2189 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2190 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2191 | MII_TG3_AUXCTL_PCTL_VREG_11V); | |
715116a1 | 2192 | } |
3f7045c1 | 2193 | |
15c3b696 MC |
2194 | /* The PHY should not be powered down on some chips because |
2195 | * of bugs. | |
2196 | */ | |
2197 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2198 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2199 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
2200 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) | |
2201 | return; | |
ce057f01 | 2202 | |
bcb37f6c MC |
2203 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2204 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2205 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2206 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2207 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2208 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2209 | } | |
2210 | ||
15c3b696 MC |
2211 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2212 | } | |
2213 | ||
ffbcfed4 MC |
2214 | /* tp->lock is held. */ |
2215 | static int tg3_nvram_lock(struct tg3 *tp) | |
2216 | { | |
2217 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2218 | int i; | |
2219 | ||
2220 | if (tp->nvram_lock_cnt == 0) { | |
2221 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2222 | for (i = 0; i < 8000; i++) { | |
2223 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2224 | break; | |
2225 | udelay(20); | |
2226 | } | |
2227 | if (i == 8000) { | |
2228 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2229 | return -ENODEV; | |
2230 | } | |
2231 | } | |
2232 | tp->nvram_lock_cnt++; | |
2233 | } | |
2234 | return 0; | |
2235 | } | |
2236 | ||
2237 | /* tp->lock is held. */ | |
2238 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2239 | { | |
2240 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2241 | if (tp->nvram_lock_cnt > 0) | |
2242 | tp->nvram_lock_cnt--; | |
2243 | if (tp->nvram_lock_cnt == 0) | |
2244 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2245 | } | |
2246 | } | |
2247 | ||
2248 | /* tp->lock is held. */ | |
2249 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2250 | { | |
2251 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2252 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2253 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2254 | ||
2255 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2256 | } | |
2257 | } | |
2258 | ||
2259 | /* tp->lock is held. */ | |
2260 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2261 | { | |
2262 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2263 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2264 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2265 | ||
2266 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2267 | } | |
2268 | } | |
2269 | ||
2270 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2271 | u32 offset, u32 *val) | |
2272 | { | |
2273 | u32 tmp; | |
2274 | int i; | |
2275 | ||
2276 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2277 | return -EINVAL; | |
2278 | ||
2279 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2280 | EEPROM_ADDR_DEVID_MASK | | |
2281 | EEPROM_ADDR_READ); | |
2282 | tw32(GRC_EEPROM_ADDR, | |
2283 | tmp | | |
2284 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2285 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2286 | EEPROM_ADDR_ADDR_MASK) | | |
2287 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2288 | ||
2289 | for (i = 0; i < 1000; i++) { | |
2290 | tmp = tr32(GRC_EEPROM_ADDR); | |
2291 | ||
2292 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2293 | break; | |
2294 | msleep(1); | |
2295 | } | |
2296 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2297 | return -EBUSY; | |
2298 | ||
62cedd11 MC |
2299 | tmp = tr32(GRC_EEPROM_DATA); |
2300 | ||
2301 | /* | |
2302 | * The data will always be opposite the native endian | |
2303 | * format. Perform a blind byteswap to compensate. | |
2304 | */ | |
2305 | *val = swab32(tmp); | |
2306 | ||
ffbcfed4 MC |
2307 | return 0; |
2308 | } | |
2309 | ||
2310 | #define NVRAM_CMD_TIMEOUT 10000 | |
2311 | ||
2312 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2313 | { | |
2314 | int i; | |
2315 | ||
2316 | tw32(NVRAM_CMD, nvram_cmd); | |
2317 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2318 | udelay(10); | |
2319 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2320 | udelay(10); | |
2321 | break; | |
2322 | } | |
2323 | } | |
2324 | ||
2325 | if (i == NVRAM_CMD_TIMEOUT) | |
2326 | return -EBUSY; | |
2327 | ||
2328 | return 0; | |
2329 | } | |
2330 | ||
2331 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2332 | { | |
2333 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2334 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2335 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2336 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2337 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2338 | ||
2339 | addr = ((addr / tp->nvram_pagesize) << | |
2340 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2341 | (addr % tp->nvram_pagesize); | |
2342 | ||
2343 | return addr; | |
2344 | } | |
2345 | ||
2346 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2347 | { | |
2348 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2349 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2350 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2351 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2352 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2353 | ||
2354 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2355 | tp->nvram_pagesize) + | |
2356 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2357 | ||
2358 | return addr; | |
2359 | } | |
2360 | ||
e4f34110 MC |
2361 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2362 | * the byteswapping settings for all other register accesses. | |
2363 | * tg3 devices are BE devices, so on a BE machine, the data | |
2364 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2365 | * machine, the 32-bit value will be byteswapped. | |
2366 | */ | |
ffbcfed4 MC |
2367 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2368 | { | |
2369 | int ret; | |
2370 | ||
2371 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | |
2372 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
2373 | ||
2374 | offset = tg3_nvram_phys_addr(tp, offset); | |
2375 | ||
2376 | if (offset > NVRAM_ADDR_MSK) | |
2377 | return -EINVAL; | |
2378 | ||
2379 | ret = tg3_nvram_lock(tp); | |
2380 | if (ret) | |
2381 | return ret; | |
2382 | ||
2383 | tg3_enable_nvram_access(tp); | |
2384 | ||
2385 | tw32(NVRAM_ADDR, offset); | |
2386 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2387 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2388 | ||
2389 | if (ret == 0) | |
e4f34110 | 2390 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2391 | |
2392 | tg3_disable_nvram_access(tp); | |
2393 | ||
2394 | tg3_nvram_unlock(tp); | |
2395 | ||
2396 | return ret; | |
2397 | } | |
2398 | ||
a9dc529d MC |
2399 | /* Ensures NVRAM data is in bytestream format. */ |
2400 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2401 | { |
2402 | u32 v; | |
a9dc529d | 2403 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2404 | if (!res) |
a9dc529d | 2405 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2406 | return res; |
2407 | } | |
2408 | ||
3f007891 MC |
2409 | /* tp->lock is held. */ |
2410 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2411 | { | |
2412 | u32 addr_high, addr_low; | |
2413 | int i; | |
2414 | ||
2415 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2416 | tp->dev->dev_addr[1]); | |
2417 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2418 | (tp->dev->dev_addr[3] << 16) | | |
2419 | (tp->dev->dev_addr[4] << 8) | | |
2420 | (tp->dev->dev_addr[5] << 0)); | |
2421 | for (i = 0; i < 4; i++) { | |
2422 | if (i == 1 && skip_mac_1) | |
2423 | continue; | |
2424 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2425 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2426 | } | |
2427 | ||
2428 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2429 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2430 | for (i = 0; i < 12; i++) { | |
2431 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2432 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2433 | } | |
2434 | } | |
2435 | ||
2436 | addr_high = (tp->dev->dev_addr[0] + | |
2437 | tp->dev->dev_addr[1] + | |
2438 | tp->dev->dev_addr[2] + | |
2439 | tp->dev->dev_addr[3] + | |
2440 | tp->dev->dev_addr[4] + | |
2441 | tp->dev->dev_addr[5]) & | |
2442 | TX_BACKOFF_SEED_MASK; | |
2443 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2444 | } | |
2445 | ||
bc1c7567 | 2446 | static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) |
1da177e4 LT |
2447 | { |
2448 | u32 misc_host_ctrl; | |
0a459aac | 2449 | bool device_should_wake, do_low_power; |
1da177e4 LT |
2450 | |
2451 | /* Make sure register accesses (indirect or otherwise) | |
2452 | * will function correctly. | |
2453 | */ | |
2454 | pci_write_config_dword(tp->pdev, | |
2455 | TG3PCI_MISC_HOST_CTRL, | |
2456 | tp->misc_host_ctrl); | |
2457 | ||
1da177e4 | 2458 | switch (state) { |
bc1c7567 | 2459 | case PCI_D0: |
12dac075 RW |
2460 | pci_enable_wake(tp->pdev, state, false); |
2461 | pci_set_power_state(tp->pdev, PCI_D0); | |
8c6bda1a | 2462 | |
9d26e213 MC |
2463 | /* Switch out of Vaux if it is a NIC */ |
2464 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
b401e9e2 | 2465 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); |
1da177e4 LT |
2466 | |
2467 | return 0; | |
2468 | ||
bc1c7567 | 2469 | case PCI_D1: |
bc1c7567 | 2470 | case PCI_D2: |
bc1c7567 | 2471 | case PCI_D3hot: |
1da177e4 LT |
2472 | break; |
2473 | ||
2474 | default: | |
12dac075 RW |
2475 | printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n", |
2476 | tp->dev->name, state); | |
1da177e4 | 2477 | return -EINVAL; |
855e1111 | 2478 | } |
5e7dfd0f MC |
2479 | |
2480 | /* Restore the CLKREQ setting. */ | |
2481 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2482 | u16 lnkctl; | |
2483 | ||
2484 | pci_read_config_word(tp->pdev, | |
2485 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2486 | &lnkctl); | |
2487 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2488 | pci_write_config_word(tp->pdev, | |
2489 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2490 | lnkctl); | |
2491 | } | |
2492 | ||
1da177e4 LT |
2493 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2494 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2495 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2496 | ||
05ac4cb7 MC |
2497 | device_should_wake = pci_pme_capable(tp->pdev, state) && |
2498 | device_may_wakeup(&tp->pdev->dev) && | |
2499 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
2500 | ||
dd477003 | 2501 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
0a459aac | 2502 | do_low_power = false; |
b02fd9e3 MC |
2503 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) && |
2504 | !tp->link_config.phy_is_low_power) { | |
2505 | struct phy_device *phydev; | |
0a459aac | 2506 | u32 phyid, advertising; |
b02fd9e3 | 2507 | |
3f0e3ad7 | 2508 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
2509 | |
2510 | tp->link_config.phy_is_low_power = 1; | |
2511 | ||
2512 | tp->link_config.orig_speed = phydev->speed; | |
2513 | tp->link_config.orig_duplex = phydev->duplex; | |
2514 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2515 | tp->link_config.orig_advertising = phydev->advertising; | |
2516 | ||
2517 | advertising = ADVERTISED_TP | | |
2518 | ADVERTISED_Pause | | |
2519 | ADVERTISED_Autoneg | | |
2520 | ADVERTISED_10baseT_Half; | |
2521 | ||
2522 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
05ac4cb7 | 2523 | device_should_wake) { |
b02fd9e3 MC |
2524 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) |
2525 | advertising |= | |
2526 | ADVERTISED_100baseT_Half | | |
2527 | ADVERTISED_100baseT_Full | | |
2528 | ADVERTISED_10baseT_Full; | |
2529 | else | |
2530 | advertising |= ADVERTISED_10baseT_Full; | |
2531 | } | |
2532 | ||
2533 | phydev->advertising = advertising; | |
2534 | ||
2535 | phy_start_aneg(phydev); | |
0a459aac MC |
2536 | |
2537 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
2538 | if (phyid != TG3_PHY_ID_BCMAC131) { | |
2539 | phyid &= TG3_PHY_OUI_MASK; | |
f72b5349 RK |
2540 | if (phyid == TG3_PHY_OUI_1 || |
2541 | phyid == TG3_PHY_OUI_2 || | |
0a459aac MC |
2542 | phyid == TG3_PHY_OUI_3) |
2543 | do_low_power = true; | |
2544 | } | |
b02fd9e3 | 2545 | } |
dd477003 | 2546 | } else { |
2023276e | 2547 | do_low_power = true; |
0a459aac | 2548 | |
dd477003 MC |
2549 | if (tp->link_config.phy_is_low_power == 0) { |
2550 | tp->link_config.phy_is_low_power = 1; | |
2551 | tp->link_config.orig_speed = tp->link_config.speed; | |
2552 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2553 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2554 | } | |
1da177e4 | 2555 | |
dd477003 MC |
2556 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { |
2557 | tp->link_config.speed = SPEED_10; | |
2558 | tp->link_config.duplex = DUPLEX_HALF; | |
2559 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2560 | tg3_setup_phy(tp, 0); | |
2561 | } | |
1da177e4 LT |
2562 | } |
2563 | ||
b5d3772c MC |
2564 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2565 | u32 val; | |
2566 | ||
2567 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2568 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2569 | } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
6921d201 MC |
2570 | int i; |
2571 | u32 val; | |
2572 | ||
2573 | for (i = 0; i < 200; i++) { | |
2574 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2575 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2576 | break; | |
2577 | msleep(1); | |
2578 | } | |
2579 | } | |
a85feb8c GZ |
2580 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
2581 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2582 | WOL_DRV_STATE_SHUTDOWN | | |
2583 | WOL_DRV_WOL | | |
2584 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2585 | |
05ac4cb7 | 2586 | if (device_should_wake) { |
1da177e4 LT |
2587 | u32 mac_mode; |
2588 | ||
2589 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
0a459aac | 2590 | if (do_low_power) { |
dd477003 MC |
2591 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); |
2592 | udelay(40); | |
2593 | } | |
1da177e4 | 2594 | |
3f7045c1 MC |
2595 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
2596 | mac_mode = MAC_MODE_PORT_MODE_GMII; | |
2597 | else | |
2598 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2599 | |
e8f3f6ca MC |
2600 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2601 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2602 | ASIC_REV_5700) { | |
2603 | u32 speed = (tp->tg3_flags & | |
2604 | TG3_FLAG_WOL_SPEED_100MB) ? | |
2605 | SPEED_100 : SPEED_10; | |
2606 | if (tg3_5700_link_polarity(tp, speed)) | |
2607 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2608 | else | |
2609 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2610 | } | |
1da177e4 LT |
2611 | } else { |
2612 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2613 | } | |
2614 | ||
cbf46853 | 2615 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) |
1da177e4 LT |
2616 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2617 | ||
05ac4cb7 MC |
2618 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
2619 | if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
2620 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && | |
2621 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2622 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))) | |
2623 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
1da177e4 | 2624 | |
3bda1258 MC |
2625 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
2626 | mac_mode |= tp->mac_mode & | |
2627 | (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
2628 | if (mac_mode & MAC_MODE_APE_TX_EN) | |
2629 | mac_mode |= MAC_MODE_TDE_ENABLE; | |
2630 | } | |
2631 | ||
1da177e4 LT |
2632 | tw32_f(MAC_MODE, mac_mode); |
2633 | udelay(100); | |
2634 | ||
2635 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2636 | udelay(10); | |
2637 | } | |
2638 | ||
2639 | if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && | |
2640 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2641 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2642 | u32 base_val; | |
2643 | ||
2644 | base_val = tp->pci_clock_ctrl; | |
2645 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2646 | CLOCK_CTRL_TXCLK_DISABLE); | |
2647 | ||
b401e9e2 MC |
2648 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2649 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
d7b0a857 | 2650 | } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
795d01c5 | 2651 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
d7b0a857 | 2652 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { |
4cf78e4f | 2653 | /* do nothing */ |
85e94ced | 2654 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
1da177e4 LT |
2655 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { |
2656 | u32 newbits1, newbits2; | |
2657 | ||
2658 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2659 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2660 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2661 | CLOCK_CTRL_TXCLK_DISABLE | | |
2662 | CLOCK_CTRL_ALTCLK); | |
2663 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2664 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
2665 | newbits1 = CLOCK_CTRL_625_CORE; | |
2666 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2667 | } else { | |
2668 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2669 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2670 | } | |
2671 | ||
b401e9e2 MC |
2672 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2673 | 40); | |
1da177e4 | 2674 | |
b401e9e2 MC |
2675 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2676 | 40); | |
1da177e4 LT |
2677 | |
2678 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
2679 | u32 newbits3; | |
2680 | ||
2681 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2682 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2683 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2684 | CLOCK_CTRL_TXCLK_DISABLE | | |
2685 | CLOCK_CTRL_44MHZ_CORE); | |
2686 | } else { | |
2687 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2688 | } | |
2689 | ||
b401e9e2 MC |
2690 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
2691 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
2692 | } |
2693 | } | |
2694 | ||
05ac4cb7 | 2695 | if (!(device_should_wake) && |
22435849 | 2696 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
0a459aac | 2697 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 2698 | |
1da177e4 LT |
2699 | tg3_frob_aux_power(tp); |
2700 | ||
2701 | /* Workaround for unstable PLL clock */ | |
2702 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2703 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2704 | u32 val = tr32(0x7d00); | |
2705 | ||
2706 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2707 | tw32(0x7d00, val); | |
6921d201 | 2708 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
ec41c7df MC |
2709 | int err; |
2710 | ||
2711 | err = tg3_nvram_lock(tp); | |
1da177e4 | 2712 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
2713 | if (!err) |
2714 | tg3_nvram_unlock(tp); | |
6921d201 | 2715 | } |
1da177e4 LT |
2716 | } |
2717 | ||
bbadf503 MC |
2718 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
2719 | ||
05ac4cb7 | 2720 | if (device_should_wake) |
12dac075 RW |
2721 | pci_enable_wake(tp->pdev, state, true); |
2722 | ||
1da177e4 | 2723 | /* Finally, set the new power state. */ |
12dac075 | 2724 | pci_set_power_state(tp->pdev, state); |
1da177e4 | 2725 | |
1da177e4 LT |
2726 | return 0; |
2727 | } | |
2728 | ||
1da177e4 LT |
2729 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
2730 | { | |
2731 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2732 | case MII_TG3_AUX_STAT_10HALF: | |
2733 | *speed = SPEED_10; | |
2734 | *duplex = DUPLEX_HALF; | |
2735 | break; | |
2736 | ||
2737 | case MII_TG3_AUX_STAT_10FULL: | |
2738 | *speed = SPEED_10; | |
2739 | *duplex = DUPLEX_FULL; | |
2740 | break; | |
2741 | ||
2742 | case MII_TG3_AUX_STAT_100HALF: | |
2743 | *speed = SPEED_100; | |
2744 | *duplex = DUPLEX_HALF; | |
2745 | break; | |
2746 | ||
2747 | case MII_TG3_AUX_STAT_100FULL: | |
2748 | *speed = SPEED_100; | |
2749 | *duplex = DUPLEX_FULL; | |
2750 | break; | |
2751 | ||
2752 | case MII_TG3_AUX_STAT_1000HALF: | |
2753 | *speed = SPEED_1000; | |
2754 | *duplex = DUPLEX_HALF; | |
2755 | break; | |
2756 | ||
2757 | case MII_TG3_AUX_STAT_1000FULL: | |
2758 | *speed = SPEED_1000; | |
2759 | *duplex = DUPLEX_FULL; | |
2760 | break; | |
2761 | ||
2762 | default: | |
7f97a4bd | 2763 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
715116a1 MC |
2764 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
2765 | SPEED_10; | |
2766 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2767 | DUPLEX_HALF; | |
2768 | break; | |
2769 | } | |
1da177e4 LT |
2770 | *speed = SPEED_INVALID; |
2771 | *duplex = DUPLEX_INVALID; | |
2772 | break; | |
855e1111 | 2773 | } |
1da177e4 LT |
2774 | } |
2775 | ||
2776 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
2777 | { | |
2778 | u32 new_adv; | |
2779 | int i; | |
2780 | ||
2781 | if (tp->link_config.phy_is_low_power) { | |
2782 | /* Entering low power mode. Disable gigabit and | |
2783 | * 100baseT advertisements. | |
2784 | */ | |
2785 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2786 | ||
2787 | new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2788 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
2789 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2790 | new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); | |
2791 | ||
2792 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2793 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
1da177e4 LT |
2794 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) |
2795 | tp->link_config.advertising &= | |
2796 | ~(ADVERTISED_1000baseT_Half | | |
2797 | ADVERTISED_1000baseT_Full); | |
2798 | ||
ba4d07a8 | 2799 | new_adv = ADVERTISE_CSMA; |
1da177e4 LT |
2800 | if (tp->link_config.advertising & ADVERTISED_10baseT_Half) |
2801 | new_adv |= ADVERTISE_10HALF; | |
2802 | if (tp->link_config.advertising & ADVERTISED_10baseT_Full) | |
2803 | new_adv |= ADVERTISE_10FULL; | |
2804 | if (tp->link_config.advertising & ADVERTISED_100baseT_Half) | |
2805 | new_adv |= ADVERTISE_100HALF; | |
2806 | if (tp->link_config.advertising & ADVERTISED_100baseT_Full) | |
2807 | new_adv |= ADVERTISE_100FULL; | |
ba4d07a8 MC |
2808 | |
2809 | new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2810 | ||
1da177e4 LT |
2811 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2812 | ||
2813 | if (tp->link_config.advertising & | |
2814 | (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { | |
2815 | new_adv = 0; | |
2816 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
2817 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2818 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
2819 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
2820 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) && | |
2821 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2822 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) | |
2823 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2824 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2825 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2826 | } else { | |
2827 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2828 | } | |
2829 | } else { | |
ba4d07a8 MC |
2830 | new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); |
2831 | new_adv |= ADVERTISE_CSMA; | |
2832 | ||
1da177e4 LT |
2833 | /* Asking for a specific link mode. */ |
2834 | if (tp->link_config.speed == SPEED_1000) { | |
1da177e4 LT |
2835 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2836 | ||
2837 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2838 | new_adv = MII_TG3_CTRL_ADV_1000_FULL; | |
2839 | else | |
2840 | new_adv = MII_TG3_CTRL_ADV_1000_HALF; | |
2841 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2842 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2843 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2844 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
1da177e4 | 2845 | } else { |
1da177e4 LT |
2846 | if (tp->link_config.speed == SPEED_100) { |
2847 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2848 | new_adv |= ADVERTISE_100FULL; | |
2849 | else | |
2850 | new_adv |= ADVERTISE_100HALF; | |
2851 | } else { | |
2852 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2853 | new_adv |= ADVERTISE_10FULL; | |
2854 | else | |
2855 | new_adv |= ADVERTISE_10HALF; | |
2856 | } | |
2857 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
ba4d07a8 MC |
2858 | |
2859 | new_adv = 0; | |
1da177e4 | 2860 | } |
ba4d07a8 MC |
2861 | |
2862 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
1da177e4 LT |
2863 | } |
2864 | ||
2865 | if (tp->link_config.autoneg == AUTONEG_DISABLE && | |
2866 | tp->link_config.speed != SPEED_INVALID) { | |
2867 | u32 bmcr, orig_bmcr; | |
2868 | ||
2869 | tp->link_config.active_speed = tp->link_config.speed; | |
2870 | tp->link_config.active_duplex = tp->link_config.duplex; | |
2871 | ||
2872 | bmcr = 0; | |
2873 | switch (tp->link_config.speed) { | |
2874 | default: | |
2875 | case SPEED_10: | |
2876 | break; | |
2877 | ||
2878 | case SPEED_100: | |
2879 | bmcr |= BMCR_SPEED100; | |
2880 | break; | |
2881 | ||
2882 | case SPEED_1000: | |
2883 | bmcr |= TG3_BMCR_SPEED1000; | |
2884 | break; | |
855e1111 | 2885 | } |
1da177e4 LT |
2886 | |
2887 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2888 | bmcr |= BMCR_FULLDPLX; | |
2889 | ||
2890 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
2891 | (bmcr != orig_bmcr)) { | |
2892 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
2893 | for (i = 0; i < 1500; i++) { | |
2894 | u32 tmp; | |
2895 | ||
2896 | udelay(10); | |
2897 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
2898 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
2899 | continue; | |
2900 | if (!(tmp & BMSR_LSTATUS)) { | |
2901 | udelay(40); | |
2902 | break; | |
2903 | } | |
2904 | } | |
2905 | tg3_writephy(tp, MII_BMCR, bmcr); | |
2906 | udelay(40); | |
2907 | } | |
2908 | } else { | |
2909 | tg3_writephy(tp, MII_BMCR, | |
2910 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2911 | } | |
2912 | } | |
2913 | ||
2914 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
2915 | { | |
2916 | int err; | |
2917 | ||
2918 | /* Turn off tap power management. */ | |
2919 | /* Set Extended packet length bit */ | |
2920 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
2921 | ||
2922 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012); | |
2923 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804); | |
2924 | ||
2925 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013); | |
2926 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204); | |
2927 | ||
2928 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2929 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132); | |
2930 | ||
2931 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2932 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232); | |
2933 | ||
2934 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
2935 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20); | |
2936 | ||
2937 | udelay(40); | |
2938 | ||
2939 | return err; | |
2940 | } | |
2941 | ||
3600d918 | 2942 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 2943 | { |
3600d918 MC |
2944 | u32 adv_reg, all_mask = 0; |
2945 | ||
2946 | if (mask & ADVERTISED_10baseT_Half) | |
2947 | all_mask |= ADVERTISE_10HALF; | |
2948 | if (mask & ADVERTISED_10baseT_Full) | |
2949 | all_mask |= ADVERTISE_10FULL; | |
2950 | if (mask & ADVERTISED_100baseT_Half) | |
2951 | all_mask |= ADVERTISE_100HALF; | |
2952 | if (mask & ADVERTISED_100baseT_Full) | |
2953 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
2954 | |
2955 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
2956 | return 0; | |
2957 | ||
1da177e4 LT |
2958 | if ((adv_reg & all_mask) != all_mask) |
2959 | return 0; | |
2960 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
2961 | u32 tg3_ctrl; | |
2962 | ||
3600d918 MC |
2963 | all_mask = 0; |
2964 | if (mask & ADVERTISED_1000baseT_Half) | |
2965 | all_mask |= ADVERTISE_1000HALF; | |
2966 | if (mask & ADVERTISED_1000baseT_Full) | |
2967 | all_mask |= ADVERTISE_1000FULL; | |
2968 | ||
1da177e4 LT |
2969 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) |
2970 | return 0; | |
2971 | ||
1da177e4 LT |
2972 | if ((tg3_ctrl & all_mask) != all_mask) |
2973 | return 0; | |
2974 | } | |
2975 | return 1; | |
2976 | } | |
2977 | ||
ef167e27 MC |
2978 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
2979 | { | |
2980 | u32 curadv, reqadv; | |
2981 | ||
2982 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
2983 | return 1; | |
2984 | ||
2985 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
2986 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2987 | ||
2988 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
2989 | if (curadv != reqadv) | |
2990 | return 0; | |
2991 | ||
2992 | if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) | |
2993 | tg3_readphy(tp, MII_LPA, rmtadv); | |
2994 | } else { | |
2995 | /* Reprogram the advertisement register, even if it | |
2996 | * does not affect the current link. If the link | |
2997 | * gets renegotiated in the future, we can save an | |
2998 | * additional renegotiation cycle by advertising | |
2999 | * it correctly in the first place. | |
3000 | */ | |
3001 | if (curadv != reqadv) { | |
3002 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3003 | ADVERTISE_PAUSE_ASYM); | |
3004 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3005 | } | |
3006 | } | |
3007 | ||
3008 | return 1; | |
3009 | } | |
3010 | ||
1da177e4 LT |
3011 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3012 | { | |
3013 | int current_link_up; | |
3014 | u32 bmsr, dummy; | |
ef167e27 | 3015 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3016 | u16 current_speed; |
3017 | u8 current_duplex; | |
3018 | int i, err; | |
3019 | ||
3020 | tw32(MAC_EVENT, 0); | |
3021 | ||
3022 | tw32_f(MAC_STATUS, | |
3023 | (MAC_STATUS_SYNC_CHANGED | | |
3024 | MAC_STATUS_CFG_CHANGED | | |
3025 | MAC_STATUS_MI_COMPLETION | | |
3026 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3027 | udelay(40); | |
3028 | ||
8ef21428 MC |
3029 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3030 | tw32_f(MAC_MI_MODE, | |
3031 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3032 | udelay(80); | |
3033 | } | |
1da177e4 LT |
3034 | |
3035 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); | |
3036 | ||
3037 | /* Some third-party PHYs need to be reset on link going | |
3038 | * down. | |
3039 | */ | |
3040 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3041 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3042 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3043 | netif_carrier_ok(tp->dev)) { | |
3044 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3045 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3046 | !(bmsr & BMSR_LSTATUS)) | |
3047 | force_reset = 1; | |
3048 | } | |
3049 | if (force_reset) | |
3050 | tg3_phy_reset(tp); | |
3051 | ||
3052 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
3053 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3054 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
3055 | !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) | |
3056 | bmsr = 0; | |
3057 | ||
3058 | if (!(bmsr & BMSR_LSTATUS)) { | |
3059 | err = tg3_init_5401phy_dsp(tp); | |
3060 | if (err) | |
3061 | return err; | |
3062 | ||
3063 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3064 | for (i = 0; i < 1000; i++) { | |
3065 | udelay(10); | |
3066 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3067 | (bmsr & BMSR_LSTATUS)) { | |
3068 | udelay(40); | |
3069 | break; | |
3070 | } | |
3071 | } | |
3072 | ||
3073 | if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 && | |
3074 | !(bmsr & BMSR_LSTATUS) && | |
3075 | tp->link_config.active_speed == SPEED_1000) { | |
3076 | err = tg3_phy_reset(tp); | |
3077 | if (!err) | |
3078 | err = tg3_init_5401phy_dsp(tp); | |
3079 | if (err) | |
3080 | return err; | |
3081 | } | |
3082 | } | |
3083 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3084 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3085 | /* 5701 {A0,B0} CRC bug workaround */ | |
3086 | tg3_writephy(tp, 0x15, 0x0a75); | |
3087 | tg3_writephy(tp, 0x1c, 0x8c68); | |
3088 | tg3_writephy(tp, 0x1c, 0x8d68); | |
3089 | tg3_writephy(tp, 0x1c, 0x8c68); | |
3090 | } | |
3091 | ||
3092 | /* Clear pending interrupts... */ | |
3093 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
3094 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
3095 | ||
3096 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) | |
3097 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); | |
7f97a4bd | 3098 | else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) |
1da177e4 LT |
3099 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3100 | ||
3101 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3102 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3103 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3104 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3105 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3106 | else | |
3107 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3108 | } | |
3109 | ||
3110 | current_link_up = 0; | |
3111 | current_speed = SPEED_INVALID; | |
3112 | current_duplex = DUPLEX_INVALID; | |
3113 | ||
3114 | if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) { | |
3115 | u32 val; | |
3116 | ||
3117 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007); | |
3118 | tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); | |
3119 | if (!(val & (1 << 10))) { | |
3120 | val |= (1 << 10); | |
3121 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
3122 | goto relink; | |
3123 | } | |
3124 | } | |
3125 | ||
3126 | bmsr = 0; | |
3127 | for (i = 0; i < 100; i++) { | |
3128 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3129 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3130 | (bmsr & BMSR_LSTATUS)) | |
3131 | break; | |
3132 | udelay(40); | |
3133 | } | |
3134 | ||
3135 | if (bmsr & BMSR_LSTATUS) { | |
3136 | u32 aux_stat, bmcr; | |
3137 | ||
3138 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3139 | for (i = 0; i < 2000; i++) { | |
3140 | udelay(10); | |
3141 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3142 | aux_stat) | |
3143 | break; | |
3144 | } | |
3145 | ||
3146 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3147 | ¤t_speed, | |
3148 | ¤t_duplex); | |
3149 | ||
3150 | bmcr = 0; | |
3151 | for (i = 0; i < 200; i++) { | |
3152 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3153 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3154 | continue; | |
3155 | if (bmcr && bmcr != 0x7fff) | |
3156 | break; | |
3157 | udelay(10); | |
3158 | } | |
3159 | ||
ef167e27 MC |
3160 | lcl_adv = 0; |
3161 | rmt_adv = 0; | |
1da177e4 | 3162 | |
ef167e27 MC |
3163 | tp->link_config.active_speed = current_speed; |
3164 | tp->link_config.active_duplex = current_duplex; | |
3165 | ||
3166 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3167 | if ((bmcr & BMCR_ANENABLE) && | |
3168 | tg3_copper_is_advertising_all(tp, | |
3169 | tp->link_config.advertising)) { | |
3170 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3171 | &rmt_adv)) | |
3172 | current_link_up = 1; | |
1da177e4 LT |
3173 | } |
3174 | } else { | |
3175 | if (!(bmcr & BMCR_ANENABLE) && | |
3176 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3177 | tp->link_config.duplex == current_duplex && |
3178 | tp->link_config.flowctrl == | |
3179 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3180 | current_link_up = 1; |
1da177e4 LT |
3181 | } |
3182 | } | |
3183 | ||
ef167e27 MC |
3184 | if (current_link_up == 1 && |
3185 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3186 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3187 | } |
3188 | ||
1da177e4 | 3189 | relink: |
6921d201 | 3190 | if (current_link_up == 0 || tp->link_config.phy_is_low_power) { |
1da177e4 LT |
3191 | u32 tmp; |
3192 | ||
3193 | tg3_phy_copper_begin(tp); | |
3194 | ||
3195 | tg3_readphy(tp, MII_BMSR, &tmp); | |
3196 | if (!tg3_readphy(tp, MII_BMSR, &tmp) && | |
3197 | (tmp & BMSR_LSTATUS)) | |
3198 | current_link_up = 1; | |
3199 | } | |
3200 | ||
3201 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3202 | if (current_link_up == 1) { | |
3203 | if (tp->link_config.active_speed == SPEED_100 || | |
3204 | tp->link_config.active_speed == SPEED_10) | |
3205 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3206 | else | |
3207 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7f97a4bd MC |
3208 | } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) |
3209 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3210 | else | |
1da177e4 LT |
3211 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3212 | ||
3213 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3214 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3215 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3216 | ||
1da177e4 | 3217 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3218 | if (current_link_up == 1 && |
3219 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3220 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3221 | else |
3222 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3223 | } |
3224 | ||
3225 | /* ??? Without this setting Netgear GA302T PHY does not | |
3226 | * ??? send/receive packets... | |
3227 | */ | |
3228 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 && | |
3229 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { | |
3230 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3231 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3232 | udelay(80); | |
3233 | } | |
3234 | ||
3235 | tw32_f(MAC_MODE, tp->mac_mode); | |
3236 | udelay(40); | |
3237 | ||
3238 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { | |
3239 | /* Polled via timer. */ | |
3240 | tw32_f(MAC_EVENT, 0); | |
3241 | } else { | |
3242 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3243 | } | |
3244 | udelay(40); | |
3245 | ||
3246 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3247 | current_link_up == 1 && | |
3248 | tp->link_config.active_speed == SPEED_1000 && | |
3249 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || | |
3250 | (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { | |
3251 | udelay(120); | |
3252 | tw32_f(MAC_STATUS, | |
3253 | (MAC_STATUS_SYNC_CHANGED | | |
3254 | MAC_STATUS_CFG_CHANGED)); | |
3255 | udelay(40); | |
3256 | tg3_write_mem(tp, | |
3257 | NIC_SRAM_FIRMWARE_MBOX, | |
3258 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3259 | } | |
3260 | ||
5e7dfd0f MC |
3261 | /* Prevent send BD corruption. */ |
3262 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
3263 | u16 oldlnkctl, newlnkctl; | |
3264 | ||
3265 | pci_read_config_word(tp->pdev, | |
3266 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3267 | &oldlnkctl); | |
3268 | if (tp->link_config.active_speed == SPEED_100 || | |
3269 | tp->link_config.active_speed == SPEED_10) | |
3270 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3271 | else | |
3272 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3273 | if (newlnkctl != oldlnkctl) | |
3274 | pci_write_config_word(tp->pdev, | |
3275 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3276 | newlnkctl); | |
3277 | } | |
3278 | ||
1da177e4 LT |
3279 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3280 | if (current_link_up) | |
3281 | netif_carrier_on(tp->dev); | |
3282 | else | |
3283 | netif_carrier_off(tp->dev); | |
3284 | tg3_link_report(tp); | |
3285 | } | |
3286 | ||
3287 | return 0; | |
3288 | } | |
3289 | ||
3290 | struct tg3_fiber_aneginfo { | |
3291 | int state; | |
3292 | #define ANEG_STATE_UNKNOWN 0 | |
3293 | #define ANEG_STATE_AN_ENABLE 1 | |
3294 | #define ANEG_STATE_RESTART_INIT 2 | |
3295 | #define ANEG_STATE_RESTART 3 | |
3296 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3297 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3298 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3299 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3300 | #define ANEG_STATE_ACK_DETECT 8 | |
3301 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3302 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3303 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3304 | #define ANEG_STATE_IDLE_DETECT 12 | |
3305 | #define ANEG_STATE_LINK_OK 13 | |
3306 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3307 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3308 | ||
3309 | u32 flags; | |
3310 | #define MR_AN_ENABLE 0x00000001 | |
3311 | #define MR_RESTART_AN 0x00000002 | |
3312 | #define MR_AN_COMPLETE 0x00000004 | |
3313 | #define MR_PAGE_RX 0x00000008 | |
3314 | #define MR_NP_LOADED 0x00000010 | |
3315 | #define MR_TOGGLE_TX 0x00000020 | |
3316 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3317 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3318 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3319 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3320 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3321 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3322 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3323 | #define MR_TOGGLE_RX 0x00002000 | |
3324 | #define MR_NP_RX 0x00004000 | |
3325 | ||
3326 | #define MR_LINK_OK 0x80000000 | |
3327 | ||
3328 | unsigned long link_time, cur_time; | |
3329 | ||
3330 | u32 ability_match_cfg; | |
3331 | int ability_match_count; | |
3332 | ||
3333 | char ability_match, idle_match, ack_match; | |
3334 | ||
3335 | u32 txconfig, rxconfig; | |
3336 | #define ANEG_CFG_NP 0x00000080 | |
3337 | #define ANEG_CFG_ACK 0x00000040 | |
3338 | #define ANEG_CFG_RF2 0x00000020 | |
3339 | #define ANEG_CFG_RF1 0x00000010 | |
3340 | #define ANEG_CFG_PS2 0x00000001 | |
3341 | #define ANEG_CFG_PS1 0x00008000 | |
3342 | #define ANEG_CFG_HD 0x00004000 | |
3343 | #define ANEG_CFG_FD 0x00002000 | |
3344 | #define ANEG_CFG_INVAL 0x00001f06 | |
3345 | ||
3346 | }; | |
3347 | #define ANEG_OK 0 | |
3348 | #define ANEG_DONE 1 | |
3349 | #define ANEG_TIMER_ENAB 2 | |
3350 | #define ANEG_FAILED -1 | |
3351 | ||
3352 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3353 | ||
3354 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3355 | struct tg3_fiber_aneginfo *ap) | |
3356 | { | |
5be73b47 | 3357 | u16 flowctrl; |
1da177e4 LT |
3358 | unsigned long delta; |
3359 | u32 rx_cfg_reg; | |
3360 | int ret; | |
3361 | ||
3362 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3363 | ap->rxconfig = 0; | |
3364 | ap->link_time = 0; | |
3365 | ap->cur_time = 0; | |
3366 | ap->ability_match_cfg = 0; | |
3367 | ap->ability_match_count = 0; | |
3368 | ap->ability_match = 0; | |
3369 | ap->idle_match = 0; | |
3370 | ap->ack_match = 0; | |
3371 | } | |
3372 | ap->cur_time++; | |
3373 | ||
3374 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3375 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3376 | ||
3377 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3378 | ap->ability_match_cfg = rx_cfg_reg; | |
3379 | ap->ability_match = 0; | |
3380 | ap->ability_match_count = 0; | |
3381 | } else { | |
3382 | if (++ap->ability_match_count > 1) { | |
3383 | ap->ability_match = 1; | |
3384 | ap->ability_match_cfg = rx_cfg_reg; | |
3385 | } | |
3386 | } | |
3387 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3388 | ap->ack_match = 1; | |
3389 | else | |
3390 | ap->ack_match = 0; | |
3391 | ||
3392 | ap->idle_match = 0; | |
3393 | } else { | |
3394 | ap->idle_match = 1; | |
3395 | ap->ability_match_cfg = 0; | |
3396 | ap->ability_match_count = 0; | |
3397 | ap->ability_match = 0; | |
3398 | ap->ack_match = 0; | |
3399 | ||
3400 | rx_cfg_reg = 0; | |
3401 | } | |
3402 | ||
3403 | ap->rxconfig = rx_cfg_reg; | |
3404 | ret = ANEG_OK; | |
3405 | ||
3406 | switch(ap->state) { | |
3407 | case ANEG_STATE_UNKNOWN: | |
3408 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3409 | ap->state = ANEG_STATE_AN_ENABLE; | |
3410 | ||
3411 | /* fallthru */ | |
3412 | case ANEG_STATE_AN_ENABLE: | |
3413 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3414 | if (ap->flags & MR_AN_ENABLE) { | |
3415 | ap->link_time = 0; | |
3416 | ap->cur_time = 0; | |
3417 | ap->ability_match_cfg = 0; | |
3418 | ap->ability_match_count = 0; | |
3419 | ap->ability_match = 0; | |
3420 | ap->idle_match = 0; | |
3421 | ap->ack_match = 0; | |
3422 | ||
3423 | ap->state = ANEG_STATE_RESTART_INIT; | |
3424 | } else { | |
3425 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3426 | } | |
3427 | break; | |
3428 | ||
3429 | case ANEG_STATE_RESTART_INIT: | |
3430 | ap->link_time = ap->cur_time; | |
3431 | ap->flags &= ~(MR_NP_LOADED); | |
3432 | ap->txconfig = 0; | |
3433 | tw32(MAC_TX_AUTO_NEG, 0); | |
3434 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3435 | tw32_f(MAC_MODE, tp->mac_mode); | |
3436 | udelay(40); | |
3437 | ||
3438 | ret = ANEG_TIMER_ENAB; | |
3439 | ap->state = ANEG_STATE_RESTART; | |
3440 | ||
3441 | /* fallthru */ | |
3442 | case ANEG_STATE_RESTART: | |
3443 | delta = ap->cur_time - ap->link_time; | |
3444 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3445 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; | |
3446 | } else { | |
3447 | ret = ANEG_TIMER_ENAB; | |
3448 | } | |
3449 | break; | |
3450 | ||
3451 | case ANEG_STATE_DISABLE_LINK_OK: | |
3452 | ret = ANEG_DONE; | |
3453 | break; | |
3454 | ||
3455 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3456 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3457 | ap->txconfig = ANEG_CFG_FD; |
3458 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3459 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3460 | ap->txconfig |= ANEG_CFG_PS1; | |
3461 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3462 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3463 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3464 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3465 | tw32_f(MAC_MODE, tp->mac_mode); | |
3466 | udelay(40); | |
3467 | ||
3468 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3469 | break; | |
3470 | ||
3471 | case ANEG_STATE_ABILITY_DETECT: | |
3472 | if (ap->ability_match != 0 && ap->rxconfig != 0) { | |
3473 | ap->state = ANEG_STATE_ACK_DETECT_INIT; | |
3474 | } | |
3475 | break; | |
3476 | ||
3477 | case ANEG_STATE_ACK_DETECT_INIT: | |
3478 | ap->txconfig |= ANEG_CFG_ACK; | |
3479 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3480 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3481 | tw32_f(MAC_MODE, tp->mac_mode); | |
3482 | udelay(40); | |
3483 | ||
3484 | ap->state = ANEG_STATE_ACK_DETECT; | |
3485 | ||
3486 | /* fallthru */ | |
3487 | case ANEG_STATE_ACK_DETECT: | |
3488 | if (ap->ack_match != 0) { | |
3489 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3490 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3491 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3492 | } else { | |
3493 | ap->state = ANEG_STATE_AN_ENABLE; | |
3494 | } | |
3495 | } else if (ap->ability_match != 0 && | |
3496 | ap->rxconfig == 0) { | |
3497 | ap->state = ANEG_STATE_AN_ENABLE; | |
3498 | } | |
3499 | break; | |
3500 | ||
3501 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3502 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3503 | ret = ANEG_FAILED; | |
3504 | break; | |
3505 | } | |
3506 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3507 | MR_LP_ADV_HALF_DUPLEX | | |
3508 | MR_LP_ADV_SYM_PAUSE | | |
3509 | MR_LP_ADV_ASYM_PAUSE | | |
3510 | MR_LP_ADV_REMOTE_FAULT1 | | |
3511 | MR_LP_ADV_REMOTE_FAULT2 | | |
3512 | MR_LP_ADV_NEXT_PAGE | | |
3513 | MR_TOGGLE_RX | | |
3514 | MR_NP_RX); | |
3515 | if (ap->rxconfig & ANEG_CFG_FD) | |
3516 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3517 | if (ap->rxconfig & ANEG_CFG_HD) | |
3518 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3519 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3520 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3521 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3522 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3523 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3524 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3525 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3526 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3527 | if (ap->rxconfig & ANEG_CFG_NP) | |
3528 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3529 | ||
3530 | ap->link_time = ap->cur_time; | |
3531 | ||
3532 | ap->flags ^= (MR_TOGGLE_TX); | |
3533 | if (ap->rxconfig & 0x0008) | |
3534 | ap->flags |= MR_TOGGLE_RX; | |
3535 | if (ap->rxconfig & ANEG_CFG_NP) | |
3536 | ap->flags |= MR_NP_RX; | |
3537 | ap->flags |= MR_PAGE_RX; | |
3538 | ||
3539 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3540 | ret = ANEG_TIMER_ENAB; | |
3541 | break; | |
3542 | ||
3543 | case ANEG_STATE_COMPLETE_ACK: | |
3544 | if (ap->ability_match != 0 && | |
3545 | ap->rxconfig == 0) { | |
3546 | ap->state = ANEG_STATE_AN_ENABLE; | |
3547 | break; | |
3548 | } | |
3549 | delta = ap->cur_time - ap->link_time; | |
3550 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3551 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3552 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3553 | } else { | |
3554 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3555 | !(ap->flags & MR_NP_RX)) { | |
3556 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3557 | } else { | |
3558 | ret = ANEG_FAILED; | |
3559 | } | |
3560 | } | |
3561 | } | |
3562 | break; | |
3563 | ||
3564 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3565 | ap->link_time = ap->cur_time; | |
3566 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3567 | tw32_f(MAC_MODE, tp->mac_mode); | |
3568 | udelay(40); | |
3569 | ||
3570 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3571 | ret = ANEG_TIMER_ENAB; | |
3572 | break; | |
3573 | ||
3574 | case ANEG_STATE_IDLE_DETECT: | |
3575 | if (ap->ability_match != 0 && | |
3576 | ap->rxconfig == 0) { | |
3577 | ap->state = ANEG_STATE_AN_ENABLE; | |
3578 | break; | |
3579 | } | |
3580 | delta = ap->cur_time - ap->link_time; | |
3581 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3582 | /* XXX another gem from the Broadcom driver :( */ | |
3583 | ap->state = ANEG_STATE_LINK_OK; | |
3584 | } | |
3585 | break; | |
3586 | ||
3587 | case ANEG_STATE_LINK_OK: | |
3588 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3589 | ret = ANEG_DONE; | |
3590 | break; | |
3591 | ||
3592 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3593 | /* ??? unimplemented */ | |
3594 | break; | |
3595 | ||
3596 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3597 | /* ??? unimplemented */ | |
3598 | break; | |
3599 | ||
3600 | default: | |
3601 | ret = ANEG_FAILED; | |
3602 | break; | |
855e1111 | 3603 | } |
1da177e4 LT |
3604 | |
3605 | return ret; | |
3606 | } | |
3607 | ||
5be73b47 | 3608 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3609 | { |
3610 | int res = 0; | |
3611 | struct tg3_fiber_aneginfo aninfo; | |
3612 | int status = ANEG_FAILED; | |
3613 | unsigned int tick; | |
3614 | u32 tmp; | |
3615 | ||
3616 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3617 | ||
3618 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3619 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3620 | udelay(40); | |
3621 | ||
3622 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3623 | udelay(40); | |
3624 | ||
3625 | memset(&aninfo, 0, sizeof(aninfo)); | |
3626 | aninfo.flags |= MR_AN_ENABLE; | |
3627 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3628 | aninfo.cur_time = 0; | |
3629 | tick = 0; | |
3630 | while (++tick < 195000) { | |
3631 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3632 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3633 | break; | |
3634 | ||
3635 | udelay(1); | |
3636 | } | |
3637 | ||
3638 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3639 | tw32_f(MAC_MODE, tp->mac_mode); | |
3640 | udelay(40); | |
3641 | ||
5be73b47 MC |
3642 | *txflags = aninfo.txconfig; |
3643 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3644 | |
3645 | if (status == ANEG_DONE && | |
3646 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3647 | MR_LP_ADV_FULL_DUPLEX))) | |
3648 | res = 1; | |
3649 | ||
3650 | return res; | |
3651 | } | |
3652 | ||
3653 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3654 | { | |
3655 | u32 mac_status = tr32(MAC_STATUS); | |
3656 | int i; | |
3657 | ||
3658 | /* Reset when initting first time or we have a link. */ | |
3659 | if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && | |
3660 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3661 | return; | |
3662 | ||
3663 | /* Set PLL lock range. */ | |
3664 | tg3_writephy(tp, 0x16, 0x8007); | |
3665 | ||
3666 | /* SW reset */ | |
3667 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3668 | ||
3669 | /* Wait for reset to complete. */ | |
3670 | /* XXX schedule_timeout() ... */ | |
3671 | for (i = 0; i < 500; i++) | |
3672 | udelay(10); | |
3673 | ||
3674 | /* Config mode; select PMA/Ch 1 regs. */ | |
3675 | tg3_writephy(tp, 0x10, 0x8411); | |
3676 | ||
3677 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3678 | tg3_writephy(tp, 0x11, 0x0a10); | |
3679 | ||
3680 | tg3_writephy(tp, 0x18, 0x00a0); | |
3681 | tg3_writephy(tp, 0x16, 0x41ff); | |
3682 | ||
3683 | /* Assert and deassert POR. */ | |
3684 | tg3_writephy(tp, 0x13, 0x0400); | |
3685 | udelay(40); | |
3686 | tg3_writephy(tp, 0x13, 0x0000); | |
3687 | ||
3688 | tg3_writephy(tp, 0x11, 0x0a50); | |
3689 | udelay(40); | |
3690 | tg3_writephy(tp, 0x11, 0x0a10); | |
3691 | ||
3692 | /* Wait for signal to stabilize */ | |
3693 | /* XXX schedule_timeout() ... */ | |
3694 | for (i = 0; i < 15000; i++) | |
3695 | udelay(10); | |
3696 | ||
3697 | /* Deselect the channel register so we can read the PHYID | |
3698 | * later. | |
3699 | */ | |
3700 | tg3_writephy(tp, 0x10, 0x8011); | |
3701 | } | |
3702 | ||
3703 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3704 | { | |
82cd3d11 | 3705 | u16 flowctrl; |
1da177e4 LT |
3706 | u32 sg_dig_ctrl, sg_dig_status; |
3707 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3708 | int workaround, port_a; | |
3709 | int current_link_up; | |
3710 | ||
3711 | serdes_cfg = 0; | |
3712 | expected_sg_dig_ctrl = 0; | |
3713 | workaround = 0; | |
3714 | port_a = 1; | |
3715 | current_link_up = 0; | |
3716 | ||
3717 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3718 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3719 | workaround = 1; | |
3720 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3721 | port_a = 0; | |
3722 | ||
3723 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3724 | /* preserve bits 20-23 for voltage regulator */ | |
3725 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3726 | } | |
3727 | ||
3728 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3729 | ||
3730 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 3731 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
3732 | if (workaround) { |
3733 | u32 val = serdes_cfg; | |
3734 | ||
3735 | if (port_a) | |
3736 | val |= 0xc010000; | |
3737 | else | |
3738 | val |= 0x4010000; | |
3739 | tw32_f(MAC_SERDES_CFG, val); | |
3740 | } | |
c98f6e3b MC |
3741 | |
3742 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
3743 | } |
3744 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3745 | tg3_setup_flow_control(tp, 0, 0); | |
3746 | current_link_up = 1; | |
3747 | } | |
3748 | goto out; | |
3749 | } | |
3750 | ||
3751 | /* Want auto-negotiation. */ | |
c98f6e3b | 3752 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 3753 | |
82cd3d11 MC |
3754 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
3755 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3756 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3757 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3758 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
3759 | |
3760 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
3d3ebe74 MC |
3761 | if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) && |
3762 | tp->serdes_counter && | |
3763 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3764 | MAC_STATUS_RCVD_CFG)) == | |
3765 | MAC_STATUS_PCS_SYNCED)) { | |
3766 | tp->serdes_counter--; | |
3767 | current_link_up = 1; | |
3768 | goto out; | |
3769 | } | |
3770 | restart_autoneg: | |
1da177e4 LT |
3771 | if (workaround) |
3772 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 3773 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
3774 | udelay(5); |
3775 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3776 | ||
3d3ebe74 MC |
3777 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
3778 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
1da177e4 LT |
3779 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
3780 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 3781 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
3782 | mac_status = tr32(MAC_STATUS); |
3783 | ||
c98f6e3b | 3784 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 3785 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
3786 | u32 local_adv = 0, remote_adv = 0; |
3787 | ||
3788 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3789 | local_adv |= ADVERTISE_1000XPAUSE; | |
3790 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3791 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 3792 | |
c98f6e3b | 3793 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 3794 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 3795 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 3796 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
3797 | |
3798 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3799 | current_link_up = 1; | |
3d3ebe74 MC |
3800 | tp->serdes_counter = 0; |
3801 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
c98f6e3b | 3802 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
3803 | if (tp->serdes_counter) |
3804 | tp->serdes_counter--; | |
1da177e4 LT |
3805 | else { |
3806 | if (workaround) { | |
3807 | u32 val = serdes_cfg; | |
3808 | ||
3809 | if (port_a) | |
3810 | val |= 0xc010000; | |
3811 | else | |
3812 | val |= 0x4010000; | |
3813 | ||
3814 | tw32_f(MAC_SERDES_CFG, val); | |
3815 | } | |
3816 | ||
c98f6e3b | 3817 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
3818 | udelay(40); |
3819 | ||
3820 | /* Link parallel detection - link is up */ | |
3821 | /* only if we have PCS_SYNC and not */ | |
3822 | /* receiving config code words */ | |
3823 | mac_status = tr32(MAC_STATUS); | |
3824 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
3825 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
3826 | tg3_setup_flow_control(tp, 0, 0); | |
3827 | current_link_up = 1; | |
3d3ebe74 MC |
3828 | tp->tg3_flags2 |= |
3829 | TG3_FLG2_PARALLEL_DETECT; | |
3830 | tp->serdes_counter = | |
3831 | SERDES_PARALLEL_DET_TIMEOUT; | |
3832 | } else | |
3833 | goto restart_autoneg; | |
1da177e4 LT |
3834 | } |
3835 | } | |
3d3ebe74 MC |
3836 | } else { |
3837 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
3838 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
1da177e4 LT |
3839 | } |
3840 | ||
3841 | out: | |
3842 | return current_link_up; | |
3843 | } | |
3844 | ||
3845 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
3846 | { | |
3847 | int current_link_up = 0; | |
3848 | ||
5cf64b8a | 3849 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 3850 | goto out; |
1da177e4 LT |
3851 | |
3852 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 3853 | u32 txflags, rxflags; |
1da177e4 | 3854 | int i; |
6aa20a22 | 3855 | |
5be73b47 MC |
3856 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
3857 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 3858 | |
5be73b47 MC |
3859 | if (txflags & ANEG_CFG_PS1) |
3860 | local_adv |= ADVERTISE_1000XPAUSE; | |
3861 | if (txflags & ANEG_CFG_PS2) | |
3862 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
3863 | ||
3864 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
3865 | remote_adv |= LPA_1000XPAUSE; | |
3866 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
3867 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
3868 | |
3869 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3870 | ||
1da177e4 LT |
3871 | current_link_up = 1; |
3872 | } | |
3873 | for (i = 0; i < 30; i++) { | |
3874 | udelay(20); | |
3875 | tw32_f(MAC_STATUS, | |
3876 | (MAC_STATUS_SYNC_CHANGED | | |
3877 | MAC_STATUS_CFG_CHANGED)); | |
3878 | udelay(40); | |
3879 | if ((tr32(MAC_STATUS) & | |
3880 | (MAC_STATUS_SYNC_CHANGED | | |
3881 | MAC_STATUS_CFG_CHANGED)) == 0) | |
3882 | break; | |
3883 | } | |
3884 | ||
3885 | mac_status = tr32(MAC_STATUS); | |
3886 | if (current_link_up == 0 && | |
3887 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
3888 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
3889 | current_link_up = 1; | |
3890 | } else { | |
5be73b47 MC |
3891 | tg3_setup_flow_control(tp, 0, 0); |
3892 | ||
1da177e4 LT |
3893 | /* Forcing 1000FD link up. */ |
3894 | current_link_up = 1; | |
1da177e4 LT |
3895 | |
3896 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
3897 | udelay(40); | |
e8f3f6ca MC |
3898 | |
3899 | tw32_f(MAC_MODE, tp->mac_mode); | |
3900 | udelay(40); | |
1da177e4 LT |
3901 | } |
3902 | ||
3903 | out: | |
3904 | return current_link_up; | |
3905 | } | |
3906 | ||
3907 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
3908 | { | |
3909 | u32 orig_pause_cfg; | |
3910 | u16 orig_active_speed; | |
3911 | u8 orig_active_duplex; | |
3912 | u32 mac_status; | |
3913 | int current_link_up; | |
3914 | int i; | |
3915 | ||
8d018621 | 3916 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
3917 | orig_active_speed = tp->link_config.active_speed; |
3918 | orig_active_duplex = tp->link_config.active_duplex; | |
3919 | ||
3920 | if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && | |
3921 | netif_carrier_ok(tp->dev) && | |
3922 | (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { | |
3923 | mac_status = tr32(MAC_STATUS); | |
3924 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
3925 | MAC_STATUS_SIGNAL_DET | | |
3926 | MAC_STATUS_CFG_CHANGED | | |
3927 | MAC_STATUS_RCVD_CFG); | |
3928 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
3929 | MAC_STATUS_SIGNAL_DET)) { | |
3930 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
3931 | MAC_STATUS_CFG_CHANGED)); | |
3932 | return 0; | |
3933 | } | |
3934 | } | |
3935 | ||
3936 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3937 | ||
3938 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
3939 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
3940 | tw32_f(MAC_MODE, tp->mac_mode); | |
3941 | udelay(40); | |
3942 | ||
3943 | if (tp->phy_id == PHY_ID_BCM8002) | |
3944 | tg3_init_bcm8002(tp); | |
3945 | ||
3946 | /* Enable link change event even when serdes polling. */ | |
3947 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3948 | udelay(40); | |
3949 | ||
3950 | current_link_up = 0; | |
3951 | mac_status = tr32(MAC_STATUS); | |
3952 | ||
3953 | if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) | |
3954 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
3955 | else | |
3956 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
3957 | ||
898a56f8 | 3958 | tp->napi[0].hw_status->status = |
1da177e4 | 3959 | (SD_STATUS_UPDATED | |
898a56f8 | 3960 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
3961 | |
3962 | for (i = 0; i < 100; i++) { | |
3963 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
3964 | MAC_STATUS_CFG_CHANGED)); | |
3965 | udelay(5); | |
3966 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
3967 | MAC_STATUS_CFG_CHANGED | |
3968 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
3969 | break; |
3970 | } | |
3971 | ||
3972 | mac_status = tr32(MAC_STATUS); | |
3973 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
3974 | current_link_up = 0; | |
3d3ebe74 MC |
3975 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
3976 | tp->serdes_counter == 0) { | |
1da177e4 LT |
3977 | tw32_f(MAC_MODE, (tp->mac_mode | |
3978 | MAC_MODE_SEND_CONFIGS)); | |
3979 | udelay(1); | |
3980 | tw32_f(MAC_MODE, tp->mac_mode); | |
3981 | } | |
3982 | } | |
3983 | ||
3984 | if (current_link_up == 1) { | |
3985 | tp->link_config.active_speed = SPEED_1000; | |
3986 | tp->link_config.active_duplex = DUPLEX_FULL; | |
3987 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
3988 | LED_CTRL_LNKLED_OVERRIDE | | |
3989 | LED_CTRL_1000MBPS_ON)); | |
3990 | } else { | |
3991 | tp->link_config.active_speed = SPEED_INVALID; | |
3992 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
3993 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
3994 | LED_CTRL_LNKLED_OVERRIDE | | |
3995 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
3996 | } | |
3997 | ||
3998 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
3999 | if (current_link_up) | |
4000 | netif_carrier_on(tp->dev); | |
4001 | else | |
4002 | netif_carrier_off(tp->dev); | |
4003 | tg3_link_report(tp); | |
4004 | } else { | |
8d018621 | 4005 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4006 | if (orig_pause_cfg != now_pause_cfg || |
4007 | orig_active_speed != tp->link_config.active_speed || | |
4008 | orig_active_duplex != tp->link_config.active_duplex) | |
4009 | tg3_link_report(tp); | |
4010 | } | |
4011 | ||
4012 | return 0; | |
4013 | } | |
4014 | ||
747e8f8b MC |
4015 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4016 | { | |
4017 | int current_link_up, err = 0; | |
4018 | u32 bmsr, bmcr; | |
4019 | u16 current_speed; | |
4020 | u8 current_duplex; | |
ef167e27 | 4021 | u32 local_adv, remote_adv; |
747e8f8b MC |
4022 | |
4023 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4024 | tw32_f(MAC_MODE, tp->mac_mode); | |
4025 | udelay(40); | |
4026 | ||
4027 | tw32(MAC_EVENT, 0); | |
4028 | ||
4029 | tw32_f(MAC_STATUS, | |
4030 | (MAC_STATUS_SYNC_CHANGED | | |
4031 | MAC_STATUS_CFG_CHANGED | | |
4032 | MAC_STATUS_MI_COMPLETION | | |
4033 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4034 | udelay(40); | |
4035 | ||
4036 | if (force_reset) | |
4037 | tg3_phy_reset(tp); | |
4038 | ||
4039 | current_link_up = 0; | |
4040 | current_speed = SPEED_INVALID; | |
4041 | current_duplex = DUPLEX_INVALID; | |
4042 | ||
4043 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4044 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4045 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4046 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4047 | bmsr |= BMSR_LSTATUS; | |
4048 | else | |
4049 | bmsr &= ~BMSR_LSTATUS; | |
4050 | } | |
747e8f8b MC |
4051 | |
4052 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4053 | ||
4054 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
2bd3ed04 | 4055 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { |
747e8f8b MC |
4056 | /* do nothing, just check for link up at the end */ |
4057 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4058 | u32 adv, new_adv; | |
4059 | ||
4060 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4061 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4062 | ADVERTISE_1000XPAUSE | | |
4063 | ADVERTISE_1000XPSE_ASYM | | |
4064 | ADVERTISE_SLCT); | |
4065 | ||
ba4d07a8 | 4066 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4067 | |
4068 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4069 | new_adv |= ADVERTISE_1000XHALF; | |
4070 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4071 | new_adv |= ADVERTISE_1000XFULL; | |
4072 | ||
4073 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4074 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4075 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4076 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4077 | ||
4078 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4079 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
747e8f8b MC |
4080 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; |
4081 | ||
4082 | return err; | |
4083 | } | |
4084 | } else { | |
4085 | u32 new_bmcr; | |
4086 | ||
4087 | bmcr &= ~BMCR_SPEED1000; | |
4088 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4089 | ||
4090 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4091 | new_bmcr |= BMCR_FULLDPLX; | |
4092 | ||
4093 | if (new_bmcr != bmcr) { | |
4094 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4095 | * to be set on write. | |
4096 | */ | |
4097 | new_bmcr |= BMCR_SPEED1000; | |
4098 | ||
4099 | /* Force a linkdown */ | |
4100 | if (netif_carrier_ok(tp->dev)) { | |
4101 | u32 adv; | |
4102 | ||
4103 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4104 | adv &= ~(ADVERTISE_1000XFULL | | |
4105 | ADVERTISE_1000XHALF | | |
4106 | ADVERTISE_SLCT); | |
4107 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4108 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4109 | BMCR_ANRESTART | | |
4110 | BMCR_ANENABLE); | |
4111 | udelay(10); | |
4112 | netif_carrier_off(tp->dev); | |
4113 | } | |
4114 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4115 | bmcr = new_bmcr; | |
4116 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4117 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4118 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4119 | ASIC_REV_5714) { | |
4120 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4121 | bmsr |= BMSR_LSTATUS; | |
4122 | else | |
4123 | bmsr &= ~BMSR_LSTATUS; | |
4124 | } | |
747e8f8b MC |
4125 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; |
4126 | } | |
4127 | } | |
4128 | ||
4129 | if (bmsr & BMSR_LSTATUS) { | |
4130 | current_speed = SPEED_1000; | |
4131 | current_link_up = 1; | |
4132 | if (bmcr & BMCR_FULLDPLX) | |
4133 | current_duplex = DUPLEX_FULL; | |
4134 | else | |
4135 | current_duplex = DUPLEX_HALF; | |
4136 | ||
ef167e27 MC |
4137 | local_adv = 0; |
4138 | remote_adv = 0; | |
4139 | ||
747e8f8b | 4140 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4141 | u32 common; |
747e8f8b MC |
4142 | |
4143 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4144 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4145 | common = local_adv & remote_adv; | |
4146 | if (common & (ADVERTISE_1000XHALF | | |
4147 | ADVERTISE_1000XFULL)) { | |
4148 | if (common & ADVERTISE_1000XFULL) | |
4149 | current_duplex = DUPLEX_FULL; | |
4150 | else | |
4151 | current_duplex = DUPLEX_HALF; | |
747e8f8b MC |
4152 | } |
4153 | else | |
4154 | current_link_up = 0; | |
4155 | } | |
4156 | } | |
4157 | ||
ef167e27 MC |
4158 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4159 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4160 | ||
747e8f8b MC |
4161 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4162 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4163 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4164 | ||
4165 | tw32_f(MAC_MODE, tp->mac_mode); | |
4166 | udelay(40); | |
4167 | ||
4168 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4169 | ||
4170 | tp->link_config.active_speed = current_speed; | |
4171 | tp->link_config.active_duplex = current_duplex; | |
4172 | ||
4173 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4174 | if (current_link_up) | |
4175 | netif_carrier_on(tp->dev); | |
4176 | else { | |
4177 | netif_carrier_off(tp->dev); | |
4178 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4179 | } | |
4180 | tg3_link_report(tp); | |
4181 | } | |
4182 | return err; | |
4183 | } | |
4184 | ||
4185 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4186 | { | |
3d3ebe74 | 4187 | if (tp->serdes_counter) { |
747e8f8b | 4188 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4189 | tp->serdes_counter--; |
747e8f8b MC |
4190 | return; |
4191 | } | |
4192 | if (!netif_carrier_ok(tp->dev) && | |
4193 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4194 | u32 bmcr; | |
4195 | ||
4196 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4197 | if (bmcr & BMCR_ANENABLE) { | |
4198 | u32 phy1, phy2; | |
4199 | ||
4200 | /* Select shadow register 0x1f */ | |
4201 | tg3_writephy(tp, 0x1c, 0x7c00); | |
4202 | tg3_readphy(tp, 0x1c, &phy1); | |
4203 | ||
4204 | /* Select expansion interrupt status register */ | |
4205 | tg3_writephy(tp, 0x17, 0x0f01); | |
4206 | tg3_readphy(tp, 0x15, &phy2); | |
4207 | tg3_readphy(tp, 0x15, &phy2); | |
4208 | ||
4209 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4210 | /* We have signal detect and not receiving | |
4211 | * config code words, link is up by parallel | |
4212 | * detection. | |
4213 | */ | |
4214 | ||
4215 | bmcr &= ~BMCR_ANENABLE; | |
4216 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4217 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4218 | tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT; | |
4219 | } | |
4220 | } | |
4221 | } | |
4222 | else if (netif_carrier_ok(tp->dev) && | |
4223 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
4224 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { | |
4225 | u32 phy2; | |
4226 | ||
4227 | /* Select expansion interrupt status register */ | |
4228 | tg3_writephy(tp, 0x17, 0x0f01); | |
4229 | tg3_readphy(tp, 0x15, &phy2); | |
4230 | if (phy2 & 0x20) { | |
4231 | u32 bmcr; | |
4232 | ||
4233 | /* Config code words received, turn on autoneg. */ | |
4234 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4235 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4236 | ||
4237 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4238 | ||
4239 | } | |
4240 | } | |
4241 | } | |
4242 | ||
1da177e4 LT |
4243 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4244 | { | |
4245 | int err; | |
4246 | ||
4247 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
4248 | err = tg3_setup_fiber_phy(tp, force_reset); | |
747e8f8b MC |
4249 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { |
4250 | err = tg3_setup_fiber_mii_phy(tp, force_reset); | |
1da177e4 LT |
4251 | } else { |
4252 | err = tg3_setup_copper_phy(tp, force_reset); | |
4253 | } | |
4254 | ||
bcb37f6c | 4255 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
aa6c91fe MC |
4256 | u32 val, scale; |
4257 | ||
4258 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4259 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4260 | scale = 65; | |
4261 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4262 | scale = 6; | |
4263 | else | |
4264 | scale = 12; | |
4265 | ||
4266 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4267 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4268 | tw32(GRC_MISC_CFG, val); | |
4269 | } | |
4270 | ||
1da177e4 LT |
4271 | if (tp->link_config.active_speed == SPEED_1000 && |
4272 | tp->link_config.active_duplex == DUPLEX_HALF) | |
4273 | tw32(MAC_TX_LENGTHS, | |
4274 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4275 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4276 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4277 | else | |
4278 | tw32(MAC_TX_LENGTHS, | |
4279 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4280 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4281 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4282 | ||
4283 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4284 | if (netif_carrier_ok(tp->dev)) { | |
4285 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4286 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4287 | } else { |
4288 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4289 | } | |
4290 | } | |
4291 | ||
8ed5d97e MC |
4292 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { |
4293 | u32 val = tr32(PCIE_PWR_MGMT_THRESH); | |
4294 | if (!netif_carrier_ok(tp->dev)) | |
4295 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4296 | tp->pwrmgmt_thresh; | |
4297 | else | |
4298 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4299 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4300 | } | |
4301 | ||
1da177e4 LT |
4302 | return err; |
4303 | } | |
4304 | ||
df3e6548 MC |
4305 | /* This is called whenever we suspect that the system chipset is re- |
4306 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4307 | * is bogus tx completions. We try to recover by setting the | |
4308 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4309 | * in the workqueue. | |
4310 | */ | |
4311 | static void tg3_tx_recover(struct tg3 *tp) | |
4312 | { | |
4313 | BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || | |
4314 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4315 | ||
4316 | printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-" | |
4317 | "mapped I/O cycles to the network device, attempting to " | |
4318 | "recover. Please report the problem to the driver maintainer " | |
4319 | "and include system chipset information.\n", tp->dev->name); | |
4320 | ||
4321 | spin_lock(&tp->lock); | |
df3e6548 | 4322 | tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; |
df3e6548 MC |
4323 | spin_unlock(&tp->lock); |
4324 | } | |
4325 | ||
f3f3f27e | 4326 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 MC |
4327 | { |
4328 | smp_mb(); | |
f3f3f27e MC |
4329 | return tnapi->tx_pending - |
4330 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4331 | } |
4332 | ||
1da177e4 LT |
4333 | /* Tigon3 never reports partial packet sends. So we do not |
4334 | * need special logic to handle SKBs that have not had all | |
4335 | * of their frags sent yet, like SunGEM does. | |
4336 | */ | |
17375d25 | 4337 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4338 | { |
17375d25 | 4339 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4340 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4341 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
4342 | struct netdev_queue *txq; |
4343 | int index = tnapi - tp->napi; | |
4344 | ||
4345 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) | |
4346 | index--; | |
4347 | ||
4348 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
4349 | |
4350 | while (sw_idx != hw_idx) { | |
f3f3f27e | 4351 | struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4352 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4353 | int i, tx_bug = 0; |
4354 | ||
4355 | if (unlikely(skb == NULL)) { | |
4356 | tg3_tx_recover(tp); | |
4357 | return; | |
4358 | } | |
1da177e4 | 4359 | |
90079ce8 | 4360 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); |
1da177e4 LT |
4361 | |
4362 | ri->skb = NULL; | |
4363 | ||
4364 | sw_idx = NEXT_TX(sw_idx); | |
4365 | ||
4366 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4367 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4368 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4369 | tx_bug = 1; | |
1da177e4 LT |
4370 | sw_idx = NEXT_TX(sw_idx); |
4371 | } | |
4372 | ||
f47c11ee | 4373 | dev_kfree_skb(skb); |
df3e6548 MC |
4374 | |
4375 | if (unlikely(tx_bug)) { | |
4376 | tg3_tx_recover(tp); | |
4377 | return; | |
4378 | } | |
1da177e4 LT |
4379 | } |
4380 | ||
f3f3f27e | 4381 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4382 | |
1b2a7205 MC |
4383 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4384 | * before checking for netif_queue_stopped(). Without the | |
4385 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4386 | * will miss it and cause the queue to be stopped forever. | |
4387 | */ | |
4388 | smp_mb(); | |
4389 | ||
fe5f5787 | 4390 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 4391 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
4392 | __netif_tx_lock(txq, smp_processor_id()); |
4393 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 4394 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
4395 | netif_tx_wake_queue(txq); |
4396 | __netif_tx_unlock(txq); | |
51b91468 | 4397 | } |
1da177e4 LT |
4398 | } |
4399 | ||
4400 | /* Returns size of skb allocated or < 0 on error. | |
4401 | * | |
4402 | * We only need to fill in the address because the other members | |
4403 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4404 | * | |
4405 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4406 | * posting buffers we only dirty the first cache line of the RX | |
4407 | * descriptor (containing the address). Whereas for the RX status | |
4408 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4409 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4410 | */ | |
17375d25 | 4411 | static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key, |
1da177e4 LT |
4412 | int src_idx, u32 dest_idx_unmasked) |
4413 | { | |
17375d25 | 4414 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4415 | struct tg3_rx_buffer_desc *desc; |
4416 | struct ring_info *map, *src_map; | |
4417 | struct sk_buff *skb; | |
4418 | dma_addr_t mapping; | |
4419 | int skb_size, dest_idx; | |
21f581a5 | 4420 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
1da177e4 LT |
4421 | |
4422 | src_map = NULL; | |
4423 | switch (opaque_key) { | |
4424 | case RXD_OPAQUE_RING_STD: | |
4425 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
21f581a5 MC |
4426 | desc = &tpr->rx_std[dest_idx]; |
4427 | map = &tpr->rx_std_buffers[dest_idx]; | |
1da177e4 | 4428 | if (src_idx >= 0) |
21f581a5 | 4429 | src_map = &tpr->rx_std_buffers[src_idx]; |
287be12e | 4430 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4431 | break; |
4432 | ||
4433 | case RXD_OPAQUE_RING_JUMBO: | |
4434 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
79ed5ac7 | 4435 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4436 | map = &tpr->rx_jmb_buffers[dest_idx]; |
1da177e4 | 4437 | if (src_idx >= 0) |
21f581a5 | 4438 | src_map = &tpr->rx_jmb_buffers[src_idx]; |
287be12e | 4439 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4440 | break; |
4441 | ||
4442 | default: | |
4443 | return -EINVAL; | |
855e1111 | 4444 | } |
1da177e4 LT |
4445 | |
4446 | /* Do not overwrite any of the map or rp information | |
4447 | * until we are sure we can commit to a new buffer. | |
4448 | * | |
4449 | * Callers depend upon this behavior and assume that | |
4450 | * we leave everything unchanged if we fail. | |
4451 | */ | |
287be12e | 4452 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4453 | if (skb == NULL) |
4454 | return -ENOMEM; | |
4455 | ||
1da177e4 LT |
4456 | skb_reserve(skb, tp->rx_offset); |
4457 | ||
287be12e | 4458 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 4459 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
4460 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
4461 | dev_kfree_skb(skb); | |
4462 | return -EIO; | |
4463 | } | |
1da177e4 LT |
4464 | |
4465 | map->skb = skb; | |
4466 | pci_unmap_addr_set(map, mapping, mapping); | |
4467 | ||
4468 | if (src_map != NULL) | |
4469 | src_map->skb = NULL; | |
4470 | ||
4471 | desc->addr_hi = ((u64)mapping >> 32); | |
4472 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4473 | ||
4474 | return skb_size; | |
4475 | } | |
4476 | ||
4477 | /* We only need to move over in the address because the other | |
4478 | * members of the RX descriptor are invariant. See notes above | |
4479 | * tg3_alloc_rx_skb for full details. | |
4480 | */ | |
17375d25 | 4481 | static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key, |
1da177e4 LT |
4482 | int src_idx, u32 dest_idx_unmasked) |
4483 | { | |
17375d25 | 4484 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4485 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4486 | struct ring_info *src_map, *dest_map; | |
4487 | int dest_idx; | |
21f581a5 | 4488 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
1da177e4 LT |
4489 | |
4490 | switch (opaque_key) { | |
4491 | case RXD_OPAQUE_RING_STD: | |
4492 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
21f581a5 MC |
4493 | dest_desc = &tpr->rx_std[dest_idx]; |
4494 | dest_map = &tpr->rx_std_buffers[dest_idx]; | |
4495 | src_desc = &tpr->rx_std[src_idx]; | |
4496 | src_map = &tpr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4497 | break; |
4498 | ||
4499 | case RXD_OPAQUE_RING_JUMBO: | |
4500 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
79ed5ac7 | 4501 | dest_desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4502 | dest_map = &tpr->rx_jmb_buffers[dest_idx]; |
79ed5ac7 | 4503 | src_desc = &tpr->rx_jmb[src_idx].std; |
21f581a5 | 4504 | src_map = &tpr->rx_jmb_buffers[src_idx]; |
1da177e4 LT |
4505 | break; |
4506 | ||
4507 | default: | |
4508 | return; | |
855e1111 | 4509 | } |
1da177e4 LT |
4510 | |
4511 | dest_map->skb = src_map->skb; | |
4512 | pci_unmap_addr_set(dest_map, mapping, | |
4513 | pci_unmap_addr(src_map, mapping)); | |
4514 | dest_desc->addr_hi = src_desc->addr_hi; | |
4515 | dest_desc->addr_lo = src_desc->addr_lo; | |
4516 | ||
4517 | src_map->skb = NULL; | |
4518 | } | |
4519 | ||
1da177e4 LT |
4520 | /* The RX ring scheme is composed of multiple rings which post fresh |
4521 | * buffers to the chip, and one special ring the chip uses to report | |
4522 | * status back to the host. | |
4523 | * | |
4524 | * The special ring reports the status of received packets to the | |
4525 | * host. The chip does not write into the original descriptor the | |
4526 | * RX buffer was obtained from. The chip simply takes the original | |
4527 | * descriptor as provided by the host, updates the status and length | |
4528 | * field, then writes this into the next status ring entry. | |
4529 | * | |
4530 | * Each ring the host uses to post buffers to the chip is described | |
4531 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4532 | * it is first placed into the on-chip ram. When the packet's length | |
4533 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4534 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4535 | * which is within the range of the new packet's length is chosen. | |
4536 | * | |
4537 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4538 | * sense from a cache coherency perspective. If only the host writes | |
4539 | * to the buffer post rings, and only the chip writes to the rx status | |
4540 | * rings, then cache lines never move beyond shared-modified state. | |
4541 | * If both the host and chip were to write into the same ring, cache line | |
4542 | * eviction could occur since both entities want it in an exclusive state. | |
4543 | */ | |
17375d25 | 4544 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 4545 | { |
17375d25 | 4546 | struct tg3 *tp = tnapi->tp; |
f92905de | 4547 | u32 work_mask, rx_std_posted = 0; |
72334482 | 4548 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 4549 | u16 hw_idx; |
1da177e4 | 4550 | int received; |
21f581a5 | 4551 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
1da177e4 | 4552 | |
8d9d7cfc | 4553 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
4554 | /* |
4555 | * We need to order the read of hw_idx and the read of | |
4556 | * the opaque cookie. | |
4557 | */ | |
4558 | rmb(); | |
1da177e4 LT |
4559 | work_mask = 0; |
4560 | received = 0; | |
4561 | while (sw_idx != hw_idx && budget > 0) { | |
72334482 | 4562 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
4563 | unsigned int len; |
4564 | struct sk_buff *skb; | |
4565 | dma_addr_t dma_addr; | |
4566 | u32 opaque_key, desc_idx, *post_ptr; | |
4567 | ||
4568 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4569 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4570 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
21f581a5 MC |
4571 | struct ring_info *ri = &tpr->rx_std_buffers[desc_idx]; |
4572 | dma_addr = pci_unmap_addr(ri, mapping); | |
4573 | skb = ri->skb; | |
4574 | post_ptr = &tpr->rx_std_ptr; | |
f92905de | 4575 | rx_std_posted++; |
1da177e4 | 4576 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
21f581a5 MC |
4577 | struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx]; |
4578 | dma_addr = pci_unmap_addr(ri, mapping); | |
4579 | skb = ri->skb; | |
4580 | post_ptr = &tpr->rx_jmb_ptr; | |
4581 | } else | |
1da177e4 | 4582 | goto next_pkt_nopost; |
1da177e4 LT |
4583 | |
4584 | work_mask |= opaque_key; | |
4585 | ||
4586 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4587 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4588 | drop_it: | |
17375d25 | 4589 | tg3_recycle_rx(tnapi, opaque_key, |
1da177e4 LT |
4590 | desc_idx, *post_ptr); |
4591 | drop_it_no_recycle: | |
4592 | /* Other statistics kept track of by card. */ | |
4593 | tp->net_stats.rx_dropped++; | |
4594 | goto next_pkt; | |
4595 | } | |
4596 | ||
ad829268 MC |
4597 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
4598 | ETH_FCS_LEN; | |
1da177e4 | 4599 | |
6aa20a22 | 4600 | if (len > RX_COPY_THRESHOLD |
ad829268 MC |
4601 | && tp->rx_offset == NET_IP_ALIGN |
4602 | /* rx_offset will likely not equal NET_IP_ALIGN | |
4603 | * if this is a 5701 card running in PCI-X mode | |
4604 | * [see tg3_get_invariants()] | |
4605 | */ | |
1da177e4 LT |
4606 | ) { |
4607 | int skb_size; | |
4608 | ||
17375d25 | 4609 | skb_size = tg3_alloc_rx_skb(tnapi, opaque_key, |
1da177e4 LT |
4610 | desc_idx, *post_ptr); |
4611 | if (skb_size < 0) | |
4612 | goto drop_it; | |
4613 | ||
287be12e | 4614 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
4615 | PCI_DMA_FROMDEVICE); |
4616 | ||
4617 | skb_put(skb, len); | |
4618 | } else { | |
4619 | struct sk_buff *copy_skb; | |
4620 | ||
17375d25 | 4621 | tg3_recycle_rx(tnapi, opaque_key, |
1da177e4 LT |
4622 | desc_idx, *post_ptr); |
4623 | ||
ad829268 MC |
4624 | copy_skb = netdev_alloc_skb(tp->dev, |
4625 | len + TG3_RAW_IP_ALIGN); | |
1da177e4 LT |
4626 | if (copy_skb == NULL) |
4627 | goto drop_it_no_recycle; | |
4628 | ||
ad829268 | 4629 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4630 | skb_put(copy_skb, len); |
4631 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 4632 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
4633 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
4634 | ||
4635 | /* We'll reuse the original ring buffer. */ | |
4636 | skb = copy_skb; | |
4637 | } | |
4638 | ||
4639 | if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) && | |
4640 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
4641 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4642 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4643 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4644 | else | |
4645 | skb->ip_summed = CHECKSUM_NONE; | |
4646 | ||
4647 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
4648 | |
4649 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4650 | skb->protocol != htons(ETH_P_8021Q)) { | |
4651 | dev_kfree_skb(skb); | |
4652 | goto next_pkt; | |
4653 | } | |
4654 | ||
1da177e4 LT |
4655 | #if TG3_VLAN_TAG_USED |
4656 | if (tp->vlgrp != NULL && | |
4657 | desc->type_flags & RXD_FLAG_VLAN) { | |
17375d25 | 4658 | vlan_gro_receive(&tnapi->napi, tp->vlgrp, |
8ef0442f | 4659 | desc->err_vlan & RXD_VLAN_MASK, skb); |
1da177e4 LT |
4660 | } else |
4661 | #endif | |
17375d25 | 4662 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 4663 | |
1da177e4 LT |
4664 | received++; |
4665 | budget--; | |
4666 | ||
4667 | next_pkt: | |
4668 | (*post_ptr)++; | |
f92905de MC |
4669 | |
4670 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
4671 | u32 idx = *post_ptr % TG3_RX_RING_SIZE; | |
4672 | ||
4673 | tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + | |
4674 | TG3_64BIT_REG_LOW, idx); | |
4675 | work_mask &= ~RXD_OPAQUE_RING_STD; | |
4676 | rx_std_posted = 0; | |
4677 | } | |
1da177e4 | 4678 | next_pkt_nopost: |
483ba50b | 4679 | sw_idx++; |
6b31a515 | 4680 | sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1); |
52f6d697 MC |
4681 | |
4682 | /* Refresh hw_idx to see if there is new work */ | |
4683 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 4684 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
4685 | rmb(); |
4686 | } | |
1da177e4 LT |
4687 | } |
4688 | ||
4689 | /* ACK the status ring. */ | |
72334482 MC |
4690 | tnapi->rx_rcb_ptr = sw_idx; |
4691 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
4692 | |
4693 | /* Refill RX ring(s). */ | |
4694 | if (work_mask & RXD_OPAQUE_RING_STD) { | |
21f581a5 | 4695 | sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE; |
1da177e4 LT |
4696 | tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, |
4697 | sw_idx); | |
4698 | } | |
4699 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
21f581a5 | 4700 | sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE; |
1da177e4 LT |
4701 | tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, |
4702 | sw_idx); | |
4703 | } | |
4704 | mmiowb(); | |
4705 | ||
4706 | return received; | |
4707 | } | |
4708 | ||
17375d25 | 4709 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
1da177e4 | 4710 | { |
17375d25 | 4711 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4712 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 | 4713 | |
1da177e4 LT |
4714 | /* handle link change and other phy events */ |
4715 | if (!(tp->tg3_flags & | |
4716 | (TG3_FLAG_USE_LINKCHG_REG | | |
4717 | TG3_FLAG_POLL_SERDES))) { | |
4718 | if (sblk->status & SD_STATUS_LINK_CHG) { | |
4719 | sblk->status = SD_STATUS_UPDATED | | |
4720 | (sblk->status & ~SD_STATUS_LINK_CHG); | |
f47c11ee | 4721 | spin_lock(&tp->lock); |
dd477003 MC |
4722 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
4723 | tw32_f(MAC_STATUS, | |
4724 | (MAC_STATUS_SYNC_CHANGED | | |
4725 | MAC_STATUS_CFG_CHANGED | | |
4726 | MAC_STATUS_MI_COMPLETION | | |
4727 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4728 | udelay(40); | |
4729 | } else | |
4730 | tg3_setup_phy(tp, 0); | |
f47c11ee | 4731 | spin_unlock(&tp->lock); |
1da177e4 LT |
4732 | } |
4733 | } | |
4734 | ||
4735 | /* run TX completion thread */ | |
f3f3f27e | 4736 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 4737 | tg3_tx(tnapi); |
6f535763 | 4738 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) |
4fd7ab59 | 4739 | return work_done; |
1da177e4 LT |
4740 | } |
4741 | ||
1da177e4 LT |
4742 | /* run RX thread, within the bounds set by NAPI. |
4743 | * All RX "locking" is done by ensuring outside | |
bea3348e | 4744 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 4745 | */ |
8d9d7cfc | 4746 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 4747 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 4748 | |
6f535763 DM |
4749 | return work_done; |
4750 | } | |
4751 | ||
4752 | static int tg3_poll(struct napi_struct *napi, int budget) | |
4753 | { | |
8ef0442f MC |
4754 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
4755 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 4756 | int work_done = 0; |
898a56f8 | 4757 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
4758 | |
4759 | while (1) { | |
17375d25 | 4760 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 DM |
4761 | |
4762 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
4763 | goto tx_recovery; | |
4764 | ||
4765 | if (unlikely(work_done >= budget)) | |
4766 | break; | |
4767 | ||
4fd7ab59 | 4768 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { |
17375d25 | 4769 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
4770 | * to tell the hw how much work has been processed, |
4771 | * so we must read it before checking for more work. | |
4772 | */ | |
898a56f8 MC |
4773 | tnapi->last_tag = sblk->status_tag; |
4774 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
4775 | rmb(); |
4776 | } else | |
4777 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 4778 | |
17375d25 | 4779 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 4780 | napi_complete(napi); |
17375d25 | 4781 | tg3_int_reenable(tnapi); |
6f535763 DM |
4782 | break; |
4783 | } | |
1da177e4 LT |
4784 | } |
4785 | ||
bea3348e | 4786 | return work_done; |
6f535763 DM |
4787 | |
4788 | tx_recovery: | |
4fd7ab59 | 4789 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 4790 | napi_complete(napi); |
6f535763 | 4791 | schedule_work(&tp->reset_task); |
4fd7ab59 | 4792 | return work_done; |
1da177e4 LT |
4793 | } |
4794 | ||
f47c11ee DM |
4795 | static void tg3_irq_quiesce(struct tg3 *tp) |
4796 | { | |
4f125f42 MC |
4797 | int i; |
4798 | ||
f47c11ee DM |
4799 | BUG_ON(tp->irq_sync); |
4800 | ||
4801 | tp->irq_sync = 1; | |
4802 | smp_mb(); | |
4803 | ||
4f125f42 MC |
4804 | for (i = 0; i < tp->irq_cnt; i++) |
4805 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
4806 | } |
4807 | ||
4808 | static inline int tg3_irq_sync(struct tg3 *tp) | |
4809 | { | |
4810 | return tp->irq_sync; | |
4811 | } | |
4812 | ||
4813 | /* Fully shutdown all tg3 driver activity elsewhere in the system. | |
4814 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
4815 | * with as well. Most of the time, this is not necessary except when | |
4816 | * shutting down the device. | |
4817 | */ | |
4818 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
4819 | { | |
46966545 | 4820 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
4821 | if (irq_sync) |
4822 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
4823 | } |
4824 | ||
4825 | static inline void tg3_full_unlock(struct tg3 *tp) | |
4826 | { | |
f47c11ee DM |
4827 | spin_unlock_bh(&tp->lock); |
4828 | } | |
4829 | ||
fcfa0a32 MC |
4830 | /* One-shot MSI handler - Chip automatically disables interrupt |
4831 | * after sending MSI so driver doesn't have to do it. | |
4832 | */ | |
7d12e780 | 4833 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 4834 | { |
09943a18 MC |
4835 | struct tg3_napi *tnapi = dev_id; |
4836 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 4837 | |
898a56f8 | 4838 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
4839 | if (tnapi->rx_rcb) |
4840 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
4841 | |
4842 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 4843 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
4844 | |
4845 | return IRQ_HANDLED; | |
4846 | } | |
4847 | ||
88b06bc2 MC |
4848 | /* MSI ISR - No need to check for interrupt sharing and no need to |
4849 | * flush status block and interrupt mailbox. PCI ordering rules | |
4850 | * guarantee that MSI will arrive after the status block. | |
4851 | */ | |
7d12e780 | 4852 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 4853 | { |
09943a18 MC |
4854 | struct tg3_napi *tnapi = dev_id; |
4855 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 4856 | |
898a56f8 | 4857 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
4858 | if (tnapi->rx_rcb) |
4859 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 4860 | /* |
fac9b83e | 4861 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 4862 | * chip-internal interrupt pending events. |
fac9b83e | 4863 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
4864 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
4865 | * event coalescing. | |
4866 | */ | |
4867 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 4868 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 4869 | napi_schedule(&tnapi->napi); |
61487480 | 4870 | |
88b06bc2 MC |
4871 | return IRQ_RETVAL(1); |
4872 | } | |
4873 | ||
7d12e780 | 4874 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 4875 | { |
09943a18 MC |
4876 | struct tg3_napi *tnapi = dev_id; |
4877 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 4878 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
4879 | unsigned int handled = 1; |
4880 | ||
1da177e4 LT |
4881 | /* In INTx mode, it is possible for the interrupt to arrive at |
4882 | * the CPU before the status block posted prior to the interrupt. | |
4883 | * Reading the PCI State register will confirm whether the | |
4884 | * interrupt is ours and will flush the status block. | |
4885 | */ | |
d18edcb2 MC |
4886 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
4887 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
4888 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
4889 | handled = 0; | |
f47c11ee | 4890 | goto out; |
fac9b83e | 4891 | } |
d18edcb2 MC |
4892 | } |
4893 | ||
4894 | /* | |
4895 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
4896 | * chip-internal interrupt pending events. | |
4897 | * Writing non-zero to intr-mbox-0 additional tells the | |
4898 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
4899 | * event coalescing. | |
c04cb347 MC |
4900 | * |
4901 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
4902 | * spurious interrupts. The flush impacts performance but | |
4903 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 4904 | */ |
c04cb347 | 4905 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
4906 | if (tg3_irq_sync(tp)) |
4907 | goto out; | |
4908 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 4909 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 4910 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 4911 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
4912 | } else { |
4913 | /* No work, shared interrupt perhaps? re-enable | |
4914 | * interrupts, and flush that PCI write | |
4915 | */ | |
4916 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
4917 | 0x00000000); | |
fac9b83e | 4918 | } |
f47c11ee | 4919 | out: |
fac9b83e DM |
4920 | return IRQ_RETVAL(handled); |
4921 | } | |
4922 | ||
7d12e780 | 4923 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 4924 | { |
09943a18 MC |
4925 | struct tg3_napi *tnapi = dev_id; |
4926 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 4927 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
4928 | unsigned int handled = 1; |
4929 | ||
fac9b83e DM |
4930 | /* In INTx mode, it is possible for the interrupt to arrive at |
4931 | * the CPU before the status block posted prior to the interrupt. | |
4932 | * Reading the PCI State register will confirm whether the | |
4933 | * interrupt is ours and will flush the status block. | |
4934 | */ | |
898a56f8 | 4935 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
d18edcb2 MC |
4936 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || |
4937 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
4938 | handled = 0; | |
f47c11ee | 4939 | goto out; |
1da177e4 | 4940 | } |
d18edcb2 MC |
4941 | } |
4942 | ||
4943 | /* | |
4944 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
4945 | * chip-internal interrupt pending events. | |
4946 | * writing non-zero to intr-mbox-0 additional tells the | |
4947 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
4948 | * event coalescing. | |
c04cb347 MC |
4949 | * |
4950 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
4951 | * spurious interrupts. The flush impacts performance but | |
4952 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 4953 | */ |
c04cb347 | 4954 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
4955 | |
4956 | /* | |
4957 | * In a shared interrupt configuration, sometimes other devices' | |
4958 | * interrupts will scream. We record the current status tag here | |
4959 | * so that the above check can report that the screaming interrupts | |
4960 | * are unhandled. Eventually they will be silenced. | |
4961 | */ | |
898a56f8 | 4962 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 4963 | |
d18edcb2 MC |
4964 | if (tg3_irq_sync(tp)) |
4965 | goto out; | |
624f8e50 | 4966 | |
72334482 | 4967 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 4968 | |
09943a18 | 4969 | napi_schedule(&tnapi->napi); |
624f8e50 | 4970 | |
f47c11ee | 4971 | out: |
1da177e4 LT |
4972 | return IRQ_RETVAL(handled); |
4973 | } | |
4974 | ||
7938109f | 4975 | /* ISR for interrupt test */ |
7d12e780 | 4976 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 4977 | { |
09943a18 MC |
4978 | struct tg3_napi *tnapi = dev_id; |
4979 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 4980 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 4981 | |
f9804ddb MC |
4982 | if ((sblk->status & SD_STATUS_UPDATED) || |
4983 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 4984 | tg3_disable_ints(tp); |
7938109f MC |
4985 | return IRQ_RETVAL(1); |
4986 | } | |
4987 | return IRQ_RETVAL(0); | |
4988 | } | |
4989 | ||
8e7a22e3 | 4990 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 4991 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 4992 | |
b9ec6c1b MC |
4993 | /* Restart hardware after configuration changes, self-test, etc. |
4994 | * Invoked with tp->lock held. | |
4995 | */ | |
4996 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
4997 | __releases(tp->lock) |
4998 | __acquires(tp->lock) | |
b9ec6c1b MC |
4999 | { |
5000 | int err; | |
5001 | ||
5002 | err = tg3_init_hw(tp, reset_phy); | |
5003 | if (err) { | |
5004 | printk(KERN_ERR PFX "%s: Failed to re-initialize device, " | |
5005 | "aborting.\n", tp->dev->name); | |
5006 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
5007 | tg3_full_unlock(tp); | |
5008 | del_timer_sync(&tp->timer); | |
5009 | tp->irq_sync = 0; | |
fed97810 | 5010 | tg3_napi_enable(tp); |
b9ec6c1b MC |
5011 | dev_close(tp->dev); |
5012 | tg3_full_lock(tp, 0); | |
5013 | } | |
5014 | return err; | |
5015 | } | |
5016 | ||
1da177e4 LT |
5017 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5018 | static void tg3_poll_controller(struct net_device *dev) | |
5019 | { | |
4f125f42 | 5020 | int i; |
88b06bc2 MC |
5021 | struct tg3 *tp = netdev_priv(dev); |
5022 | ||
4f125f42 MC |
5023 | for (i = 0; i < tp->irq_cnt; i++) |
5024 | tg3_interrupt(tp->napi[i].irq_vec, dev); | |
1da177e4 LT |
5025 | } |
5026 | #endif | |
5027 | ||
c4028958 | 5028 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 5029 | { |
c4028958 | 5030 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 5031 | int err; |
1da177e4 LT |
5032 | unsigned int restart_timer; |
5033 | ||
7faa006f | 5034 | tg3_full_lock(tp, 0); |
7faa006f MC |
5035 | |
5036 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
5037 | tg3_full_unlock(tp); |
5038 | return; | |
5039 | } | |
5040 | ||
5041 | tg3_full_unlock(tp); | |
5042 | ||
b02fd9e3 MC |
5043 | tg3_phy_stop(tp); |
5044 | ||
1da177e4 LT |
5045 | tg3_netif_stop(tp); |
5046 | ||
f47c11ee | 5047 | tg3_full_lock(tp, 1); |
1da177e4 LT |
5048 | |
5049 | restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; | |
5050 | tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; | |
5051 | ||
df3e6548 MC |
5052 | if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { |
5053 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
5054 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
5055 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
5056 | tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; | |
5057 | } | |
5058 | ||
944d980e | 5059 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
5060 | err = tg3_init_hw(tp, 1); |
5061 | if (err) | |
b9ec6c1b | 5062 | goto out; |
1da177e4 LT |
5063 | |
5064 | tg3_netif_start(tp); | |
5065 | ||
1da177e4 LT |
5066 | if (restart_timer) |
5067 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 5068 | |
b9ec6c1b | 5069 | out: |
7faa006f | 5070 | tg3_full_unlock(tp); |
b02fd9e3 MC |
5071 | |
5072 | if (!err) | |
5073 | tg3_phy_start(tp); | |
1da177e4 LT |
5074 | } |
5075 | ||
b0408751 MC |
5076 | static void tg3_dump_short_state(struct tg3 *tp) |
5077 | { | |
5078 | printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n", | |
5079 | tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS)); | |
5080 | printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n", | |
5081 | tr32(RDMAC_STATUS), tr32(WDMAC_STATUS)); | |
5082 | } | |
5083 | ||
1da177e4 LT |
5084 | static void tg3_tx_timeout(struct net_device *dev) |
5085 | { | |
5086 | struct tg3 *tp = netdev_priv(dev); | |
5087 | ||
b0408751 | 5088 | if (netif_msg_tx_err(tp)) { |
9f88f29f MC |
5089 | printk(KERN_ERR PFX "%s: transmit timed out, resetting\n", |
5090 | dev->name); | |
b0408751 MC |
5091 | tg3_dump_short_state(tp); |
5092 | } | |
1da177e4 LT |
5093 | |
5094 | schedule_work(&tp->reset_task); | |
5095 | } | |
5096 | ||
c58ec932 MC |
5097 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5098 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5099 | { | |
5100 | u32 base = (u32) mapping & 0xffffffff; | |
5101 | ||
5102 | return ((base > 0xffffdcc0) && | |
5103 | (base + len + 8 < base)); | |
5104 | } | |
5105 | ||
72f2afb8 MC |
5106 | /* Test for DMA addresses > 40-bit */ |
5107 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5108 | int len) | |
5109 | { | |
5110 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
6728a8e2 | 5111 | if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) |
50cf156a | 5112 | return (((u64) mapping + len) > DMA_BIT_MASK(40)); |
72f2afb8 MC |
5113 | return 0; |
5114 | #else | |
5115 | return 0; | |
5116 | #endif | |
5117 | } | |
5118 | ||
f3f3f27e | 5119 | static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32); |
1da177e4 | 5120 | |
72f2afb8 | 5121 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 MC |
5122 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
5123 | struct sk_buff *skb, u32 last_plus_one, | |
5124 | u32 *start, u32 base_flags, u32 mss) | |
1da177e4 | 5125 | { |
24f4efd4 | 5126 | struct tg3 *tp = tnapi->tp; |
41588ba1 | 5127 | struct sk_buff *new_skb; |
c58ec932 | 5128 | dma_addr_t new_addr = 0; |
1da177e4 | 5129 | u32 entry = *start; |
c58ec932 | 5130 | int i, ret = 0; |
1da177e4 | 5131 | |
41588ba1 MC |
5132 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
5133 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5134 | else { | |
5135 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5136 | ||
5137 | new_skb = skb_copy_expand(skb, | |
5138 | skb_headroom(skb) + more_headroom, | |
5139 | skb_tailroom(skb), GFP_ATOMIC); | |
5140 | } | |
5141 | ||
1da177e4 | 5142 | if (!new_skb) { |
c58ec932 MC |
5143 | ret = -1; |
5144 | } else { | |
5145 | /* New SKB is guaranteed to be linear. */ | |
5146 | entry = *start; | |
90079ce8 | 5147 | ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE); |
042a53a9 | 5148 | new_addr = skb_shinfo(new_skb)->dma_head; |
90079ce8 | 5149 | |
c58ec932 MC |
5150 | /* Make sure new skb does not cross any 4G boundaries. |
5151 | * Drop the packet if it does. | |
5152 | */ | |
0e1406dd MC |
5153 | if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5154 | tg3_4g_overflow_test(new_addr, new_skb->len))) { | |
638266f7 DM |
5155 | if (!ret) |
5156 | skb_dma_unmap(&tp->pdev->dev, new_skb, | |
5157 | DMA_TO_DEVICE); | |
c58ec932 MC |
5158 | ret = -1; |
5159 | dev_kfree_skb(new_skb); | |
5160 | new_skb = NULL; | |
5161 | } else { | |
f3f3f27e | 5162 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, |
c58ec932 MC |
5163 | base_flags, 1 | (mss << 1)); |
5164 | *start = NEXT_TX(entry); | |
5165 | } | |
1da177e4 LT |
5166 | } |
5167 | ||
1da177e4 LT |
5168 | /* Now clean up the sw ring entries. */ |
5169 | i = 0; | |
5170 | while (entry != last_plus_one) { | |
f3f3f27e MC |
5171 | if (i == 0) |
5172 | tnapi->tx_buffers[entry].skb = new_skb; | |
5173 | else | |
5174 | tnapi->tx_buffers[entry].skb = NULL; | |
1da177e4 LT |
5175 | entry = NEXT_TX(entry); |
5176 | i++; | |
5177 | } | |
5178 | ||
90079ce8 | 5179 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); |
1da177e4 LT |
5180 | dev_kfree_skb(skb); |
5181 | ||
c58ec932 | 5182 | return ret; |
1da177e4 LT |
5183 | } |
5184 | ||
f3f3f27e | 5185 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, |
1da177e4 LT |
5186 | dma_addr_t mapping, int len, u32 flags, |
5187 | u32 mss_and_is_end) | |
5188 | { | |
f3f3f27e | 5189 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; |
1da177e4 LT |
5190 | int is_end = (mss_and_is_end & 0x1); |
5191 | u32 mss = (mss_and_is_end >> 1); | |
5192 | u32 vlan_tag = 0; | |
5193 | ||
5194 | if (is_end) | |
5195 | flags |= TXD_FLAG_END; | |
5196 | if (flags & TXD_FLAG_VLAN) { | |
5197 | vlan_tag = flags >> 16; | |
5198 | flags &= 0xffff; | |
5199 | } | |
5200 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5201 | ||
5202 | txd->addr_hi = ((u64) mapping >> 32); | |
5203 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5204 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5205 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5206 | } | |
5207 | ||
5a6f3074 | 5208 | /* hard_start_xmit for devices that don't have any bugs and |
e849cdc3 | 5209 | * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only. |
5a6f3074 | 5210 | */ |
61357325 SH |
5211 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, |
5212 | struct net_device *dev) | |
5a6f3074 MC |
5213 | { |
5214 | struct tg3 *tp = netdev_priv(dev); | |
5a6f3074 | 5215 | u32 len, entry, base_flags, mss; |
90079ce8 DM |
5216 | struct skb_shared_info *sp; |
5217 | dma_addr_t mapping; | |
fe5f5787 MC |
5218 | struct tg3_napi *tnapi; |
5219 | struct netdev_queue *txq; | |
5a6f3074 | 5220 | |
fe5f5787 MC |
5221 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5222 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
5223 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) | |
5224 | tnapi++; | |
5a6f3074 | 5225 | |
00b70504 | 5226 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5227 | * and TX reclaim runs via tp->napi.poll inside of a software |
5a6f3074 MC |
5228 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5229 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5230 | */ | |
f3f3f27e | 5231 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
fe5f5787 MC |
5232 | if (!netif_tx_queue_stopped(txq)) { |
5233 | netif_tx_stop_queue(txq); | |
5a6f3074 MC |
5234 | |
5235 | /* This is a hard error, log it. */ | |
5236 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when " | |
5237 | "queue awake!\n", dev->name); | |
5238 | } | |
5a6f3074 MC |
5239 | return NETDEV_TX_BUSY; |
5240 | } | |
5241 | ||
f3f3f27e | 5242 | entry = tnapi->tx_prod; |
5a6f3074 | 5243 | base_flags = 0; |
5a6f3074 | 5244 | mss = 0; |
c13e3713 | 5245 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { |
5a6f3074 | 5246 | int tcp_opt_len, ip_tcp_len; |
f6eb9b1f | 5247 | u32 hdrlen; |
5a6f3074 MC |
5248 | |
5249 | if (skb_header_cloned(skb) && | |
5250 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5251 | dev_kfree_skb(skb); | |
5252 | goto out_unlock; | |
5253 | } | |
5254 | ||
b0026624 | 5255 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) |
f6eb9b1f | 5256 | hdrlen = skb_headlen(skb) - ETH_HLEN; |
b0026624 | 5257 | else { |
eddc9ec5 ACM |
5258 | struct iphdr *iph = ip_hdr(skb); |
5259 | ||
ab6a5bb6 | 5260 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5261 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
b0026624 | 5262 | |
eddc9ec5 ACM |
5263 | iph->check = 0; |
5264 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
f6eb9b1f | 5265 | hdrlen = ip_tcp_len + tcp_opt_len; |
b0026624 | 5266 | } |
5a6f3074 | 5267 | |
e849cdc3 | 5268 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
f6eb9b1f MC |
5269 | mss |= (hdrlen & 0xc) << 12; |
5270 | if (hdrlen & 0x10) | |
5271 | base_flags |= 0x00000010; | |
5272 | base_flags |= (hdrlen & 0x3e0) << 5; | |
5273 | } else | |
5274 | mss |= hdrlen << 9; | |
5275 | ||
5a6f3074 MC |
5276 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5277 | TXD_FLAG_CPU_POST_DMA); | |
5278 | ||
aa8223c7 | 5279 | tcp_hdr(skb)->check = 0; |
5a6f3074 | 5280 | |
5a6f3074 | 5281 | } |
84fa7933 | 5282 | else if (skb->ip_summed == CHECKSUM_PARTIAL) |
5a6f3074 | 5283 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
5a6f3074 MC |
5284 | #if TG3_VLAN_TAG_USED |
5285 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
5286 | base_flags |= (TXD_FLAG_VLAN | | |
5287 | (vlan_tx_tag_get(skb) << 16)); | |
5288 | #endif | |
5289 | ||
90079ce8 DM |
5290 | if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) { |
5291 | dev_kfree_skb(skb); | |
5292 | goto out_unlock; | |
5293 | } | |
5294 | ||
5295 | sp = skb_shinfo(skb); | |
5296 | ||
042a53a9 | 5297 | mapping = sp->dma_head; |
5a6f3074 | 5298 | |
f3f3f27e | 5299 | tnapi->tx_buffers[entry].skb = skb; |
5a6f3074 | 5300 | |
fe5f5787 MC |
5301 | len = skb_headlen(skb); |
5302 | ||
f6eb9b1f MC |
5303 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && |
5304 | !mss && skb->len > ETH_DATA_LEN) | |
5305 | base_flags |= TXD_FLAG_JMB_PKT; | |
5306 | ||
f3f3f27e | 5307 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
5a6f3074 MC |
5308 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5309 | ||
5310 | entry = NEXT_TX(entry); | |
5311 | ||
5312 | /* Now loop through additional data fragments, and queue them. */ | |
5313 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5314 | unsigned int i, last; | |
5315 | ||
5316 | last = skb_shinfo(skb)->nr_frags - 1; | |
5317 | for (i = 0; i <= last; i++) { | |
5318 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5319 | ||
5320 | len = frag->size; | |
042a53a9 | 5321 | mapping = sp->dma_maps[i]; |
f3f3f27e | 5322 | tnapi->tx_buffers[entry].skb = NULL; |
5a6f3074 | 5323 | |
f3f3f27e | 5324 | tg3_set_txd(tnapi, entry, mapping, len, |
5a6f3074 MC |
5325 | base_flags, (i == last) | (mss << 1)); |
5326 | ||
5327 | entry = NEXT_TX(entry); | |
5328 | } | |
5329 | } | |
5330 | ||
5331 | /* Packets are ready, update Tx producer idx local and on card. */ | |
f3f3f27e | 5332 | tw32_tx_mbox(tnapi->prodmbox, entry); |
5a6f3074 | 5333 | |
f3f3f27e MC |
5334 | tnapi->tx_prod = entry; |
5335 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
fe5f5787 | 5336 | netif_tx_stop_queue(txq); |
f3f3f27e | 5337 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
fe5f5787 | 5338 | netif_tx_wake_queue(txq); |
5a6f3074 MC |
5339 | } |
5340 | ||
5341 | out_unlock: | |
cdd0db05 | 5342 | mmiowb(); |
5a6f3074 MC |
5343 | |
5344 | return NETDEV_TX_OK; | |
5345 | } | |
5346 | ||
61357325 SH |
5347 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *, |
5348 | struct net_device *); | |
52c0fd83 MC |
5349 | |
5350 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5351 | * TSO header is greater than 80 bytes. | |
5352 | */ | |
5353 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5354 | { | |
5355 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 5356 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
5357 | |
5358 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 5359 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 5360 | netif_stop_queue(tp->dev); |
f3f3f27e | 5361 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
5362 | return NETDEV_TX_BUSY; |
5363 | ||
5364 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
5365 | } |
5366 | ||
5367 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 5368 | if (IS_ERR(segs)) |
52c0fd83 MC |
5369 | goto tg3_tso_bug_end; |
5370 | ||
5371 | do { | |
5372 | nskb = segs; | |
5373 | segs = segs->next; | |
5374 | nskb->next = NULL; | |
5375 | tg3_start_xmit_dma_bug(nskb, tp->dev); | |
5376 | } while (segs); | |
5377 | ||
5378 | tg3_tso_bug_end: | |
5379 | dev_kfree_skb(skb); | |
5380 | ||
5381 | return NETDEV_TX_OK; | |
5382 | } | |
52c0fd83 | 5383 | |
5a6f3074 MC |
5384 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
5385 | * support TG3_FLG2_HW_TSO_1 or firmware TSO only. | |
5386 | */ | |
61357325 SH |
5387 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb, |
5388 | struct net_device *dev) | |
1da177e4 LT |
5389 | { |
5390 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 5391 | u32 len, entry, base_flags, mss; |
90079ce8 | 5392 | struct skb_shared_info *sp; |
1da177e4 | 5393 | int would_hit_hwbug; |
90079ce8 | 5394 | dma_addr_t mapping; |
24f4efd4 MC |
5395 | struct tg3_napi *tnapi; |
5396 | struct netdev_queue *txq; | |
1da177e4 | 5397 | |
24f4efd4 MC |
5398 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5399 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
5400 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) | |
5401 | tnapi++; | |
1da177e4 | 5402 | |
00b70504 | 5403 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5404 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
5405 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5406 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 5407 | */ |
f3f3f27e | 5408 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
5409 | if (!netif_tx_queue_stopped(txq)) { |
5410 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
5411 | |
5412 | /* This is a hard error, log it. */ | |
5413 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when " | |
5414 | "queue awake!\n", dev->name); | |
5415 | } | |
1da177e4 LT |
5416 | return NETDEV_TX_BUSY; |
5417 | } | |
5418 | ||
f3f3f27e | 5419 | entry = tnapi->tx_prod; |
1da177e4 | 5420 | base_flags = 0; |
84fa7933 | 5421 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 5422 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 5423 | |
c13e3713 | 5424 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { |
eddc9ec5 | 5425 | struct iphdr *iph; |
92c6b8d1 | 5426 | u32 tcp_opt_len, ip_tcp_len, hdr_len; |
1da177e4 LT |
5427 | |
5428 | if (skb_header_cloned(skb) && | |
5429 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5430 | dev_kfree_skb(skb); | |
5431 | goto out_unlock; | |
5432 | } | |
5433 | ||
ab6a5bb6 | 5434 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5435 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
1da177e4 | 5436 | |
52c0fd83 MC |
5437 | hdr_len = ip_tcp_len + tcp_opt_len; |
5438 | if (unlikely((ETH_HLEN + hdr_len) > 80) && | |
7f62ad5d | 5439 | (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) |
52c0fd83 MC |
5440 | return (tg3_tso_bug(tp, skb)); |
5441 | ||
1da177e4 LT |
5442 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5443 | TXD_FLAG_CPU_POST_DMA); | |
5444 | ||
eddc9ec5 ACM |
5445 | iph = ip_hdr(skb); |
5446 | iph->check = 0; | |
5447 | iph->tot_len = htons(mss + hdr_len); | |
1da177e4 | 5448 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { |
aa8223c7 | 5449 | tcp_hdr(skb)->check = 0; |
1da177e4 | 5450 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
5451 | } else |
5452 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5453 | iph->daddr, 0, | |
5454 | IPPROTO_TCP, | |
5455 | 0); | |
1da177e4 | 5456 | |
615774fe MC |
5457 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
5458 | mss |= (hdr_len & 0xc) << 12; | |
5459 | if (hdr_len & 0x10) | |
5460 | base_flags |= 0x00000010; | |
5461 | base_flags |= (hdr_len & 0x3e0) << 5; | |
5462 | } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) | |
92c6b8d1 MC |
5463 | mss |= hdr_len << 9; |
5464 | else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) || | |
5465 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
eddc9ec5 | 5466 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5467 | int tsflags; |
5468 | ||
eddc9ec5 | 5469 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5470 | mss |= (tsflags << 11); |
5471 | } | |
5472 | } else { | |
eddc9ec5 | 5473 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5474 | int tsflags; |
5475 | ||
eddc9ec5 | 5476 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5477 | base_flags |= tsflags << 12; |
5478 | } | |
5479 | } | |
5480 | } | |
1da177e4 LT |
5481 | #if TG3_VLAN_TAG_USED |
5482 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
5483 | base_flags |= (TXD_FLAG_VLAN | | |
5484 | (vlan_tx_tag_get(skb) << 16)); | |
5485 | #endif | |
5486 | ||
615774fe MC |
5487 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && |
5488 | !mss && skb->len > ETH_DATA_LEN) | |
5489 | base_flags |= TXD_FLAG_JMB_PKT; | |
5490 | ||
90079ce8 DM |
5491 | if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) { |
5492 | dev_kfree_skb(skb); | |
5493 | goto out_unlock; | |
5494 | } | |
5495 | ||
5496 | sp = skb_shinfo(skb); | |
5497 | ||
042a53a9 | 5498 | mapping = sp->dma_head; |
1da177e4 | 5499 | |
f3f3f27e | 5500 | tnapi->tx_buffers[entry].skb = skb; |
1da177e4 LT |
5501 | |
5502 | would_hit_hwbug = 0; | |
5503 | ||
24f4efd4 MC |
5504 | len = skb_headlen(skb); |
5505 | ||
92c6b8d1 MC |
5506 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8) |
5507 | would_hit_hwbug = 1; | |
5508 | ||
0e1406dd MC |
5509 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5510 | tg3_4g_overflow_test(mapping, len)) | |
5511 | would_hit_hwbug = 1; | |
5512 | ||
5513 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && | |
5514 | tg3_40bit_overflow_test(tp, mapping, len)) | |
41588ba1 | 5515 | would_hit_hwbug = 1; |
0e1406dd MC |
5516 | |
5517 | if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) | |
c58ec932 | 5518 | would_hit_hwbug = 1; |
1da177e4 | 5519 | |
f3f3f27e | 5520 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
1da177e4 LT |
5521 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5522 | ||
5523 | entry = NEXT_TX(entry); | |
5524 | ||
5525 | /* Now loop through additional data fragments, and queue them. */ | |
5526 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5527 | unsigned int i, last; | |
5528 | ||
5529 | last = skb_shinfo(skb)->nr_frags - 1; | |
5530 | for (i = 0; i <= last; i++) { | |
5531 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5532 | ||
5533 | len = frag->size; | |
042a53a9 | 5534 | mapping = sp->dma_maps[i]; |
1da177e4 | 5535 | |
f3f3f27e | 5536 | tnapi->tx_buffers[entry].skb = NULL; |
1da177e4 | 5537 | |
92c6b8d1 MC |
5538 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && |
5539 | len <= 8) | |
5540 | would_hit_hwbug = 1; | |
5541 | ||
0e1406dd MC |
5542 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5543 | tg3_4g_overflow_test(mapping, len)) | |
c58ec932 | 5544 | would_hit_hwbug = 1; |
1da177e4 | 5545 | |
0e1406dd MC |
5546 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && |
5547 | tg3_40bit_overflow_test(tp, mapping, len)) | |
72f2afb8 MC |
5548 | would_hit_hwbug = 1; |
5549 | ||
1da177e4 | 5550 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
f3f3f27e | 5551 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
5552 | base_flags, (i == last)|(mss << 1)); |
5553 | else | |
f3f3f27e | 5554 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
5555 | base_flags, (i == last)); |
5556 | ||
5557 | entry = NEXT_TX(entry); | |
5558 | } | |
5559 | } | |
5560 | ||
5561 | if (would_hit_hwbug) { | |
5562 | u32 last_plus_one = entry; | |
5563 | u32 start; | |
1da177e4 | 5564 | |
c58ec932 MC |
5565 | start = entry - 1 - skb_shinfo(skb)->nr_frags; |
5566 | start &= (TG3_TX_RING_SIZE - 1); | |
1da177e4 LT |
5567 | |
5568 | /* If the workaround fails due to memory/mapping | |
5569 | * failure, silently drop this packet. | |
5570 | */ | |
24f4efd4 | 5571 | if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one, |
c58ec932 | 5572 | &start, base_flags, mss)) |
1da177e4 LT |
5573 | goto out_unlock; |
5574 | ||
5575 | entry = start; | |
5576 | } | |
5577 | ||
5578 | /* Packets are ready, update Tx producer idx local and on card. */ | |
24f4efd4 | 5579 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 5580 | |
f3f3f27e MC |
5581 | tnapi->tx_prod = entry; |
5582 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 5583 | netif_tx_stop_queue(txq); |
f3f3f27e | 5584 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 5585 | netif_tx_wake_queue(txq); |
51b91468 | 5586 | } |
1da177e4 LT |
5587 | |
5588 | out_unlock: | |
cdd0db05 | 5589 | mmiowb(); |
1da177e4 LT |
5590 | |
5591 | return NETDEV_TX_OK; | |
5592 | } | |
5593 | ||
5594 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, | |
5595 | int new_mtu) | |
5596 | { | |
5597 | dev->mtu = new_mtu; | |
5598 | ||
ef7f5ec0 | 5599 | if (new_mtu > ETH_DATA_LEN) { |
a4e2b347 | 5600 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { |
ef7f5ec0 MC |
5601 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
5602 | ethtool_op_set_tso(dev, 0); | |
5603 | } | |
5604 | else | |
5605 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; | |
5606 | } else { | |
a4e2b347 | 5607 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) |
ef7f5ec0 | 5608 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
0f893dc6 | 5609 | tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; |
ef7f5ec0 | 5610 | } |
1da177e4 LT |
5611 | } |
5612 | ||
5613 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
5614 | { | |
5615 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 5616 | int err; |
1da177e4 LT |
5617 | |
5618 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
5619 | return -EINVAL; | |
5620 | ||
5621 | if (!netif_running(dev)) { | |
5622 | /* We'll just catch it later when the | |
5623 | * device is up'd. | |
5624 | */ | |
5625 | tg3_set_mtu(dev, tp, new_mtu); | |
5626 | return 0; | |
5627 | } | |
5628 | ||
b02fd9e3 MC |
5629 | tg3_phy_stop(tp); |
5630 | ||
1da177e4 | 5631 | tg3_netif_stop(tp); |
f47c11ee DM |
5632 | |
5633 | tg3_full_lock(tp, 1); | |
1da177e4 | 5634 | |
944d980e | 5635 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
5636 | |
5637 | tg3_set_mtu(dev, tp, new_mtu); | |
5638 | ||
b9ec6c1b | 5639 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 5640 | |
b9ec6c1b MC |
5641 | if (!err) |
5642 | tg3_netif_start(tp); | |
1da177e4 | 5643 | |
f47c11ee | 5644 | tg3_full_unlock(tp); |
1da177e4 | 5645 | |
b02fd9e3 MC |
5646 | if (!err) |
5647 | tg3_phy_start(tp); | |
5648 | ||
b9ec6c1b | 5649 | return err; |
1da177e4 LT |
5650 | } |
5651 | ||
21f581a5 MC |
5652 | static void tg3_rx_prodring_free(struct tg3 *tp, |
5653 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 5654 | { |
1da177e4 | 5655 | int i; |
f3f3f27e | 5656 | struct ring_info *rxp; |
1da177e4 LT |
5657 | |
5658 | for (i = 0; i < TG3_RX_RING_SIZE; i++) { | |
21f581a5 | 5659 | rxp = &tpr->rx_std_buffers[i]; |
1da177e4 LT |
5660 | |
5661 | if (rxp->skb == NULL) | |
5662 | continue; | |
1da177e4 | 5663 | |
1da177e4 LT |
5664 | pci_unmap_single(tp->pdev, |
5665 | pci_unmap_addr(rxp, mapping), | |
cf7a7298 | 5666 | tp->rx_pkt_map_sz, |
1da177e4 LT |
5667 | PCI_DMA_FROMDEVICE); |
5668 | dev_kfree_skb_any(rxp->skb); | |
5669 | rxp->skb = NULL; | |
5670 | } | |
5671 | ||
cf7a7298 MC |
5672 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
5673 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { | |
21f581a5 | 5674 | rxp = &tpr->rx_jmb_buffers[i]; |
1da177e4 | 5675 | |
cf7a7298 MC |
5676 | if (rxp->skb == NULL) |
5677 | continue; | |
1da177e4 | 5678 | |
cf7a7298 MC |
5679 | pci_unmap_single(tp->pdev, |
5680 | pci_unmap_addr(rxp, mapping), | |
5681 | TG3_RX_JMB_MAP_SZ, | |
5682 | PCI_DMA_FROMDEVICE); | |
5683 | dev_kfree_skb_any(rxp->skb); | |
5684 | rxp->skb = NULL; | |
1da177e4 | 5685 | } |
1da177e4 LT |
5686 | } |
5687 | } | |
5688 | ||
5689 | /* Initialize tx/rx rings for packet processing. | |
5690 | * | |
5691 | * The chip has been shut down and the driver detached from | |
5692 | * the networking, so no interrupts or new tx packets will | |
5693 | * end up in the driver. tp->{tx,}lock are held and thus | |
5694 | * we may not sleep. | |
5695 | */ | |
21f581a5 MC |
5696 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
5697 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 5698 | { |
287be12e | 5699 | u32 i, rx_pkt_dma_sz; |
17375d25 | 5700 | struct tg3_napi *tnapi = &tp->napi[0]; |
1da177e4 | 5701 | |
1da177e4 | 5702 | /* Zero out all descriptors. */ |
21f581a5 | 5703 | memset(tpr->rx_std, 0, TG3_RX_RING_BYTES); |
1da177e4 | 5704 | |
287be12e | 5705 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
a4e2b347 | 5706 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && |
287be12e MC |
5707 | tp->dev->mtu > ETH_DATA_LEN) |
5708 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
5709 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 5710 | |
1da177e4 LT |
5711 | /* Initialize invariants of the rings, we only set this |
5712 | * stuff once. This works because the card does not | |
5713 | * write into the rx buffer posting rings. | |
5714 | */ | |
5715 | for (i = 0; i < TG3_RX_RING_SIZE; i++) { | |
5716 | struct tg3_rx_buffer_desc *rxd; | |
5717 | ||
21f581a5 | 5718 | rxd = &tpr->rx_std[i]; |
287be12e | 5719 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
5720 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
5721 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
5722 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
5723 | } | |
5724 | ||
1da177e4 LT |
5725 | /* Now allocate fresh SKBs for each rx ring. */ |
5726 | for (i = 0; i < tp->rx_pending; i++) { | |
17375d25 | 5727 | if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) { |
32d8c572 MC |
5728 | printk(KERN_WARNING PFX |
5729 | "%s: Using a smaller RX standard ring, " | |
5730 | "only %d out of %d buffers were allocated " | |
5731 | "successfully.\n", | |
5732 | tp->dev->name, i, tp->rx_pending); | |
5733 | if (i == 0) | |
cf7a7298 | 5734 | goto initfail; |
32d8c572 | 5735 | tp->rx_pending = i; |
1da177e4 | 5736 | break; |
32d8c572 | 5737 | } |
1da177e4 LT |
5738 | } |
5739 | ||
cf7a7298 MC |
5740 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)) |
5741 | goto done; | |
5742 | ||
21f581a5 | 5743 | memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES); |
cf7a7298 | 5744 | |
0f893dc6 | 5745 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { |
cf7a7298 MC |
5746 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { |
5747 | struct tg3_rx_buffer_desc *rxd; | |
5748 | ||
79ed5ac7 | 5749 | rxd = &tpr->rx_jmb[i].std; |
cf7a7298 MC |
5750 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; |
5751 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
5752 | RXD_FLAG_JUMBO; | |
5753 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
5754 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
5755 | } | |
5756 | ||
1da177e4 | 5757 | for (i = 0; i < tp->rx_jumbo_pending; i++) { |
17375d25 | 5758 | if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO, |
32d8c572 MC |
5759 | -1, i) < 0) { |
5760 | printk(KERN_WARNING PFX | |
5761 | "%s: Using a smaller RX jumbo ring, " | |
5762 | "only %d out of %d buffers were " | |
5763 | "allocated successfully.\n", | |
5764 | tp->dev->name, i, tp->rx_jumbo_pending); | |
cf7a7298 MC |
5765 | if (i == 0) |
5766 | goto initfail; | |
32d8c572 | 5767 | tp->rx_jumbo_pending = i; |
1da177e4 | 5768 | break; |
32d8c572 | 5769 | } |
1da177e4 LT |
5770 | } |
5771 | } | |
cf7a7298 MC |
5772 | |
5773 | done: | |
32d8c572 | 5774 | return 0; |
cf7a7298 MC |
5775 | |
5776 | initfail: | |
21f581a5 | 5777 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 5778 | return -ENOMEM; |
1da177e4 LT |
5779 | } |
5780 | ||
21f581a5 MC |
5781 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
5782 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 5783 | { |
21f581a5 MC |
5784 | kfree(tpr->rx_std_buffers); |
5785 | tpr->rx_std_buffers = NULL; | |
5786 | kfree(tpr->rx_jmb_buffers); | |
5787 | tpr->rx_jmb_buffers = NULL; | |
5788 | if (tpr->rx_std) { | |
1da177e4 | 5789 | pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES, |
21f581a5 MC |
5790 | tpr->rx_std, tpr->rx_std_mapping); |
5791 | tpr->rx_std = NULL; | |
1da177e4 | 5792 | } |
21f581a5 | 5793 | if (tpr->rx_jmb) { |
1da177e4 | 5794 | pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES, |
21f581a5 MC |
5795 | tpr->rx_jmb, tpr->rx_jmb_mapping); |
5796 | tpr->rx_jmb = NULL; | |
1da177e4 | 5797 | } |
cf7a7298 MC |
5798 | } |
5799 | ||
21f581a5 MC |
5800 | static int tg3_rx_prodring_init(struct tg3 *tp, |
5801 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 5802 | { |
21f581a5 MC |
5803 | tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) * |
5804 | TG3_RX_RING_SIZE, GFP_KERNEL); | |
5805 | if (!tpr->rx_std_buffers) | |
cf7a7298 MC |
5806 | return -ENOMEM; |
5807 | ||
21f581a5 MC |
5808 | tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES, |
5809 | &tpr->rx_std_mapping); | |
5810 | if (!tpr->rx_std) | |
cf7a7298 MC |
5811 | goto err_out; |
5812 | ||
5813 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
21f581a5 MC |
5814 | tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) * |
5815 | TG3_RX_JUMBO_RING_SIZE, | |
5816 | GFP_KERNEL); | |
5817 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
5818 | goto err_out; |
5819 | ||
21f581a5 MC |
5820 | tpr->rx_jmb = pci_alloc_consistent(tp->pdev, |
5821 | TG3_RX_JUMBO_RING_BYTES, | |
5822 | &tpr->rx_jmb_mapping); | |
5823 | if (!tpr->rx_jmb) | |
cf7a7298 MC |
5824 | goto err_out; |
5825 | } | |
5826 | ||
5827 | return 0; | |
5828 | ||
5829 | err_out: | |
21f581a5 | 5830 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
5831 | return -ENOMEM; |
5832 | } | |
5833 | ||
5834 | /* Free up pending packets in all rx/tx rings. | |
5835 | * | |
5836 | * The chip has been shut down and the driver detached from | |
5837 | * the networking, so no interrupts or new tx packets will | |
5838 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
5839 | * in an interrupt context and thus may sleep. | |
5840 | */ | |
5841 | static void tg3_free_rings(struct tg3 *tp) | |
5842 | { | |
f77a6a8e | 5843 | int i, j; |
cf7a7298 | 5844 | |
f77a6a8e MC |
5845 | for (j = 0; j < tp->irq_cnt; j++) { |
5846 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 5847 | |
0c1d0e2b MC |
5848 | if (!tnapi->tx_buffers) |
5849 | continue; | |
5850 | ||
f77a6a8e MC |
5851 | for (i = 0; i < TG3_TX_RING_SIZE; ) { |
5852 | struct tx_ring_info *txp; | |
5853 | struct sk_buff *skb; | |
cf7a7298 | 5854 | |
f77a6a8e MC |
5855 | txp = &tnapi->tx_buffers[i]; |
5856 | skb = txp->skb; | |
cf7a7298 | 5857 | |
f77a6a8e MC |
5858 | if (skb == NULL) { |
5859 | i++; | |
5860 | continue; | |
5861 | } | |
cf7a7298 | 5862 | |
f77a6a8e | 5863 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); |
cf7a7298 | 5864 | |
f77a6a8e | 5865 | txp->skb = NULL; |
cf7a7298 | 5866 | |
f77a6a8e MC |
5867 | i += skb_shinfo(skb)->nr_frags + 1; |
5868 | ||
5869 | dev_kfree_skb_any(skb); | |
5870 | } | |
cf7a7298 MC |
5871 | } |
5872 | ||
21f581a5 | 5873 | tg3_rx_prodring_free(tp, &tp->prodring[0]); |
cf7a7298 MC |
5874 | } |
5875 | ||
5876 | /* Initialize tx/rx rings for packet processing. | |
5877 | * | |
5878 | * The chip has been shut down and the driver detached from | |
5879 | * the networking, so no interrupts or new tx packets will | |
5880 | * end up in the driver. tp->{tx,}lock are held and thus | |
5881 | * we may not sleep. | |
5882 | */ | |
5883 | static int tg3_init_rings(struct tg3 *tp) | |
5884 | { | |
f77a6a8e | 5885 | int i; |
72334482 | 5886 | |
cf7a7298 MC |
5887 | /* Free up all the SKBs. */ |
5888 | tg3_free_rings(tp); | |
5889 | ||
f77a6a8e MC |
5890 | for (i = 0; i < tp->irq_cnt; i++) { |
5891 | struct tg3_napi *tnapi = &tp->napi[i]; | |
5892 | ||
5893 | tnapi->last_tag = 0; | |
5894 | tnapi->last_irq_tag = 0; | |
5895 | tnapi->hw_status->status = 0; | |
5896 | tnapi->hw_status->status_tag = 0; | |
5897 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 5898 | |
f77a6a8e MC |
5899 | tnapi->tx_prod = 0; |
5900 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
5901 | if (tnapi->tx_ring) |
5902 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
5903 | |
5904 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
5905 | if (tnapi->rx_rcb) |
5906 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
f77a6a8e | 5907 | } |
72334482 | 5908 | |
21f581a5 | 5909 | return tg3_rx_prodring_alloc(tp, &tp->prodring[0]); |
cf7a7298 MC |
5910 | } |
5911 | ||
5912 | /* | |
5913 | * Must not be invoked with interrupt sources disabled and | |
5914 | * the hardware shutdown down. | |
5915 | */ | |
5916 | static void tg3_free_consistent(struct tg3 *tp) | |
5917 | { | |
f77a6a8e | 5918 | int i; |
898a56f8 | 5919 | |
f77a6a8e MC |
5920 | for (i = 0; i < tp->irq_cnt; i++) { |
5921 | struct tg3_napi *tnapi = &tp->napi[i]; | |
5922 | ||
5923 | if (tnapi->tx_ring) { | |
5924 | pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES, | |
5925 | tnapi->tx_ring, tnapi->tx_desc_mapping); | |
5926 | tnapi->tx_ring = NULL; | |
5927 | } | |
5928 | ||
5929 | kfree(tnapi->tx_buffers); | |
5930 | tnapi->tx_buffers = NULL; | |
5931 | ||
5932 | if (tnapi->rx_rcb) { | |
5933 | pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp), | |
5934 | tnapi->rx_rcb, | |
5935 | tnapi->rx_rcb_mapping); | |
5936 | tnapi->rx_rcb = NULL; | |
5937 | } | |
5938 | ||
5939 | if (tnapi->hw_status) { | |
5940 | pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE, | |
5941 | tnapi->hw_status, | |
5942 | tnapi->status_mapping); | |
5943 | tnapi->hw_status = NULL; | |
5944 | } | |
1da177e4 | 5945 | } |
f77a6a8e | 5946 | |
1da177e4 LT |
5947 | if (tp->hw_stats) { |
5948 | pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats), | |
5949 | tp->hw_stats, tp->stats_mapping); | |
5950 | tp->hw_stats = NULL; | |
5951 | } | |
f77a6a8e | 5952 | |
21f581a5 | 5953 | tg3_rx_prodring_fini(tp, &tp->prodring[0]); |
1da177e4 LT |
5954 | } |
5955 | ||
5956 | /* | |
5957 | * Must not be invoked with interrupt sources disabled and | |
5958 | * the hardware shutdown down. Can sleep. | |
5959 | */ | |
5960 | static int tg3_alloc_consistent(struct tg3 *tp) | |
5961 | { | |
f77a6a8e | 5962 | int i; |
898a56f8 | 5963 | |
21f581a5 | 5964 | if (tg3_rx_prodring_init(tp, &tp->prodring[0])) |
1da177e4 LT |
5965 | return -ENOMEM; |
5966 | ||
f77a6a8e MC |
5967 | tp->hw_stats = pci_alloc_consistent(tp->pdev, |
5968 | sizeof(struct tg3_hw_stats), | |
5969 | &tp->stats_mapping); | |
5970 | if (!tp->hw_stats) | |
1da177e4 LT |
5971 | goto err_out; |
5972 | ||
f77a6a8e | 5973 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 5974 | |
f77a6a8e MC |
5975 | for (i = 0; i < tp->irq_cnt; i++) { |
5976 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 5977 | struct tg3_hw_status *sblk; |
1da177e4 | 5978 | |
f77a6a8e MC |
5979 | tnapi->hw_status = pci_alloc_consistent(tp->pdev, |
5980 | TG3_HW_STATUS_SIZE, | |
5981 | &tnapi->status_mapping); | |
5982 | if (!tnapi->hw_status) | |
5983 | goto err_out; | |
898a56f8 | 5984 | |
f77a6a8e | 5985 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
5986 | sblk = tnapi->hw_status; |
5987 | ||
5988 | /* | |
5989 | * When RSS is enabled, the status block format changes | |
5990 | * slightly. The "rx_jumbo_consumer", "reserved", | |
5991 | * and "rx_mini_consumer" members get mapped to the | |
5992 | * other three rx return ring producer indexes. | |
5993 | */ | |
5994 | switch (i) { | |
5995 | default: | |
5996 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
5997 | break; | |
5998 | case 2: | |
5999 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6000 | break; | |
6001 | case 3: | |
6002 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6003 | break; | |
6004 | case 4: | |
6005 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6006 | break; | |
6007 | } | |
72334482 | 6008 | |
0c1d0e2b MC |
6009 | /* |
6010 | * If multivector RSS is enabled, vector 0 does not handle | |
6011 | * rx or tx interrupts. Don't allocate any resources for it. | |
6012 | */ | |
6013 | if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) | |
6014 | continue; | |
6015 | ||
f77a6a8e MC |
6016 | tnapi->rx_rcb = pci_alloc_consistent(tp->pdev, |
6017 | TG3_RX_RCB_RING_BYTES(tp), | |
6018 | &tnapi->rx_rcb_mapping); | |
6019 | if (!tnapi->rx_rcb) | |
6020 | goto err_out; | |
72334482 | 6021 | |
f77a6a8e | 6022 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
1da177e4 | 6023 | |
f77a6a8e MC |
6024 | tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) * |
6025 | TG3_TX_RING_SIZE, GFP_KERNEL); | |
6026 | if (!tnapi->tx_buffers) | |
6027 | goto err_out; | |
6028 | ||
6029 | tnapi->tx_ring = pci_alloc_consistent(tp->pdev, | |
6030 | TG3_TX_RING_BYTES, | |
6031 | &tnapi->tx_desc_mapping); | |
6032 | if (!tnapi->tx_ring) | |
6033 | goto err_out; | |
6034 | } | |
1da177e4 LT |
6035 | |
6036 | return 0; | |
6037 | ||
6038 | err_out: | |
6039 | tg3_free_consistent(tp); | |
6040 | return -ENOMEM; | |
6041 | } | |
6042 | ||
6043 | #define MAX_WAIT_CNT 1000 | |
6044 | ||
6045 | /* To stop a block, clear the enable bit and poll till it | |
6046 | * clears. tp->lock is held. | |
6047 | */ | |
b3b7d6be | 6048 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
6049 | { |
6050 | unsigned int i; | |
6051 | u32 val; | |
6052 | ||
6053 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
6054 | switch (ofs) { | |
6055 | case RCVLSC_MODE: | |
6056 | case DMAC_MODE: | |
6057 | case MBFREE_MODE: | |
6058 | case BUFMGR_MODE: | |
6059 | case MEMARB_MODE: | |
6060 | /* We can't enable/disable these bits of the | |
6061 | * 5705/5750, just say success. | |
6062 | */ | |
6063 | return 0; | |
6064 | ||
6065 | default: | |
6066 | break; | |
855e1111 | 6067 | } |
1da177e4 LT |
6068 | } |
6069 | ||
6070 | val = tr32(ofs); | |
6071 | val &= ~enable_bit; | |
6072 | tw32_f(ofs, val); | |
6073 | ||
6074 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6075 | udelay(100); | |
6076 | val = tr32(ofs); | |
6077 | if ((val & enable_bit) == 0) | |
6078 | break; | |
6079 | } | |
6080 | ||
b3b7d6be | 6081 | if (i == MAX_WAIT_CNT && !silent) { |
1da177e4 LT |
6082 | printk(KERN_ERR PFX "tg3_stop_block timed out, " |
6083 | "ofs=%lx enable_bit=%x\n", | |
6084 | ofs, enable_bit); | |
6085 | return -ENODEV; | |
6086 | } | |
6087 | ||
6088 | return 0; | |
6089 | } | |
6090 | ||
6091 | /* tp->lock is held. */ | |
b3b7d6be | 6092 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
6093 | { |
6094 | int i, err; | |
6095 | ||
6096 | tg3_disable_ints(tp); | |
6097 | ||
6098 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6099 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6100 | udelay(10); | |
6101 | ||
b3b7d6be DM |
6102 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
6103 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6104 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6105 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6106 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6107 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6108 | ||
6109 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6110 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6111 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6112 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6113 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6114 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6115 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
6116 | |
6117 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6118 | tw32_f(MAC_MODE, tp->mac_mode); | |
6119 | udelay(40); | |
6120 | ||
6121 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6122 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6123 | ||
6124 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6125 | udelay(100); | |
6126 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6127 | break; | |
6128 | } | |
6129 | if (i >= MAX_WAIT_CNT) { | |
6130 | printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, " | |
6131 | "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n", | |
6132 | tp->dev->name, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 6133 | err |= -ENODEV; |
1da177e4 LT |
6134 | } |
6135 | ||
e6de8ad1 | 6136 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
6137 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
6138 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
6139 | |
6140 | tw32(FTQ_RESET, 0xffffffff); | |
6141 | tw32(FTQ_RESET, 0x00000000); | |
6142 | ||
b3b7d6be DM |
6143 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
6144 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 6145 | |
f77a6a8e MC |
6146 | for (i = 0; i < tp->irq_cnt; i++) { |
6147 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6148 | if (tnapi->hw_status) | |
6149 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6150 | } | |
1da177e4 LT |
6151 | if (tp->hw_stats) |
6152 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6153 | ||
1da177e4 LT |
6154 | return err; |
6155 | } | |
6156 | ||
0d3031d9 MC |
6157 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
6158 | { | |
6159 | int i; | |
6160 | u32 apedata; | |
6161 | ||
6162 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
6163 | if (apedata != APE_SEG_SIG_MAGIC) | |
6164 | return; | |
6165 | ||
6166 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 6167 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
6168 | return; |
6169 | ||
6170 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6171 | for (i = 0; i < 10; i++) { | |
6172 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6173 | return; | |
6174 | ||
6175 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6176 | ||
6177 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6178 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6179 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6180 | ||
6181 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6182 | ||
6183 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6184 | break; | |
6185 | ||
6186 | udelay(100); | |
6187 | } | |
6188 | ||
6189 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6190 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6191 | } | |
6192 | ||
6193 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6194 | { | |
6195 | u32 event; | |
6196 | u32 apedata; | |
6197 | ||
6198 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
6199 | return; | |
6200 | ||
6201 | switch (kind) { | |
6202 | case RESET_KIND_INIT: | |
6203 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6204 | APE_HOST_SEG_SIG_MAGIC); | |
6205 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6206 | APE_HOST_SEG_LEN_MAGIC); | |
6207 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6208 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6209 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6210 | APE_HOST_DRIVER_ID_MAGIC); | |
6211 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
6212 | APE_HOST_BEHAV_NO_PHYLOCK); | |
6213 | ||
6214 | event = APE_EVENT_STATUS_STATE_START; | |
6215 | break; | |
6216 | case RESET_KIND_SHUTDOWN: | |
b2aee154 MC |
6217 | /* With the interface we are currently using, |
6218 | * APE does not track driver state. Wiping | |
6219 | * out the HOST SEGMENT SIGNATURE forces | |
6220 | * the APE to assume OS absent status. | |
6221 | */ | |
6222 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
6223 | ||
0d3031d9 MC |
6224 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
6225 | break; | |
6226 | case RESET_KIND_SUSPEND: | |
6227 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
6228 | break; | |
6229 | default: | |
6230 | return; | |
6231 | } | |
6232 | ||
6233 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
6234 | ||
6235 | tg3_ape_send_event(tp, event); | |
6236 | } | |
6237 | ||
1da177e4 LT |
6238 | /* tp->lock is held. */ |
6239 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
6240 | { | |
f49639e6 DM |
6241 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
6242 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 LT |
6243 | |
6244 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6245 | switch (kind) { | |
6246 | case RESET_KIND_INIT: | |
6247 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6248 | DRV_STATE_START); | |
6249 | break; | |
6250 | ||
6251 | case RESET_KIND_SHUTDOWN: | |
6252 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6253 | DRV_STATE_UNLOAD); | |
6254 | break; | |
6255 | ||
6256 | case RESET_KIND_SUSPEND: | |
6257 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6258 | DRV_STATE_SUSPEND); | |
6259 | break; | |
6260 | ||
6261 | default: | |
6262 | break; | |
855e1111 | 6263 | } |
1da177e4 | 6264 | } |
0d3031d9 MC |
6265 | |
6266 | if (kind == RESET_KIND_INIT || | |
6267 | kind == RESET_KIND_SUSPEND) | |
6268 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6269 | } |
6270 | ||
6271 | /* tp->lock is held. */ | |
6272 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
6273 | { | |
6274 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6275 | switch (kind) { | |
6276 | case RESET_KIND_INIT: | |
6277 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6278 | DRV_STATE_START_DONE); | |
6279 | break; | |
6280 | ||
6281 | case RESET_KIND_SHUTDOWN: | |
6282 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6283 | DRV_STATE_UNLOAD_DONE); | |
6284 | break; | |
6285 | ||
6286 | default: | |
6287 | break; | |
855e1111 | 6288 | } |
1da177e4 | 6289 | } |
0d3031d9 MC |
6290 | |
6291 | if (kind == RESET_KIND_SHUTDOWN) | |
6292 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6293 | } |
6294 | ||
6295 | /* tp->lock is held. */ | |
6296 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
6297 | { | |
6298 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
6299 | switch (kind) { | |
6300 | case RESET_KIND_INIT: | |
6301 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6302 | DRV_STATE_START); | |
6303 | break; | |
6304 | ||
6305 | case RESET_KIND_SHUTDOWN: | |
6306 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6307 | DRV_STATE_UNLOAD); | |
6308 | break; | |
6309 | ||
6310 | case RESET_KIND_SUSPEND: | |
6311 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6312 | DRV_STATE_SUSPEND); | |
6313 | break; | |
6314 | ||
6315 | default: | |
6316 | break; | |
855e1111 | 6317 | } |
1da177e4 LT |
6318 | } |
6319 | } | |
6320 | ||
7a6f4369 MC |
6321 | static int tg3_poll_fw(struct tg3 *tp) |
6322 | { | |
6323 | int i; | |
6324 | u32 val; | |
6325 | ||
b5d3772c | 6326 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
6327 | /* Wait up to 20ms for init done. */ |
6328 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
6329 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
6330 | return 0; | |
0ccead18 | 6331 | udelay(100); |
b5d3772c MC |
6332 | } |
6333 | return -ENODEV; | |
6334 | } | |
6335 | ||
7a6f4369 MC |
6336 | /* Wait for firmware initialization to complete. */ |
6337 | for (i = 0; i < 100000; i++) { | |
6338 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
6339 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
6340 | break; | |
6341 | udelay(10); | |
6342 | } | |
6343 | ||
6344 | /* Chip might not be fitted with firmware. Some Sun onboard | |
6345 | * parts are configured like that. So don't signal the timeout | |
6346 | * of the above loop as an error, but do report the lack of | |
6347 | * running firmware once. | |
6348 | */ | |
6349 | if (i >= 100000 && | |
6350 | !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { | |
6351 | tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED; | |
6352 | ||
6353 | printk(KERN_INFO PFX "%s: No firmware running.\n", | |
6354 | tp->dev->name); | |
6355 | } | |
6356 | ||
6357 | return 0; | |
6358 | } | |
6359 | ||
ee6a99b5 MC |
6360 | /* Save PCI command register before chip reset */ |
6361 | static void tg3_save_pci_state(struct tg3 *tp) | |
6362 | { | |
8a6eac90 | 6363 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
6364 | } |
6365 | ||
6366 | /* Restore PCI state after chip reset */ | |
6367 | static void tg3_restore_pci_state(struct tg3 *tp) | |
6368 | { | |
6369 | u32 val; | |
6370 | ||
6371 | /* Re-enable indirect register accesses. */ | |
6372 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
6373 | tp->misc_host_ctrl); | |
6374 | ||
6375 | /* Set MAX PCI retry to zero. */ | |
6376 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
6377 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
6378 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) | |
6379 | val |= PCISTATE_RETRY_SAME_DMA; | |
0d3031d9 MC |
6380 | /* Allow reads and writes to the APE register and memory space. */ |
6381 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
6382 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
6383 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
ee6a99b5 MC |
6384 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
6385 | ||
8a6eac90 | 6386 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 6387 | |
fcb389df MC |
6388 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
6389 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
6390 | pcie_set_readrq(tp->pdev, 4096); | |
6391 | else { | |
6392 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
6393 | tp->pci_cacheline_sz); | |
6394 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
6395 | tp->pci_lat_timer); | |
6396 | } | |
114342f2 | 6397 | } |
5f5c51e3 | 6398 | |
ee6a99b5 | 6399 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
52f4490c | 6400 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
9974a356 MC |
6401 | u16 pcix_cmd; |
6402 | ||
6403 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6404 | &pcix_cmd); | |
6405 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
6406 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6407 | pcix_cmd); | |
6408 | } | |
ee6a99b5 MC |
6409 | |
6410 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
ee6a99b5 MC |
6411 | |
6412 | /* Chip reset on 5780 will reset MSI enable bit, | |
6413 | * so need to restore it. | |
6414 | */ | |
6415 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
6416 | u16 ctrl; | |
6417 | ||
6418 | pci_read_config_word(tp->pdev, | |
6419 | tp->msi_cap + PCI_MSI_FLAGS, | |
6420 | &ctrl); | |
6421 | pci_write_config_word(tp->pdev, | |
6422 | tp->msi_cap + PCI_MSI_FLAGS, | |
6423 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
6424 | val = tr32(MSGINT_MODE); | |
6425 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
6426 | } | |
6427 | } | |
6428 | } | |
6429 | ||
1da177e4 LT |
6430 | static void tg3_stop_fw(struct tg3 *); |
6431 | ||
6432 | /* tp->lock is held. */ | |
6433 | static int tg3_chip_reset(struct tg3 *tp) | |
6434 | { | |
6435 | u32 val; | |
1ee582d8 | 6436 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 6437 | int i, err; |
1da177e4 | 6438 | |
f49639e6 DM |
6439 | tg3_nvram_lock(tp); |
6440 | ||
77b483f1 MC |
6441 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
6442 | ||
f49639e6 DM |
6443 | /* No matching tg3_nvram_unlock() after this because |
6444 | * chip reset below will undo the nvram lock. | |
6445 | */ | |
6446 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 6447 | |
ee6a99b5 MC |
6448 | /* GRC_MISC_CFG core clock reset will clear the memory |
6449 | * enable bit in PCI register 4 and the MSI enable bit | |
6450 | * on some chips, so we save relevant registers here. | |
6451 | */ | |
6452 | tg3_save_pci_state(tp); | |
6453 | ||
d9ab5ad1 | 6454 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
321d32a0 | 6455 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) |
d9ab5ad1 MC |
6456 | tw32(GRC_FASTBOOT_PC, 0); |
6457 | ||
1da177e4 LT |
6458 | /* |
6459 | * We must avoid the readl() that normally takes place. | |
6460 | * It locks machines, causes machine checks, and other | |
6461 | * fun things. So, temporarily disable the 5701 | |
6462 | * hardware workaround, while we do the reset. | |
6463 | */ | |
1ee582d8 MC |
6464 | write_op = tp->write32; |
6465 | if (write_op == tg3_write_flush_reg32) | |
6466 | tp->write32 = tg3_write32; | |
1da177e4 | 6467 | |
d18edcb2 MC |
6468 | /* Prevent the irq handler from reading or writing PCI registers |
6469 | * during chip reset when the memory enable bit in the PCI command | |
6470 | * register may be cleared. The chip does not generate interrupt | |
6471 | * at this time, but the irq handler may still be called due to irq | |
6472 | * sharing or irqpoll. | |
6473 | */ | |
6474 | tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; | |
f77a6a8e MC |
6475 | for (i = 0; i < tp->irq_cnt; i++) { |
6476 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6477 | if (tnapi->hw_status) { | |
6478 | tnapi->hw_status->status = 0; | |
6479 | tnapi->hw_status->status_tag = 0; | |
6480 | } | |
6481 | tnapi->last_tag = 0; | |
6482 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 6483 | } |
d18edcb2 | 6484 | smp_mb(); |
4f125f42 MC |
6485 | |
6486 | for (i = 0; i < tp->irq_cnt; i++) | |
6487 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 6488 | |
255ca311 MC |
6489 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
6490 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
6491 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
6492 | } | |
6493 | ||
1da177e4 LT |
6494 | /* do the reset */ |
6495 | val = GRC_MISC_CFG_CORECLK_RESET; | |
6496 | ||
6497 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
6498 | if (tr32(0x7e2c) == 0x60) { | |
6499 | tw32(0x7e2c, 0x20); | |
6500 | } | |
6501 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { | |
6502 | tw32(GRC_MISC_CFG, (1 << 29)); | |
6503 | val |= (1 << 29); | |
6504 | } | |
6505 | } | |
6506 | ||
b5d3772c MC |
6507 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
6508 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
6509 | tw32(GRC_VCPU_EXT_CTRL, | |
6510 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
6511 | } | |
6512 | ||
1da177e4 LT |
6513 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
6514 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; | |
6515 | tw32(GRC_MISC_CFG, val); | |
6516 | ||
1ee582d8 MC |
6517 | /* restore 5701 hardware bug workaround write method */ |
6518 | tp->write32 = write_op; | |
1da177e4 LT |
6519 | |
6520 | /* Unfortunately, we have to delay before the PCI read back. | |
6521 | * Some 575X chips even will not respond to a PCI cfg access | |
6522 | * when the reset command is given to the chip. | |
6523 | * | |
6524 | * How do these hardware designers expect things to work | |
6525 | * properly if the PCI write is posted for a long period | |
6526 | * of time? It is always necessary to have some method by | |
6527 | * which a register read back can occur to push the write | |
6528 | * out which does the reset. | |
6529 | * | |
6530 | * For most tg3 variants the trick below was working. | |
6531 | * Ho hum... | |
6532 | */ | |
6533 | udelay(120); | |
6534 | ||
6535 | /* Flush PCI posted writes. The normal MMIO registers | |
6536 | * are inaccessible at this time so this is the only | |
6537 | * way to make this reliably (actually, this is no longer | |
6538 | * the case, see above). I tried to use indirect | |
6539 | * register read/write but this upset some 5701 variants. | |
6540 | */ | |
6541 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
6542 | ||
6543 | udelay(120); | |
6544 | ||
5e7dfd0f | 6545 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { |
e7126997 MC |
6546 | u16 val16; |
6547 | ||
1da177e4 LT |
6548 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
6549 | int i; | |
6550 | u32 cfg_val; | |
6551 | ||
6552 | /* Wait for link training to complete. */ | |
6553 | for (i = 0; i < 5000; i++) | |
6554 | udelay(100); | |
6555 | ||
6556 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
6557 | pci_write_config_dword(tp->pdev, 0xc4, | |
6558 | cfg_val | (1 << 15)); | |
6559 | } | |
5e7dfd0f | 6560 | |
e7126997 MC |
6561 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
6562 | pci_read_config_word(tp->pdev, | |
6563 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
6564 | &val16); | |
6565 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
6566 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
6567 | /* | |
6568 | * Older PCIe devices only support the 128 byte | |
6569 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 6570 | */ |
e7126997 MC |
6571 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
6572 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)) | |
6573 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; | |
5e7dfd0f MC |
6574 | pci_write_config_word(tp->pdev, |
6575 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
e7126997 | 6576 | val16); |
5e7dfd0f MC |
6577 | |
6578 | pcie_set_readrq(tp->pdev, 4096); | |
6579 | ||
6580 | /* Clear error status */ | |
6581 | pci_write_config_word(tp->pdev, | |
6582 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
6583 | PCI_EXP_DEVSTA_CED | | |
6584 | PCI_EXP_DEVSTA_NFED | | |
6585 | PCI_EXP_DEVSTA_FED | | |
6586 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
6587 | } |
6588 | ||
ee6a99b5 | 6589 | tg3_restore_pci_state(tp); |
1da177e4 | 6590 | |
d18edcb2 MC |
6591 | tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING; |
6592 | ||
ee6a99b5 MC |
6593 | val = 0; |
6594 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
4cf78e4f | 6595 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 6596 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
6597 | |
6598 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
6599 | tg3_stop_fw(tp); | |
6600 | tw32(0x5000, 0x400); | |
6601 | } | |
6602 | ||
6603 | tw32(GRC_MODE, tp->grc_mode); | |
6604 | ||
6605 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 6606 | val = tr32(0xc4); |
1da177e4 LT |
6607 | |
6608 | tw32(0xc4, val | (1 << 15)); | |
6609 | } | |
6610 | ||
6611 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
6612 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
6613 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
6614 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
6615 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
6616 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
6617 | } | |
6618 | ||
6619 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
6620 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; | |
6621 | tw32_f(MAC_MODE, tp->mac_mode); | |
747e8f8b MC |
6622 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { |
6623 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; | |
6624 | tw32_f(MAC_MODE, tp->mac_mode); | |
3bda1258 MC |
6625 | } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
6626 | tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
6627 | if (tp->mac_mode & MAC_MODE_APE_TX_EN) | |
6628 | tp->mac_mode |= MAC_MODE_TDE_ENABLE; | |
6629 | tw32_f(MAC_MODE, tp->mac_mode); | |
1da177e4 LT |
6630 | } else |
6631 | tw32_f(MAC_MODE, 0); | |
6632 | udelay(40); | |
6633 | ||
77b483f1 MC |
6634 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
6635 | ||
7a6f4369 MC |
6636 | err = tg3_poll_fw(tp); |
6637 | if (err) | |
6638 | return err; | |
1da177e4 | 6639 | |
0a9140cf MC |
6640 | tg3_mdio_start(tp); |
6641 | ||
52cdf852 MC |
6642 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
6643 | u8 phy_addr; | |
6644 | ||
6645 | phy_addr = tp->phy_addr; | |
6646 | tp->phy_addr = TG3_PHY_PCIE_ADDR; | |
6647 | ||
6648 | tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR, | |
6649 | TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT); | |
6650 | val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL | | |
6651 | TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL | | |
6652 | TG3_PCIEPHY_TX0CTRL1_NB_EN; | |
6653 | tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val); | |
6654 | udelay(10); | |
6655 | ||
6656 | tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR, | |
6657 | TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT); | |
6658 | val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN | | |
6659 | TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN; | |
6660 | tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val); | |
6661 | udelay(10); | |
6662 | ||
6663 | tp->phy_addr = phy_addr; | |
6664 | } | |
6665 | ||
1da177e4 | 6666 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
f6eb9b1f MC |
6667 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
6668 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
6669 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) { | |
ab0049b4 | 6670 | val = tr32(0x7c00); |
1da177e4 LT |
6671 | |
6672 | tw32(0x7c00, val | (1 << 25)); | |
6673 | } | |
6674 | ||
6675 | /* Reprobe ASF enable state. */ | |
6676 | tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; | |
6677 | tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; | |
6678 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
6679 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
6680 | u32 nic_cfg; | |
6681 | ||
6682 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
6683 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
6684 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
4ba526ce | 6685 | tp->last_event_jiffies = jiffies; |
cbf46853 | 6686 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
6687 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
6688 | } | |
6689 | } | |
6690 | ||
6691 | return 0; | |
6692 | } | |
6693 | ||
6694 | /* tp->lock is held. */ | |
6695 | static void tg3_stop_fw(struct tg3 *tp) | |
6696 | { | |
0d3031d9 MC |
6697 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
6698 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
6699 | /* Wait for RX cpu to ACK the previous event. */ |
6700 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
6701 | |
6702 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
6703 | |
6704 | tg3_generate_fw_event(tp); | |
1da177e4 | 6705 | |
7c5026aa MC |
6706 | /* Wait for RX cpu to ACK this event. */ |
6707 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
6708 | } |
6709 | } | |
6710 | ||
6711 | /* tp->lock is held. */ | |
944d980e | 6712 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
6713 | { |
6714 | int err; | |
6715 | ||
6716 | tg3_stop_fw(tp); | |
6717 | ||
944d980e | 6718 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 6719 | |
b3b7d6be | 6720 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
6721 | err = tg3_chip_reset(tp); |
6722 | ||
daba2a63 MC |
6723 | __tg3_set_mac_addr(tp, 0); |
6724 | ||
944d980e MC |
6725 | tg3_write_sig_legacy(tp, kind); |
6726 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
6727 | |
6728 | if (err) | |
6729 | return err; | |
6730 | ||
6731 | return 0; | |
6732 | } | |
6733 | ||
1da177e4 LT |
6734 | #define RX_CPU_SCRATCH_BASE 0x30000 |
6735 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
6736 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
6737 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
6738 | ||
6739 | /* tp->lock is held. */ | |
6740 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
6741 | { | |
6742 | int i; | |
6743 | ||
5d9428de ES |
6744 | BUG_ON(offset == TX_CPU_BASE && |
6745 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)); | |
1da177e4 | 6746 | |
b5d3772c MC |
6747 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
6748 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
6749 | ||
6750 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
6751 | return 0; | |
6752 | } | |
1da177e4 LT |
6753 | if (offset == RX_CPU_BASE) { |
6754 | for (i = 0; i < 10000; i++) { | |
6755 | tw32(offset + CPU_STATE, 0xffffffff); | |
6756 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
6757 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
6758 | break; | |
6759 | } | |
6760 | ||
6761 | tw32(offset + CPU_STATE, 0xffffffff); | |
6762 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
6763 | udelay(10); | |
6764 | } else { | |
6765 | for (i = 0; i < 10000; i++) { | |
6766 | tw32(offset + CPU_STATE, 0xffffffff); | |
6767 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
6768 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
6769 | break; | |
6770 | } | |
6771 | } | |
6772 | ||
6773 | if (i >= 10000) { | |
6774 | printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, " | |
6775 | "and %s CPU\n", | |
6776 | tp->dev->name, | |
6777 | (offset == RX_CPU_BASE ? "RX" : "TX")); | |
6778 | return -ENODEV; | |
6779 | } | |
ec41c7df MC |
6780 | |
6781 | /* Clear firmware's nvram arbitration. */ | |
6782 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
6783 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
1da177e4 LT |
6784 | return 0; |
6785 | } | |
6786 | ||
6787 | struct fw_info { | |
077f849d JSR |
6788 | unsigned int fw_base; |
6789 | unsigned int fw_len; | |
6790 | const __be32 *fw_data; | |
1da177e4 LT |
6791 | }; |
6792 | ||
6793 | /* tp->lock is held. */ | |
6794 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
6795 | int cpu_scratch_size, struct fw_info *info) | |
6796 | { | |
ec41c7df | 6797 | int err, lock_err, i; |
1da177e4 LT |
6798 | void (*write_op)(struct tg3 *, u32, u32); |
6799 | ||
6800 | if (cpu_base == TX_CPU_BASE && | |
6801 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
6802 | printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load " | |
6803 | "TX cpu firmware on %s which is 5705.\n", | |
6804 | tp->dev->name); | |
6805 | return -EINVAL; | |
6806 | } | |
6807 | ||
6808 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
6809 | write_op = tg3_write_mem; | |
6810 | else | |
6811 | write_op = tg3_write_indirect_reg32; | |
6812 | ||
1b628151 MC |
6813 | /* It is possible that bootcode is still loading at this point. |
6814 | * Get the nvram lock first before halting the cpu. | |
6815 | */ | |
ec41c7df | 6816 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 6817 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
6818 | if (!lock_err) |
6819 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
6820 | if (err) |
6821 | goto out; | |
6822 | ||
6823 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
6824 | write_op(tp, cpu_scratch_base + i, 0); | |
6825 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6826 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 6827 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 6828 | write_op(tp, (cpu_scratch_base + |
077f849d | 6829 | (info->fw_base & 0xffff) + |
1da177e4 | 6830 | (i * sizeof(u32))), |
077f849d | 6831 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
6832 | |
6833 | err = 0; | |
6834 | ||
6835 | out: | |
1da177e4 LT |
6836 | return err; |
6837 | } | |
6838 | ||
6839 | /* tp->lock is held. */ | |
6840 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
6841 | { | |
6842 | struct fw_info info; | |
077f849d | 6843 | const __be32 *fw_data; |
1da177e4 LT |
6844 | int err, i; |
6845 | ||
077f849d JSR |
6846 | fw_data = (void *)tp->fw->data; |
6847 | ||
6848 | /* Firmware blob starts with version numbers, followed by | |
6849 | start address and length. We are setting complete length. | |
6850 | length = end_address_of_bss - start_address_of_text. | |
6851 | Remainder is the blob to be loaded contiguously | |
6852 | from start address. */ | |
6853 | ||
6854 | info.fw_base = be32_to_cpu(fw_data[1]); | |
6855 | info.fw_len = tp->fw->size - 12; | |
6856 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
6857 | |
6858 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
6859 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
6860 | &info); | |
6861 | if (err) | |
6862 | return err; | |
6863 | ||
6864 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
6865 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
6866 | &info); | |
6867 | if (err) | |
6868 | return err; | |
6869 | ||
6870 | /* Now startup only the RX cpu. */ | |
6871 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 6872 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
6873 | |
6874 | for (i = 0; i < 5; i++) { | |
077f849d | 6875 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
6876 | break; |
6877 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
6878 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 6879 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
6880 | udelay(1000); |
6881 | } | |
6882 | if (i >= 5) { | |
6883 | printk(KERN_ERR PFX "tg3_load_firmware fails for %s " | |
6884 | "to set RX CPU PC, is %08x should be %08x\n", | |
6885 | tp->dev->name, tr32(RX_CPU_BASE + CPU_PC), | |
077f849d | 6886 | info.fw_base); |
1da177e4 LT |
6887 | return -ENODEV; |
6888 | } | |
6889 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
6890 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
6891 | ||
6892 | return 0; | |
6893 | } | |
6894 | ||
1da177e4 | 6895 | /* 5705 needs a special version of the TSO firmware. */ |
1da177e4 LT |
6896 | |
6897 | /* tp->lock is held. */ | |
6898 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
6899 | { | |
6900 | struct fw_info info; | |
077f849d | 6901 | const __be32 *fw_data; |
1da177e4 LT |
6902 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
6903 | int err, i; | |
6904 | ||
6905 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
6906 | return 0; | |
6907 | ||
077f849d JSR |
6908 | fw_data = (void *)tp->fw->data; |
6909 | ||
6910 | /* Firmware blob starts with version numbers, followed by | |
6911 | start address and length. We are setting complete length. | |
6912 | length = end_address_of_bss - start_address_of_text. | |
6913 | Remainder is the blob to be loaded contiguously | |
6914 | from start address. */ | |
6915 | ||
6916 | info.fw_base = be32_to_cpu(fw_data[1]); | |
6917 | cpu_scratch_size = tp->fw_len; | |
6918 | info.fw_len = tp->fw->size - 12; | |
6919 | info.fw_data = &fw_data[3]; | |
6920 | ||
1da177e4 | 6921 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
6922 | cpu_base = RX_CPU_BASE; |
6923 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 6924 | } else { |
1da177e4 LT |
6925 | cpu_base = TX_CPU_BASE; |
6926 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
6927 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
6928 | } | |
6929 | ||
6930 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
6931 | cpu_scratch_base, cpu_scratch_size, | |
6932 | &info); | |
6933 | if (err) | |
6934 | return err; | |
6935 | ||
6936 | /* Now startup the cpu. */ | |
6937 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 6938 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
6939 | |
6940 | for (i = 0; i < 5; i++) { | |
077f849d | 6941 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
6942 | break; |
6943 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6944 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 6945 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
6946 | udelay(1000); |
6947 | } | |
6948 | if (i >= 5) { | |
6949 | printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s " | |
6950 | "to set CPU PC, is %08x should be %08x\n", | |
6951 | tp->dev->name, tr32(cpu_base + CPU_PC), | |
077f849d | 6952 | info.fw_base); |
1da177e4 LT |
6953 | return -ENODEV; |
6954 | } | |
6955 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
6956 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
6957 | return 0; | |
6958 | } | |
6959 | ||
1da177e4 | 6960 | |
1da177e4 LT |
6961 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
6962 | { | |
6963 | struct tg3 *tp = netdev_priv(dev); | |
6964 | struct sockaddr *addr = p; | |
986e0aeb | 6965 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 6966 | |
f9804ddb MC |
6967 | if (!is_valid_ether_addr(addr->sa_data)) |
6968 | return -EINVAL; | |
6969 | ||
1da177e4 LT |
6970 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
6971 | ||
e75f7c90 MC |
6972 | if (!netif_running(dev)) |
6973 | return 0; | |
6974 | ||
58712ef9 | 6975 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { |
986e0aeb | 6976 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 6977 | |
986e0aeb MC |
6978 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
6979 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
6980 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
6981 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
6982 | ||
6983 | /* Skip MAC addr 1 if ASF is using it. */ | |
6984 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
6985 | !(addr1_high == 0 && addr1_low == 0)) | |
6986 | skip_mac_1 = 1; | |
58712ef9 | 6987 | } |
986e0aeb MC |
6988 | spin_lock_bh(&tp->lock); |
6989 | __tg3_set_mac_addr(tp, skip_mac_1); | |
6990 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 6991 | |
b9ec6c1b | 6992 | return err; |
1da177e4 LT |
6993 | } |
6994 | ||
6995 | /* tp->lock is held. */ | |
6996 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
6997 | dma_addr_t mapping, u32 maxlen_flags, | |
6998 | u32 nic_addr) | |
6999 | { | |
7000 | tg3_write_mem(tp, | |
7001 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7002 | ((u64) mapping >> 32)); | |
7003 | tg3_write_mem(tp, | |
7004 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7005 | ((u64) mapping & 0xffffffff)); | |
7006 | tg3_write_mem(tp, | |
7007 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7008 | maxlen_flags); | |
7009 | ||
7010 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7011 | tg3_write_mem(tp, | |
7012 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7013 | nic_addr); | |
7014 | } | |
7015 | ||
7016 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7017 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7018 | { |
b6080e12 MC |
7019 | int i; |
7020 | ||
7021 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { | |
7022 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); | |
7023 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7024 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
7025 | ||
7026 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); | |
7027 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7028 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7029 | } else { | |
7030 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7031 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7032 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
7033 | ||
7034 | tw32(HOSTCC_RXCOL_TICKS, 0); | |
7035 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7036 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7037 | } |
b6080e12 | 7038 | |
15f9850d DM |
7039 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
7040 | u32 val = ec->stats_block_coalesce_usecs; | |
7041 | ||
b6080e12 MC |
7042 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7043 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7044 | ||
15f9850d DM |
7045 | if (!netif_carrier_ok(tp->dev)) |
7046 | val = 0; | |
7047 | ||
7048 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7049 | } | |
b6080e12 MC |
7050 | |
7051 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7052 | u32 reg; | |
7053 | ||
7054 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7055 | tw32(reg, ec->rx_coalesce_usecs); | |
7056 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
7057 | tw32(reg, ec->tx_coalesce_usecs); | |
7058 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; | |
7059 | tw32(reg, ec->rx_max_coalesced_frames); | |
7060 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7061 | tw32(reg, ec->tx_max_coalesced_frames); | |
7062 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7063 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
7064 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7065 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7066 | } | |
7067 | ||
7068 | for (; i < tp->irq_max - 1; i++) { | |
7069 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7070 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7071 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7072 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7073 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7074 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7075 | } | |
15f9850d | 7076 | } |
1da177e4 | 7077 | |
2d31ecaf MC |
7078 | /* tp->lock is held. */ |
7079 | static void tg3_rings_reset(struct tg3 *tp) | |
7080 | { | |
7081 | int i; | |
f77a6a8e | 7082 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
7083 | struct tg3_napi *tnapi = &tp->napi[0]; |
7084 | ||
7085 | /* Disable all transmit rings but the first. */ | |
7086 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7087 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; | |
7088 | else | |
7089 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7090 | ||
7091 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7092 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7093 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7094 | BDINFO_FLAGS_DISABLED); | |
7095 | ||
7096 | ||
7097 | /* Disable all receive return rings but the first. */ | |
f6eb9b1f MC |
7098 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
7099 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; | |
7100 | else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
2d31ecaf MC |
7101 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
7102 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
7103 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; | |
7104 | else | |
7105 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7106 | ||
7107 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7108 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7109 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7110 | BDINFO_FLAGS_DISABLED); | |
7111 | ||
7112 | /* Disable interrupts */ | |
7113 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
7114 | ||
7115 | /* Zero mailbox registers. */ | |
f77a6a8e MC |
7116 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) { |
7117 | for (i = 1; i < TG3_IRQ_MAX_VECS; i++) { | |
7118 | tp->napi[i].tx_prod = 0; | |
7119 | tp->napi[i].tx_cons = 0; | |
7120 | tw32_mailbox(tp->napi[i].prodmbox, 0); | |
7121 | tw32_rx_mbox(tp->napi[i].consmbox, 0); | |
7122 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7123 | } | |
7124 | } else { | |
7125 | tp->napi[0].tx_prod = 0; | |
7126 | tp->napi[0].tx_cons = 0; | |
7127 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7128 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7129 | } | |
2d31ecaf MC |
7130 | |
7131 | /* Make sure the NIC-based send BD rings are disabled. */ | |
7132 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7133 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
7134 | for (i = 0; i < 16; i++) | |
7135 | tw32_tx_mbox(mbox + i * 8, 0); | |
7136 | } | |
7137 | ||
7138 | txrcb = NIC_SRAM_SEND_RCB; | |
7139 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7140 | ||
7141 | /* Clear status block in ram. */ | |
7142 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7143 | ||
7144 | /* Set status block DMA address */ | |
7145 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7146 | ((u64) tnapi->status_mapping >> 32)); | |
7147 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7148 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7149 | ||
f77a6a8e MC |
7150 | if (tnapi->tx_ring) { |
7151 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7152 | (TG3_TX_RING_SIZE << | |
7153 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7154 | NIC_SRAM_TX_BUFFER_DESC); | |
7155 | txrcb += TG3_BDINFO_SIZE; | |
7156 | } | |
7157 | ||
7158 | if (tnapi->rx_rcb) { | |
7159 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7160 | (TG3_RX_RCB_RING_SIZE(tp) << | |
7161 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); | |
7162 | rxrcb += TG3_BDINFO_SIZE; | |
7163 | } | |
7164 | ||
7165 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 7166 | |
f77a6a8e MC |
7167 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
7168 | u64 mapping = (u64)tnapi->status_mapping; | |
7169 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7170 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7171 | ||
7172 | /* Clear status block in ram. */ | |
7173 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7174 | ||
7175 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7176 | (TG3_TX_RING_SIZE << | |
7177 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7178 | NIC_SRAM_TX_BUFFER_DESC); | |
7179 | ||
7180 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7181 | (TG3_RX_RCB_RING_SIZE(tp) << | |
7182 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); | |
7183 | ||
7184 | stblk += 8; | |
7185 | txrcb += TG3_BDINFO_SIZE; | |
7186 | rxrcb += TG3_BDINFO_SIZE; | |
7187 | } | |
2d31ecaf MC |
7188 | } |
7189 | ||
1da177e4 | 7190 | /* tp->lock is held. */ |
8e7a22e3 | 7191 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
7192 | { |
7193 | u32 val, rdmac_mode; | |
7194 | int i, err, limit; | |
21f581a5 | 7195 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
1da177e4 LT |
7196 | |
7197 | tg3_disable_ints(tp); | |
7198 | ||
7199 | tg3_stop_fw(tp); | |
7200 | ||
7201 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
7202 | ||
7203 | if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) { | |
e6de8ad1 | 7204 | tg3_abort_hw(tp, 1); |
1da177e4 LT |
7205 | } |
7206 | ||
dd477003 MC |
7207 | if (reset_phy && |
7208 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) | |
d4d2c558 MC |
7209 | tg3_phy_reset(tp); |
7210 | ||
1da177e4 LT |
7211 | err = tg3_chip_reset(tp); |
7212 | if (err) | |
7213 | return err; | |
7214 | ||
7215 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
7216 | ||
bcb37f6c | 7217 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
7218 | val = tr32(TG3_CPMU_CTRL); |
7219 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
7220 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
7221 | |
7222 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
7223 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
7224 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
7225 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
7226 | ||
7227 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
7228 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
7229 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
7230 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
7231 | ||
7232 | val = tr32(TG3_CPMU_HST_ACC); | |
7233 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
7234 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
7235 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
7236 | } |
7237 | ||
33466d93 MC |
7238 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7239 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
7240 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
7241 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
7242 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
7243 | |
7244 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
7245 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
7246 | ||
7247 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 7248 | |
f40386c8 MC |
7249 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
7250 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
7251 | } |
7252 | ||
1da177e4 LT |
7253 | /* This works around an issue with Athlon chipsets on |
7254 | * B3 tigon3 silicon. This bit has no effect on any | |
7255 | * other revision. But do not set this on PCI Express | |
795d01c5 | 7256 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 7257 | */ |
795d01c5 MC |
7258 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { |
7259 | if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
7260 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
7261 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7262 | } | |
1da177e4 LT |
7263 | |
7264 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
7265 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
7266 | val = tr32(TG3PCI_PCISTATE); | |
7267 | val |= PCISTATE_RETRY_SAME_DMA; | |
7268 | tw32(TG3PCI_PCISTATE, val); | |
7269 | } | |
7270 | ||
0d3031d9 MC |
7271 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
7272 | /* Allow reads and writes to the | |
7273 | * APE register and memory space. | |
7274 | */ | |
7275 | val = tr32(TG3PCI_PCISTATE); | |
7276 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
7277 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
7278 | tw32(TG3PCI_PCISTATE, val); | |
7279 | } | |
7280 | ||
1da177e4 LT |
7281 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
7282 | /* Enable some hw fixes. */ | |
7283 | val = tr32(TG3PCI_MSI_DATA); | |
7284 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
7285 | tw32(TG3PCI_MSI_DATA, val); | |
7286 | } | |
7287 | ||
7288 | /* Descriptor ring init may make accesses to the | |
7289 | * NIC SRAM area to setup the TX descriptors, so we | |
7290 | * can only do this after the hardware has been | |
7291 | * successfully reset. | |
7292 | */ | |
32d8c572 MC |
7293 | err = tg3_init_rings(tp); |
7294 | if (err) | |
7295 | return err; | |
1da177e4 | 7296 | |
9936bcf6 | 7297 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && |
f6eb9b1f MC |
7298 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 && |
7299 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) { | |
d30cdd28 MC |
7300 | /* This value is determined during the probe time DMA |
7301 | * engine test, tg3_test_dma. | |
7302 | */ | |
7303 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
7304 | } | |
1da177e4 LT |
7305 | |
7306 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
7307 | GRC_MODE_4X_NIC_SEND_RINGS | | |
7308 | GRC_MODE_NO_TX_PHDR_CSUM | | |
7309 | GRC_MODE_NO_RX_PHDR_CSUM); | |
7310 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
7311 | |
7312 | /* Pseudo-header checksum is done by hardware logic and not | |
7313 | * the offload processers, so make the chip do the pseudo- | |
7314 | * header checksums on receive. For transmit it is more | |
7315 | * convenient to do the pseudo-header checksum in software | |
7316 | * as Linux does that on transmit for us in all cases. | |
7317 | */ | |
7318 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
7319 | |
7320 | tw32(GRC_MODE, | |
7321 | tp->grc_mode | | |
7322 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
7323 | ||
7324 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
7325 | val = tr32(GRC_MISC_CFG); | |
7326 | val &= ~0xff; | |
7327 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
7328 | tw32(GRC_MISC_CFG, val); | |
7329 | ||
7330 | /* Initialize MBUF/DESC pool. */ | |
cbf46853 | 7331 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
1da177e4 LT |
7332 | /* Do nothing. */ |
7333 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
7334 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
7335 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
7336 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
7337 | else | |
7338 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
7339 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
7340 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
7341 | } | |
1da177e4 LT |
7342 | else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
7343 | int fw_len; | |
7344 | ||
077f849d | 7345 | fw_len = tp->fw_len; |
1da177e4 LT |
7346 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
7347 | tw32(BUFMGR_MB_POOL_ADDR, | |
7348 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
7349 | tw32(BUFMGR_MB_POOL_SIZE, | |
7350 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
7351 | } | |
1da177e4 | 7352 | |
0f893dc6 | 7353 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
7354 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
7355 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
7356 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
7357 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
7358 | tw32(BUFMGR_MB_HIGH_WATER, | |
7359 | tp->bufmgr_config.mbuf_high_water); | |
7360 | } else { | |
7361 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
7362 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
7363 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
7364 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
7365 | tw32(BUFMGR_MB_HIGH_WATER, | |
7366 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
7367 | } | |
7368 | tw32(BUFMGR_DMA_LOW_WATER, | |
7369 | tp->bufmgr_config.dma_low_water); | |
7370 | tw32(BUFMGR_DMA_HIGH_WATER, | |
7371 | tp->bufmgr_config.dma_high_water); | |
7372 | ||
7373 | tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); | |
7374 | for (i = 0; i < 2000; i++) { | |
7375 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
7376 | break; | |
7377 | udelay(10); | |
7378 | } | |
7379 | if (i >= 2000) { | |
7380 | printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n", | |
7381 | tp->dev->name); | |
7382 | return -ENODEV; | |
7383 | } | |
7384 | ||
7385 | /* Setup replenish threshold. */ | |
f92905de MC |
7386 | val = tp->rx_pending / 8; |
7387 | if (val == 0) | |
7388 | val = 1; | |
7389 | else if (val > tp->rx_std_max_post) | |
7390 | val = tp->rx_std_max_post; | |
b5d3772c MC |
7391 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7392 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) | |
7393 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
7394 | ||
7395 | if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2)) | |
7396 | val = TG3_RX_INTERNAL_RING_SZ_5906 / 2; | |
7397 | } | |
f92905de MC |
7398 | |
7399 | tw32(RCVBDI_STD_THRESH, val); | |
1da177e4 LT |
7400 | |
7401 | /* Initialize TG3_BDINFO's at: | |
7402 | * RCVDBDI_STD_BD: standard eth size rx ring | |
7403 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
7404 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
7405 | * | |
7406 | * like so: | |
7407 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
7408 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
7409 | * ring attribute flags | |
7410 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
7411 | * | |
7412 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
7413 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
7414 | * | |
7415 | * The size of each ring is fixed in the firmware, but the location is | |
7416 | * configurable. | |
7417 | */ | |
7418 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 7419 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 7420 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 7421 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
87668d35 MC |
7422 | if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) |
7423 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, | |
7424 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 7425 | |
fdb72b38 MC |
7426 | /* Disable the mini ring */ |
7427 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
1da177e4 LT |
7428 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
7429 | BDINFO_FLAGS_DISABLED); | |
7430 | ||
fdb72b38 MC |
7431 | /* Program the jumbo buffer descriptor ring control |
7432 | * blocks on those devices that have them. | |
7433 | */ | |
8f666b07 | 7434 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
fdb72b38 | 7435 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
7436 | /* Setup replenish threshold. */ |
7437 | tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); | |
7438 | ||
0f893dc6 | 7439 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { |
1da177e4 | 7440 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 7441 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 7442 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 7443 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
1da177e4 | 7444 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
79ed5ac7 MC |
7445 | (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) | |
7446 | BDINFO_FLAGS_USE_EXT_RECV); | |
87668d35 MC |
7447 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
7448 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, | |
7449 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
7450 | } else { |
7451 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
7452 | BDINFO_FLAGS_DISABLED); | |
7453 | } | |
7454 | ||
f6eb9b1f MC |
7455 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
7456 | val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) | | |
7457 | (RX_STD_MAX_SIZE << 2); | |
7458 | else | |
7459 | val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT; | |
fdb72b38 MC |
7460 | } else |
7461 | val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT; | |
7462 | ||
7463 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 7464 | |
21f581a5 | 7465 | tpr->rx_std_ptr = tp->rx_pending; |
1da177e4 | 7466 | tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, |
21f581a5 | 7467 | tpr->rx_std_ptr); |
1da177e4 | 7468 | |
21f581a5 MC |
7469 | tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? |
7470 | tp->rx_jumbo_pending : 0; | |
1da177e4 | 7471 | tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, |
21f581a5 | 7472 | tpr->rx_jmb_ptr); |
1da177e4 | 7473 | |
f6eb9b1f MC |
7474 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
7475 | tw32(STD_REPLENISH_LWM, 32); | |
7476 | tw32(JMB_REPLENISH_LWM, 16); | |
7477 | } | |
7478 | ||
2d31ecaf MC |
7479 | tg3_rings_reset(tp); |
7480 | ||
1da177e4 | 7481 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 7482 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
7483 | |
7484 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
7485 | tw32(MAC_RX_MTU_SIZE, |
7486 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
7487 | |
7488 | /* The slot time is changed by tg3_setup_phy if we | |
7489 | * run at gigabit with half duplex. | |
7490 | */ | |
7491 | tw32(MAC_TX_LENGTHS, | |
7492 | (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
7493 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
7494 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
7495 | ||
7496 | /* Receive rules. */ | |
7497 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
7498 | tw32(RCVLPC_CONFIG, 0x0181); | |
7499 | ||
7500 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
7501 | * the RCVLPC_STATE_ENABLE mask. | |
7502 | */ | |
7503 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
7504 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
7505 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
7506 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
7507 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 7508 | |
57e6983c | 7509 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
7510 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
7511 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
7512 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
7513 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
7514 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
7515 | ||
85e94ced MC |
7516 | /* If statement applies to 5705 and 5750 PCI devices only */ |
7517 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
7518 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
7519 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { | |
1da177e4 | 7520 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && |
c13e3713 | 7521 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7522 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
7523 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
7524 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { | |
7525 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
7526 | } | |
7527 | } | |
7528 | ||
85e94ced MC |
7529 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) |
7530 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
7531 | ||
1da177e4 | 7532 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
027455ad MC |
7533 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
7534 | ||
e849cdc3 MC |
7535 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
7536 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
027455ad MC |
7537 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
7538 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 LT |
7539 | |
7540 | /* Receive/send statistics. */ | |
1661394e MC |
7541 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7542 | val = tr32(RCVLPC_STATS_ENABLE); | |
7543 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
7544 | tw32(RCVLPC_STATS_ENABLE, val); | |
7545 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
7546 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
1da177e4 LT |
7547 | val = tr32(RCVLPC_STATS_ENABLE); |
7548 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
7549 | tw32(RCVLPC_STATS_ENABLE, val); | |
7550 | } else { | |
7551 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
7552 | } | |
7553 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
7554 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
7555 | tw32(SNDDATAI_STATSCTRL, | |
7556 | (SNDDATAI_SCTRL_ENABLE | | |
7557 | SNDDATAI_SCTRL_FASTUPD)); | |
7558 | ||
7559 | /* Setup host coalescing engine. */ | |
7560 | tw32(HOSTCC_MODE, 0); | |
7561 | for (i = 0; i < 2000; i++) { | |
7562 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
7563 | break; | |
7564 | udelay(10); | |
7565 | } | |
7566 | ||
d244c892 | 7567 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 7568 | |
1da177e4 LT |
7569 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
7570 | /* Status/statistics block address. See tg3_timer, | |
7571 | * the tg3_periodic_fetch_stats call there, and | |
7572 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
7573 | */ | |
1da177e4 LT |
7574 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
7575 | ((u64) tp->stats_mapping >> 32)); | |
7576 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7577 | ((u64) tp->stats_mapping & 0xffffffff)); | |
7578 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 7579 | |
1da177e4 | 7580 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
7581 | |
7582 | /* Clear statistics and status block memory areas */ | |
7583 | for (i = NIC_SRAM_STATS_BLK; | |
7584 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
7585 | i += sizeof(u32)) { | |
7586 | tg3_write_mem(tp, i, 0); | |
7587 | udelay(40); | |
7588 | } | |
1da177e4 LT |
7589 | } |
7590 | ||
7591 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
7592 | ||
7593 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
7594 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
7595 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7596 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
7597 | ||
c94e3941 MC |
7598 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { |
7599 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
7600 | /* reset to prevent losing 1st rx packet intermittently */ | |
7601 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
7602 | udelay(10); | |
7603 | } | |
7604 | ||
3bda1258 MC |
7605 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7606 | tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
7607 | else | |
7608 | tp->mac_mode = 0; | |
7609 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
1da177e4 | 7610 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; |
e8f3f6ca MC |
7611 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
7612 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
7613 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | |
7614 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
7615 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
7616 | udelay(40); | |
7617 | ||
314fba34 | 7618 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
9d26e213 | 7619 | * If TG3_FLG2_IS_NIC is zero, we should read the |
314fba34 MC |
7620 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
7621 | * whether used as inputs or outputs, are set by boot code after | |
7622 | * reset. | |
7623 | */ | |
9d26e213 | 7624 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { |
314fba34 MC |
7625 | u32 gpio_mask; |
7626 | ||
9d26e213 MC |
7627 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
7628 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
7629 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
7630 | |
7631 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
7632 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
7633 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
7634 | ||
af36e6b6 MC |
7635 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
7636 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
7637 | ||
aaf84465 | 7638 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
7639 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
7640 | ||
7641 | /* GPIO1 must be driven high for eeprom write protect */ | |
9d26e213 MC |
7642 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) |
7643 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
7644 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 7645 | } |
1da177e4 LT |
7646 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
7647 | udelay(100); | |
7648 | ||
baf8a94a MC |
7649 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) { |
7650 | val = tr32(MSGINT_MODE); | |
7651 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
7652 | tw32(MSGINT_MODE, val); | |
7653 | } | |
7654 | ||
1da177e4 LT |
7655 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
7656 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
7657 | udelay(40); | |
7658 | } | |
7659 | ||
7660 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
7661 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
7662 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
7663 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
7664 | WDMAC_MODE_LNGREAD_ENAB); | |
7665 | ||
85e94ced MC |
7666 | /* If statement applies to 5705 and 5750 PCI devices only */ |
7667 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
7668 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
7669 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { | |
29ea095f | 7670 | if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && |
1da177e4 LT |
7671 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
7672 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
7673 | /* nothing */ | |
7674 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
7675 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
7676 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
7677 | val |= WDMAC_MODE_RX_ACCEL; | |
7678 | } | |
7679 | } | |
7680 | ||
d9ab5ad1 | 7681 | /* Enable host coalescing bug fix */ |
321d32a0 | 7682 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
f51f3562 | 7683 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 7684 | |
788a035e MC |
7685 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
7686 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
7687 | ||
1da177e4 LT |
7688 | tw32_f(WDMAC_MODE, val); |
7689 | udelay(40); | |
7690 | ||
9974a356 MC |
7691 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
7692 | u16 pcix_cmd; | |
7693 | ||
7694 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7695 | &pcix_cmd); | |
1da177e4 | 7696 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
7697 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
7698 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 7699 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
7700 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
7701 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 7702 | } |
9974a356 MC |
7703 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
7704 | pcix_cmd); | |
1da177e4 LT |
7705 | } |
7706 | ||
7707 | tw32_f(RDMAC_MODE, rdmac_mode); | |
7708 | udelay(40); | |
7709 | ||
7710 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
7711 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7712 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
9936bcf6 MC |
7713 | |
7714 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
7715 | tw32(SNDDATAC_MODE, | |
7716 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
7717 | else | |
7718 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
7719 | ||
1da177e4 LT |
7720 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
7721 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7722 | tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ); | |
7723 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); | |
1da177e4 LT |
7724 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
7725 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
baf8a94a MC |
7726 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
7727 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) | |
7728 | val |= SNDBDI_MODE_MULTI_TXQ_EN; | |
7729 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
7730 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
7731 | ||
7732 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
7733 | err = tg3_load_5701_a0_firmware_fix(tp); | |
7734 | if (err) | |
7735 | return err; | |
7736 | } | |
7737 | ||
1da177e4 LT |
7738 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
7739 | err = tg3_load_tso_firmware(tp); | |
7740 | if (err) | |
7741 | return err; | |
7742 | } | |
1da177e4 LT |
7743 | |
7744 | tp->tx_mode = TX_MODE_ENABLE; | |
7745 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
7746 | udelay(100); | |
7747 | ||
baf8a94a MC |
7748 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { |
7749 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
7750 | u8 *ent = (u8 *)&val; | |
7751 | ||
7752 | /* Setup the indirection table */ | |
7753 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
7754 | int idx = i % sizeof(val); | |
7755 | ||
7756 | ent[idx] = i % (tp->irq_cnt - 1); | |
7757 | if (idx == sizeof(val) - 1) { | |
7758 | tw32(reg, val); | |
7759 | reg += 4; | |
7760 | } | |
7761 | } | |
7762 | ||
7763 | /* Setup the "secret" hash key. */ | |
7764 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
7765 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
7766 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
7767 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
7768 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
7769 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
7770 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
7771 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
7772 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
7773 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
7774 | } | |
7775 | ||
1da177e4 | 7776 | tp->rx_mode = RX_MODE_ENABLE; |
321d32a0 | 7777 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
af36e6b6 MC |
7778 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
7779 | ||
baf8a94a MC |
7780 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
7781 | tp->rx_mode |= RX_MODE_RSS_ENABLE | | |
7782 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
7783 | RX_MODE_RSS_IPV6_HASH_EN | | |
7784 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
7785 | RX_MODE_RSS_IPV4_HASH_EN | | |
7786 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
7787 | ||
1da177e4 LT |
7788 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
7789 | udelay(10); | |
7790 | ||
1da177e4 LT |
7791 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
7792 | ||
7793 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
c94e3941 | 7794 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { |
1da177e4 LT |
7795 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
7796 | udelay(10); | |
7797 | } | |
7798 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
7799 | udelay(10); | |
7800 | ||
7801 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
7802 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && | |
7803 | !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) { | |
7804 | /* Set drive transmission level to 1.2V */ | |
7805 | /* only if the signal pre-emphasis bit is not set */ | |
7806 | val = tr32(MAC_SERDES_CFG); | |
7807 | val &= 0xfffff000; | |
7808 | val |= 0x880; | |
7809 | tw32(MAC_SERDES_CFG, val); | |
7810 | } | |
7811 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
7812 | tw32(MAC_SERDES_CFG, 0x616000); | |
7813 | } | |
7814 | ||
7815 | /* Prevent chip from dropping frames when flow control | |
7816 | * is enabled. | |
7817 | */ | |
7818 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2); | |
7819 | ||
7820 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
7821 | (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
7822 | /* Use hardware link auto-negotiation */ | |
7823 | tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; | |
7824 | } | |
7825 | ||
d4d2c558 MC |
7826 | if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && |
7827 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { | |
7828 | u32 tmp; | |
7829 | ||
7830 | tmp = tr32(SERDES_RX_CTRL); | |
7831 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
7832 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
7833 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
7834 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
7835 | } | |
7836 | ||
dd477003 MC |
7837 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
7838 | if (tp->link_config.phy_is_low_power) { | |
7839 | tp->link_config.phy_is_low_power = 0; | |
7840 | tp->link_config.speed = tp->link_config.orig_speed; | |
7841 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
7842 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
7843 | } | |
1da177e4 | 7844 | |
dd477003 MC |
7845 | err = tg3_setup_phy(tp, 0); |
7846 | if (err) | |
7847 | return err; | |
1da177e4 | 7848 | |
dd477003 | 7849 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && |
7f97a4bd | 7850 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) { |
dd477003 MC |
7851 | u32 tmp; |
7852 | ||
7853 | /* Clear CRC stats. */ | |
7854 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
7855 | tg3_writephy(tp, MII_TG3_TEST1, | |
7856 | tmp | MII_TG3_TEST1_CRC_EN); | |
7857 | tg3_readphy(tp, 0x14, &tmp); | |
7858 | } | |
1da177e4 LT |
7859 | } |
7860 | } | |
7861 | ||
7862 | __tg3_set_rx_mode(tp->dev); | |
7863 | ||
7864 | /* Initialize receive rules. */ | |
7865 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
7866 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
7867 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
7868 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
7869 | ||
4cf78e4f | 7870 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
a4e2b347 | 7871 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
1da177e4 LT |
7872 | limit = 8; |
7873 | else | |
7874 | limit = 16; | |
7875 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
7876 | limit -= 4; | |
7877 | switch (limit) { | |
7878 | case 16: | |
7879 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
7880 | case 15: | |
7881 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
7882 | case 14: | |
7883 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
7884 | case 13: | |
7885 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
7886 | case 12: | |
7887 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
7888 | case 11: | |
7889 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
7890 | case 10: | |
7891 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
7892 | case 9: | |
7893 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
7894 | case 8: | |
7895 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
7896 | case 7: | |
7897 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
7898 | case 6: | |
7899 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
7900 | case 5: | |
7901 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
7902 | case 4: | |
7903 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
7904 | case 3: | |
7905 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
7906 | case 2: | |
7907 | case 1: | |
7908 | ||
7909 | default: | |
7910 | break; | |
855e1111 | 7911 | } |
1da177e4 | 7912 | |
9ce768ea MC |
7913 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7914 | /* Write our heartbeat update interval to APE. */ | |
7915 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
7916 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 7917 | |
1da177e4 LT |
7918 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
7919 | ||
1da177e4 LT |
7920 | return 0; |
7921 | } | |
7922 | ||
7923 | /* Called at device open time to get the chip ready for | |
7924 | * packet processing. Invoked with tp->lock held. | |
7925 | */ | |
8e7a22e3 | 7926 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 7927 | { |
1da177e4 LT |
7928 | tg3_switch_clocks(tp); |
7929 | ||
7930 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
7931 | ||
2f751b67 | 7932 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
7933 | } |
7934 | ||
7935 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
7936 | do { u32 __val = tr32(REG); \ | |
7937 | (PSTAT)->low += __val; \ | |
7938 | if ((PSTAT)->low < __val) \ | |
7939 | (PSTAT)->high += 1; \ | |
7940 | } while (0) | |
7941 | ||
7942 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
7943 | { | |
7944 | struct tg3_hw_stats *sp = tp->hw_stats; | |
7945 | ||
7946 | if (!netif_carrier_ok(tp->dev)) | |
7947 | return; | |
7948 | ||
7949 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
7950 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
7951 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
7952 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
7953 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
7954 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
7955 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
7956 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
7957 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
7958 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
7959 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
7960 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
7961 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
7962 | ||
7963 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
7964 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
7965 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
7966 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
7967 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
7968 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
7969 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
7970 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
7971 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
7972 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
7973 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
7974 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
7975 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
7976 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
7977 | |
7978 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
7979 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
7980 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); | |
1da177e4 LT |
7981 | } |
7982 | ||
7983 | static void tg3_timer(unsigned long __opaque) | |
7984 | { | |
7985 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 7986 | |
f475f163 MC |
7987 | if (tp->irq_sync) |
7988 | goto restart_timer; | |
7989 | ||
f47c11ee | 7990 | spin_lock(&tp->lock); |
1da177e4 | 7991 | |
fac9b83e DM |
7992 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { |
7993 | /* All of this garbage is because when using non-tagged | |
7994 | * IRQ status the mailbox/status_block protocol the chip | |
7995 | * uses with the cpu is race prone. | |
7996 | */ | |
898a56f8 | 7997 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
7998 | tw32(GRC_LOCAL_CTRL, |
7999 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
8000 | } else { | |
8001 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 8002 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 8003 | } |
1da177e4 | 8004 | |
fac9b83e DM |
8005 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
8006 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | |
f47c11ee | 8007 | spin_unlock(&tp->lock); |
fac9b83e DM |
8008 | schedule_work(&tp->reset_task); |
8009 | return; | |
8010 | } | |
1da177e4 LT |
8011 | } |
8012 | ||
1da177e4 LT |
8013 | /* This part only runs once per second. */ |
8014 | if (!--tp->timer_counter) { | |
fac9b83e DM |
8015 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
8016 | tg3_periodic_fetch_stats(tp); | |
8017 | ||
1da177e4 LT |
8018 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
8019 | u32 mac_stat; | |
8020 | int phy_event; | |
8021 | ||
8022 | mac_stat = tr32(MAC_STATUS); | |
8023 | ||
8024 | phy_event = 0; | |
8025 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) { | |
8026 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) | |
8027 | phy_event = 1; | |
8028 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
8029 | phy_event = 1; | |
8030 | ||
8031 | if (phy_event) | |
8032 | tg3_setup_phy(tp, 0); | |
8033 | } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { | |
8034 | u32 mac_stat = tr32(MAC_STATUS); | |
8035 | int need_setup = 0; | |
8036 | ||
8037 | if (netif_carrier_ok(tp->dev) && | |
8038 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
8039 | need_setup = 1; | |
8040 | } | |
8041 | if (! netif_carrier_ok(tp->dev) && | |
8042 | (mac_stat & (MAC_STATUS_PCS_SYNCED | | |
8043 | MAC_STATUS_SIGNAL_DET))) { | |
8044 | need_setup = 1; | |
8045 | } | |
8046 | if (need_setup) { | |
3d3ebe74 MC |
8047 | if (!tp->serdes_counter) { |
8048 | tw32_f(MAC_MODE, | |
8049 | (tp->mac_mode & | |
8050 | ~MAC_MODE_PORT_MODE_MASK)); | |
8051 | udelay(40); | |
8052 | tw32_f(MAC_MODE, tp->mac_mode); | |
8053 | udelay(40); | |
8054 | } | |
1da177e4 LT |
8055 | tg3_setup_phy(tp, 0); |
8056 | } | |
747e8f8b MC |
8057 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
8058 | tg3_serdes_parallel_detect(tp); | |
1da177e4 LT |
8059 | |
8060 | tp->timer_counter = tp->timer_multiplier; | |
8061 | } | |
8062 | ||
130b8e4d MC |
8063 | /* Heartbeat is only sent once every 2 seconds. |
8064 | * | |
8065 | * The heartbeat is to tell the ASF firmware that the host | |
8066 | * driver is still alive. In the event that the OS crashes, | |
8067 | * ASF needs to reset the hardware to free up the FIFO space | |
8068 | * that may be filled with rx packets destined for the host. | |
8069 | * If the FIFO is full, ASF will no longer function properly. | |
8070 | * | |
8071 | * Unintended resets have been reported on real time kernels | |
8072 | * where the timer doesn't run on time. Netpoll will also have | |
8073 | * same problem. | |
8074 | * | |
8075 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
8076 | * to check the ring condition when the heartbeat is expiring | |
8077 | * before doing the reset. This will prevent most unintended | |
8078 | * resets. | |
8079 | */ | |
1da177e4 | 8080 | if (!--tp->asf_counter) { |
bc7959b2 MC |
8081 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
8082 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
8083 | tg3_wait_for_event_ack(tp); |
8084 | ||
bbadf503 | 8085 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 8086 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 8087 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
28fbef78 | 8088 | /* 5 seconds timeout */ |
bbadf503 | 8089 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); |
4ba526ce MC |
8090 | |
8091 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
8092 | } |
8093 | tp->asf_counter = tp->asf_multiplier; | |
8094 | } | |
8095 | ||
f47c11ee | 8096 | spin_unlock(&tp->lock); |
1da177e4 | 8097 | |
f475f163 | 8098 | restart_timer: |
1da177e4 LT |
8099 | tp->timer.expires = jiffies + tp->timer_offset; |
8100 | add_timer(&tp->timer); | |
8101 | } | |
8102 | ||
4f125f42 | 8103 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 8104 | { |
7d12e780 | 8105 | irq_handler_t fn; |
fcfa0a32 | 8106 | unsigned long flags; |
4f125f42 MC |
8107 | char *name; |
8108 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
8109 | ||
8110 | if (tp->irq_cnt == 1) | |
8111 | name = tp->dev->name; | |
8112 | else { | |
8113 | name = &tnapi->irq_lbl[0]; | |
8114 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
8115 | name[IFNAMSIZ-1] = 0; | |
8116 | } | |
fcfa0a32 | 8117 | |
679563f4 | 8118 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { |
fcfa0a32 MC |
8119 | fn = tg3_msi; |
8120 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
8121 | fn = tg3_msi_1shot; | |
1fb9df5d | 8122 | flags = IRQF_SAMPLE_RANDOM; |
fcfa0a32 MC |
8123 | } else { |
8124 | fn = tg3_interrupt; | |
8125 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
8126 | fn = tg3_interrupt_tagged; | |
1fb9df5d | 8127 | flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM; |
fcfa0a32 | 8128 | } |
4f125f42 MC |
8129 | |
8130 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
8131 | } |
8132 | ||
7938109f MC |
8133 | static int tg3_test_interrupt(struct tg3 *tp) |
8134 | { | |
09943a18 | 8135 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 8136 | struct net_device *dev = tp->dev; |
b16250e3 | 8137 | int err, i, intr_ok = 0; |
f6eb9b1f | 8138 | u32 val; |
7938109f | 8139 | |
d4bc3927 MC |
8140 | if (!netif_running(dev)) |
8141 | return -ENODEV; | |
8142 | ||
7938109f MC |
8143 | tg3_disable_ints(tp); |
8144 | ||
4f125f42 | 8145 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 8146 | |
f6eb9b1f MC |
8147 | /* |
8148 | * Turn off MSI one shot mode. Otherwise this test has no | |
8149 | * observable way to know whether the interrupt was delivered. | |
8150 | */ | |
8151 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | |
8152 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { | |
8153 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; | |
8154 | tw32(MSGINT_MODE, val); | |
8155 | } | |
8156 | ||
4f125f42 | 8157 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 8158 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
8159 | if (err) |
8160 | return err; | |
8161 | ||
898a56f8 | 8162 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
8163 | tg3_enable_ints(tp); |
8164 | ||
8165 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 8166 | tnapi->coal_now); |
7938109f MC |
8167 | |
8168 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
8169 | u32 int_mbox, misc_host_ctrl; |
8170 | ||
898a56f8 | 8171 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
8172 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
8173 | ||
8174 | if ((int_mbox != 0) || | |
8175 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
8176 | intr_ok = 1; | |
7938109f | 8177 | break; |
b16250e3 MC |
8178 | } |
8179 | ||
7938109f MC |
8180 | msleep(10); |
8181 | } | |
8182 | ||
8183 | tg3_disable_ints(tp); | |
8184 | ||
4f125f42 | 8185 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 8186 | |
4f125f42 | 8187 | err = tg3_request_irq(tp, 0); |
7938109f MC |
8188 | |
8189 | if (err) | |
8190 | return err; | |
8191 | ||
f6eb9b1f MC |
8192 | if (intr_ok) { |
8193 | /* Reenable MSI one shot mode. */ | |
8194 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | |
8195 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { | |
8196 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; | |
8197 | tw32(MSGINT_MODE, val); | |
8198 | } | |
7938109f | 8199 | return 0; |
f6eb9b1f | 8200 | } |
7938109f MC |
8201 | |
8202 | return -EIO; | |
8203 | } | |
8204 | ||
8205 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
8206 | * successfully restored | |
8207 | */ | |
8208 | static int tg3_test_msi(struct tg3 *tp) | |
8209 | { | |
7938109f MC |
8210 | int err; |
8211 | u16 pci_cmd; | |
8212 | ||
8213 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) | |
8214 | return 0; | |
8215 | ||
8216 | /* Turn off SERR reporting in case MSI terminates with Master | |
8217 | * Abort. | |
8218 | */ | |
8219 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
8220 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
8221 | pci_cmd & ~PCI_COMMAND_SERR); | |
8222 | ||
8223 | err = tg3_test_interrupt(tp); | |
8224 | ||
8225 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
8226 | ||
8227 | if (!err) | |
8228 | return 0; | |
8229 | ||
8230 | /* other failures */ | |
8231 | if (err != -EIO) | |
8232 | return err; | |
8233 | ||
8234 | /* MSI test failed, go back to INTx mode */ | |
8235 | printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " | |
8236 | "switching to INTx mode. Please report this failure to " | |
8237 | "the PCI maintainer and include system chipset information.\n", | |
8238 | tp->dev->name); | |
8239 | ||
4f125f42 | 8240 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 8241 | |
7938109f MC |
8242 | pci_disable_msi(tp->pdev); |
8243 | ||
8244 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
8245 | ||
4f125f42 | 8246 | err = tg3_request_irq(tp, 0); |
7938109f MC |
8247 | if (err) |
8248 | return err; | |
8249 | ||
8250 | /* Need to reset the chip because the MSI cycle may have terminated | |
8251 | * with Master Abort. | |
8252 | */ | |
f47c11ee | 8253 | tg3_full_lock(tp, 1); |
7938109f | 8254 | |
944d980e | 8255 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 8256 | err = tg3_init_hw(tp, 1); |
7938109f | 8257 | |
f47c11ee | 8258 | tg3_full_unlock(tp); |
7938109f MC |
8259 | |
8260 | if (err) | |
4f125f42 | 8261 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
8262 | |
8263 | return err; | |
8264 | } | |
8265 | ||
9e9fd12d MC |
8266 | static int tg3_request_firmware(struct tg3 *tp) |
8267 | { | |
8268 | const __be32 *fw_data; | |
8269 | ||
8270 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
8271 | printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n", | |
8272 | tp->dev->name, tp->fw_needed); | |
8273 | return -ENOENT; | |
8274 | } | |
8275 | ||
8276 | fw_data = (void *)tp->fw->data; | |
8277 | ||
8278 | /* Firmware blob starts with version numbers, followed by | |
8279 | * start address and _full_ length including BSS sections | |
8280 | * (which must be longer than the actual data, of course | |
8281 | */ | |
8282 | ||
8283 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
8284 | if (tp->fw_len < (tp->fw->size - 12)) { | |
8285 | printk(KERN_ERR "%s: bogus length %d in \"%s\"\n", | |
8286 | tp->dev->name, tp->fw_len, tp->fw_needed); | |
8287 | release_firmware(tp->fw); | |
8288 | tp->fw = NULL; | |
8289 | return -EINVAL; | |
8290 | } | |
8291 | ||
8292 | /* We no longer need firmware; we have it. */ | |
8293 | tp->fw_needed = NULL; | |
8294 | return 0; | |
8295 | } | |
8296 | ||
679563f4 MC |
8297 | static bool tg3_enable_msix(struct tg3 *tp) |
8298 | { | |
8299 | int i, rc, cpus = num_online_cpus(); | |
8300 | struct msix_entry msix_ent[tp->irq_max]; | |
8301 | ||
8302 | if (cpus == 1) | |
8303 | /* Just fallback to the simpler MSI mode. */ | |
8304 | return false; | |
8305 | ||
8306 | /* | |
8307 | * We want as many rx rings enabled as there are cpus. | |
8308 | * The first MSIX vector only deals with link interrupts, etc, | |
8309 | * so we add one to the number of vectors we are requesting. | |
8310 | */ | |
8311 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
8312 | ||
8313 | for (i = 0; i < tp->irq_max; i++) { | |
8314 | msix_ent[i].entry = i; | |
8315 | msix_ent[i].vector = 0; | |
8316 | } | |
8317 | ||
8318 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
8319 | if (rc != 0) { | |
8320 | if (rc < TG3_RSS_MIN_NUM_MSIX_VECS) | |
8321 | return false; | |
8322 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) | |
8323 | return false; | |
8324 | printk(KERN_NOTICE | |
8325 | "%s: Requested %d MSI-X vectors, received %d\n", | |
8326 | tp->dev->name, tp->irq_cnt, rc); | |
8327 | tp->irq_cnt = rc; | |
8328 | } | |
8329 | ||
baf8a94a MC |
8330 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS; |
8331 | ||
679563f4 MC |
8332 | for (i = 0; i < tp->irq_max; i++) |
8333 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
8334 | ||
fe5f5787 MC |
8335 | tp->dev->real_num_tx_queues = tp->irq_cnt - 1; |
8336 | ||
679563f4 MC |
8337 | return true; |
8338 | } | |
8339 | ||
07b0173c MC |
8340 | static void tg3_ints_init(struct tg3 *tp) |
8341 | { | |
679563f4 MC |
8342 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) && |
8343 | !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
07b0173c MC |
8344 | /* All MSI supporting chips should support tagged |
8345 | * status. Assert that this is the case. | |
8346 | */ | |
679563f4 MC |
8347 | printk(KERN_WARNING PFX "%s: MSI without TAGGED? " |
8348 | "Not using MSI.\n", tp->dev->name); | |
8349 | goto defcfg; | |
07b0173c | 8350 | } |
4f125f42 | 8351 | |
679563f4 MC |
8352 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp)) |
8353 | tp->tg3_flags2 |= TG3_FLG2_USING_MSIX; | |
8354 | else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) && | |
8355 | pci_enable_msi(tp->pdev) == 0) | |
8356 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | |
8357 | ||
8358 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { | |
8359 | u32 msi_mode = tr32(MSGINT_MODE); | |
baf8a94a MC |
8360 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) |
8361 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; | |
679563f4 MC |
8362 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
8363 | } | |
8364 | defcfg: | |
8365 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { | |
8366 | tp->irq_cnt = 1; | |
8367 | tp->napi[0].irq_vec = tp->pdev->irq; | |
fe5f5787 | 8368 | tp->dev->real_num_tx_queues = 1; |
679563f4 | 8369 | } |
07b0173c MC |
8370 | } |
8371 | ||
8372 | static void tg3_ints_fini(struct tg3 *tp) | |
8373 | { | |
679563f4 MC |
8374 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) |
8375 | pci_disable_msix(tp->pdev); | |
8376 | else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | |
8377 | pci_disable_msi(tp->pdev); | |
8378 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX; | |
baf8a94a | 8379 | tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS; |
07b0173c MC |
8380 | } |
8381 | ||
1da177e4 LT |
8382 | static int tg3_open(struct net_device *dev) |
8383 | { | |
8384 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 8385 | int i, err; |
1da177e4 | 8386 | |
9e9fd12d MC |
8387 | if (tp->fw_needed) { |
8388 | err = tg3_request_firmware(tp); | |
8389 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8390 | if (err) | |
8391 | return err; | |
8392 | } else if (err) { | |
8393 | printk(KERN_WARNING "%s: TSO capability disabled.\n", | |
8394 | tp->dev->name); | |
8395 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; | |
8396 | } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
8397 | printk(KERN_NOTICE "%s: TSO capability restored.\n", | |
8398 | tp->dev->name); | |
8399 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; | |
8400 | } | |
8401 | } | |
8402 | ||
c49a1561 MC |
8403 | netif_carrier_off(tp->dev); |
8404 | ||
bc1c7567 | 8405 | err = tg3_set_power_state(tp, PCI_D0); |
2f751b67 | 8406 | if (err) |
bc1c7567 | 8407 | return err; |
2f751b67 MC |
8408 | |
8409 | tg3_full_lock(tp, 0); | |
bc1c7567 | 8410 | |
1da177e4 LT |
8411 | tg3_disable_ints(tp); |
8412 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
8413 | ||
f47c11ee | 8414 | tg3_full_unlock(tp); |
1da177e4 | 8415 | |
679563f4 MC |
8416 | /* |
8417 | * Setup interrupts first so we know how | |
8418 | * many NAPI resources to allocate | |
8419 | */ | |
8420 | tg3_ints_init(tp); | |
8421 | ||
1da177e4 LT |
8422 | /* The placement of this call is tied |
8423 | * to the setup and use of Host TX descriptors. | |
8424 | */ | |
8425 | err = tg3_alloc_consistent(tp); | |
8426 | if (err) | |
679563f4 | 8427 | goto err_out1; |
88b06bc2 | 8428 | |
fed97810 | 8429 | tg3_napi_enable(tp); |
1da177e4 | 8430 | |
4f125f42 MC |
8431 | for (i = 0; i < tp->irq_cnt; i++) { |
8432 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8433 | err = tg3_request_irq(tp, i); | |
8434 | if (err) { | |
8435 | for (i--; i >= 0; i--) | |
8436 | free_irq(tnapi->irq_vec, tnapi); | |
8437 | break; | |
8438 | } | |
8439 | } | |
1da177e4 | 8440 | |
07b0173c | 8441 | if (err) |
679563f4 | 8442 | goto err_out2; |
bea3348e | 8443 | |
f47c11ee | 8444 | tg3_full_lock(tp, 0); |
1da177e4 | 8445 | |
8e7a22e3 | 8446 | err = tg3_init_hw(tp, 1); |
1da177e4 | 8447 | if (err) { |
944d980e | 8448 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
8449 | tg3_free_rings(tp); |
8450 | } else { | |
fac9b83e DM |
8451 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) |
8452 | tp->timer_offset = HZ; | |
8453 | else | |
8454 | tp->timer_offset = HZ / 10; | |
8455 | ||
8456 | BUG_ON(tp->timer_offset > HZ); | |
8457 | tp->timer_counter = tp->timer_multiplier = | |
8458 | (HZ / tp->timer_offset); | |
8459 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 8460 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
8461 | |
8462 | init_timer(&tp->timer); | |
8463 | tp->timer.expires = jiffies + tp->timer_offset; | |
8464 | tp->timer.data = (unsigned long) tp; | |
8465 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
8466 | } |
8467 | ||
f47c11ee | 8468 | tg3_full_unlock(tp); |
1da177e4 | 8469 | |
07b0173c | 8470 | if (err) |
679563f4 | 8471 | goto err_out3; |
1da177e4 | 8472 | |
7938109f MC |
8473 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { |
8474 | err = tg3_test_msi(tp); | |
fac9b83e | 8475 | |
7938109f | 8476 | if (err) { |
f47c11ee | 8477 | tg3_full_lock(tp, 0); |
944d980e | 8478 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 8479 | tg3_free_rings(tp); |
f47c11ee | 8480 | tg3_full_unlock(tp); |
7938109f | 8481 | |
679563f4 | 8482 | goto err_out2; |
7938109f | 8483 | } |
fcfa0a32 | 8484 | |
f6eb9b1f MC |
8485 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
8486 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI) && | |
8487 | (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) { | |
8488 | u32 val = tr32(PCIE_TRANSACTION_CFG); | |
fcfa0a32 | 8489 | |
f6eb9b1f MC |
8490 | tw32(PCIE_TRANSACTION_CFG, |
8491 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 8492 | } |
7938109f MC |
8493 | } |
8494 | ||
b02fd9e3 MC |
8495 | tg3_phy_start(tp); |
8496 | ||
f47c11ee | 8497 | tg3_full_lock(tp, 0); |
1da177e4 | 8498 | |
7938109f MC |
8499 | add_timer(&tp->timer); |
8500 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
1da177e4 LT |
8501 | tg3_enable_ints(tp); |
8502 | ||
f47c11ee | 8503 | tg3_full_unlock(tp); |
1da177e4 | 8504 | |
fe5f5787 | 8505 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
8506 | |
8507 | return 0; | |
07b0173c | 8508 | |
679563f4 | 8509 | err_out3: |
4f125f42 MC |
8510 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
8511 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8512 | free_irq(tnapi->irq_vec, tnapi); | |
8513 | } | |
07b0173c | 8514 | |
679563f4 | 8515 | err_out2: |
fed97810 | 8516 | tg3_napi_disable(tp); |
07b0173c | 8517 | tg3_free_consistent(tp); |
679563f4 MC |
8518 | |
8519 | err_out1: | |
8520 | tg3_ints_fini(tp); | |
07b0173c | 8521 | return err; |
1da177e4 LT |
8522 | } |
8523 | ||
8524 | #if 0 | |
8525 | /*static*/ void tg3_dump_state(struct tg3 *tp) | |
8526 | { | |
8527 | u32 val32, val32_2, val32_3, val32_4, val32_5; | |
8528 | u16 val16; | |
8529 | int i; | |
898a56f8 | 8530 | struct tg3_hw_status *sblk = tp->napi[0]->hw_status; |
1da177e4 LT |
8531 | |
8532 | pci_read_config_word(tp->pdev, PCI_STATUS, &val16); | |
8533 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32); | |
8534 | printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n", | |
8535 | val16, val32); | |
8536 | ||
8537 | /* MAC block */ | |
8538 | printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n", | |
8539 | tr32(MAC_MODE), tr32(MAC_STATUS)); | |
8540 | printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n", | |
8541 | tr32(MAC_EVENT), tr32(MAC_LED_CTRL)); | |
8542 | printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n", | |
8543 | tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS)); | |
8544 | printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n", | |
8545 | tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS)); | |
8546 | ||
8547 | /* Send data initiator control block */ | |
8548 | printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n", | |
8549 | tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS)); | |
8550 | printk(" SNDDATAI_STATSCTRL[%08x]\n", | |
8551 | tr32(SNDDATAI_STATSCTRL)); | |
8552 | ||
8553 | /* Send data completion control block */ | |
8554 | printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE)); | |
8555 | ||
8556 | /* Send BD ring selector block */ | |
8557 | printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n", | |
8558 | tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS)); | |
8559 | ||
8560 | /* Send BD initiator control block */ | |
8561 | printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n", | |
8562 | tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS)); | |
8563 | ||
8564 | /* Send BD completion control block */ | |
8565 | printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE)); | |
8566 | ||
8567 | /* Receive list placement control block */ | |
8568 | printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n", | |
8569 | tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS)); | |
8570 | printk(" RCVLPC_STATSCTRL[%08x]\n", | |
8571 | tr32(RCVLPC_STATSCTRL)); | |
8572 | ||
8573 | /* Receive data and receive BD initiator control block */ | |
8574 | printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n", | |
8575 | tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS)); | |
8576 | ||
8577 | /* Receive data completion control block */ | |
8578 | printk("DEBUG: RCVDCC_MODE[%08x]\n", | |
8579 | tr32(RCVDCC_MODE)); | |
8580 | ||
8581 | /* Receive BD initiator control block */ | |
8582 | printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n", | |
8583 | tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS)); | |
8584 | ||
8585 | /* Receive BD completion control block */ | |
8586 | printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n", | |
8587 | tr32(RCVCC_MODE), tr32(RCVCC_STATUS)); | |
8588 | ||
8589 | /* Receive list selector control block */ | |
8590 | printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n", | |
8591 | tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS)); | |
8592 | ||
8593 | /* Mbuf cluster free block */ | |
8594 | printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n", | |
8595 | tr32(MBFREE_MODE), tr32(MBFREE_STATUS)); | |
8596 | ||
8597 | /* Host coalescing control block */ | |
8598 | printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n", | |
8599 | tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS)); | |
8600 | printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n", | |
8601 | tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
8602 | tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW)); | |
8603 | printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n", | |
8604 | tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
8605 | tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW)); | |
8606 | printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n", | |
8607 | tr32(HOSTCC_STATS_BLK_NIC_ADDR)); | |
8608 | printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n", | |
8609 | tr32(HOSTCC_STATUS_BLK_NIC_ADDR)); | |
8610 | ||
8611 | /* Memory arbiter control block */ | |
8612 | printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n", | |
8613 | tr32(MEMARB_MODE), tr32(MEMARB_STATUS)); | |
8614 | ||
8615 | /* Buffer manager control block */ | |
8616 | printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n", | |
8617 | tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS)); | |
8618 | printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n", | |
8619 | tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE)); | |
8620 | printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] " | |
8621 | "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n", | |
8622 | tr32(BUFMGR_DMA_DESC_POOL_ADDR), | |
8623 | tr32(BUFMGR_DMA_DESC_POOL_SIZE)); | |
8624 | ||
8625 | /* Read DMA control block */ | |
8626 | printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n", | |
8627 | tr32(RDMAC_MODE), tr32(RDMAC_STATUS)); | |
8628 | ||
8629 | /* Write DMA control block */ | |
8630 | printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n", | |
8631 | tr32(WDMAC_MODE), tr32(WDMAC_STATUS)); | |
8632 | ||
8633 | /* DMA completion block */ | |
8634 | printk("DEBUG: DMAC_MODE[%08x]\n", | |
8635 | tr32(DMAC_MODE)); | |
8636 | ||
8637 | /* GRC block */ | |
8638 | printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n", | |
8639 | tr32(GRC_MODE), tr32(GRC_MISC_CFG)); | |
8640 | printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n", | |
8641 | tr32(GRC_LOCAL_CTRL)); | |
8642 | ||
8643 | /* TG3_BDINFOs */ | |
8644 | printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n", | |
8645 | tr32(RCVDBDI_JUMBO_BD + 0x0), | |
8646 | tr32(RCVDBDI_JUMBO_BD + 0x4), | |
8647 | tr32(RCVDBDI_JUMBO_BD + 0x8), | |
8648 | tr32(RCVDBDI_JUMBO_BD + 0xc)); | |
8649 | printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n", | |
8650 | tr32(RCVDBDI_STD_BD + 0x0), | |
8651 | tr32(RCVDBDI_STD_BD + 0x4), | |
8652 | tr32(RCVDBDI_STD_BD + 0x8), | |
8653 | tr32(RCVDBDI_STD_BD + 0xc)); | |
8654 | printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n", | |
8655 | tr32(RCVDBDI_MINI_BD + 0x0), | |
8656 | tr32(RCVDBDI_MINI_BD + 0x4), | |
8657 | tr32(RCVDBDI_MINI_BD + 0x8), | |
8658 | tr32(RCVDBDI_MINI_BD + 0xc)); | |
8659 | ||
8660 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32); | |
8661 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2); | |
8662 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3); | |
8663 | tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4); | |
8664 | printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n", | |
8665 | val32, val32_2, val32_3, val32_4); | |
8666 | ||
8667 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32); | |
8668 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2); | |
8669 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3); | |
8670 | tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4); | |
8671 | printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n", | |
8672 | val32, val32_2, val32_3, val32_4); | |
8673 | ||
8674 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32); | |
8675 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2); | |
8676 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3); | |
8677 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4); | |
8678 | tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5); | |
8679 | printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n", | |
8680 | val32, val32_2, val32_3, val32_4, val32_5); | |
8681 | ||
8682 | /* SW status block */ | |
898a56f8 MC |
8683 | printk(KERN_DEBUG |
8684 | "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", | |
8685 | sblk->status, | |
8686 | sblk->status_tag, | |
8687 | sblk->rx_jumbo_consumer, | |
8688 | sblk->rx_consumer, | |
8689 | sblk->rx_mini_consumer, | |
8690 | sblk->idx[0].rx_producer, | |
8691 | sblk->idx[0].tx_consumer); | |
1da177e4 LT |
8692 | |
8693 | /* SW statistics block */ | |
8694 | printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n", | |
8695 | ((u32 *)tp->hw_stats)[0], | |
8696 | ((u32 *)tp->hw_stats)[1], | |
8697 | ((u32 *)tp->hw_stats)[2], | |
8698 | ((u32 *)tp->hw_stats)[3]); | |
8699 | ||
8700 | /* Mailboxes */ | |
8701 | printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n", | |
09ee929c MC |
8702 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0), |
8703 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4), | |
8704 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0), | |
8705 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4)); | |
1da177e4 LT |
8706 | |
8707 | /* NIC side send descriptors. */ | |
8708 | for (i = 0; i < 6; i++) { | |
8709 | unsigned long txd; | |
8710 | ||
8711 | txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC | |
8712 | + (i * sizeof(struct tg3_tx_buffer_desc)); | |
8713 | printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n", | |
8714 | i, | |
8715 | readl(txd + 0x0), readl(txd + 0x4), | |
8716 | readl(txd + 0x8), readl(txd + 0xc)); | |
8717 | } | |
8718 | ||
8719 | /* NIC side RX descriptors. */ | |
8720 | for (i = 0; i < 6; i++) { | |
8721 | unsigned long rxd; | |
8722 | ||
8723 | rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC | |
8724 | + (i * sizeof(struct tg3_rx_buffer_desc)); | |
8725 | printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n", | |
8726 | i, | |
8727 | readl(rxd + 0x0), readl(rxd + 0x4), | |
8728 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
8729 | rxd += (4 * sizeof(u32)); | |
8730 | printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n", | |
8731 | i, | |
8732 | readl(rxd + 0x0), readl(rxd + 0x4), | |
8733 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
8734 | } | |
8735 | ||
8736 | for (i = 0; i < 6; i++) { | |
8737 | unsigned long rxd; | |
8738 | ||
8739 | rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC | |
8740 | + (i * sizeof(struct tg3_rx_buffer_desc)); | |
8741 | printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n", | |
8742 | i, | |
8743 | readl(rxd + 0x0), readl(rxd + 0x4), | |
8744 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
8745 | rxd += (4 * sizeof(u32)); | |
8746 | printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n", | |
8747 | i, | |
8748 | readl(rxd + 0x0), readl(rxd + 0x4), | |
8749 | readl(rxd + 0x8), readl(rxd + 0xc)); | |
8750 | } | |
8751 | } | |
8752 | #endif | |
8753 | ||
8754 | static struct net_device_stats *tg3_get_stats(struct net_device *); | |
8755 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); | |
8756 | ||
8757 | static int tg3_close(struct net_device *dev) | |
8758 | { | |
4f125f42 | 8759 | int i; |
1da177e4 LT |
8760 | struct tg3 *tp = netdev_priv(dev); |
8761 | ||
fed97810 | 8762 | tg3_napi_disable(tp); |
28e53bdd | 8763 | cancel_work_sync(&tp->reset_task); |
7faa006f | 8764 | |
fe5f5787 | 8765 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
8766 | |
8767 | del_timer_sync(&tp->timer); | |
8768 | ||
24bb4fb6 MC |
8769 | tg3_phy_stop(tp); |
8770 | ||
f47c11ee | 8771 | tg3_full_lock(tp, 1); |
1da177e4 LT |
8772 | #if 0 |
8773 | tg3_dump_state(tp); | |
8774 | #endif | |
8775 | ||
8776 | tg3_disable_ints(tp); | |
8777 | ||
944d980e | 8778 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 8779 | tg3_free_rings(tp); |
5cf64b8a | 8780 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
1da177e4 | 8781 | |
f47c11ee | 8782 | tg3_full_unlock(tp); |
1da177e4 | 8783 | |
4f125f42 MC |
8784 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
8785 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8786 | free_irq(tnapi->irq_vec, tnapi); | |
8787 | } | |
07b0173c MC |
8788 | |
8789 | tg3_ints_fini(tp); | |
1da177e4 LT |
8790 | |
8791 | memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev), | |
8792 | sizeof(tp->net_stats_prev)); | |
8793 | memcpy(&tp->estats_prev, tg3_get_estats(tp), | |
8794 | sizeof(tp->estats_prev)); | |
8795 | ||
8796 | tg3_free_consistent(tp); | |
8797 | ||
bc1c7567 MC |
8798 | tg3_set_power_state(tp, PCI_D3hot); |
8799 | ||
8800 | netif_carrier_off(tp->dev); | |
8801 | ||
1da177e4 LT |
8802 | return 0; |
8803 | } | |
8804 | ||
8805 | static inline unsigned long get_stat64(tg3_stat64_t *val) | |
8806 | { | |
8807 | unsigned long ret; | |
8808 | ||
8809 | #if (BITS_PER_LONG == 32) | |
8810 | ret = val->low; | |
8811 | #else | |
8812 | ret = ((u64)val->high << 32) | ((u64)val->low); | |
8813 | #endif | |
8814 | return ret; | |
8815 | } | |
8816 | ||
816f8b86 SB |
8817 | static inline u64 get_estat64(tg3_stat64_t *val) |
8818 | { | |
8819 | return ((u64)val->high << 32) | ((u64)val->low); | |
8820 | } | |
8821 | ||
1da177e4 LT |
8822 | static unsigned long calc_crc_errors(struct tg3 *tp) |
8823 | { | |
8824 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
8825 | ||
8826 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
8827 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
8828 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
8829 | u32 val; |
8830 | ||
f47c11ee | 8831 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
8832 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
8833 | tg3_writephy(tp, MII_TG3_TEST1, | |
8834 | val | MII_TG3_TEST1_CRC_EN); | |
1da177e4 LT |
8835 | tg3_readphy(tp, 0x14, &val); |
8836 | } else | |
8837 | val = 0; | |
f47c11ee | 8838 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
8839 | |
8840 | tp->phy_crc_errors += val; | |
8841 | ||
8842 | return tp->phy_crc_errors; | |
8843 | } | |
8844 | ||
8845 | return get_stat64(&hw_stats->rx_fcs_errors); | |
8846 | } | |
8847 | ||
8848 | #define ESTAT_ADD(member) \ | |
8849 | estats->member = old_estats->member + \ | |
816f8b86 | 8850 | get_estat64(&hw_stats->member) |
1da177e4 LT |
8851 | |
8852 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
8853 | { | |
8854 | struct tg3_ethtool_stats *estats = &tp->estats; | |
8855 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
8856 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
8857 | ||
8858 | if (!hw_stats) | |
8859 | return old_estats; | |
8860 | ||
8861 | ESTAT_ADD(rx_octets); | |
8862 | ESTAT_ADD(rx_fragments); | |
8863 | ESTAT_ADD(rx_ucast_packets); | |
8864 | ESTAT_ADD(rx_mcast_packets); | |
8865 | ESTAT_ADD(rx_bcast_packets); | |
8866 | ESTAT_ADD(rx_fcs_errors); | |
8867 | ESTAT_ADD(rx_align_errors); | |
8868 | ESTAT_ADD(rx_xon_pause_rcvd); | |
8869 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
8870 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
8871 | ESTAT_ADD(rx_xoff_entered); | |
8872 | ESTAT_ADD(rx_frame_too_long_errors); | |
8873 | ESTAT_ADD(rx_jabbers); | |
8874 | ESTAT_ADD(rx_undersize_packets); | |
8875 | ESTAT_ADD(rx_in_length_errors); | |
8876 | ESTAT_ADD(rx_out_length_errors); | |
8877 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
8878 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
8879 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
8880 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
8881 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
8882 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
8883 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
8884 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
8885 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
8886 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
8887 | ||
8888 | ESTAT_ADD(tx_octets); | |
8889 | ESTAT_ADD(tx_collisions); | |
8890 | ESTAT_ADD(tx_xon_sent); | |
8891 | ESTAT_ADD(tx_xoff_sent); | |
8892 | ESTAT_ADD(tx_flow_control); | |
8893 | ESTAT_ADD(tx_mac_errors); | |
8894 | ESTAT_ADD(tx_single_collisions); | |
8895 | ESTAT_ADD(tx_mult_collisions); | |
8896 | ESTAT_ADD(tx_deferred); | |
8897 | ESTAT_ADD(tx_excessive_collisions); | |
8898 | ESTAT_ADD(tx_late_collisions); | |
8899 | ESTAT_ADD(tx_collide_2times); | |
8900 | ESTAT_ADD(tx_collide_3times); | |
8901 | ESTAT_ADD(tx_collide_4times); | |
8902 | ESTAT_ADD(tx_collide_5times); | |
8903 | ESTAT_ADD(tx_collide_6times); | |
8904 | ESTAT_ADD(tx_collide_7times); | |
8905 | ESTAT_ADD(tx_collide_8times); | |
8906 | ESTAT_ADD(tx_collide_9times); | |
8907 | ESTAT_ADD(tx_collide_10times); | |
8908 | ESTAT_ADD(tx_collide_11times); | |
8909 | ESTAT_ADD(tx_collide_12times); | |
8910 | ESTAT_ADD(tx_collide_13times); | |
8911 | ESTAT_ADD(tx_collide_14times); | |
8912 | ESTAT_ADD(tx_collide_15times); | |
8913 | ESTAT_ADD(tx_ucast_packets); | |
8914 | ESTAT_ADD(tx_mcast_packets); | |
8915 | ESTAT_ADD(tx_bcast_packets); | |
8916 | ESTAT_ADD(tx_carrier_sense_errors); | |
8917 | ESTAT_ADD(tx_discards); | |
8918 | ESTAT_ADD(tx_errors); | |
8919 | ||
8920 | ESTAT_ADD(dma_writeq_full); | |
8921 | ESTAT_ADD(dma_write_prioq_full); | |
8922 | ESTAT_ADD(rxbds_empty); | |
8923 | ESTAT_ADD(rx_discards); | |
8924 | ESTAT_ADD(rx_errors); | |
8925 | ESTAT_ADD(rx_threshold_hit); | |
8926 | ||
8927 | ESTAT_ADD(dma_readq_full); | |
8928 | ESTAT_ADD(dma_read_prioq_full); | |
8929 | ESTAT_ADD(tx_comp_queue_full); | |
8930 | ||
8931 | ESTAT_ADD(ring_set_send_prod_index); | |
8932 | ESTAT_ADD(ring_status_update); | |
8933 | ESTAT_ADD(nic_irqs); | |
8934 | ESTAT_ADD(nic_avoided_irqs); | |
8935 | ESTAT_ADD(nic_tx_threshold_hit); | |
8936 | ||
8937 | return estats; | |
8938 | } | |
8939 | ||
8940 | static struct net_device_stats *tg3_get_stats(struct net_device *dev) | |
8941 | { | |
8942 | struct tg3 *tp = netdev_priv(dev); | |
8943 | struct net_device_stats *stats = &tp->net_stats; | |
8944 | struct net_device_stats *old_stats = &tp->net_stats_prev; | |
8945 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
8946 | ||
8947 | if (!hw_stats) | |
8948 | return old_stats; | |
8949 | ||
8950 | stats->rx_packets = old_stats->rx_packets + | |
8951 | get_stat64(&hw_stats->rx_ucast_packets) + | |
8952 | get_stat64(&hw_stats->rx_mcast_packets) + | |
8953 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 8954 | |
1da177e4 LT |
8955 | stats->tx_packets = old_stats->tx_packets + |
8956 | get_stat64(&hw_stats->tx_ucast_packets) + | |
8957 | get_stat64(&hw_stats->tx_mcast_packets) + | |
8958 | get_stat64(&hw_stats->tx_bcast_packets); | |
8959 | ||
8960 | stats->rx_bytes = old_stats->rx_bytes + | |
8961 | get_stat64(&hw_stats->rx_octets); | |
8962 | stats->tx_bytes = old_stats->tx_bytes + | |
8963 | get_stat64(&hw_stats->tx_octets); | |
8964 | ||
8965 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 8966 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
8967 | stats->tx_errors = old_stats->tx_errors + |
8968 | get_stat64(&hw_stats->tx_errors) + | |
8969 | get_stat64(&hw_stats->tx_mac_errors) + | |
8970 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
8971 | get_stat64(&hw_stats->tx_discards); | |
8972 | ||
8973 | stats->multicast = old_stats->multicast + | |
8974 | get_stat64(&hw_stats->rx_mcast_packets); | |
8975 | stats->collisions = old_stats->collisions + | |
8976 | get_stat64(&hw_stats->tx_collisions); | |
8977 | ||
8978 | stats->rx_length_errors = old_stats->rx_length_errors + | |
8979 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
8980 | get_stat64(&hw_stats->rx_undersize_packets); | |
8981 | ||
8982 | stats->rx_over_errors = old_stats->rx_over_errors + | |
8983 | get_stat64(&hw_stats->rxbds_empty); | |
8984 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
8985 | get_stat64(&hw_stats->rx_align_errors); | |
8986 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
8987 | get_stat64(&hw_stats->tx_discards); | |
8988 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
8989 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
8990 | ||
8991 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
8992 | calc_crc_errors(tp); | |
8993 | ||
4f63b877 JL |
8994 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
8995 | get_stat64(&hw_stats->rx_discards); | |
8996 | ||
1da177e4 LT |
8997 | return stats; |
8998 | } | |
8999 | ||
9000 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9001 | { | |
9002 | u32 reg; | |
9003 | u32 tmp; | |
9004 | int j, k; | |
9005 | ||
9006 | reg = 0xffffffff; | |
9007 | ||
9008 | for (j = 0; j < len; j++) { | |
9009 | reg ^= buf[j]; | |
9010 | ||
9011 | for (k = 0; k < 8; k++) { | |
9012 | tmp = reg & 0x01; | |
9013 | ||
9014 | reg >>= 1; | |
9015 | ||
9016 | if (tmp) { | |
9017 | reg ^= 0xedb88320; | |
9018 | } | |
9019 | } | |
9020 | } | |
9021 | ||
9022 | return ~reg; | |
9023 | } | |
9024 | ||
9025 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9026 | { | |
9027 | /* accept or reject all multicast frames */ | |
9028 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9029 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9030 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9031 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9032 | } | |
9033 | ||
9034 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9035 | { | |
9036 | struct tg3 *tp = netdev_priv(dev); | |
9037 | u32 rx_mode; | |
9038 | ||
9039 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9040 | RX_MODE_KEEP_VLAN_TAG); | |
9041 | ||
9042 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG | |
9043 | * flag clear. | |
9044 | */ | |
9045 | #if TG3_VLAN_TAG_USED | |
9046 | if (!tp->vlgrp && | |
9047 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
9048 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9049 | #else | |
9050 | /* By definition, VLAN is disabled always in this | |
9051 | * case. | |
9052 | */ | |
9053 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
9054 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9055 | #endif | |
9056 | ||
9057 | if (dev->flags & IFF_PROMISC) { | |
9058 | /* Promiscuous mode. */ | |
9059 | rx_mode |= RX_MODE_PROMISC; | |
9060 | } else if (dev->flags & IFF_ALLMULTI) { | |
9061 | /* Accept all multicast. */ | |
9062 | tg3_set_multi (tp, 1); | |
9063 | } else if (dev->mc_count < 1) { | |
9064 | /* Reject all multicast. */ | |
9065 | tg3_set_multi (tp, 0); | |
9066 | } else { | |
9067 | /* Accept one or more multicast(s). */ | |
9068 | struct dev_mc_list *mclist; | |
9069 | unsigned int i; | |
9070 | u32 mc_filter[4] = { 0, }; | |
9071 | u32 regidx; | |
9072 | u32 bit; | |
9073 | u32 crc; | |
9074 | ||
9075 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
9076 | i++, mclist = mclist->next) { | |
9077 | ||
9078 | crc = calc_crc (mclist->dmi_addr, ETH_ALEN); | |
9079 | bit = ~crc & 0x7f; | |
9080 | regidx = (bit & 0x60) >> 5; | |
9081 | bit &= 0x1f; | |
9082 | mc_filter[regidx] |= (1 << bit); | |
9083 | } | |
9084 | ||
9085 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9086 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9087 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9088 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9089 | } | |
9090 | ||
9091 | if (rx_mode != tp->rx_mode) { | |
9092 | tp->rx_mode = rx_mode; | |
9093 | tw32_f(MAC_RX_MODE, rx_mode); | |
9094 | udelay(10); | |
9095 | } | |
9096 | } | |
9097 | ||
9098 | static void tg3_set_rx_mode(struct net_device *dev) | |
9099 | { | |
9100 | struct tg3 *tp = netdev_priv(dev); | |
9101 | ||
e75f7c90 MC |
9102 | if (!netif_running(dev)) |
9103 | return; | |
9104 | ||
f47c11ee | 9105 | tg3_full_lock(tp, 0); |
1da177e4 | 9106 | __tg3_set_rx_mode(dev); |
f47c11ee | 9107 | tg3_full_unlock(tp); |
1da177e4 LT |
9108 | } |
9109 | ||
9110 | #define TG3_REGDUMP_LEN (32 * 1024) | |
9111 | ||
9112 | static int tg3_get_regs_len(struct net_device *dev) | |
9113 | { | |
9114 | return TG3_REGDUMP_LEN; | |
9115 | } | |
9116 | ||
9117 | static void tg3_get_regs(struct net_device *dev, | |
9118 | struct ethtool_regs *regs, void *_p) | |
9119 | { | |
9120 | u32 *p = _p; | |
9121 | struct tg3 *tp = netdev_priv(dev); | |
9122 | u8 *orig_p = _p; | |
9123 | int i; | |
9124 | ||
9125 | regs->version = 0; | |
9126 | ||
9127 | memset(p, 0, TG3_REGDUMP_LEN); | |
9128 | ||
bc1c7567 MC |
9129 | if (tp->link_config.phy_is_low_power) |
9130 | return; | |
9131 | ||
f47c11ee | 9132 | tg3_full_lock(tp, 0); |
1da177e4 LT |
9133 | |
9134 | #define __GET_REG32(reg) (*(p)++ = tr32(reg)) | |
9135 | #define GET_REG32_LOOP(base,len) \ | |
9136 | do { p = (u32 *)(orig_p + (base)); \ | |
9137 | for (i = 0; i < len; i += 4) \ | |
9138 | __GET_REG32((base) + i); \ | |
9139 | } while (0) | |
9140 | #define GET_REG32_1(reg) \ | |
9141 | do { p = (u32 *)(orig_p + (reg)); \ | |
9142 | __GET_REG32((reg)); \ | |
9143 | } while (0) | |
9144 | ||
9145 | GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0); | |
9146 | GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200); | |
9147 | GET_REG32_LOOP(MAC_MODE, 0x4f0); | |
9148 | GET_REG32_LOOP(SNDDATAI_MODE, 0xe0); | |
9149 | GET_REG32_1(SNDDATAC_MODE); | |
9150 | GET_REG32_LOOP(SNDBDS_MODE, 0x80); | |
9151 | GET_REG32_LOOP(SNDBDI_MODE, 0x48); | |
9152 | GET_REG32_1(SNDBDC_MODE); | |
9153 | GET_REG32_LOOP(RCVLPC_MODE, 0x20); | |
9154 | GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c); | |
9155 | GET_REG32_LOOP(RCVDBDI_MODE, 0x0c); | |
9156 | GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c); | |
9157 | GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44); | |
9158 | GET_REG32_1(RCVDCC_MODE); | |
9159 | GET_REG32_LOOP(RCVBDI_MODE, 0x20); | |
9160 | GET_REG32_LOOP(RCVCC_MODE, 0x14); | |
9161 | GET_REG32_LOOP(RCVLSC_MODE, 0x08); | |
9162 | GET_REG32_1(MBFREE_MODE); | |
9163 | GET_REG32_LOOP(HOSTCC_MODE, 0x100); | |
9164 | GET_REG32_LOOP(MEMARB_MODE, 0x10); | |
9165 | GET_REG32_LOOP(BUFMGR_MODE, 0x58); | |
9166 | GET_REG32_LOOP(RDMAC_MODE, 0x08); | |
9167 | GET_REG32_LOOP(WDMAC_MODE, 0x08); | |
091465d7 CE |
9168 | GET_REG32_1(RX_CPU_MODE); |
9169 | GET_REG32_1(RX_CPU_STATE); | |
9170 | GET_REG32_1(RX_CPU_PGMCTR); | |
9171 | GET_REG32_1(RX_CPU_HWBKPT); | |
9172 | GET_REG32_1(TX_CPU_MODE); | |
9173 | GET_REG32_1(TX_CPU_STATE); | |
9174 | GET_REG32_1(TX_CPU_PGMCTR); | |
1da177e4 LT |
9175 | GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110); |
9176 | GET_REG32_LOOP(FTQ_RESET, 0x120); | |
9177 | GET_REG32_LOOP(MSGINT_MODE, 0x0c); | |
9178 | GET_REG32_1(DMAC_MODE); | |
9179 | GET_REG32_LOOP(GRC_MODE, 0x4c); | |
9180 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
9181 | GET_REG32_LOOP(NVRAM_CMD, 0x24); | |
9182 | ||
9183 | #undef __GET_REG32 | |
9184 | #undef GET_REG32_LOOP | |
9185 | #undef GET_REG32_1 | |
9186 | ||
f47c11ee | 9187 | tg3_full_unlock(tp); |
1da177e4 LT |
9188 | } |
9189 | ||
9190 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9191 | { | |
9192 | struct tg3 *tp = netdev_priv(dev); | |
9193 | ||
9194 | return tp->nvram_size; | |
9195 | } | |
9196 | ||
1da177e4 LT |
9197 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
9198 | { | |
9199 | struct tg3 *tp = netdev_priv(dev); | |
9200 | int ret; | |
9201 | u8 *pd; | |
b9fc7dc5 | 9202 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 9203 | __be32 val; |
1da177e4 | 9204 | |
df259d8c MC |
9205 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
9206 | return -EINVAL; | |
9207 | ||
bc1c7567 MC |
9208 | if (tp->link_config.phy_is_low_power) |
9209 | return -EAGAIN; | |
9210 | ||
1da177e4 LT |
9211 | offset = eeprom->offset; |
9212 | len = eeprom->len; | |
9213 | eeprom->len = 0; | |
9214 | ||
9215 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9216 | ||
9217 | if (offset & 3) { | |
9218 | /* adjustments to start on required 4 byte boundary */ | |
9219 | b_offset = offset & 3; | |
9220 | b_count = 4 - b_offset; | |
9221 | if (b_count > len) { | |
9222 | /* i.e. offset=1 len=2 */ | |
9223 | b_count = len; | |
9224 | } | |
a9dc529d | 9225 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
9226 | if (ret) |
9227 | return ret; | |
1da177e4 LT |
9228 | memcpy(data, ((char*)&val) + b_offset, b_count); |
9229 | len -= b_count; | |
9230 | offset += b_count; | |
9231 | eeprom->len += b_count; | |
9232 | } | |
9233 | ||
9234 | /* read bytes upto the last 4 byte boundary */ | |
9235 | pd = &data[eeprom->len]; | |
9236 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 9237 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
9238 | if (ret) { |
9239 | eeprom->len += i; | |
9240 | return ret; | |
9241 | } | |
1da177e4 LT |
9242 | memcpy(pd + i, &val, 4); |
9243 | } | |
9244 | eeprom->len += i; | |
9245 | ||
9246 | if (len & 3) { | |
9247 | /* read last bytes not ending on 4 byte boundary */ | |
9248 | pd = &data[eeprom->len]; | |
9249 | b_count = len & 3; | |
9250 | b_offset = offset + len - b_count; | |
a9dc529d | 9251 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
9252 | if (ret) |
9253 | return ret; | |
b9fc7dc5 | 9254 | memcpy(pd, &val, b_count); |
1da177e4 LT |
9255 | eeprom->len += b_count; |
9256 | } | |
9257 | return 0; | |
9258 | } | |
9259 | ||
6aa20a22 | 9260 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
9261 | |
9262 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9263 | { | |
9264 | struct tg3 *tp = netdev_priv(dev); | |
9265 | int ret; | |
b9fc7dc5 | 9266 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 9267 | u8 *buf; |
a9dc529d | 9268 | __be32 start, end; |
1da177e4 | 9269 | |
bc1c7567 MC |
9270 | if (tp->link_config.phy_is_low_power) |
9271 | return -EAGAIN; | |
9272 | ||
df259d8c MC |
9273 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
9274 | eeprom->magic != TG3_EEPROM_MAGIC) | |
1da177e4 LT |
9275 | return -EINVAL; |
9276 | ||
9277 | offset = eeprom->offset; | |
9278 | len = eeprom->len; | |
9279 | ||
9280 | if ((b_offset = (offset & 3))) { | |
9281 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 9282 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
9283 | if (ret) |
9284 | return ret; | |
1da177e4 LT |
9285 | len += b_offset; |
9286 | offset &= ~3; | |
1c8594b4 MC |
9287 | if (len < 4) |
9288 | len = 4; | |
1da177e4 LT |
9289 | } |
9290 | ||
9291 | odd_len = 0; | |
1c8594b4 | 9292 | if (len & 3) { |
1da177e4 LT |
9293 | /* adjustments to end on required 4 byte boundary */ |
9294 | odd_len = 1; | |
9295 | len = (len + 3) & ~3; | |
a9dc529d | 9296 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
9297 | if (ret) |
9298 | return ret; | |
1da177e4 LT |
9299 | } |
9300 | ||
9301 | buf = data; | |
9302 | if (b_offset || odd_len) { | |
9303 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 9304 | if (!buf) |
1da177e4 LT |
9305 | return -ENOMEM; |
9306 | if (b_offset) | |
9307 | memcpy(buf, &start, 4); | |
9308 | if (odd_len) | |
9309 | memcpy(buf+len-4, &end, 4); | |
9310 | memcpy(buf + b_offset, data, eeprom->len); | |
9311 | } | |
9312 | ||
9313 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
9314 | ||
9315 | if (buf != data) | |
9316 | kfree(buf); | |
9317 | ||
9318 | return ret; | |
9319 | } | |
9320 | ||
9321 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9322 | { | |
b02fd9e3 MC |
9323 | struct tg3 *tp = netdev_priv(dev); |
9324 | ||
9325 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
3f0e3ad7 | 9326 | struct phy_device *phydev; |
b02fd9e3 MC |
9327 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) |
9328 | return -EAGAIN; | |
3f0e3ad7 MC |
9329 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9330 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 9331 | } |
6aa20a22 | 9332 | |
1da177e4 LT |
9333 | cmd->supported = (SUPPORTED_Autoneg); |
9334 | ||
9335 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
9336 | cmd->supported |= (SUPPORTED_1000baseT_Half | | |
9337 | SUPPORTED_1000baseT_Full); | |
9338 | ||
ef348144 | 9339 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { |
1da177e4 LT |
9340 | cmd->supported |= (SUPPORTED_100baseT_Half | |
9341 | SUPPORTED_100baseT_Full | | |
9342 | SUPPORTED_10baseT_Half | | |
9343 | SUPPORTED_10baseT_Full | | |
3bebab59 | 9344 | SUPPORTED_TP); |
ef348144 KK |
9345 | cmd->port = PORT_TP; |
9346 | } else { | |
1da177e4 | 9347 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
9348 | cmd->port = PORT_FIBRE; |
9349 | } | |
6aa20a22 | 9350 | |
1da177e4 LT |
9351 | cmd->advertising = tp->link_config.advertising; |
9352 | if (netif_running(dev)) { | |
9353 | cmd->speed = tp->link_config.active_speed; | |
9354 | cmd->duplex = tp->link_config.active_duplex; | |
9355 | } | |
882e9793 | 9356 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 9357 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
9358 | cmd->autoneg = tp->link_config.autoneg; |
9359 | cmd->maxtxpkt = 0; | |
9360 | cmd->maxrxpkt = 0; | |
9361 | return 0; | |
9362 | } | |
6aa20a22 | 9363 | |
1da177e4 LT |
9364 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
9365 | { | |
9366 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9367 | |
b02fd9e3 | 9368 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 9369 | struct phy_device *phydev; |
b02fd9e3 MC |
9370 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) |
9371 | return -EAGAIN; | |
3f0e3ad7 MC |
9372 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9373 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
9374 | } |
9375 | ||
7e5856bd MC |
9376 | if (cmd->autoneg != AUTONEG_ENABLE && |
9377 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 9378 | return -EINVAL; |
7e5856bd MC |
9379 | |
9380 | if (cmd->autoneg == AUTONEG_DISABLE && | |
9381 | cmd->duplex != DUPLEX_FULL && | |
9382 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 9383 | return -EINVAL; |
1da177e4 | 9384 | |
7e5856bd MC |
9385 | if (cmd->autoneg == AUTONEG_ENABLE) { |
9386 | u32 mask = ADVERTISED_Autoneg | | |
9387 | ADVERTISED_Pause | | |
9388 | ADVERTISED_Asym_Pause; | |
9389 | ||
9390 | if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY)) | |
9391 | mask |= ADVERTISED_1000baseT_Half | | |
9392 | ADVERTISED_1000baseT_Full; | |
9393 | ||
9394 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
9395 | mask |= ADVERTISED_100baseT_Half | | |
9396 | ADVERTISED_100baseT_Full | | |
9397 | ADVERTISED_10baseT_Half | | |
9398 | ADVERTISED_10baseT_Full | | |
9399 | ADVERTISED_TP; | |
9400 | else | |
9401 | mask |= ADVERTISED_FIBRE; | |
9402 | ||
9403 | if (cmd->advertising & ~mask) | |
9404 | return -EINVAL; | |
9405 | ||
9406 | mask &= (ADVERTISED_1000baseT_Half | | |
9407 | ADVERTISED_1000baseT_Full | | |
9408 | ADVERTISED_100baseT_Half | | |
9409 | ADVERTISED_100baseT_Full | | |
9410 | ADVERTISED_10baseT_Half | | |
9411 | ADVERTISED_10baseT_Full); | |
9412 | ||
9413 | cmd->advertising &= mask; | |
9414 | } else { | |
9415 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { | |
9416 | if (cmd->speed != SPEED_1000) | |
9417 | return -EINVAL; | |
9418 | ||
9419 | if (cmd->duplex != DUPLEX_FULL) | |
9420 | return -EINVAL; | |
9421 | } else { | |
9422 | if (cmd->speed != SPEED_100 && | |
9423 | cmd->speed != SPEED_10) | |
9424 | return -EINVAL; | |
9425 | } | |
9426 | } | |
9427 | ||
f47c11ee | 9428 | tg3_full_lock(tp, 0); |
1da177e4 LT |
9429 | |
9430 | tp->link_config.autoneg = cmd->autoneg; | |
9431 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
9432 | tp->link_config.advertising = (cmd->advertising | |
9433 | ADVERTISED_Autoneg); | |
1da177e4 LT |
9434 | tp->link_config.speed = SPEED_INVALID; |
9435 | tp->link_config.duplex = DUPLEX_INVALID; | |
9436 | } else { | |
9437 | tp->link_config.advertising = 0; | |
9438 | tp->link_config.speed = cmd->speed; | |
9439 | tp->link_config.duplex = cmd->duplex; | |
b02fd9e3 | 9440 | } |
6aa20a22 | 9441 | |
24fcad6b MC |
9442 | tp->link_config.orig_speed = tp->link_config.speed; |
9443 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
9444 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
9445 | ||
1da177e4 LT |
9446 | if (netif_running(dev)) |
9447 | tg3_setup_phy(tp, 1); | |
9448 | ||
f47c11ee | 9449 | tg3_full_unlock(tp); |
6aa20a22 | 9450 | |
1da177e4 LT |
9451 | return 0; |
9452 | } | |
6aa20a22 | 9453 | |
1da177e4 LT |
9454 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
9455 | { | |
9456 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9457 | |
1da177e4 LT |
9458 | strcpy(info->driver, DRV_MODULE_NAME); |
9459 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 9460 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
9461 | strcpy(info->bus_info, pci_name(tp->pdev)); |
9462 | } | |
6aa20a22 | 9463 | |
1da177e4 LT |
9464 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
9465 | { | |
9466 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9467 | |
12dac075 RW |
9468 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
9469 | device_can_wakeup(&tp->pdev->dev)) | |
a85feb8c GZ |
9470 | wol->supported = WAKE_MAGIC; |
9471 | else | |
9472 | wol->supported = 0; | |
1da177e4 | 9473 | wol->wolopts = 0; |
05ac4cb7 MC |
9474 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && |
9475 | device_can_wakeup(&tp->pdev->dev)) | |
1da177e4 LT |
9476 | wol->wolopts = WAKE_MAGIC; |
9477 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
9478 | } | |
6aa20a22 | 9479 | |
1da177e4 LT |
9480 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
9481 | { | |
9482 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 9483 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 9484 | |
1da177e4 LT |
9485 | if (wol->wolopts & ~WAKE_MAGIC) |
9486 | return -EINVAL; | |
9487 | if ((wol->wolopts & WAKE_MAGIC) && | |
12dac075 | 9488 | !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 9489 | return -EINVAL; |
6aa20a22 | 9490 | |
f47c11ee | 9491 | spin_lock_bh(&tp->lock); |
12dac075 | 9492 | if (wol->wolopts & WAKE_MAGIC) { |
1da177e4 | 9493 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
12dac075 RW |
9494 | device_set_wakeup_enable(dp, true); |
9495 | } else { | |
1da177e4 | 9496 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; |
12dac075 RW |
9497 | device_set_wakeup_enable(dp, false); |
9498 | } | |
f47c11ee | 9499 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 9500 | |
1da177e4 LT |
9501 | return 0; |
9502 | } | |
6aa20a22 | 9503 | |
1da177e4 LT |
9504 | static u32 tg3_get_msglevel(struct net_device *dev) |
9505 | { | |
9506 | struct tg3 *tp = netdev_priv(dev); | |
9507 | return tp->msg_enable; | |
9508 | } | |
6aa20a22 | 9509 | |
1da177e4 LT |
9510 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
9511 | { | |
9512 | struct tg3 *tp = netdev_priv(dev); | |
9513 | tp->msg_enable = value; | |
9514 | } | |
6aa20a22 | 9515 | |
1da177e4 LT |
9516 | static int tg3_set_tso(struct net_device *dev, u32 value) |
9517 | { | |
9518 | struct tg3 *tp = netdev_priv(dev); | |
9519 | ||
9520 | if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
9521 | if (value) | |
9522 | return -EINVAL; | |
9523 | return 0; | |
9524 | } | |
027455ad | 9525 | if ((dev->features & NETIF_F_IPV6_CSUM) && |
e849cdc3 MC |
9526 | ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || |
9527 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) { | |
9936bcf6 | 9528 | if (value) { |
b0026624 | 9529 | dev->features |= NETIF_F_TSO6; |
e849cdc3 MC |
9530 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
9531 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
9532 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
9533 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 9534 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
e849cdc3 | 9535 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
9936bcf6 MC |
9536 | dev->features |= NETIF_F_TSO_ECN; |
9537 | } else | |
9538 | dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); | |
b0026624 | 9539 | } |
1da177e4 LT |
9540 | return ethtool_op_set_tso(dev, value); |
9541 | } | |
6aa20a22 | 9542 | |
1da177e4 LT |
9543 | static int tg3_nway_reset(struct net_device *dev) |
9544 | { | |
9545 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 9546 | int r; |
6aa20a22 | 9547 | |
1da177e4 LT |
9548 | if (!netif_running(dev)) |
9549 | return -EAGAIN; | |
9550 | ||
c94e3941 MC |
9551 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) |
9552 | return -EINVAL; | |
9553 | ||
b02fd9e3 MC |
9554 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
9555 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
9556 | return -EAGAIN; | |
3f0e3ad7 | 9557 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
9558 | } else { |
9559 | u32 bmcr; | |
9560 | ||
9561 | spin_lock_bh(&tp->lock); | |
9562 | r = -EINVAL; | |
9563 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
9564 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
9565 | ((bmcr & BMCR_ANENABLE) || | |
9566 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) { | |
9567 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | | |
9568 | BMCR_ANENABLE); | |
9569 | r = 0; | |
9570 | } | |
9571 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 9572 | } |
6aa20a22 | 9573 | |
1da177e4 LT |
9574 | return r; |
9575 | } | |
6aa20a22 | 9576 | |
1da177e4 LT |
9577 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
9578 | { | |
9579 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9580 | |
1da177e4 LT |
9581 | ering->rx_max_pending = TG3_RX_RING_SIZE - 1; |
9582 | ering->rx_mini_max_pending = 0; | |
4f81c32b MC |
9583 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
9584 | ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1; | |
9585 | else | |
9586 | ering->rx_jumbo_max_pending = 0; | |
9587 | ||
9588 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
9589 | |
9590 | ering->rx_pending = tp->rx_pending; | |
9591 | ering->rx_mini_pending = 0; | |
4f81c32b MC |
9592 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
9593 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
9594 | else | |
9595 | ering->rx_jumbo_pending = 0; | |
9596 | ||
f3f3f27e | 9597 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 9598 | } |
6aa20a22 | 9599 | |
1da177e4 LT |
9600 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
9601 | { | |
9602 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 9603 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 9604 | |
1da177e4 LT |
9605 | if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || |
9606 | (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || | |
bc3a9254 MC |
9607 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
9608 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
7f62ad5d | 9609 | ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && |
bc3a9254 | 9610 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 9611 | return -EINVAL; |
6aa20a22 | 9612 | |
bbe832c0 | 9613 | if (netif_running(dev)) { |
b02fd9e3 | 9614 | tg3_phy_stop(tp); |
1da177e4 | 9615 | tg3_netif_stop(tp); |
bbe832c0 MC |
9616 | irq_sync = 1; |
9617 | } | |
1da177e4 | 9618 | |
bbe832c0 | 9619 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 9620 | |
1da177e4 LT |
9621 | tp->rx_pending = ering->rx_pending; |
9622 | ||
9623 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | |
9624 | tp->rx_pending > 63) | |
9625 | tp->rx_pending = 63; | |
9626 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd MC |
9627 | |
9628 | for (i = 0; i < TG3_IRQ_MAX_VECS; i++) | |
9629 | tp->napi[i].tx_pending = ering->tx_pending; | |
1da177e4 LT |
9630 | |
9631 | if (netif_running(dev)) { | |
944d980e | 9632 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
9633 | err = tg3_restart_hw(tp, 1); |
9634 | if (!err) | |
9635 | tg3_netif_start(tp); | |
1da177e4 LT |
9636 | } |
9637 | ||
f47c11ee | 9638 | tg3_full_unlock(tp); |
6aa20a22 | 9639 | |
b02fd9e3 MC |
9640 | if (irq_sync && !err) |
9641 | tg3_phy_start(tp); | |
9642 | ||
b9ec6c1b | 9643 | return err; |
1da177e4 | 9644 | } |
6aa20a22 | 9645 | |
1da177e4 LT |
9646 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
9647 | { | |
9648 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9649 | |
1da177e4 | 9650 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; |
8d018621 | 9651 | |
e18ce346 | 9652 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
9653 | epause->rx_pause = 1; |
9654 | else | |
9655 | epause->rx_pause = 0; | |
9656 | ||
e18ce346 | 9657 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
9658 | epause->tx_pause = 1; |
9659 | else | |
9660 | epause->tx_pause = 0; | |
1da177e4 | 9661 | } |
6aa20a22 | 9662 | |
1da177e4 LT |
9663 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
9664 | { | |
9665 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 9666 | int err = 0; |
6aa20a22 | 9667 | |
b02fd9e3 MC |
9668 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
9669 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
9670 | return -EAGAIN; | |
1da177e4 | 9671 | |
b02fd9e3 MC |
9672 | if (epause->autoneg) { |
9673 | u32 newadv; | |
9674 | struct phy_device *phydev; | |
f47c11ee | 9675 | |
3f0e3ad7 | 9676 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
1da177e4 | 9677 | |
b02fd9e3 MC |
9678 | if (epause->rx_pause) { |
9679 | if (epause->tx_pause) | |
9680 | newadv = ADVERTISED_Pause; | |
9681 | else | |
9682 | newadv = ADVERTISED_Pause | | |
9683 | ADVERTISED_Asym_Pause; | |
9684 | } else if (epause->tx_pause) { | |
9685 | newadv = ADVERTISED_Asym_Pause; | |
9686 | } else | |
9687 | newadv = 0; | |
9688 | ||
9689 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
9690 | u32 oldadv = phydev->advertising & | |
9691 | (ADVERTISED_Pause | | |
9692 | ADVERTISED_Asym_Pause); | |
9693 | if (oldadv != newadv) { | |
9694 | phydev->advertising &= | |
9695 | ~(ADVERTISED_Pause | | |
9696 | ADVERTISED_Asym_Pause); | |
9697 | phydev->advertising |= newadv; | |
9698 | err = phy_start_aneg(phydev); | |
9699 | } | |
9700 | } else { | |
9701 | tp->link_config.advertising &= | |
9702 | ~(ADVERTISED_Pause | | |
9703 | ADVERTISED_Asym_Pause); | |
9704 | tp->link_config.advertising |= newadv; | |
9705 | } | |
9706 | } else { | |
9707 | if (epause->rx_pause) | |
e18ce346 | 9708 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 9709 | else |
e18ce346 | 9710 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
f47c11ee | 9711 | |
b02fd9e3 | 9712 | if (epause->tx_pause) |
e18ce346 | 9713 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 9714 | else |
e18ce346 | 9715 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
9716 | |
9717 | if (netif_running(dev)) | |
9718 | tg3_setup_flow_control(tp, 0, 0); | |
9719 | } | |
9720 | } else { | |
9721 | int irq_sync = 0; | |
9722 | ||
9723 | if (netif_running(dev)) { | |
9724 | tg3_netif_stop(tp); | |
9725 | irq_sync = 1; | |
9726 | } | |
9727 | ||
9728 | tg3_full_lock(tp, irq_sync); | |
9729 | ||
9730 | if (epause->autoneg) | |
9731 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
9732 | else | |
9733 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
9734 | if (epause->rx_pause) | |
e18ce346 | 9735 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 9736 | else |
e18ce346 | 9737 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 9738 | if (epause->tx_pause) |
e18ce346 | 9739 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 9740 | else |
e18ce346 | 9741 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
9742 | |
9743 | if (netif_running(dev)) { | |
9744 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9745 | err = tg3_restart_hw(tp, 1); | |
9746 | if (!err) | |
9747 | tg3_netif_start(tp); | |
9748 | } | |
9749 | ||
9750 | tg3_full_unlock(tp); | |
9751 | } | |
6aa20a22 | 9752 | |
b9ec6c1b | 9753 | return err; |
1da177e4 | 9754 | } |
6aa20a22 | 9755 | |
1da177e4 LT |
9756 | static u32 tg3_get_rx_csum(struct net_device *dev) |
9757 | { | |
9758 | struct tg3 *tp = netdev_priv(dev); | |
9759 | return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0; | |
9760 | } | |
6aa20a22 | 9761 | |
1da177e4 LT |
9762 | static int tg3_set_rx_csum(struct net_device *dev, u32 data) |
9763 | { | |
9764 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9765 | |
1da177e4 LT |
9766 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
9767 | if (data != 0) | |
9768 | return -EINVAL; | |
9769 | return 0; | |
9770 | } | |
6aa20a22 | 9771 | |
f47c11ee | 9772 | spin_lock_bh(&tp->lock); |
1da177e4 LT |
9773 | if (data) |
9774 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
9775 | else | |
9776 | tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; | |
f47c11ee | 9777 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 9778 | |
1da177e4 LT |
9779 | return 0; |
9780 | } | |
6aa20a22 | 9781 | |
1da177e4 LT |
9782 | static int tg3_set_tx_csum(struct net_device *dev, u32 data) |
9783 | { | |
9784 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9785 | |
1da177e4 LT |
9786 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
9787 | if (data != 0) | |
9788 | return -EINVAL; | |
9789 | return 0; | |
9790 | } | |
6aa20a22 | 9791 | |
321d32a0 | 9792 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
6460d948 | 9793 | ethtool_op_set_tx_ipv6_csum(dev, data); |
1da177e4 | 9794 | else |
9c27dbdf | 9795 | ethtool_op_set_tx_csum(dev, data); |
1da177e4 LT |
9796 | |
9797 | return 0; | |
9798 | } | |
9799 | ||
b9f2c044 | 9800 | static int tg3_get_sset_count (struct net_device *dev, int sset) |
1da177e4 | 9801 | { |
b9f2c044 JG |
9802 | switch (sset) { |
9803 | case ETH_SS_TEST: | |
9804 | return TG3_NUM_TEST; | |
9805 | case ETH_SS_STATS: | |
9806 | return TG3_NUM_STATS; | |
9807 | default: | |
9808 | return -EOPNOTSUPP; | |
9809 | } | |
4cafd3f5 MC |
9810 | } |
9811 | ||
1da177e4 LT |
9812 | static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf) |
9813 | { | |
9814 | switch (stringset) { | |
9815 | case ETH_SS_STATS: | |
9816 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
9817 | break; | |
4cafd3f5 MC |
9818 | case ETH_SS_TEST: |
9819 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
9820 | break; | |
1da177e4 LT |
9821 | default: |
9822 | WARN_ON(1); /* we need a WARN() */ | |
9823 | break; | |
9824 | } | |
9825 | } | |
9826 | ||
4009a93d MC |
9827 | static int tg3_phys_id(struct net_device *dev, u32 data) |
9828 | { | |
9829 | struct tg3 *tp = netdev_priv(dev); | |
9830 | int i; | |
9831 | ||
9832 | if (!netif_running(tp->dev)) | |
9833 | return -EAGAIN; | |
9834 | ||
9835 | if (data == 0) | |
759afc31 | 9836 | data = UINT_MAX / 2; |
4009a93d MC |
9837 | |
9838 | for (i = 0; i < (data * 2); i++) { | |
9839 | if ((i % 2) == 0) | |
9840 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
9841 | LED_CTRL_1000MBPS_ON | | |
9842 | LED_CTRL_100MBPS_ON | | |
9843 | LED_CTRL_10MBPS_ON | | |
9844 | LED_CTRL_TRAFFIC_OVERRIDE | | |
9845 | LED_CTRL_TRAFFIC_BLINK | | |
9846 | LED_CTRL_TRAFFIC_LED); | |
6aa20a22 | 9847 | |
4009a93d MC |
9848 | else |
9849 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
9850 | LED_CTRL_TRAFFIC_OVERRIDE); | |
9851 | ||
9852 | if (msleep_interruptible(500)) | |
9853 | break; | |
9854 | } | |
9855 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
9856 | return 0; | |
9857 | } | |
9858 | ||
1da177e4 LT |
9859 | static void tg3_get_ethtool_stats (struct net_device *dev, |
9860 | struct ethtool_stats *estats, u64 *tmp_stats) | |
9861 | { | |
9862 | struct tg3 *tp = netdev_priv(dev); | |
9863 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
9864 | } | |
9865 | ||
566f86ad | 9866 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
9867 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
9868 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
9869 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
b16250e3 MC |
9870 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
9871 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
9872 | |
9873 | static int tg3_test_nvram(struct tg3 *tp) | |
9874 | { | |
b9fc7dc5 | 9875 | u32 csum, magic; |
a9dc529d | 9876 | __be32 *buf; |
ab0049b4 | 9877 | int i, j, k, err = 0, size; |
566f86ad | 9878 | |
df259d8c MC |
9879 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
9880 | return 0; | |
9881 | ||
e4f34110 | 9882 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
9883 | return -EIO; |
9884 | ||
1b27777a MC |
9885 | if (magic == TG3_EEPROM_MAGIC) |
9886 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 9887 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
9888 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
9889 | TG3_EEPROM_SB_FORMAT_1) { | |
9890 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
9891 | case TG3_EEPROM_SB_REVISION_0: | |
9892 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
9893 | break; | |
9894 | case TG3_EEPROM_SB_REVISION_2: | |
9895 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
9896 | break; | |
9897 | case TG3_EEPROM_SB_REVISION_3: | |
9898 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
9899 | break; | |
9900 | default: | |
9901 | return 0; | |
9902 | } | |
9903 | } else | |
1b27777a | 9904 | return 0; |
b16250e3 MC |
9905 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
9906 | size = NVRAM_SELFBOOT_HW_SIZE; | |
9907 | else | |
1b27777a MC |
9908 | return -EIO; |
9909 | ||
9910 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
9911 | if (buf == NULL) |
9912 | return -ENOMEM; | |
9913 | ||
1b27777a MC |
9914 | err = -EIO; |
9915 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
9916 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
9917 | if (err) | |
566f86ad | 9918 | break; |
566f86ad | 9919 | } |
1b27777a | 9920 | if (i < size) |
566f86ad MC |
9921 | goto out; |
9922 | ||
1b27777a | 9923 | /* Selfboot format */ |
a9dc529d | 9924 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 9925 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 9926 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
9927 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
9928 | ||
b9fc7dc5 | 9929 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
9930 | TG3_EEPROM_SB_REVISION_2) { |
9931 | /* For rev 2, the csum doesn't include the MBA. */ | |
9932 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
9933 | csum8 += buf8[i]; | |
9934 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
9935 | csum8 += buf8[i]; | |
9936 | } else { | |
9937 | for (i = 0; i < size; i++) | |
9938 | csum8 += buf8[i]; | |
9939 | } | |
1b27777a | 9940 | |
ad96b485 AB |
9941 | if (csum8 == 0) { |
9942 | err = 0; | |
9943 | goto out; | |
9944 | } | |
9945 | ||
9946 | err = -EIO; | |
9947 | goto out; | |
1b27777a | 9948 | } |
566f86ad | 9949 | |
b9fc7dc5 | 9950 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
9951 | TG3_EEPROM_MAGIC_HW) { |
9952 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 9953 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 9954 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
9955 | |
9956 | /* Separate the parity bits and the data bytes. */ | |
9957 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
9958 | if ((i == 0) || (i == 8)) { | |
9959 | int l; | |
9960 | u8 msk; | |
9961 | ||
9962 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
9963 | parity[k++] = buf8[i] & msk; | |
9964 | i++; | |
9965 | } | |
9966 | else if (i == 16) { | |
9967 | int l; | |
9968 | u8 msk; | |
9969 | ||
9970 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
9971 | parity[k++] = buf8[i] & msk; | |
9972 | i++; | |
9973 | ||
9974 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
9975 | parity[k++] = buf8[i] & msk; | |
9976 | i++; | |
9977 | } | |
9978 | data[j++] = buf8[i]; | |
9979 | } | |
9980 | ||
9981 | err = -EIO; | |
9982 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
9983 | u8 hw8 = hweight8(data[i]); | |
9984 | ||
9985 | if ((hw8 & 0x1) && parity[i]) | |
9986 | goto out; | |
9987 | else if (!(hw8 & 0x1) && !parity[i]) | |
9988 | goto out; | |
9989 | } | |
9990 | err = 0; | |
9991 | goto out; | |
9992 | } | |
9993 | ||
566f86ad MC |
9994 | /* Bootstrap checksum at offset 0x10 */ |
9995 | csum = calc_crc((unsigned char *) buf, 0x10); | |
a9dc529d | 9996 | if (csum != be32_to_cpu(buf[0x10/4])) |
566f86ad MC |
9997 | goto out; |
9998 | ||
9999 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10000 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
a9dc529d MC |
10001 | if (csum != be32_to_cpu(buf[0xfc/4])) |
10002 | goto out; | |
566f86ad MC |
10003 | |
10004 | err = 0; | |
10005 | ||
10006 | out: | |
10007 | kfree(buf); | |
10008 | return err; | |
10009 | } | |
10010 | ||
ca43007a MC |
10011 | #define TG3_SERDES_TIMEOUT_SEC 2 |
10012 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10013 | ||
10014 | static int tg3_test_link(struct tg3 *tp) | |
10015 | { | |
10016 | int i, max; | |
10017 | ||
10018 | if (!netif_running(tp->dev)) | |
10019 | return -ENODEV; | |
10020 | ||
4c987487 | 10021 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) |
ca43007a MC |
10022 | max = TG3_SERDES_TIMEOUT_SEC; |
10023 | else | |
10024 | max = TG3_COPPER_TIMEOUT_SEC; | |
10025 | ||
10026 | for (i = 0; i < max; i++) { | |
10027 | if (netif_carrier_ok(tp->dev)) | |
10028 | return 0; | |
10029 | ||
10030 | if (msleep_interruptible(1000)) | |
10031 | break; | |
10032 | } | |
10033 | ||
10034 | return -EIO; | |
10035 | } | |
10036 | ||
a71116d1 | 10037 | /* Only test the commonly used registers */ |
30ca3e37 | 10038 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 10039 | { |
b16250e3 | 10040 | int i, is_5705, is_5750; |
a71116d1 MC |
10041 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
10042 | static struct { | |
10043 | u16 offset; | |
10044 | u16 flags; | |
10045 | #define TG3_FL_5705 0x1 | |
10046 | #define TG3_FL_NOT_5705 0x2 | |
10047 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 10048 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
10049 | u32 read_mask; |
10050 | u32 write_mask; | |
10051 | } reg_tbl[] = { | |
10052 | /* MAC Control Registers */ | |
10053 | { MAC_MODE, TG3_FL_NOT_5705, | |
10054 | 0x00000000, 0x00ef6f8c }, | |
10055 | { MAC_MODE, TG3_FL_5705, | |
10056 | 0x00000000, 0x01ef6b8c }, | |
10057 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10058 | 0x03800107, 0x00000000 }, | |
10059 | { MAC_STATUS, TG3_FL_5705, | |
10060 | 0x03800100, 0x00000000 }, | |
10061 | { MAC_ADDR_0_HIGH, 0x0000, | |
10062 | 0x00000000, 0x0000ffff }, | |
10063 | { MAC_ADDR_0_LOW, 0x0000, | |
10064 | 0x00000000, 0xffffffff }, | |
10065 | { MAC_RX_MTU_SIZE, 0x0000, | |
10066 | 0x00000000, 0x0000ffff }, | |
10067 | { MAC_TX_MODE, 0x0000, | |
10068 | 0x00000000, 0x00000070 }, | |
10069 | { MAC_TX_LENGTHS, 0x0000, | |
10070 | 0x00000000, 0x00003fff }, | |
10071 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10072 | 0x00000000, 0x000007fc }, | |
10073 | { MAC_RX_MODE, TG3_FL_5705, | |
10074 | 0x00000000, 0x000007dc }, | |
10075 | { MAC_HASH_REG_0, 0x0000, | |
10076 | 0x00000000, 0xffffffff }, | |
10077 | { MAC_HASH_REG_1, 0x0000, | |
10078 | 0x00000000, 0xffffffff }, | |
10079 | { MAC_HASH_REG_2, 0x0000, | |
10080 | 0x00000000, 0xffffffff }, | |
10081 | { MAC_HASH_REG_3, 0x0000, | |
10082 | 0x00000000, 0xffffffff }, | |
10083 | ||
10084 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10085 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10086 | 0x00000000, 0xffffffff }, | |
10087 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10088 | 0x00000000, 0xffffffff }, | |
10089 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10090 | 0x00000000, 0x00000003 }, | |
10091 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10092 | 0x00000000, 0xffffffff }, | |
10093 | { RCVDBDI_STD_BD+0, 0x0000, | |
10094 | 0x00000000, 0xffffffff }, | |
10095 | { RCVDBDI_STD_BD+4, 0x0000, | |
10096 | 0x00000000, 0xffffffff }, | |
10097 | { RCVDBDI_STD_BD+8, 0x0000, | |
10098 | 0x00000000, 0xffff0002 }, | |
10099 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10100 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10101 | |
a71116d1 MC |
10102 | /* Receive BD Initiator Control Registers. */ |
10103 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10104 | 0x00000000, 0xffffffff }, | |
10105 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10106 | 0x00000000, 0x000003ff }, | |
10107 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10108 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10109 | |
a71116d1 MC |
10110 | /* Host Coalescing Control Registers. */ |
10111 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10112 | 0x00000000, 0x00000004 }, | |
10113 | { HOSTCC_MODE, TG3_FL_5705, | |
10114 | 0x00000000, 0x000000f6 }, | |
10115 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10116 | 0x00000000, 0xffffffff }, | |
10117 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10118 | 0x00000000, 0x000003ff }, | |
10119 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10120 | 0x00000000, 0xffffffff }, | |
10121 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10122 | 0x00000000, 0x000003ff }, | |
10123 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10124 | 0x00000000, 0xffffffff }, | |
10125 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10126 | 0x00000000, 0x000000ff }, | |
10127 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10128 | 0x00000000, 0xffffffff }, | |
10129 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10130 | 0x00000000, 0x000000ff }, | |
10131 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10132 | 0x00000000, 0xffffffff }, | |
10133 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10134 | 0x00000000, 0xffffffff }, | |
10135 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10136 | 0x00000000, 0xffffffff }, | |
10137 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10138 | 0x00000000, 0x000000ff }, | |
10139 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10140 | 0x00000000, 0xffffffff }, | |
10141 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10142 | 0x00000000, 0x000000ff }, | |
10143 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10144 | 0x00000000, 0xffffffff }, | |
10145 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10146 | 0x00000000, 0xffffffff }, | |
10147 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10148 | 0x00000000, 0xffffffff }, | |
10149 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10150 | 0x00000000, 0xffffffff }, | |
10151 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10152 | 0x00000000, 0xffffffff }, | |
10153 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10154 | 0xffffffff, 0x00000000 }, | |
10155 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10156 | 0xffffffff, 0x00000000 }, | |
10157 | ||
10158 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 10159 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 10160 | 0x00000000, 0x007fff80 }, |
b16250e3 | 10161 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
10162 | 0x00000000, 0x007fffff }, |
10163 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10164 | 0x00000000, 0x0000003f }, | |
10165 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10166 | 0x00000000, 0x000001ff }, | |
10167 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10168 | 0x00000000, 0x000001ff }, | |
10169 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10170 | 0xffffffff, 0x00000000 }, | |
10171 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10172 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 10173 | |
a71116d1 MC |
10174 | /* Mailbox Registers */ |
10175 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10176 | 0x00000000, 0x000001ff }, | |
10177 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10178 | 0x00000000, 0x000001ff }, | |
10179 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10180 | 0x00000000, 0x000007ff }, | |
10181 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10182 | 0x00000000, 0x000001ff }, | |
10183 | ||
10184 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10185 | }; | |
10186 | ||
b16250e3 MC |
10187 | is_5705 = is_5750 = 0; |
10188 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
a71116d1 | 10189 | is_5705 = 1; |
b16250e3 MC |
10190 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
10191 | is_5750 = 1; | |
10192 | } | |
a71116d1 MC |
10193 | |
10194 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10195 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
10196 | continue; | |
10197 | ||
10198 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
10199 | continue; | |
10200 | ||
10201 | if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
10202 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
10203 | continue; | |
10204 | ||
b16250e3 MC |
10205 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
10206 | continue; | |
10207 | ||
a71116d1 MC |
10208 | offset = (u32) reg_tbl[i].offset; |
10209 | read_mask = reg_tbl[i].read_mask; | |
10210 | write_mask = reg_tbl[i].write_mask; | |
10211 | ||
10212 | /* Save the original register content */ | |
10213 | save_val = tr32(offset); | |
10214 | ||
10215 | /* Determine the read-only value. */ | |
10216 | read_val = save_val & read_mask; | |
10217 | ||
10218 | /* Write zero to the register, then make sure the read-only bits | |
10219 | * are not changed and the read/write bits are all zeros. | |
10220 | */ | |
10221 | tw32(offset, 0); | |
10222 | ||
10223 | val = tr32(offset); | |
10224 | ||
10225 | /* Test the read-only and read/write bits. */ | |
10226 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
10227 | goto out; | |
10228 | ||
10229 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
10230 | * make sure the read-only bits are not changed and the | |
10231 | * read/write bits are all ones. | |
10232 | */ | |
10233 | tw32(offset, read_mask | write_mask); | |
10234 | ||
10235 | val = tr32(offset); | |
10236 | ||
10237 | /* Test the read-only bits. */ | |
10238 | if ((val & read_mask) != read_val) | |
10239 | goto out; | |
10240 | ||
10241 | /* Test the read/write bits. */ | |
10242 | if ((val & write_mask) != write_mask) | |
10243 | goto out; | |
10244 | ||
10245 | tw32(offset, save_val); | |
10246 | } | |
10247 | ||
10248 | return 0; | |
10249 | ||
10250 | out: | |
9f88f29f MC |
10251 | if (netif_msg_hw(tp)) |
10252 | printk(KERN_ERR PFX "Register test failed at offset %x\n", | |
10253 | offset); | |
a71116d1 MC |
10254 | tw32(offset, save_val); |
10255 | return -EIO; | |
10256 | } | |
10257 | ||
7942e1db MC |
10258 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
10259 | { | |
f71e1309 | 10260 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
10261 | int i; |
10262 | u32 j; | |
10263 | ||
e9edda69 | 10264 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
10265 | for (j = 0; j < len; j += 4) { |
10266 | u32 val; | |
10267 | ||
10268 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
10269 | tg3_read_mem(tp, offset + j, &val); | |
10270 | if (val != test_pattern[i]) | |
10271 | return -EIO; | |
10272 | } | |
10273 | } | |
10274 | return 0; | |
10275 | } | |
10276 | ||
10277 | static int tg3_test_memory(struct tg3 *tp) | |
10278 | { | |
10279 | static struct mem_entry { | |
10280 | u32 offset; | |
10281 | u32 len; | |
10282 | } mem_tbl_570x[] = { | |
38690194 | 10283 | { 0x00000000, 0x00b50}, |
7942e1db MC |
10284 | { 0x00002000, 0x1c000}, |
10285 | { 0xffffffff, 0x00000} | |
10286 | }, mem_tbl_5705[] = { | |
10287 | { 0x00000100, 0x0000c}, | |
10288 | { 0x00000200, 0x00008}, | |
7942e1db MC |
10289 | { 0x00004000, 0x00800}, |
10290 | { 0x00006000, 0x01000}, | |
10291 | { 0x00008000, 0x02000}, | |
10292 | { 0x00010000, 0x0e000}, | |
10293 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
10294 | }, mem_tbl_5755[] = { |
10295 | { 0x00000200, 0x00008}, | |
10296 | { 0x00004000, 0x00800}, | |
10297 | { 0x00006000, 0x00800}, | |
10298 | { 0x00008000, 0x02000}, | |
10299 | { 0x00010000, 0x0c000}, | |
10300 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
10301 | }, mem_tbl_5906[] = { |
10302 | { 0x00000200, 0x00008}, | |
10303 | { 0x00004000, 0x00400}, | |
10304 | { 0x00006000, 0x00400}, | |
10305 | { 0x00008000, 0x01000}, | |
10306 | { 0x00010000, 0x01000}, | |
10307 | { 0xffffffff, 0x00000} | |
7942e1db MC |
10308 | }; |
10309 | struct mem_entry *mem_tbl; | |
10310 | int err = 0; | |
10311 | int i; | |
10312 | ||
321d32a0 MC |
10313 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
10314 | mem_tbl = mem_tbl_5755; | |
10315 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
10316 | mem_tbl = mem_tbl_5906; | |
10317 | else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
10318 | mem_tbl = mem_tbl_5705; | |
10319 | else | |
7942e1db MC |
10320 | mem_tbl = mem_tbl_570x; |
10321 | ||
10322 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
10323 | if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset, | |
10324 | mem_tbl[i].len)) != 0) | |
10325 | break; | |
10326 | } | |
6aa20a22 | 10327 | |
7942e1db MC |
10328 | return err; |
10329 | } | |
10330 | ||
9f40dead MC |
10331 | #define TG3_MAC_LOOPBACK 0 |
10332 | #define TG3_PHY_LOOPBACK 1 | |
10333 | ||
10334 | static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |
c76949a6 | 10335 | { |
9f40dead | 10336 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
fd2ce37f | 10337 | u32 desc_idx, coal_now; |
c76949a6 MC |
10338 | struct sk_buff *skb, *rx_skb; |
10339 | u8 *tx_data; | |
10340 | dma_addr_t map; | |
10341 | int num_pkts, tx_len, rx_len, i, err; | |
10342 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 10343 | struct tg3_napi *tnapi, *rnapi; |
21f581a5 | 10344 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
c76949a6 | 10345 | |
0c1d0e2b MC |
10346 | if (tp->irq_cnt > 1) { |
10347 | tnapi = &tp->napi[1]; | |
10348 | rnapi = &tp->napi[1]; | |
10349 | } else { | |
10350 | tnapi = &tp->napi[0]; | |
10351 | rnapi = &tp->napi[0]; | |
10352 | } | |
fd2ce37f | 10353 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 10354 | |
9f40dead | 10355 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
c94e3941 MC |
10356 | /* HW errata - mac loopback fails in some cases on 5780. |
10357 | * Normal traffic and PHY loopback are not affected by | |
10358 | * errata. | |
10359 | */ | |
10360 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) | |
10361 | return 0; | |
10362 | ||
9f40dead | 10363 | mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) | |
e8f3f6ca MC |
10364 | MAC_MODE_PORT_INT_LPBACK; |
10365 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
10366 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
3f7045c1 MC |
10367 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) |
10368 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
10369 | else | |
10370 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9f40dead MC |
10371 | tw32(MAC_MODE, mac_mode); |
10372 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | |
3f7045c1 MC |
10373 | u32 val; |
10374 | ||
7f97a4bd MC |
10375 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
10376 | tg3_phy_fet_toggle_apd(tp, false); | |
5d64ad34 MC |
10377 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
10378 | } else | |
10379 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 10380 | |
9ef8ca99 MC |
10381 | tg3_phy_toggle_automdix(tp, 0); |
10382 | ||
3f7045c1 | 10383 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 10384 | udelay(40); |
5d64ad34 | 10385 | |
e8f3f6ca | 10386 | mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; |
7f97a4bd MC |
10387 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
10388 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
10389 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800); | |
5d64ad34 MC |
10390 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
10391 | } else | |
10392 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 10393 | |
c94e3941 MC |
10394 | /* reset to prevent losing 1st rx packet intermittently */ |
10395 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
10396 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
10397 | udelay(10); | |
10398 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
10399 | } | |
e8f3f6ca MC |
10400 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
10401 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) | |
10402 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
10403 | else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) | |
10404 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
ff18ff02 MC |
10405 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
10406 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
10407 | } | |
9f40dead | 10408 | tw32(MAC_MODE, mac_mode); |
9f40dead MC |
10409 | } |
10410 | else | |
10411 | return -EINVAL; | |
c76949a6 MC |
10412 | |
10413 | err = -EIO; | |
10414 | ||
c76949a6 | 10415 | tx_len = 1514; |
a20e9c62 | 10416 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
10417 | if (!skb) |
10418 | return -ENOMEM; | |
10419 | ||
c76949a6 MC |
10420 | tx_data = skb_put(skb, tx_len); |
10421 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
10422 | memset(tx_data + 6, 0x0, 8); | |
10423 | ||
10424 | tw32(MAC_RX_MTU_SIZE, tx_len + 4); | |
10425 | ||
10426 | for (i = 14; i < tx_len; i++) | |
10427 | tx_data[i] = (u8) (i & 0xff); | |
10428 | ||
a21771dd MC |
10429 | if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) { |
10430 | dev_kfree_skb(skb); | |
10431 | return -EIO; | |
10432 | } | |
c76949a6 MC |
10433 | |
10434 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 10435 | rnapi->coal_now); |
c76949a6 MC |
10436 | |
10437 | udelay(10); | |
10438 | ||
898a56f8 | 10439 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 10440 | |
c76949a6 MC |
10441 | num_pkts = 0; |
10442 | ||
a21771dd MC |
10443 | tg3_set_txd(tnapi, tnapi->tx_prod, |
10444 | skb_shinfo(skb)->dma_head, tx_len, 0, 1); | |
c76949a6 | 10445 | |
f3f3f27e | 10446 | tnapi->tx_prod++; |
c76949a6 MC |
10447 | num_pkts++; |
10448 | ||
f3f3f27e MC |
10449 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
10450 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
10451 | |
10452 | udelay(10); | |
10453 | ||
303fc921 MC |
10454 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
10455 | for (i = 0; i < 35; i++) { | |
c76949a6 | 10456 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 10457 | coal_now); |
c76949a6 MC |
10458 | |
10459 | udelay(10); | |
10460 | ||
898a56f8 MC |
10461 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
10462 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 10463 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
10464 | (rx_idx == (rx_start_idx + num_pkts))) |
10465 | break; | |
10466 | } | |
10467 | ||
a21771dd | 10468 | skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE); |
c76949a6 MC |
10469 | dev_kfree_skb(skb); |
10470 | ||
f3f3f27e | 10471 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
10472 | goto out; |
10473 | ||
10474 | if (rx_idx != rx_start_idx + num_pkts) | |
10475 | goto out; | |
10476 | ||
72334482 | 10477 | desc = &rnapi->rx_rcb[rx_start_idx]; |
c76949a6 MC |
10478 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
10479 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
10480 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
10481 | goto out; | |
10482 | ||
10483 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
10484 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
10485 | goto out; | |
10486 | ||
10487 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; | |
10488 | if (rx_len != tx_len) | |
10489 | goto out; | |
10490 | ||
21f581a5 | 10491 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; |
c76949a6 | 10492 | |
21f581a5 | 10493 | map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping); |
c76949a6 MC |
10494 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); |
10495 | ||
10496 | for (i = 14; i < tx_len; i++) { | |
10497 | if (*(rx_skb->data + i) != (u8) (i & 0xff)) | |
10498 | goto out; | |
10499 | } | |
10500 | err = 0; | |
6aa20a22 | 10501 | |
c76949a6 MC |
10502 | /* tg3_free_rings will unmap and free the rx_skb */ |
10503 | out: | |
10504 | return err; | |
10505 | } | |
10506 | ||
9f40dead MC |
10507 | #define TG3_MAC_LOOPBACK_FAILED 1 |
10508 | #define TG3_PHY_LOOPBACK_FAILED 2 | |
10509 | #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \ | |
10510 | TG3_PHY_LOOPBACK_FAILED) | |
10511 | ||
10512 | static int tg3_test_loopback(struct tg3 *tp) | |
10513 | { | |
10514 | int err = 0; | |
9936bcf6 | 10515 | u32 cpmuctrl = 0; |
9f40dead MC |
10516 | |
10517 | if (!netif_running(tp->dev)) | |
10518 | return TG3_LOOPBACK_FAILED; | |
10519 | ||
b9ec6c1b MC |
10520 | err = tg3_reset_hw(tp, 1); |
10521 | if (err) | |
10522 | return TG3_LOOPBACK_FAILED; | |
9f40dead | 10523 | |
6833c043 MC |
10524 | /* Turn off gphy autopowerdown. */ |
10525 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
10526 | tg3_phy_toggle_apd(tp, false); | |
10527 | ||
321d32a0 | 10528 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
10529 | int i; |
10530 | u32 status; | |
10531 | ||
10532 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
10533 | ||
10534 | /* Wait for up to 40 microseconds to acquire lock. */ | |
10535 | for (i = 0; i < 4; i++) { | |
10536 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
10537 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
10538 | break; | |
10539 | udelay(10); | |
10540 | } | |
10541 | ||
10542 | if (status != CPMU_MUTEX_GNT_DRIVER) | |
10543 | return TG3_LOOPBACK_FAILED; | |
10544 | ||
b2a5c19c | 10545 | /* Turn off link-based power management. */ |
e875093c | 10546 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
109115e1 MC |
10547 | tw32(TG3_CPMU_CTRL, |
10548 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
10549 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9936bcf6 MC |
10550 | } |
10551 | ||
9f40dead MC |
10552 | if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) |
10553 | err |= TG3_MAC_LOOPBACK_FAILED; | |
9936bcf6 | 10554 | |
321d32a0 | 10555 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
10556 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
10557 | ||
10558 | /* Release the mutex */ | |
10559 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
10560 | } | |
10561 | ||
dd477003 MC |
10562 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && |
10563 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { | |
9f40dead MC |
10564 | if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) |
10565 | err |= TG3_PHY_LOOPBACK_FAILED; | |
10566 | } | |
10567 | ||
6833c043 MC |
10568 | /* Re-enable gphy autopowerdown. */ |
10569 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
10570 | tg3_phy_toggle_apd(tp, true); | |
10571 | ||
9f40dead MC |
10572 | return err; |
10573 | } | |
10574 | ||
4cafd3f5 MC |
10575 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
10576 | u64 *data) | |
10577 | { | |
566f86ad MC |
10578 | struct tg3 *tp = netdev_priv(dev); |
10579 | ||
bc1c7567 MC |
10580 | if (tp->link_config.phy_is_low_power) |
10581 | tg3_set_power_state(tp, PCI_D0); | |
10582 | ||
566f86ad MC |
10583 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
10584 | ||
10585 | if (tg3_test_nvram(tp) != 0) { | |
10586 | etest->flags |= ETH_TEST_FL_FAILED; | |
10587 | data[0] = 1; | |
10588 | } | |
ca43007a MC |
10589 | if (tg3_test_link(tp) != 0) { |
10590 | etest->flags |= ETH_TEST_FL_FAILED; | |
10591 | data[1] = 1; | |
10592 | } | |
a71116d1 | 10593 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 10594 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
10595 | |
10596 | if (netif_running(dev)) { | |
b02fd9e3 | 10597 | tg3_phy_stop(tp); |
a71116d1 | 10598 | tg3_netif_stop(tp); |
bbe832c0 MC |
10599 | irq_sync = 1; |
10600 | } | |
a71116d1 | 10601 | |
bbe832c0 | 10602 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
10603 | |
10604 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 10605 | err = tg3_nvram_lock(tp); |
a71116d1 MC |
10606 | tg3_halt_cpu(tp, RX_CPU_BASE); |
10607 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
10608 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
ec41c7df MC |
10609 | if (!err) |
10610 | tg3_nvram_unlock(tp); | |
a71116d1 | 10611 | |
d9ab5ad1 MC |
10612 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
10613 | tg3_phy_reset(tp); | |
10614 | ||
a71116d1 MC |
10615 | if (tg3_test_registers(tp) != 0) { |
10616 | etest->flags |= ETH_TEST_FL_FAILED; | |
10617 | data[2] = 1; | |
10618 | } | |
7942e1db MC |
10619 | if (tg3_test_memory(tp) != 0) { |
10620 | etest->flags |= ETH_TEST_FL_FAILED; | |
10621 | data[3] = 1; | |
10622 | } | |
9f40dead | 10623 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 10624 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 10625 | |
f47c11ee DM |
10626 | tg3_full_unlock(tp); |
10627 | ||
d4bc3927 MC |
10628 | if (tg3_test_interrupt(tp) != 0) { |
10629 | etest->flags |= ETH_TEST_FL_FAILED; | |
10630 | data[5] = 1; | |
10631 | } | |
f47c11ee DM |
10632 | |
10633 | tg3_full_lock(tp, 0); | |
d4bc3927 | 10634 | |
a71116d1 MC |
10635 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
10636 | if (netif_running(dev)) { | |
10637 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
b02fd9e3 MC |
10638 | err2 = tg3_restart_hw(tp, 1); |
10639 | if (!err2) | |
b9ec6c1b | 10640 | tg3_netif_start(tp); |
a71116d1 | 10641 | } |
f47c11ee DM |
10642 | |
10643 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
10644 | |
10645 | if (irq_sync && !err2) | |
10646 | tg3_phy_start(tp); | |
a71116d1 | 10647 | } |
bc1c7567 MC |
10648 | if (tp->link_config.phy_is_low_power) |
10649 | tg3_set_power_state(tp, PCI_D3hot); | |
10650 | ||
4cafd3f5 MC |
10651 | } |
10652 | ||
1da177e4 LT |
10653 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
10654 | { | |
10655 | struct mii_ioctl_data *data = if_mii(ifr); | |
10656 | struct tg3 *tp = netdev_priv(dev); | |
10657 | int err; | |
10658 | ||
b02fd9e3 | 10659 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 10660 | struct phy_device *phydev; |
b02fd9e3 MC |
10661 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) |
10662 | return -EAGAIN; | |
3f0e3ad7 MC |
10663 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10664 | return phy_mii_ioctl(phydev, data, cmd); | |
b02fd9e3 MC |
10665 | } |
10666 | ||
1da177e4 LT |
10667 | switch(cmd) { |
10668 | case SIOCGMIIPHY: | |
882e9793 | 10669 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
10670 | |
10671 | /* fallthru */ | |
10672 | case SIOCGMIIREG: { | |
10673 | u32 mii_regval; | |
10674 | ||
10675 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
10676 | break; /* We have no PHY */ | |
10677 | ||
bc1c7567 MC |
10678 | if (tp->link_config.phy_is_low_power) |
10679 | return -EAGAIN; | |
10680 | ||
f47c11ee | 10681 | spin_lock_bh(&tp->lock); |
1da177e4 | 10682 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 10683 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
10684 | |
10685 | data->val_out = mii_regval; | |
10686 | ||
10687 | return err; | |
10688 | } | |
10689 | ||
10690 | case SIOCSMIIREG: | |
10691 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
10692 | break; /* We have no PHY */ | |
10693 | ||
bc1c7567 MC |
10694 | if (tp->link_config.phy_is_low_power) |
10695 | return -EAGAIN; | |
10696 | ||
f47c11ee | 10697 | spin_lock_bh(&tp->lock); |
1da177e4 | 10698 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 10699 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
10700 | |
10701 | return err; | |
10702 | ||
10703 | default: | |
10704 | /* do nothing */ | |
10705 | break; | |
10706 | } | |
10707 | return -EOPNOTSUPP; | |
10708 | } | |
10709 | ||
10710 | #if TG3_VLAN_TAG_USED | |
10711 | static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
10712 | { | |
10713 | struct tg3 *tp = netdev_priv(dev); | |
10714 | ||
844b3eed MC |
10715 | if (!netif_running(dev)) { |
10716 | tp->vlgrp = grp; | |
10717 | return; | |
10718 | } | |
10719 | ||
10720 | tg3_netif_stop(tp); | |
29315e87 | 10721 | |
f47c11ee | 10722 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10723 | |
10724 | tp->vlgrp = grp; | |
10725 | ||
10726 | /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */ | |
10727 | __tg3_set_rx_mode(dev); | |
10728 | ||
844b3eed | 10729 | tg3_netif_start(tp); |
46966545 MC |
10730 | |
10731 | tg3_full_unlock(tp); | |
1da177e4 | 10732 | } |
1da177e4 LT |
10733 | #endif |
10734 | ||
15f9850d DM |
10735 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
10736 | { | |
10737 | struct tg3 *tp = netdev_priv(dev); | |
10738 | ||
10739 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
10740 | return 0; | |
10741 | } | |
10742 | ||
d244c892 MC |
10743 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
10744 | { | |
10745 | struct tg3 *tp = netdev_priv(dev); | |
10746 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
10747 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
10748 | ||
10749 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
10750 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
10751 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
10752 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
10753 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
10754 | } | |
10755 | ||
10756 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
10757 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
10758 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
10759 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
10760 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
10761 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
10762 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
10763 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
10764 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
10765 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
10766 | return -EINVAL; | |
10767 | ||
10768 | /* No rx interrupts will be generated if both are zero */ | |
10769 | if ((ec->rx_coalesce_usecs == 0) && | |
10770 | (ec->rx_max_coalesced_frames == 0)) | |
10771 | return -EINVAL; | |
10772 | ||
10773 | /* No tx interrupts will be generated if both are zero */ | |
10774 | if ((ec->tx_coalesce_usecs == 0) && | |
10775 | (ec->tx_max_coalesced_frames == 0)) | |
10776 | return -EINVAL; | |
10777 | ||
10778 | /* Only copy relevant parameters, ignore all others. */ | |
10779 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
10780 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
10781 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
10782 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
10783 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
10784 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
10785 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
10786 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
10787 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
10788 | ||
10789 | if (netif_running(dev)) { | |
10790 | tg3_full_lock(tp, 0); | |
10791 | __tg3_set_coalesce(tp, &tp->coal); | |
10792 | tg3_full_unlock(tp); | |
10793 | } | |
10794 | return 0; | |
10795 | } | |
10796 | ||
7282d491 | 10797 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
10798 | .get_settings = tg3_get_settings, |
10799 | .set_settings = tg3_set_settings, | |
10800 | .get_drvinfo = tg3_get_drvinfo, | |
10801 | .get_regs_len = tg3_get_regs_len, | |
10802 | .get_regs = tg3_get_regs, | |
10803 | .get_wol = tg3_get_wol, | |
10804 | .set_wol = tg3_set_wol, | |
10805 | .get_msglevel = tg3_get_msglevel, | |
10806 | .set_msglevel = tg3_set_msglevel, | |
10807 | .nway_reset = tg3_nway_reset, | |
10808 | .get_link = ethtool_op_get_link, | |
10809 | .get_eeprom_len = tg3_get_eeprom_len, | |
10810 | .get_eeprom = tg3_get_eeprom, | |
10811 | .set_eeprom = tg3_set_eeprom, | |
10812 | .get_ringparam = tg3_get_ringparam, | |
10813 | .set_ringparam = tg3_set_ringparam, | |
10814 | .get_pauseparam = tg3_get_pauseparam, | |
10815 | .set_pauseparam = tg3_set_pauseparam, | |
10816 | .get_rx_csum = tg3_get_rx_csum, | |
10817 | .set_rx_csum = tg3_set_rx_csum, | |
1da177e4 | 10818 | .set_tx_csum = tg3_set_tx_csum, |
1da177e4 | 10819 | .set_sg = ethtool_op_set_sg, |
1da177e4 | 10820 | .set_tso = tg3_set_tso, |
4cafd3f5 | 10821 | .self_test = tg3_self_test, |
1da177e4 | 10822 | .get_strings = tg3_get_strings, |
4009a93d | 10823 | .phys_id = tg3_phys_id, |
1da177e4 | 10824 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 10825 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 10826 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 10827 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
10828 | }; |
10829 | ||
10830 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
10831 | { | |
1b27777a | 10832 | u32 cursize, val, magic; |
1da177e4 LT |
10833 | |
10834 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
10835 | ||
e4f34110 | 10836 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
10837 | return; |
10838 | ||
b16250e3 MC |
10839 | if ((magic != TG3_EEPROM_MAGIC) && |
10840 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
10841 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
10842 | return; |
10843 | ||
10844 | /* | |
10845 | * Size the chip by reading offsets at increasing powers of two. | |
10846 | * When we encounter our validation signature, we know the addressing | |
10847 | * has wrapped around, and thus have our chip size. | |
10848 | */ | |
1b27777a | 10849 | cursize = 0x10; |
1da177e4 LT |
10850 | |
10851 | while (cursize < tp->nvram_size) { | |
e4f34110 | 10852 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
10853 | return; |
10854 | ||
1820180b | 10855 | if (val == magic) |
1da177e4 LT |
10856 | break; |
10857 | ||
10858 | cursize <<= 1; | |
10859 | } | |
10860 | ||
10861 | tp->nvram_size = cursize; | |
10862 | } | |
6aa20a22 | 10863 | |
1da177e4 LT |
10864 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
10865 | { | |
10866 | u32 val; | |
10867 | ||
df259d8c MC |
10868 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
10869 | tg3_nvram_read(tp, 0, &val) != 0) | |
1b27777a MC |
10870 | return; |
10871 | ||
10872 | /* Selfboot format */ | |
1820180b | 10873 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
10874 | tg3_get_eeprom_size(tp); |
10875 | return; | |
10876 | } | |
10877 | ||
6d348f2c | 10878 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 10879 | if (val != 0) { |
6d348f2c MC |
10880 | /* This is confusing. We want to operate on the |
10881 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
10882 | * call will read from NVRAM and byteswap the data | |
10883 | * according to the byteswapping settings for all | |
10884 | * other register accesses. This ensures the data we | |
10885 | * want will always reside in the lower 16-bits. | |
10886 | * However, the data in NVRAM is in LE format, which | |
10887 | * means the data from the NVRAM read will always be | |
10888 | * opposite the endianness of the CPU. The 16-bit | |
10889 | * byteswap then brings the data to CPU endianness. | |
10890 | */ | |
10891 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
10892 | return; |
10893 | } | |
10894 | } | |
fd1122a2 | 10895 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
10896 | } |
10897 | ||
10898 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
10899 | { | |
10900 | u32 nvcfg1; | |
10901 | ||
10902 | nvcfg1 = tr32(NVRAM_CFG1); | |
10903 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
10904 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
8590a603 | 10905 | } else { |
1da177e4 LT |
10906 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
10907 | tw32(NVRAM_CFG1, nvcfg1); | |
10908 | } | |
10909 | ||
4c987487 | 10910 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || |
a4e2b347 | 10911 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 | 10912 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
10913 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
10914 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10915 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
10916 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10917 | break; | |
10918 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
10919 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10920 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
10921 | break; | |
10922 | case FLASH_VENDOR_ATMEL_EEPROM: | |
10923 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10924 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
10925 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10926 | break; | |
10927 | case FLASH_VENDOR_ST: | |
10928 | tp->nvram_jedecnum = JEDEC_ST; | |
10929 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
10930 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10931 | break; | |
10932 | case FLASH_VENDOR_SAIFUN: | |
10933 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
10934 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
10935 | break; | |
10936 | case FLASH_VENDOR_SST_SMALL: | |
10937 | case FLASH_VENDOR_SST_LARGE: | |
10938 | tp->nvram_jedecnum = JEDEC_SST; | |
10939 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
10940 | break; | |
1da177e4 | 10941 | } |
8590a603 | 10942 | } else { |
1da177e4 LT |
10943 | tp->nvram_jedecnum = JEDEC_ATMEL; |
10944 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
10945 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10946 | } | |
10947 | } | |
10948 | ||
a1b950d5 MC |
10949 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
10950 | { | |
10951 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
10952 | case FLASH_5752PAGE_SIZE_256: | |
10953 | tp->nvram_pagesize = 256; | |
10954 | break; | |
10955 | case FLASH_5752PAGE_SIZE_512: | |
10956 | tp->nvram_pagesize = 512; | |
10957 | break; | |
10958 | case FLASH_5752PAGE_SIZE_1K: | |
10959 | tp->nvram_pagesize = 1024; | |
10960 | break; | |
10961 | case FLASH_5752PAGE_SIZE_2K: | |
10962 | tp->nvram_pagesize = 2048; | |
10963 | break; | |
10964 | case FLASH_5752PAGE_SIZE_4K: | |
10965 | tp->nvram_pagesize = 4096; | |
10966 | break; | |
10967 | case FLASH_5752PAGE_SIZE_264: | |
10968 | tp->nvram_pagesize = 264; | |
10969 | break; | |
10970 | case FLASH_5752PAGE_SIZE_528: | |
10971 | tp->nvram_pagesize = 528; | |
10972 | break; | |
10973 | } | |
10974 | } | |
10975 | ||
361b4ac2 MC |
10976 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
10977 | { | |
10978 | u32 nvcfg1; | |
10979 | ||
10980 | nvcfg1 = tr32(NVRAM_CFG1); | |
10981 | ||
e6af301b MC |
10982 | /* NVRAM protection for TPM */ |
10983 | if (nvcfg1 & (1 << 27)) | |
f66a29b0 | 10984 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
e6af301b | 10985 | |
361b4ac2 | 10986 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
10987 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
10988 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
10989 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10990 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10991 | break; | |
10992 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
10993 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
10994 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
10995 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
10996 | break; | |
10997 | case FLASH_5752VENDOR_ST_M45PE10: | |
10998 | case FLASH_5752VENDOR_ST_M45PE20: | |
10999 | case FLASH_5752VENDOR_ST_M45PE40: | |
11000 | tp->nvram_jedecnum = JEDEC_ST; | |
11001 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11002 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11003 | break; | |
361b4ac2 MC |
11004 | } |
11005 | ||
11006 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | |
a1b950d5 | 11007 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 11008 | } else { |
361b4ac2 MC |
11009 | /* For eeprom, set pagesize to maximum eeprom size */ |
11010 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11011 | ||
11012 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11013 | tw32(NVRAM_CFG1, nvcfg1); | |
11014 | } | |
11015 | } | |
11016 | ||
d3c7b886 MC |
11017 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
11018 | { | |
989a9d23 | 11019 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
11020 | |
11021 | nvcfg1 = tr32(NVRAM_CFG1); | |
11022 | ||
11023 | /* NVRAM protection for TPM */ | |
989a9d23 | 11024 | if (nvcfg1 & (1 << 27)) { |
f66a29b0 | 11025 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
989a9d23 MC |
11026 | protect = 1; |
11027 | } | |
d3c7b886 | 11028 | |
989a9d23 MC |
11029 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
11030 | switch (nvcfg1) { | |
8590a603 MC |
11031 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
11032 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11033 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11034 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11035 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11036 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11037 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11038 | tp->nvram_pagesize = 264; | |
11039 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11040 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11041 | tp->nvram_size = (protect ? 0x3e200 : | |
11042 | TG3_NVRAM_SIZE_512KB); | |
11043 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11044 | tp->nvram_size = (protect ? 0x1f200 : | |
11045 | TG3_NVRAM_SIZE_256KB); | |
11046 | else | |
11047 | tp->nvram_size = (protect ? 0x1f200 : | |
11048 | TG3_NVRAM_SIZE_128KB); | |
11049 | break; | |
11050 | case FLASH_5752VENDOR_ST_M45PE10: | |
11051 | case FLASH_5752VENDOR_ST_M45PE20: | |
11052 | case FLASH_5752VENDOR_ST_M45PE40: | |
11053 | tp->nvram_jedecnum = JEDEC_ST; | |
11054 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11055 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11056 | tp->nvram_pagesize = 256; | |
11057 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11058 | tp->nvram_size = (protect ? | |
11059 | TG3_NVRAM_SIZE_64KB : | |
11060 | TG3_NVRAM_SIZE_128KB); | |
11061 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
11062 | tp->nvram_size = (protect ? | |
11063 | TG3_NVRAM_SIZE_64KB : | |
11064 | TG3_NVRAM_SIZE_256KB); | |
11065 | else | |
11066 | tp->nvram_size = (protect ? | |
11067 | TG3_NVRAM_SIZE_128KB : | |
11068 | TG3_NVRAM_SIZE_512KB); | |
11069 | break; | |
d3c7b886 MC |
11070 | } |
11071 | } | |
11072 | ||
1b27777a MC |
11073 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
11074 | { | |
11075 | u32 nvcfg1; | |
11076 | ||
11077 | nvcfg1 = tr32(NVRAM_CFG1); | |
11078 | ||
11079 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
11080 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
11081 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11082 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
11083 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11084 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11085 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11086 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
1b27777a | 11087 | |
8590a603 MC |
11088 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11089 | tw32(NVRAM_CFG1, nvcfg1); | |
11090 | break; | |
11091 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11092 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11093 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11094 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11095 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11096 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11097 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11098 | tp->nvram_pagesize = 264; | |
11099 | break; | |
11100 | case FLASH_5752VENDOR_ST_M45PE10: | |
11101 | case FLASH_5752VENDOR_ST_M45PE20: | |
11102 | case FLASH_5752VENDOR_ST_M45PE40: | |
11103 | tp->nvram_jedecnum = JEDEC_ST; | |
11104 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11105 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11106 | tp->nvram_pagesize = 256; | |
11107 | break; | |
1b27777a MC |
11108 | } |
11109 | } | |
11110 | ||
6b91fa02 MC |
11111 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
11112 | { | |
11113 | u32 nvcfg1, protect = 0; | |
11114 | ||
11115 | nvcfg1 = tr32(NVRAM_CFG1); | |
11116 | ||
11117 | /* NVRAM protection for TPM */ | |
11118 | if (nvcfg1 & (1 << 27)) { | |
f66a29b0 | 11119 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
6b91fa02 MC |
11120 | protect = 1; |
11121 | } | |
11122 | ||
11123 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11124 | switch (nvcfg1) { | |
8590a603 MC |
11125 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
11126 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11127 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11128 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11129 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11130 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11131 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11132 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11133 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11134 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11135 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11136 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
11137 | tp->nvram_pagesize = 256; | |
11138 | break; | |
11139 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11140 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11141 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11142 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11143 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11144 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11145 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11146 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11147 | tp->nvram_jedecnum = JEDEC_ST; | |
11148 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11149 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11150 | tp->nvram_pagesize = 256; | |
11151 | break; | |
6b91fa02 MC |
11152 | } |
11153 | ||
11154 | if (protect) { | |
11155 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
11156 | } else { | |
11157 | switch (nvcfg1) { | |
8590a603 MC |
11158 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
11159 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11160 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11161 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11162 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
11163 | break; | |
11164 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11165 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11166 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11167 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11168 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11169 | break; | |
11170 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11171 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11172 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11173 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11174 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11175 | break; | |
11176 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11177 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11178 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11179 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11180 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11181 | break; | |
6b91fa02 MC |
11182 | } |
11183 | } | |
11184 | } | |
11185 | ||
b5d3772c MC |
11186 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
11187 | { | |
11188 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11189 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11190 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11191 | } | |
11192 | ||
321d32a0 MC |
11193 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
11194 | { | |
11195 | u32 nvcfg1; | |
11196 | ||
11197 | nvcfg1 = tr32(NVRAM_CFG1); | |
11198 | ||
11199 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11200 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11201 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11202 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11203 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11204 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11205 | ||
11206 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11207 | tw32(NVRAM_CFG1, nvcfg1); | |
11208 | return; | |
11209 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11210 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11211 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11212 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11213 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11214 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11215 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11216 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11217 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11218 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11219 | ||
11220 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11221 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11222 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11223 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11224 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11225 | break; | |
11226 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11227 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11228 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11229 | break; | |
11230 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11231 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11232 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11233 | break; | |
11234 | } | |
11235 | break; | |
11236 | case FLASH_5752VENDOR_ST_M45PE10: | |
11237 | case FLASH_5752VENDOR_ST_M45PE20: | |
11238 | case FLASH_5752VENDOR_ST_M45PE40: | |
11239 | tp->nvram_jedecnum = JEDEC_ST; | |
11240 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11241 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11242 | ||
11243 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11244 | case FLASH_5752VENDOR_ST_M45PE10: | |
11245 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11246 | break; | |
11247 | case FLASH_5752VENDOR_ST_M45PE20: | |
11248 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11249 | break; | |
11250 | case FLASH_5752VENDOR_ST_M45PE40: | |
11251 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11252 | break; | |
11253 | } | |
11254 | break; | |
11255 | default: | |
df259d8c | 11256 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; |
321d32a0 MC |
11257 | return; |
11258 | } | |
11259 | ||
a1b950d5 MC |
11260 | tg3_nvram_get_pagesize(tp, nvcfg1); |
11261 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
321d32a0 | 11262 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; |
a1b950d5 MC |
11263 | } |
11264 | ||
11265 | ||
11266 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
11267 | { | |
11268 | u32 nvcfg1; | |
11269 | ||
11270 | nvcfg1 = tr32(NVRAM_CFG1); | |
11271 | ||
11272 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11273 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
11274 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
11275 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11276 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11277 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11278 | ||
11279 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11280 | tw32(NVRAM_CFG1, nvcfg1); | |
11281 | return; | |
11282 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
11283 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
11284 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
11285 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11286 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11287 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11288 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
11289 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11290 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11291 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11292 | ||
11293 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11294 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11295 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11296 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11297 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11298 | break; | |
11299 | default: | |
11300 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11301 | break; | |
11302 | } | |
321d32a0 | 11303 | break; |
a1b950d5 MC |
11304 | case FLASH_5717VENDOR_ST_M_M25PE10: |
11305 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
11306 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
11307 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
11308 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11309 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11310 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11311 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11312 | case FLASH_5717VENDOR_ST_25USPT: | |
11313 | case FLASH_5717VENDOR_ST_45USPT: | |
11314 | tp->nvram_jedecnum = JEDEC_ST; | |
11315 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11316 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11317 | ||
11318 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11319 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11320 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11321 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11322 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11323 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11324 | break; | |
11325 | default: | |
11326 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11327 | break; | |
11328 | } | |
321d32a0 | 11329 | break; |
a1b950d5 MC |
11330 | default: |
11331 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
11332 | return; | |
321d32a0 | 11333 | } |
a1b950d5 MC |
11334 | |
11335 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
11336 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
11337 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
321d32a0 MC |
11338 | } |
11339 | ||
1da177e4 LT |
11340 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
11341 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
11342 | { | |
1da177e4 LT |
11343 | tw32_f(GRC_EEPROM_ADDR, |
11344 | (EEPROM_ADDR_FSM_RESET | | |
11345 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
11346 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
11347 | ||
9d57f01c | 11348 | msleep(1); |
1da177e4 LT |
11349 | |
11350 | /* Enable seeprom accesses. */ | |
11351 | tw32_f(GRC_LOCAL_CTRL, | |
11352 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
11353 | udelay(100); | |
11354 | ||
11355 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
11356 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
11357 | tp->tg3_flags |= TG3_FLAG_NVRAM; | |
11358 | ||
ec41c7df MC |
11359 | if (tg3_nvram_lock(tp)) { |
11360 | printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, " | |
11361 | "tg3_nvram_init failed.\n", tp->dev->name); | |
11362 | return; | |
11363 | } | |
e6af301b | 11364 | tg3_enable_nvram_access(tp); |
1da177e4 | 11365 | |
989a9d23 MC |
11366 | tp->nvram_size = 0; |
11367 | ||
361b4ac2 MC |
11368 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
11369 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
11370 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
11371 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 11372 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
11373 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
11374 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 11375 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
11376 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
11377 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
11378 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
11379 | tg3_get_5906_nvram_info(tp); | |
321d32a0 MC |
11380 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
11381 | tg3_get_57780_nvram_info(tp); | |
a1b950d5 MC |
11382 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
11383 | tg3_get_5717_nvram_info(tp); | |
361b4ac2 MC |
11384 | else |
11385 | tg3_get_nvram_info(tp); | |
11386 | ||
989a9d23 MC |
11387 | if (tp->nvram_size == 0) |
11388 | tg3_get_nvram_size(tp); | |
1da177e4 | 11389 | |
e6af301b | 11390 | tg3_disable_nvram_access(tp); |
381291b7 | 11391 | tg3_nvram_unlock(tp); |
1da177e4 LT |
11392 | |
11393 | } else { | |
11394 | tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); | |
11395 | ||
11396 | tg3_get_eeprom_size(tp); | |
11397 | } | |
11398 | } | |
11399 | ||
1da177e4 LT |
11400 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
11401 | u32 offset, u32 len, u8 *buf) | |
11402 | { | |
11403 | int i, j, rc = 0; | |
11404 | u32 val; | |
11405 | ||
11406 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 11407 | u32 addr; |
a9dc529d | 11408 | __be32 data; |
1da177e4 LT |
11409 | |
11410 | addr = offset + i; | |
11411 | ||
11412 | memcpy(&data, buf + i, 4); | |
11413 | ||
62cedd11 MC |
11414 | /* |
11415 | * The SEEPROM interface expects the data to always be opposite | |
11416 | * the native endian format. We accomplish this by reversing | |
11417 | * all the operations that would have been performed on the | |
11418 | * data from a call to tg3_nvram_read_be32(). | |
11419 | */ | |
11420 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
11421 | |
11422 | val = tr32(GRC_EEPROM_ADDR); | |
11423 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
11424 | ||
11425 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
11426 | EEPROM_ADDR_READ); | |
11427 | tw32(GRC_EEPROM_ADDR, val | | |
11428 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
11429 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
11430 | EEPROM_ADDR_START | | |
11431 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 11432 | |
9d57f01c | 11433 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
11434 | val = tr32(GRC_EEPROM_ADDR); |
11435 | ||
11436 | if (val & EEPROM_ADDR_COMPLETE) | |
11437 | break; | |
9d57f01c | 11438 | msleep(1); |
1da177e4 LT |
11439 | } |
11440 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
11441 | rc = -EBUSY; | |
11442 | break; | |
11443 | } | |
11444 | } | |
11445 | ||
11446 | return rc; | |
11447 | } | |
11448 | ||
11449 | /* offset and length are dword aligned */ | |
11450 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
11451 | u8 *buf) | |
11452 | { | |
11453 | int ret = 0; | |
11454 | u32 pagesize = tp->nvram_pagesize; | |
11455 | u32 pagemask = pagesize - 1; | |
11456 | u32 nvram_cmd; | |
11457 | u8 *tmp; | |
11458 | ||
11459 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
11460 | if (tmp == NULL) | |
11461 | return -ENOMEM; | |
11462 | ||
11463 | while (len) { | |
11464 | int j; | |
e6af301b | 11465 | u32 phy_addr, page_off, size; |
1da177e4 LT |
11466 | |
11467 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 11468 | |
1da177e4 | 11469 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
11470 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
11471 | (__be32 *) (tmp + j)); | |
11472 | if (ret) | |
1da177e4 LT |
11473 | break; |
11474 | } | |
11475 | if (ret) | |
11476 | break; | |
11477 | ||
11478 | page_off = offset & pagemask; | |
11479 | size = pagesize; | |
11480 | if (len < size) | |
11481 | size = len; | |
11482 | ||
11483 | len -= size; | |
11484 | ||
11485 | memcpy(tmp + page_off, buf, size); | |
11486 | ||
11487 | offset = offset + (pagesize - page_off); | |
11488 | ||
e6af301b | 11489 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
11490 | |
11491 | /* | |
11492 | * Before we can erase the flash page, we need | |
11493 | * to issue a special "write enable" command. | |
11494 | */ | |
11495 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11496 | ||
11497 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11498 | break; | |
11499 | ||
11500 | /* Erase the target page */ | |
11501 | tw32(NVRAM_ADDR, phy_addr); | |
11502 | ||
11503 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
11504 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
11505 | ||
11506 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11507 | break; | |
11508 | ||
11509 | /* Issue another write enable to start the write. */ | |
11510 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11511 | ||
11512 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11513 | break; | |
11514 | ||
11515 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 11516 | __be32 data; |
1da177e4 | 11517 | |
b9fc7dc5 | 11518 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 11519 | |
b9fc7dc5 | 11520 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
11521 | |
11522 | tw32(NVRAM_ADDR, phy_addr + j); | |
11523 | ||
11524 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
11525 | NVRAM_CMD_WR; | |
11526 | ||
11527 | if (j == 0) | |
11528 | nvram_cmd |= NVRAM_CMD_FIRST; | |
11529 | else if (j == (pagesize - 4)) | |
11530 | nvram_cmd |= NVRAM_CMD_LAST; | |
11531 | ||
11532 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
11533 | break; | |
11534 | } | |
11535 | if (ret) | |
11536 | break; | |
11537 | } | |
11538 | ||
11539 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11540 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
11541 | ||
11542 | kfree(tmp); | |
11543 | ||
11544 | return ret; | |
11545 | } | |
11546 | ||
11547 | /* offset and length are dword aligned */ | |
11548 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
11549 | u8 *buf) | |
11550 | { | |
11551 | int i, ret = 0; | |
11552 | ||
11553 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
11554 | u32 page_off, phy_addr, nvram_cmd; |
11555 | __be32 data; | |
1da177e4 LT |
11556 | |
11557 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 11558 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
11559 | |
11560 | page_off = offset % tp->nvram_pagesize; | |
11561 | ||
1820180b | 11562 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
11563 | |
11564 | tw32(NVRAM_ADDR, phy_addr); | |
11565 | ||
11566 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
11567 | ||
11568 | if ((page_off == 0) || (i == 0)) | |
11569 | nvram_cmd |= NVRAM_CMD_FIRST; | |
f6d9a256 | 11570 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
11571 | nvram_cmd |= NVRAM_CMD_LAST; |
11572 | ||
11573 | if (i == (len - 4)) | |
11574 | nvram_cmd |= NVRAM_CMD_LAST; | |
11575 | ||
321d32a0 MC |
11576 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
11577 | !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
4c987487 MC |
11578 | (tp->nvram_jedecnum == JEDEC_ST) && |
11579 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
11580 | |
11581 | if ((ret = tg3_nvram_exec_cmd(tp, | |
11582 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
11583 | NVRAM_CMD_DONE))) | |
11584 | ||
11585 | break; | |
11586 | } | |
11587 | if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
11588 | /* We always do complete word writes to eeprom. */ | |
11589 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
11590 | } | |
11591 | ||
11592 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
11593 | break; | |
11594 | } | |
11595 | return ret; | |
11596 | } | |
11597 | ||
11598 | /* offset and length are dword aligned */ | |
11599 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
11600 | { | |
11601 | int ret; | |
11602 | ||
1da177e4 | 11603 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
314fba34 MC |
11604 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
11605 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
11606 | udelay(40); |
11607 | } | |
11608 | ||
11609 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { | |
11610 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
11611 | } | |
11612 | else { | |
11613 | u32 grc_mode; | |
11614 | ||
ec41c7df MC |
11615 | ret = tg3_nvram_lock(tp); |
11616 | if (ret) | |
11617 | return ret; | |
1da177e4 | 11618 | |
e6af301b MC |
11619 | tg3_enable_nvram_access(tp); |
11620 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 11621 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) |
1da177e4 | 11622 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
11623 | |
11624 | grc_mode = tr32(GRC_MODE); | |
11625 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
11626 | ||
11627 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || | |
11628 | !(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
11629 | ||
11630 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
11631 | buf); | |
11632 | } | |
11633 | else { | |
11634 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, | |
11635 | buf); | |
11636 | } | |
11637 | ||
11638 | grc_mode = tr32(GRC_MODE); | |
11639 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
11640 | ||
e6af301b | 11641 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
11642 | tg3_nvram_unlock(tp); |
11643 | } | |
11644 | ||
11645 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
314fba34 | 11646 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
11647 | udelay(40); |
11648 | } | |
11649 | ||
11650 | return ret; | |
11651 | } | |
11652 | ||
11653 | struct subsys_tbl_ent { | |
11654 | u16 subsys_vendor, subsys_devid; | |
11655 | u32 phy_id; | |
11656 | }; | |
11657 | ||
11658 | static struct subsys_tbl_ent subsys_id_to_phy_id[] = { | |
11659 | /* Broadcom boards. */ | |
11660 | { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */ | |
11661 | { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */ | |
11662 | { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */ | |
11663 | { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */ | |
11664 | { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */ | |
11665 | { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */ | |
11666 | { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */ | |
11667 | { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */ | |
11668 | { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */ | |
11669 | { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */ | |
11670 | { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */ | |
11671 | ||
11672 | /* 3com boards. */ | |
11673 | { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */ | |
11674 | { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */ | |
11675 | { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */ | |
11676 | { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */ | |
11677 | { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */ | |
11678 | ||
11679 | /* DELL boards. */ | |
11680 | { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */ | |
11681 | { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */ | |
11682 | { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */ | |
11683 | { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */ | |
11684 | ||
11685 | /* Compaq boards. */ | |
11686 | { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */ | |
11687 | { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */ | |
11688 | { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */ | |
11689 | { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */ | |
11690 | { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */ | |
11691 | ||
11692 | /* IBM boards. */ | |
11693 | { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */ | |
11694 | }; | |
11695 | ||
11696 | static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp) | |
11697 | { | |
11698 | int i; | |
11699 | ||
11700 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
11701 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
11702 | tp->pdev->subsystem_vendor) && | |
11703 | (subsys_id_to_phy_id[i].subsys_devid == | |
11704 | tp->pdev->subsystem_device)) | |
11705 | return &subsys_id_to_phy_id[i]; | |
11706 | } | |
11707 | return NULL; | |
11708 | } | |
11709 | ||
7d0c41ef | 11710 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 11711 | { |
1da177e4 | 11712 | u32 val; |
caf636c7 MC |
11713 | u16 pmcsr; |
11714 | ||
11715 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
11716 | * so need make sure we're in D0. | |
11717 | */ | |
11718 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
11719 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
11720 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
11721 | msleep(1); | |
7d0c41ef MC |
11722 | |
11723 | /* Make sure register accesses (indirect or otherwise) | |
11724 | * will function correctly. | |
11725 | */ | |
11726 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
11727 | tp->misc_host_ctrl); | |
1da177e4 | 11728 | |
f49639e6 DM |
11729 | /* The memory arbiter has to be enabled in order for SRAM accesses |
11730 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
11731 | * sure it is enabled, but other entities such as system netboot | |
11732 | * code might disable it. | |
11733 | */ | |
11734 | val = tr32(MEMARB_MODE); | |
11735 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
11736 | ||
1da177e4 | 11737 | tp->phy_id = PHY_ID_INVALID; |
7d0c41ef MC |
11738 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
11739 | ||
a85feb8c GZ |
11740 | /* Assume an onboard device and WOL capable by default. */ |
11741 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; | |
72b845e0 | 11742 | |
b5d3772c | 11743 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 11744 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
b5d3772c | 11745 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
11746 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
11747 | } | |
0527ba35 MC |
11748 | val = tr32(VCPU_CFGSHDW); |
11749 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
8ed5d97e | 11750 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; |
0527ba35 | 11751 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
2023276e | 11752 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) |
0527ba35 | 11753 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
05ac4cb7 | 11754 | goto done; |
b5d3772c MC |
11755 | } |
11756 | ||
1da177e4 LT |
11757 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
11758 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
11759 | u32 nic_cfg, led_cfg; | |
a9daf367 | 11760 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 11761 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
11762 | |
11763 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
11764 | tp->nic_sram_data_cfg = nic_cfg; | |
11765 | ||
11766 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
11767 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
11768 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && | |
11769 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && | |
11770 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) && | |
11771 | (ver > 0) && (ver < 0x100)) | |
11772 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
11773 | ||
a9daf367 MC |
11774 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
11775 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
11776 | ||
1da177e4 LT |
11777 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
11778 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
11779 | eeprom_phy_serdes = 1; | |
11780 | ||
11781 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
11782 | if (nic_phy_id != 0) { | |
11783 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
11784 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
11785 | ||
11786 | eeprom_phy_id = (id1 >> 16) << 10; | |
11787 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
11788 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
11789 | } else | |
11790 | eeprom_phy_id = 0; | |
11791 | ||
7d0c41ef | 11792 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 11793 | if (eeprom_phy_serdes) { |
a4e2b347 | 11794 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) |
747e8f8b MC |
11795 | tp->tg3_flags2 |= TG3_FLG2_MII_SERDES; |
11796 | else | |
11797 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
11798 | } | |
7d0c41ef | 11799 | |
cbf46853 | 11800 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
11801 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
11802 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 11803 | else |
1da177e4 LT |
11804 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
11805 | ||
11806 | switch (led_cfg) { | |
11807 | default: | |
11808 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
11809 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
11810 | break; | |
11811 | ||
11812 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
11813 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
11814 | break; | |
11815 | ||
11816 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
11817 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
11818 | |
11819 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
11820 | * read on some older 5700/5701 bootcode. | |
11821 | */ | |
11822 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
11823 | ASIC_REV_5700 || | |
11824 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
11825 | ASIC_REV_5701) | |
11826 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
11827 | ||
1da177e4 LT |
11828 | break; |
11829 | ||
11830 | case SHASTA_EXT_LED_SHARED: | |
11831 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
11832 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
11833 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
11834 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
11835 | LED_CTRL_MODE_PHY_2); | |
11836 | break; | |
11837 | ||
11838 | case SHASTA_EXT_LED_MAC: | |
11839 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
11840 | break; | |
11841 | ||
11842 | case SHASTA_EXT_LED_COMBO: | |
11843 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
11844 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
11845 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
11846 | LED_CTRL_MODE_PHY_2); | |
11847 | break; | |
11848 | ||
855e1111 | 11849 | } |
1da177e4 LT |
11850 | |
11851 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
11852 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
11853 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
11854 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
11855 | ||
b2a5c19c MC |
11856 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
11857 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 11858 | |
9d26e213 | 11859 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
1da177e4 | 11860 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
11861 | if ((tp->pdev->subsystem_vendor == |
11862 | PCI_VENDOR_ID_ARIMA) && | |
11863 | (tp->pdev->subsystem_device == 0x205a || | |
11864 | tp->pdev->subsystem_device == 0x2063)) | |
11865 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
11866 | } else { | |
f49639e6 | 11867 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
11868 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
11869 | } | |
1da177e4 LT |
11870 | |
11871 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
11872 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
cbf46853 | 11873 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
11874 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
11875 | } | |
b2b98d4a MC |
11876 | |
11877 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
11878 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
0d3031d9 | 11879 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; |
b2b98d4a | 11880 | |
a85feb8c GZ |
11881 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES && |
11882 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) | |
11883 | tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; | |
1da177e4 | 11884 | |
12dac075 | 11885 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
05ac4cb7 | 11886 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) |
0527ba35 MC |
11887 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
11888 | ||
1da177e4 LT |
11889 | if (cfg2 & (1 << 17)) |
11890 | tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING; | |
11891 | ||
11892 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
11893 | /* bootcode if bit 18 is set */ | |
11894 | if (cfg2 & (1 << 18)) | |
11895 | tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS; | |
8ed5d97e | 11896 | |
321d32a0 MC |
11897 | if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
11898 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 MC |
11899 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
11900 | tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD; | |
11901 | ||
8ed5d97e MC |
11902 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
11903 | u32 cfg3; | |
11904 | ||
11905 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
11906 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
11907 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
11908 | } | |
a9daf367 MC |
11909 | |
11910 | if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE) | |
11911 | tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE; | |
11912 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) | |
11913 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; | |
11914 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
11915 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; | |
1da177e4 | 11916 | } |
05ac4cb7 MC |
11917 | done: |
11918 | device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP); | |
11919 | device_set_wakeup_enable(&tp->pdev->dev, | |
11920 | tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
7d0c41ef MC |
11921 | } |
11922 | ||
b2a5c19c MC |
11923 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
11924 | { | |
11925 | int i; | |
11926 | u32 val; | |
11927 | ||
11928 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
11929 | tw32(OTP_CTRL, cmd); | |
11930 | ||
11931 | /* Wait for up to 1 ms for command to execute. */ | |
11932 | for (i = 0; i < 100; i++) { | |
11933 | val = tr32(OTP_STATUS); | |
11934 | if (val & OTP_STATUS_CMD_DONE) | |
11935 | break; | |
11936 | udelay(10); | |
11937 | } | |
11938 | ||
11939 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
11940 | } | |
11941 | ||
11942 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
11943 | * configuration is a 32-bit value that straddles the alignment boundary. | |
11944 | * We do two 32-bit reads and then shift and merge the results. | |
11945 | */ | |
11946 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
11947 | { | |
11948 | u32 bhalf_otp, thalf_otp; | |
11949 | ||
11950 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
11951 | ||
11952 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
11953 | return 0; | |
11954 | ||
11955 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
11956 | ||
11957 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
11958 | return 0; | |
11959 | ||
11960 | thalf_otp = tr32(OTP_READ_DATA); | |
11961 | ||
11962 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
11963 | ||
11964 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
11965 | return 0; | |
11966 | ||
11967 | bhalf_otp = tr32(OTP_READ_DATA); | |
11968 | ||
11969 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
11970 | } | |
11971 | ||
7d0c41ef MC |
11972 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
11973 | { | |
11974 | u32 hw_phy_id_1, hw_phy_id_2; | |
11975 | u32 hw_phy_id, hw_phy_id_masked; | |
11976 | int err; | |
1da177e4 | 11977 | |
b02fd9e3 MC |
11978 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
11979 | return tg3_phy_init(tp); | |
11980 | ||
1da177e4 | 11981 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 11982 | * firmware access to the PHY hardware. |
1da177e4 LT |
11983 | */ |
11984 | err = 0; | |
0d3031d9 MC |
11985 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || |
11986 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
1da177e4 LT |
11987 | hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID; |
11988 | } else { | |
11989 | /* Now read the physical PHY_ID from the chip and verify | |
11990 | * that it is sane. If it doesn't look good, we fall back | |
11991 | * to either the hard-coded table based PHY_ID and failing | |
11992 | * that the value found in the eeprom area. | |
11993 | */ | |
11994 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
11995 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
11996 | ||
11997 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
11998 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
11999 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
12000 | ||
12001 | hw_phy_id_masked = hw_phy_id & PHY_ID_MASK; | |
12002 | } | |
12003 | ||
12004 | if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) { | |
12005 | tp->phy_id = hw_phy_id; | |
12006 | if (hw_phy_id_masked == PHY_ID_BCM8002) | |
12007 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
da6b2d01 MC |
12008 | else |
12009 | tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES; | |
1da177e4 | 12010 | } else { |
7d0c41ef MC |
12011 | if (tp->phy_id != PHY_ID_INVALID) { |
12012 | /* Do nothing, phy ID already set up in | |
12013 | * tg3_get_eeprom_hw_cfg(). | |
12014 | */ | |
1da177e4 LT |
12015 | } else { |
12016 | struct subsys_tbl_ent *p; | |
12017 | ||
12018 | /* No eeprom signature? Try the hardcoded | |
12019 | * subsys device table. | |
12020 | */ | |
12021 | p = lookup_by_subsys(tp); | |
12022 | if (!p) | |
12023 | return -ENODEV; | |
12024 | ||
12025 | tp->phy_id = p->phy_id; | |
12026 | if (!tp->phy_id || | |
12027 | tp->phy_id == PHY_ID_BCM8002) | |
12028 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
12029 | } | |
12030 | } | |
12031 | ||
747e8f8b | 12032 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) && |
0d3031d9 | 12033 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && |
1da177e4 | 12034 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
3600d918 | 12035 | u32 bmsr, adv_reg, tg3_ctrl, mask; |
1da177e4 LT |
12036 | |
12037 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
12038 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
12039 | (bmsr & BMSR_LSTATUS)) | |
12040 | goto skip_phy_reset; | |
6aa20a22 | 12041 | |
1da177e4 LT |
12042 | err = tg3_phy_reset(tp); |
12043 | if (err) | |
12044 | return err; | |
12045 | ||
12046 | adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
12047 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
12048 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
12049 | tg3_ctrl = 0; | |
12050 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
12051 | tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | | |
12052 | MII_TG3_CTRL_ADV_1000_FULL); | |
12053 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
12054 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
12055 | tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER | | |
12056 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
12057 | } | |
12058 | ||
3600d918 MC |
12059 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
12060 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
12061 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
12062 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
1da177e4 LT |
12063 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); |
12064 | ||
12065 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
12066 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
12067 | ||
12068 | tg3_writephy(tp, MII_BMCR, | |
12069 | BMCR_ANENABLE | BMCR_ANRESTART); | |
12070 | } | |
12071 | tg3_phy_set_wirespeed(tp); | |
12072 | ||
12073 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
12074 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
12075 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
12076 | } | |
12077 | ||
12078 | skip_phy_reset: | |
12079 | if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { | |
12080 | err = tg3_init_5401phy_dsp(tp); | |
12081 | if (err) | |
12082 | return err; | |
12083 | } | |
12084 | ||
12085 | if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) { | |
12086 | err = tg3_init_5401phy_dsp(tp); | |
12087 | } | |
12088 | ||
747e8f8b | 12089 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) |
1da177e4 LT |
12090 | tp->link_config.advertising = |
12091 | (ADVERTISED_1000baseT_Half | | |
12092 | ADVERTISED_1000baseT_Full | | |
12093 | ADVERTISED_Autoneg | | |
12094 | ADVERTISED_FIBRE); | |
12095 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) | |
12096 | tp->link_config.advertising &= | |
12097 | ~(ADVERTISED_1000baseT_Half | | |
12098 | ADVERTISED_1000baseT_Full); | |
12099 | ||
12100 | return err; | |
12101 | } | |
12102 | ||
12103 | static void __devinit tg3_read_partno(struct tg3 *tp) | |
12104 | { | |
6d348f2c | 12105 | unsigned char vpd_data[256]; /* in little-endian format */ |
af2c6a4a | 12106 | unsigned int i; |
1b27777a | 12107 | u32 magic; |
1da177e4 | 12108 | |
df259d8c MC |
12109 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
12110 | tg3_nvram_read(tp, 0x0, &magic)) | |
f49639e6 | 12111 | goto out_not_found; |
1da177e4 | 12112 | |
1820180b | 12113 | if (magic == TG3_EEPROM_MAGIC) { |
1b27777a MC |
12114 | for (i = 0; i < 256; i += 4) { |
12115 | u32 tmp; | |
1da177e4 | 12116 | |
6d348f2c MC |
12117 | /* The data is in little-endian format in NVRAM. |
12118 | * Use the big-endian read routines to preserve | |
12119 | * the byte order as it exists in NVRAM. | |
12120 | */ | |
12121 | if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp)) | |
1b27777a MC |
12122 | goto out_not_found; |
12123 | ||
6d348f2c | 12124 | memcpy(&vpd_data[i], &tmp, sizeof(tmp)); |
1b27777a MC |
12125 | } |
12126 | } else { | |
12127 | int vpd_cap; | |
12128 | ||
12129 | vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD); | |
12130 | for (i = 0; i < 256; i += 4) { | |
12131 | u32 tmp, j = 0; | |
b9fc7dc5 | 12132 | __le32 v; |
1b27777a MC |
12133 | u16 tmp16; |
12134 | ||
12135 | pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR, | |
12136 | i); | |
12137 | while (j++ < 100) { | |
12138 | pci_read_config_word(tp->pdev, vpd_cap + | |
12139 | PCI_VPD_ADDR, &tmp16); | |
12140 | if (tmp16 & 0x8000) | |
12141 | break; | |
12142 | msleep(1); | |
12143 | } | |
f49639e6 DM |
12144 | if (!(tmp16 & 0x8000)) |
12145 | goto out_not_found; | |
12146 | ||
1b27777a MC |
12147 | pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA, |
12148 | &tmp); | |
b9fc7dc5 | 12149 | v = cpu_to_le32(tmp); |
6d348f2c | 12150 | memcpy(&vpd_data[i], &v, sizeof(v)); |
1b27777a | 12151 | } |
1da177e4 LT |
12152 | } |
12153 | ||
12154 | /* Now parse and find the part number. */ | |
af2c6a4a | 12155 | for (i = 0; i < 254; ) { |
1da177e4 | 12156 | unsigned char val = vpd_data[i]; |
af2c6a4a | 12157 | unsigned int block_end; |
1da177e4 LT |
12158 | |
12159 | if (val == 0x82 || val == 0x91) { | |
12160 | i = (i + 3 + | |
12161 | (vpd_data[i + 1] + | |
12162 | (vpd_data[i + 2] << 8))); | |
12163 | continue; | |
12164 | } | |
12165 | ||
12166 | if (val != 0x90) | |
12167 | goto out_not_found; | |
12168 | ||
12169 | block_end = (i + 3 + | |
12170 | (vpd_data[i + 1] + | |
12171 | (vpd_data[i + 2] << 8))); | |
12172 | i += 3; | |
af2c6a4a MC |
12173 | |
12174 | if (block_end > 256) | |
12175 | goto out_not_found; | |
12176 | ||
12177 | while (i < (block_end - 2)) { | |
1da177e4 LT |
12178 | if (vpd_data[i + 0] == 'P' && |
12179 | vpd_data[i + 1] == 'N') { | |
12180 | int partno_len = vpd_data[i + 2]; | |
12181 | ||
af2c6a4a MC |
12182 | i += 3; |
12183 | if (partno_len > 24 || (partno_len + i) > 256) | |
1da177e4 LT |
12184 | goto out_not_found; |
12185 | ||
12186 | memcpy(tp->board_part_number, | |
af2c6a4a | 12187 | &vpd_data[i], partno_len); |
1da177e4 LT |
12188 | |
12189 | /* Success. */ | |
12190 | return; | |
12191 | } | |
af2c6a4a | 12192 | i += 3 + vpd_data[i + 2]; |
1da177e4 LT |
12193 | } |
12194 | ||
12195 | /* Part number not found. */ | |
12196 | goto out_not_found; | |
12197 | } | |
12198 | ||
12199 | out_not_found: | |
b5d3772c MC |
12200 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12201 | strcpy(tp->board_part_number, "BCM95906"); | |
df259d8c MC |
12202 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && |
12203 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
12204 | strcpy(tp->board_part_number, "BCM57780"); | |
12205 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
12206 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
12207 | strcpy(tp->board_part_number, "BCM57760"); | |
12208 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
12209 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
12210 | strcpy(tp->board_part_number, "BCM57790"); | |
5e7ccf20 MC |
12211 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && |
12212 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
12213 | strcpy(tp->board_part_number, "BCM57788"); | |
b5d3772c MC |
12214 | else |
12215 | strcpy(tp->board_part_number, "none"); | |
1da177e4 LT |
12216 | } |
12217 | ||
9c8a620e MC |
12218 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
12219 | { | |
12220 | u32 val; | |
12221 | ||
e4f34110 | 12222 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 12223 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 12224 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
12225 | val != 0) |
12226 | return 0; | |
12227 | ||
12228 | return 1; | |
12229 | } | |
12230 | ||
acd9c119 MC |
12231 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
12232 | { | |
ff3a7cb2 | 12233 | u32 val, offset, start, ver_offset; |
acd9c119 | 12234 | int i; |
ff3a7cb2 | 12235 | bool newver = false; |
acd9c119 MC |
12236 | |
12237 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
12238 | tg3_nvram_read(tp, 0x4, &start)) | |
12239 | return; | |
12240 | ||
12241 | offset = tg3_nvram_logical_addr(tp, offset); | |
12242 | ||
ff3a7cb2 | 12243 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
12244 | return; |
12245 | ||
ff3a7cb2 MC |
12246 | if ((val & 0xfc000000) == 0x0c000000) { |
12247 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
12248 | return; |
12249 | ||
ff3a7cb2 MC |
12250 | if (val == 0) |
12251 | newver = true; | |
12252 | } | |
12253 | ||
12254 | if (newver) { | |
12255 | if (tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
12256 | return; | |
12257 | ||
12258 | offset = offset + ver_offset - start; | |
12259 | for (i = 0; i < 16; i += 4) { | |
12260 | __be32 v; | |
12261 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
12262 | return; | |
12263 | ||
12264 | memcpy(tp->fw_ver + i, &v, sizeof(v)); | |
12265 | } | |
12266 | } else { | |
12267 | u32 major, minor; | |
12268 | ||
12269 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
12270 | return; | |
12271 | ||
12272 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
12273 | TG3_NVM_BCVER_MAJSFT; | |
12274 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
12275 | snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor); | |
acd9c119 MC |
12276 | } |
12277 | } | |
12278 | ||
a6f6cb1c MC |
12279 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
12280 | { | |
12281 | u32 val, major, minor; | |
12282 | ||
12283 | /* Use native endian representation */ | |
12284 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
12285 | return; | |
12286 | ||
12287 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
12288 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
12289 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
12290 | TG3_NVM_HWSB_CFG1_MINSFT; | |
12291 | ||
12292 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
12293 | } | |
12294 | ||
dfe00d7d MC |
12295 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
12296 | { | |
12297 | u32 offset, major, minor, build; | |
12298 | ||
12299 | tp->fw_ver[0] = 's'; | |
12300 | tp->fw_ver[1] = 'b'; | |
12301 | tp->fw_ver[2] = '\0'; | |
12302 | ||
12303 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
12304 | return; | |
12305 | ||
12306 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
12307 | case TG3_EEPROM_SB_REVISION_0: | |
12308 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
12309 | break; | |
12310 | case TG3_EEPROM_SB_REVISION_2: | |
12311 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
12312 | break; | |
12313 | case TG3_EEPROM_SB_REVISION_3: | |
12314 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
12315 | break; | |
12316 | default: | |
12317 | return; | |
12318 | } | |
12319 | ||
e4f34110 | 12320 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
12321 | return; |
12322 | ||
12323 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
12324 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
12325 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
12326 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
12327 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
12328 | ||
12329 | if (minor > 99 || build > 26) | |
12330 | return; | |
12331 | ||
12332 | snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor); | |
12333 | ||
12334 | if (build > 0) { | |
12335 | tp->fw_ver[8] = 'a' + build - 1; | |
12336 | tp->fw_ver[9] = '\0'; | |
12337 | } | |
12338 | } | |
12339 | ||
acd9c119 | 12340 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
12341 | { |
12342 | u32 val, offset, start; | |
acd9c119 | 12343 | int i, vlen; |
9c8a620e MC |
12344 | |
12345 | for (offset = TG3_NVM_DIR_START; | |
12346 | offset < TG3_NVM_DIR_END; | |
12347 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 12348 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
12349 | return; |
12350 | ||
9c8a620e MC |
12351 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
12352 | break; | |
12353 | } | |
12354 | ||
12355 | if (offset == TG3_NVM_DIR_END) | |
12356 | return; | |
12357 | ||
12358 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
12359 | start = 0x08000000; | |
e4f34110 | 12360 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
12361 | return; |
12362 | ||
e4f34110 | 12363 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 12364 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 12365 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
12366 | return; |
12367 | ||
12368 | offset += val - start; | |
12369 | ||
acd9c119 | 12370 | vlen = strlen(tp->fw_ver); |
9c8a620e | 12371 | |
acd9c119 MC |
12372 | tp->fw_ver[vlen++] = ','; |
12373 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
12374 | |
12375 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
12376 | __be32 v; |
12377 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
12378 | return; |
12379 | ||
b9fc7dc5 | 12380 | offset += sizeof(v); |
c4e6575c | 12381 | |
acd9c119 MC |
12382 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
12383 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 12384 | break; |
c4e6575c | 12385 | } |
9c8a620e | 12386 | |
acd9c119 MC |
12387 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
12388 | vlen += sizeof(v); | |
c4e6575c | 12389 | } |
acd9c119 MC |
12390 | } |
12391 | ||
7fd76445 MC |
12392 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
12393 | { | |
12394 | int vlen; | |
12395 | u32 apedata; | |
12396 | ||
12397 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || | |
12398 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
12399 | return; | |
12400 | ||
12401 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
12402 | if (apedata != APE_SEG_SIG_MAGIC) | |
12403 | return; | |
12404 | ||
12405 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
12406 | if (!(apedata & APE_FW_STATUS_READY)) | |
12407 | return; | |
12408 | ||
12409 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
12410 | ||
12411 | vlen = strlen(tp->fw_ver); | |
12412 | ||
12413 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d", | |
12414 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, | |
12415 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
12416 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
12417 | (apedata & APE_FW_VERSION_BLDMSK)); | |
12418 | } | |
12419 | ||
acd9c119 MC |
12420 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
12421 | { | |
12422 | u32 val; | |
12423 | ||
df259d8c MC |
12424 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { |
12425 | tp->fw_ver[0] = 's'; | |
12426 | tp->fw_ver[1] = 'b'; | |
12427 | tp->fw_ver[2] = '\0'; | |
12428 | ||
12429 | return; | |
12430 | } | |
12431 | ||
acd9c119 MC |
12432 | if (tg3_nvram_read(tp, 0, &val)) |
12433 | return; | |
12434 | ||
12435 | if (val == TG3_EEPROM_MAGIC) | |
12436 | tg3_read_bc_ver(tp); | |
12437 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
12438 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
12439 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
12440 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
12441 | else |
12442 | return; | |
12443 | ||
12444 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
12445 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
12446 | return; | |
12447 | ||
12448 | tg3_read_mgmtfw_ver(tp); | |
9c8a620e MC |
12449 | |
12450 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; | |
c4e6575c MC |
12451 | } |
12452 | ||
7544b097 MC |
12453 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
12454 | ||
1da177e4 LT |
12455 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
12456 | { | |
12457 | static struct pci_device_id write_reorder_chipsets[] = { | |
1da177e4 LT |
12458 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, |
12459 | PCI_DEVICE_ID_AMD_FE_GATE_700C) }, | |
c165b004 JL |
12460 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, |
12461 | PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
399de50b MC |
12462 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, |
12463 | PCI_DEVICE_ID_VIA_8385_0) }, | |
1da177e4 LT |
12464 | { }, |
12465 | }; | |
12466 | u32 misc_ctrl_reg; | |
1da177e4 LT |
12467 | u32 pci_state_reg, grc_misc_cfg; |
12468 | u32 val; | |
12469 | u16 pci_cmd; | |
5e7dfd0f | 12470 | int err; |
1da177e4 | 12471 | |
1da177e4 LT |
12472 | /* Force memory write invalidate off. If we leave it on, |
12473 | * then on 5700_BX chips we have to enable a workaround. | |
12474 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
12475 | * to match the cacheline size. The Broadcom driver have this | |
12476 | * workaround but turns MWI off all the times so never uses | |
12477 | * it. This seems to suggest that the workaround is insufficient. | |
12478 | */ | |
12479 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
12480 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
12481 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
12482 | ||
12483 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
12484 | * has the register indirect write enable bit set before | |
12485 | * we try to access any of the MMIO registers. It is also | |
12486 | * critical that the PCI-X hw workaround situation is decided | |
12487 | * before that as well. | |
12488 | */ | |
12489 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12490 | &misc_ctrl_reg); | |
12491 | ||
12492 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
12493 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
12494 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
12495 | u32 prod_id_asic_rev; | |
12496 | ||
f6eb9b1f MC |
12497 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C || |
12498 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S || | |
12499 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C || | |
12500 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S) | |
12501 | pci_read_config_dword(tp->pdev, | |
12502 | TG3PCI_GEN2_PRODID_ASICREV, | |
12503 | &prod_id_asic_rev); | |
12504 | else | |
12505 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
12506 | &prod_id_asic_rev); | |
12507 | ||
321d32a0 | 12508 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 12509 | } |
1da177e4 | 12510 | |
ff645bec MC |
12511 | /* Wrong chip ID in 5752 A0. This code can be removed later |
12512 | * as A0 is not in production. | |
12513 | */ | |
12514 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
12515 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
12516 | ||
6892914f MC |
12517 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
12518 | * we need to disable memory and use config. cycles | |
12519 | * only to access all registers. The 5702/03 chips | |
12520 | * can mistakenly decode the special cycles from the | |
12521 | * ICH chipsets as memory write cycles, causing corruption | |
12522 | * of register and memory space. Only certain ICH bridges | |
12523 | * will drive special cycles with non-zero data during the | |
12524 | * address phase which can fall within the 5703's address | |
12525 | * range. This is not an ICH bug as the PCI spec allows | |
12526 | * non-zero address during special cycles. However, only | |
12527 | * these ICH bridges are known to drive non-zero addresses | |
12528 | * during special cycles. | |
12529 | * | |
12530 | * Since special cycles do not cross PCI bridges, we only | |
12531 | * enable this workaround if the 5703 is on the secondary | |
12532 | * bus of these ICH bridges. | |
12533 | */ | |
12534 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
12535 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
12536 | static struct tg3_dev_id { | |
12537 | u32 vendor; | |
12538 | u32 device; | |
12539 | u32 rev; | |
12540 | } ich_chipsets[] = { | |
12541 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
12542 | PCI_ANY_ID }, | |
12543 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
12544 | PCI_ANY_ID }, | |
12545 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
12546 | 0xa }, | |
12547 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
12548 | PCI_ANY_ID }, | |
12549 | { }, | |
12550 | }; | |
12551 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
12552 | struct pci_dev *bridge = NULL; | |
12553 | ||
12554 | while (pci_id->vendor != 0) { | |
12555 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
12556 | bridge); | |
12557 | if (!bridge) { | |
12558 | pci_id++; | |
12559 | continue; | |
12560 | } | |
12561 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 12562 | if (bridge->revision > pci_id->rev) |
6892914f MC |
12563 | continue; |
12564 | } | |
12565 | if (bridge->subordinate && | |
12566 | (bridge->subordinate->number == | |
12567 | tp->pdev->bus->number)) { | |
12568 | ||
12569 | tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND; | |
12570 | pci_dev_put(bridge); | |
12571 | break; | |
12572 | } | |
12573 | } | |
12574 | } | |
12575 | ||
41588ba1 MC |
12576 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { |
12577 | static struct tg3_dev_id { | |
12578 | u32 vendor; | |
12579 | u32 device; | |
12580 | } bridge_chipsets[] = { | |
12581 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
12582 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
12583 | { }, | |
12584 | }; | |
12585 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
12586 | struct pci_dev *bridge = NULL; | |
12587 | ||
12588 | while (pci_id->vendor != 0) { | |
12589 | bridge = pci_get_device(pci_id->vendor, | |
12590 | pci_id->device, | |
12591 | bridge); | |
12592 | if (!bridge) { | |
12593 | pci_id++; | |
12594 | continue; | |
12595 | } | |
12596 | if (bridge->subordinate && | |
12597 | (bridge->subordinate->number <= | |
12598 | tp->pdev->bus->number) && | |
12599 | (bridge->subordinate->subordinate >= | |
12600 | tp->pdev->bus->number)) { | |
12601 | tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; | |
12602 | pci_dev_put(bridge); | |
12603 | break; | |
12604 | } | |
12605 | } | |
12606 | } | |
12607 | ||
4a29cc2e MC |
12608 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
12609 | * DMA addresses > 40-bit. This bridge may have other additional | |
12610 | * 57xx devices behind it in some 4-port NIC designs for example. | |
12611 | * Any tg3 device found behind the bridge will also need the 40-bit | |
12612 | * DMA workaround. | |
12613 | */ | |
a4e2b347 MC |
12614 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
12615 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
12616 | tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; | |
4a29cc2e | 12617 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; |
4cf78e4f | 12618 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
a4e2b347 | 12619 | } |
4a29cc2e MC |
12620 | else { |
12621 | struct pci_dev *bridge = NULL; | |
12622 | ||
12623 | do { | |
12624 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
12625 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
12626 | bridge); | |
12627 | if (bridge && bridge->subordinate && | |
12628 | (bridge->subordinate->number <= | |
12629 | tp->pdev->bus->number) && | |
12630 | (bridge->subordinate->subordinate >= | |
12631 | tp->pdev->bus->number)) { | |
12632 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
12633 | pci_dev_put(bridge); | |
12634 | break; | |
12635 | } | |
12636 | } while (bridge); | |
12637 | } | |
4cf78e4f | 12638 | |
1da177e4 LT |
12639 | /* Initialize misc host control in PCI block. */ |
12640 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
12641 | MISC_HOST_CTRL_CHIPREV); | |
12642 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12643 | tp->misc_host_ctrl); | |
12644 | ||
f6eb9b1f MC |
12645 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
12646 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
12647 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
7544b097 MC |
12648 | tp->pdev_peer = tg3_find_peer(tp); |
12649 | ||
321d32a0 MC |
12650 | /* Intentionally exclude ASIC_REV_5906 */ |
12651 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 12652 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 12653 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 12654 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 12655 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f MC |
12656 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12657 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
321d32a0 MC |
12658 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; |
12659 | ||
12660 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
12661 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 12662 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
321d32a0 | 12663 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
a4e2b347 | 12664 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
6708e5cc JL |
12665 | tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; |
12666 | ||
1b440c56 JL |
12667 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || |
12668 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
12669 | tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; | |
12670 | ||
027455ad MC |
12671 | /* 5700 B0 chips do not support checksumming correctly due |
12672 | * to hardware bugs. | |
12673 | */ | |
12674 | if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0) | |
12675 | tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS; | |
12676 | else { | |
12677 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
12678 | tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; | |
12679 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
12680 | tp->dev->features |= NETIF_F_IPV6_CSUM; | |
12681 | } | |
12682 | ||
507399f1 | 12683 | /* Determine TSO capabilities */ |
e849cdc3 MC |
12684 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
12685 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; | |
12686 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
12687 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
507399f1 MC |
12688 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; |
12689 | else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
12690 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; | |
12691 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && | |
12692 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
12693 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; | |
12694 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12695 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
12696 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
12697 | tp->tg3_flags2 |= TG3_FLG2_TSO_BUG; | |
12698 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | |
12699 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
12700 | else | |
12701 | tp->fw_needed = FIRMWARE_TG3TSO; | |
12702 | } | |
12703 | ||
12704 | tp->irq_max = 1; | |
12705 | ||
5a6f3074 | 12706 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7544b097 MC |
12707 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; |
12708 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
12709 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
12710 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
12711 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
12712 | tp->pdev_peer == tp->pdev)) | |
12713 | tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; | |
12714 | ||
321d32a0 | 12715 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
b5d3772c | 12716 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
fcfa0a32 | 12717 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; |
52c0fd83 | 12718 | } |
4f125f42 | 12719 | |
507399f1 MC |
12720 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
12721 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; | |
12722 | tp->irq_max = TG3_IRQ_MAX_VECS; | |
12723 | } | |
f6eb9b1f | 12724 | } |
0e1406dd | 12725 | |
615774fe MC |
12726 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12727 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
12728 | tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG; | |
12729 | else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) { | |
12730 | tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG; | |
12731 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | |
0e1406dd | 12732 | } |
f6eb9b1f | 12733 | |
f51f3562 | 12734 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
f6eb9b1f MC |
12735 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
12736 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
8f666b07 | 12737 | tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; |
0f893dc6 | 12738 | |
52f4490c MC |
12739 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
12740 | &pci_state_reg); | |
12741 | ||
5e7dfd0f MC |
12742 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); |
12743 | if (tp->pcie_cap != 0) { | |
12744 | u16 lnkctl; | |
12745 | ||
1da177e4 | 12746 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
5f5c51e3 MC |
12747 | |
12748 | pcie_set_readrq(tp->pdev, 4096); | |
12749 | ||
5e7dfd0f MC |
12750 | pci_read_config_word(tp->pdev, |
12751 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
12752 | &lnkctl); | |
12753 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
12754 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
c7835a77 | 12755 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; |
5e7dfd0f | 12756 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 12757 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
12758 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
12759 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
5e7dfd0f | 12760 | tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; |
c7835a77 | 12761 | } |
52f4490c | 12762 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
fcb389df | 12763 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
52f4490c MC |
12764 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
12765 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
12766 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
12767 | if (!tp->pcix_cap) { | |
12768 | printk(KERN_ERR PFX "Cannot find PCI-X " | |
12769 | "capability, aborting.\n"); | |
12770 | return -EIO; | |
12771 | } | |
12772 | ||
12773 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
12774 | tp->tg3_flags |= TG3_FLAG_PCIX_MODE; | |
12775 | } | |
1da177e4 | 12776 | |
399de50b MC |
12777 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
12778 | * reordering to the mailbox registers done by the host | |
12779 | * controller can cause major troubles. We read back from | |
12780 | * every mailbox register write to force the writes to be | |
12781 | * posted to the chip in order. | |
12782 | */ | |
12783 | if (pci_dev_present(write_reorder_chipsets) && | |
12784 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
12785 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
12786 | ||
69fc4053 MC |
12787 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
12788 | &tp->pci_cacheline_sz); | |
12789 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
12790 | &tp->pci_lat_timer); | |
1da177e4 LT |
12791 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
12792 | tp->pci_lat_timer < 64) { | |
12793 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
12794 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
12795 | tp->pci_lat_timer); | |
1da177e4 LT |
12796 | } |
12797 | ||
52f4490c MC |
12798 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
12799 | /* 5700 BX chips need to have their TX producer index | |
12800 | * mailboxes written twice to workaround a bug. | |
12801 | */ | |
12802 | tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; | |
1da177e4 | 12803 | |
52f4490c | 12804 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
12805 | * |
12806 | * The workaround is to use indirect register accesses | |
12807 | * for all chip writes not to mailbox registers. | |
12808 | */ | |
52f4490c | 12809 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
1da177e4 | 12810 | u32 pm_reg; |
1da177e4 LT |
12811 | |
12812 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
12813 | ||
12814 | /* The chip can have it's power management PCI config | |
12815 | * space registers clobbered due to this bug. | |
12816 | * So explicitly force the chip into D0 here. | |
12817 | */ | |
9974a356 MC |
12818 | pci_read_config_dword(tp->pdev, |
12819 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
12820 | &pm_reg); |
12821 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
12822 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
12823 | pci_write_config_dword(tp->pdev, |
12824 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
12825 | pm_reg); |
12826 | ||
12827 | /* Also, force SERR#/PERR# in PCI command. */ | |
12828 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
12829 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
12830 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
12831 | } | |
12832 | } | |
12833 | ||
1da177e4 LT |
12834 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
12835 | tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; | |
12836 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
12837 | tp->tg3_flags |= TG3_FLAG_PCI_32BIT; | |
12838 | ||
12839 | /* Chip-specific fixup from Broadcom driver */ | |
12840 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
12841 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
12842 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
12843 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
12844 | } | |
12845 | ||
1ee582d8 | 12846 | /* Default fast path register access methods */ |
20094930 | 12847 | tp->read32 = tg3_read32; |
1ee582d8 | 12848 | tp->write32 = tg3_write32; |
09ee929c | 12849 | tp->read32_mbox = tg3_read32; |
20094930 | 12850 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
12851 | tp->write32_tx_mbox = tg3_write32; |
12852 | tp->write32_rx_mbox = tg3_write32; | |
12853 | ||
12854 | /* Various workaround register access methods */ | |
12855 | if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) | |
12856 | tp->write32 = tg3_write_indirect_reg32; | |
98efd8a6 MC |
12857 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
12858 | ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
12859 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
12860 | /* | |
12861 | * Back to back register writes can cause problems on these | |
12862 | * chips, the workaround is to read back all reg writes | |
12863 | * except those to mailbox regs. | |
12864 | * | |
12865 | * See tg3_write_indirect_reg32(). | |
12866 | */ | |
1ee582d8 | 12867 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
12868 | } |
12869 | ||
1ee582d8 MC |
12870 | if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || |
12871 | (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { | |
12872 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
12873 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
12874 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
12875 | } | |
20094930 | 12876 | |
6892914f MC |
12877 | if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { |
12878 | tp->read32 = tg3_read_indirect_reg32; | |
12879 | tp->write32 = tg3_write_indirect_reg32; | |
12880 | tp->read32_mbox = tg3_read_indirect_mbox; | |
12881 | tp->write32_mbox = tg3_write_indirect_mbox; | |
12882 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
12883 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
12884 | ||
12885 | iounmap(tp->regs); | |
22abe310 | 12886 | tp->regs = NULL; |
6892914f MC |
12887 | |
12888 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
12889 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
12890 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
12891 | } | |
b5d3772c MC |
12892 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
12893 | tp->read32_mbox = tg3_read32_mbox_5906; | |
12894 | tp->write32_mbox = tg3_write32_mbox_5906; | |
12895 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
12896 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
12897 | } | |
6892914f | 12898 | |
bbadf503 MC |
12899 | if (tp->write32 == tg3_write_indirect_reg32 || |
12900 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
12901 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
f49639e6 | 12902 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
bbadf503 MC |
12903 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; |
12904 | ||
7d0c41ef | 12905 | /* Get eeprom hw config before calling tg3_set_power_state(). |
9d26e213 | 12906 | * In particular, the TG3_FLG2_IS_NIC flag must be |
7d0c41ef MC |
12907 | * determined before calling tg3_set_power_state() so that |
12908 | * we know whether or not to switch out of Vaux power. | |
12909 | * When the flag is set, it means that GPIO1 is used for eeprom | |
12910 | * write protect and also implies that it is a LOM where GPIOs | |
12911 | * are not used to switch power. | |
6aa20a22 | 12912 | */ |
7d0c41ef MC |
12913 | tg3_get_eeprom_hw_cfg(tp); |
12914 | ||
0d3031d9 MC |
12915 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
12916 | /* Allow reads and writes to the | |
12917 | * APE register and memory space. | |
12918 | */ | |
12919 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
12920 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
12921 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
12922 | pci_state_reg); | |
12923 | } | |
12924 | ||
9936bcf6 | 12925 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 12926 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 12927 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f MC |
12928 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12929 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
d30cdd28 MC |
12930 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; |
12931 | ||
314fba34 MC |
12932 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). |
12933 | * GPIO1 driven high will bring 5700's external PHY out of reset. | |
12934 | * It is also used as eeprom write protect on LOMs. | |
12935 | */ | |
12936 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
12937 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
12938 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | |
12939 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
12940 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
12941 | /* Unused GPIO3 must be driven as output on 5752 because there |
12942 | * are no pull-up resistors on unused GPIO pins. | |
12943 | */ | |
12944 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
12945 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 12946 | |
321d32a0 MC |
12947 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
12948 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
af36e6b6 MC |
12949 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
12950 | ||
8d519ab2 MC |
12951 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
12952 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
12953 | /* Turn off the debug UART. */ |
12954 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
12955 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
12956 | /* Keep VMain power. */ | |
12957 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
12958 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
12959 | } | |
12960 | ||
1da177e4 | 12961 | /* Force the chip into D0. */ |
bc1c7567 | 12962 | err = tg3_set_power_state(tp, PCI_D0); |
1da177e4 LT |
12963 | if (err) { |
12964 | printk(KERN_ERR PFX "(%s) transition to D0 failed\n", | |
12965 | pci_name(tp->pdev)); | |
12966 | return err; | |
12967 | } | |
12968 | ||
1da177e4 LT |
12969 | /* Derive initial jumbo mode from MTU assigned in |
12970 | * ether_setup() via the alloc_etherdev() call | |
12971 | */ | |
0f893dc6 | 12972 | if (tp->dev->mtu > ETH_DATA_LEN && |
a4e2b347 | 12973 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
0f893dc6 | 12974 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
1da177e4 LT |
12975 | |
12976 | /* Determine WakeOnLan speed to use. */ | |
12977 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12978 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
12979 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
12980 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
12981 | tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); | |
12982 | } else { | |
12983 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | |
12984 | } | |
12985 | ||
7f97a4bd MC |
12986 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12987 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; | |
12988 | ||
1da177e4 LT |
12989 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
12990 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
12991 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
12992 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
747e8f8b | 12993 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
7f97a4bd | 12994 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) || |
747e8f8b | 12995 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) |
1da177e4 LT |
12996 | tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; |
12997 | ||
12998 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
12999 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
13000 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG; | |
13001 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) | |
13002 | tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; | |
13003 | ||
321d32a0 | 13004 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
7f97a4bd | 13005 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && |
321d32a0 | 13006 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f MC |
13007 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
13008 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) { | |
c424cb24 | 13009 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 13010 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
13011 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
13012 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
13013 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
13014 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
13015 | tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; | |
c1d2a196 MC |
13016 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
13017 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM; | |
321d32a0 | 13018 | } else |
c424cb24 MC |
13019 | tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; |
13020 | } | |
1da177e4 | 13021 | |
b2a5c19c MC |
13022 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
13023 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
13024 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
13025 | if (tp->phy_otp == 0) | |
13026 | tp->phy_otp = TG3_OTP_DEFAULT; | |
13027 | } | |
13028 | ||
f51f3562 | 13029 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) |
8ef21428 MC |
13030 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
13031 | else | |
13032 | tp->mi_mode = MAC_MI_MODE_BASE; | |
13033 | ||
1da177e4 | 13034 | tp->coalesce_mode = 0; |
1da177e4 LT |
13035 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
13036 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
13037 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
13038 | ||
321d32a0 MC |
13039 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
13040 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
57e6983c MC |
13041 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; |
13042 | ||
158d7abd MC |
13043 | err = tg3_mdio_init(tp); |
13044 | if (err) | |
13045 | return err; | |
1da177e4 LT |
13046 | |
13047 | /* Initialize data/descriptor byte/word swapping. */ | |
13048 | val = tr32(GRC_MODE); | |
13049 | val &= GRC_MODE_HOST_STACKUP; | |
13050 | tw32(GRC_MODE, val | tp->grc_mode); | |
13051 | ||
13052 | tg3_switch_clocks(tp); | |
13053 | ||
13054 | /* Clear this out for sanity. */ | |
13055 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
13056 | ||
13057 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13058 | &pci_state_reg); | |
13059 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
13060 | (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { | |
13061 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
13062 | ||
13063 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
13064 | chiprevid == CHIPREV_ID_5701_B0 || | |
13065 | chiprevid == CHIPREV_ID_5701_B2 || | |
13066 | chiprevid == CHIPREV_ID_5701_B5) { | |
13067 | void __iomem *sram_base; | |
13068 | ||
13069 | /* Write some dummy words into the SRAM status block | |
13070 | * area, see if it reads back correctly. If the return | |
13071 | * value is bad, force enable the PCIX workaround. | |
13072 | */ | |
13073 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
13074 | ||
13075 | writel(0x00000000, sram_base); | |
13076 | writel(0x00000000, sram_base + 4); | |
13077 | writel(0xffffffff, sram_base + 4); | |
13078 | if (readl(sram_base) != 0x00000000) | |
13079 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13080 | } | |
13081 | } | |
13082 | ||
13083 | udelay(50); | |
13084 | tg3_nvram_init(tp); | |
13085 | ||
13086 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
13087 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
13088 | ||
1da177e4 LT |
13089 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
13090 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
13091 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
13092 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | |
13093 | ||
fac9b83e DM |
13094 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && |
13095 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | |
13096 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | |
13097 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
13098 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
13099 | HOSTCC_MODE_CLRTICK_TXBD); | |
13100 | ||
13101 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
13102 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13103 | tp->misc_host_ctrl); | |
13104 | } | |
13105 | ||
3bda1258 MC |
13106 | /* Preserve the APE MAC_MODE bits */ |
13107 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
13108 | tp->mac_mode = tr32(MAC_MODE) | | |
13109 | MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
13110 | else | |
13111 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
13112 | ||
1da177e4 LT |
13113 | /* these are limited to 10/100 only */ |
13114 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
13115 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
13116 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
13117 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13118 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
13119 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
13120 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
13121 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13122 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
13123 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
13124 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 13125 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
7f97a4bd | 13126 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) |
1da177e4 LT |
13127 | tp->tg3_flags |= TG3_FLAG_10_100_ONLY; |
13128 | ||
13129 | err = tg3_phy_probe(tp); | |
13130 | if (err) { | |
13131 | printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n", | |
13132 | pci_name(tp->pdev), err); | |
13133 | /* ... but do not return immediately ... */ | |
b02fd9e3 | 13134 | tg3_mdio_fini(tp); |
1da177e4 LT |
13135 | } |
13136 | ||
13137 | tg3_read_partno(tp); | |
c4e6575c | 13138 | tg3_read_fw_ver(tp); |
1da177e4 LT |
13139 | |
13140 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
13141 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
13142 | } else { | |
13143 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
13144 | tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT; | |
13145 | else | |
13146 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
13147 | } | |
13148 | ||
13149 | /* 5700 {AX,BX} chips have a broken status block link | |
13150 | * change bit implementation, so we must use the | |
13151 | * status register in those cases. | |
13152 | */ | |
13153 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
13154 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
13155 | else | |
13156 | tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; | |
13157 | ||
13158 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
13159 | * have to force the link status polling mechanism based | |
13160 | * upon subsystem IDs. | |
13161 | */ | |
13162 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 13163 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
1da177e4 LT |
13164 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { |
13165 | tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT | | |
13166 | TG3_FLAG_USE_LINKCHG_REG); | |
13167 | } | |
13168 | ||
13169 | /* For all SERDES we poll the MAC status register. */ | |
13170 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
13171 | tp->tg3_flags |= TG3_FLAG_POLL_SERDES; | |
13172 | else | |
13173 | tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; | |
13174 | ||
ad829268 | 13175 | tp->rx_offset = NET_IP_ALIGN; |
1da177e4 LT |
13176 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
13177 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) | |
13178 | tp->rx_offset = 0; | |
13179 | ||
f92905de MC |
13180 | tp->rx_std_max_post = TG3_RX_RING_SIZE; |
13181 | ||
13182 | /* Increment the rx prod index on the rx std ring by at most | |
13183 | * 8 for these chips to workaround hw errata. | |
13184 | */ | |
13185 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13186 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
13187 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
13188 | tp->rx_std_max_post = 8; | |
13189 | ||
8ed5d97e MC |
13190 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) |
13191 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
13192 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
13193 | ||
1da177e4 LT |
13194 | return err; |
13195 | } | |
13196 | ||
49b6e95f | 13197 | #ifdef CONFIG_SPARC |
1da177e4 LT |
13198 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
13199 | { | |
13200 | struct net_device *dev = tp->dev; | |
13201 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 13202 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 13203 | const unsigned char *addr; |
49b6e95f DM |
13204 | int len; |
13205 | ||
13206 | addr = of_get_property(dp, "local-mac-address", &len); | |
13207 | if (addr && len == 6) { | |
13208 | memcpy(dev->dev_addr, addr, 6); | |
13209 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
13210 | return 0; | |
1da177e4 LT |
13211 | } |
13212 | return -ENODEV; | |
13213 | } | |
13214 | ||
13215 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
13216 | { | |
13217 | struct net_device *dev = tp->dev; | |
13218 | ||
13219 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 13220 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
13221 | return 0; |
13222 | } | |
13223 | #endif | |
13224 | ||
13225 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
13226 | { | |
13227 | struct net_device *dev = tp->dev; | |
13228 | u32 hi, lo, mac_offset; | |
008652b3 | 13229 | int addr_ok = 0; |
1da177e4 | 13230 | |
49b6e95f | 13231 | #ifdef CONFIG_SPARC |
1da177e4 LT |
13232 | if (!tg3_get_macaddr_sparc(tp)) |
13233 | return 0; | |
13234 | #endif | |
13235 | ||
13236 | mac_offset = 0x7c; | |
f49639e6 | 13237 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
a4e2b347 | 13238 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
13239 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
13240 | mac_offset = 0xcc; | |
13241 | if (tg3_nvram_lock(tp)) | |
13242 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
13243 | else | |
13244 | tg3_nvram_unlock(tp); | |
a1b950d5 MC |
13245 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13246 | if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC) | |
13247 | mac_offset = 0xcc; | |
13248 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
b5d3772c | 13249 | mac_offset = 0x10; |
1da177e4 LT |
13250 | |
13251 | /* First try to get it from MAC address mailbox. */ | |
13252 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
13253 | if ((hi >> 16) == 0x484b) { | |
13254 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
13255 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
13256 | ||
13257 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
13258 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
13259 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
13260 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
13261 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 13262 | |
008652b3 MC |
13263 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
13264 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
13265 | } | |
13266 | if (!addr_ok) { | |
13267 | /* Next, try NVRAM. */ | |
df259d8c MC |
13268 | if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && |
13269 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && | |
6d348f2c | 13270 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
13271 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
13272 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
13273 | } |
13274 | /* Finally just fetch it out of the MAC control regs. */ | |
13275 | else { | |
13276 | hi = tr32(MAC_ADDR_0_HIGH); | |
13277 | lo = tr32(MAC_ADDR_0_LOW); | |
13278 | ||
13279 | dev->dev_addr[5] = lo & 0xff; | |
13280 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
13281 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
13282 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
13283 | dev->dev_addr[1] = hi & 0xff; | |
13284 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
13285 | } | |
1da177e4 LT |
13286 | } |
13287 | ||
13288 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 13289 | #ifdef CONFIG_SPARC |
1da177e4 LT |
13290 | if (!tg3_get_default_macaddr_sparc(tp)) |
13291 | return 0; | |
13292 | #endif | |
13293 | return -EINVAL; | |
13294 | } | |
2ff43697 | 13295 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
13296 | return 0; |
13297 | } | |
13298 | ||
59e6b434 DM |
13299 | #define BOUNDARY_SINGLE_CACHELINE 1 |
13300 | #define BOUNDARY_MULTI_CACHELINE 2 | |
13301 | ||
13302 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
13303 | { | |
13304 | int cacheline_size; | |
13305 | u8 byte; | |
13306 | int goal; | |
13307 | ||
13308 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
13309 | if (byte == 0) | |
13310 | cacheline_size = 1024; | |
13311 | else | |
13312 | cacheline_size = (int) byte * 4; | |
13313 | ||
13314 | /* On 5703 and later chips, the boundary bits have no | |
13315 | * effect. | |
13316 | */ | |
13317 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13318 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13319 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
13320 | goto out; | |
13321 | ||
13322 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
13323 | goal = BOUNDARY_MULTI_CACHELINE; | |
13324 | #else | |
13325 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
13326 | goal = BOUNDARY_SINGLE_CACHELINE; | |
13327 | #else | |
13328 | goal = 0; | |
13329 | #endif | |
13330 | #endif | |
13331 | ||
13332 | if (!goal) | |
13333 | goto out; | |
13334 | ||
13335 | /* PCI controllers on most RISC systems tend to disconnect | |
13336 | * when a device tries to burst across a cache-line boundary. | |
13337 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
13338 | * | |
13339 | * Unfortunately, for PCI-E there are only limited | |
13340 | * write-side controls for this, and thus for reads | |
13341 | * we will still get the disconnects. We'll also waste | |
13342 | * these PCI cycles for both read and write for chips | |
13343 | * other than 5700 and 5701 which do not implement the | |
13344 | * boundary bits. | |
13345 | */ | |
13346 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13347 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
13348 | switch (cacheline_size) { | |
13349 | case 16: | |
13350 | case 32: | |
13351 | case 64: | |
13352 | case 128: | |
13353 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13354 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
13355 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
13356 | } else { | |
13357 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
13358 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
13359 | } | |
13360 | break; | |
13361 | ||
13362 | case 256: | |
13363 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
13364 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
13365 | break; | |
13366 | ||
13367 | default: | |
13368 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
13369 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
13370 | break; | |
855e1111 | 13371 | } |
59e6b434 DM |
13372 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
13373 | switch (cacheline_size) { | |
13374 | case 16: | |
13375 | case 32: | |
13376 | case 64: | |
13377 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13378 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
13379 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
13380 | break; | |
13381 | } | |
13382 | /* fallthrough */ | |
13383 | case 128: | |
13384 | default: | |
13385 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
13386 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
13387 | break; | |
855e1111 | 13388 | } |
59e6b434 DM |
13389 | } else { |
13390 | switch (cacheline_size) { | |
13391 | case 16: | |
13392 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13393 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
13394 | DMA_RWCTRL_WRITE_BNDRY_16); | |
13395 | break; | |
13396 | } | |
13397 | /* fallthrough */ | |
13398 | case 32: | |
13399 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13400 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
13401 | DMA_RWCTRL_WRITE_BNDRY_32); | |
13402 | break; | |
13403 | } | |
13404 | /* fallthrough */ | |
13405 | case 64: | |
13406 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13407 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
13408 | DMA_RWCTRL_WRITE_BNDRY_64); | |
13409 | break; | |
13410 | } | |
13411 | /* fallthrough */ | |
13412 | case 128: | |
13413 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13414 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
13415 | DMA_RWCTRL_WRITE_BNDRY_128); | |
13416 | break; | |
13417 | } | |
13418 | /* fallthrough */ | |
13419 | case 256: | |
13420 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
13421 | DMA_RWCTRL_WRITE_BNDRY_256); | |
13422 | break; | |
13423 | case 512: | |
13424 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
13425 | DMA_RWCTRL_WRITE_BNDRY_512); | |
13426 | break; | |
13427 | case 1024: | |
13428 | default: | |
13429 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
13430 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
13431 | break; | |
855e1111 | 13432 | } |
59e6b434 DM |
13433 | } |
13434 | ||
13435 | out: | |
13436 | return val; | |
13437 | } | |
13438 | ||
1da177e4 LT |
13439 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
13440 | { | |
13441 | struct tg3_internal_buffer_desc test_desc; | |
13442 | u32 sram_dma_descs; | |
13443 | int i, ret; | |
13444 | ||
13445 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
13446 | ||
13447 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
13448 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
13449 | tw32(RDMAC_STATUS, 0); | |
13450 | tw32(WDMAC_STATUS, 0); | |
13451 | ||
13452 | tw32(BUFMGR_MODE, 0); | |
13453 | tw32(FTQ_RESET, 0); | |
13454 | ||
13455 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
13456 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
13457 | test_desc.nic_mbuf = 0x00002100; | |
13458 | test_desc.len = size; | |
13459 | ||
13460 | /* | |
13461 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
13462 | * the *second* time the tg3 driver was getting loaded after an | |
13463 | * initial scan. | |
13464 | * | |
13465 | * Broadcom tells me: | |
13466 | * ...the DMA engine is connected to the GRC block and a DMA | |
13467 | * reset may affect the GRC block in some unpredictable way... | |
13468 | * The behavior of resets to individual blocks has not been tested. | |
13469 | * | |
13470 | * Broadcom noted the GRC reset will also reset all sub-components. | |
13471 | */ | |
13472 | if (to_device) { | |
13473 | test_desc.cqid_sqid = (13 << 8) | 2; | |
13474 | ||
13475 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
13476 | udelay(40); | |
13477 | } else { | |
13478 | test_desc.cqid_sqid = (16 << 8) | 7; | |
13479 | ||
13480 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
13481 | udelay(40); | |
13482 | } | |
13483 | test_desc.flags = 0x00000005; | |
13484 | ||
13485 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
13486 | u32 val; | |
13487 | ||
13488 | val = *(((u32 *)&test_desc) + i); | |
13489 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
13490 | sram_dma_descs + (i * sizeof(u32))); | |
13491 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
13492 | } | |
13493 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
13494 | ||
13495 | if (to_device) { | |
13496 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); | |
13497 | } else { | |
13498 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); | |
13499 | } | |
13500 | ||
13501 | ret = -ENODEV; | |
13502 | for (i = 0; i < 40; i++) { | |
13503 | u32 val; | |
13504 | ||
13505 | if (to_device) | |
13506 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
13507 | else | |
13508 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
13509 | if ((val & 0xffff) == sram_dma_descs) { | |
13510 | ret = 0; | |
13511 | break; | |
13512 | } | |
13513 | ||
13514 | udelay(100); | |
13515 | } | |
13516 | ||
13517 | return ret; | |
13518 | } | |
13519 | ||
ded7340d | 13520 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 LT |
13521 | |
13522 | static int __devinit tg3_test_dma(struct tg3 *tp) | |
13523 | { | |
13524 | dma_addr_t buf_dma; | |
59e6b434 | 13525 | u32 *buf, saved_dma_rwctrl; |
1da177e4 LT |
13526 | int ret; |
13527 | ||
13528 | buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma); | |
13529 | if (!buf) { | |
13530 | ret = -ENOMEM; | |
13531 | goto out_nofree; | |
13532 | } | |
13533 | ||
13534 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
13535 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
13536 | ||
59e6b434 | 13537 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 LT |
13538 | |
13539 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
13540 | /* DMA read watermark not used on PCIE */ | |
13541 | tp->dma_rwctrl |= 0x00180000; | |
13542 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
85e94ced MC |
13543 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
13544 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
13545 | tp->dma_rwctrl |= 0x003f0000; |
13546 | else | |
13547 | tp->dma_rwctrl |= 0x003f000f; | |
13548 | } else { | |
13549 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
13550 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
13551 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 13552 | u32 read_water = 0x7; |
1da177e4 | 13553 | |
4a29cc2e MC |
13554 | /* If the 5704 is behind the EPB bridge, we can |
13555 | * do the less restrictive ONE_DMA workaround for | |
13556 | * better performance. | |
13557 | */ | |
13558 | if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && | |
13559 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
13560 | tp->dma_rwctrl |= 0x8000; | |
13561 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
13562 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
13563 | ||
49afdeb6 MC |
13564 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
13565 | read_water = 4; | |
59e6b434 | 13566 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
13567 | tp->dma_rwctrl |= |
13568 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
13569 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
13570 | (1 << 23); | |
4cf78e4f MC |
13571 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
13572 | /* 5780 always in PCIX mode */ | |
13573 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
13574 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
13575 | /* 5714 always in PCIX mode */ | |
13576 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
13577 | } else { |
13578 | tp->dma_rwctrl |= 0x001b000f; | |
13579 | } | |
13580 | } | |
13581 | ||
13582 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
13583 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
13584 | tp->dma_rwctrl &= 0xfffffff0; | |
13585 | ||
13586 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13587 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
13588 | /* Remove this if it causes problems for some boards. */ | |
13589 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
13590 | ||
13591 | /* On 5700/5701 chips, we need to set this bit. | |
13592 | * Otherwise the chip will issue cacheline transactions | |
13593 | * to streamable DMA memory with not all the byte | |
13594 | * enables turned on. This is an error on several | |
13595 | * RISC PCI controllers, in particular sparc64. | |
13596 | * | |
13597 | * On 5703/5704 chips, this bit has been reassigned | |
13598 | * a different meaning. In particular, it is used | |
13599 | * on those chips to enable a PCI-X workaround. | |
13600 | */ | |
13601 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
13602 | } | |
13603 | ||
13604 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
13605 | ||
13606 | #if 0 | |
13607 | /* Unneeded, already done by tg3_get_invariants. */ | |
13608 | tg3_switch_clocks(tp); | |
13609 | #endif | |
13610 | ||
13611 | ret = 0; | |
13612 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13613 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
13614 | goto out; | |
13615 | ||
59e6b434 DM |
13616 | /* It is best to perform DMA test with maximum write burst size |
13617 | * to expose the 5700/5701 write DMA bug. | |
13618 | */ | |
13619 | saved_dma_rwctrl = tp->dma_rwctrl; | |
13620 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
13621 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
13622 | ||
1da177e4 LT |
13623 | while (1) { |
13624 | u32 *p = buf, i; | |
13625 | ||
13626 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
13627 | p[i] = i; | |
13628 | ||
13629 | /* Send the buffer to the chip. */ | |
13630 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
13631 | if (ret) { | |
13632 | printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret); | |
13633 | break; | |
13634 | } | |
13635 | ||
13636 | #if 0 | |
13637 | /* validate data reached card RAM correctly. */ | |
13638 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
13639 | u32 val; | |
13640 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
13641 | if (le32_to_cpu(val) != p[i]) { | |
13642 | printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i); | |
13643 | /* ret = -ENODEV here? */ | |
13644 | } | |
13645 | p[i] = 0; | |
13646 | } | |
13647 | #endif | |
13648 | /* Now read it back. */ | |
13649 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
13650 | if (ret) { | |
13651 | printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret); | |
13652 | ||
13653 | break; | |
13654 | } | |
13655 | ||
13656 | /* Verify it. */ | |
13657 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
13658 | if (p[i] == i) | |
13659 | continue; | |
13660 | ||
59e6b434 DM |
13661 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
13662 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
13663 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
13664 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
13665 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
13666 | break; | |
13667 | } else { | |
13668 | printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i); | |
13669 | ret = -ENODEV; | |
13670 | goto out; | |
13671 | } | |
13672 | } | |
13673 | ||
13674 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
13675 | /* Success. */ | |
13676 | ret = 0; | |
13677 | break; | |
13678 | } | |
13679 | } | |
59e6b434 DM |
13680 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
13681 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
6d1cfbab MC |
13682 | static struct pci_device_id dma_wait_state_chipsets[] = { |
13683 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, | |
13684 | PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, | |
13685 | { }, | |
13686 | }; | |
13687 | ||
59e6b434 | 13688 | /* DMA test passed without adjusting DMA boundary, |
6d1cfbab MC |
13689 | * now look for chipsets that are known to expose the |
13690 | * DMA bug without failing the test. | |
59e6b434 | 13691 | */ |
6d1cfbab MC |
13692 | if (pci_dev_present(dma_wait_state_chipsets)) { |
13693 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
13694 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
13695 | } | |
13696 | else | |
13697 | /* Safe to use the calculated DMA boundary. */ | |
13698 | tp->dma_rwctrl = saved_dma_rwctrl; | |
13699 | ||
59e6b434 DM |
13700 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
13701 | } | |
1da177e4 LT |
13702 | |
13703 | out: | |
13704 | pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma); | |
13705 | out_nofree: | |
13706 | return ret; | |
13707 | } | |
13708 | ||
13709 | static void __devinit tg3_init_link_config(struct tg3 *tp) | |
13710 | { | |
13711 | tp->link_config.advertising = | |
13712 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
13713 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
13714 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | | |
13715 | ADVERTISED_Autoneg | ADVERTISED_MII); | |
13716 | tp->link_config.speed = SPEED_INVALID; | |
13717 | tp->link_config.duplex = DUPLEX_INVALID; | |
13718 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
1da177e4 LT |
13719 | tp->link_config.active_speed = SPEED_INVALID; |
13720 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
13721 | tp->link_config.phy_is_low_power = 0; | |
13722 | tp->link_config.orig_speed = SPEED_INVALID; | |
13723 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
13724 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
13725 | } | |
13726 | ||
13727 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) | |
13728 | { | |
f6eb9b1f MC |
13729 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS && |
13730 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) { | |
fdfec172 MC |
13731 | tp->bufmgr_config.mbuf_read_dma_low_water = |
13732 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
13733 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
13734 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
13735 | tp->bufmgr_config.mbuf_high_water = | |
13736 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
13737 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
13738 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
13739 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
13740 | tp->bufmgr_config.mbuf_high_water = | |
13741 | DEFAULT_MB_HIGH_WATER_5906; | |
13742 | } | |
fdfec172 MC |
13743 | |
13744 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
13745 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
13746 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
13747 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
13748 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
13749 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
13750 | } else { | |
13751 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
13752 | DEFAULT_MB_RDMA_LOW_WATER; | |
13753 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
13754 | DEFAULT_MB_MACRX_LOW_WATER; | |
13755 | tp->bufmgr_config.mbuf_high_water = | |
13756 | DEFAULT_MB_HIGH_WATER; | |
13757 | ||
13758 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
13759 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
13760 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
13761 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
13762 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
13763 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
13764 | } | |
1da177e4 LT |
13765 | |
13766 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
13767 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
13768 | } | |
13769 | ||
13770 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
13771 | { | |
13772 | switch (tp->phy_id & PHY_ID_MASK) { | |
13773 | case PHY_ID_BCM5400: return "5400"; | |
13774 | case PHY_ID_BCM5401: return "5401"; | |
13775 | case PHY_ID_BCM5411: return "5411"; | |
13776 | case PHY_ID_BCM5701: return "5701"; | |
13777 | case PHY_ID_BCM5703: return "5703"; | |
13778 | case PHY_ID_BCM5704: return "5704"; | |
13779 | case PHY_ID_BCM5705: return "5705"; | |
13780 | case PHY_ID_BCM5750: return "5750"; | |
85e94ced | 13781 | case PHY_ID_BCM5752: return "5752"; |
a4e2b347 | 13782 | case PHY_ID_BCM5714: return "5714"; |
4cf78e4f | 13783 | case PHY_ID_BCM5780: return "5780"; |
af36e6b6 | 13784 | case PHY_ID_BCM5755: return "5755"; |
d9ab5ad1 | 13785 | case PHY_ID_BCM5787: return "5787"; |
d30cdd28 | 13786 | case PHY_ID_BCM5784: return "5784"; |
126a3368 | 13787 | case PHY_ID_BCM5756: return "5722/5756"; |
b5d3772c | 13788 | case PHY_ID_BCM5906: return "5906"; |
9936bcf6 | 13789 | case PHY_ID_BCM5761: return "5761"; |
c2060fe1 | 13790 | case PHY_ID_BCM5717: return "5717"; |
1da177e4 LT |
13791 | case PHY_ID_BCM8002: return "8002/serdes"; |
13792 | case 0: return "serdes"; | |
13793 | default: return "unknown"; | |
855e1111 | 13794 | } |
1da177e4 LT |
13795 | } |
13796 | ||
f9804ddb MC |
13797 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
13798 | { | |
13799 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
13800 | strcpy(str, "PCI Express"); | |
13801 | return str; | |
13802 | } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
13803 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
13804 | ||
13805 | strcpy(str, "PCIX:"); | |
13806 | ||
13807 | if ((clock_ctrl == 7) || | |
13808 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
13809 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
13810 | strcat(str, "133MHz"); | |
13811 | else if (clock_ctrl == 0) | |
13812 | strcat(str, "33MHz"); | |
13813 | else if (clock_ctrl == 2) | |
13814 | strcat(str, "50MHz"); | |
13815 | else if (clock_ctrl == 4) | |
13816 | strcat(str, "66MHz"); | |
13817 | else if (clock_ctrl == 6) | |
13818 | strcat(str, "100MHz"); | |
f9804ddb MC |
13819 | } else { |
13820 | strcpy(str, "PCI:"); | |
13821 | if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) | |
13822 | strcat(str, "66MHz"); | |
13823 | else | |
13824 | strcat(str, "33MHz"); | |
13825 | } | |
13826 | if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) | |
13827 | strcat(str, ":32-bit"); | |
13828 | else | |
13829 | strcat(str, ":64-bit"); | |
13830 | return str; | |
13831 | } | |
13832 | ||
8c2dc7e1 | 13833 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
13834 | { |
13835 | struct pci_dev *peer; | |
13836 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
13837 | ||
13838 | for (func = 0; func < 8; func++) { | |
13839 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
13840 | if (peer && peer != tp->pdev) | |
13841 | break; | |
13842 | pci_dev_put(peer); | |
13843 | } | |
16fe9d74 MC |
13844 | /* 5704 can be configured in single-port mode, set peer to |
13845 | * tp->pdev in that case. | |
13846 | */ | |
13847 | if (!peer) { | |
13848 | peer = tp->pdev; | |
13849 | return peer; | |
13850 | } | |
1da177e4 LT |
13851 | |
13852 | /* | |
13853 | * We don't need to keep the refcount elevated; there's no way | |
13854 | * to remove one half of this device without removing the other | |
13855 | */ | |
13856 | pci_dev_put(peer); | |
13857 | ||
13858 | return peer; | |
13859 | } | |
13860 | ||
15f9850d DM |
13861 | static void __devinit tg3_init_coal(struct tg3 *tp) |
13862 | { | |
13863 | struct ethtool_coalesce *ec = &tp->coal; | |
13864 | ||
13865 | memset(ec, 0, sizeof(*ec)); | |
13866 | ec->cmd = ETHTOOL_GCOALESCE; | |
13867 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
13868 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
13869 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
13870 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
13871 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
13872 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
13873 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
13874 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
13875 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
13876 | ||
13877 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
13878 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
13879 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
13880 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
13881 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
13882 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
13883 | } | |
d244c892 MC |
13884 | |
13885 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
13886 | ec->rx_coalesce_usecs_irq = 0; | |
13887 | ec->tx_coalesce_usecs_irq = 0; | |
13888 | ec->stats_block_coalesce_usecs = 0; | |
13889 | } | |
15f9850d DM |
13890 | } |
13891 | ||
7c7d64b8 SH |
13892 | static const struct net_device_ops tg3_netdev_ops = { |
13893 | .ndo_open = tg3_open, | |
13894 | .ndo_stop = tg3_close, | |
00829823 SH |
13895 | .ndo_start_xmit = tg3_start_xmit, |
13896 | .ndo_get_stats = tg3_get_stats, | |
13897 | .ndo_validate_addr = eth_validate_addr, | |
13898 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
13899 | .ndo_set_mac_address = tg3_set_mac_addr, | |
13900 | .ndo_do_ioctl = tg3_ioctl, | |
13901 | .ndo_tx_timeout = tg3_tx_timeout, | |
13902 | .ndo_change_mtu = tg3_change_mtu, | |
13903 | #if TG3_VLAN_TAG_USED | |
13904 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
13905 | #endif | |
13906 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
13907 | .ndo_poll_controller = tg3_poll_controller, | |
13908 | #endif | |
13909 | }; | |
13910 | ||
13911 | static const struct net_device_ops tg3_netdev_ops_dma_bug = { | |
13912 | .ndo_open = tg3_open, | |
13913 | .ndo_stop = tg3_close, | |
13914 | .ndo_start_xmit = tg3_start_xmit_dma_bug, | |
7c7d64b8 SH |
13915 | .ndo_get_stats = tg3_get_stats, |
13916 | .ndo_validate_addr = eth_validate_addr, | |
13917 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
13918 | .ndo_set_mac_address = tg3_set_mac_addr, | |
13919 | .ndo_do_ioctl = tg3_ioctl, | |
13920 | .ndo_tx_timeout = tg3_tx_timeout, | |
13921 | .ndo_change_mtu = tg3_change_mtu, | |
13922 | #if TG3_VLAN_TAG_USED | |
13923 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
13924 | #endif | |
13925 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
13926 | .ndo_poll_controller = tg3_poll_controller, | |
13927 | #endif | |
13928 | }; | |
13929 | ||
1da177e4 LT |
13930 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
13931 | const struct pci_device_id *ent) | |
13932 | { | |
13933 | static int tg3_version_printed = 0; | |
1da177e4 LT |
13934 | struct net_device *dev; |
13935 | struct tg3 *tp; | |
646c9edd MC |
13936 | int i, err, pm_cap; |
13937 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 13938 | char str[40]; |
72f2afb8 | 13939 | u64 dma_mask, persist_dma_mask; |
1da177e4 LT |
13940 | |
13941 | if (tg3_version_printed++ == 0) | |
13942 | printk(KERN_INFO "%s", version); | |
13943 | ||
13944 | err = pci_enable_device(pdev); | |
13945 | if (err) { | |
13946 | printk(KERN_ERR PFX "Cannot enable PCI device, " | |
13947 | "aborting.\n"); | |
13948 | return err; | |
13949 | } | |
13950 | ||
1da177e4 LT |
13951 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
13952 | if (err) { | |
13953 | printk(KERN_ERR PFX "Cannot obtain PCI resources, " | |
13954 | "aborting.\n"); | |
13955 | goto err_out_disable_pdev; | |
13956 | } | |
13957 | ||
13958 | pci_set_master(pdev); | |
13959 | ||
13960 | /* Find power-management capability. */ | |
13961 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
13962 | if (pm_cap == 0) { | |
13963 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
13964 | "aborting.\n"); | |
13965 | err = -EIO; | |
13966 | goto err_out_free_res; | |
13967 | } | |
13968 | ||
fe5f5787 | 13969 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 LT |
13970 | if (!dev) { |
13971 | printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n"); | |
13972 | err = -ENOMEM; | |
13973 | goto err_out_free_res; | |
13974 | } | |
13975 | ||
1da177e4 LT |
13976 | SET_NETDEV_DEV(dev, &pdev->dev); |
13977 | ||
1da177e4 LT |
13978 | #if TG3_VLAN_TAG_USED |
13979 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
1da177e4 LT |
13980 | #endif |
13981 | ||
13982 | tp = netdev_priv(dev); | |
13983 | tp->pdev = pdev; | |
13984 | tp->dev = dev; | |
13985 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
13986 | tp->rx_mode = TG3_DEF_RX_MODE; |
13987 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 13988 | |
1da177e4 LT |
13989 | if (tg3_debug > 0) |
13990 | tp->msg_enable = tg3_debug; | |
13991 | else | |
13992 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
13993 | ||
13994 | /* The word/byte swap controls here control register access byte | |
13995 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
13996 | * setting below. | |
13997 | */ | |
13998 | tp->misc_host_ctrl = | |
13999 | MISC_HOST_CTRL_MASK_PCI_INT | | |
14000 | MISC_HOST_CTRL_WORD_SWAP | | |
14001 | MISC_HOST_CTRL_INDIR_ACCESS | | |
14002 | MISC_HOST_CTRL_PCISTATE_RW; | |
14003 | ||
14004 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
14005 | * on descriptor entries, anything which isn't packet data. | |
14006 | * | |
14007 | * The StrongARM chips on the board (one for tx, one for rx) | |
14008 | * are running in big-endian mode. | |
14009 | */ | |
14010 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
14011 | GRC_MODE_WSWAP_NONFRM_DATA); | |
14012 | #ifdef __BIG_ENDIAN | |
14013 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
14014 | #endif | |
14015 | spin_lock_init(&tp->lock); | |
1da177e4 | 14016 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 14017 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 14018 | |
d5fe488a | 14019 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 14020 | if (!tp->regs) { |
1da177e4 LT |
14021 | printk(KERN_ERR PFX "Cannot map device registers, " |
14022 | "aborting.\n"); | |
14023 | err = -ENOMEM; | |
14024 | goto err_out_free_dev; | |
14025 | } | |
14026 | ||
14027 | tg3_init_link_config(tp); | |
14028 | ||
1da177e4 LT |
14029 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
14030 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 14031 | |
646c9edd MC |
14032 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
14033 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
14034 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
14035 | for (i = 0; i < TG3_IRQ_MAX_VECS; i++) { | |
14036 | struct tg3_napi *tnapi = &tp->napi[i]; | |
14037 | ||
14038 | tnapi->tp = tp; | |
14039 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
14040 | ||
14041 | tnapi->int_mbox = intmbx; | |
14042 | if (i < 4) | |
14043 | intmbx += 0x8; | |
14044 | else | |
14045 | intmbx += 0x4; | |
14046 | ||
14047 | tnapi->consmbox = rcvmbx; | |
14048 | tnapi->prodmbox = sndmbx; | |
14049 | ||
14050 | if (i) | |
14051 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); | |
14052 | else | |
14053 | tnapi->coal_now = HOSTCC_MODE_NOW; | |
14054 | ||
14055 | if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)) | |
14056 | break; | |
14057 | ||
14058 | /* | |
14059 | * If we support MSIX, we'll be using RSS. If we're using | |
14060 | * RSS, the first vector only handles link interrupts and the | |
14061 | * remaining vectors handle rx and tx interrupts. Reuse the | |
14062 | * mailbox values for the next iteration. The values we setup | |
14063 | * above are still useful for the single vectored mode. | |
14064 | */ | |
14065 | if (!i) | |
14066 | continue; | |
14067 | ||
14068 | rcvmbx += 0x8; | |
14069 | ||
14070 | if (sndmbx & 0x4) | |
14071 | sndmbx -= 0x4; | |
14072 | else | |
14073 | sndmbx += 0xc; | |
14074 | } | |
14075 | ||
8ef0442f | 14076 | netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64); |
1da177e4 | 14077 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 14078 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
1da177e4 | 14079 | dev->irq = pdev->irq; |
1da177e4 LT |
14080 | |
14081 | err = tg3_get_invariants(tp); | |
14082 | if (err) { | |
14083 | printk(KERN_ERR PFX "Problem fetching invariants of chip, " | |
14084 | "aborting.\n"); | |
14085 | goto err_out_iounmap; | |
14086 | } | |
14087 | ||
615774fe MC |
14088 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && |
14089 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) | |
00829823 SH |
14090 | dev->netdev_ops = &tg3_netdev_ops; |
14091 | else | |
14092 | dev->netdev_ops = &tg3_netdev_ops_dma_bug; | |
14093 | ||
14094 | ||
4a29cc2e MC |
14095 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
14096 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
14097 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
14098 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
14099 | * do DMA address check in tg3_start_xmit(). | |
14100 | */ | |
4a29cc2e | 14101 | if (tp->tg3_flags2 & TG3_FLG2_IS_5788) |
284901a9 | 14102 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
4a29cc2e | 14103 | else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { |
50cf156a | 14104 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 14105 | #ifdef CONFIG_HIGHMEM |
6a35528a | 14106 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 14107 | #endif |
4a29cc2e | 14108 | } else |
6a35528a | 14109 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
14110 | |
14111 | /* Configure DMA attributes. */ | |
284901a9 | 14112 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
14113 | err = pci_set_dma_mask(pdev, dma_mask); |
14114 | if (!err) { | |
14115 | dev->features |= NETIF_F_HIGHDMA; | |
14116 | err = pci_set_consistent_dma_mask(pdev, | |
14117 | persist_dma_mask); | |
14118 | if (err < 0) { | |
14119 | printk(KERN_ERR PFX "Unable to obtain 64 bit " | |
14120 | "DMA for consistent allocations\n"); | |
14121 | goto err_out_iounmap; | |
14122 | } | |
14123 | } | |
14124 | } | |
284901a9 YH |
14125 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
14126 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 MC |
14127 | if (err) { |
14128 | printk(KERN_ERR PFX "No usable DMA configuration, " | |
14129 | "aborting.\n"); | |
14130 | goto err_out_iounmap; | |
14131 | } | |
14132 | } | |
14133 | ||
fdfec172 | 14134 | tg3_init_bufmgr_config(tp); |
1da177e4 | 14135 | |
507399f1 MC |
14136 | /* Selectively allow TSO based on operating conditions */ |
14137 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || | |
14138 | (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) | |
1da177e4 | 14139 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
507399f1 MC |
14140 | else { |
14141 | tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG); | |
14142 | tp->fw_needed = NULL; | |
1da177e4 | 14143 | } |
507399f1 MC |
14144 | |
14145 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
14146 | tp->fw_needed = FIRMWARE_TG3; | |
1da177e4 | 14147 | |
4e3a7aaa MC |
14148 | /* TSO is on by default on chips that support hardware TSO. |
14149 | * Firmware TSO on older chips gives lower performance, so it | |
14150 | * is off by default, but can be enabled using ethtool. | |
14151 | */ | |
e849cdc3 MC |
14152 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) && |
14153 | (dev->features & NETIF_F_IP_CSUM)) | |
14154 | dev->features |= NETIF_F_TSO; | |
14155 | ||
14156 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || | |
14157 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) { | |
14158 | if (dev->features & NETIF_F_IPV6_CSUM) | |
b0026624 | 14159 | dev->features |= NETIF_F_TSO6; |
e849cdc3 MC |
14160 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
14161 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
14162 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14163 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 14164 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
e849cdc3 | 14165 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
9936bcf6 | 14166 | dev->features |= NETIF_F_TSO_ECN; |
b0026624 | 14167 | } |
1da177e4 | 14168 | |
1da177e4 LT |
14169 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
14170 | !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
14171 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
14172 | tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; | |
14173 | tp->rx_pending = 63; | |
14174 | } | |
14175 | ||
1da177e4 LT |
14176 | err = tg3_get_device_address(tp); |
14177 | if (err) { | |
14178 | printk(KERN_ERR PFX "Could not obtain valid ethernet address, " | |
14179 | "aborting.\n"); | |
077f849d | 14180 | goto err_out_fw; |
1da177e4 LT |
14181 | } |
14182 | ||
c88864df | 14183 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
63532394 | 14184 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); |
79ea13ce | 14185 | if (!tp->aperegs) { |
c88864df MC |
14186 | printk(KERN_ERR PFX "Cannot map APE registers, " |
14187 | "aborting.\n"); | |
14188 | err = -ENOMEM; | |
077f849d | 14189 | goto err_out_fw; |
c88864df MC |
14190 | } |
14191 | ||
14192 | tg3_ape_lock_init(tp); | |
7fd76445 MC |
14193 | |
14194 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
14195 | tg3_read_dash_ver(tp); | |
c88864df MC |
14196 | } |
14197 | ||
1da177e4 LT |
14198 | /* |
14199 | * Reset chip in case UNDI or EFI driver did not shutdown | |
14200 | * DMA self test will enable WDMAC and we'll see (spurious) | |
14201 | * pending DMA on the PCI bus at that point. | |
14202 | */ | |
14203 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
14204 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 14205 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 14206 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
14207 | } |
14208 | ||
14209 | err = tg3_test_dma(tp); | |
14210 | if (err) { | |
14211 | printk(KERN_ERR PFX "DMA engine test failed, aborting.\n"); | |
c88864df | 14212 | goto err_out_apeunmap; |
1da177e4 LT |
14213 | } |
14214 | ||
1da177e4 LT |
14215 | /* flow control autonegotiation is default behavior */ |
14216 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
e18ce346 | 14217 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
1da177e4 | 14218 | |
15f9850d DM |
14219 | tg3_init_coal(tp); |
14220 | ||
c49a1561 MC |
14221 | pci_set_drvdata(pdev, dev); |
14222 | ||
1da177e4 LT |
14223 | err = register_netdev(dev); |
14224 | if (err) { | |
14225 | printk(KERN_ERR PFX "Cannot register net device, " | |
14226 | "aborting.\n"); | |
0d3031d9 | 14227 | goto err_out_apeunmap; |
1da177e4 LT |
14228 | } |
14229 | ||
df59c940 | 14230 | printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
1da177e4 LT |
14231 | dev->name, |
14232 | tp->board_part_number, | |
14233 | tp->pci_chip_rev_id, | |
f9804ddb | 14234 | tg3_bus_string(tp, str), |
e174961c | 14235 | dev->dev_addr); |
1da177e4 | 14236 | |
3f0e3ad7 MC |
14237 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { |
14238 | struct phy_device *phydev; | |
14239 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
df59c940 MC |
14240 | printk(KERN_INFO |
14241 | "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
3f0e3ad7 MC |
14242 | tp->dev->name, phydev->drv->name, |
14243 | dev_name(&phydev->dev)); | |
14244 | } else | |
df59c940 MC |
14245 | printk(KERN_INFO |
14246 | "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n", | |
14247 | tp->dev->name, tg3_phy_string(tp), | |
14248 | ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" : | |
14249 | ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" : | |
14250 | "10/100/1000Base-T")), | |
14251 | (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0); | |
14252 | ||
14253 | printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
1da177e4 LT |
14254 | dev->name, |
14255 | (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0, | |
14256 | (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, | |
14257 | (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0, | |
14258 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, | |
1da177e4 | 14259 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); |
4a29cc2e MC |
14260 | printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
14261 | dev->name, tp->dma_rwctrl, | |
284901a9 | 14262 | (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 : |
50cf156a | 14263 | (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64)); |
1da177e4 LT |
14264 | |
14265 | return 0; | |
14266 | ||
0d3031d9 MC |
14267 | err_out_apeunmap: |
14268 | if (tp->aperegs) { | |
14269 | iounmap(tp->aperegs); | |
14270 | tp->aperegs = NULL; | |
14271 | } | |
14272 | ||
077f849d JSR |
14273 | err_out_fw: |
14274 | if (tp->fw) | |
14275 | release_firmware(tp->fw); | |
14276 | ||
1da177e4 | 14277 | err_out_iounmap: |
6892914f MC |
14278 | if (tp->regs) { |
14279 | iounmap(tp->regs); | |
22abe310 | 14280 | tp->regs = NULL; |
6892914f | 14281 | } |
1da177e4 LT |
14282 | |
14283 | err_out_free_dev: | |
14284 | free_netdev(dev); | |
14285 | ||
14286 | err_out_free_res: | |
14287 | pci_release_regions(pdev); | |
14288 | ||
14289 | err_out_disable_pdev: | |
14290 | pci_disable_device(pdev); | |
14291 | pci_set_drvdata(pdev, NULL); | |
14292 | return err; | |
14293 | } | |
14294 | ||
14295 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
14296 | { | |
14297 | struct net_device *dev = pci_get_drvdata(pdev); | |
14298 | ||
14299 | if (dev) { | |
14300 | struct tg3 *tp = netdev_priv(dev); | |
14301 | ||
077f849d JSR |
14302 | if (tp->fw) |
14303 | release_firmware(tp->fw); | |
14304 | ||
7faa006f | 14305 | flush_scheduled_work(); |
158d7abd | 14306 | |
b02fd9e3 MC |
14307 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
14308 | tg3_phy_fini(tp); | |
158d7abd | 14309 | tg3_mdio_fini(tp); |
b02fd9e3 | 14310 | } |
158d7abd | 14311 | |
1da177e4 | 14312 | unregister_netdev(dev); |
0d3031d9 MC |
14313 | if (tp->aperegs) { |
14314 | iounmap(tp->aperegs); | |
14315 | tp->aperegs = NULL; | |
14316 | } | |
6892914f MC |
14317 | if (tp->regs) { |
14318 | iounmap(tp->regs); | |
22abe310 | 14319 | tp->regs = NULL; |
6892914f | 14320 | } |
1da177e4 LT |
14321 | free_netdev(dev); |
14322 | pci_release_regions(pdev); | |
14323 | pci_disable_device(pdev); | |
14324 | pci_set_drvdata(pdev, NULL); | |
14325 | } | |
14326 | } | |
14327 | ||
14328 | static int tg3_suspend(struct pci_dev *pdev, pm_message_t state) | |
14329 | { | |
14330 | struct net_device *dev = pci_get_drvdata(pdev); | |
14331 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 14332 | pci_power_t target_state; |
1da177e4 LT |
14333 | int err; |
14334 | ||
3e0c95fd MC |
14335 | /* PCI register 4 needs to be saved whether netif_running() or not. |
14336 | * MSI address and data need to be saved if using MSI and | |
14337 | * netif_running(). | |
14338 | */ | |
14339 | pci_save_state(pdev); | |
14340 | ||
1da177e4 LT |
14341 | if (!netif_running(dev)) |
14342 | return 0; | |
14343 | ||
7faa006f | 14344 | flush_scheduled_work(); |
b02fd9e3 | 14345 | tg3_phy_stop(tp); |
1da177e4 LT |
14346 | tg3_netif_stop(tp); |
14347 | ||
14348 | del_timer_sync(&tp->timer); | |
14349 | ||
f47c11ee | 14350 | tg3_full_lock(tp, 1); |
1da177e4 | 14351 | tg3_disable_ints(tp); |
f47c11ee | 14352 | tg3_full_unlock(tp); |
1da177e4 LT |
14353 | |
14354 | netif_device_detach(dev); | |
14355 | ||
f47c11ee | 14356 | tg3_full_lock(tp, 0); |
944d980e | 14357 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
6a9eba15 | 14358 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
f47c11ee | 14359 | tg3_full_unlock(tp); |
1da177e4 | 14360 | |
12dac075 RW |
14361 | target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot; |
14362 | ||
14363 | err = tg3_set_power_state(tp, target_state); | |
1da177e4 | 14364 | if (err) { |
b02fd9e3 MC |
14365 | int err2; |
14366 | ||
f47c11ee | 14367 | tg3_full_lock(tp, 0); |
1da177e4 | 14368 | |
6a9eba15 | 14369 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b02fd9e3 MC |
14370 | err2 = tg3_restart_hw(tp, 1); |
14371 | if (err2) | |
b9ec6c1b | 14372 | goto out; |
1da177e4 LT |
14373 | |
14374 | tp->timer.expires = jiffies + tp->timer_offset; | |
14375 | add_timer(&tp->timer); | |
14376 | ||
14377 | netif_device_attach(dev); | |
14378 | tg3_netif_start(tp); | |
14379 | ||
b9ec6c1b | 14380 | out: |
f47c11ee | 14381 | tg3_full_unlock(tp); |
b02fd9e3 MC |
14382 | |
14383 | if (!err2) | |
14384 | tg3_phy_start(tp); | |
1da177e4 LT |
14385 | } |
14386 | ||
14387 | return err; | |
14388 | } | |
14389 | ||
14390 | static int tg3_resume(struct pci_dev *pdev) | |
14391 | { | |
14392 | struct net_device *dev = pci_get_drvdata(pdev); | |
14393 | struct tg3 *tp = netdev_priv(dev); | |
14394 | int err; | |
14395 | ||
3e0c95fd MC |
14396 | pci_restore_state(tp->pdev); |
14397 | ||
1da177e4 LT |
14398 | if (!netif_running(dev)) |
14399 | return 0; | |
14400 | ||
bc1c7567 | 14401 | err = tg3_set_power_state(tp, PCI_D0); |
1da177e4 LT |
14402 | if (err) |
14403 | return err; | |
14404 | ||
14405 | netif_device_attach(dev); | |
14406 | ||
f47c11ee | 14407 | tg3_full_lock(tp, 0); |
1da177e4 | 14408 | |
6a9eba15 | 14409 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b9ec6c1b MC |
14410 | err = tg3_restart_hw(tp, 1); |
14411 | if (err) | |
14412 | goto out; | |
1da177e4 LT |
14413 | |
14414 | tp->timer.expires = jiffies + tp->timer_offset; | |
14415 | add_timer(&tp->timer); | |
14416 | ||
1da177e4 LT |
14417 | tg3_netif_start(tp); |
14418 | ||
b9ec6c1b | 14419 | out: |
f47c11ee | 14420 | tg3_full_unlock(tp); |
1da177e4 | 14421 | |
b02fd9e3 MC |
14422 | if (!err) |
14423 | tg3_phy_start(tp); | |
14424 | ||
b9ec6c1b | 14425 | return err; |
1da177e4 LT |
14426 | } |
14427 | ||
14428 | static struct pci_driver tg3_driver = { | |
14429 | .name = DRV_MODULE_NAME, | |
14430 | .id_table = tg3_pci_tbl, | |
14431 | .probe = tg3_init_one, | |
14432 | .remove = __devexit_p(tg3_remove_one), | |
14433 | .suspend = tg3_suspend, | |
14434 | .resume = tg3_resume | |
14435 | }; | |
14436 | ||
14437 | static int __init tg3_init(void) | |
14438 | { | |
29917620 | 14439 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
14440 | } |
14441 | ||
14442 | static void __exit tg3_cleanup(void) | |
14443 | { | |
14444 | pci_unregister_driver(&tg3_driver); | |
14445 | } | |
14446 | ||
14447 | module_init(tg3_init); | |
14448 | module_exit(tg3_cleanup); |