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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
b86fb2cf | 7 | * Copyright (C) 2005-2011 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
6867c843 | 21 | #include <linux/stringify.h> |
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/compiler.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
14c85021 | 27 | #include <linux/in.h> |
1da177e4 LT |
28 | #include <linux/init.h> |
29 | #include <linux/ioport.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/ethtool.h> | |
3110f5f5 | 35 | #include <linux/mdio.h> |
1da177e4 | 36 | #include <linux/mii.h> |
158d7abd | 37 | #include <linux/phy.h> |
a9daf367 | 38 | #include <linux/brcmphy.h> |
1da177e4 LT |
39 | #include <linux/if_vlan.h> |
40 | #include <linux/ip.h> | |
41 | #include <linux/tcp.h> | |
42 | #include <linux/workqueue.h> | |
61487480 | 43 | #include <linux/prefetch.h> |
f9a5f7d3 | 44 | #include <linux/dma-mapping.h> |
077f849d | 45 | #include <linux/firmware.h> |
1da177e4 LT |
46 | |
47 | #include <net/checksum.h> | |
c9bdd4b5 | 48 | #include <net/ip.h> |
1da177e4 LT |
49 | |
50 | #include <asm/system.h> | |
27fd9de8 | 51 | #include <linux/io.h> |
1da177e4 | 52 | #include <asm/byteorder.h> |
27fd9de8 | 53 | #include <linux/uaccess.h> |
1da177e4 | 54 | |
49b6e95f | 55 | #ifdef CONFIG_SPARC |
1da177e4 | 56 | #include <asm/idprom.h> |
49b6e95f | 57 | #include <asm/prom.h> |
1da177e4 LT |
58 | #endif |
59 | ||
63532394 MC |
60 | #define BAR_0 0 |
61 | #define BAR_2 2 | |
62 | ||
1da177e4 LT |
63 | #include "tg3.h" |
64 | ||
65 | #define DRV_MODULE_NAME "tg3" | |
6867c843 | 66 | #define TG3_MAJ_NUM 3 |
b86fb2cf | 67 | #define TG3_MIN_NUM 117 |
6867c843 MC |
68 | #define DRV_MODULE_VERSION \ |
69 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | |
b86fb2cf | 70 | #define DRV_MODULE_RELDATE "January 25, 2011" |
1da177e4 LT |
71 | |
72 | #define TG3_DEF_MAC_MODE 0 | |
73 | #define TG3_DEF_RX_MODE 0 | |
74 | #define TG3_DEF_TX_MODE 0 | |
75 | #define TG3_DEF_MSG_ENABLE \ | |
76 | (NETIF_MSG_DRV | \ | |
77 | NETIF_MSG_PROBE | \ | |
78 | NETIF_MSG_LINK | \ | |
79 | NETIF_MSG_TIMER | \ | |
80 | NETIF_MSG_IFDOWN | \ | |
81 | NETIF_MSG_IFUP | \ | |
82 | NETIF_MSG_RX_ERR | \ | |
83 | NETIF_MSG_TX_ERR) | |
84 | ||
85 | /* length of time before we decide the hardware is borked, | |
86 | * and dev->tx_timeout() should be called to fix the problem | |
87 | */ | |
88 | #define TG3_TX_TIMEOUT (5 * HZ) | |
89 | ||
90 | /* hardware minimum and maximum for a single frame's data payload */ | |
91 | #define TG3_MIN_MTU 60 | |
92 | #define TG3_MAX_MTU(tp) \ | |
8f666b07 | 93 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
94 | |
95 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
96 | * You can't change the ring sizes, but you can change where you place | |
97 | * them in the NIC onboard memory. | |
98 | */ | |
7cb32cf2 | 99 | #define TG3_RX_STD_RING_SIZE(tp) \ |
de9f5230 MC |
100 | ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ |
101 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) | |
1da177e4 | 102 | #define TG3_DEF_RX_RING_PENDING 200 |
7cb32cf2 | 103 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
de9f5230 MC |
104 | ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ |
105 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) | |
1da177e4 | 106 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
c6cdf436 | 107 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
108 | |
109 | /* Do not place this n-ring entries value into the tp struct itself, | |
110 | * we really want to expose these constants to GCC so that modulo et | |
111 | * al. operations are done with shifts and masks instead of with | |
112 | * hw multiply/modulo instructions. Another solution would be to | |
113 | * replace things like '% foo' with '& (foo - 1)'. | |
114 | */ | |
1da177e4 LT |
115 | |
116 | #define TG3_TX_RING_SIZE 512 | |
117 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
118 | ||
2c49a44d MC |
119 | #define TG3_RX_STD_RING_BYTES(tp) \ |
120 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) | |
121 | #define TG3_RX_JMB_RING_BYTES(tp) \ | |
122 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) | |
123 | #define TG3_RX_RCB_RING_BYTES(tp) \ | |
7cb32cf2 | 124 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
1da177e4 LT |
125 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
126 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
127 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
128 | ||
287be12e MC |
129 | #define TG3_DMA_BYTE_ENAB 64 |
130 | ||
131 | #define TG3_RX_STD_DMA_SZ 1536 | |
132 | #define TG3_RX_JMB_DMA_SZ 9046 | |
133 | ||
134 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
135 | ||
136 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
137 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 138 | |
2c49a44d MC |
139 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
140 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) | |
2b2cdb65 | 141 | |
2c49a44d MC |
142 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
143 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) | |
2b2cdb65 | 144 | |
d2757fc4 MC |
145 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
146 | * that are at least dword aligned when used in PCIX mode. The driver | |
147 | * works around this bug by double copying the packet. This workaround | |
148 | * is built into the normal double copy length check for efficiency. | |
149 | * | |
150 | * However, the double copy is only necessary on those architectures | |
151 | * where unaligned memory accesses are inefficient. For those architectures | |
152 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
153 | * the 5701 in the normal rx path. Doing so saves a device structure | |
154 | * dereference by hardcoding the double copy threshold in place. | |
155 | */ | |
156 | #define TG3_RX_COPY_THRESHOLD 256 | |
157 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
158 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
159 | #else | |
160 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
161 | #endif | |
162 | ||
1da177e4 | 163 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 164 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
1da177e4 | 165 | |
ad829268 MC |
166 | #define TG3_RAW_IP_ALIGN 2 |
167 | ||
1da177e4 LT |
168 | /* number of ETHTOOL_GSTATS u64's */ |
169 | #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64)) | |
170 | ||
4cafd3f5 MC |
171 | #define TG3_NUM_TEST 6 |
172 | ||
c6cdf436 MC |
173 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
174 | ||
077f849d JSR |
175 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
176 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
177 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
178 | ||
1da177e4 | 179 | static char version[] __devinitdata = |
05dbe005 | 180 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
181 | |
182 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
183 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
184 | MODULE_LICENSE("GPL"); | |
185 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
186 | MODULE_FIRMWARE(FIRMWARE_TG3); |
187 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
188 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
189 | ||
1da177e4 LT |
190 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
191 | module_param(tg3_debug, int, 0); | |
192 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
193 | ||
a3aa1884 | 194 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
195 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
196 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
197 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
198 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
199 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
200 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
201 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
202 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
203 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
204 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
205 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
206 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
207 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
208 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
209 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
210 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
211 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
212 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
213 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
214 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
215 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
13185217 | 217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
126a3368 | 218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 | 219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
13185217 HK |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
b0f75221 MC |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
302b500b | 266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
13185217 HK |
267 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
268 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
269 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
270 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
271 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
272 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
273 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
274 | {} | |
1da177e4 LT |
275 | }; |
276 | ||
277 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
278 | ||
50da859d | 279 | static const struct { |
1da177e4 LT |
280 | const char string[ETH_GSTRING_LEN]; |
281 | } ethtool_stats_keys[TG3_NUM_STATS] = { | |
282 | { "rx_octets" }, | |
283 | { "rx_fragments" }, | |
284 | { "rx_ucast_packets" }, | |
285 | { "rx_mcast_packets" }, | |
286 | { "rx_bcast_packets" }, | |
287 | { "rx_fcs_errors" }, | |
288 | { "rx_align_errors" }, | |
289 | { "rx_xon_pause_rcvd" }, | |
290 | { "rx_xoff_pause_rcvd" }, | |
291 | { "rx_mac_ctrl_rcvd" }, | |
292 | { "rx_xoff_entered" }, | |
293 | { "rx_frame_too_long_errors" }, | |
294 | { "rx_jabbers" }, | |
295 | { "rx_undersize_packets" }, | |
296 | { "rx_in_length_errors" }, | |
297 | { "rx_out_length_errors" }, | |
298 | { "rx_64_or_less_octet_packets" }, | |
299 | { "rx_65_to_127_octet_packets" }, | |
300 | { "rx_128_to_255_octet_packets" }, | |
301 | { "rx_256_to_511_octet_packets" }, | |
302 | { "rx_512_to_1023_octet_packets" }, | |
303 | { "rx_1024_to_1522_octet_packets" }, | |
304 | { "rx_1523_to_2047_octet_packets" }, | |
305 | { "rx_2048_to_4095_octet_packets" }, | |
306 | { "rx_4096_to_8191_octet_packets" }, | |
307 | { "rx_8192_to_9022_octet_packets" }, | |
308 | ||
309 | { "tx_octets" }, | |
310 | { "tx_collisions" }, | |
311 | ||
312 | { "tx_xon_sent" }, | |
313 | { "tx_xoff_sent" }, | |
314 | { "tx_flow_control" }, | |
315 | { "tx_mac_errors" }, | |
316 | { "tx_single_collisions" }, | |
317 | { "tx_mult_collisions" }, | |
318 | { "tx_deferred" }, | |
319 | { "tx_excessive_collisions" }, | |
320 | { "tx_late_collisions" }, | |
321 | { "tx_collide_2times" }, | |
322 | { "tx_collide_3times" }, | |
323 | { "tx_collide_4times" }, | |
324 | { "tx_collide_5times" }, | |
325 | { "tx_collide_6times" }, | |
326 | { "tx_collide_7times" }, | |
327 | { "tx_collide_8times" }, | |
328 | { "tx_collide_9times" }, | |
329 | { "tx_collide_10times" }, | |
330 | { "tx_collide_11times" }, | |
331 | { "tx_collide_12times" }, | |
332 | { "tx_collide_13times" }, | |
333 | { "tx_collide_14times" }, | |
334 | { "tx_collide_15times" }, | |
335 | { "tx_ucast_packets" }, | |
336 | { "tx_mcast_packets" }, | |
337 | { "tx_bcast_packets" }, | |
338 | { "tx_carrier_sense_errors" }, | |
339 | { "tx_discards" }, | |
340 | { "tx_errors" }, | |
341 | ||
342 | { "dma_writeq_full" }, | |
343 | { "dma_write_prioq_full" }, | |
344 | { "rxbds_empty" }, | |
345 | { "rx_discards" }, | |
346 | { "rx_errors" }, | |
347 | { "rx_threshold_hit" }, | |
348 | ||
349 | { "dma_readq_full" }, | |
350 | { "dma_read_prioq_full" }, | |
351 | { "tx_comp_queue_full" }, | |
352 | ||
353 | { "ring_set_send_prod_index" }, | |
354 | { "ring_status_update" }, | |
355 | { "nic_irqs" }, | |
356 | { "nic_avoided_irqs" }, | |
357 | { "nic_tx_threshold_hit" } | |
358 | }; | |
359 | ||
50da859d | 360 | static const struct { |
4cafd3f5 MC |
361 | const char string[ETH_GSTRING_LEN]; |
362 | } ethtool_test_keys[TG3_NUM_TEST] = { | |
363 | { "nvram test (online) " }, | |
364 | { "link test (online) " }, | |
365 | { "register test (offline)" }, | |
366 | { "memory test (offline)" }, | |
367 | { "loopback test (offline)" }, | |
368 | { "interrupt test (offline)" }, | |
369 | }; | |
370 | ||
b401e9e2 MC |
371 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
372 | { | |
373 | writel(val, tp->regs + off); | |
374 | } | |
375 | ||
376 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
377 | { | |
de6f31eb | 378 | return readl(tp->regs + off); |
b401e9e2 MC |
379 | } |
380 | ||
0d3031d9 MC |
381 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
382 | { | |
383 | writel(val, tp->aperegs + off); | |
384 | } | |
385 | ||
386 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
387 | { | |
de6f31eb | 388 | return readl(tp->aperegs + off); |
0d3031d9 MC |
389 | } |
390 | ||
1da177e4 LT |
391 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
392 | { | |
6892914f MC |
393 | unsigned long flags; |
394 | ||
395 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
396 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
397 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 398 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
399 | } |
400 | ||
401 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
402 | { | |
403 | writel(val, tp->regs + off); | |
404 | readl(tp->regs + off); | |
1da177e4 LT |
405 | } |
406 | ||
6892914f | 407 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 408 | { |
6892914f MC |
409 | unsigned long flags; |
410 | u32 val; | |
411 | ||
412 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
413 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
414 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
415 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
416 | return val; | |
417 | } | |
418 | ||
419 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
420 | { | |
421 | unsigned long flags; | |
422 | ||
423 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
424 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
425 | TG3_64BIT_REG_LOW, val); | |
426 | return; | |
427 | } | |
66711e66 | 428 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
429 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
430 | TG3_64BIT_REG_LOW, val); | |
431 | return; | |
1da177e4 | 432 | } |
6892914f MC |
433 | |
434 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
435 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
436 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
437 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
438 | ||
439 | /* In indirect mode when disabling interrupts, we also need | |
440 | * to clear the interrupt bit in the GRC local ctrl register. | |
441 | */ | |
442 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
443 | (val == 0x1)) { | |
444 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
445 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
446 | } | |
447 | } | |
448 | ||
449 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
450 | { | |
451 | unsigned long flags; | |
452 | u32 val; | |
453 | ||
454 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
455 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
456 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
457 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
458 | return val; | |
459 | } | |
460 | ||
b401e9e2 MC |
461 | /* usec_wait specifies the wait time in usec when writing to certain registers |
462 | * where it is unsafe to read back the register without some delay. | |
463 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
464 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
465 | */ | |
466 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 467 | { |
b401e9e2 MC |
468 | if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || |
469 | (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
470 | /* Non-posted methods */ | |
471 | tp->write32(tp, off, val); | |
472 | else { | |
473 | /* Posted method */ | |
474 | tg3_write32(tp, off, val); | |
475 | if (usec_wait) | |
476 | udelay(usec_wait); | |
477 | tp->read32(tp, off); | |
478 | } | |
479 | /* Wait again after the read for the posted method to guarantee that | |
480 | * the wait time is met. | |
481 | */ | |
482 | if (usec_wait) | |
483 | udelay(usec_wait); | |
1da177e4 LT |
484 | } |
485 | ||
09ee929c MC |
486 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
487 | { | |
488 | tp->write32_mbox(tp, off, val); | |
6892914f MC |
489 | if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && |
490 | !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
491 | tp->read32_mbox(tp, off); | |
09ee929c MC |
492 | } |
493 | ||
20094930 | 494 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
495 | { |
496 | void __iomem *mbox = tp->regs + off; | |
497 | writel(val, mbox); | |
498 | if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) | |
499 | writel(val, mbox); | |
500 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
501 | readl(mbox); | |
502 | } | |
503 | ||
b5d3772c MC |
504 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
505 | { | |
de6f31eb | 506 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
507 | } |
508 | ||
509 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
510 | { | |
511 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
512 | } | |
513 | ||
c6cdf436 | 514 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 515 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
516 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
517 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
518 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 519 | |
c6cdf436 MC |
520 | #define tw32(reg, val) tp->write32(tp, reg, val) |
521 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
522 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
523 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
524 | |
525 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
526 | { | |
6892914f MC |
527 | unsigned long flags; |
528 | ||
b5d3772c MC |
529 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
530 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
531 | return; | |
532 | ||
6892914f | 533 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
534 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
535 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
536 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 537 | |
bbadf503 MC |
538 | /* Always leave this as zero. */ |
539 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
540 | } else { | |
541 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
542 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 543 | |
bbadf503 MC |
544 | /* Always leave this as zero. */ |
545 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
546 | } | |
547 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
548 | } |
549 | ||
1da177e4 LT |
550 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
551 | { | |
6892914f MC |
552 | unsigned long flags; |
553 | ||
b5d3772c MC |
554 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
555 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
556 | *val = 0; | |
557 | return; | |
558 | } | |
559 | ||
6892914f | 560 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
561 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
562 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
563 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 564 | |
bbadf503 MC |
565 | /* Always leave this as zero. */ |
566 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
567 | } else { | |
568 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
569 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
570 | ||
571 | /* Always leave this as zero. */ | |
572 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
573 | } | |
6892914f | 574 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
575 | } |
576 | ||
0d3031d9 MC |
577 | static void tg3_ape_lock_init(struct tg3 *tp) |
578 | { | |
579 | int i; | |
f92d9dc1 MC |
580 | u32 regbase; |
581 | ||
582 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
583 | regbase = TG3_APE_LOCK_GRANT; | |
584 | else | |
585 | regbase = TG3_APE_PER_LOCK_GRANT; | |
0d3031d9 MC |
586 | |
587 | /* Make sure the driver hasn't any stale locks. */ | |
588 | for (i = 0; i < 8; i++) | |
f92d9dc1 | 589 | tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER); |
0d3031d9 MC |
590 | } |
591 | ||
592 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
593 | { | |
594 | int i, off; | |
595 | int ret = 0; | |
f92d9dc1 | 596 | u32 status, req, gnt; |
0d3031d9 MC |
597 | |
598 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
599 | return 0; | |
600 | ||
601 | switch (locknum) { | |
33f401ae MC |
602 | case TG3_APE_LOCK_GRC: |
603 | case TG3_APE_LOCK_MEM: | |
604 | break; | |
605 | default: | |
606 | return -EINVAL; | |
0d3031d9 MC |
607 | } |
608 | ||
f92d9dc1 MC |
609 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
610 | req = TG3_APE_LOCK_REQ; | |
611 | gnt = TG3_APE_LOCK_GRANT; | |
612 | } else { | |
613 | req = TG3_APE_PER_LOCK_REQ; | |
614 | gnt = TG3_APE_PER_LOCK_GRANT; | |
615 | } | |
616 | ||
0d3031d9 MC |
617 | off = 4 * locknum; |
618 | ||
f92d9dc1 | 619 | tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER); |
0d3031d9 MC |
620 | |
621 | /* Wait for up to 1 millisecond to acquire lock. */ | |
622 | for (i = 0; i < 100; i++) { | |
f92d9dc1 | 623 | status = tg3_ape_read32(tp, gnt + off); |
0d3031d9 MC |
624 | if (status == APE_LOCK_GRANT_DRIVER) |
625 | break; | |
626 | udelay(10); | |
627 | } | |
628 | ||
629 | if (status != APE_LOCK_GRANT_DRIVER) { | |
630 | /* Revoke the lock request. */ | |
f92d9dc1 | 631 | tg3_ape_write32(tp, gnt + off, |
0d3031d9 MC |
632 | APE_LOCK_GRANT_DRIVER); |
633 | ||
634 | ret = -EBUSY; | |
635 | } | |
636 | ||
637 | return ret; | |
638 | } | |
639 | ||
640 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
641 | { | |
f92d9dc1 | 642 | u32 gnt; |
0d3031d9 MC |
643 | |
644 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
645 | return; | |
646 | ||
647 | switch (locknum) { | |
33f401ae MC |
648 | case TG3_APE_LOCK_GRC: |
649 | case TG3_APE_LOCK_MEM: | |
650 | break; | |
651 | default: | |
652 | return; | |
0d3031d9 MC |
653 | } |
654 | ||
f92d9dc1 MC |
655 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
656 | gnt = TG3_APE_LOCK_GRANT; | |
657 | else | |
658 | gnt = TG3_APE_PER_LOCK_GRANT; | |
659 | ||
660 | tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER); | |
0d3031d9 MC |
661 | } |
662 | ||
1da177e4 LT |
663 | static void tg3_disable_ints(struct tg3 *tp) |
664 | { | |
89aeb3bc MC |
665 | int i; |
666 | ||
1da177e4 LT |
667 | tw32(TG3PCI_MISC_HOST_CTRL, |
668 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
669 | for (i = 0; i < tp->irq_max; i++) |
670 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
671 | } |
672 | ||
1da177e4 LT |
673 | static void tg3_enable_ints(struct tg3 *tp) |
674 | { | |
89aeb3bc | 675 | int i; |
89aeb3bc | 676 | |
bbe832c0 MC |
677 | tp->irq_sync = 0; |
678 | wmb(); | |
679 | ||
1da177e4 LT |
680 | tw32(TG3PCI_MISC_HOST_CTRL, |
681 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 682 | |
f89f38b8 | 683 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
684 | for (i = 0; i < tp->irq_cnt; i++) { |
685 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 686 | |
898a56f8 | 687 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
89aeb3bc MC |
688 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) |
689 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
f19af9c2 | 690 | |
f89f38b8 | 691 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 692 | } |
f19af9c2 MC |
693 | |
694 | /* Force an initial interrupt */ | |
695 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
696 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) | |
697 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
698 | else | |
f89f38b8 MC |
699 | tw32(HOSTCC_MODE, tp->coal_now); |
700 | ||
701 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
702 | } |
703 | ||
17375d25 | 704 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 705 | { |
17375d25 | 706 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 707 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
708 | unsigned int work_exists = 0; |
709 | ||
710 | /* check for phy events */ | |
711 | if (!(tp->tg3_flags & | |
712 | (TG3_FLAG_USE_LINKCHG_REG | | |
713 | TG3_FLAG_POLL_SERDES))) { | |
714 | if (sblk->status & SD_STATUS_LINK_CHG) | |
715 | work_exists = 1; | |
716 | } | |
717 | /* check for RX/TX work to do */ | |
f3f3f27e | 718 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 719 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
720 | work_exists = 1; |
721 | ||
722 | return work_exists; | |
723 | } | |
724 | ||
17375d25 | 725 | /* tg3_int_reenable |
04237ddd MC |
726 | * similar to tg3_enable_ints, but it accurately determines whether there |
727 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 728 | * which reenables interrupts |
1da177e4 | 729 | */ |
17375d25 | 730 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 731 | { |
17375d25 MC |
732 | struct tg3 *tp = tnapi->tp; |
733 | ||
898a56f8 | 734 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
735 | mmiowb(); |
736 | ||
fac9b83e DM |
737 | /* When doing tagged status, this work check is unnecessary. |
738 | * The last_tag we write above tells the chip which piece of | |
739 | * work we've completed. | |
740 | */ | |
741 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
17375d25 | 742 | tg3_has_work(tnapi)) |
04237ddd | 743 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 744 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
745 | } |
746 | ||
1da177e4 LT |
747 | static void tg3_switch_clocks(struct tg3 *tp) |
748 | { | |
f6eb9b1f | 749 | u32 clock_ctrl; |
1da177e4 LT |
750 | u32 orig_clock_ctrl; |
751 | ||
795d01c5 MC |
752 | if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
753 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
4cf78e4f MC |
754 | return; |
755 | ||
f6eb9b1f MC |
756 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
757 | ||
1da177e4 LT |
758 | orig_clock_ctrl = clock_ctrl; |
759 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
760 | CLOCK_CTRL_CLKRUN_OENABLE | | |
761 | 0x1f); | |
762 | tp->pci_clock_ctrl = clock_ctrl; | |
763 | ||
764 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
765 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
b401e9e2 MC |
766 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
767 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
768 | } |
769 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
770 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
771 | clock_ctrl | | |
772 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
773 | 40); | |
774 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
775 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
776 | 40); | |
1da177e4 | 777 | } |
b401e9e2 | 778 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
779 | } |
780 | ||
781 | #define PHY_BUSY_LOOPS 5000 | |
782 | ||
783 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
784 | { | |
785 | u32 frame_val; | |
786 | unsigned int loops; | |
787 | int ret; | |
788 | ||
789 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
790 | tw32_f(MAC_MI_MODE, | |
791 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
792 | udelay(80); | |
793 | } | |
794 | ||
795 | *val = 0x0; | |
796 | ||
882e9793 | 797 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
798 | MI_COM_PHY_ADDR_MASK); |
799 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
800 | MI_COM_REG_ADDR_MASK); | |
801 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 802 | |
1da177e4 LT |
803 | tw32_f(MAC_MI_COM, frame_val); |
804 | ||
805 | loops = PHY_BUSY_LOOPS; | |
806 | while (loops != 0) { | |
807 | udelay(10); | |
808 | frame_val = tr32(MAC_MI_COM); | |
809 | ||
810 | if ((frame_val & MI_COM_BUSY) == 0) { | |
811 | udelay(5); | |
812 | frame_val = tr32(MAC_MI_COM); | |
813 | break; | |
814 | } | |
815 | loops -= 1; | |
816 | } | |
817 | ||
818 | ret = -EBUSY; | |
819 | if (loops != 0) { | |
820 | *val = frame_val & MI_COM_DATA_MASK; | |
821 | ret = 0; | |
822 | } | |
823 | ||
824 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
825 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
826 | udelay(80); | |
827 | } | |
828 | ||
829 | return ret; | |
830 | } | |
831 | ||
832 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
833 | { | |
834 | u32 frame_val; | |
835 | unsigned int loops; | |
836 | int ret; | |
837 | ||
f07e9af3 | 838 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
b5d3772c MC |
839 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) |
840 | return 0; | |
841 | ||
1da177e4 LT |
842 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
843 | tw32_f(MAC_MI_MODE, | |
844 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
845 | udelay(80); | |
846 | } | |
847 | ||
882e9793 | 848 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
849 | MI_COM_PHY_ADDR_MASK); |
850 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
851 | MI_COM_REG_ADDR_MASK); | |
852 | frame_val |= (val & MI_COM_DATA_MASK); | |
853 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 854 | |
1da177e4 LT |
855 | tw32_f(MAC_MI_COM, frame_val); |
856 | ||
857 | loops = PHY_BUSY_LOOPS; | |
858 | while (loops != 0) { | |
859 | udelay(10); | |
860 | frame_val = tr32(MAC_MI_COM); | |
861 | if ((frame_val & MI_COM_BUSY) == 0) { | |
862 | udelay(5); | |
863 | frame_val = tr32(MAC_MI_COM); | |
864 | break; | |
865 | } | |
866 | loops -= 1; | |
867 | } | |
868 | ||
869 | ret = -EBUSY; | |
870 | if (loops != 0) | |
871 | ret = 0; | |
872 | ||
873 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
874 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
875 | udelay(80); | |
876 | } | |
877 | ||
878 | return ret; | |
879 | } | |
880 | ||
95e2869a MC |
881 | static int tg3_bmcr_reset(struct tg3 *tp) |
882 | { | |
883 | u32 phy_control; | |
884 | int limit, err; | |
885 | ||
886 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
887 | * clears or we time out. | |
888 | */ | |
889 | phy_control = BMCR_RESET; | |
890 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
891 | if (err != 0) | |
892 | return -EBUSY; | |
893 | ||
894 | limit = 5000; | |
895 | while (limit--) { | |
896 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
897 | if (err != 0) | |
898 | return -EBUSY; | |
899 | ||
900 | if ((phy_control & BMCR_RESET) == 0) { | |
901 | udelay(40); | |
902 | break; | |
903 | } | |
904 | udelay(10); | |
905 | } | |
d4675b52 | 906 | if (limit < 0) |
95e2869a MC |
907 | return -EBUSY; |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
158d7abd MC |
912 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
913 | { | |
3d16543d | 914 | struct tg3 *tp = bp->priv; |
158d7abd MC |
915 | u32 val; |
916 | ||
24bb4fb6 | 917 | spin_lock_bh(&tp->lock); |
158d7abd MC |
918 | |
919 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
920 | val = -EIO; |
921 | ||
922 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
923 | |
924 | return val; | |
925 | } | |
926 | ||
927 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
928 | { | |
3d16543d | 929 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 930 | u32 ret = 0; |
158d7abd | 931 | |
24bb4fb6 | 932 | spin_lock_bh(&tp->lock); |
158d7abd MC |
933 | |
934 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 935 | ret = -EIO; |
158d7abd | 936 | |
24bb4fb6 MC |
937 | spin_unlock_bh(&tp->lock); |
938 | ||
939 | return ret; | |
158d7abd MC |
940 | } |
941 | ||
942 | static int tg3_mdio_reset(struct mii_bus *bp) | |
943 | { | |
944 | return 0; | |
945 | } | |
946 | ||
9c61d6bc | 947 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
948 | { |
949 | u32 val; | |
fcb389df | 950 | struct phy_device *phydev; |
a9daf367 | 951 | |
3f0e3ad7 | 952 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 953 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
954 | case PHY_ID_BCM50610: |
955 | case PHY_ID_BCM50610M: | |
fcb389df MC |
956 | val = MAC_PHYCFG2_50610_LED_MODES; |
957 | break; | |
6a443a0f | 958 | case PHY_ID_BCMAC131: |
fcb389df MC |
959 | val = MAC_PHYCFG2_AC131_LED_MODES; |
960 | break; | |
6a443a0f | 961 | case PHY_ID_RTL8211C: |
fcb389df MC |
962 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
963 | break; | |
6a443a0f | 964 | case PHY_ID_RTL8201E: |
fcb389df MC |
965 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
966 | break; | |
967 | default: | |
a9daf367 | 968 | return; |
fcb389df MC |
969 | } |
970 | ||
971 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
972 | tw32(MAC_PHYCFG2, val); | |
973 | ||
974 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
975 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
976 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
977 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
978 | tw32(MAC_PHYCFG1, val); |
979 | ||
980 | return; | |
981 | } | |
982 | ||
14417063 | 983 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) |
fcb389df MC |
984 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
985 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
986 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
987 | MAC_PHYCFG2_ACT_MASK_MASK | | |
988 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
989 | MAC_PHYCFG2_INBAND_ENABLE; | |
990 | ||
991 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 992 | |
bb85fbb6 MC |
993 | val = tr32(MAC_PHYCFG1); |
994 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
995 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
14417063 | 996 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
997 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
998 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
999 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1000 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
1001 | } | |
bb85fbb6 MC |
1002 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1003 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1004 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1005 | |
a9daf367 MC |
1006 | val = tr32(MAC_EXT_RGMII_MODE); |
1007 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1008 | MAC_RGMII_MODE_RX_QUALITY | | |
1009 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1010 | MAC_RGMII_MODE_RX_ENG_DET | | |
1011 | MAC_RGMII_MODE_TX_ENABLE | | |
1012 | MAC_RGMII_MODE_TX_LOWPWR | | |
1013 | MAC_RGMII_MODE_TX_RESET); | |
14417063 | 1014 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
1015 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1016 | val |= MAC_RGMII_MODE_RX_INT_B | | |
1017 | MAC_RGMII_MODE_RX_QUALITY | | |
1018 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1019 | MAC_RGMII_MODE_RX_ENG_DET; | |
1020 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1021 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
1022 | MAC_RGMII_MODE_TX_LOWPWR | | |
1023 | MAC_RGMII_MODE_TX_RESET; | |
1024 | } | |
1025 | tw32(MAC_EXT_RGMII_MODE, val); | |
1026 | } | |
1027 | ||
158d7abd MC |
1028 | static void tg3_mdio_start(struct tg3 *tp) |
1029 | { | |
158d7abd MC |
1030 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1031 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1032 | udelay(80); | |
a9daf367 | 1033 | |
9ea4818d MC |
1034 | if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && |
1035 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1036 | tg3_mdio_config_5785(tp); | |
1037 | } | |
1038 | ||
1039 | static int tg3_mdio_init(struct tg3 *tp) | |
1040 | { | |
1041 | int i; | |
1042 | u32 reg; | |
1043 | struct phy_device *phydev; | |
1044 | ||
0a58d668 | 1045 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
9c7df915 | 1046 | u32 is_serdes; |
882e9793 | 1047 | |
9c7df915 | 1048 | tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1; |
882e9793 | 1049 | |
d1ec96af MC |
1050 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1051 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1052 | else | |
1053 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1054 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1055 | if (is_serdes) |
1056 | tp->phy_addr += 7; | |
1057 | } else | |
3f0e3ad7 | 1058 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1059 | |
158d7abd MC |
1060 | tg3_mdio_start(tp); |
1061 | ||
1062 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || | |
1063 | (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)) | |
1064 | return 0; | |
1065 | ||
298cf9be LB |
1066 | tp->mdio_bus = mdiobus_alloc(); |
1067 | if (tp->mdio_bus == NULL) | |
1068 | return -ENOMEM; | |
158d7abd | 1069 | |
298cf9be LB |
1070 | tp->mdio_bus->name = "tg3 mdio bus"; |
1071 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1072 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1073 | tp->mdio_bus->priv = tp; |
1074 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1075 | tp->mdio_bus->read = &tg3_mdio_read; | |
1076 | tp->mdio_bus->write = &tg3_mdio_write; | |
1077 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1078 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1079 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1080 | |
1081 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1082 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1083 | |
1084 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1085 | * Unfortunately, it does not ensure the PHY is powered up before | |
1086 | * accessing the PHY ID registers. A chip reset is the | |
1087 | * quickest way to bring the device back to an operational state.. | |
1088 | */ | |
1089 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1090 | tg3_bmcr_reset(tp); | |
1091 | ||
298cf9be | 1092 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1093 | if (i) { |
ab96b241 | 1094 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1095 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1096 | return i; |
1097 | } | |
158d7abd | 1098 | |
3f0e3ad7 | 1099 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1100 | |
9c61d6bc | 1101 | if (!phydev || !phydev->drv) { |
ab96b241 | 1102 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1103 | mdiobus_unregister(tp->mdio_bus); |
1104 | mdiobus_free(tp->mdio_bus); | |
1105 | return -ENODEV; | |
1106 | } | |
1107 | ||
1108 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1109 | case PHY_ID_BCM57780: |
321d32a0 | 1110 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1111 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1112 | break; |
6a443a0f MC |
1113 | case PHY_ID_BCM50610: |
1114 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1115 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1116 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1117 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1118 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
14417063 | 1119 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE) |
a9daf367 MC |
1120 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
1121 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1122 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1123 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1124 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
fcb389df | 1125 | /* fallthru */ |
6a443a0f | 1126 | case PHY_ID_RTL8211C: |
fcb389df | 1127 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1128 | break; |
6a443a0f MC |
1129 | case PHY_ID_RTL8201E: |
1130 | case PHY_ID_BCMAC131: | |
a9daf367 | 1131 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1132 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
f07e9af3 | 1133 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
a9daf367 MC |
1134 | break; |
1135 | } | |
1136 | ||
9c61d6bc MC |
1137 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; |
1138 | ||
1139 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1140 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1141 | |
1142 | return 0; | |
158d7abd MC |
1143 | } |
1144 | ||
1145 | static void tg3_mdio_fini(struct tg3 *tp) | |
1146 | { | |
1147 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
1148 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; | |
298cf9be LB |
1149 | mdiobus_unregister(tp->mdio_bus); |
1150 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1151 | } |
1152 | } | |
1153 | ||
ddfc87bf MC |
1154 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
1155 | { | |
1156 | int err; | |
1157 | ||
1158 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1159 | if (err) | |
1160 | goto done; | |
1161 | ||
1162 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1163 | if (err) | |
1164 | goto done; | |
1165 | ||
1166 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1167 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1168 | if (err) | |
1169 | goto done; | |
1170 | ||
1171 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); | |
1172 | ||
1173 | done: | |
1174 | return err; | |
1175 | } | |
1176 | ||
1177 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) | |
1178 | { | |
1179 | int err; | |
1180 | ||
1181 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); | |
1182 | if (err) | |
1183 | goto done; | |
1184 | ||
1185 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); | |
1186 | if (err) | |
1187 | goto done; | |
1188 | ||
1189 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, | |
1190 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); | |
1191 | if (err) | |
1192 | goto done; | |
1193 | ||
1194 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); | |
1195 | ||
1196 | done: | |
1197 | return err; | |
1198 | } | |
1199 | ||
4ba526ce MC |
1200 | /* tp->lock is held. */ |
1201 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1202 | { | |
1203 | u32 val; | |
1204 | ||
1205 | val = tr32(GRC_RX_CPU_EVENT); | |
1206 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1207 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1208 | ||
1209 | tp->last_event_jiffies = jiffies; | |
1210 | } | |
1211 | ||
1212 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1213 | ||
95e2869a MC |
1214 | /* tp->lock is held. */ |
1215 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1216 | { | |
1217 | int i; | |
4ba526ce MC |
1218 | unsigned int delay_cnt; |
1219 | long time_remain; | |
1220 | ||
1221 | /* If enough time has passed, no wait is necessary. */ | |
1222 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1223 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1224 | (long)jiffies; | |
1225 | if (time_remain < 0) | |
1226 | return; | |
1227 | ||
1228 | /* Check if we can shorten the wait time. */ | |
1229 | delay_cnt = jiffies_to_usecs(time_remain); | |
1230 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1231 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1232 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1233 | |
4ba526ce | 1234 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1235 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1236 | break; | |
4ba526ce | 1237 | udelay(8); |
95e2869a MC |
1238 | } |
1239 | } | |
1240 | ||
1241 | /* tp->lock is held. */ | |
1242 | static void tg3_ump_link_report(struct tg3 *tp) | |
1243 | { | |
1244 | u32 reg; | |
1245 | u32 val; | |
1246 | ||
1247 | if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
1248 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
1249 | return; | |
1250 | ||
1251 | tg3_wait_for_event_ack(tp); | |
1252 | ||
1253 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1254 | ||
1255 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1256 | ||
1257 | val = 0; | |
1258 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1259 | val = reg << 16; | |
1260 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1261 | val |= (reg & 0xffff); | |
1262 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1263 | ||
1264 | val = 0; | |
1265 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1266 | val = reg << 16; | |
1267 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1268 | val |= (reg & 0xffff); | |
1269 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1270 | ||
1271 | val = 0; | |
f07e9af3 | 1272 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
95e2869a MC |
1273 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
1274 | val = reg << 16; | |
1275 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1276 | val |= (reg & 0xffff); | |
1277 | } | |
1278 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1279 | ||
1280 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1281 | val = reg << 16; | |
1282 | else | |
1283 | val = 0; | |
1284 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1285 | ||
4ba526ce | 1286 | tg3_generate_fw_event(tp); |
95e2869a MC |
1287 | } |
1288 | ||
1289 | static void tg3_link_report(struct tg3 *tp) | |
1290 | { | |
1291 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1292 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1293 | tg3_ump_link_report(tp); |
1294 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1295 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1296 | (tp->link_config.active_speed == SPEED_1000 ? | |
1297 | 1000 : | |
1298 | (tp->link_config.active_speed == SPEED_100 ? | |
1299 | 100 : 10)), | |
1300 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1301 | "full" : "half")); | |
1302 | ||
1303 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1304 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1305 | "on" : "off", | |
1306 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1307 | "on" : "off"); | |
95e2869a MC |
1308 | tg3_ump_link_report(tp); |
1309 | } | |
1310 | } | |
1311 | ||
1312 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1313 | { | |
1314 | u16 miireg; | |
1315 | ||
e18ce346 | 1316 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1317 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1318 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1319 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1320 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1321 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1322 | else | |
1323 | miireg = 0; | |
1324 | ||
1325 | return miireg; | |
1326 | } | |
1327 | ||
1328 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1329 | { | |
1330 | u16 miireg; | |
1331 | ||
e18ce346 | 1332 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1333 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1334 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1335 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1336 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1337 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1338 | else | |
1339 | miireg = 0; | |
1340 | ||
1341 | return miireg; | |
1342 | } | |
1343 | ||
95e2869a MC |
1344 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1345 | { | |
1346 | u8 cap = 0; | |
1347 | ||
1348 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1349 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1350 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1351 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1352 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1353 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1354 | } else { |
1355 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1356 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1357 | } |
1358 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1359 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1360 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1361 | } |
1362 | ||
1363 | return cap; | |
1364 | } | |
1365 | ||
f51f3562 | 1366 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1367 | { |
b02fd9e3 | 1368 | u8 autoneg; |
f51f3562 | 1369 | u8 flowctrl = 0; |
95e2869a MC |
1370 | u32 old_rx_mode = tp->rx_mode; |
1371 | u32 old_tx_mode = tp->tx_mode; | |
1372 | ||
b02fd9e3 | 1373 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
3f0e3ad7 | 1374 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1375 | else |
1376 | autoneg = tp->link_config.autoneg; | |
1377 | ||
1378 | if (autoneg == AUTONEG_ENABLE && | |
95e2869a | 1379 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { |
f07e9af3 | 1380 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
f51f3562 | 1381 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1382 | else |
bc02ff95 | 1383 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1384 | } else |
1385 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1386 | |
f51f3562 | 1387 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1388 | |
e18ce346 | 1389 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1390 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1391 | else | |
1392 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1393 | ||
f51f3562 | 1394 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1395 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1396 | |
e18ce346 | 1397 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1398 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1399 | else | |
1400 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1401 | ||
f51f3562 | 1402 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1403 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1404 | } |
1405 | ||
b02fd9e3 MC |
1406 | static void tg3_adjust_link(struct net_device *dev) |
1407 | { | |
1408 | u8 oldflowctrl, linkmesg = 0; | |
1409 | u32 mac_mode, lcl_adv, rmt_adv; | |
1410 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1411 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1412 | |
24bb4fb6 | 1413 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1414 | |
1415 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1416 | MAC_MODE_HALF_DUPLEX); | |
1417 | ||
1418 | oldflowctrl = tp->link_config.active_flowctrl; | |
1419 | ||
1420 | if (phydev->link) { | |
1421 | lcl_adv = 0; | |
1422 | rmt_adv = 0; | |
1423 | ||
1424 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1425 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1426 | else if (phydev->speed == SPEED_1000 || |
1427 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1428 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1429 | else |
1430 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1431 | |
1432 | if (phydev->duplex == DUPLEX_HALF) | |
1433 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1434 | else { | |
1435 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1436 | tp->link_config.flowctrl); | |
1437 | ||
1438 | if (phydev->pause) | |
1439 | rmt_adv = LPA_PAUSE_CAP; | |
1440 | if (phydev->asym_pause) | |
1441 | rmt_adv |= LPA_PAUSE_ASYM; | |
1442 | } | |
1443 | ||
1444 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1445 | } else | |
1446 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1447 | ||
1448 | if (mac_mode != tp->mac_mode) { | |
1449 | tp->mac_mode = mac_mode; | |
1450 | tw32_f(MAC_MODE, tp->mac_mode); | |
1451 | udelay(40); | |
1452 | } | |
1453 | ||
fcb389df MC |
1454 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1455 | if (phydev->speed == SPEED_10) | |
1456 | tw32(MAC_MI_STAT, | |
1457 | MAC_MI_STAT_10MBPS_MODE | | |
1458 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1459 | else | |
1460 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1461 | } | |
1462 | ||
b02fd9e3 MC |
1463 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1464 | tw32(MAC_TX_LENGTHS, | |
1465 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1466 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1467 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1468 | else | |
1469 | tw32(MAC_TX_LENGTHS, | |
1470 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1471 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1472 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1473 | ||
1474 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1475 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1476 | phydev->speed != tp->link_config.active_speed || | |
1477 | phydev->duplex != tp->link_config.active_duplex || | |
1478 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1479 | linkmesg = 1; |
b02fd9e3 MC |
1480 | |
1481 | tp->link_config.active_speed = phydev->speed; | |
1482 | tp->link_config.active_duplex = phydev->duplex; | |
1483 | ||
24bb4fb6 | 1484 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1485 | |
1486 | if (linkmesg) | |
1487 | tg3_link_report(tp); | |
1488 | } | |
1489 | ||
1490 | static int tg3_phy_init(struct tg3 *tp) | |
1491 | { | |
1492 | struct phy_device *phydev; | |
1493 | ||
f07e9af3 | 1494 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
b02fd9e3 MC |
1495 | return 0; |
1496 | ||
1497 | /* Bring the PHY back to a known state. */ | |
1498 | tg3_bmcr_reset(tp); | |
1499 | ||
3f0e3ad7 | 1500 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1501 | |
1502 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1503 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1504 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1505 | if (IS_ERR(phydev)) { |
ab96b241 | 1506 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1507 | return PTR_ERR(phydev); |
1508 | } | |
1509 | ||
b02fd9e3 | 1510 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1511 | switch (phydev->interface) { |
1512 | case PHY_INTERFACE_MODE_GMII: | |
1513 | case PHY_INTERFACE_MODE_RGMII: | |
f07e9af3 | 1514 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
321d32a0 MC |
1515 | phydev->supported &= (PHY_GBIT_FEATURES | |
1516 | SUPPORTED_Pause | | |
1517 | SUPPORTED_Asym_Pause); | |
1518 | break; | |
1519 | } | |
1520 | /* fallthru */ | |
9c61d6bc MC |
1521 | case PHY_INTERFACE_MODE_MII: |
1522 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1523 | SUPPORTED_Pause | | |
1524 | SUPPORTED_Asym_Pause); | |
1525 | break; | |
1526 | default: | |
3f0e3ad7 | 1527 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1528 | return -EINVAL; |
1529 | } | |
1530 | ||
f07e9af3 | 1531 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1532 | |
1533 | phydev->advertising = phydev->supported; | |
1534 | ||
b02fd9e3 MC |
1535 | return 0; |
1536 | } | |
1537 | ||
1538 | static void tg3_phy_start(struct tg3 *tp) | |
1539 | { | |
1540 | struct phy_device *phydev; | |
1541 | ||
f07e9af3 | 1542 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1543 | return; |
1544 | ||
3f0e3ad7 | 1545 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1546 | |
80096068 MC |
1547 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1548 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
b02fd9e3 MC |
1549 | phydev->speed = tp->link_config.orig_speed; |
1550 | phydev->duplex = tp->link_config.orig_duplex; | |
1551 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1552 | phydev->advertising = tp->link_config.orig_advertising; | |
1553 | } | |
1554 | ||
1555 | phy_start(phydev); | |
1556 | ||
1557 | phy_start_aneg(phydev); | |
1558 | } | |
1559 | ||
1560 | static void tg3_phy_stop(struct tg3 *tp) | |
1561 | { | |
f07e9af3 | 1562 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 MC |
1563 | return; |
1564 | ||
3f0e3ad7 | 1565 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1566 | } |
1567 | ||
1568 | static void tg3_phy_fini(struct tg3 *tp) | |
1569 | { | |
f07e9af3 | 1570 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 | 1571 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
f07e9af3 | 1572 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
b02fd9e3 MC |
1573 | } |
1574 | } | |
1575 | ||
52b02d04 MC |
1576 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) |
1577 | { | |
1578 | int err; | |
1579 | ||
1580 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1581 | if (!err) | |
1582 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); | |
1583 | ||
1584 | return err; | |
1585 | } | |
1586 | ||
6ee7c0a0 | 1587 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) |
b2a5c19c | 1588 | { |
6ee7c0a0 MC |
1589 | int err; |
1590 | ||
1591 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1592 | if (!err) | |
1593 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1594 | ||
1595 | return err; | |
b2a5c19c MC |
1596 | } |
1597 | ||
7f97a4bd MC |
1598 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1599 | { | |
1600 | u32 phytest; | |
1601 | ||
1602 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1603 | u32 phy; | |
1604 | ||
1605 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1606 | phytest | MII_TG3_FET_SHADOW_EN); | |
1607 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1608 | if (enable) | |
1609 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1610 | else | |
1611 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1612 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1613 | } | |
1614 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1615 | } | |
1616 | } | |
1617 | ||
6833c043 MC |
1618 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1619 | { | |
1620 | u32 reg; | |
1621 | ||
ecf1410b | 1622 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
0a58d668 | 1623 | ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
f07e9af3 | 1624 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
6833c043 MC |
1625 | return; |
1626 | ||
f07e9af3 | 1627 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd MC |
1628 | tg3_phy_fet_toggle_apd(tp, enable); |
1629 | return; | |
1630 | } | |
1631 | ||
6833c043 MC |
1632 | reg = MII_TG3_MISC_SHDW_WREN | |
1633 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1634 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1635 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1636 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1637 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1638 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1639 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1640 | ||
1641 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1642 | ||
1643 | ||
1644 | reg = MII_TG3_MISC_SHDW_WREN | | |
1645 | MII_TG3_MISC_SHDW_APD_SEL | | |
1646 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1647 | if (enable) | |
1648 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1649 | ||
1650 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1651 | } | |
1652 | ||
9ef8ca99 MC |
1653 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1654 | { | |
1655 | u32 phy; | |
1656 | ||
1657 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
f07e9af3 | 1658 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
9ef8ca99 MC |
1659 | return; |
1660 | ||
f07e9af3 | 1661 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
9ef8ca99 MC |
1662 | u32 ephy; |
1663 | ||
535ef6e1 MC |
1664 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1665 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1666 | ||
1667 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1668 | ephy | MII_TG3_FET_SHADOW_EN); | |
1669 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1670 | if (enable) |
535ef6e1 | 1671 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1672 | else |
535ef6e1 MC |
1673 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1674 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1675 | } |
535ef6e1 | 1676 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1677 | } |
1678 | } else { | |
1679 | phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | | |
1680 | MII_TG3_AUXCTL_SHDWSEL_MISC; | |
1681 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) && | |
1682 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) { | |
1683 | if (enable) | |
1684 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1685 | else | |
1686 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1687 | phy |= MII_TG3_AUXCTL_MISC_WREN; | |
1688 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1689 | } | |
1690 | } | |
1691 | } | |
1692 | ||
1da177e4 LT |
1693 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1694 | { | |
1695 | u32 val; | |
1696 | ||
f07e9af3 | 1697 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
1da177e4 LT |
1698 | return; |
1699 | ||
1700 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) && | |
1701 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) | |
1702 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1703 | (val | (1 << 15) | (1 << 4))); | |
1704 | } | |
1705 | ||
b2a5c19c MC |
1706 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1707 | { | |
1708 | u32 otp, phy; | |
1709 | ||
1710 | if (!tp->phy_otp) | |
1711 | return; | |
1712 | ||
1713 | otp = tp->phy_otp; | |
1714 | ||
1715 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1716 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1717 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1718 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1719 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1720 | ||
1721 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1722 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1723 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1724 | ||
1725 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1726 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1727 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1728 | ||
1729 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1730 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1731 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1732 | ||
1733 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1734 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1735 | ||
1736 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1737 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1738 | ||
1739 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1740 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1741 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1742 | ||
1743 | /* Turn off SM_DSP clock. */ | |
1744 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1745 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1746 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1747 | } | |
1748 | ||
52b02d04 MC |
1749 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
1750 | { | |
1751 | u32 val; | |
1752 | ||
1753 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | |
1754 | return; | |
1755 | ||
1756 | tp->setlpicnt = 0; | |
1757 | ||
1758 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | |
1759 | current_link_up == 1 && | |
a6b68dab MC |
1760 | tp->link_config.active_duplex == DUPLEX_FULL && |
1761 | (tp->link_config.active_speed == SPEED_100 || | |
1762 | tp->link_config.active_speed == SPEED_1000)) { | |
52b02d04 MC |
1763 | u32 eeectl; |
1764 | ||
1765 | if (tp->link_config.active_speed == SPEED_1000) | |
1766 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; | |
1767 | else | |
1768 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; | |
1769 | ||
1770 | tw32(TG3_CPMU_EEE_CTRL, eeectl); | |
1771 | ||
3110f5f5 MC |
1772 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
1773 | TG3_CL45_D7_EEERES_STAT, &val); | |
52b02d04 | 1774 | |
21a00ab2 MC |
1775 | switch (val) { |
1776 | case TG3_CL45_D7_EEERES_STAT_LP_1000T: | |
1777 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { | |
1778 | case ASIC_REV_5717: | |
1779 | case ASIC_REV_5719: | |
1780 | case ASIC_REV_57765: | |
1781 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1782 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1783 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1784 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1785 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
1786 | ||
1787 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | |
1788 | ||
1789 | /* Turn off SM_DSP clock. */ | |
1790 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1791 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1792 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
1793 | } | |
1794 | /* Fallthrough */ | |
1795 | case TG3_CL45_D7_EEERES_STAT_LP_100TX: | |
52b02d04 | 1796 | tp->setlpicnt = 2; |
21a00ab2 | 1797 | } |
52b02d04 MC |
1798 | } |
1799 | ||
1800 | if (!tp->setlpicnt) { | |
1801 | val = tr32(TG3_CPMU_EEE_MODE); | |
1802 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
1803 | } | |
1804 | } | |
1805 | ||
1da177e4 LT |
1806 | static int tg3_wait_macro_done(struct tg3 *tp) |
1807 | { | |
1808 | int limit = 100; | |
1809 | ||
1810 | while (limit--) { | |
1811 | u32 tmp32; | |
1812 | ||
f08aa1a8 | 1813 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
1da177e4 LT |
1814 | if ((tmp32 & 0x1000) == 0) |
1815 | break; | |
1816 | } | |
1817 | } | |
d4675b52 | 1818 | if (limit < 0) |
1da177e4 LT |
1819 | return -EBUSY; |
1820 | ||
1821 | return 0; | |
1822 | } | |
1823 | ||
1824 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1825 | { | |
1826 | static const u32 test_pat[4][6] = { | |
1827 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1828 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1829 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1830 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1831 | }; | |
1832 | int chan; | |
1833 | ||
1834 | for (chan = 0; chan < 4; chan++) { | |
1835 | int i; | |
1836 | ||
1837 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1838 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1839 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1840 | |
1841 | for (i = 0; i < 6; i++) | |
1842 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1843 | test_pat[chan][i]); | |
1844 | ||
f08aa1a8 | 1845 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1846 | if (tg3_wait_macro_done(tp)) { |
1847 | *resetp = 1; | |
1848 | return -EBUSY; | |
1849 | } | |
1850 | ||
1851 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1852 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1853 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
1da177e4 LT |
1854 | if (tg3_wait_macro_done(tp)) { |
1855 | *resetp = 1; | |
1856 | return -EBUSY; | |
1857 | } | |
1858 | ||
f08aa1a8 | 1859 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
1da177e4 LT |
1860 | if (tg3_wait_macro_done(tp)) { |
1861 | *resetp = 1; | |
1862 | return -EBUSY; | |
1863 | } | |
1864 | ||
1865 | for (i = 0; i < 6; i += 2) { | |
1866 | u32 low, high; | |
1867 | ||
1868 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1869 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1870 | tg3_wait_macro_done(tp)) { | |
1871 | *resetp = 1; | |
1872 | return -EBUSY; | |
1873 | } | |
1874 | low &= 0x7fff; | |
1875 | high &= 0x000f; | |
1876 | if (low != test_pat[chan][i] || | |
1877 | high != test_pat[chan][i+1]) { | |
1878 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1879 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1880 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1881 | ||
1882 | return -EBUSY; | |
1883 | } | |
1884 | } | |
1885 | } | |
1886 | ||
1887 | return 0; | |
1888 | } | |
1889 | ||
1890 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1891 | { | |
1892 | int chan; | |
1893 | ||
1894 | for (chan = 0; chan < 4; chan++) { | |
1895 | int i; | |
1896 | ||
1897 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1898 | (chan * 0x2000) | 0x0200); | |
f08aa1a8 | 1899 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
1da177e4 LT |
1900 | for (i = 0; i < 6; i++) |
1901 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
f08aa1a8 | 1902 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
1da177e4 LT |
1903 | if (tg3_wait_macro_done(tp)) |
1904 | return -EBUSY; | |
1905 | } | |
1906 | ||
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1911 | { | |
1912 | u32 reg32, phy9_orig; | |
1913 | int retries, do_phy_reset, err; | |
1914 | ||
1915 | retries = 10; | |
1916 | do_phy_reset = 1; | |
1917 | do { | |
1918 | if (do_phy_reset) { | |
1919 | err = tg3_bmcr_reset(tp); | |
1920 | if (err) | |
1921 | return err; | |
1922 | do_phy_reset = 0; | |
1923 | } | |
1924 | ||
1925 | /* Disable transmitter and interrupt. */ | |
1926 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1927 | continue; | |
1928 | ||
1929 | reg32 |= 0x3000; | |
1930 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1931 | ||
1932 | /* Set full-duplex, 1000 mbps. */ | |
1933 | tg3_writephy(tp, MII_BMCR, | |
1934 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1935 | ||
1936 | /* Set to master mode. */ | |
1937 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1938 | continue; | |
1939 | ||
1940 | tg3_writephy(tp, MII_TG3_CTRL, | |
1941 | (MII_TG3_CTRL_AS_MASTER | | |
1942 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1943 | ||
1944 | /* Enable SM_DSP_CLOCK and 6dB. */ | |
1945 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1946 | ||
1947 | /* Block the PHY control access. */ | |
6ee7c0a0 | 1948 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
1da177e4 LT |
1949 | |
1950 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
1951 | if (!err) | |
1952 | break; | |
1953 | } while (--retries); | |
1954 | ||
1955 | err = tg3_phy_reset_chanpat(tp); | |
1956 | if (err) | |
1957 | return err; | |
1958 | ||
6ee7c0a0 | 1959 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
1da177e4 LT |
1960 | |
1961 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
f08aa1a8 | 1962 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
1da177e4 LT |
1963 | |
1964 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1965 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
1966 | /* Set Extended packet length bit for jumbo frames */ | |
1967 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); | |
859a5887 | 1968 | } else { |
1da177e4 LT |
1969 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
1970 | } | |
1971 | ||
1972 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
1973 | ||
1974 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
1975 | reg32 &= ~0x3000; | |
1976 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1977 | } else if (!err) | |
1978 | err = -EBUSY; | |
1979 | ||
1980 | return err; | |
1981 | } | |
1982 | ||
1983 | /* This will reset the tigon3 PHY if there is no valid | |
1984 | * link unless the FORCE argument is non-zero. | |
1985 | */ | |
1986 | static int tg3_phy_reset(struct tg3 *tp) | |
1987 | { | |
f833c4c1 | 1988 | u32 val, cpmuctrl; |
1da177e4 LT |
1989 | int err; |
1990 | ||
60189ddf | 1991 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
1992 | val = tr32(GRC_MISC_CFG); |
1993 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
1994 | udelay(40); | |
1995 | } | |
f833c4c1 MC |
1996 | err = tg3_readphy(tp, MII_BMSR, &val); |
1997 | err |= tg3_readphy(tp, MII_BMSR, &val); | |
1da177e4 LT |
1998 | if (err != 0) |
1999 | return -EBUSY; | |
2000 | ||
c8e1e82b MC |
2001 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
2002 | netif_carrier_off(tp->dev); | |
2003 | tg3_link_report(tp); | |
2004 | } | |
2005 | ||
1da177e4 LT |
2006 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
2007 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2008 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
2009 | err = tg3_phy_reset_5703_4_5(tp); | |
2010 | if (err) | |
2011 | return err; | |
2012 | goto out; | |
2013 | } | |
2014 | ||
b2a5c19c MC |
2015 | cpmuctrl = 0; |
2016 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
2017 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
2018 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
2019 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
2020 | tw32(TG3_CPMU_CTRL, | |
2021 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
2022 | } | |
2023 | ||
1da177e4 LT |
2024 | err = tg3_bmcr_reset(tp); |
2025 | if (err) | |
2026 | return err; | |
2027 | ||
b2a5c19c | 2028 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
f833c4c1 MC |
2029 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
2030 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); | |
b2a5c19c MC |
2031 | |
2032 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
2033 | } | |
2034 | ||
bcb37f6c MC |
2035 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2036 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2037 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2038 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
2039 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
2040 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2041 | udelay(40); | |
2042 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2043 | } | |
2044 | } | |
2045 | ||
0a58d668 | 2046 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
f07e9af3 | 2047 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
ecf1410b MC |
2048 | return 0; |
2049 | ||
b2a5c19c MC |
2050 | tg3_phy_apply_otp(tp); |
2051 | ||
f07e9af3 | 2052 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
2053 | tg3_phy_toggle_apd(tp, true); |
2054 | else | |
2055 | tg3_phy_toggle_apd(tp, false); | |
2056 | ||
1da177e4 | 2057 | out: |
f07e9af3 | 2058 | if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) { |
1da177e4 | 2059 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
6ee7c0a0 MC |
2060 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
2061 | tg3_phydsp_write(tp, 0x000a, 0x0323); | |
1da177e4 LT |
2062 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
2063 | } | |
f07e9af3 | 2064 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
f08aa1a8 MC |
2065 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
2066 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
1da177e4 | 2067 | } |
f07e9af3 | 2068 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
1da177e4 | 2069 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
6ee7c0a0 MC |
2070 | tg3_phydsp_write(tp, 0x000a, 0x310b); |
2071 | tg3_phydsp_write(tp, 0x201f, 0x9506); | |
2072 | tg3_phydsp_write(tp, 0x401f, 0x14e2); | |
1da177e4 | 2073 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
f07e9af3 | 2074 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
c424cb24 MC |
2075 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
2076 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
f07e9af3 | 2077 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { |
c1d2a196 MC |
2078 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); |
2079 | tg3_writephy(tp, MII_TG3_TEST1, | |
2080 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2081 | } else | |
2082 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
c424cb24 MC |
2083 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
2084 | } | |
1da177e4 LT |
2085 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2086 | /* support jumbo frames */ | |
79eb6904 | 2087 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
2088 | /* Cannot do read-modify-write on 5401 */ |
2089 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
8f666b07 | 2090 | } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 LT |
2091 | /* Set bit 14 with read-modify-write to preserve other bits */ |
2092 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) && | |
f833c4c1 MC |
2093 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) |
2094 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000); | |
1da177e4 LT |
2095 | } |
2096 | ||
2097 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2098 | * jumbo frames transmission. | |
2099 | */ | |
8f666b07 | 2100 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
f833c4c1 | 2101 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
c6cdf436 | 2102 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
f833c4c1 | 2103 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
1da177e4 LT |
2104 | } |
2105 | ||
715116a1 | 2106 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2107 | /* adjust output voltage */ |
535ef6e1 | 2108 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2109 | } |
2110 | ||
9ef8ca99 | 2111 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2112 | tg3_phy_set_wirespeed(tp); |
2113 | return 0; | |
2114 | } | |
2115 | ||
2116 | static void tg3_frob_aux_power(struct tg3 *tp) | |
2117 | { | |
683644b7 | 2118 | bool need_vaux = false; |
1da177e4 | 2119 | |
334355aa MC |
2120 | /* The GPIOs do something completely different on 57765. */ |
2121 | if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 || | |
a50d0796 | 2122 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
334355aa | 2123 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
1da177e4 LT |
2124 | return; |
2125 | ||
683644b7 MC |
2126 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
2127 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
d78b59f5 MC |
2128 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
2129 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) && | |
683644b7 | 2130 | tp->pdev_peer != tp->pdev) { |
8c2dc7e1 MC |
2131 | struct net_device *dev_peer; |
2132 | ||
2133 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
683644b7 | 2134 | |
bc1c7567 | 2135 | /* remove_one() may have been run on the peer. */ |
683644b7 MC |
2136 | if (dev_peer) { |
2137 | struct tg3 *tp_peer = netdev_priv(dev_peer); | |
2138 | ||
2139 | if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) | |
2140 | return; | |
2141 | ||
2142 | if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) || | |
2143 | (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
2144 | need_vaux = true; | |
2145 | } | |
1da177e4 LT |
2146 | } |
2147 | ||
683644b7 MC |
2148 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) || |
2149 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
2150 | need_vaux = true; | |
2151 | ||
2152 | if (need_vaux) { | |
1da177e4 LT |
2153 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2154 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
b401e9e2 MC |
2155 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2156 | (GRC_LCLCTRL_GPIO_OE0 | | |
2157 | GRC_LCLCTRL_GPIO_OE1 | | |
2158 | GRC_LCLCTRL_GPIO_OE2 | | |
2159 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2160 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2161 | 100); | |
8d519ab2 MC |
2162 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
2163 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
2164 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ |
2165 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2166 | GRC_LCLCTRL_GPIO_OE1 | | |
2167 | GRC_LCLCTRL_GPIO_OE2 | | |
2168 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2169 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2170 | tp->grc_local_ctrl; | |
2171 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2172 | ||
2173 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2174 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2175 | ||
2176 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2177 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1da177e4 LT |
2178 | } else { |
2179 | u32 no_gpio2; | |
dc56b7d4 | 2180 | u32 grc_local_ctrl = 0; |
1da177e4 | 2181 | |
dc56b7d4 MC |
2182 | /* Workaround to prevent overdrawing Amps. */ |
2183 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2184 | ASIC_REV_5714) { | |
2185 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
b401e9e2 MC |
2186 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2187 | grc_local_ctrl, 100); | |
dc56b7d4 MC |
2188 | } |
2189 | ||
1da177e4 LT |
2190 | /* On 5753 and variants, GPIO2 cannot be used. */ |
2191 | no_gpio2 = tp->nic_sram_data_cfg & | |
2192 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2193 | ||
dc56b7d4 | 2194 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | |
1da177e4 LT |
2195 | GRC_LCLCTRL_GPIO_OE1 | |
2196 | GRC_LCLCTRL_GPIO_OE2 | | |
2197 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2198 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2199 | if (no_gpio2) { | |
2200 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2201 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2202 | } | |
b401e9e2 MC |
2203 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2204 | grc_local_ctrl, 100); | |
1da177e4 LT |
2205 | |
2206 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2207 | ||
b401e9e2 MC |
2208 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2209 | grc_local_ctrl, 100); | |
1da177e4 LT |
2210 | |
2211 | if (!no_gpio2) { | |
2212 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
b401e9e2 MC |
2213 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2214 | grc_local_ctrl, 100); | |
1da177e4 LT |
2215 | } |
2216 | } | |
2217 | } else { | |
2218 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2219 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
b401e9e2 MC |
2220 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2221 | (GRC_LCLCTRL_GPIO_OE1 | | |
2222 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 | 2223 | |
b401e9e2 MC |
2224 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2225 | GRC_LCLCTRL_GPIO_OE1, 100); | |
1da177e4 | 2226 | |
b401e9e2 MC |
2227 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2228 | (GRC_LCLCTRL_GPIO_OE1 | | |
2229 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 LT |
2230 | } |
2231 | } | |
2232 | } | |
2233 | ||
e8f3f6ca MC |
2234 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2235 | { | |
2236 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2237 | return 1; | |
79eb6904 | 2238 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2239 | if (speed != SPEED_10) |
2240 | return 1; | |
2241 | } else if (speed == SPEED_10) | |
2242 | return 1; | |
2243 | ||
2244 | return 0; | |
2245 | } | |
2246 | ||
1da177e4 LT |
2247 | static int tg3_setup_phy(struct tg3 *, int); |
2248 | ||
2249 | #define RESET_KIND_SHUTDOWN 0 | |
2250 | #define RESET_KIND_INIT 1 | |
2251 | #define RESET_KIND_SUSPEND 2 | |
2252 | ||
2253 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2254 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2255 | ||
0a459aac | 2256 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2257 | { |
ce057f01 MC |
2258 | u32 val; |
2259 | ||
f07e9af3 | 2260 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
5129724a MC |
2261 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
2262 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2263 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2264 | ||
2265 | sg_dig_ctrl |= | |
2266 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2267 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2268 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2269 | } | |
3f7045c1 | 2270 | return; |
5129724a | 2271 | } |
3f7045c1 | 2272 | |
60189ddf | 2273 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2274 | tg3_bmcr_reset(tp); |
2275 | val = tr32(GRC_MISC_CFG); | |
2276 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2277 | udelay(40); | |
2278 | return; | |
f07e9af3 | 2279 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
0e5f784c MC |
2280 | u32 phytest; |
2281 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2282 | u32 phy; | |
2283 | ||
2284 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2285 | tg3_writephy(tp, MII_BMCR, | |
2286 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2287 | ||
2288 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2289 | phytest | MII_TG3_FET_SHADOW_EN); | |
2290 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2291 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2292 | tg3_writephy(tp, | |
2293 | MII_TG3_FET_SHDW_AUXMODE4, | |
2294 | phy); | |
2295 | } | |
2296 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2297 | } | |
2298 | return; | |
0a459aac | 2299 | } else if (do_low_power) { |
715116a1 MC |
2300 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2301 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac MC |
2302 | |
2303 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
2304 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL | | |
2305 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2306 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2307 | MII_TG3_AUXCTL_PCTL_VREG_11V); | |
715116a1 | 2308 | } |
3f7045c1 | 2309 | |
15c3b696 MC |
2310 | /* The PHY should not be powered down on some chips because |
2311 | * of bugs. | |
2312 | */ | |
2313 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2314 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2315 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
f07e9af3 | 2316 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
15c3b696 | 2317 | return; |
ce057f01 | 2318 | |
bcb37f6c MC |
2319 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2320 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2321 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2322 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2323 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2324 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2325 | } | |
2326 | ||
15c3b696 MC |
2327 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2328 | } | |
2329 | ||
ffbcfed4 MC |
2330 | /* tp->lock is held. */ |
2331 | static int tg3_nvram_lock(struct tg3 *tp) | |
2332 | { | |
2333 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2334 | int i; | |
2335 | ||
2336 | if (tp->nvram_lock_cnt == 0) { | |
2337 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2338 | for (i = 0; i < 8000; i++) { | |
2339 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2340 | break; | |
2341 | udelay(20); | |
2342 | } | |
2343 | if (i == 8000) { | |
2344 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2345 | return -ENODEV; | |
2346 | } | |
2347 | } | |
2348 | tp->nvram_lock_cnt++; | |
2349 | } | |
2350 | return 0; | |
2351 | } | |
2352 | ||
2353 | /* tp->lock is held. */ | |
2354 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2355 | { | |
2356 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2357 | if (tp->nvram_lock_cnt > 0) | |
2358 | tp->nvram_lock_cnt--; | |
2359 | if (tp->nvram_lock_cnt == 0) | |
2360 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2361 | } | |
2362 | } | |
2363 | ||
2364 | /* tp->lock is held. */ | |
2365 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2366 | { | |
2367 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2368 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2369 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2370 | ||
2371 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2372 | } | |
2373 | } | |
2374 | ||
2375 | /* tp->lock is held. */ | |
2376 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2377 | { | |
2378 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2379 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2380 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2381 | ||
2382 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2383 | } | |
2384 | } | |
2385 | ||
2386 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2387 | u32 offset, u32 *val) | |
2388 | { | |
2389 | u32 tmp; | |
2390 | int i; | |
2391 | ||
2392 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2393 | return -EINVAL; | |
2394 | ||
2395 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2396 | EEPROM_ADDR_DEVID_MASK | | |
2397 | EEPROM_ADDR_READ); | |
2398 | tw32(GRC_EEPROM_ADDR, | |
2399 | tmp | | |
2400 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2401 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2402 | EEPROM_ADDR_ADDR_MASK) | | |
2403 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2404 | ||
2405 | for (i = 0; i < 1000; i++) { | |
2406 | tmp = tr32(GRC_EEPROM_ADDR); | |
2407 | ||
2408 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2409 | break; | |
2410 | msleep(1); | |
2411 | } | |
2412 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2413 | return -EBUSY; | |
2414 | ||
62cedd11 MC |
2415 | tmp = tr32(GRC_EEPROM_DATA); |
2416 | ||
2417 | /* | |
2418 | * The data will always be opposite the native endian | |
2419 | * format. Perform a blind byteswap to compensate. | |
2420 | */ | |
2421 | *val = swab32(tmp); | |
2422 | ||
ffbcfed4 MC |
2423 | return 0; |
2424 | } | |
2425 | ||
2426 | #define NVRAM_CMD_TIMEOUT 10000 | |
2427 | ||
2428 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2429 | { | |
2430 | int i; | |
2431 | ||
2432 | tw32(NVRAM_CMD, nvram_cmd); | |
2433 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2434 | udelay(10); | |
2435 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2436 | udelay(10); | |
2437 | break; | |
2438 | } | |
2439 | } | |
2440 | ||
2441 | if (i == NVRAM_CMD_TIMEOUT) | |
2442 | return -EBUSY; | |
2443 | ||
2444 | return 0; | |
2445 | } | |
2446 | ||
2447 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2448 | { | |
2449 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2450 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2451 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2452 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2453 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2454 | ||
2455 | addr = ((addr / tp->nvram_pagesize) << | |
2456 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2457 | (addr % tp->nvram_pagesize); | |
2458 | ||
2459 | return addr; | |
2460 | } | |
2461 | ||
2462 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2463 | { | |
2464 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2465 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2466 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2467 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2468 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2469 | ||
2470 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2471 | tp->nvram_pagesize) + | |
2472 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2473 | ||
2474 | return addr; | |
2475 | } | |
2476 | ||
e4f34110 MC |
2477 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2478 | * the byteswapping settings for all other register accesses. | |
2479 | * tg3 devices are BE devices, so on a BE machine, the data | |
2480 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2481 | * machine, the 32-bit value will be byteswapped. | |
2482 | */ | |
ffbcfed4 MC |
2483 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2484 | { | |
2485 | int ret; | |
2486 | ||
2487 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | |
2488 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
2489 | ||
2490 | offset = tg3_nvram_phys_addr(tp, offset); | |
2491 | ||
2492 | if (offset > NVRAM_ADDR_MSK) | |
2493 | return -EINVAL; | |
2494 | ||
2495 | ret = tg3_nvram_lock(tp); | |
2496 | if (ret) | |
2497 | return ret; | |
2498 | ||
2499 | tg3_enable_nvram_access(tp); | |
2500 | ||
2501 | tw32(NVRAM_ADDR, offset); | |
2502 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2503 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2504 | ||
2505 | if (ret == 0) | |
e4f34110 | 2506 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2507 | |
2508 | tg3_disable_nvram_access(tp); | |
2509 | ||
2510 | tg3_nvram_unlock(tp); | |
2511 | ||
2512 | return ret; | |
2513 | } | |
2514 | ||
a9dc529d MC |
2515 | /* Ensures NVRAM data is in bytestream format. */ |
2516 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2517 | { |
2518 | u32 v; | |
a9dc529d | 2519 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2520 | if (!res) |
a9dc529d | 2521 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2522 | return res; |
2523 | } | |
2524 | ||
3f007891 MC |
2525 | /* tp->lock is held. */ |
2526 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2527 | { | |
2528 | u32 addr_high, addr_low; | |
2529 | int i; | |
2530 | ||
2531 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2532 | tp->dev->dev_addr[1]); | |
2533 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2534 | (tp->dev->dev_addr[3] << 16) | | |
2535 | (tp->dev->dev_addr[4] << 8) | | |
2536 | (tp->dev->dev_addr[5] << 0)); | |
2537 | for (i = 0; i < 4; i++) { | |
2538 | if (i == 1 && skip_mac_1) | |
2539 | continue; | |
2540 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2541 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2542 | } | |
2543 | ||
2544 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2545 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2546 | for (i = 0; i < 12; i++) { | |
2547 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2548 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2549 | } | |
2550 | } | |
2551 | ||
2552 | addr_high = (tp->dev->dev_addr[0] + | |
2553 | tp->dev->dev_addr[1] + | |
2554 | tp->dev->dev_addr[2] + | |
2555 | tp->dev->dev_addr[3] + | |
2556 | tp->dev->dev_addr[4] + | |
2557 | tp->dev->dev_addr[5]) & | |
2558 | TX_BACKOFF_SEED_MASK; | |
2559 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2560 | } | |
2561 | ||
c866b7ea | 2562 | static void tg3_enable_register_access(struct tg3 *tp) |
1da177e4 | 2563 | { |
c866b7ea RW |
2564 | /* |
2565 | * Make sure register accesses (indirect or otherwise) will function | |
2566 | * correctly. | |
1da177e4 LT |
2567 | */ |
2568 | pci_write_config_dword(tp->pdev, | |
c866b7ea RW |
2569 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
2570 | } | |
1da177e4 | 2571 | |
c866b7ea RW |
2572 | static int tg3_power_up(struct tg3 *tp) |
2573 | { | |
2574 | tg3_enable_register_access(tp); | |
8c6bda1a | 2575 | |
c866b7ea | 2576 | pci_set_power_state(tp->pdev, PCI_D0); |
1da177e4 | 2577 | |
c866b7ea RW |
2578 | /* Switch out of Vaux if it is a NIC */ |
2579 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
2580 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); | |
1da177e4 | 2581 | |
c866b7ea RW |
2582 | return 0; |
2583 | } | |
1da177e4 | 2584 | |
c866b7ea RW |
2585 | static int tg3_power_down_prepare(struct tg3 *tp) |
2586 | { | |
2587 | u32 misc_host_ctrl; | |
2588 | bool device_should_wake, do_low_power; | |
2589 | ||
2590 | tg3_enable_register_access(tp); | |
5e7dfd0f MC |
2591 | |
2592 | /* Restore the CLKREQ setting. */ | |
2593 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2594 | u16 lnkctl; | |
2595 | ||
2596 | pci_read_config_word(tp->pdev, | |
2597 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2598 | &lnkctl); | |
2599 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2600 | pci_write_config_word(tp->pdev, | |
2601 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2602 | lnkctl); | |
2603 | } | |
2604 | ||
1da177e4 LT |
2605 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2606 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2607 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2608 | ||
c866b7ea | 2609 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
05ac4cb7 MC |
2610 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
2611 | ||
dd477003 | 2612 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
0a459aac | 2613 | do_low_power = false; |
f07e9af3 | 2614 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
80096068 | 2615 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
b02fd9e3 | 2616 | struct phy_device *phydev; |
0a459aac | 2617 | u32 phyid, advertising; |
b02fd9e3 | 2618 | |
3f0e3ad7 | 2619 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 2620 | |
80096068 | 2621 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
b02fd9e3 MC |
2622 | |
2623 | tp->link_config.orig_speed = phydev->speed; | |
2624 | tp->link_config.orig_duplex = phydev->duplex; | |
2625 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2626 | tp->link_config.orig_advertising = phydev->advertising; | |
2627 | ||
2628 | advertising = ADVERTISED_TP | | |
2629 | ADVERTISED_Pause | | |
2630 | ADVERTISED_Autoneg | | |
2631 | ADVERTISED_10baseT_Half; | |
2632 | ||
2633 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
05ac4cb7 | 2634 | device_should_wake) { |
b02fd9e3 MC |
2635 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) |
2636 | advertising |= | |
2637 | ADVERTISED_100baseT_Half | | |
2638 | ADVERTISED_100baseT_Full | | |
2639 | ADVERTISED_10baseT_Full; | |
2640 | else | |
2641 | advertising |= ADVERTISED_10baseT_Full; | |
2642 | } | |
2643 | ||
2644 | phydev->advertising = advertising; | |
2645 | ||
2646 | phy_start_aneg(phydev); | |
0a459aac MC |
2647 | |
2648 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
2649 | if (phyid != PHY_ID_BCMAC131) { |
2650 | phyid &= PHY_BCM_OUI_MASK; | |
2651 | if (phyid == PHY_BCM_OUI_1 || | |
2652 | phyid == PHY_BCM_OUI_2 || | |
2653 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
2654 | do_low_power = true; |
2655 | } | |
b02fd9e3 | 2656 | } |
dd477003 | 2657 | } else { |
2023276e | 2658 | do_low_power = true; |
0a459aac | 2659 | |
80096068 MC |
2660 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
2661 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
2662 | tp->link_config.orig_speed = tp->link_config.speed; |
2663 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2664 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2665 | } | |
1da177e4 | 2666 | |
f07e9af3 | 2667 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
dd477003 MC |
2668 | tp->link_config.speed = SPEED_10; |
2669 | tp->link_config.duplex = DUPLEX_HALF; | |
2670 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2671 | tg3_setup_phy(tp, 0); | |
2672 | } | |
1da177e4 LT |
2673 | } |
2674 | ||
b5d3772c MC |
2675 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2676 | u32 val; | |
2677 | ||
2678 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2679 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2680 | } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
6921d201 MC |
2681 | int i; |
2682 | u32 val; | |
2683 | ||
2684 | for (i = 0; i < 200; i++) { | |
2685 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2686 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2687 | break; | |
2688 | msleep(1); | |
2689 | } | |
2690 | } | |
a85feb8c GZ |
2691 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
2692 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2693 | WOL_DRV_STATE_SHUTDOWN | | |
2694 | WOL_DRV_WOL | | |
2695 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2696 | |
05ac4cb7 | 2697 | if (device_should_wake) { |
1da177e4 LT |
2698 | u32 mac_mode; |
2699 | ||
f07e9af3 | 2700 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
0a459aac | 2701 | if (do_low_power) { |
dd477003 MC |
2702 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); |
2703 | udelay(40); | |
2704 | } | |
1da177e4 | 2705 | |
f07e9af3 | 2706 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
3f7045c1 MC |
2707 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
2708 | else | |
2709 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2710 | |
e8f3f6ca MC |
2711 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2712 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2713 | ASIC_REV_5700) { | |
2714 | u32 speed = (tp->tg3_flags & | |
2715 | TG3_FLAG_WOL_SPEED_100MB) ? | |
2716 | SPEED_100 : SPEED_10; | |
2717 | if (tg3_5700_link_polarity(tp, speed)) | |
2718 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2719 | else | |
2720 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2721 | } | |
1da177e4 LT |
2722 | } else { |
2723 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2724 | } | |
2725 | ||
cbf46853 | 2726 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) |
1da177e4 LT |
2727 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2728 | ||
05ac4cb7 MC |
2729 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
2730 | if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
2731 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && | |
2732 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2733 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))) | |
2734 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
1da177e4 | 2735 | |
d2394e6b MC |
2736 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
2737 | mac_mode |= MAC_MODE_APE_TX_EN | | |
2738 | MAC_MODE_APE_RX_EN | | |
2739 | MAC_MODE_TDE_ENABLE; | |
3bda1258 | 2740 | |
1da177e4 LT |
2741 | tw32_f(MAC_MODE, mac_mode); |
2742 | udelay(100); | |
2743 | ||
2744 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2745 | udelay(10); | |
2746 | } | |
2747 | ||
2748 | if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && | |
2749 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2750 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2751 | u32 base_val; | |
2752 | ||
2753 | base_val = tp->pci_clock_ctrl; | |
2754 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2755 | CLOCK_CTRL_TXCLK_DISABLE); | |
2756 | ||
b401e9e2 MC |
2757 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2758 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
d7b0a857 | 2759 | } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
795d01c5 | 2760 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
d7b0a857 | 2761 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { |
4cf78e4f | 2762 | /* do nothing */ |
85e94ced | 2763 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
1da177e4 LT |
2764 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { |
2765 | u32 newbits1, newbits2; | |
2766 | ||
2767 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2768 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2769 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2770 | CLOCK_CTRL_TXCLK_DISABLE | | |
2771 | CLOCK_CTRL_ALTCLK); | |
2772 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2773 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
2774 | newbits1 = CLOCK_CTRL_625_CORE; | |
2775 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2776 | } else { | |
2777 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2778 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2779 | } | |
2780 | ||
b401e9e2 MC |
2781 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2782 | 40); | |
1da177e4 | 2783 | |
b401e9e2 MC |
2784 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2785 | 40); | |
1da177e4 LT |
2786 | |
2787 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
2788 | u32 newbits3; | |
2789 | ||
2790 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2791 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2792 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2793 | CLOCK_CTRL_TXCLK_DISABLE | | |
2794 | CLOCK_CTRL_44MHZ_CORE); | |
2795 | } else { | |
2796 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2797 | } | |
2798 | ||
b401e9e2 MC |
2799 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
2800 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
2801 | } |
2802 | } | |
2803 | ||
05ac4cb7 | 2804 | if (!(device_should_wake) && |
22435849 | 2805 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
0a459aac | 2806 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 2807 | |
1da177e4 LT |
2808 | tg3_frob_aux_power(tp); |
2809 | ||
2810 | /* Workaround for unstable PLL clock */ | |
2811 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2812 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2813 | u32 val = tr32(0x7d00); | |
2814 | ||
2815 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2816 | tw32(0x7d00, val); | |
6921d201 | 2817 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
ec41c7df MC |
2818 | int err; |
2819 | ||
2820 | err = tg3_nvram_lock(tp); | |
1da177e4 | 2821 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
2822 | if (!err) |
2823 | tg3_nvram_unlock(tp); | |
6921d201 | 2824 | } |
1da177e4 LT |
2825 | } |
2826 | ||
bbadf503 MC |
2827 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
2828 | ||
c866b7ea RW |
2829 | return 0; |
2830 | } | |
12dac075 | 2831 | |
c866b7ea RW |
2832 | static void tg3_power_down(struct tg3 *tp) |
2833 | { | |
2834 | tg3_power_down_prepare(tp); | |
1da177e4 | 2835 | |
c866b7ea RW |
2836 | pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
2837 | pci_set_power_state(tp->pdev, PCI_D3hot); | |
1da177e4 LT |
2838 | } |
2839 | ||
1da177e4 LT |
2840 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
2841 | { | |
2842 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2843 | case MII_TG3_AUX_STAT_10HALF: | |
2844 | *speed = SPEED_10; | |
2845 | *duplex = DUPLEX_HALF; | |
2846 | break; | |
2847 | ||
2848 | case MII_TG3_AUX_STAT_10FULL: | |
2849 | *speed = SPEED_10; | |
2850 | *duplex = DUPLEX_FULL; | |
2851 | break; | |
2852 | ||
2853 | case MII_TG3_AUX_STAT_100HALF: | |
2854 | *speed = SPEED_100; | |
2855 | *duplex = DUPLEX_HALF; | |
2856 | break; | |
2857 | ||
2858 | case MII_TG3_AUX_STAT_100FULL: | |
2859 | *speed = SPEED_100; | |
2860 | *duplex = DUPLEX_FULL; | |
2861 | break; | |
2862 | ||
2863 | case MII_TG3_AUX_STAT_1000HALF: | |
2864 | *speed = SPEED_1000; | |
2865 | *duplex = DUPLEX_HALF; | |
2866 | break; | |
2867 | ||
2868 | case MII_TG3_AUX_STAT_1000FULL: | |
2869 | *speed = SPEED_1000; | |
2870 | *duplex = DUPLEX_FULL; | |
2871 | break; | |
2872 | ||
2873 | default: | |
f07e9af3 | 2874 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
715116a1 MC |
2875 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
2876 | SPEED_10; | |
2877 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2878 | DUPLEX_HALF; | |
2879 | break; | |
2880 | } | |
1da177e4 LT |
2881 | *speed = SPEED_INVALID; |
2882 | *duplex = DUPLEX_INVALID; | |
2883 | break; | |
855e1111 | 2884 | } |
1da177e4 LT |
2885 | } |
2886 | ||
2887 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
2888 | { | |
2889 | u32 new_adv; | |
2890 | int i; | |
2891 | ||
80096068 | 2892 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
1da177e4 LT |
2893 | /* Entering low power mode. Disable gigabit and |
2894 | * 100baseT advertisements. | |
2895 | */ | |
2896 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2897 | ||
2898 | new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2899 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
2900 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2901 | new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); | |
2902 | ||
2903 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2904 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
f07e9af3 | 2905 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
1da177e4 LT |
2906 | tp->link_config.advertising &= |
2907 | ~(ADVERTISED_1000baseT_Half | | |
2908 | ADVERTISED_1000baseT_Full); | |
2909 | ||
ba4d07a8 | 2910 | new_adv = ADVERTISE_CSMA; |
1da177e4 LT |
2911 | if (tp->link_config.advertising & ADVERTISED_10baseT_Half) |
2912 | new_adv |= ADVERTISE_10HALF; | |
2913 | if (tp->link_config.advertising & ADVERTISED_10baseT_Full) | |
2914 | new_adv |= ADVERTISE_10FULL; | |
2915 | if (tp->link_config.advertising & ADVERTISED_100baseT_Half) | |
2916 | new_adv |= ADVERTISE_100HALF; | |
2917 | if (tp->link_config.advertising & ADVERTISED_100baseT_Full) | |
2918 | new_adv |= ADVERTISE_100FULL; | |
ba4d07a8 MC |
2919 | |
2920 | new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2921 | ||
1da177e4 LT |
2922 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2923 | ||
2924 | if (tp->link_config.advertising & | |
2925 | (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { | |
2926 | new_adv = 0; | |
2927 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
2928 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2929 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
2930 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
f07e9af3 | 2931 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) && |
1da177e4 LT |
2932 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
2933 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) | |
2934 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2935 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2936 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2937 | } else { | |
2938 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2939 | } | |
2940 | } else { | |
ba4d07a8 MC |
2941 | new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); |
2942 | new_adv |= ADVERTISE_CSMA; | |
2943 | ||
1da177e4 LT |
2944 | /* Asking for a specific link mode. */ |
2945 | if (tp->link_config.speed == SPEED_1000) { | |
1da177e4 LT |
2946 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2947 | ||
2948 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2949 | new_adv = MII_TG3_CTRL_ADV_1000_FULL; | |
2950 | else | |
2951 | new_adv = MII_TG3_CTRL_ADV_1000_HALF; | |
2952 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2953 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2954 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2955 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
1da177e4 | 2956 | } else { |
1da177e4 LT |
2957 | if (tp->link_config.speed == SPEED_100) { |
2958 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2959 | new_adv |= ADVERTISE_100FULL; | |
2960 | else | |
2961 | new_adv |= ADVERTISE_100HALF; | |
2962 | } else { | |
2963 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2964 | new_adv |= ADVERTISE_10FULL; | |
2965 | else | |
2966 | new_adv |= ADVERTISE_10HALF; | |
2967 | } | |
2968 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
ba4d07a8 MC |
2969 | |
2970 | new_adv = 0; | |
1da177e4 | 2971 | } |
ba4d07a8 MC |
2972 | |
2973 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
1da177e4 LT |
2974 | } |
2975 | ||
52b02d04 | 2976 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { |
a6b68dab | 2977 | u32 val; |
52b02d04 MC |
2978 | |
2979 | tw32(TG3_CPMU_EEE_MODE, | |
2980 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); | |
2981 | ||
2982 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
2983 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
2984 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
2985 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
2986 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
2987 | ||
21a00ab2 MC |
2988 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
2989 | case ASIC_REV_5717: | |
2990 | case ASIC_REV_57765: | |
2991 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) | |
2992 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | | |
2993 | MII_TG3_DSP_CH34TP2_HIBW01); | |
2994 | /* Fall through */ | |
2995 | case ASIC_REV_5719: | |
2996 | val = MII_TG3_DSP_TAP26_ALNOKO | | |
2997 | MII_TG3_DSP_TAP26_RMRXSTO | | |
2998 | MII_TG3_DSP_TAP26_OPCSINPT; | |
2999 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | |
3000 | } | |
52b02d04 | 3001 | |
a6b68dab | 3002 | val = 0; |
52b02d04 MC |
3003 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { |
3004 | /* Advertise 100-BaseTX EEE ability */ | |
3005 | if (tp->link_config.advertising & | |
3110f5f5 MC |
3006 | ADVERTISED_100baseT_Full) |
3007 | val |= MDIO_AN_EEE_ADV_100TX; | |
52b02d04 MC |
3008 | /* Advertise 1000-BaseT EEE ability */ |
3009 | if (tp->link_config.advertising & | |
3110f5f5 MC |
3010 | ADVERTISED_1000baseT_Full) |
3011 | val |= MDIO_AN_EEE_ADV_1000T; | |
52b02d04 | 3012 | } |
3110f5f5 | 3013 | tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); |
52b02d04 MC |
3014 | |
3015 | /* Turn off SM_DSP clock. */ | |
3016 | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
3017 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
3018 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
3019 | } | |
3020 | ||
1da177e4 LT |
3021 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
3022 | tp->link_config.speed != SPEED_INVALID) { | |
3023 | u32 bmcr, orig_bmcr; | |
3024 | ||
3025 | tp->link_config.active_speed = tp->link_config.speed; | |
3026 | tp->link_config.active_duplex = tp->link_config.duplex; | |
3027 | ||
3028 | bmcr = 0; | |
3029 | switch (tp->link_config.speed) { | |
3030 | default: | |
3031 | case SPEED_10: | |
3032 | break; | |
3033 | ||
3034 | case SPEED_100: | |
3035 | bmcr |= BMCR_SPEED100; | |
3036 | break; | |
3037 | ||
3038 | case SPEED_1000: | |
3039 | bmcr |= TG3_BMCR_SPEED1000; | |
3040 | break; | |
855e1111 | 3041 | } |
1da177e4 LT |
3042 | |
3043 | if (tp->link_config.duplex == DUPLEX_FULL) | |
3044 | bmcr |= BMCR_FULLDPLX; | |
3045 | ||
3046 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
3047 | (bmcr != orig_bmcr)) { | |
3048 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
3049 | for (i = 0; i < 1500; i++) { | |
3050 | u32 tmp; | |
3051 | ||
3052 | udelay(10); | |
3053 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
3054 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
3055 | continue; | |
3056 | if (!(tmp & BMSR_LSTATUS)) { | |
3057 | udelay(40); | |
3058 | break; | |
3059 | } | |
3060 | } | |
3061 | tg3_writephy(tp, MII_BMCR, bmcr); | |
3062 | udelay(40); | |
3063 | } | |
3064 | } else { | |
3065 | tg3_writephy(tp, MII_BMCR, | |
3066 | BMCR_ANENABLE | BMCR_ANRESTART); | |
3067 | } | |
3068 | } | |
3069 | ||
3070 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
3071 | { | |
3072 | int err; | |
3073 | ||
3074 | /* Turn off tap power management. */ | |
3075 | /* Set Extended packet length bit */ | |
3076 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
3077 | ||
6ee7c0a0 MC |
3078 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
3079 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); | |
3080 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); | |
3081 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); | |
3082 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); | |
1da177e4 LT |
3083 | |
3084 | udelay(40); | |
3085 | ||
3086 | return err; | |
3087 | } | |
3088 | ||
3600d918 | 3089 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 3090 | { |
3600d918 MC |
3091 | u32 adv_reg, all_mask = 0; |
3092 | ||
3093 | if (mask & ADVERTISED_10baseT_Half) | |
3094 | all_mask |= ADVERTISE_10HALF; | |
3095 | if (mask & ADVERTISED_10baseT_Full) | |
3096 | all_mask |= ADVERTISE_10FULL; | |
3097 | if (mask & ADVERTISED_100baseT_Half) | |
3098 | all_mask |= ADVERTISE_100HALF; | |
3099 | if (mask & ADVERTISED_100baseT_Full) | |
3100 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
3101 | |
3102 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
3103 | return 0; | |
3104 | ||
1da177e4 LT |
3105 | if ((adv_reg & all_mask) != all_mask) |
3106 | return 0; | |
f07e9af3 | 3107 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
3108 | u32 tg3_ctrl; |
3109 | ||
3600d918 MC |
3110 | all_mask = 0; |
3111 | if (mask & ADVERTISED_1000baseT_Half) | |
3112 | all_mask |= ADVERTISE_1000HALF; | |
3113 | if (mask & ADVERTISED_1000baseT_Full) | |
3114 | all_mask |= ADVERTISE_1000FULL; | |
3115 | ||
1da177e4 LT |
3116 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) |
3117 | return 0; | |
3118 | ||
1da177e4 LT |
3119 | if ((tg3_ctrl & all_mask) != all_mask) |
3120 | return 0; | |
3121 | } | |
3122 | return 1; | |
3123 | } | |
3124 | ||
ef167e27 MC |
3125 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
3126 | { | |
3127 | u32 curadv, reqadv; | |
3128 | ||
3129 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3130 | return 1; | |
3131 | ||
3132 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3133 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3134 | ||
3135 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3136 | if (curadv != reqadv) | |
3137 | return 0; | |
3138 | ||
3139 | if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) | |
3140 | tg3_readphy(tp, MII_LPA, rmtadv); | |
3141 | } else { | |
3142 | /* Reprogram the advertisement register, even if it | |
3143 | * does not affect the current link. If the link | |
3144 | * gets renegotiated in the future, we can save an | |
3145 | * additional renegotiation cycle by advertising | |
3146 | * it correctly in the first place. | |
3147 | */ | |
3148 | if (curadv != reqadv) { | |
3149 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3150 | ADVERTISE_PAUSE_ASYM); | |
3151 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3152 | } | |
3153 | } | |
3154 | ||
3155 | return 1; | |
3156 | } | |
3157 | ||
1da177e4 LT |
3158 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3159 | { | |
3160 | int current_link_up; | |
f833c4c1 | 3161 | u32 bmsr, val; |
ef167e27 | 3162 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3163 | u16 current_speed; |
3164 | u8 current_duplex; | |
3165 | int i, err; | |
3166 | ||
3167 | tw32(MAC_EVENT, 0); | |
3168 | ||
3169 | tw32_f(MAC_STATUS, | |
3170 | (MAC_STATUS_SYNC_CHANGED | | |
3171 | MAC_STATUS_CFG_CHANGED | | |
3172 | MAC_STATUS_MI_COMPLETION | | |
3173 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3174 | udelay(40); | |
3175 | ||
8ef21428 MC |
3176 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3177 | tw32_f(MAC_MI_MODE, | |
3178 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3179 | udelay(80); | |
3180 | } | |
1da177e4 LT |
3181 | |
3182 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); | |
3183 | ||
3184 | /* Some third-party PHYs need to be reset on link going | |
3185 | * down. | |
3186 | */ | |
3187 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3188 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3189 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3190 | netif_carrier_ok(tp->dev)) { | |
3191 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3192 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3193 | !(bmsr & BMSR_LSTATUS)) | |
3194 | force_reset = 1; | |
3195 | } | |
3196 | if (force_reset) | |
3197 | tg3_phy_reset(tp); | |
3198 | ||
79eb6904 | 3199 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3200 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3201 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
3202 | !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) | |
3203 | bmsr = 0; | |
3204 | ||
3205 | if (!(bmsr & BMSR_LSTATUS)) { | |
3206 | err = tg3_init_5401phy_dsp(tp); | |
3207 | if (err) | |
3208 | return err; | |
3209 | ||
3210 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3211 | for (i = 0; i < 1000; i++) { | |
3212 | udelay(10); | |
3213 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3214 | (bmsr & BMSR_LSTATUS)) { | |
3215 | udelay(40); | |
3216 | break; | |
3217 | } | |
3218 | } | |
3219 | ||
79eb6904 MC |
3220 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3221 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3222 | !(bmsr & BMSR_LSTATUS) && |
3223 | tp->link_config.active_speed == SPEED_1000) { | |
3224 | err = tg3_phy_reset(tp); | |
3225 | if (!err) | |
3226 | err = tg3_init_5401phy_dsp(tp); | |
3227 | if (err) | |
3228 | return err; | |
3229 | } | |
3230 | } | |
3231 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3232 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3233 | /* 5701 {A0,B0} CRC bug workaround */ | |
3234 | tg3_writephy(tp, 0x15, 0x0a75); | |
f08aa1a8 MC |
3235 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
3236 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); | |
3237 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | |
1da177e4 LT |
3238 | } |
3239 | ||
3240 | /* Clear pending interrupts... */ | |
f833c4c1 MC |
3241 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
3242 | tg3_readphy(tp, MII_TG3_ISTAT, &val); | |
1da177e4 | 3243 | |
f07e9af3 | 3244 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
1da177e4 | 3245 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
f07e9af3 | 3246 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
1da177e4 LT |
3247 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3248 | ||
3249 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3250 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3251 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3252 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3253 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3254 | else | |
3255 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3256 | } | |
3257 | ||
3258 | current_link_up = 0; | |
3259 | current_speed = SPEED_INVALID; | |
3260 | current_duplex = DUPLEX_INVALID; | |
3261 | ||
f07e9af3 | 3262 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
1da177e4 LT |
3263 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007); |
3264 | tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); | |
3265 | if (!(val & (1 << 10))) { | |
3266 | val |= (1 << 10); | |
3267 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
3268 | goto relink; | |
3269 | } | |
3270 | } | |
3271 | ||
3272 | bmsr = 0; | |
3273 | for (i = 0; i < 100; i++) { | |
3274 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3275 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3276 | (bmsr & BMSR_LSTATUS)) | |
3277 | break; | |
3278 | udelay(40); | |
3279 | } | |
3280 | ||
3281 | if (bmsr & BMSR_LSTATUS) { | |
3282 | u32 aux_stat, bmcr; | |
3283 | ||
3284 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3285 | for (i = 0; i < 2000; i++) { | |
3286 | udelay(10); | |
3287 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3288 | aux_stat) | |
3289 | break; | |
3290 | } | |
3291 | ||
3292 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3293 | ¤t_speed, | |
3294 | ¤t_duplex); | |
3295 | ||
3296 | bmcr = 0; | |
3297 | for (i = 0; i < 200; i++) { | |
3298 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3299 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3300 | continue; | |
3301 | if (bmcr && bmcr != 0x7fff) | |
3302 | break; | |
3303 | udelay(10); | |
3304 | } | |
3305 | ||
ef167e27 MC |
3306 | lcl_adv = 0; |
3307 | rmt_adv = 0; | |
1da177e4 | 3308 | |
ef167e27 MC |
3309 | tp->link_config.active_speed = current_speed; |
3310 | tp->link_config.active_duplex = current_duplex; | |
3311 | ||
3312 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3313 | if ((bmcr & BMCR_ANENABLE) && | |
3314 | tg3_copper_is_advertising_all(tp, | |
3315 | tp->link_config.advertising)) { | |
3316 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3317 | &rmt_adv)) | |
3318 | current_link_up = 1; | |
1da177e4 LT |
3319 | } |
3320 | } else { | |
3321 | if (!(bmcr & BMCR_ANENABLE) && | |
3322 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3323 | tp->link_config.duplex == current_duplex && |
3324 | tp->link_config.flowctrl == | |
3325 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3326 | current_link_up = 1; |
1da177e4 LT |
3327 | } |
3328 | } | |
3329 | ||
ef167e27 MC |
3330 | if (current_link_up == 1 && |
3331 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3332 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3333 | } |
3334 | ||
1da177e4 | 3335 | relink: |
80096068 | 3336 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
1da177e4 LT |
3337 | tg3_phy_copper_begin(tp); |
3338 | ||
f833c4c1 MC |
3339 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3340 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3341 | (bmsr & BMSR_LSTATUS)) | |
1da177e4 LT |
3342 | current_link_up = 1; |
3343 | } | |
3344 | ||
3345 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3346 | if (current_link_up == 1) { | |
3347 | if (tp->link_config.active_speed == SPEED_100 || | |
3348 | tp->link_config.active_speed == SPEED_10) | |
3349 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3350 | else | |
3351 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
f07e9af3 | 3352 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
7f97a4bd MC |
3353 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
3354 | else | |
1da177e4 LT |
3355 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3356 | ||
3357 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3358 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3359 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3360 | ||
1da177e4 | 3361 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3362 | if (current_link_up == 1 && |
3363 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3364 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3365 | else |
3366 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3367 | } |
3368 | ||
3369 | /* ??? Without this setting Netgear GA302T PHY does not | |
3370 | * ??? send/receive packets... | |
3371 | */ | |
79eb6904 | 3372 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
3373 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
3374 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3375 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3376 | udelay(80); | |
3377 | } | |
3378 | ||
3379 | tw32_f(MAC_MODE, tp->mac_mode); | |
3380 | udelay(40); | |
3381 | ||
52b02d04 MC |
3382 | tg3_phy_eee_adjust(tp, current_link_up); |
3383 | ||
1da177e4 LT |
3384 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
3385 | /* Polled via timer. */ | |
3386 | tw32_f(MAC_EVENT, 0); | |
3387 | } else { | |
3388 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3389 | } | |
3390 | udelay(40); | |
3391 | ||
3392 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3393 | current_link_up == 1 && | |
3394 | tp->link_config.active_speed == SPEED_1000 && | |
3395 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || | |
3396 | (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { | |
3397 | udelay(120); | |
3398 | tw32_f(MAC_STATUS, | |
3399 | (MAC_STATUS_SYNC_CHANGED | | |
3400 | MAC_STATUS_CFG_CHANGED)); | |
3401 | udelay(40); | |
3402 | tg3_write_mem(tp, | |
3403 | NIC_SRAM_FIRMWARE_MBOX, | |
3404 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3405 | } | |
3406 | ||
5e7dfd0f MC |
3407 | /* Prevent send BD corruption. */ |
3408 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
3409 | u16 oldlnkctl, newlnkctl; | |
3410 | ||
3411 | pci_read_config_word(tp->pdev, | |
3412 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3413 | &oldlnkctl); | |
3414 | if (tp->link_config.active_speed == SPEED_100 || | |
3415 | tp->link_config.active_speed == SPEED_10) | |
3416 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3417 | else | |
3418 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3419 | if (newlnkctl != oldlnkctl) | |
3420 | pci_write_config_word(tp->pdev, | |
3421 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3422 | newlnkctl); | |
3423 | } | |
3424 | ||
1da177e4 LT |
3425 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3426 | if (current_link_up) | |
3427 | netif_carrier_on(tp->dev); | |
3428 | else | |
3429 | netif_carrier_off(tp->dev); | |
3430 | tg3_link_report(tp); | |
3431 | } | |
3432 | ||
3433 | return 0; | |
3434 | } | |
3435 | ||
3436 | struct tg3_fiber_aneginfo { | |
3437 | int state; | |
3438 | #define ANEG_STATE_UNKNOWN 0 | |
3439 | #define ANEG_STATE_AN_ENABLE 1 | |
3440 | #define ANEG_STATE_RESTART_INIT 2 | |
3441 | #define ANEG_STATE_RESTART 3 | |
3442 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3443 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3444 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3445 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3446 | #define ANEG_STATE_ACK_DETECT 8 | |
3447 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3448 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3449 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3450 | #define ANEG_STATE_IDLE_DETECT 12 | |
3451 | #define ANEG_STATE_LINK_OK 13 | |
3452 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3453 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3454 | ||
3455 | u32 flags; | |
3456 | #define MR_AN_ENABLE 0x00000001 | |
3457 | #define MR_RESTART_AN 0x00000002 | |
3458 | #define MR_AN_COMPLETE 0x00000004 | |
3459 | #define MR_PAGE_RX 0x00000008 | |
3460 | #define MR_NP_LOADED 0x00000010 | |
3461 | #define MR_TOGGLE_TX 0x00000020 | |
3462 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3463 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3464 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3465 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3466 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3467 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3468 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3469 | #define MR_TOGGLE_RX 0x00002000 | |
3470 | #define MR_NP_RX 0x00004000 | |
3471 | ||
3472 | #define MR_LINK_OK 0x80000000 | |
3473 | ||
3474 | unsigned long link_time, cur_time; | |
3475 | ||
3476 | u32 ability_match_cfg; | |
3477 | int ability_match_count; | |
3478 | ||
3479 | char ability_match, idle_match, ack_match; | |
3480 | ||
3481 | u32 txconfig, rxconfig; | |
3482 | #define ANEG_CFG_NP 0x00000080 | |
3483 | #define ANEG_CFG_ACK 0x00000040 | |
3484 | #define ANEG_CFG_RF2 0x00000020 | |
3485 | #define ANEG_CFG_RF1 0x00000010 | |
3486 | #define ANEG_CFG_PS2 0x00000001 | |
3487 | #define ANEG_CFG_PS1 0x00008000 | |
3488 | #define ANEG_CFG_HD 0x00004000 | |
3489 | #define ANEG_CFG_FD 0x00002000 | |
3490 | #define ANEG_CFG_INVAL 0x00001f06 | |
3491 | ||
3492 | }; | |
3493 | #define ANEG_OK 0 | |
3494 | #define ANEG_DONE 1 | |
3495 | #define ANEG_TIMER_ENAB 2 | |
3496 | #define ANEG_FAILED -1 | |
3497 | ||
3498 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3499 | ||
3500 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3501 | struct tg3_fiber_aneginfo *ap) | |
3502 | { | |
5be73b47 | 3503 | u16 flowctrl; |
1da177e4 LT |
3504 | unsigned long delta; |
3505 | u32 rx_cfg_reg; | |
3506 | int ret; | |
3507 | ||
3508 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3509 | ap->rxconfig = 0; | |
3510 | ap->link_time = 0; | |
3511 | ap->cur_time = 0; | |
3512 | ap->ability_match_cfg = 0; | |
3513 | ap->ability_match_count = 0; | |
3514 | ap->ability_match = 0; | |
3515 | ap->idle_match = 0; | |
3516 | ap->ack_match = 0; | |
3517 | } | |
3518 | ap->cur_time++; | |
3519 | ||
3520 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3521 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3522 | ||
3523 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3524 | ap->ability_match_cfg = rx_cfg_reg; | |
3525 | ap->ability_match = 0; | |
3526 | ap->ability_match_count = 0; | |
3527 | } else { | |
3528 | if (++ap->ability_match_count > 1) { | |
3529 | ap->ability_match = 1; | |
3530 | ap->ability_match_cfg = rx_cfg_reg; | |
3531 | } | |
3532 | } | |
3533 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3534 | ap->ack_match = 1; | |
3535 | else | |
3536 | ap->ack_match = 0; | |
3537 | ||
3538 | ap->idle_match = 0; | |
3539 | } else { | |
3540 | ap->idle_match = 1; | |
3541 | ap->ability_match_cfg = 0; | |
3542 | ap->ability_match_count = 0; | |
3543 | ap->ability_match = 0; | |
3544 | ap->ack_match = 0; | |
3545 | ||
3546 | rx_cfg_reg = 0; | |
3547 | } | |
3548 | ||
3549 | ap->rxconfig = rx_cfg_reg; | |
3550 | ret = ANEG_OK; | |
3551 | ||
33f401ae | 3552 | switch (ap->state) { |
1da177e4 LT |
3553 | case ANEG_STATE_UNKNOWN: |
3554 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3555 | ap->state = ANEG_STATE_AN_ENABLE; | |
3556 | ||
3557 | /* fallthru */ | |
3558 | case ANEG_STATE_AN_ENABLE: | |
3559 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3560 | if (ap->flags & MR_AN_ENABLE) { | |
3561 | ap->link_time = 0; | |
3562 | ap->cur_time = 0; | |
3563 | ap->ability_match_cfg = 0; | |
3564 | ap->ability_match_count = 0; | |
3565 | ap->ability_match = 0; | |
3566 | ap->idle_match = 0; | |
3567 | ap->ack_match = 0; | |
3568 | ||
3569 | ap->state = ANEG_STATE_RESTART_INIT; | |
3570 | } else { | |
3571 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3572 | } | |
3573 | break; | |
3574 | ||
3575 | case ANEG_STATE_RESTART_INIT: | |
3576 | ap->link_time = ap->cur_time; | |
3577 | ap->flags &= ~(MR_NP_LOADED); | |
3578 | ap->txconfig = 0; | |
3579 | tw32(MAC_TX_AUTO_NEG, 0); | |
3580 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3581 | tw32_f(MAC_MODE, tp->mac_mode); | |
3582 | udelay(40); | |
3583 | ||
3584 | ret = ANEG_TIMER_ENAB; | |
3585 | ap->state = ANEG_STATE_RESTART; | |
3586 | ||
3587 | /* fallthru */ | |
3588 | case ANEG_STATE_RESTART: | |
3589 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 3590 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 3591 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 3592 | else |
1da177e4 | 3593 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
3594 | break; |
3595 | ||
3596 | case ANEG_STATE_DISABLE_LINK_OK: | |
3597 | ret = ANEG_DONE; | |
3598 | break; | |
3599 | ||
3600 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3601 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3602 | ap->txconfig = ANEG_CFG_FD; |
3603 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3604 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3605 | ap->txconfig |= ANEG_CFG_PS1; | |
3606 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3607 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3608 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3609 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3610 | tw32_f(MAC_MODE, tp->mac_mode); | |
3611 | udelay(40); | |
3612 | ||
3613 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3614 | break; | |
3615 | ||
3616 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 3617 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 3618 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
3619 | break; |
3620 | ||
3621 | case ANEG_STATE_ACK_DETECT_INIT: | |
3622 | ap->txconfig |= ANEG_CFG_ACK; | |
3623 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3624 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3625 | tw32_f(MAC_MODE, tp->mac_mode); | |
3626 | udelay(40); | |
3627 | ||
3628 | ap->state = ANEG_STATE_ACK_DETECT; | |
3629 | ||
3630 | /* fallthru */ | |
3631 | case ANEG_STATE_ACK_DETECT: | |
3632 | if (ap->ack_match != 0) { | |
3633 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3634 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3635 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3636 | } else { | |
3637 | ap->state = ANEG_STATE_AN_ENABLE; | |
3638 | } | |
3639 | } else if (ap->ability_match != 0 && | |
3640 | ap->rxconfig == 0) { | |
3641 | ap->state = ANEG_STATE_AN_ENABLE; | |
3642 | } | |
3643 | break; | |
3644 | ||
3645 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3646 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3647 | ret = ANEG_FAILED; | |
3648 | break; | |
3649 | } | |
3650 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3651 | MR_LP_ADV_HALF_DUPLEX | | |
3652 | MR_LP_ADV_SYM_PAUSE | | |
3653 | MR_LP_ADV_ASYM_PAUSE | | |
3654 | MR_LP_ADV_REMOTE_FAULT1 | | |
3655 | MR_LP_ADV_REMOTE_FAULT2 | | |
3656 | MR_LP_ADV_NEXT_PAGE | | |
3657 | MR_TOGGLE_RX | | |
3658 | MR_NP_RX); | |
3659 | if (ap->rxconfig & ANEG_CFG_FD) | |
3660 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3661 | if (ap->rxconfig & ANEG_CFG_HD) | |
3662 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3663 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3664 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3665 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3666 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3667 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3668 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3669 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3670 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3671 | if (ap->rxconfig & ANEG_CFG_NP) | |
3672 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3673 | ||
3674 | ap->link_time = ap->cur_time; | |
3675 | ||
3676 | ap->flags ^= (MR_TOGGLE_TX); | |
3677 | if (ap->rxconfig & 0x0008) | |
3678 | ap->flags |= MR_TOGGLE_RX; | |
3679 | if (ap->rxconfig & ANEG_CFG_NP) | |
3680 | ap->flags |= MR_NP_RX; | |
3681 | ap->flags |= MR_PAGE_RX; | |
3682 | ||
3683 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3684 | ret = ANEG_TIMER_ENAB; | |
3685 | break; | |
3686 | ||
3687 | case ANEG_STATE_COMPLETE_ACK: | |
3688 | if (ap->ability_match != 0 && | |
3689 | ap->rxconfig == 0) { | |
3690 | ap->state = ANEG_STATE_AN_ENABLE; | |
3691 | break; | |
3692 | } | |
3693 | delta = ap->cur_time - ap->link_time; | |
3694 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3695 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3696 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3697 | } else { | |
3698 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3699 | !(ap->flags & MR_NP_RX)) { | |
3700 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3701 | } else { | |
3702 | ret = ANEG_FAILED; | |
3703 | } | |
3704 | } | |
3705 | } | |
3706 | break; | |
3707 | ||
3708 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3709 | ap->link_time = ap->cur_time; | |
3710 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3711 | tw32_f(MAC_MODE, tp->mac_mode); | |
3712 | udelay(40); | |
3713 | ||
3714 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3715 | ret = ANEG_TIMER_ENAB; | |
3716 | break; | |
3717 | ||
3718 | case ANEG_STATE_IDLE_DETECT: | |
3719 | if (ap->ability_match != 0 && | |
3720 | ap->rxconfig == 0) { | |
3721 | ap->state = ANEG_STATE_AN_ENABLE; | |
3722 | break; | |
3723 | } | |
3724 | delta = ap->cur_time - ap->link_time; | |
3725 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3726 | /* XXX another gem from the Broadcom driver :( */ | |
3727 | ap->state = ANEG_STATE_LINK_OK; | |
3728 | } | |
3729 | break; | |
3730 | ||
3731 | case ANEG_STATE_LINK_OK: | |
3732 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3733 | ret = ANEG_DONE; | |
3734 | break; | |
3735 | ||
3736 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3737 | /* ??? unimplemented */ | |
3738 | break; | |
3739 | ||
3740 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3741 | /* ??? unimplemented */ | |
3742 | break; | |
3743 | ||
3744 | default: | |
3745 | ret = ANEG_FAILED; | |
3746 | break; | |
855e1111 | 3747 | } |
1da177e4 LT |
3748 | |
3749 | return ret; | |
3750 | } | |
3751 | ||
5be73b47 | 3752 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3753 | { |
3754 | int res = 0; | |
3755 | struct tg3_fiber_aneginfo aninfo; | |
3756 | int status = ANEG_FAILED; | |
3757 | unsigned int tick; | |
3758 | u32 tmp; | |
3759 | ||
3760 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3761 | ||
3762 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3763 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3764 | udelay(40); | |
3765 | ||
3766 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3767 | udelay(40); | |
3768 | ||
3769 | memset(&aninfo, 0, sizeof(aninfo)); | |
3770 | aninfo.flags |= MR_AN_ENABLE; | |
3771 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3772 | aninfo.cur_time = 0; | |
3773 | tick = 0; | |
3774 | while (++tick < 195000) { | |
3775 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3776 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3777 | break; | |
3778 | ||
3779 | udelay(1); | |
3780 | } | |
3781 | ||
3782 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3783 | tw32_f(MAC_MODE, tp->mac_mode); | |
3784 | udelay(40); | |
3785 | ||
5be73b47 MC |
3786 | *txflags = aninfo.txconfig; |
3787 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3788 | |
3789 | if (status == ANEG_DONE && | |
3790 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3791 | MR_LP_ADV_FULL_DUPLEX))) | |
3792 | res = 1; | |
3793 | ||
3794 | return res; | |
3795 | } | |
3796 | ||
3797 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3798 | { | |
3799 | u32 mac_status = tr32(MAC_STATUS); | |
3800 | int i; | |
3801 | ||
3802 | /* Reset when initting first time or we have a link. */ | |
3803 | if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && | |
3804 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3805 | return; | |
3806 | ||
3807 | /* Set PLL lock range. */ | |
3808 | tg3_writephy(tp, 0x16, 0x8007); | |
3809 | ||
3810 | /* SW reset */ | |
3811 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3812 | ||
3813 | /* Wait for reset to complete. */ | |
3814 | /* XXX schedule_timeout() ... */ | |
3815 | for (i = 0; i < 500; i++) | |
3816 | udelay(10); | |
3817 | ||
3818 | /* Config mode; select PMA/Ch 1 regs. */ | |
3819 | tg3_writephy(tp, 0x10, 0x8411); | |
3820 | ||
3821 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3822 | tg3_writephy(tp, 0x11, 0x0a10); | |
3823 | ||
3824 | tg3_writephy(tp, 0x18, 0x00a0); | |
3825 | tg3_writephy(tp, 0x16, 0x41ff); | |
3826 | ||
3827 | /* Assert and deassert POR. */ | |
3828 | tg3_writephy(tp, 0x13, 0x0400); | |
3829 | udelay(40); | |
3830 | tg3_writephy(tp, 0x13, 0x0000); | |
3831 | ||
3832 | tg3_writephy(tp, 0x11, 0x0a50); | |
3833 | udelay(40); | |
3834 | tg3_writephy(tp, 0x11, 0x0a10); | |
3835 | ||
3836 | /* Wait for signal to stabilize */ | |
3837 | /* XXX schedule_timeout() ... */ | |
3838 | for (i = 0; i < 15000; i++) | |
3839 | udelay(10); | |
3840 | ||
3841 | /* Deselect the channel register so we can read the PHYID | |
3842 | * later. | |
3843 | */ | |
3844 | tg3_writephy(tp, 0x10, 0x8011); | |
3845 | } | |
3846 | ||
3847 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3848 | { | |
82cd3d11 | 3849 | u16 flowctrl; |
1da177e4 LT |
3850 | u32 sg_dig_ctrl, sg_dig_status; |
3851 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3852 | int workaround, port_a; | |
3853 | int current_link_up; | |
3854 | ||
3855 | serdes_cfg = 0; | |
3856 | expected_sg_dig_ctrl = 0; | |
3857 | workaround = 0; | |
3858 | port_a = 1; | |
3859 | current_link_up = 0; | |
3860 | ||
3861 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3862 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3863 | workaround = 1; | |
3864 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3865 | port_a = 0; | |
3866 | ||
3867 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3868 | /* preserve bits 20-23 for voltage regulator */ | |
3869 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3870 | } | |
3871 | ||
3872 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3873 | ||
3874 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 3875 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
3876 | if (workaround) { |
3877 | u32 val = serdes_cfg; | |
3878 | ||
3879 | if (port_a) | |
3880 | val |= 0xc010000; | |
3881 | else | |
3882 | val |= 0x4010000; | |
3883 | tw32_f(MAC_SERDES_CFG, val); | |
3884 | } | |
c98f6e3b MC |
3885 | |
3886 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
3887 | } |
3888 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3889 | tg3_setup_flow_control(tp, 0, 0); | |
3890 | current_link_up = 1; | |
3891 | } | |
3892 | goto out; | |
3893 | } | |
3894 | ||
3895 | /* Want auto-negotiation. */ | |
c98f6e3b | 3896 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 3897 | |
82cd3d11 MC |
3898 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
3899 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3900 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3901 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3902 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
3903 | |
3904 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
f07e9af3 | 3905 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
3d3ebe74 MC |
3906 | tp->serdes_counter && |
3907 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3908 | MAC_STATUS_RCVD_CFG)) == | |
3909 | MAC_STATUS_PCS_SYNCED)) { | |
3910 | tp->serdes_counter--; | |
3911 | current_link_up = 1; | |
3912 | goto out; | |
3913 | } | |
3914 | restart_autoneg: | |
1da177e4 LT |
3915 | if (workaround) |
3916 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 3917 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
3918 | udelay(5); |
3919 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3920 | ||
3d3ebe74 | 3921 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
f07e9af3 | 3922 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
3923 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
3924 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 3925 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
3926 | mac_status = tr32(MAC_STATUS); |
3927 | ||
c98f6e3b | 3928 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 3929 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
3930 | u32 local_adv = 0, remote_adv = 0; |
3931 | ||
3932 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3933 | local_adv |= ADVERTISE_1000XPAUSE; | |
3934 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3935 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 3936 | |
c98f6e3b | 3937 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 3938 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 3939 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 3940 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
3941 | |
3942 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3943 | current_link_up = 1; | |
3d3ebe74 | 3944 | tp->serdes_counter = 0; |
f07e9af3 | 3945 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
c98f6e3b | 3946 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
3947 | if (tp->serdes_counter) |
3948 | tp->serdes_counter--; | |
1da177e4 LT |
3949 | else { |
3950 | if (workaround) { | |
3951 | u32 val = serdes_cfg; | |
3952 | ||
3953 | if (port_a) | |
3954 | val |= 0xc010000; | |
3955 | else | |
3956 | val |= 0x4010000; | |
3957 | ||
3958 | tw32_f(MAC_SERDES_CFG, val); | |
3959 | } | |
3960 | ||
c98f6e3b | 3961 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
3962 | udelay(40); |
3963 | ||
3964 | /* Link parallel detection - link is up */ | |
3965 | /* only if we have PCS_SYNC and not */ | |
3966 | /* receiving config code words */ | |
3967 | mac_status = tr32(MAC_STATUS); | |
3968 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
3969 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
3970 | tg3_setup_flow_control(tp, 0, 0); | |
3971 | current_link_up = 1; | |
f07e9af3 MC |
3972 | tp->phy_flags |= |
3973 | TG3_PHYFLG_PARALLEL_DETECT; | |
3d3ebe74 MC |
3974 | tp->serdes_counter = |
3975 | SERDES_PARALLEL_DET_TIMEOUT; | |
3976 | } else | |
3977 | goto restart_autoneg; | |
1da177e4 LT |
3978 | } |
3979 | } | |
3d3ebe74 MC |
3980 | } else { |
3981 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
f07e9af3 | 3982 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
1da177e4 LT |
3983 | } |
3984 | ||
3985 | out: | |
3986 | return current_link_up; | |
3987 | } | |
3988 | ||
3989 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
3990 | { | |
3991 | int current_link_up = 0; | |
3992 | ||
5cf64b8a | 3993 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 3994 | goto out; |
1da177e4 LT |
3995 | |
3996 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 3997 | u32 txflags, rxflags; |
1da177e4 | 3998 | int i; |
6aa20a22 | 3999 | |
5be73b47 MC |
4000 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
4001 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 4002 | |
5be73b47 MC |
4003 | if (txflags & ANEG_CFG_PS1) |
4004 | local_adv |= ADVERTISE_1000XPAUSE; | |
4005 | if (txflags & ANEG_CFG_PS2) | |
4006 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
4007 | ||
4008 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
4009 | remote_adv |= LPA_1000XPAUSE; | |
4010 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
4011 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
4012 | |
4013 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4014 | ||
1da177e4 LT |
4015 | current_link_up = 1; |
4016 | } | |
4017 | for (i = 0; i < 30; i++) { | |
4018 | udelay(20); | |
4019 | tw32_f(MAC_STATUS, | |
4020 | (MAC_STATUS_SYNC_CHANGED | | |
4021 | MAC_STATUS_CFG_CHANGED)); | |
4022 | udelay(40); | |
4023 | if ((tr32(MAC_STATUS) & | |
4024 | (MAC_STATUS_SYNC_CHANGED | | |
4025 | MAC_STATUS_CFG_CHANGED)) == 0) | |
4026 | break; | |
4027 | } | |
4028 | ||
4029 | mac_status = tr32(MAC_STATUS); | |
4030 | if (current_link_up == 0 && | |
4031 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
4032 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
4033 | current_link_up = 1; | |
4034 | } else { | |
5be73b47 MC |
4035 | tg3_setup_flow_control(tp, 0, 0); |
4036 | ||
1da177e4 LT |
4037 | /* Forcing 1000FD link up. */ |
4038 | current_link_up = 1; | |
1da177e4 LT |
4039 | |
4040 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
4041 | udelay(40); | |
e8f3f6ca MC |
4042 | |
4043 | tw32_f(MAC_MODE, tp->mac_mode); | |
4044 | udelay(40); | |
1da177e4 LT |
4045 | } |
4046 | ||
4047 | out: | |
4048 | return current_link_up; | |
4049 | } | |
4050 | ||
4051 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
4052 | { | |
4053 | u32 orig_pause_cfg; | |
4054 | u16 orig_active_speed; | |
4055 | u8 orig_active_duplex; | |
4056 | u32 mac_status; | |
4057 | int current_link_up; | |
4058 | int i; | |
4059 | ||
8d018621 | 4060 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4061 | orig_active_speed = tp->link_config.active_speed; |
4062 | orig_active_duplex = tp->link_config.active_duplex; | |
4063 | ||
4064 | if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && | |
4065 | netif_carrier_ok(tp->dev) && | |
4066 | (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { | |
4067 | mac_status = tr32(MAC_STATUS); | |
4068 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
4069 | MAC_STATUS_SIGNAL_DET | | |
4070 | MAC_STATUS_CFG_CHANGED | | |
4071 | MAC_STATUS_RCVD_CFG); | |
4072 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
4073 | MAC_STATUS_SIGNAL_DET)) { | |
4074 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4075 | MAC_STATUS_CFG_CHANGED)); | |
4076 | return 0; | |
4077 | } | |
4078 | } | |
4079 | ||
4080 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
4081 | ||
4082 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
4083 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
4084 | tw32_f(MAC_MODE, tp->mac_mode); | |
4085 | udelay(40); | |
4086 | ||
79eb6904 | 4087 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
4088 | tg3_init_bcm8002(tp); |
4089 | ||
4090 | /* Enable link change event even when serdes polling. */ | |
4091 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4092 | udelay(40); | |
4093 | ||
4094 | current_link_up = 0; | |
4095 | mac_status = tr32(MAC_STATUS); | |
4096 | ||
4097 | if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) | |
4098 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
4099 | else | |
4100 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
4101 | ||
898a56f8 | 4102 | tp->napi[0].hw_status->status = |
1da177e4 | 4103 | (SD_STATUS_UPDATED | |
898a56f8 | 4104 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4105 | |
4106 | for (i = 0; i < 100; i++) { | |
4107 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4108 | MAC_STATUS_CFG_CHANGED)); | |
4109 | udelay(5); | |
4110 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4111 | MAC_STATUS_CFG_CHANGED | |
4112 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4113 | break; |
4114 | } | |
4115 | ||
4116 | mac_status = tr32(MAC_STATUS); | |
4117 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4118 | current_link_up = 0; | |
3d3ebe74 MC |
4119 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4120 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4121 | tw32_f(MAC_MODE, (tp->mac_mode | |
4122 | MAC_MODE_SEND_CONFIGS)); | |
4123 | udelay(1); | |
4124 | tw32_f(MAC_MODE, tp->mac_mode); | |
4125 | } | |
4126 | } | |
4127 | ||
4128 | if (current_link_up == 1) { | |
4129 | tp->link_config.active_speed = SPEED_1000; | |
4130 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4131 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4132 | LED_CTRL_LNKLED_OVERRIDE | | |
4133 | LED_CTRL_1000MBPS_ON)); | |
4134 | } else { | |
4135 | tp->link_config.active_speed = SPEED_INVALID; | |
4136 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4137 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4138 | LED_CTRL_LNKLED_OVERRIDE | | |
4139 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4140 | } | |
4141 | ||
4142 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4143 | if (current_link_up) | |
4144 | netif_carrier_on(tp->dev); | |
4145 | else | |
4146 | netif_carrier_off(tp->dev); | |
4147 | tg3_link_report(tp); | |
4148 | } else { | |
8d018621 | 4149 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4150 | if (orig_pause_cfg != now_pause_cfg || |
4151 | orig_active_speed != tp->link_config.active_speed || | |
4152 | orig_active_duplex != tp->link_config.active_duplex) | |
4153 | tg3_link_report(tp); | |
4154 | } | |
4155 | ||
4156 | return 0; | |
4157 | } | |
4158 | ||
747e8f8b MC |
4159 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4160 | { | |
4161 | int current_link_up, err = 0; | |
4162 | u32 bmsr, bmcr; | |
4163 | u16 current_speed; | |
4164 | u8 current_duplex; | |
ef167e27 | 4165 | u32 local_adv, remote_adv; |
747e8f8b MC |
4166 | |
4167 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4168 | tw32_f(MAC_MODE, tp->mac_mode); | |
4169 | udelay(40); | |
4170 | ||
4171 | tw32(MAC_EVENT, 0); | |
4172 | ||
4173 | tw32_f(MAC_STATUS, | |
4174 | (MAC_STATUS_SYNC_CHANGED | | |
4175 | MAC_STATUS_CFG_CHANGED | | |
4176 | MAC_STATUS_MI_COMPLETION | | |
4177 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4178 | udelay(40); | |
4179 | ||
4180 | if (force_reset) | |
4181 | tg3_phy_reset(tp); | |
4182 | ||
4183 | current_link_up = 0; | |
4184 | current_speed = SPEED_INVALID; | |
4185 | current_duplex = DUPLEX_INVALID; | |
4186 | ||
4187 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4188 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4189 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4190 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4191 | bmsr |= BMSR_LSTATUS; | |
4192 | else | |
4193 | bmsr &= ~BMSR_LSTATUS; | |
4194 | } | |
747e8f8b MC |
4195 | |
4196 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4197 | ||
4198 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
f07e9af3 | 4199 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4200 | /* do nothing, just check for link up at the end */ |
4201 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4202 | u32 adv, new_adv; | |
4203 | ||
4204 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4205 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4206 | ADVERTISE_1000XPAUSE | | |
4207 | ADVERTISE_1000XPSE_ASYM | | |
4208 | ADVERTISE_SLCT); | |
4209 | ||
ba4d07a8 | 4210 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4211 | |
4212 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4213 | new_adv |= ADVERTISE_1000XHALF; | |
4214 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4215 | new_adv |= ADVERTISE_1000XFULL; | |
4216 | ||
4217 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4218 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4219 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4220 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4221 | ||
4222 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4223 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
f07e9af3 | 4224 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4225 | |
4226 | return err; | |
4227 | } | |
4228 | } else { | |
4229 | u32 new_bmcr; | |
4230 | ||
4231 | bmcr &= ~BMCR_SPEED1000; | |
4232 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4233 | ||
4234 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4235 | new_bmcr |= BMCR_FULLDPLX; | |
4236 | ||
4237 | if (new_bmcr != bmcr) { | |
4238 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4239 | * to be set on write. | |
4240 | */ | |
4241 | new_bmcr |= BMCR_SPEED1000; | |
4242 | ||
4243 | /* Force a linkdown */ | |
4244 | if (netif_carrier_ok(tp->dev)) { | |
4245 | u32 adv; | |
4246 | ||
4247 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4248 | adv &= ~(ADVERTISE_1000XFULL | | |
4249 | ADVERTISE_1000XHALF | | |
4250 | ADVERTISE_SLCT); | |
4251 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4252 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4253 | BMCR_ANRESTART | | |
4254 | BMCR_ANENABLE); | |
4255 | udelay(10); | |
4256 | netif_carrier_off(tp->dev); | |
4257 | } | |
4258 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4259 | bmcr = new_bmcr; | |
4260 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4261 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4262 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4263 | ASIC_REV_5714) { | |
4264 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4265 | bmsr |= BMSR_LSTATUS; | |
4266 | else | |
4267 | bmsr &= ~BMSR_LSTATUS; | |
4268 | } | |
f07e9af3 | 4269 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4270 | } |
4271 | } | |
4272 | ||
4273 | if (bmsr & BMSR_LSTATUS) { | |
4274 | current_speed = SPEED_1000; | |
4275 | current_link_up = 1; | |
4276 | if (bmcr & BMCR_FULLDPLX) | |
4277 | current_duplex = DUPLEX_FULL; | |
4278 | else | |
4279 | current_duplex = DUPLEX_HALF; | |
4280 | ||
ef167e27 MC |
4281 | local_adv = 0; |
4282 | remote_adv = 0; | |
4283 | ||
747e8f8b | 4284 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4285 | u32 common; |
747e8f8b MC |
4286 | |
4287 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4288 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4289 | common = local_adv & remote_adv; | |
4290 | if (common & (ADVERTISE_1000XHALF | | |
4291 | ADVERTISE_1000XFULL)) { | |
4292 | if (common & ADVERTISE_1000XFULL) | |
4293 | current_duplex = DUPLEX_FULL; | |
4294 | else | |
4295 | current_duplex = DUPLEX_HALF; | |
57d8b880 MC |
4296 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
4297 | /* Link is up via parallel detect */ | |
859a5887 | 4298 | } else { |
747e8f8b | 4299 | current_link_up = 0; |
859a5887 | 4300 | } |
747e8f8b MC |
4301 | } |
4302 | } | |
4303 | ||
ef167e27 MC |
4304 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4305 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4306 | ||
747e8f8b MC |
4307 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4308 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4309 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4310 | ||
4311 | tw32_f(MAC_MODE, tp->mac_mode); | |
4312 | udelay(40); | |
4313 | ||
4314 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4315 | ||
4316 | tp->link_config.active_speed = current_speed; | |
4317 | tp->link_config.active_duplex = current_duplex; | |
4318 | ||
4319 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4320 | if (current_link_up) | |
4321 | netif_carrier_on(tp->dev); | |
4322 | else { | |
4323 | netif_carrier_off(tp->dev); | |
f07e9af3 | 4324 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4325 | } |
4326 | tg3_link_report(tp); | |
4327 | } | |
4328 | return err; | |
4329 | } | |
4330 | ||
4331 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4332 | { | |
3d3ebe74 | 4333 | if (tp->serdes_counter) { |
747e8f8b | 4334 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4335 | tp->serdes_counter--; |
747e8f8b MC |
4336 | return; |
4337 | } | |
c6cdf436 | 4338 | |
747e8f8b MC |
4339 | if (!netif_carrier_ok(tp->dev) && |
4340 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4341 | u32 bmcr; | |
4342 | ||
4343 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4344 | if (bmcr & BMCR_ANENABLE) { | |
4345 | u32 phy1, phy2; | |
4346 | ||
4347 | /* Select shadow register 0x1f */ | |
f08aa1a8 MC |
4348 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
4349 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); | |
747e8f8b MC |
4350 | |
4351 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4352 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4353 | MII_TG3_DSP_EXP1_INT_STAT); | |
4354 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
4355 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4356 | |
4357 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4358 | /* We have signal detect and not receiving | |
4359 | * config code words, link is up by parallel | |
4360 | * detection. | |
4361 | */ | |
4362 | ||
4363 | bmcr &= ~BMCR_ANENABLE; | |
4364 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4365 | tg3_writephy(tp, MII_BMCR, bmcr); | |
f07e9af3 | 4366 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4367 | } |
4368 | } | |
859a5887 MC |
4369 | } else if (netif_carrier_ok(tp->dev) && |
4370 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
f07e9af3 | 4371 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
747e8f8b MC |
4372 | u32 phy2; |
4373 | ||
4374 | /* Select expansion interrupt status register */ | |
f08aa1a8 MC |
4375 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
4376 | MII_TG3_DSP_EXP1_INT_STAT); | |
4377 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); | |
747e8f8b MC |
4378 | if (phy2 & 0x20) { |
4379 | u32 bmcr; | |
4380 | ||
4381 | /* Config code words received, turn on autoneg. */ | |
4382 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4383 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4384 | ||
f07e9af3 | 4385 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
747e8f8b MC |
4386 | |
4387 | } | |
4388 | } | |
4389 | } | |
4390 | ||
1da177e4 LT |
4391 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4392 | { | |
4393 | int err; | |
4394 | ||
f07e9af3 | 4395 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 | 4396 | err = tg3_setup_fiber_phy(tp, force_reset); |
f07e9af3 | 4397 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
747e8f8b | 4398 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 4399 | else |
1da177e4 | 4400 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 4401 | |
bcb37f6c | 4402 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
aa6c91fe MC |
4403 | u32 val, scale; |
4404 | ||
4405 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4406 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4407 | scale = 65; | |
4408 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4409 | scale = 6; | |
4410 | else | |
4411 | scale = 12; | |
4412 | ||
4413 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4414 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4415 | tw32(GRC_MISC_CFG, val); | |
4416 | } | |
4417 | ||
1da177e4 LT |
4418 | if (tp->link_config.active_speed == SPEED_1000 && |
4419 | tp->link_config.active_duplex == DUPLEX_HALF) | |
4420 | tw32(MAC_TX_LENGTHS, | |
4421 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4422 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4423 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4424 | else | |
4425 | tw32(MAC_TX_LENGTHS, | |
4426 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4427 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4428 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4429 | ||
4430 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4431 | if (netif_carrier_ok(tp->dev)) { | |
4432 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4433 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4434 | } else { |
4435 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4436 | } | |
4437 | } | |
4438 | ||
8ed5d97e MC |
4439 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { |
4440 | u32 val = tr32(PCIE_PWR_MGMT_THRESH); | |
4441 | if (!netif_carrier_ok(tp->dev)) | |
4442 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4443 | tp->pwrmgmt_thresh; | |
4444 | else | |
4445 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4446 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4447 | } | |
4448 | ||
1da177e4 LT |
4449 | return err; |
4450 | } | |
4451 | ||
66cfd1bd MC |
4452 | static inline int tg3_irq_sync(struct tg3 *tp) |
4453 | { | |
4454 | return tp->irq_sync; | |
4455 | } | |
4456 | ||
df3e6548 MC |
4457 | /* This is called whenever we suspect that the system chipset is re- |
4458 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4459 | * is bogus tx completions. We try to recover by setting the | |
4460 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4461 | * in the workqueue. | |
4462 | */ | |
4463 | static void tg3_tx_recover(struct tg3 *tp) | |
4464 | { | |
4465 | BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || | |
4466 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4467 | ||
5129c3a3 MC |
4468 | netdev_warn(tp->dev, |
4469 | "The system may be re-ordering memory-mapped I/O " | |
4470 | "cycles to the network device, attempting to recover. " | |
4471 | "Please report the problem to the driver maintainer " | |
4472 | "and include system chipset information.\n"); | |
df3e6548 MC |
4473 | |
4474 | spin_lock(&tp->lock); | |
df3e6548 | 4475 | tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; |
df3e6548 MC |
4476 | spin_unlock(&tp->lock); |
4477 | } | |
4478 | ||
f3f3f27e | 4479 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 | 4480 | { |
f65aac16 MC |
4481 | /* Tell compiler to fetch tx indices from memory. */ |
4482 | barrier(); | |
f3f3f27e MC |
4483 | return tnapi->tx_pending - |
4484 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4485 | } |
4486 | ||
1da177e4 LT |
4487 | /* Tigon3 never reports partial packet sends. So we do not |
4488 | * need special logic to handle SKBs that have not had all | |
4489 | * of their frags sent yet, like SunGEM does. | |
4490 | */ | |
17375d25 | 4491 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4492 | { |
17375d25 | 4493 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4494 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4495 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
4496 | struct netdev_queue *txq; |
4497 | int index = tnapi - tp->napi; | |
4498 | ||
19cfaecc | 4499 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 MC |
4500 | index--; |
4501 | ||
4502 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
4503 | |
4504 | while (sw_idx != hw_idx) { | |
f4188d8a | 4505 | struct ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4506 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4507 | int i, tx_bug = 0; |
4508 | ||
4509 | if (unlikely(skb == NULL)) { | |
4510 | tg3_tx_recover(tp); | |
4511 | return; | |
4512 | } | |
1da177e4 | 4513 | |
f4188d8a | 4514 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 4515 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4516 | skb_headlen(skb), |
4517 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4518 | |
4519 | ri->skb = NULL; | |
4520 | ||
4521 | sw_idx = NEXT_TX(sw_idx); | |
4522 | ||
4523 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4524 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4525 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4526 | tx_bug = 1; | |
f4188d8a AD |
4527 | |
4528 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 4529 | dma_unmap_addr(ri, mapping), |
f4188d8a AD |
4530 | skb_shinfo(skb)->frags[i].size, |
4531 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4532 | sw_idx = NEXT_TX(sw_idx); |
4533 | } | |
4534 | ||
f47c11ee | 4535 | dev_kfree_skb(skb); |
df3e6548 MC |
4536 | |
4537 | if (unlikely(tx_bug)) { | |
4538 | tg3_tx_recover(tp); | |
4539 | return; | |
4540 | } | |
1da177e4 LT |
4541 | } |
4542 | ||
f3f3f27e | 4543 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4544 | |
1b2a7205 MC |
4545 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4546 | * before checking for netif_queue_stopped(). Without the | |
4547 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4548 | * will miss it and cause the queue to be stopped forever. | |
4549 | */ | |
4550 | smp_mb(); | |
4551 | ||
fe5f5787 | 4552 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 4553 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
4554 | __netif_tx_lock(txq, smp_processor_id()); |
4555 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 4556 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
4557 | netif_tx_wake_queue(txq); |
4558 | __netif_tx_unlock(txq); | |
51b91468 | 4559 | } |
1da177e4 LT |
4560 | } |
4561 | ||
2b2cdb65 MC |
4562 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
4563 | { | |
4564 | if (!ri->skb) | |
4565 | return; | |
4566 | ||
4e5e4f0d | 4567 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
2b2cdb65 MC |
4568 | map_sz, PCI_DMA_FROMDEVICE); |
4569 | dev_kfree_skb_any(ri->skb); | |
4570 | ri->skb = NULL; | |
4571 | } | |
4572 | ||
1da177e4 LT |
4573 | /* Returns size of skb allocated or < 0 on error. |
4574 | * | |
4575 | * We only need to fill in the address because the other members | |
4576 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4577 | * | |
4578 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4579 | * posting buffers we only dirty the first cache line of the RX | |
4580 | * descriptor (containing the address). Whereas for the RX status | |
4581 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4582 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4583 | */ | |
86b21e59 | 4584 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 4585 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
4586 | { |
4587 | struct tg3_rx_buffer_desc *desc; | |
f94e290e | 4588 | struct ring_info *map; |
1da177e4 LT |
4589 | struct sk_buff *skb; |
4590 | dma_addr_t mapping; | |
4591 | int skb_size, dest_idx; | |
4592 | ||
1da177e4 LT |
4593 | switch (opaque_key) { |
4594 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4595 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
21f581a5 MC |
4596 | desc = &tpr->rx_std[dest_idx]; |
4597 | map = &tpr->rx_std_buffers[dest_idx]; | |
287be12e | 4598 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4599 | break; |
4600 | ||
4601 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4602 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
79ed5ac7 | 4603 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4604 | map = &tpr->rx_jmb_buffers[dest_idx]; |
287be12e | 4605 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4606 | break; |
4607 | ||
4608 | default: | |
4609 | return -EINVAL; | |
855e1111 | 4610 | } |
1da177e4 LT |
4611 | |
4612 | /* Do not overwrite any of the map or rp information | |
4613 | * until we are sure we can commit to a new buffer. | |
4614 | * | |
4615 | * Callers depend upon this behavior and assume that | |
4616 | * we leave everything unchanged if we fail. | |
4617 | */ | |
287be12e | 4618 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4619 | if (skb == NULL) |
4620 | return -ENOMEM; | |
4621 | ||
1da177e4 LT |
4622 | skb_reserve(skb, tp->rx_offset); |
4623 | ||
287be12e | 4624 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 4625 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
4626 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
4627 | dev_kfree_skb(skb); | |
4628 | return -EIO; | |
4629 | } | |
1da177e4 LT |
4630 | |
4631 | map->skb = skb; | |
4e5e4f0d | 4632 | dma_unmap_addr_set(map, mapping, mapping); |
1da177e4 | 4633 | |
1da177e4 LT |
4634 | desc->addr_hi = ((u64)mapping >> 32); |
4635 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4636 | ||
4637 | return skb_size; | |
4638 | } | |
4639 | ||
4640 | /* We only need to move over in the address because the other | |
4641 | * members of the RX descriptor are invariant. See notes above | |
4642 | * tg3_alloc_rx_skb for full details. | |
4643 | */ | |
a3896167 MC |
4644 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
4645 | struct tg3_rx_prodring_set *dpr, | |
4646 | u32 opaque_key, int src_idx, | |
4647 | u32 dest_idx_unmasked) | |
1da177e4 | 4648 | { |
17375d25 | 4649 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4650 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4651 | struct ring_info *src_map, *dest_map; | |
8fea32b9 | 4652 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
c6cdf436 | 4653 | int dest_idx; |
1da177e4 LT |
4654 | |
4655 | switch (opaque_key) { | |
4656 | case RXD_OPAQUE_RING_STD: | |
2c49a44d | 4657 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
a3896167 MC |
4658 | dest_desc = &dpr->rx_std[dest_idx]; |
4659 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4660 | src_desc = &spr->rx_std[src_idx]; | |
4661 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4662 | break; |
4663 | ||
4664 | case RXD_OPAQUE_RING_JUMBO: | |
2c49a44d | 4665 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
a3896167 MC |
4666 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
4667 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
4668 | src_desc = &spr->rx_jmb[src_idx].std; | |
4669 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
4670 | break; |
4671 | ||
4672 | default: | |
4673 | return; | |
855e1111 | 4674 | } |
1da177e4 LT |
4675 | |
4676 | dest_map->skb = src_map->skb; | |
4e5e4f0d FT |
4677 | dma_unmap_addr_set(dest_map, mapping, |
4678 | dma_unmap_addr(src_map, mapping)); | |
1da177e4 LT |
4679 | dest_desc->addr_hi = src_desc->addr_hi; |
4680 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
4681 | |
4682 | /* Ensure that the update to the skb happens after the physical | |
4683 | * addresses have been transferred to the new BD location. | |
4684 | */ | |
4685 | smp_wmb(); | |
4686 | ||
1da177e4 LT |
4687 | src_map->skb = NULL; |
4688 | } | |
4689 | ||
1da177e4 LT |
4690 | /* The RX ring scheme is composed of multiple rings which post fresh |
4691 | * buffers to the chip, and one special ring the chip uses to report | |
4692 | * status back to the host. | |
4693 | * | |
4694 | * The special ring reports the status of received packets to the | |
4695 | * host. The chip does not write into the original descriptor the | |
4696 | * RX buffer was obtained from. The chip simply takes the original | |
4697 | * descriptor as provided by the host, updates the status and length | |
4698 | * field, then writes this into the next status ring entry. | |
4699 | * | |
4700 | * Each ring the host uses to post buffers to the chip is described | |
4701 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4702 | * it is first placed into the on-chip ram. When the packet's length | |
4703 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4704 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4705 | * which is within the range of the new packet's length is chosen. | |
4706 | * | |
4707 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4708 | * sense from a cache coherency perspective. If only the host writes | |
4709 | * to the buffer post rings, and only the chip writes to the rx status | |
4710 | * rings, then cache lines never move beyond shared-modified state. | |
4711 | * If both the host and chip were to write into the same ring, cache line | |
4712 | * eviction could occur since both entities want it in an exclusive state. | |
4713 | */ | |
17375d25 | 4714 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 4715 | { |
17375d25 | 4716 | struct tg3 *tp = tnapi->tp; |
f92905de | 4717 | u32 work_mask, rx_std_posted = 0; |
4361935a | 4718 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 4719 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 4720 | u16 hw_idx; |
1da177e4 | 4721 | int received; |
8fea32b9 | 4722 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
1da177e4 | 4723 | |
8d9d7cfc | 4724 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
4725 | /* |
4726 | * We need to order the read of hw_idx and the read of | |
4727 | * the opaque cookie. | |
4728 | */ | |
4729 | rmb(); | |
1da177e4 LT |
4730 | work_mask = 0; |
4731 | received = 0; | |
4361935a MC |
4732 | std_prod_idx = tpr->rx_std_prod_idx; |
4733 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 4734 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 4735 | struct ring_info *ri; |
72334482 | 4736 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
4737 | unsigned int len; |
4738 | struct sk_buff *skb; | |
4739 | dma_addr_t dma_addr; | |
4740 | u32 opaque_key, desc_idx, *post_ptr; | |
4741 | ||
4742 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4743 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4744 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
8fea32b9 | 4745 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
4e5e4f0d | 4746 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4747 | skb = ri->skb; |
4361935a | 4748 | post_ptr = &std_prod_idx; |
f92905de | 4749 | rx_std_posted++; |
1da177e4 | 4750 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
8fea32b9 | 4751 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
4e5e4f0d | 4752 | dma_addr = dma_unmap_addr(ri, mapping); |
21f581a5 | 4753 | skb = ri->skb; |
4361935a | 4754 | post_ptr = &jmb_prod_idx; |
21f581a5 | 4755 | } else |
1da177e4 | 4756 | goto next_pkt_nopost; |
1da177e4 LT |
4757 | |
4758 | work_mask |= opaque_key; | |
4759 | ||
4760 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4761 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4762 | drop_it: | |
a3896167 | 4763 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4764 | desc_idx, *post_ptr); |
4765 | drop_it_no_recycle: | |
4766 | /* Other statistics kept track of by card. */ | |
b0057c51 | 4767 | tp->rx_dropped++; |
1da177e4 LT |
4768 | goto next_pkt; |
4769 | } | |
4770 | ||
ad829268 MC |
4771 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
4772 | ETH_FCS_LEN; | |
1da177e4 | 4773 | |
d2757fc4 | 4774 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
4775 | int skb_size; |
4776 | ||
86b21e59 | 4777 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, |
afc081f8 | 4778 | *post_ptr); |
1da177e4 LT |
4779 | if (skb_size < 0) |
4780 | goto drop_it; | |
4781 | ||
287be12e | 4782 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
4783 | PCI_DMA_FROMDEVICE); |
4784 | ||
61e800cf MC |
4785 | /* Ensure that the update to the skb happens |
4786 | * after the usage of the old DMA mapping. | |
4787 | */ | |
4788 | smp_wmb(); | |
4789 | ||
4790 | ri->skb = NULL; | |
4791 | ||
1da177e4 LT |
4792 | skb_put(skb, len); |
4793 | } else { | |
4794 | struct sk_buff *copy_skb; | |
4795 | ||
a3896167 | 4796 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4797 | desc_idx, *post_ptr); |
4798 | ||
bf933c80 | 4799 | copy_skb = netdev_alloc_skb(tp->dev, len + |
9dc7a113 | 4800 | TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4801 | if (copy_skb == NULL) |
4802 | goto drop_it_no_recycle; | |
4803 | ||
bf933c80 | 4804 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); |
1da177e4 LT |
4805 | skb_put(copy_skb, len); |
4806 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 4807 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
4808 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
4809 | ||
4810 | /* We'll reuse the original ring buffer. */ | |
4811 | skb = copy_skb; | |
4812 | } | |
4813 | ||
4814 | if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) && | |
4815 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
4816 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4817 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4818 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4819 | else | |
bc8acf2c | 4820 | skb_checksum_none_assert(skb); |
1da177e4 LT |
4821 | |
4822 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
4823 | |
4824 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4825 | skb->protocol != htons(ETH_P_8021Q)) { | |
4826 | dev_kfree_skb(skb); | |
b0057c51 | 4827 | goto drop_it_no_recycle; |
f7b493e0 MC |
4828 | } |
4829 | ||
9dc7a113 | 4830 | if (desc->type_flags & RXD_FLAG_VLAN && |
bf933c80 MC |
4831 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
4832 | __vlan_hwaccel_put_tag(skb, | |
4833 | desc->err_vlan & RXD_VLAN_MASK); | |
9dc7a113 | 4834 | |
bf933c80 | 4835 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 4836 | |
1da177e4 LT |
4837 | received++; |
4838 | budget--; | |
4839 | ||
4840 | next_pkt: | |
4841 | (*post_ptr)++; | |
f92905de MC |
4842 | |
4843 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
2c49a44d MC |
4844 | tpr->rx_std_prod_idx = std_prod_idx & |
4845 | tp->rx_std_ring_mask; | |
86cfe4ff MC |
4846 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
4847 | tpr->rx_std_prod_idx); | |
f92905de MC |
4848 | work_mask &= ~RXD_OPAQUE_RING_STD; |
4849 | rx_std_posted = 0; | |
4850 | } | |
1da177e4 | 4851 | next_pkt_nopost: |
483ba50b | 4852 | sw_idx++; |
7cb32cf2 | 4853 | sw_idx &= tp->rx_ret_ring_mask; |
52f6d697 MC |
4854 | |
4855 | /* Refresh hw_idx to see if there is new work */ | |
4856 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 4857 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
4858 | rmb(); |
4859 | } | |
1da177e4 LT |
4860 | } |
4861 | ||
4862 | /* ACK the status ring. */ | |
72334482 MC |
4863 | tnapi->rx_rcb_ptr = sw_idx; |
4864 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
4865 | |
4866 | /* Refill RX ring(s). */ | |
e4af1af9 | 4867 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { |
b196c7e4 | 4868 | if (work_mask & RXD_OPAQUE_RING_STD) { |
2c49a44d MC |
4869 | tpr->rx_std_prod_idx = std_prod_idx & |
4870 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
4871 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
4872 | tpr->rx_std_prod_idx); | |
4873 | } | |
4874 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
2c49a44d MC |
4875 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
4876 | tp->rx_jmb_ring_mask; | |
b196c7e4 MC |
4877 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
4878 | tpr->rx_jmb_prod_idx); | |
4879 | } | |
4880 | mmiowb(); | |
4881 | } else if (work_mask) { | |
4882 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
4883 | * updated before the producer indices can be updated. | |
4884 | */ | |
4885 | smp_wmb(); | |
4886 | ||
2c49a44d MC |
4887 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
4888 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; | |
b196c7e4 | 4889 | |
e4af1af9 MC |
4890 | if (tnapi != &tp->napi[1]) |
4891 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 4892 | } |
1da177e4 LT |
4893 | |
4894 | return received; | |
4895 | } | |
4896 | ||
35f2d7d0 | 4897 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 4898 | { |
1da177e4 LT |
4899 | /* handle link change and other phy events */ |
4900 | if (!(tp->tg3_flags & | |
4901 | (TG3_FLAG_USE_LINKCHG_REG | | |
4902 | TG3_FLAG_POLL_SERDES))) { | |
35f2d7d0 MC |
4903 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
4904 | ||
1da177e4 LT |
4905 | if (sblk->status & SD_STATUS_LINK_CHG) { |
4906 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 4907 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 4908 | spin_lock(&tp->lock); |
dd477003 MC |
4909 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
4910 | tw32_f(MAC_STATUS, | |
4911 | (MAC_STATUS_SYNC_CHANGED | | |
4912 | MAC_STATUS_CFG_CHANGED | | |
4913 | MAC_STATUS_MI_COMPLETION | | |
4914 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4915 | udelay(40); | |
4916 | } else | |
4917 | tg3_setup_phy(tp, 0); | |
f47c11ee | 4918 | spin_unlock(&tp->lock); |
1da177e4 LT |
4919 | } |
4920 | } | |
35f2d7d0 MC |
4921 | } |
4922 | ||
f89f38b8 MC |
4923 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
4924 | struct tg3_rx_prodring_set *dpr, | |
4925 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
4926 | { |
4927 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 4928 | int i, err = 0; |
b196c7e4 MC |
4929 | |
4930 | while (1) { | |
4931 | src_prod_idx = spr->rx_std_prod_idx; | |
4932 | ||
4933 | /* Make sure updates to the rx_std_buffers[] entries and the | |
4934 | * standard producer index are seen in the correct order. | |
4935 | */ | |
4936 | smp_rmb(); | |
4937 | ||
4938 | if (spr->rx_std_cons_idx == src_prod_idx) | |
4939 | break; | |
4940 | ||
4941 | if (spr->rx_std_cons_idx < src_prod_idx) | |
4942 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
4943 | else | |
2c49a44d MC |
4944 | cpycnt = tp->rx_std_ring_mask + 1 - |
4945 | spr->rx_std_cons_idx; | |
b196c7e4 | 4946 | |
2c49a44d MC |
4947 | cpycnt = min(cpycnt, |
4948 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); | |
b196c7e4 MC |
4949 | |
4950 | si = spr->rx_std_cons_idx; | |
4951 | di = dpr->rx_std_prod_idx; | |
4952 | ||
e92967bf MC |
4953 | for (i = di; i < di + cpycnt; i++) { |
4954 | if (dpr->rx_std_buffers[i].skb) { | |
4955 | cpycnt = i - di; | |
f89f38b8 | 4956 | err = -ENOSPC; |
e92967bf MC |
4957 | break; |
4958 | } | |
4959 | } | |
4960 | ||
4961 | if (!cpycnt) | |
4962 | break; | |
4963 | ||
4964 | /* Ensure that updates to the rx_std_buffers ring and the | |
4965 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
4966 | * ordered correctly WRT the skb check above. | |
4967 | */ | |
4968 | smp_rmb(); | |
4969 | ||
b196c7e4 MC |
4970 | memcpy(&dpr->rx_std_buffers[di], |
4971 | &spr->rx_std_buffers[si], | |
4972 | cpycnt * sizeof(struct ring_info)); | |
4973 | ||
4974 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
4975 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
4976 | sbd = &spr->rx_std[si]; | |
4977 | dbd = &dpr->rx_std[di]; | |
4978 | dbd->addr_hi = sbd->addr_hi; | |
4979 | dbd->addr_lo = sbd->addr_lo; | |
4980 | } | |
4981 | ||
2c49a44d MC |
4982 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
4983 | tp->rx_std_ring_mask; | |
4984 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & | |
4985 | tp->rx_std_ring_mask; | |
b196c7e4 MC |
4986 | } |
4987 | ||
4988 | while (1) { | |
4989 | src_prod_idx = spr->rx_jmb_prod_idx; | |
4990 | ||
4991 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
4992 | * the jumbo producer index are seen in the correct order. | |
4993 | */ | |
4994 | smp_rmb(); | |
4995 | ||
4996 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
4997 | break; | |
4998 | ||
4999 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
5000 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
5001 | else | |
2c49a44d MC |
5002 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
5003 | spr->rx_jmb_cons_idx; | |
b196c7e4 MC |
5004 | |
5005 | cpycnt = min(cpycnt, | |
2c49a44d | 5006 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
b196c7e4 MC |
5007 | |
5008 | si = spr->rx_jmb_cons_idx; | |
5009 | di = dpr->rx_jmb_prod_idx; | |
5010 | ||
e92967bf MC |
5011 | for (i = di; i < di + cpycnt; i++) { |
5012 | if (dpr->rx_jmb_buffers[i].skb) { | |
5013 | cpycnt = i - di; | |
f89f38b8 | 5014 | err = -ENOSPC; |
e92967bf MC |
5015 | break; |
5016 | } | |
5017 | } | |
5018 | ||
5019 | if (!cpycnt) | |
5020 | break; | |
5021 | ||
5022 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
5023 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
5024 | * ordered correctly WRT the skb check above. | |
5025 | */ | |
5026 | smp_rmb(); | |
5027 | ||
b196c7e4 MC |
5028 | memcpy(&dpr->rx_jmb_buffers[di], |
5029 | &spr->rx_jmb_buffers[si], | |
5030 | cpycnt * sizeof(struct ring_info)); | |
5031 | ||
5032 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
5033 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
5034 | sbd = &spr->rx_jmb[si].std; | |
5035 | dbd = &dpr->rx_jmb[di].std; | |
5036 | dbd->addr_hi = sbd->addr_hi; | |
5037 | dbd->addr_lo = sbd->addr_lo; | |
5038 | } | |
5039 | ||
2c49a44d MC |
5040 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
5041 | tp->rx_jmb_ring_mask; | |
5042 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & | |
5043 | tp->rx_jmb_ring_mask; | |
b196c7e4 | 5044 | } |
f89f38b8 MC |
5045 | |
5046 | return err; | |
b196c7e4 MC |
5047 | } |
5048 | ||
35f2d7d0 MC |
5049 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
5050 | { | |
5051 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
5052 | |
5053 | /* run TX completion thread */ | |
f3f3f27e | 5054 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 5055 | tg3_tx(tnapi); |
6f535763 | 5056 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) |
4fd7ab59 | 5057 | return work_done; |
1da177e4 LT |
5058 | } |
5059 | ||
1da177e4 LT |
5060 | /* run RX thread, within the bounds set by NAPI. |
5061 | * All RX "locking" is done by ensuring outside | |
bea3348e | 5062 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 5063 | */ |
8d9d7cfc | 5064 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 5065 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 5066 | |
b196c7e4 | 5067 | if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) { |
8fea32b9 | 5068 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
f89f38b8 | 5069 | int i, err = 0; |
e4af1af9 MC |
5070 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
5071 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 5072 | |
e4af1af9 | 5073 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 | 5074 | err |= tg3_rx_prodring_xfer(tp, dpr, |
8fea32b9 | 5075 | &tp->napi[i].prodring); |
b196c7e4 MC |
5076 | |
5077 | wmb(); | |
5078 | ||
e4af1af9 MC |
5079 | if (std_prod_idx != dpr->rx_std_prod_idx) |
5080 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
5081 | dpr->rx_std_prod_idx); | |
b196c7e4 | 5082 | |
e4af1af9 MC |
5083 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
5084 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
5085 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
5086 | |
5087 | mmiowb(); | |
f89f38b8 MC |
5088 | |
5089 | if (err) | |
5090 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
5091 | } |
5092 | ||
6f535763 DM |
5093 | return work_done; |
5094 | } | |
5095 | ||
35f2d7d0 MC |
5096 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5097 | { | |
5098 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5099 | struct tg3 *tp = tnapi->tp; | |
5100 | int work_done = 0; | |
5101 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5102 | ||
5103 | while (1) { | |
5104 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5105 | ||
5106 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5107 | goto tx_recovery; | |
5108 | ||
5109 | if (unlikely(work_done >= budget)) | |
5110 | break; | |
5111 | ||
c6cdf436 | 5112 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5113 | * to tell the hw how much work has been processed, |
5114 | * so we must read it before checking for more work. | |
5115 | */ | |
5116 | tnapi->last_tag = sblk->status_tag; | |
5117 | tnapi->last_irq_tag = tnapi->last_tag; | |
5118 | rmb(); | |
5119 | ||
5120 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5121 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5122 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5123 | napi_complete(napi); |
5124 | /* Reenable interrupts. */ | |
5125 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5126 | mmiowb(); | |
5127 | break; | |
5128 | } | |
5129 | } | |
5130 | ||
5131 | return work_done; | |
5132 | ||
5133 | tx_recovery: | |
5134 | /* work_done is guaranteed to be less than budget. */ | |
5135 | napi_complete(napi); | |
5136 | schedule_work(&tp->reset_task); | |
5137 | return work_done; | |
5138 | } | |
5139 | ||
6f535763 DM |
5140 | static int tg3_poll(struct napi_struct *napi, int budget) |
5141 | { | |
8ef0442f MC |
5142 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
5143 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 5144 | int work_done = 0; |
898a56f8 | 5145 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
5146 | |
5147 | while (1) { | |
35f2d7d0 MC |
5148 | tg3_poll_link(tp); |
5149 | ||
17375d25 | 5150 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 DM |
5151 | |
5152 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5153 | goto tx_recovery; | |
5154 | ||
5155 | if (unlikely(work_done >= budget)) | |
5156 | break; | |
5157 | ||
4fd7ab59 | 5158 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { |
17375d25 | 5159 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
5160 | * to tell the hw how much work has been processed, |
5161 | * so we must read it before checking for more work. | |
5162 | */ | |
898a56f8 MC |
5163 | tnapi->last_tag = sblk->status_tag; |
5164 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
5165 | rmb(); |
5166 | } else | |
5167 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 5168 | |
17375d25 | 5169 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 5170 | napi_complete(napi); |
17375d25 | 5171 | tg3_int_reenable(tnapi); |
6f535763 DM |
5172 | break; |
5173 | } | |
1da177e4 LT |
5174 | } |
5175 | ||
bea3348e | 5176 | return work_done; |
6f535763 DM |
5177 | |
5178 | tx_recovery: | |
4fd7ab59 | 5179 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 5180 | napi_complete(napi); |
6f535763 | 5181 | schedule_work(&tp->reset_task); |
4fd7ab59 | 5182 | return work_done; |
1da177e4 LT |
5183 | } |
5184 | ||
66cfd1bd MC |
5185 | static void tg3_napi_disable(struct tg3 *tp) |
5186 | { | |
5187 | int i; | |
5188 | ||
5189 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
5190 | napi_disable(&tp->napi[i].napi); | |
5191 | } | |
5192 | ||
5193 | static void tg3_napi_enable(struct tg3 *tp) | |
5194 | { | |
5195 | int i; | |
5196 | ||
5197 | for (i = 0; i < tp->irq_cnt; i++) | |
5198 | napi_enable(&tp->napi[i].napi); | |
5199 | } | |
5200 | ||
5201 | static void tg3_napi_init(struct tg3 *tp) | |
5202 | { | |
5203 | int i; | |
5204 | ||
5205 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); | |
5206 | for (i = 1; i < tp->irq_cnt; i++) | |
5207 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); | |
5208 | } | |
5209 | ||
5210 | static void tg3_napi_fini(struct tg3 *tp) | |
5211 | { | |
5212 | int i; | |
5213 | ||
5214 | for (i = 0; i < tp->irq_cnt; i++) | |
5215 | netif_napi_del(&tp->napi[i].napi); | |
5216 | } | |
5217 | ||
5218 | static inline void tg3_netif_stop(struct tg3 *tp) | |
5219 | { | |
5220 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5221 | tg3_napi_disable(tp); | |
5222 | netif_tx_disable(tp->dev); | |
5223 | } | |
5224 | ||
5225 | static inline void tg3_netif_start(struct tg3 *tp) | |
5226 | { | |
5227 | /* NOTE: unconditional netif_tx_wake_all_queues is only | |
5228 | * appropriate so long as all callers are assured to | |
5229 | * have free tx slots (such as after tg3_init_hw) | |
5230 | */ | |
5231 | netif_tx_wake_all_queues(tp->dev); | |
5232 | ||
5233 | tg3_napi_enable(tp); | |
5234 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
5235 | tg3_enable_ints(tp); | |
5236 | } | |
5237 | ||
f47c11ee DM |
5238 | static void tg3_irq_quiesce(struct tg3 *tp) |
5239 | { | |
4f125f42 MC |
5240 | int i; |
5241 | ||
f47c11ee DM |
5242 | BUG_ON(tp->irq_sync); |
5243 | ||
5244 | tp->irq_sync = 1; | |
5245 | smp_mb(); | |
5246 | ||
4f125f42 MC |
5247 | for (i = 0; i < tp->irq_cnt; i++) |
5248 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
5249 | } |
5250 | ||
f47c11ee DM |
5251 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
5252 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5253 | * with as well. Most of the time, this is not necessary except when | |
5254 | * shutting down the device. | |
5255 | */ | |
5256 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5257 | { | |
46966545 | 5258 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
5259 | if (irq_sync) |
5260 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
5261 | } |
5262 | ||
5263 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5264 | { | |
f47c11ee DM |
5265 | spin_unlock_bh(&tp->lock); |
5266 | } | |
5267 | ||
fcfa0a32 MC |
5268 | /* One-shot MSI handler - Chip automatically disables interrupt |
5269 | * after sending MSI so driver doesn't have to do it. | |
5270 | */ | |
7d12e780 | 5271 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 5272 | { |
09943a18 MC |
5273 | struct tg3_napi *tnapi = dev_id; |
5274 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 5275 | |
898a56f8 | 5276 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5277 | if (tnapi->rx_rcb) |
5278 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
5279 | |
5280 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 5281 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
5282 | |
5283 | return IRQ_HANDLED; | |
5284 | } | |
5285 | ||
88b06bc2 MC |
5286 | /* MSI ISR - No need to check for interrupt sharing and no need to |
5287 | * flush status block and interrupt mailbox. PCI ordering rules | |
5288 | * guarantee that MSI will arrive after the status block. | |
5289 | */ | |
7d12e780 | 5290 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 5291 | { |
09943a18 MC |
5292 | struct tg3_napi *tnapi = dev_id; |
5293 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 5294 | |
898a56f8 | 5295 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5296 | if (tnapi->rx_rcb) |
5297 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 5298 | /* |
fac9b83e | 5299 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 5300 | * chip-internal interrupt pending events. |
fac9b83e | 5301 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
5302 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
5303 | * event coalescing. | |
5304 | */ | |
5305 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 5306 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 5307 | napi_schedule(&tnapi->napi); |
61487480 | 5308 | |
88b06bc2 MC |
5309 | return IRQ_RETVAL(1); |
5310 | } | |
5311 | ||
7d12e780 | 5312 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 5313 | { |
09943a18 MC |
5314 | struct tg3_napi *tnapi = dev_id; |
5315 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5316 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
5317 | unsigned int handled = 1; |
5318 | ||
1da177e4 LT |
5319 | /* In INTx mode, it is possible for the interrupt to arrive at |
5320 | * the CPU before the status block posted prior to the interrupt. | |
5321 | * Reading the PCI State register will confirm whether the | |
5322 | * interrupt is ours and will flush the status block. | |
5323 | */ | |
d18edcb2 MC |
5324 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
5325 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
5326 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5327 | handled = 0; | |
f47c11ee | 5328 | goto out; |
fac9b83e | 5329 | } |
d18edcb2 MC |
5330 | } |
5331 | ||
5332 | /* | |
5333 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5334 | * chip-internal interrupt pending events. | |
5335 | * Writing non-zero to intr-mbox-0 additional tells the | |
5336 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5337 | * event coalescing. | |
c04cb347 MC |
5338 | * |
5339 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5340 | * spurious interrupts. The flush impacts performance but | |
5341 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5342 | */ |
c04cb347 | 5343 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
5344 | if (tg3_irq_sync(tp)) |
5345 | goto out; | |
5346 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 5347 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 5348 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 5349 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
5350 | } else { |
5351 | /* No work, shared interrupt perhaps? re-enable | |
5352 | * interrupts, and flush that PCI write | |
5353 | */ | |
5354 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5355 | 0x00000000); | |
fac9b83e | 5356 | } |
f47c11ee | 5357 | out: |
fac9b83e DM |
5358 | return IRQ_RETVAL(handled); |
5359 | } | |
5360 | ||
7d12e780 | 5361 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 5362 | { |
09943a18 MC |
5363 | struct tg3_napi *tnapi = dev_id; |
5364 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5365 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
5366 | unsigned int handled = 1; |
5367 | ||
fac9b83e DM |
5368 | /* In INTx mode, it is possible for the interrupt to arrive at |
5369 | * the CPU before the status block posted prior to the interrupt. | |
5370 | * Reading the PCI State register will confirm whether the | |
5371 | * interrupt is ours and will flush the status block. | |
5372 | */ | |
898a56f8 | 5373 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
d18edcb2 MC |
5374 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || |
5375 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5376 | handled = 0; | |
f47c11ee | 5377 | goto out; |
1da177e4 | 5378 | } |
d18edcb2 MC |
5379 | } |
5380 | ||
5381 | /* | |
5382 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5383 | * chip-internal interrupt pending events. | |
5384 | * writing non-zero to intr-mbox-0 additional tells the | |
5385 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5386 | * event coalescing. | |
c04cb347 MC |
5387 | * |
5388 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5389 | * spurious interrupts. The flush impacts performance but | |
5390 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5391 | */ |
c04cb347 | 5392 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
5393 | |
5394 | /* | |
5395 | * In a shared interrupt configuration, sometimes other devices' | |
5396 | * interrupts will scream. We record the current status tag here | |
5397 | * so that the above check can report that the screaming interrupts | |
5398 | * are unhandled. Eventually they will be silenced. | |
5399 | */ | |
898a56f8 | 5400 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 5401 | |
d18edcb2 MC |
5402 | if (tg3_irq_sync(tp)) |
5403 | goto out; | |
624f8e50 | 5404 | |
72334482 | 5405 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 5406 | |
09943a18 | 5407 | napi_schedule(&tnapi->napi); |
624f8e50 | 5408 | |
f47c11ee | 5409 | out: |
1da177e4 LT |
5410 | return IRQ_RETVAL(handled); |
5411 | } | |
5412 | ||
7938109f | 5413 | /* ISR for interrupt test */ |
7d12e780 | 5414 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 5415 | { |
09943a18 MC |
5416 | struct tg3_napi *tnapi = dev_id; |
5417 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5418 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 5419 | |
f9804ddb MC |
5420 | if ((sblk->status & SD_STATUS_UPDATED) || |
5421 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 5422 | tg3_disable_ints(tp); |
7938109f MC |
5423 | return IRQ_RETVAL(1); |
5424 | } | |
5425 | return IRQ_RETVAL(0); | |
5426 | } | |
5427 | ||
8e7a22e3 | 5428 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 5429 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 5430 | |
b9ec6c1b MC |
5431 | /* Restart hardware after configuration changes, self-test, etc. |
5432 | * Invoked with tp->lock held. | |
5433 | */ | |
5434 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
5435 | __releases(tp->lock) |
5436 | __acquires(tp->lock) | |
b9ec6c1b MC |
5437 | { |
5438 | int err; | |
5439 | ||
5440 | err = tg3_init_hw(tp, reset_phy); | |
5441 | if (err) { | |
5129c3a3 MC |
5442 | netdev_err(tp->dev, |
5443 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
5444 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
5445 | tg3_full_unlock(tp); | |
5446 | del_timer_sync(&tp->timer); | |
5447 | tp->irq_sync = 0; | |
fed97810 | 5448 | tg3_napi_enable(tp); |
b9ec6c1b MC |
5449 | dev_close(tp->dev); |
5450 | tg3_full_lock(tp, 0); | |
5451 | } | |
5452 | return err; | |
5453 | } | |
5454 | ||
1da177e4 LT |
5455 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5456 | static void tg3_poll_controller(struct net_device *dev) | |
5457 | { | |
4f125f42 | 5458 | int i; |
88b06bc2 MC |
5459 | struct tg3 *tp = netdev_priv(dev); |
5460 | ||
4f125f42 | 5461 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 5462 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
5463 | } |
5464 | #endif | |
5465 | ||
c4028958 | 5466 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 5467 | { |
c4028958 | 5468 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 5469 | int err; |
1da177e4 LT |
5470 | unsigned int restart_timer; |
5471 | ||
7faa006f | 5472 | tg3_full_lock(tp, 0); |
7faa006f MC |
5473 | |
5474 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
5475 | tg3_full_unlock(tp); |
5476 | return; | |
5477 | } | |
5478 | ||
5479 | tg3_full_unlock(tp); | |
5480 | ||
b02fd9e3 MC |
5481 | tg3_phy_stop(tp); |
5482 | ||
1da177e4 LT |
5483 | tg3_netif_stop(tp); |
5484 | ||
f47c11ee | 5485 | tg3_full_lock(tp, 1); |
1da177e4 LT |
5486 | |
5487 | restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; | |
5488 | tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; | |
5489 | ||
df3e6548 MC |
5490 | if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { |
5491 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
5492 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
5493 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
5494 | tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; | |
5495 | } | |
5496 | ||
944d980e | 5497 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
5498 | err = tg3_init_hw(tp, 1); |
5499 | if (err) | |
b9ec6c1b | 5500 | goto out; |
1da177e4 LT |
5501 | |
5502 | tg3_netif_start(tp); | |
5503 | ||
1da177e4 LT |
5504 | if (restart_timer) |
5505 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 5506 | |
b9ec6c1b | 5507 | out: |
7faa006f | 5508 | tg3_full_unlock(tp); |
b02fd9e3 MC |
5509 | |
5510 | if (!err) | |
5511 | tg3_phy_start(tp); | |
1da177e4 LT |
5512 | } |
5513 | ||
b0408751 MC |
5514 | static void tg3_dump_short_state(struct tg3 *tp) |
5515 | { | |
05dbe005 JP |
5516 | netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n", |
5517 | tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS)); | |
5518 | netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n", | |
5519 | tr32(RDMAC_STATUS), tr32(WDMAC_STATUS)); | |
b0408751 MC |
5520 | } |
5521 | ||
1da177e4 LT |
5522 | static void tg3_tx_timeout(struct net_device *dev) |
5523 | { | |
5524 | struct tg3 *tp = netdev_priv(dev); | |
5525 | ||
b0408751 | 5526 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 5527 | netdev_err(dev, "transmit timed out, resetting\n"); |
b0408751 MC |
5528 | tg3_dump_short_state(tp); |
5529 | } | |
1da177e4 LT |
5530 | |
5531 | schedule_work(&tp->reset_task); | |
5532 | } | |
5533 | ||
c58ec932 MC |
5534 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5535 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5536 | { | |
5537 | u32 base = (u32) mapping & 0xffffffff; | |
5538 | ||
807540ba | 5539 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
c58ec932 MC |
5540 | } |
5541 | ||
72f2afb8 MC |
5542 | /* Test for DMA addresses > 40-bit */ |
5543 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5544 | int len) | |
5545 | { | |
5546 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
6728a8e2 | 5547 | if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) |
807540ba | 5548 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
72f2afb8 MC |
5549 | return 0; |
5550 | #else | |
5551 | return 0; | |
5552 | #endif | |
5553 | } | |
5554 | ||
f3f3f27e | 5555 | static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32); |
1da177e4 | 5556 | |
72f2afb8 | 5557 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 MC |
5558 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
5559 | struct sk_buff *skb, u32 last_plus_one, | |
5560 | u32 *start, u32 base_flags, u32 mss) | |
1da177e4 | 5561 | { |
24f4efd4 | 5562 | struct tg3 *tp = tnapi->tp; |
41588ba1 | 5563 | struct sk_buff *new_skb; |
c58ec932 | 5564 | dma_addr_t new_addr = 0; |
1da177e4 | 5565 | u32 entry = *start; |
c58ec932 | 5566 | int i, ret = 0; |
1da177e4 | 5567 | |
41588ba1 MC |
5568 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
5569 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5570 | else { | |
5571 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5572 | ||
5573 | new_skb = skb_copy_expand(skb, | |
5574 | skb_headroom(skb) + more_headroom, | |
5575 | skb_tailroom(skb), GFP_ATOMIC); | |
5576 | } | |
5577 | ||
1da177e4 | 5578 | if (!new_skb) { |
c58ec932 MC |
5579 | ret = -1; |
5580 | } else { | |
5581 | /* New SKB is guaranteed to be linear. */ | |
5582 | entry = *start; | |
f4188d8a AD |
5583 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
5584 | PCI_DMA_TODEVICE); | |
5585 | /* Make sure the mapping succeeded */ | |
5586 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
5587 | ret = -1; | |
5588 | dev_kfree_skb(new_skb); | |
5589 | new_skb = NULL; | |
90079ce8 | 5590 | |
c58ec932 MC |
5591 | /* Make sure new skb does not cross any 4G boundaries. |
5592 | * Drop the packet if it does. | |
5593 | */ | |
f4188d8a AD |
5594 | } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5595 | tg3_4g_overflow_test(new_addr, new_skb->len)) { | |
5596 | pci_unmap_single(tp->pdev, new_addr, new_skb->len, | |
5597 | PCI_DMA_TODEVICE); | |
c58ec932 MC |
5598 | ret = -1; |
5599 | dev_kfree_skb(new_skb); | |
5600 | new_skb = NULL; | |
5601 | } else { | |
f3f3f27e | 5602 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, |
c58ec932 MC |
5603 | base_flags, 1 | (mss << 1)); |
5604 | *start = NEXT_TX(entry); | |
5605 | } | |
1da177e4 LT |
5606 | } |
5607 | ||
1da177e4 LT |
5608 | /* Now clean up the sw ring entries. */ |
5609 | i = 0; | |
5610 | while (entry != last_plus_one) { | |
f4188d8a AD |
5611 | int len; |
5612 | ||
f3f3f27e | 5613 | if (i == 0) |
f4188d8a | 5614 | len = skb_headlen(skb); |
f3f3f27e | 5615 | else |
f4188d8a AD |
5616 | len = skb_shinfo(skb)->frags[i-1].size; |
5617 | ||
5618 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 5619 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
5620 | mapping), |
5621 | len, PCI_DMA_TODEVICE); | |
5622 | if (i == 0) { | |
5623 | tnapi->tx_buffers[entry].skb = new_skb; | |
4e5e4f0d | 5624 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
5625 | new_addr); |
5626 | } else { | |
f3f3f27e | 5627 | tnapi->tx_buffers[entry].skb = NULL; |
f4188d8a | 5628 | } |
1da177e4 LT |
5629 | entry = NEXT_TX(entry); |
5630 | i++; | |
5631 | } | |
5632 | ||
5633 | dev_kfree_skb(skb); | |
5634 | ||
c58ec932 | 5635 | return ret; |
1da177e4 LT |
5636 | } |
5637 | ||
f3f3f27e | 5638 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, |
1da177e4 LT |
5639 | dma_addr_t mapping, int len, u32 flags, |
5640 | u32 mss_and_is_end) | |
5641 | { | |
f3f3f27e | 5642 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; |
1da177e4 LT |
5643 | int is_end = (mss_and_is_end & 0x1); |
5644 | u32 mss = (mss_and_is_end >> 1); | |
5645 | u32 vlan_tag = 0; | |
5646 | ||
5647 | if (is_end) | |
5648 | flags |= TXD_FLAG_END; | |
5649 | if (flags & TXD_FLAG_VLAN) { | |
5650 | vlan_tag = flags >> 16; | |
5651 | flags &= 0xffff; | |
5652 | } | |
5653 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5654 | ||
5655 | txd->addr_hi = ((u64) mapping >> 32); | |
5656 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5657 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5658 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5659 | } | |
5660 | ||
5a6f3074 | 5661 | /* hard_start_xmit for devices that don't have any bugs and |
e849cdc3 | 5662 | * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only. |
5a6f3074 | 5663 | */ |
61357325 SH |
5664 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, |
5665 | struct net_device *dev) | |
5a6f3074 MC |
5666 | { |
5667 | struct tg3 *tp = netdev_priv(dev); | |
5a6f3074 | 5668 | u32 len, entry, base_flags, mss; |
90079ce8 | 5669 | dma_addr_t mapping; |
fe5f5787 MC |
5670 | struct tg3_napi *tnapi; |
5671 | struct netdev_queue *txq; | |
f4188d8a AD |
5672 | unsigned int i, last; |
5673 | ||
fe5f5787 MC |
5674 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5675 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 5676 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 | 5677 | tnapi++; |
5a6f3074 | 5678 | |
00b70504 | 5679 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5680 | * and TX reclaim runs via tp->napi.poll inside of a software |
5a6f3074 MC |
5681 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5682 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5683 | */ | |
f3f3f27e | 5684 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
fe5f5787 MC |
5685 | if (!netif_tx_queue_stopped(txq)) { |
5686 | netif_tx_stop_queue(txq); | |
5a6f3074 MC |
5687 | |
5688 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
5689 | netdev_err(dev, |
5690 | "BUG! Tx Ring full when queue awake!\n"); | |
5a6f3074 | 5691 | } |
5a6f3074 MC |
5692 | return NETDEV_TX_BUSY; |
5693 | } | |
5694 | ||
f3f3f27e | 5695 | entry = tnapi->tx_prod; |
5a6f3074 | 5696 | base_flags = 0; |
be98da6a MC |
5697 | mss = skb_shinfo(skb)->gso_size; |
5698 | if (mss) { | |
5a6f3074 | 5699 | int tcp_opt_len, ip_tcp_len; |
f6eb9b1f | 5700 | u32 hdrlen; |
5a6f3074 MC |
5701 | |
5702 | if (skb_header_cloned(skb) && | |
5703 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5704 | dev_kfree_skb(skb); | |
5705 | goto out_unlock; | |
5706 | } | |
5707 | ||
02e96080 | 5708 | if (skb_is_gso_v6(skb)) { |
f6eb9b1f | 5709 | hdrlen = skb_headlen(skb) - ETH_HLEN; |
02e96080 | 5710 | } else { |
eddc9ec5 ACM |
5711 | struct iphdr *iph = ip_hdr(skb); |
5712 | ||
ab6a5bb6 | 5713 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5714 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
b0026624 | 5715 | |
eddc9ec5 ACM |
5716 | iph->check = 0; |
5717 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
f6eb9b1f | 5718 | hdrlen = ip_tcp_len + tcp_opt_len; |
b0026624 | 5719 | } |
5a6f3074 | 5720 | |
e849cdc3 | 5721 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
f6eb9b1f MC |
5722 | mss |= (hdrlen & 0xc) << 12; |
5723 | if (hdrlen & 0x10) | |
5724 | base_flags |= 0x00000010; | |
5725 | base_flags |= (hdrlen & 0x3e0) << 5; | |
5726 | } else | |
5727 | mss |= hdrlen << 9; | |
5728 | ||
5a6f3074 MC |
5729 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5730 | TXD_FLAG_CPU_POST_DMA); | |
5731 | ||
aa8223c7 | 5732 | tcp_hdr(skb)->check = 0; |
5a6f3074 | 5733 | |
859a5887 | 5734 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
5a6f3074 | 5735 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
859a5887 MC |
5736 | } |
5737 | ||
eab6d18d | 5738 | if (vlan_tx_tag_present(skb)) |
5a6f3074 MC |
5739 | base_flags |= (TXD_FLAG_VLAN | |
5740 | (vlan_tx_tag_get(skb) << 16)); | |
5a6f3074 | 5741 | |
f4188d8a AD |
5742 | len = skb_headlen(skb); |
5743 | ||
5744 | /* Queue skb data, a.k.a. the main skb fragment. */ | |
5745 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5746 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
5747 | dev_kfree_skb(skb); |
5748 | goto out_unlock; | |
5749 | } | |
5750 | ||
f3f3f27e | 5751 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 5752 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
fe5f5787 | 5753 | |
b703df6f | 5754 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
8fc2f995 | 5755 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
f6eb9b1f MC |
5756 | base_flags |= TXD_FLAG_JMB_PKT; |
5757 | ||
f3f3f27e | 5758 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
5a6f3074 MC |
5759 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5760 | ||
5761 | entry = NEXT_TX(entry); | |
5762 | ||
5763 | /* Now loop through additional data fragments, and queue them. */ | |
5764 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5a6f3074 MC |
5765 | last = skb_shinfo(skb)->nr_frags - 1; |
5766 | for (i = 0; i <= last; i++) { | |
5767 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5768 | ||
5769 | len = frag->size; | |
f4188d8a AD |
5770 | mapping = pci_map_page(tp->pdev, |
5771 | frag->page, | |
5772 | frag->page_offset, | |
5773 | len, PCI_DMA_TODEVICE); | |
5774 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
5775 | goto dma_error; | |
5776 | ||
f3f3f27e | 5777 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 5778 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a | 5779 | mapping); |
5a6f3074 | 5780 | |
f3f3f27e | 5781 | tg3_set_txd(tnapi, entry, mapping, len, |
5a6f3074 MC |
5782 | base_flags, (i == last) | (mss << 1)); |
5783 | ||
5784 | entry = NEXT_TX(entry); | |
5785 | } | |
5786 | } | |
5787 | ||
5788 | /* Packets are ready, update Tx producer idx local and on card. */ | |
f3f3f27e | 5789 | tw32_tx_mbox(tnapi->prodmbox, entry); |
5a6f3074 | 5790 | |
f3f3f27e MC |
5791 | tnapi->tx_prod = entry; |
5792 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
fe5f5787 | 5793 | netif_tx_stop_queue(txq); |
f65aac16 MC |
5794 | |
5795 | /* netif_tx_stop_queue() must be done before checking | |
5796 | * checking tx index in tg3_tx_avail() below, because in | |
5797 | * tg3_tx(), we update tx index before checking for | |
5798 | * netif_tx_queue_stopped(). | |
5799 | */ | |
5800 | smp_mb(); | |
f3f3f27e | 5801 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
fe5f5787 | 5802 | netif_tx_wake_queue(txq); |
5a6f3074 MC |
5803 | } |
5804 | ||
5805 | out_unlock: | |
cdd0db05 | 5806 | mmiowb(); |
5a6f3074 MC |
5807 | |
5808 | return NETDEV_TX_OK; | |
f4188d8a AD |
5809 | |
5810 | dma_error: | |
5811 | last = i; | |
5812 | entry = tnapi->tx_prod; | |
5813 | tnapi->tx_buffers[entry].skb = NULL; | |
5814 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 5815 | dma_unmap_addr(&tnapi->tx_buffers[entry], mapping), |
f4188d8a AD |
5816 | skb_headlen(skb), |
5817 | PCI_DMA_TODEVICE); | |
5818 | for (i = 0; i <= last; i++) { | |
5819 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5820 | entry = NEXT_TX(entry); | |
5821 | ||
5822 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 5823 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
5824 | mapping), |
5825 | frag->size, PCI_DMA_TODEVICE); | |
5826 | } | |
5827 | ||
5828 | dev_kfree_skb(skb); | |
5829 | return NETDEV_TX_OK; | |
5a6f3074 MC |
5830 | } |
5831 | ||
61357325 SH |
5832 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *, |
5833 | struct net_device *); | |
52c0fd83 MC |
5834 | |
5835 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5836 | * TSO header is greater than 80 bytes. | |
5837 | */ | |
5838 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5839 | { | |
5840 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 5841 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
5842 | |
5843 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 5844 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 5845 | netif_stop_queue(tp->dev); |
f65aac16 MC |
5846 | |
5847 | /* netif_tx_stop_queue() must be done before checking | |
5848 | * checking tx index in tg3_tx_avail() below, because in | |
5849 | * tg3_tx(), we update tx index before checking for | |
5850 | * netif_tx_queue_stopped(). | |
5851 | */ | |
5852 | smp_mb(); | |
f3f3f27e | 5853 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
5854 | return NETDEV_TX_BUSY; |
5855 | ||
5856 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
5857 | } |
5858 | ||
5859 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 5860 | if (IS_ERR(segs)) |
52c0fd83 MC |
5861 | goto tg3_tso_bug_end; |
5862 | ||
5863 | do { | |
5864 | nskb = segs; | |
5865 | segs = segs->next; | |
5866 | nskb->next = NULL; | |
5867 | tg3_start_xmit_dma_bug(nskb, tp->dev); | |
5868 | } while (segs); | |
5869 | ||
5870 | tg3_tso_bug_end: | |
5871 | dev_kfree_skb(skb); | |
5872 | ||
5873 | return NETDEV_TX_OK; | |
5874 | } | |
52c0fd83 | 5875 | |
5a6f3074 MC |
5876 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
5877 | * support TG3_FLG2_HW_TSO_1 or firmware TSO only. | |
5878 | */ | |
61357325 SH |
5879 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb, |
5880 | struct net_device *dev) | |
1da177e4 LT |
5881 | { |
5882 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 LT |
5883 | u32 len, entry, base_flags, mss; |
5884 | int would_hit_hwbug; | |
90079ce8 | 5885 | dma_addr_t mapping; |
24f4efd4 MC |
5886 | struct tg3_napi *tnapi; |
5887 | struct netdev_queue *txq; | |
f4188d8a AD |
5888 | unsigned int i, last; |
5889 | ||
24f4efd4 MC |
5890 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5891 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 5892 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
24f4efd4 | 5893 | tnapi++; |
1da177e4 | 5894 | |
00b70504 | 5895 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5896 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
5897 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5898 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 5899 | */ |
f3f3f27e | 5900 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
5901 | if (!netif_tx_queue_stopped(txq)) { |
5902 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
5903 | |
5904 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
5905 | netdev_err(dev, |
5906 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 5907 | } |
1da177e4 LT |
5908 | return NETDEV_TX_BUSY; |
5909 | } | |
5910 | ||
f3f3f27e | 5911 | entry = tnapi->tx_prod; |
1da177e4 | 5912 | base_flags = 0; |
84fa7933 | 5913 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 5914 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 5915 | |
be98da6a MC |
5916 | mss = skb_shinfo(skb)->gso_size; |
5917 | if (mss) { | |
eddc9ec5 | 5918 | struct iphdr *iph; |
34195c3d | 5919 | u32 tcp_opt_len, hdr_len; |
1da177e4 LT |
5920 | |
5921 | if (skb_header_cloned(skb) && | |
5922 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5923 | dev_kfree_skb(skb); | |
5924 | goto out_unlock; | |
5925 | } | |
5926 | ||
34195c3d | 5927 | iph = ip_hdr(skb); |
ab6a5bb6 | 5928 | tcp_opt_len = tcp_optlen(skb); |
1da177e4 | 5929 | |
02e96080 | 5930 | if (skb_is_gso_v6(skb)) { |
34195c3d MC |
5931 | hdr_len = skb_headlen(skb) - ETH_HLEN; |
5932 | } else { | |
5933 | u32 ip_tcp_len; | |
5934 | ||
5935 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); | |
5936 | hdr_len = ip_tcp_len + tcp_opt_len; | |
5937 | ||
5938 | iph->check = 0; | |
5939 | iph->tot_len = htons(mss + hdr_len); | |
5940 | } | |
5941 | ||
52c0fd83 | 5942 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
7f62ad5d | 5943 | (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) |
de6f31eb | 5944 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 5945 | |
1da177e4 LT |
5946 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5947 | TXD_FLAG_CPU_POST_DMA); | |
5948 | ||
1da177e4 | 5949 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { |
aa8223c7 | 5950 | tcp_hdr(skb)->check = 0; |
1da177e4 | 5951 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
5952 | } else |
5953 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5954 | iph->daddr, 0, | |
5955 | IPPROTO_TCP, | |
5956 | 0); | |
1da177e4 | 5957 | |
615774fe MC |
5958 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
5959 | mss |= (hdr_len & 0xc) << 12; | |
5960 | if (hdr_len & 0x10) | |
5961 | base_flags |= 0x00000010; | |
5962 | base_flags |= (hdr_len & 0x3e0) << 5; | |
5963 | } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) | |
92c6b8d1 MC |
5964 | mss |= hdr_len << 9; |
5965 | else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) || | |
5966 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
eddc9ec5 | 5967 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5968 | int tsflags; |
5969 | ||
eddc9ec5 | 5970 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5971 | mss |= (tsflags << 11); |
5972 | } | |
5973 | } else { | |
eddc9ec5 | 5974 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5975 | int tsflags; |
5976 | ||
eddc9ec5 | 5977 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5978 | base_flags |= tsflags << 12; |
5979 | } | |
5980 | } | |
5981 | } | |
bf933c80 | 5982 | |
eab6d18d | 5983 | if (vlan_tx_tag_present(skb)) |
1da177e4 LT |
5984 | base_flags |= (TXD_FLAG_VLAN | |
5985 | (vlan_tx_tag_get(skb) << 16)); | |
1da177e4 | 5986 | |
b703df6f | 5987 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
8fc2f995 | 5988 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
615774fe MC |
5989 | base_flags |= TXD_FLAG_JMB_PKT; |
5990 | ||
f4188d8a AD |
5991 | len = skb_headlen(skb); |
5992 | ||
5993 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5994 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
5995 | dev_kfree_skb(skb); |
5996 | goto out_unlock; | |
5997 | } | |
5998 | ||
f3f3f27e | 5999 | tnapi->tx_buffers[entry].skb = skb; |
4e5e4f0d | 6000 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
6001 | |
6002 | would_hit_hwbug = 0; | |
6003 | ||
92c6b8d1 MC |
6004 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8) |
6005 | would_hit_hwbug = 1; | |
6006 | ||
0e1406dd MC |
6007 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
6008 | tg3_4g_overflow_test(mapping, len)) | |
6009 | would_hit_hwbug = 1; | |
6010 | ||
6011 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && | |
6012 | tg3_40bit_overflow_test(tp, mapping, len)) | |
41588ba1 | 6013 | would_hit_hwbug = 1; |
0e1406dd MC |
6014 | |
6015 | if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) | |
c58ec932 | 6016 | would_hit_hwbug = 1; |
1da177e4 | 6017 | |
f3f3f27e | 6018 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
1da177e4 LT |
6019 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
6020 | ||
6021 | entry = NEXT_TX(entry); | |
6022 | ||
6023 | /* Now loop through additional data fragments, and queue them. */ | |
6024 | if (skb_shinfo(skb)->nr_frags > 0) { | |
1da177e4 LT |
6025 | last = skb_shinfo(skb)->nr_frags - 1; |
6026 | for (i = 0; i <= last; i++) { | |
6027 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6028 | ||
6029 | len = frag->size; | |
f4188d8a AD |
6030 | mapping = pci_map_page(tp->pdev, |
6031 | frag->page, | |
6032 | frag->page_offset, | |
6033 | len, PCI_DMA_TODEVICE); | |
1da177e4 | 6034 | |
f3f3f27e | 6035 | tnapi->tx_buffers[entry].skb = NULL; |
4e5e4f0d | 6036 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
f4188d8a AD |
6037 | mapping); |
6038 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
6039 | goto dma_error; | |
1da177e4 | 6040 | |
92c6b8d1 MC |
6041 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && |
6042 | len <= 8) | |
6043 | would_hit_hwbug = 1; | |
6044 | ||
0e1406dd MC |
6045 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
6046 | tg3_4g_overflow_test(mapping, len)) | |
c58ec932 | 6047 | would_hit_hwbug = 1; |
1da177e4 | 6048 | |
0e1406dd MC |
6049 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && |
6050 | tg3_40bit_overflow_test(tp, mapping, len)) | |
72f2afb8 MC |
6051 | would_hit_hwbug = 1; |
6052 | ||
1da177e4 | 6053 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
f3f3f27e | 6054 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6055 | base_flags, (i == last)|(mss << 1)); |
6056 | else | |
f3f3f27e | 6057 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
6058 | base_flags, (i == last)); |
6059 | ||
6060 | entry = NEXT_TX(entry); | |
6061 | } | |
6062 | } | |
6063 | ||
6064 | if (would_hit_hwbug) { | |
6065 | u32 last_plus_one = entry; | |
6066 | u32 start; | |
1da177e4 | 6067 | |
c58ec932 MC |
6068 | start = entry - 1 - skb_shinfo(skb)->nr_frags; |
6069 | start &= (TG3_TX_RING_SIZE - 1); | |
1da177e4 LT |
6070 | |
6071 | /* If the workaround fails due to memory/mapping | |
6072 | * failure, silently drop this packet. | |
6073 | */ | |
24f4efd4 | 6074 | if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one, |
c58ec932 | 6075 | &start, base_flags, mss)) |
1da177e4 LT |
6076 | goto out_unlock; |
6077 | ||
6078 | entry = start; | |
6079 | } | |
6080 | ||
6081 | /* Packets are ready, update Tx producer idx local and on card. */ | |
24f4efd4 | 6082 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 6083 | |
f3f3f27e MC |
6084 | tnapi->tx_prod = entry; |
6085 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 6086 | netif_tx_stop_queue(txq); |
f65aac16 MC |
6087 | |
6088 | /* netif_tx_stop_queue() must be done before checking | |
6089 | * checking tx index in tg3_tx_avail() below, because in | |
6090 | * tg3_tx(), we update tx index before checking for | |
6091 | * netif_tx_queue_stopped(). | |
6092 | */ | |
6093 | smp_mb(); | |
f3f3f27e | 6094 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 6095 | netif_tx_wake_queue(txq); |
51b91468 | 6096 | } |
1da177e4 LT |
6097 | |
6098 | out_unlock: | |
cdd0db05 | 6099 | mmiowb(); |
1da177e4 LT |
6100 | |
6101 | return NETDEV_TX_OK; | |
f4188d8a AD |
6102 | |
6103 | dma_error: | |
6104 | last = i; | |
6105 | entry = tnapi->tx_prod; | |
6106 | tnapi->tx_buffers[entry].skb = NULL; | |
6107 | pci_unmap_single(tp->pdev, | |
4e5e4f0d | 6108 | dma_unmap_addr(&tnapi->tx_buffers[entry], mapping), |
f4188d8a AD |
6109 | skb_headlen(skb), |
6110 | PCI_DMA_TODEVICE); | |
6111 | for (i = 0; i <= last; i++) { | |
6112 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6113 | entry = NEXT_TX(entry); | |
6114 | ||
6115 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6116 | dma_unmap_addr(&tnapi->tx_buffers[entry], |
f4188d8a AD |
6117 | mapping), |
6118 | frag->size, PCI_DMA_TODEVICE); | |
6119 | } | |
6120 | ||
6121 | dev_kfree_skb(skb); | |
6122 | return NETDEV_TX_OK; | |
1da177e4 LT |
6123 | } |
6124 | ||
6125 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, | |
6126 | int new_mtu) | |
6127 | { | |
6128 | dev->mtu = new_mtu; | |
6129 | ||
ef7f5ec0 | 6130 | if (new_mtu > ETH_DATA_LEN) { |
a4e2b347 | 6131 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { |
ef7f5ec0 MC |
6132 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
6133 | ethtool_op_set_tso(dev, 0); | |
859a5887 | 6134 | } else { |
ef7f5ec0 | 6135 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
859a5887 | 6136 | } |
ef7f5ec0 | 6137 | } else { |
a4e2b347 | 6138 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) |
ef7f5ec0 | 6139 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
0f893dc6 | 6140 | tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; |
ef7f5ec0 | 6141 | } |
1da177e4 LT |
6142 | } |
6143 | ||
6144 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
6145 | { | |
6146 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 6147 | int err; |
1da177e4 LT |
6148 | |
6149 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
6150 | return -EINVAL; | |
6151 | ||
6152 | if (!netif_running(dev)) { | |
6153 | /* We'll just catch it later when the | |
6154 | * device is up'd. | |
6155 | */ | |
6156 | tg3_set_mtu(dev, tp, new_mtu); | |
6157 | return 0; | |
6158 | } | |
6159 | ||
b02fd9e3 MC |
6160 | tg3_phy_stop(tp); |
6161 | ||
1da177e4 | 6162 | tg3_netif_stop(tp); |
f47c11ee DM |
6163 | |
6164 | tg3_full_lock(tp, 1); | |
1da177e4 | 6165 | |
944d980e | 6166 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
6167 | |
6168 | tg3_set_mtu(dev, tp, new_mtu); | |
6169 | ||
b9ec6c1b | 6170 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 6171 | |
b9ec6c1b MC |
6172 | if (!err) |
6173 | tg3_netif_start(tp); | |
1da177e4 | 6174 | |
f47c11ee | 6175 | tg3_full_unlock(tp); |
1da177e4 | 6176 | |
b02fd9e3 MC |
6177 | if (!err) |
6178 | tg3_phy_start(tp); | |
6179 | ||
b9ec6c1b | 6180 | return err; |
1da177e4 LT |
6181 | } |
6182 | ||
21f581a5 MC |
6183 | static void tg3_rx_prodring_free(struct tg3 *tp, |
6184 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6185 | { |
1da177e4 LT |
6186 | int i; |
6187 | ||
8fea32b9 | 6188 | if (tpr != &tp->napi[0].prodring) { |
b196c7e4 | 6189 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
2c49a44d | 6190 | i = (i + 1) & tp->rx_std_ring_mask) |
b196c7e4 MC |
6191 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6192 | tp->rx_pkt_map_sz); | |
6193 | ||
6194 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
6195 | for (i = tpr->rx_jmb_cons_idx; | |
6196 | i != tpr->rx_jmb_prod_idx; | |
2c49a44d | 6197 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
b196c7e4 MC |
6198 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6199 | TG3_RX_JMB_MAP_SZ); | |
6200 | } | |
6201 | } | |
6202 | ||
2b2cdb65 | 6203 | return; |
b196c7e4 | 6204 | } |
1da177e4 | 6205 | |
2c49a44d | 6206 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
2b2cdb65 MC |
6207 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], |
6208 | tp->rx_pkt_map_sz); | |
1da177e4 | 6209 | |
48035728 MC |
6210 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
6211 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
2c49a44d | 6212 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
2b2cdb65 MC |
6213 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], |
6214 | TG3_RX_JMB_MAP_SZ); | |
1da177e4 LT |
6215 | } |
6216 | } | |
6217 | ||
c6cdf436 | 6218 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
6219 | * |
6220 | * The chip has been shut down and the driver detached from | |
6221 | * the networking, so no interrupts or new tx packets will | |
6222 | * end up in the driver. tp->{tx,}lock are held and thus | |
6223 | * we may not sleep. | |
6224 | */ | |
21f581a5 MC |
6225 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
6226 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6227 | { |
287be12e | 6228 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 6229 | |
b196c7e4 MC |
6230 | tpr->rx_std_cons_idx = 0; |
6231 | tpr->rx_std_prod_idx = 0; | |
6232 | tpr->rx_jmb_cons_idx = 0; | |
6233 | tpr->rx_jmb_prod_idx = 0; | |
6234 | ||
8fea32b9 | 6235 | if (tpr != &tp->napi[0].prodring) { |
2c49a44d MC |
6236 | memset(&tpr->rx_std_buffers[0], 0, |
6237 | TG3_RX_STD_BUFF_RING_SIZE(tp)); | |
48035728 | 6238 | if (tpr->rx_jmb_buffers) |
2b2cdb65 | 6239 | memset(&tpr->rx_jmb_buffers[0], 0, |
2c49a44d | 6240 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
2b2cdb65 MC |
6241 | goto done; |
6242 | } | |
6243 | ||
1da177e4 | 6244 | /* Zero out all descriptors. */ |
2c49a44d | 6245 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
1da177e4 | 6246 | |
287be12e | 6247 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
a4e2b347 | 6248 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && |
287be12e MC |
6249 | tp->dev->mtu > ETH_DATA_LEN) |
6250 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6251 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 6252 | |
1da177e4 LT |
6253 | /* Initialize invariants of the rings, we only set this |
6254 | * stuff once. This works because the card does not | |
6255 | * write into the rx buffer posting rings. | |
6256 | */ | |
2c49a44d | 6257 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
1da177e4 LT |
6258 | struct tg3_rx_buffer_desc *rxd; |
6259 | ||
21f581a5 | 6260 | rxd = &tpr->rx_std[i]; |
287be12e | 6261 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
6262 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
6263 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6264 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6265 | } | |
6266 | ||
1da177e4 LT |
6267 | /* Now allocate fresh SKBs for each rx ring. */ |
6268 | for (i = 0; i < tp->rx_pending; i++) { | |
86b21e59 | 6269 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
6270 | netdev_warn(tp->dev, |
6271 | "Using a smaller RX standard ring. Only " | |
6272 | "%d out of %d buffers were allocated " | |
6273 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 6274 | if (i == 0) |
cf7a7298 | 6275 | goto initfail; |
32d8c572 | 6276 | tp->rx_pending = i; |
1da177e4 | 6277 | break; |
32d8c572 | 6278 | } |
1da177e4 LT |
6279 | } |
6280 | ||
48035728 MC |
6281 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) || |
6282 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
cf7a7298 MC |
6283 | goto done; |
6284 | ||
2c49a44d | 6285 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
cf7a7298 | 6286 | |
0d86df80 MC |
6287 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)) |
6288 | goto done; | |
cf7a7298 | 6289 | |
2c49a44d | 6290 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
0d86df80 MC |
6291 | struct tg3_rx_buffer_desc *rxd; |
6292 | ||
6293 | rxd = &tpr->rx_jmb[i].std; | |
6294 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6295 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6296 | RXD_FLAG_JUMBO; | |
6297 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6298 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6299 | } | |
6300 | ||
6301 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6302 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
5129c3a3 MC |
6303 | netdev_warn(tp->dev, |
6304 | "Using a smaller RX jumbo ring. Only %d " | |
6305 | "out of %d buffers were allocated " | |
6306 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
6307 | if (i == 0) |
6308 | goto initfail; | |
6309 | tp->rx_jumbo_pending = i; | |
6310 | break; | |
1da177e4 LT |
6311 | } |
6312 | } | |
cf7a7298 MC |
6313 | |
6314 | done: | |
32d8c572 | 6315 | return 0; |
cf7a7298 MC |
6316 | |
6317 | initfail: | |
21f581a5 | 6318 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 6319 | return -ENOMEM; |
1da177e4 LT |
6320 | } |
6321 | ||
21f581a5 MC |
6322 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
6323 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6324 | { |
21f581a5 MC |
6325 | kfree(tpr->rx_std_buffers); |
6326 | tpr->rx_std_buffers = NULL; | |
6327 | kfree(tpr->rx_jmb_buffers); | |
6328 | tpr->rx_jmb_buffers = NULL; | |
6329 | if (tpr->rx_std) { | |
4bae65c8 MC |
6330 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
6331 | tpr->rx_std, tpr->rx_std_mapping); | |
21f581a5 | 6332 | tpr->rx_std = NULL; |
1da177e4 | 6333 | } |
21f581a5 | 6334 | if (tpr->rx_jmb) { |
4bae65c8 MC |
6335 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
6336 | tpr->rx_jmb, tpr->rx_jmb_mapping); | |
21f581a5 | 6337 | tpr->rx_jmb = NULL; |
1da177e4 | 6338 | } |
cf7a7298 MC |
6339 | } |
6340 | ||
21f581a5 MC |
6341 | static int tg3_rx_prodring_init(struct tg3 *tp, |
6342 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 6343 | { |
2c49a44d MC |
6344 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
6345 | GFP_KERNEL); | |
21f581a5 | 6346 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
6347 | return -ENOMEM; |
6348 | ||
4bae65c8 MC |
6349 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
6350 | TG3_RX_STD_RING_BYTES(tp), | |
6351 | &tpr->rx_std_mapping, | |
6352 | GFP_KERNEL); | |
21f581a5 | 6353 | if (!tpr->rx_std) |
cf7a7298 MC |
6354 | goto err_out; |
6355 | ||
48035728 MC |
6356 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
6357 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
2c49a44d | 6358 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
21f581a5 MC |
6359 | GFP_KERNEL); |
6360 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
6361 | goto err_out; |
6362 | ||
4bae65c8 MC |
6363 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
6364 | TG3_RX_JMB_RING_BYTES(tp), | |
6365 | &tpr->rx_jmb_mapping, | |
6366 | GFP_KERNEL); | |
21f581a5 | 6367 | if (!tpr->rx_jmb) |
cf7a7298 MC |
6368 | goto err_out; |
6369 | } | |
6370 | ||
6371 | return 0; | |
6372 | ||
6373 | err_out: | |
21f581a5 | 6374 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
6375 | return -ENOMEM; |
6376 | } | |
6377 | ||
6378 | /* Free up pending packets in all rx/tx rings. | |
6379 | * | |
6380 | * The chip has been shut down and the driver detached from | |
6381 | * the networking, so no interrupts or new tx packets will | |
6382 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6383 | * in an interrupt context and thus may sleep. | |
6384 | */ | |
6385 | static void tg3_free_rings(struct tg3 *tp) | |
6386 | { | |
f77a6a8e | 6387 | int i, j; |
cf7a7298 | 6388 | |
f77a6a8e MC |
6389 | for (j = 0; j < tp->irq_cnt; j++) { |
6390 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 6391 | |
8fea32b9 | 6392 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
b28f6428 | 6393 | |
0c1d0e2b MC |
6394 | if (!tnapi->tx_buffers) |
6395 | continue; | |
6396 | ||
f77a6a8e | 6397 | for (i = 0; i < TG3_TX_RING_SIZE; ) { |
f4188d8a | 6398 | struct ring_info *txp; |
f77a6a8e | 6399 | struct sk_buff *skb; |
f4188d8a | 6400 | unsigned int k; |
cf7a7298 | 6401 | |
f77a6a8e MC |
6402 | txp = &tnapi->tx_buffers[i]; |
6403 | skb = txp->skb; | |
cf7a7298 | 6404 | |
f77a6a8e MC |
6405 | if (skb == NULL) { |
6406 | i++; | |
6407 | continue; | |
6408 | } | |
cf7a7298 | 6409 | |
f4188d8a | 6410 | pci_unmap_single(tp->pdev, |
4e5e4f0d | 6411 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6412 | skb_headlen(skb), |
6413 | PCI_DMA_TODEVICE); | |
f77a6a8e | 6414 | txp->skb = NULL; |
cf7a7298 | 6415 | |
f4188d8a AD |
6416 | i++; |
6417 | ||
6418 | for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { | |
6419 | txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; | |
6420 | pci_unmap_page(tp->pdev, | |
4e5e4f0d | 6421 | dma_unmap_addr(txp, mapping), |
f4188d8a AD |
6422 | skb_shinfo(skb)->frags[k].size, |
6423 | PCI_DMA_TODEVICE); | |
6424 | i++; | |
6425 | } | |
f77a6a8e MC |
6426 | |
6427 | dev_kfree_skb_any(skb); | |
6428 | } | |
2b2cdb65 | 6429 | } |
cf7a7298 MC |
6430 | } |
6431 | ||
6432 | /* Initialize tx/rx rings for packet processing. | |
6433 | * | |
6434 | * The chip has been shut down and the driver detached from | |
6435 | * the networking, so no interrupts or new tx packets will | |
6436 | * end up in the driver. tp->{tx,}lock are held and thus | |
6437 | * we may not sleep. | |
6438 | */ | |
6439 | static int tg3_init_rings(struct tg3 *tp) | |
6440 | { | |
f77a6a8e | 6441 | int i; |
72334482 | 6442 | |
cf7a7298 MC |
6443 | /* Free up all the SKBs. */ |
6444 | tg3_free_rings(tp); | |
6445 | ||
f77a6a8e MC |
6446 | for (i = 0; i < tp->irq_cnt; i++) { |
6447 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6448 | ||
6449 | tnapi->last_tag = 0; | |
6450 | tnapi->last_irq_tag = 0; | |
6451 | tnapi->hw_status->status = 0; | |
6452 | tnapi->hw_status->status_tag = 0; | |
6453 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 6454 | |
f77a6a8e MC |
6455 | tnapi->tx_prod = 0; |
6456 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
6457 | if (tnapi->tx_ring) |
6458 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
6459 | |
6460 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
6461 | if (tnapi->rx_rcb) |
6462 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 6463 | |
8fea32b9 | 6464 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
e4af1af9 | 6465 | tg3_free_rings(tp); |
2b2cdb65 | 6466 | return -ENOMEM; |
e4af1af9 | 6467 | } |
f77a6a8e | 6468 | } |
72334482 | 6469 | |
2b2cdb65 | 6470 | return 0; |
cf7a7298 MC |
6471 | } |
6472 | ||
6473 | /* | |
6474 | * Must not be invoked with interrupt sources disabled and | |
6475 | * the hardware shutdown down. | |
6476 | */ | |
6477 | static void tg3_free_consistent(struct tg3 *tp) | |
6478 | { | |
f77a6a8e | 6479 | int i; |
898a56f8 | 6480 | |
f77a6a8e MC |
6481 | for (i = 0; i < tp->irq_cnt; i++) { |
6482 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6483 | ||
6484 | if (tnapi->tx_ring) { | |
4bae65c8 | 6485 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
f77a6a8e MC |
6486 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
6487 | tnapi->tx_ring = NULL; | |
6488 | } | |
6489 | ||
6490 | kfree(tnapi->tx_buffers); | |
6491 | tnapi->tx_buffers = NULL; | |
6492 | ||
6493 | if (tnapi->rx_rcb) { | |
4bae65c8 MC |
6494 | dma_free_coherent(&tp->pdev->dev, |
6495 | TG3_RX_RCB_RING_BYTES(tp), | |
6496 | tnapi->rx_rcb, | |
6497 | tnapi->rx_rcb_mapping); | |
f77a6a8e MC |
6498 | tnapi->rx_rcb = NULL; |
6499 | } | |
6500 | ||
8fea32b9 MC |
6501 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
6502 | ||
f77a6a8e | 6503 | if (tnapi->hw_status) { |
4bae65c8 MC |
6504 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
6505 | tnapi->hw_status, | |
6506 | tnapi->status_mapping); | |
f77a6a8e MC |
6507 | tnapi->hw_status = NULL; |
6508 | } | |
1da177e4 | 6509 | } |
f77a6a8e | 6510 | |
1da177e4 | 6511 | if (tp->hw_stats) { |
4bae65c8 MC |
6512 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
6513 | tp->hw_stats, tp->stats_mapping); | |
1da177e4 LT |
6514 | tp->hw_stats = NULL; |
6515 | } | |
6516 | } | |
6517 | ||
6518 | /* | |
6519 | * Must not be invoked with interrupt sources disabled and | |
6520 | * the hardware shutdown down. Can sleep. | |
6521 | */ | |
6522 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6523 | { | |
f77a6a8e | 6524 | int i; |
898a56f8 | 6525 | |
4bae65c8 MC |
6526 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
6527 | sizeof(struct tg3_hw_stats), | |
6528 | &tp->stats_mapping, | |
6529 | GFP_KERNEL); | |
f77a6a8e | 6530 | if (!tp->hw_stats) |
1da177e4 LT |
6531 | goto err_out; |
6532 | ||
f77a6a8e | 6533 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 6534 | |
f77a6a8e MC |
6535 | for (i = 0; i < tp->irq_cnt; i++) { |
6536 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 6537 | struct tg3_hw_status *sblk; |
1da177e4 | 6538 | |
4bae65c8 MC |
6539 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
6540 | TG3_HW_STATUS_SIZE, | |
6541 | &tnapi->status_mapping, | |
6542 | GFP_KERNEL); | |
f77a6a8e MC |
6543 | if (!tnapi->hw_status) |
6544 | goto err_out; | |
898a56f8 | 6545 | |
f77a6a8e | 6546 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
6547 | sblk = tnapi->hw_status; |
6548 | ||
8fea32b9 MC |
6549 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
6550 | goto err_out; | |
6551 | ||
19cfaecc MC |
6552 | /* If multivector TSS is enabled, vector 0 does not handle |
6553 | * tx interrupts. Don't allocate any resources for it. | |
6554 | */ | |
6555 | if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) || | |
6556 | (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) { | |
6557 | tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * | |
6558 | TG3_TX_RING_SIZE, | |
6559 | GFP_KERNEL); | |
6560 | if (!tnapi->tx_buffers) | |
6561 | goto err_out; | |
6562 | ||
4bae65c8 MC |
6563 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
6564 | TG3_TX_RING_BYTES, | |
6565 | &tnapi->tx_desc_mapping, | |
6566 | GFP_KERNEL); | |
19cfaecc MC |
6567 | if (!tnapi->tx_ring) |
6568 | goto err_out; | |
6569 | } | |
6570 | ||
8d9d7cfc MC |
6571 | /* |
6572 | * When RSS is enabled, the status block format changes | |
6573 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6574 | * and "rx_mini_consumer" members get mapped to the | |
6575 | * other three rx return ring producer indexes. | |
6576 | */ | |
6577 | switch (i) { | |
6578 | default: | |
6579 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6580 | break; | |
6581 | case 2: | |
6582 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6583 | break; | |
6584 | case 3: | |
6585 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6586 | break; | |
6587 | case 4: | |
6588 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6589 | break; | |
6590 | } | |
72334482 | 6591 | |
0c1d0e2b MC |
6592 | /* |
6593 | * If multivector RSS is enabled, vector 0 does not handle | |
6594 | * rx or tx interrupts. Don't allocate any resources for it. | |
6595 | */ | |
6596 | if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) | |
6597 | continue; | |
6598 | ||
4bae65c8 MC |
6599 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
6600 | TG3_RX_RCB_RING_BYTES(tp), | |
6601 | &tnapi->rx_rcb_mapping, | |
6602 | GFP_KERNEL); | |
f77a6a8e MC |
6603 | if (!tnapi->rx_rcb) |
6604 | goto err_out; | |
72334482 | 6605 | |
f77a6a8e | 6606 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 6607 | } |
1da177e4 LT |
6608 | |
6609 | return 0; | |
6610 | ||
6611 | err_out: | |
6612 | tg3_free_consistent(tp); | |
6613 | return -ENOMEM; | |
6614 | } | |
6615 | ||
6616 | #define MAX_WAIT_CNT 1000 | |
6617 | ||
6618 | /* To stop a block, clear the enable bit and poll till it | |
6619 | * clears. tp->lock is held. | |
6620 | */ | |
b3b7d6be | 6621 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
6622 | { |
6623 | unsigned int i; | |
6624 | u32 val; | |
6625 | ||
6626 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
6627 | switch (ofs) { | |
6628 | case RCVLSC_MODE: | |
6629 | case DMAC_MODE: | |
6630 | case MBFREE_MODE: | |
6631 | case BUFMGR_MODE: | |
6632 | case MEMARB_MODE: | |
6633 | /* We can't enable/disable these bits of the | |
6634 | * 5705/5750, just say success. | |
6635 | */ | |
6636 | return 0; | |
6637 | ||
6638 | default: | |
6639 | break; | |
855e1111 | 6640 | } |
1da177e4 LT |
6641 | } |
6642 | ||
6643 | val = tr32(ofs); | |
6644 | val &= ~enable_bit; | |
6645 | tw32_f(ofs, val); | |
6646 | ||
6647 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6648 | udelay(100); | |
6649 | val = tr32(ofs); | |
6650 | if ((val & enable_bit) == 0) | |
6651 | break; | |
6652 | } | |
6653 | ||
b3b7d6be | 6654 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
6655 | dev_err(&tp->pdev->dev, |
6656 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
6657 | ofs, enable_bit); | |
1da177e4 LT |
6658 | return -ENODEV; |
6659 | } | |
6660 | ||
6661 | return 0; | |
6662 | } | |
6663 | ||
6664 | /* tp->lock is held. */ | |
b3b7d6be | 6665 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
6666 | { |
6667 | int i, err; | |
6668 | ||
6669 | tg3_disable_ints(tp); | |
6670 | ||
6671 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6672 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6673 | udelay(10); | |
6674 | ||
b3b7d6be DM |
6675 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
6676 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6677 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6678 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6679 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6680 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6681 | ||
6682 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6683 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6684 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6685 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6686 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6687 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6688 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
6689 | |
6690 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6691 | tw32_f(MAC_MODE, tp->mac_mode); | |
6692 | udelay(40); | |
6693 | ||
6694 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6695 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6696 | ||
6697 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6698 | udelay(100); | |
6699 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6700 | break; | |
6701 | } | |
6702 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
6703 | dev_err(&tp->pdev->dev, |
6704 | "%s timed out, TX_MODE_ENABLE will not clear " | |
6705 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 6706 | err |= -ENODEV; |
1da177e4 LT |
6707 | } |
6708 | ||
e6de8ad1 | 6709 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
6710 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
6711 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
6712 | |
6713 | tw32(FTQ_RESET, 0xffffffff); | |
6714 | tw32(FTQ_RESET, 0x00000000); | |
6715 | ||
b3b7d6be DM |
6716 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
6717 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 6718 | |
f77a6a8e MC |
6719 | for (i = 0; i < tp->irq_cnt; i++) { |
6720 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6721 | if (tnapi->hw_status) | |
6722 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6723 | } | |
1da177e4 LT |
6724 | if (tp->hw_stats) |
6725 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6726 | ||
1da177e4 LT |
6727 | return err; |
6728 | } | |
6729 | ||
0d3031d9 MC |
6730 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
6731 | { | |
6732 | int i; | |
6733 | u32 apedata; | |
6734 | ||
dc6d0744 MC |
6735 | /* NCSI does not support APE events */ |
6736 | if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI) | |
6737 | return; | |
6738 | ||
0d3031d9 MC |
6739 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); |
6740 | if (apedata != APE_SEG_SIG_MAGIC) | |
6741 | return; | |
6742 | ||
6743 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 6744 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
6745 | return; |
6746 | ||
6747 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6748 | for (i = 0; i < 10; i++) { | |
6749 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6750 | return; | |
6751 | ||
6752 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6753 | ||
6754 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6755 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6756 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6757 | ||
6758 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6759 | ||
6760 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6761 | break; | |
6762 | ||
6763 | udelay(100); | |
6764 | } | |
6765 | ||
6766 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6767 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6768 | } | |
6769 | ||
6770 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6771 | { | |
6772 | u32 event; | |
6773 | u32 apedata; | |
6774 | ||
6775 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
6776 | return; | |
6777 | ||
6778 | switch (kind) { | |
33f401ae MC |
6779 | case RESET_KIND_INIT: |
6780 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6781 | APE_HOST_SEG_SIG_MAGIC); | |
6782 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6783 | APE_HOST_SEG_LEN_MAGIC); | |
6784 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6785 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6786 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6867c843 | 6787 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); |
33f401ae MC |
6788 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, |
6789 | APE_HOST_BEHAV_NO_PHYLOCK); | |
dc6d0744 MC |
6790 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, |
6791 | TG3_APE_HOST_DRVR_STATE_START); | |
33f401ae MC |
6792 | |
6793 | event = APE_EVENT_STATUS_STATE_START; | |
6794 | break; | |
6795 | case RESET_KIND_SHUTDOWN: | |
6796 | /* With the interface we are currently using, | |
6797 | * APE does not track driver state. Wiping | |
6798 | * out the HOST SEGMENT SIGNATURE forces | |
6799 | * the APE to assume OS absent status. | |
6800 | */ | |
6801 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
b2aee154 | 6802 | |
dc6d0744 MC |
6803 | if (device_may_wakeup(&tp->pdev->dev) && |
6804 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) { | |
6805 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, | |
6806 | TG3_APE_HOST_WOL_SPEED_AUTO); | |
6807 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; | |
6808 | } else | |
6809 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; | |
6810 | ||
6811 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); | |
6812 | ||
33f401ae MC |
6813 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
6814 | break; | |
6815 | case RESET_KIND_SUSPEND: | |
6816 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
6817 | break; | |
6818 | default: | |
6819 | return; | |
0d3031d9 MC |
6820 | } |
6821 | ||
6822 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
6823 | ||
6824 | tg3_ape_send_event(tp, event); | |
6825 | } | |
6826 | ||
1da177e4 LT |
6827 | /* tp->lock is held. */ |
6828 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
6829 | { | |
f49639e6 DM |
6830 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
6831 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 LT |
6832 | |
6833 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6834 | switch (kind) { | |
6835 | case RESET_KIND_INIT: | |
6836 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6837 | DRV_STATE_START); | |
6838 | break; | |
6839 | ||
6840 | case RESET_KIND_SHUTDOWN: | |
6841 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6842 | DRV_STATE_UNLOAD); | |
6843 | break; | |
6844 | ||
6845 | case RESET_KIND_SUSPEND: | |
6846 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6847 | DRV_STATE_SUSPEND); | |
6848 | break; | |
6849 | ||
6850 | default: | |
6851 | break; | |
855e1111 | 6852 | } |
1da177e4 | 6853 | } |
0d3031d9 MC |
6854 | |
6855 | if (kind == RESET_KIND_INIT || | |
6856 | kind == RESET_KIND_SUSPEND) | |
6857 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6858 | } |
6859 | ||
6860 | /* tp->lock is held. */ | |
6861 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
6862 | { | |
6863 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6864 | switch (kind) { | |
6865 | case RESET_KIND_INIT: | |
6866 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6867 | DRV_STATE_START_DONE); | |
6868 | break; | |
6869 | ||
6870 | case RESET_KIND_SHUTDOWN: | |
6871 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6872 | DRV_STATE_UNLOAD_DONE); | |
6873 | break; | |
6874 | ||
6875 | default: | |
6876 | break; | |
855e1111 | 6877 | } |
1da177e4 | 6878 | } |
0d3031d9 MC |
6879 | |
6880 | if (kind == RESET_KIND_SHUTDOWN) | |
6881 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6882 | } |
6883 | ||
6884 | /* tp->lock is held. */ | |
6885 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
6886 | { | |
6887 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
6888 | switch (kind) { | |
6889 | case RESET_KIND_INIT: | |
6890 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6891 | DRV_STATE_START); | |
6892 | break; | |
6893 | ||
6894 | case RESET_KIND_SHUTDOWN: | |
6895 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6896 | DRV_STATE_UNLOAD); | |
6897 | break; | |
6898 | ||
6899 | case RESET_KIND_SUSPEND: | |
6900 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6901 | DRV_STATE_SUSPEND); | |
6902 | break; | |
6903 | ||
6904 | default: | |
6905 | break; | |
855e1111 | 6906 | } |
1da177e4 LT |
6907 | } |
6908 | } | |
6909 | ||
7a6f4369 MC |
6910 | static int tg3_poll_fw(struct tg3 *tp) |
6911 | { | |
6912 | int i; | |
6913 | u32 val; | |
6914 | ||
b5d3772c | 6915 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
6916 | /* Wait up to 20ms for init done. */ |
6917 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
6918 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
6919 | return 0; | |
0ccead18 | 6920 | udelay(100); |
b5d3772c MC |
6921 | } |
6922 | return -ENODEV; | |
6923 | } | |
6924 | ||
7a6f4369 MC |
6925 | /* Wait for firmware initialization to complete. */ |
6926 | for (i = 0; i < 100000; i++) { | |
6927 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
6928 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
6929 | break; | |
6930 | udelay(10); | |
6931 | } | |
6932 | ||
6933 | /* Chip might not be fitted with firmware. Some Sun onboard | |
6934 | * parts are configured like that. So don't signal the timeout | |
6935 | * of the above loop as an error, but do report the lack of | |
6936 | * running firmware once. | |
6937 | */ | |
6938 | if (i >= 100000 && | |
6939 | !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { | |
6940 | tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED; | |
6941 | ||
05dbe005 | 6942 | netdev_info(tp->dev, "No firmware running\n"); |
7a6f4369 MC |
6943 | } |
6944 | ||
6b10c165 MC |
6945 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
6946 | /* The 57765 A0 needs a little more | |
6947 | * time to do some important work. | |
6948 | */ | |
6949 | mdelay(10); | |
6950 | } | |
6951 | ||
7a6f4369 MC |
6952 | return 0; |
6953 | } | |
6954 | ||
ee6a99b5 MC |
6955 | /* Save PCI command register before chip reset */ |
6956 | static void tg3_save_pci_state(struct tg3 *tp) | |
6957 | { | |
8a6eac90 | 6958 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
6959 | } |
6960 | ||
6961 | /* Restore PCI state after chip reset */ | |
6962 | static void tg3_restore_pci_state(struct tg3 *tp) | |
6963 | { | |
6964 | u32 val; | |
6965 | ||
6966 | /* Re-enable indirect register accesses. */ | |
6967 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
6968 | tp->misc_host_ctrl); | |
6969 | ||
6970 | /* Set MAX PCI retry to zero. */ | |
6971 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
6972 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
6973 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) | |
6974 | val |= PCISTATE_RETRY_SAME_DMA; | |
0d3031d9 MC |
6975 | /* Allow reads and writes to the APE register and memory space. */ |
6976 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
6977 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
6978 | PCISTATE_ALLOW_APE_SHMEM_WR | |
6979 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
ee6a99b5 MC |
6980 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
6981 | ||
8a6eac90 | 6982 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 6983 | |
fcb389df MC |
6984 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
6985 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
cf79003d | 6986 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
fcb389df MC |
6987 | else { |
6988 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
6989 | tp->pci_cacheline_sz); | |
6990 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
6991 | tp->pci_lat_timer); | |
6992 | } | |
114342f2 | 6993 | } |
5f5c51e3 | 6994 | |
ee6a99b5 | 6995 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
52f4490c | 6996 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
9974a356 MC |
6997 | u16 pcix_cmd; |
6998 | ||
6999 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7000 | &pcix_cmd); | |
7001 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
7002 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
7003 | pcix_cmd); | |
7004 | } | |
ee6a99b5 MC |
7005 | |
7006 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
ee6a99b5 MC |
7007 | |
7008 | /* Chip reset on 5780 will reset MSI enable bit, | |
7009 | * so need to restore it. | |
7010 | */ | |
7011 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
7012 | u16 ctrl; | |
7013 | ||
7014 | pci_read_config_word(tp->pdev, | |
7015 | tp->msi_cap + PCI_MSI_FLAGS, | |
7016 | &ctrl); | |
7017 | pci_write_config_word(tp->pdev, | |
7018 | tp->msi_cap + PCI_MSI_FLAGS, | |
7019 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
7020 | val = tr32(MSGINT_MODE); | |
7021 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
7022 | } | |
7023 | } | |
7024 | } | |
7025 | ||
1da177e4 LT |
7026 | static void tg3_stop_fw(struct tg3 *); |
7027 | ||
7028 | /* tp->lock is held. */ | |
7029 | static int tg3_chip_reset(struct tg3 *tp) | |
7030 | { | |
7031 | u32 val; | |
1ee582d8 | 7032 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 7033 | int i, err; |
1da177e4 | 7034 | |
f49639e6 DM |
7035 | tg3_nvram_lock(tp); |
7036 | ||
77b483f1 MC |
7037 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
7038 | ||
f49639e6 DM |
7039 | /* No matching tg3_nvram_unlock() after this because |
7040 | * chip reset below will undo the nvram lock. | |
7041 | */ | |
7042 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 7043 | |
ee6a99b5 MC |
7044 | /* GRC_MISC_CFG core clock reset will clear the memory |
7045 | * enable bit in PCI register 4 and the MSI enable bit | |
7046 | * on some chips, so we save relevant registers here. | |
7047 | */ | |
7048 | tg3_save_pci_state(tp); | |
7049 | ||
d9ab5ad1 | 7050 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
321d32a0 | 7051 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) |
d9ab5ad1 MC |
7052 | tw32(GRC_FASTBOOT_PC, 0); |
7053 | ||
1da177e4 LT |
7054 | /* |
7055 | * We must avoid the readl() that normally takes place. | |
7056 | * It locks machines, causes machine checks, and other | |
7057 | * fun things. So, temporarily disable the 5701 | |
7058 | * hardware workaround, while we do the reset. | |
7059 | */ | |
1ee582d8 MC |
7060 | write_op = tp->write32; |
7061 | if (write_op == tg3_write_flush_reg32) | |
7062 | tp->write32 = tg3_write32; | |
1da177e4 | 7063 | |
d18edcb2 MC |
7064 | /* Prevent the irq handler from reading or writing PCI registers |
7065 | * during chip reset when the memory enable bit in the PCI command | |
7066 | * register may be cleared. The chip does not generate interrupt | |
7067 | * at this time, but the irq handler may still be called due to irq | |
7068 | * sharing or irqpoll. | |
7069 | */ | |
7070 | tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; | |
f77a6a8e MC |
7071 | for (i = 0; i < tp->irq_cnt; i++) { |
7072 | struct tg3_napi *tnapi = &tp->napi[i]; | |
7073 | if (tnapi->hw_status) { | |
7074 | tnapi->hw_status->status = 0; | |
7075 | tnapi->hw_status->status_tag = 0; | |
7076 | } | |
7077 | tnapi->last_tag = 0; | |
7078 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 7079 | } |
d18edcb2 | 7080 | smp_mb(); |
4f125f42 MC |
7081 | |
7082 | for (i = 0; i < tp->irq_cnt; i++) | |
7083 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 7084 | |
255ca311 MC |
7085 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7086 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
7087 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
7088 | } | |
7089 | ||
1da177e4 LT |
7090 | /* do the reset */ |
7091 | val = GRC_MISC_CFG_CORECLK_RESET; | |
7092 | ||
7093 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
88075d91 MC |
7094 | /* Force PCIe 1.0a mode */ |
7095 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
1407deb1 | 7096 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
88075d91 MC |
7097 | tr32(TG3_PCIE_PHY_TSTCTL) == |
7098 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | |
7099 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | |
7100 | ||
1da177e4 LT |
7101 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
7102 | tw32(GRC_MISC_CFG, (1 << 29)); | |
7103 | val |= (1 << 29); | |
7104 | } | |
7105 | } | |
7106 | ||
b5d3772c MC |
7107 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7108 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
7109 | tw32(GRC_VCPU_EXT_CTRL, | |
7110 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7111 | } | |
7112 | ||
f37500d3 MC |
7113 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
7114 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
7115 | !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) | |
1da177e4 | 7116 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
f37500d3 | 7117 | |
1da177e4 LT |
7118 | tw32(GRC_MISC_CFG, val); |
7119 | ||
1ee582d8 MC |
7120 | /* restore 5701 hardware bug workaround write method */ |
7121 | tp->write32 = write_op; | |
1da177e4 LT |
7122 | |
7123 | /* Unfortunately, we have to delay before the PCI read back. | |
7124 | * Some 575X chips even will not respond to a PCI cfg access | |
7125 | * when the reset command is given to the chip. | |
7126 | * | |
7127 | * How do these hardware designers expect things to work | |
7128 | * properly if the PCI write is posted for a long period | |
7129 | * of time? It is always necessary to have some method by | |
7130 | * which a register read back can occur to push the write | |
7131 | * out which does the reset. | |
7132 | * | |
7133 | * For most tg3 variants the trick below was working. | |
7134 | * Ho hum... | |
7135 | */ | |
7136 | udelay(120); | |
7137 | ||
7138 | /* Flush PCI posted writes. The normal MMIO registers | |
7139 | * are inaccessible at this time so this is the only | |
7140 | * way to make this reliably (actually, this is no longer | |
7141 | * the case, see above). I tried to use indirect | |
7142 | * register read/write but this upset some 5701 variants. | |
7143 | */ | |
7144 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
7145 | ||
7146 | udelay(120); | |
7147 | ||
5e7dfd0f | 7148 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { |
e7126997 MC |
7149 | u16 val16; |
7150 | ||
1da177e4 LT |
7151 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
7152 | int i; | |
7153 | u32 cfg_val; | |
7154 | ||
7155 | /* Wait for link training to complete. */ | |
7156 | for (i = 0; i < 5000; i++) | |
7157 | udelay(100); | |
7158 | ||
7159 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
7160 | pci_write_config_dword(tp->pdev, 0xc4, | |
7161 | cfg_val | (1 << 15)); | |
7162 | } | |
5e7dfd0f | 7163 | |
e7126997 MC |
7164 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
7165 | pci_read_config_word(tp->pdev, | |
7166 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
7167 | &val16); | |
7168 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
7169 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
7170 | /* | |
7171 | * Older PCIe devices only support the 128 byte | |
7172 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 7173 | */ |
6de34cb9 | 7174 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) |
e7126997 | 7175 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
5e7dfd0f MC |
7176 | pci_write_config_word(tp->pdev, |
7177 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
e7126997 | 7178 | val16); |
5e7dfd0f | 7179 | |
cf79003d | 7180 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); |
5e7dfd0f MC |
7181 | |
7182 | /* Clear error status */ | |
7183 | pci_write_config_word(tp->pdev, | |
7184 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
7185 | PCI_EXP_DEVSTA_CED | | |
7186 | PCI_EXP_DEVSTA_NFED | | |
7187 | PCI_EXP_DEVSTA_FED | | |
7188 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
7189 | } |
7190 | ||
ee6a99b5 | 7191 | tg3_restore_pci_state(tp); |
1da177e4 | 7192 | |
d18edcb2 MC |
7193 | tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING; |
7194 | ||
ee6a99b5 MC |
7195 | val = 0; |
7196 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
4cf78e4f | 7197 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 7198 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
7199 | |
7200 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7201 | tg3_stop_fw(tp); | |
7202 | tw32(0x5000, 0x400); | |
7203 | } | |
7204 | ||
7205 | tw32(GRC_MODE, tp->grc_mode); | |
7206 | ||
7207 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7208 | val = tr32(0xc4); |
1da177e4 LT |
7209 | |
7210 | tw32(0xc4, val | (1 << 15)); | |
7211 | } | |
7212 | ||
7213 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7214 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7215 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7216 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7217 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7218 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7219 | } | |
7220 | ||
d2394e6b MC |
7221 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7222 | tp->mac_mode = MAC_MODE_APE_TX_EN | | |
7223 | MAC_MODE_APE_RX_EN | | |
7224 | MAC_MODE_TDE_ENABLE; | |
7225 | ||
f07e9af3 | 7226 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
d2394e6b MC |
7227 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; |
7228 | val = tp->mac_mode; | |
f07e9af3 | 7229 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
d2394e6b MC |
7230 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
7231 | val = tp->mac_mode; | |
1da177e4 | 7232 | } else |
d2394e6b MC |
7233 | val = 0; |
7234 | ||
7235 | tw32_f(MAC_MODE, val); | |
1da177e4 LT |
7236 | udelay(40); |
7237 | ||
77b483f1 MC |
7238 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7239 | ||
7a6f4369 MC |
7240 | err = tg3_poll_fw(tp); |
7241 | if (err) | |
7242 | return err; | |
1da177e4 | 7243 | |
0a9140cf MC |
7244 | tg3_mdio_start(tp); |
7245 | ||
1da177e4 | 7246 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
f6eb9b1f MC |
7247 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7248 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
1407deb1 | 7249 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
ab0049b4 | 7250 | val = tr32(0x7c00); |
1da177e4 LT |
7251 | |
7252 | tw32(0x7c00, val | (1 << 25)); | |
7253 | } | |
7254 | ||
d78b59f5 MC |
7255 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
7256 | val = tr32(TG3_CPMU_CLCK_ORIDE); | |
7257 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | |
7258 | } | |
7259 | ||
1da177e4 LT |
7260 | /* Reprobe ASF enable state. */ |
7261 | tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; | |
7262 | tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; | |
7263 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
7264 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7265 | u32 nic_cfg; | |
7266 | ||
7267 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7268 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
7269 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
4ba526ce | 7270 | tp->last_event_jiffies = jiffies; |
cbf46853 | 7271 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
7272 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
7273 | } | |
7274 | } | |
7275 | ||
7276 | return 0; | |
7277 | } | |
7278 | ||
7279 | /* tp->lock is held. */ | |
7280 | static void tg3_stop_fw(struct tg3 *tp) | |
7281 | { | |
0d3031d9 MC |
7282 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
7283 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
7284 | /* Wait for RX cpu to ACK the previous event. */ |
7285 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7286 | |
7287 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
7288 | |
7289 | tg3_generate_fw_event(tp); | |
1da177e4 | 7290 | |
7c5026aa MC |
7291 | /* Wait for RX cpu to ACK this event. */ |
7292 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7293 | } |
7294 | } | |
7295 | ||
7296 | /* tp->lock is held. */ | |
944d980e | 7297 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7298 | { |
7299 | int err; | |
7300 | ||
7301 | tg3_stop_fw(tp); | |
7302 | ||
944d980e | 7303 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7304 | |
b3b7d6be | 7305 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7306 | err = tg3_chip_reset(tp); |
7307 | ||
daba2a63 MC |
7308 | __tg3_set_mac_addr(tp, 0); |
7309 | ||
944d980e MC |
7310 | tg3_write_sig_legacy(tp, kind); |
7311 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
7312 | |
7313 | if (err) | |
7314 | return err; | |
7315 | ||
7316 | return 0; | |
7317 | } | |
7318 | ||
1da177e4 LT |
7319 | #define RX_CPU_SCRATCH_BASE 0x30000 |
7320 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7321 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7322 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7323 | ||
7324 | /* tp->lock is held. */ | |
7325 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7326 | { | |
7327 | int i; | |
7328 | ||
5d9428de ES |
7329 | BUG_ON(offset == TX_CPU_BASE && |
7330 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)); | |
1da177e4 | 7331 | |
b5d3772c MC |
7332 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7333 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7334 | ||
7335 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7336 | return 0; | |
7337 | } | |
1da177e4 LT |
7338 | if (offset == RX_CPU_BASE) { |
7339 | for (i = 0; i < 10000; i++) { | |
7340 | tw32(offset + CPU_STATE, 0xffffffff); | |
7341 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7342 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7343 | break; | |
7344 | } | |
7345 | ||
7346 | tw32(offset + CPU_STATE, 0xffffffff); | |
7347 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7348 | udelay(10); | |
7349 | } else { | |
7350 | for (i = 0; i < 10000; i++) { | |
7351 | tw32(offset + CPU_STATE, 0xffffffff); | |
7352 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7353 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7354 | break; | |
7355 | } | |
7356 | } | |
7357 | ||
7358 | if (i >= 10000) { | |
05dbe005 JP |
7359 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
7360 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
1da177e4 LT |
7361 | return -ENODEV; |
7362 | } | |
ec41c7df MC |
7363 | |
7364 | /* Clear firmware's nvram arbitration. */ | |
7365 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
7366 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
1da177e4 LT |
7367 | return 0; |
7368 | } | |
7369 | ||
7370 | struct fw_info { | |
077f849d JSR |
7371 | unsigned int fw_base; |
7372 | unsigned int fw_len; | |
7373 | const __be32 *fw_data; | |
1da177e4 LT |
7374 | }; |
7375 | ||
7376 | /* tp->lock is held. */ | |
7377 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7378 | int cpu_scratch_size, struct fw_info *info) | |
7379 | { | |
ec41c7df | 7380 | int err, lock_err, i; |
1da177e4 LT |
7381 | void (*write_op)(struct tg3 *, u32, u32); |
7382 | ||
7383 | if (cpu_base == TX_CPU_BASE && | |
7384 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
5129c3a3 MC |
7385 | netdev_err(tp->dev, |
7386 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
05dbe005 | 7387 | __func__); |
1da177e4 LT |
7388 | return -EINVAL; |
7389 | } | |
7390 | ||
7391 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
7392 | write_op = tg3_write_mem; | |
7393 | else | |
7394 | write_op = tg3_write_indirect_reg32; | |
7395 | ||
1b628151 MC |
7396 | /* It is possible that bootcode is still loading at this point. |
7397 | * Get the nvram lock first before halting the cpu. | |
7398 | */ | |
ec41c7df | 7399 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 7400 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
7401 | if (!lock_err) |
7402 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
7403 | if (err) |
7404 | goto out; | |
7405 | ||
7406 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7407 | write_op(tp, cpu_scratch_base + i, 0); | |
7408 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7409 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 7410 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 7411 | write_op(tp, (cpu_scratch_base + |
077f849d | 7412 | (info->fw_base & 0xffff) + |
1da177e4 | 7413 | (i * sizeof(u32))), |
077f849d | 7414 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
7415 | |
7416 | err = 0; | |
7417 | ||
7418 | out: | |
1da177e4 LT |
7419 | return err; |
7420 | } | |
7421 | ||
7422 | /* tp->lock is held. */ | |
7423 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7424 | { | |
7425 | struct fw_info info; | |
077f849d | 7426 | const __be32 *fw_data; |
1da177e4 LT |
7427 | int err, i; |
7428 | ||
077f849d JSR |
7429 | fw_data = (void *)tp->fw->data; |
7430 | ||
7431 | /* Firmware blob starts with version numbers, followed by | |
7432 | start address and length. We are setting complete length. | |
7433 | length = end_address_of_bss - start_address_of_text. | |
7434 | Remainder is the blob to be loaded contiguously | |
7435 | from start address. */ | |
7436 | ||
7437 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7438 | info.fw_len = tp->fw->size - 12; | |
7439 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
7440 | |
7441 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7442 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7443 | &info); | |
7444 | if (err) | |
7445 | return err; | |
7446 | ||
7447 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7448 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7449 | &info); | |
7450 | if (err) | |
7451 | return err; | |
7452 | ||
7453 | /* Now startup only the RX cpu. */ | |
7454 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 7455 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7456 | |
7457 | for (i = 0; i < 5; i++) { | |
077f849d | 7458 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
7459 | break; |
7460 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7461 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7462 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7463 | udelay(1000); |
7464 | } | |
7465 | if (i >= 5) { | |
5129c3a3 MC |
7466 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
7467 | "should be %08x\n", __func__, | |
05dbe005 | 7468 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); |
1da177e4 LT |
7469 | return -ENODEV; |
7470 | } | |
7471 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7472 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7473 | ||
7474 | return 0; | |
7475 | } | |
7476 | ||
1da177e4 | 7477 | /* 5705 needs a special version of the TSO firmware. */ |
1da177e4 LT |
7478 | |
7479 | /* tp->lock is held. */ | |
7480 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7481 | { | |
7482 | struct fw_info info; | |
077f849d | 7483 | const __be32 *fw_data; |
1da177e4 LT |
7484 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
7485 | int err, i; | |
7486 | ||
7487 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
7488 | return 0; | |
7489 | ||
077f849d JSR |
7490 | fw_data = (void *)tp->fw->data; |
7491 | ||
7492 | /* Firmware blob starts with version numbers, followed by | |
7493 | start address and length. We are setting complete length. | |
7494 | length = end_address_of_bss - start_address_of_text. | |
7495 | Remainder is the blob to be loaded contiguously | |
7496 | from start address. */ | |
7497 | ||
7498 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7499 | cpu_scratch_size = tp->fw_len; | |
7500 | info.fw_len = tp->fw->size - 12; | |
7501 | info.fw_data = &fw_data[3]; | |
7502 | ||
1da177e4 | 7503 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7504 | cpu_base = RX_CPU_BASE; |
7505 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 7506 | } else { |
1da177e4 LT |
7507 | cpu_base = TX_CPU_BASE; |
7508 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7509 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7510 | } | |
7511 | ||
7512 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7513 | cpu_scratch_base, cpu_scratch_size, | |
7514 | &info); | |
7515 | if (err) | |
7516 | return err; | |
7517 | ||
7518 | /* Now startup the cpu. */ | |
7519 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 7520 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7521 | |
7522 | for (i = 0; i < 5; i++) { | |
077f849d | 7523 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
7524 | break; |
7525 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7526 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7527 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7528 | udelay(1000); |
7529 | } | |
7530 | if (i >= 5) { | |
5129c3a3 MC |
7531 | netdev_err(tp->dev, |
7532 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
05dbe005 | 7533 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); |
1da177e4 LT |
7534 | return -ENODEV; |
7535 | } | |
7536 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7537 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7538 | return 0; | |
7539 | } | |
7540 | ||
1da177e4 | 7541 | |
1da177e4 LT |
7542 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7543 | { | |
7544 | struct tg3 *tp = netdev_priv(dev); | |
7545 | struct sockaddr *addr = p; | |
986e0aeb | 7546 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7547 | |
f9804ddb MC |
7548 | if (!is_valid_ether_addr(addr->sa_data)) |
7549 | return -EINVAL; | |
7550 | ||
1da177e4 LT |
7551 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7552 | ||
e75f7c90 MC |
7553 | if (!netif_running(dev)) |
7554 | return 0; | |
7555 | ||
58712ef9 | 7556 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { |
986e0aeb | 7557 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7558 | |
986e0aeb MC |
7559 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7560 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7561 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7562 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7563 | ||
7564 | /* Skip MAC addr 1 if ASF is using it. */ | |
7565 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7566 | !(addr1_high == 0 && addr1_low == 0)) | |
7567 | skip_mac_1 = 1; | |
58712ef9 | 7568 | } |
986e0aeb MC |
7569 | spin_lock_bh(&tp->lock); |
7570 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7571 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7572 | |
b9ec6c1b | 7573 | return err; |
1da177e4 LT |
7574 | } |
7575 | ||
7576 | /* tp->lock is held. */ | |
7577 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7578 | dma_addr_t mapping, u32 maxlen_flags, | |
7579 | u32 nic_addr) | |
7580 | { | |
7581 | tg3_write_mem(tp, | |
7582 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7583 | ((u64) mapping >> 32)); | |
7584 | tg3_write_mem(tp, | |
7585 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7586 | ((u64) mapping & 0xffffffff)); | |
7587 | tg3_write_mem(tp, | |
7588 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7589 | maxlen_flags); | |
7590 | ||
7591 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7592 | tg3_write_mem(tp, | |
7593 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7594 | nic_addr); | |
7595 | } | |
7596 | ||
7597 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7598 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7599 | { |
b6080e12 MC |
7600 | int i; |
7601 | ||
19cfaecc | 7602 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) { |
b6080e12 MC |
7603 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7604 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7605 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7606 | } else { |
7607 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7608 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7609 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7610 | } |
b6080e12 | 7611 | |
20d7375c | 7612 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { |
19cfaecc MC |
7613 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
7614 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7615 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7616 | } else { | |
b6080e12 MC |
7617 | tw32(HOSTCC_RXCOL_TICKS, 0); |
7618 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7619 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7620 | } |
b6080e12 | 7621 | |
15f9850d DM |
7622 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
7623 | u32 val = ec->stats_block_coalesce_usecs; | |
7624 | ||
b6080e12 MC |
7625 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7626 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7627 | ||
15f9850d DM |
7628 | if (!netif_carrier_ok(tp->dev)) |
7629 | val = 0; | |
7630 | ||
7631 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7632 | } | |
b6080e12 MC |
7633 | |
7634 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7635 | u32 reg; | |
7636 | ||
7637 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7638 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
7639 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
7640 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
7641 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
7642 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc MC |
7643 | |
7644 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7645 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
7646 | tw32(reg, ec->tx_coalesce_usecs); | |
7647 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7648 | tw32(reg, ec->tx_max_coalesced_frames); | |
7649 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7650 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7651 | } | |
b6080e12 MC |
7652 | } |
7653 | ||
7654 | for (; i < tp->irq_max - 1; i++) { | |
7655 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 7656 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 7657 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc MC |
7658 | |
7659 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7660 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7661 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7662 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7663 | } | |
b6080e12 | 7664 | } |
15f9850d | 7665 | } |
1da177e4 | 7666 | |
2d31ecaf MC |
7667 | /* tp->lock is held. */ |
7668 | static void tg3_rings_reset(struct tg3 *tp) | |
7669 | { | |
7670 | int i; | |
f77a6a8e | 7671 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
7672 | struct tg3_napi *tnapi = &tp->napi[0]; |
7673 | ||
7674 | /* Disable all transmit rings but the first. */ | |
7675 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7676 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; | |
0a58d668 | 7677 | else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
3d37728b | 7678 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
b703df6f MC |
7679 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
7680 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
2d31ecaf MC |
7681 | else |
7682 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7683 | ||
7684 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7685 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7686 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7687 | BDINFO_FLAGS_DISABLED); | |
7688 | ||
7689 | ||
7690 | /* Disable all receive return rings but the first. */ | |
0a58d668 | 7691 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
f6eb9b1f MC |
7692 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
7693 | else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
2d31ecaf | 7694 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f MC |
7695 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
7696 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2d31ecaf MC |
7697 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
7698 | else | |
7699 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7700 | ||
7701 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7702 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7703 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7704 | BDINFO_FLAGS_DISABLED); | |
7705 | ||
7706 | /* Disable interrupts */ | |
7707 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
7708 | ||
7709 | /* Zero mailbox registers. */ | |
f77a6a8e | 7710 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) { |
6fd45cb8 | 7711 | for (i = 1; i < tp->irq_max; i++) { |
f77a6a8e MC |
7712 | tp->napi[i].tx_prod = 0; |
7713 | tp->napi[i].tx_cons = 0; | |
c2353a32 MC |
7714 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
7715 | tw32_mailbox(tp->napi[i].prodmbox, 0); | |
f77a6a8e MC |
7716 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
7717 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7718 | } | |
c2353a32 MC |
7719 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) |
7720 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
f77a6a8e MC |
7721 | } else { |
7722 | tp->napi[0].tx_prod = 0; | |
7723 | tp->napi[0].tx_cons = 0; | |
7724 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7725 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7726 | } | |
2d31ecaf MC |
7727 | |
7728 | /* Make sure the NIC-based send BD rings are disabled. */ | |
7729 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7730 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
7731 | for (i = 0; i < 16; i++) | |
7732 | tw32_tx_mbox(mbox + i * 8, 0); | |
7733 | } | |
7734 | ||
7735 | txrcb = NIC_SRAM_SEND_RCB; | |
7736 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7737 | ||
7738 | /* Clear status block in ram. */ | |
7739 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7740 | ||
7741 | /* Set status block DMA address */ | |
7742 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7743 | ((u64) tnapi->status_mapping >> 32)); | |
7744 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7745 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7746 | ||
f77a6a8e MC |
7747 | if (tnapi->tx_ring) { |
7748 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7749 | (TG3_TX_RING_SIZE << | |
7750 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7751 | NIC_SRAM_TX_BUFFER_DESC); | |
7752 | txrcb += TG3_BDINFO_SIZE; | |
7753 | } | |
7754 | ||
7755 | if (tnapi->rx_rcb) { | |
7756 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 MC |
7757 | (tp->rx_ret_ring_mask + 1) << |
7758 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); | |
f77a6a8e MC |
7759 | rxrcb += TG3_BDINFO_SIZE; |
7760 | } | |
7761 | ||
7762 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 7763 | |
f77a6a8e MC |
7764 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
7765 | u64 mapping = (u64)tnapi->status_mapping; | |
7766 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7767 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7768 | ||
7769 | /* Clear status block in ram. */ | |
7770 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7771 | ||
19cfaecc MC |
7772 | if (tnapi->tx_ring) { |
7773 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7774 | (TG3_TX_RING_SIZE << | |
7775 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7776 | NIC_SRAM_TX_BUFFER_DESC); | |
7777 | txrcb += TG3_BDINFO_SIZE; | |
7778 | } | |
f77a6a8e MC |
7779 | |
7780 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7cb32cf2 | 7781 | ((tp->rx_ret_ring_mask + 1) << |
f77a6a8e MC |
7782 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
7783 | ||
7784 | stblk += 8; | |
f77a6a8e MC |
7785 | rxrcb += TG3_BDINFO_SIZE; |
7786 | } | |
2d31ecaf MC |
7787 | } |
7788 | ||
1da177e4 | 7789 | /* tp->lock is held. */ |
8e7a22e3 | 7790 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
7791 | { |
7792 | u32 val, rdmac_mode; | |
7793 | int i, err, limit; | |
8fea32b9 | 7794 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
1da177e4 LT |
7795 | |
7796 | tg3_disable_ints(tp); | |
7797 | ||
7798 | tg3_stop_fw(tp); | |
7799 | ||
7800 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
7801 | ||
859a5887 | 7802 | if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) |
e6de8ad1 | 7803 | tg3_abort_hw(tp, 1); |
1da177e4 | 7804 | |
699c0193 MC |
7805 | /* Enable MAC control of LPI */ |
7806 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | |
7807 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, | |
7808 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | |
7809 | TG3_CPMU_EEE_LNKIDL_UART_IDL); | |
7810 | ||
7811 | tw32_f(TG3_CPMU_EEE_CTRL, | |
7812 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); | |
7813 | ||
a386b901 MC |
7814 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
7815 | TG3_CPMU_EEEMD_LPI_IN_TX | | |
7816 | TG3_CPMU_EEEMD_LPI_IN_RX | | |
7817 | TG3_CPMU_EEEMD_EEE_ENABLE; | |
7818 | ||
7819 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | |
7820 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | |
7821 | ||
7822 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
7823 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; | |
7824 | ||
7825 | tw32_f(TG3_CPMU_EEE_MODE, val); | |
7826 | ||
7827 | tw32_f(TG3_CPMU_EEE_DBTMR1, | |
7828 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | | |
7829 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); | |
7830 | ||
7831 | tw32_f(TG3_CPMU_EEE_DBTMR2, | |
d7f2ab20 | 7832 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
a386b901 | 7833 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
699c0193 MC |
7834 | } |
7835 | ||
603f1173 | 7836 | if (reset_phy) |
d4d2c558 MC |
7837 | tg3_phy_reset(tp); |
7838 | ||
1da177e4 LT |
7839 | err = tg3_chip_reset(tp); |
7840 | if (err) | |
7841 | return err; | |
7842 | ||
7843 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
7844 | ||
bcb37f6c | 7845 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
7846 | val = tr32(TG3_CPMU_CTRL); |
7847 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
7848 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
7849 | |
7850 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
7851 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
7852 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
7853 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
7854 | ||
7855 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
7856 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
7857 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
7858 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
7859 | ||
7860 | val = tr32(TG3_CPMU_HST_ACC); | |
7861 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
7862 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
7863 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
7864 | } |
7865 | ||
33466d93 MC |
7866 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7867 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
7868 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
7869 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
7870 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
7871 | |
7872 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
7873 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
7874 | ||
7875 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 7876 | |
f40386c8 MC |
7877 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
7878 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
7879 | } |
7880 | ||
614b0590 MC |
7881 | if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) { |
7882 | u32 grc_mode = tr32(GRC_MODE); | |
7883 | ||
7884 | /* Access the lower 1K of PL PCIE block registers. */ | |
7885 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
7886 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
7887 | ||
7888 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
7889 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
7890 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
7891 | ||
7892 | tw32(GRC_MODE, grc_mode); | |
7893 | } | |
7894 | ||
5093eedc MC |
7895 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
7896 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | |
7897 | u32 grc_mode = tr32(GRC_MODE); | |
cea46462 | 7898 | |
5093eedc MC |
7899 | /* Access the lower 1K of PL PCIE block registers. */ |
7900 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
7901 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
cea46462 | 7902 | |
5093eedc MC |
7903 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
7904 | TG3_PCIE_PL_LO_PHYCTL5); | |
7905 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
7906 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
cea46462 | 7907 | |
5093eedc MC |
7908 | tw32(GRC_MODE, grc_mode); |
7909 | } | |
a977dbe8 MC |
7910 | |
7911 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
7912 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
7913 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
7914 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
7915 | } |
7916 | ||
1da177e4 LT |
7917 | /* This works around an issue with Athlon chipsets on |
7918 | * B3 tigon3 silicon. This bit has no effect on any | |
7919 | * other revision. But do not set this on PCI Express | |
795d01c5 | 7920 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 7921 | */ |
795d01c5 MC |
7922 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { |
7923 | if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
7924 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
7925 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7926 | } | |
1da177e4 LT |
7927 | |
7928 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
7929 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
7930 | val = tr32(TG3PCI_PCISTATE); | |
7931 | val |= PCISTATE_RETRY_SAME_DMA; | |
7932 | tw32(TG3PCI_PCISTATE, val); | |
7933 | } | |
7934 | ||
0d3031d9 MC |
7935 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
7936 | /* Allow reads and writes to the | |
7937 | * APE register and memory space. | |
7938 | */ | |
7939 | val = tr32(TG3PCI_PCISTATE); | |
7940 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
7941 | PCISTATE_ALLOW_APE_SHMEM_WR | |
7942 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
7943 | tw32(TG3PCI_PCISTATE, val); |
7944 | } | |
7945 | ||
1da177e4 LT |
7946 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
7947 | /* Enable some hw fixes. */ | |
7948 | val = tr32(TG3PCI_MSI_DATA); | |
7949 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
7950 | tw32(TG3PCI_MSI_DATA, val); | |
7951 | } | |
7952 | ||
7953 | /* Descriptor ring init may make accesses to the | |
7954 | * NIC SRAM area to setup the TX descriptors, so we | |
7955 | * can only do this after the hardware has been | |
7956 | * successfully reset. | |
7957 | */ | |
32d8c572 MC |
7958 | err = tg3_init_rings(tp); |
7959 | if (err) | |
7960 | return err; | |
1da177e4 | 7961 | |
1407deb1 | 7962 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
cbf9ca6c MC |
7963 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
7964 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
7965 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
7966 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
cbf9ca6c MC |
7967 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
7968 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
7969 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
7970 | /* This value is determined during the probe time DMA |
7971 | * engine test, tg3_test_dma. | |
7972 | */ | |
7973 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
7974 | } | |
1da177e4 LT |
7975 | |
7976 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
7977 | GRC_MODE_4X_NIC_SEND_RINGS | | |
7978 | GRC_MODE_NO_TX_PHDR_CSUM | | |
7979 | GRC_MODE_NO_RX_PHDR_CSUM); | |
7980 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
7981 | |
7982 | /* Pseudo-header checksum is done by hardware logic and not | |
7983 | * the offload processers, so make the chip do the pseudo- | |
7984 | * header checksums on receive. For transmit it is more | |
7985 | * convenient to do the pseudo-header checksum in software | |
7986 | * as Linux does that on transmit for us in all cases. | |
7987 | */ | |
7988 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
7989 | |
7990 | tw32(GRC_MODE, | |
7991 | tp->grc_mode | | |
7992 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
7993 | ||
7994 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
7995 | val = tr32(GRC_MISC_CFG); | |
7996 | val &= ~0xff; | |
7997 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
7998 | tw32(GRC_MISC_CFG, val); | |
7999 | ||
8000 | /* Initialize MBUF/DESC pool. */ | |
cbf46853 | 8001 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
1da177e4 LT |
8002 | /* Do nothing. */ |
8003 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
8004 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
8005 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
8006 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
8007 | else | |
8008 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
8009 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
8010 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
859a5887 | 8011 | } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
1da177e4 LT |
8012 | int fw_len; |
8013 | ||
077f849d | 8014 | fw_len = tp->fw_len; |
1da177e4 LT |
8015 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
8016 | tw32(BUFMGR_MB_POOL_ADDR, | |
8017 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
8018 | tw32(BUFMGR_MB_POOL_SIZE, | |
8019 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
8020 | } | |
1da177e4 | 8021 | |
0f893dc6 | 8022 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
8023 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
8024 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
8025 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8026 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
8027 | tw32(BUFMGR_MB_HIGH_WATER, | |
8028 | tp->bufmgr_config.mbuf_high_water); | |
8029 | } else { | |
8030 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
8031 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
8032 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
8033 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
8034 | tw32(BUFMGR_MB_HIGH_WATER, | |
8035 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
8036 | } | |
8037 | tw32(BUFMGR_DMA_LOW_WATER, | |
8038 | tp->bufmgr_config.dma_low_water); | |
8039 | tw32(BUFMGR_DMA_HIGH_WATER, | |
8040 | tp->bufmgr_config.dma_high_water); | |
8041 | ||
d309a46e MC |
8042 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8043 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
8044 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | |
8045 | tw32(BUFMGR_MODE, val); | |
1da177e4 LT |
8046 | for (i = 0; i < 2000; i++) { |
8047 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
8048 | break; | |
8049 | udelay(10); | |
8050 | } | |
8051 | if (i >= 2000) { | |
05dbe005 | 8052 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
8053 | return -ENODEV; |
8054 | } | |
8055 | ||
8056 | /* Setup replenish threshold. */ | |
f92905de MC |
8057 | val = tp->rx_pending / 8; |
8058 | if (val == 0) | |
8059 | val = 1; | |
8060 | else if (val > tp->rx_std_max_post) | |
8061 | val = tp->rx_std_max_post; | |
b5d3772c MC |
8062 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
8063 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) | |
8064 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
8065 | ||
8066 | if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2)) | |
8067 | val = TG3_RX_INTERNAL_RING_SZ_5906 / 2; | |
8068 | } | |
f92905de MC |
8069 | |
8070 | tw32(RCVBDI_STD_THRESH, val); | |
1da177e4 LT |
8071 | |
8072 | /* Initialize TG3_BDINFO's at: | |
8073 | * RCVDBDI_STD_BD: standard eth size rx ring | |
8074 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
8075 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
8076 | * | |
8077 | * like so: | |
8078 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
8079 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
8080 | * ring attribute flags | |
8081 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
8082 | * | |
8083 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
8084 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
8085 | * | |
8086 | * The size of each ring is fixed in the firmware, but the location is | |
8087 | * configurable. | |
8088 | */ | |
8089 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 8090 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 8091 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8092 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
0a58d668 | 8093 | if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
87668d35 MC |
8094 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
8095 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 8096 | |
fdb72b38 MC |
8097 | /* Disable the mini ring */ |
8098 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
1da177e4 LT |
8099 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
8100 | BDINFO_FLAGS_DISABLED); | |
8101 | ||
fdb72b38 MC |
8102 | /* Program the jumbo buffer descriptor ring control |
8103 | * blocks on those devices that have them. | |
8104 | */ | |
bb18bb94 | 8105 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
4d163b75 MC |
8106 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
8107 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) { | |
1da177e4 LT |
8108 | /* Setup replenish threshold. */ |
8109 | tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); | |
8110 | ||
0f893dc6 | 8111 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { |
1da177e4 | 8112 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 8113 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 8114 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 8115 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
de9f5230 MC |
8116 | val = TG3_RX_JMB_RING_SIZE(tp) << |
8117 | BDINFO_FLAGS_MAXLEN_SHIFT; | |
1da177e4 | 8118 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
de9f5230 | 8119 | val | BDINFO_FLAGS_USE_EXT_RECV); |
a50d0796 MC |
8120 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) || |
8121 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
87668d35 MC |
8122 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
8123 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
8124 | } else { |
8125 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
8126 | BDINFO_FLAGS_DISABLED); | |
8127 | } | |
8128 | ||
1407deb1 | 8129 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
7cb32cf2 | 8130 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
de9f5230 | 8131 | val = TG3_RX_STD_MAX_SIZE_5700; |
7cb32cf2 | 8132 | else |
de9f5230 | 8133 | val = TG3_RX_STD_MAX_SIZE_5717; |
7cb32cf2 MC |
8134 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
8135 | val |= (TG3_RX_STD_DMA_SZ << 2); | |
8136 | } else | |
04380d40 | 8137 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 | 8138 | } else |
de9f5230 | 8139 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
8140 | |
8141 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 8142 | |
411da640 | 8143 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 8144 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 8145 | |
411da640 | 8146 | tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? |
21f581a5 | 8147 | tp->rx_jumbo_pending : 0; |
66711e66 | 8148 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 8149 | |
1407deb1 | 8150 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
f6eb9b1f MC |
8151 | tw32(STD_REPLENISH_LWM, 32); |
8152 | tw32(JMB_REPLENISH_LWM, 16); | |
8153 | } | |
8154 | ||
2d31ecaf MC |
8155 | tg3_rings_reset(tp); |
8156 | ||
1da177e4 | 8157 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 8158 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
8159 | |
8160 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
8161 | tw32(MAC_RX_MTU_SIZE, |
8162 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
8163 | |
8164 | /* The slot time is changed by tg3_setup_phy if we | |
8165 | * run at gigabit with half duplex. | |
8166 | */ | |
8167 | tw32(MAC_TX_LENGTHS, | |
8168 | (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
8169 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
8170 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
8171 | ||
8172 | /* Receive rules. */ | |
8173 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
8174 | tw32(RCVLPC_CONFIG, 0x0181); | |
8175 | ||
8176 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
8177 | * the RCVLPC_STATE_ENABLE mask. | |
8178 | */ | |
8179 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
8180 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
8181 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
8182 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
8183 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 8184 | |
deabaac8 | 8185 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
0339e4e3 MC |
8186 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
8187 | ||
57e6983c | 8188 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
8189 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
8190 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
8191 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
8192 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
8193 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
8194 | ||
c5908939 MC |
8195 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8196 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
1da177e4 | 8197 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && |
c13e3713 | 8198 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
8199 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
8200 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
8201 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { | |
8202 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8203 | } | |
8204 | } | |
8205 | ||
85e94ced MC |
8206 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) |
8207 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
8208 | ||
1da177e4 | 8209 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
027455ad MC |
8210 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
8211 | ||
e849cdc3 MC |
8212 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
8213 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
027455ad MC |
8214 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
8215 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 | 8216 | |
41a8a7ee MC |
8217 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
8218 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | |
8219 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
8220 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | |
1407deb1 | 8221 | (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
41a8a7ee | 8222 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
d78b59f5 MC |
8223 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8224 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b4495ed8 MC |
8225 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
8226 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | |
8227 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | |
8228 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | | |
8229 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | | |
8230 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; | |
b75cc0e4 | 8231 | } |
41a8a7ee MC |
8232 | tw32(TG3_RDMA_RSRVCTRL_REG, |
8233 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | |
8234 | } | |
8235 | ||
d78b59f5 MC |
8236 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
8237 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
d309a46e MC |
8238 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
8239 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | | |
8240 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | | |
8241 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); | |
8242 | } | |
8243 | ||
1da177e4 | 8244 | /* Receive/send statistics. */ |
1661394e MC |
8245 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
8246 | val = tr32(RCVLPC_STATS_ENABLE); | |
8247 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
8248 | tw32(RCVLPC_STATS_ENABLE, val); | |
8249 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
8250 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
1da177e4 LT |
8251 | val = tr32(RCVLPC_STATS_ENABLE); |
8252 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8253 | tw32(RCVLPC_STATS_ENABLE, val); | |
8254 | } else { | |
8255 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8256 | } | |
8257 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8258 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8259 | tw32(SNDDATAI_STATSCTRL, | |
8260 | (SNDDATAI_SCTRL_ENABLE | | |
8261 | SNDDATAI_SCTRL_FASTUPD)); | |
8262 | ||
8263 | /* Setup host coalescing engine. */ | |
8264 | tw32(HOSTCC_MODE, 0); | |
8265 | for (i = 0; i < 2000; i++) { | |
8266 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8267 | break; | |
8268 | udelay(10); | |
8269 | } | |
8270 | ||
d244c892 | 8271 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8272 | |
1da177e4 LT |
8273 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8274 | /* Status/statistics block address. See tg3_timer, | |
8275 | * the tg3_periodic_fetch_stats call there, and | |
8276 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8277 | */ | |
1da177e4 LT |
8278 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8279 | ((u64) tp->stats_mapping >> 32)); | |
8280 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8281 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8282 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8283 | |
1da177e4 | 8284 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8285 | |
8286 | /* Clear statistics and status block memory areas */ | |
8287 | for (i = NIC_SRAM_STATS_BLK; | |
8288 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8289 | i += sizeof(u32)) { | |
8290 | tg3_write_mem(tp, i, 0); | |
8291 | udelay(40); | |
8292 | } | |
1da177e4 LT |
8293 | } |
8294 | ||
8295 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8296 | ||
8297 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8298 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
8299 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8300 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
8301 | ||
f07e9af3 MC |
8302 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
8303 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | |
c94e3941 MC |
8304 | /* reset to prevent losing 1st rx packet intermittently */ |
8305 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8306 | udelay(10); | |
8307 | } | |
8308 | ||
3bda1258 | 8309 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
d2394e6b | 8310 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
8311 | else |
8312 | tp->mac_mode = 0; | |
8313 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
1da177e4 | 8314 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; |
e8f3f6ca | 8315 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
f07e9af3 | 8316 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
e8f3f6ca MC |
8317 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
8318 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8319 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8320 | udelay(40); | |
8321 | ||
314fba34 | 8322 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
9d26e213 | 8323 | * If TG3_FLG2_IS_NIC is zero, we should read the |
314fba34 MC |
8324 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8325 | * whether used as inputs or outputs, are set by boot code after | |
8326 | * reset. | |
8327 | */ | |
9d26e213 | 8328 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { |
314fba34 MC |
8329 | u32 gpio_mask; |
8330 | ||
9d26e213 MC |
8331 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8332 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8333 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8334 | |
8335 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8336 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8337 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8338 | ||
af36e6b6 MC |
8339 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8340 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8341 | ||
aaf84465 | 8342 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8343 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8344 | ||
8345 | /* GPIO1 must be driven high for eeprom write protect */ | |
9d26e213 MC |
8346 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) |
8347 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
8348 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8349 | } |
1da177e4 LT |
8350 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8351 | udelay(100); | |
8352 | ||
0583d521 MC |
8353 | if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && |
8354 | tp->irq_cnt > 1) { | |
baf8a94a MC |
8355 | val = tr32(MSGINT_MODE); |
8356 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8357 | tw32(MSGINT_MODE, val); | |
8358 | } | |
8359 | ||
1da177e4 LT |
8360 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8361 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
8362 | udelay(40); | |
8363 | } | |
8364 | ||
8365 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8366 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8367 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8368 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8369 | WDMAC_MODE_LNGREAD_ENAB); | |
8370 | ||
c5908939 MC |
8371 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
8372 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
29ea095f | 8373 | if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && |
1da177e4 LT |
8374 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8375 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8376 | /* nothing */ | |
8377 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
c5908939 | 8378 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { |
1da177e4 LT |
8379 | val |= WDMAC_MODE_RX_ACCEL; |
8380 | } | |
8381 | } | |
8382 | ||
d9ab5ad1 | 8383 | /* Enable host coalescing bug fix */ |
321d32a0 | 8384 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
f51f3562 | 8385 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8386 | |
788a035e MC |
8387 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8388 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8389 | ||
1da177e4 LT |
8390 | tw32_f(WDMAC_MODE, val); |
8391 | udelay(40); | |
8392 | ||
9974a356 MC |
8393 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
8394 | u16 pcix_cmd; | |
8395 | ||
8396 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8397 | &pcix_cmd); | |
1da177e4 | 8398 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8399 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8400 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8401 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8402 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8403 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8404 | } |
9974a356 MC |
8405 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8406 | pcix_cmd); | |
1da177e4 LT |
8407 | } |
8408 | ||
8409 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8410 | udelay(40); | |
8411 | ||
8412 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
8413 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8414 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
9936bcf6 MC |
8415 | |
8416 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8417 | tw32(SNDDATAC_MODE, | |
8418 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8419 | else | |
8420 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8421 | ||
1da177e4 LT |
8422 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8423 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
7cb32cf2 | 8424 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
de9f5230 | 8425 | if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) |
7cb32cf2 MC |
8426 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
8427 | tw32(RCVDBDI_MODE, val); | |
1da177e4 | 8428 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
1da177e4 LT |
8429 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
8430 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
baf8a94a | 8431 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
19cfaecc | 8432 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
baf8a94a MC |
8433 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8434 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8435 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8436 | ||
8437 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8438 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8439 | if (err) | |
8440 | return err; | |
8441 | } | |
8442 | ||
1da177e4 LT |
8443 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
8444 | err = tg3_load_tso_firmware(tp); | |
8445 | if (err) | |
8446 | return err; | |
8447 | } | |
1da177e4 LT |
8448 | |
8449 | tp->tx_mode = TX_MODE_ENABLE; | |
b1d05210 MC |
8450 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
8451 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
8452 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | |
1da177e4 LT |
8453 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
8454 | udelay(100); | |
8455 | ||
baf8a94a MC |
8456 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { |
8457 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8458 | u8 *ent = (u8 *)&val; | |
8459 | ||
8460 | /* Setup the indirection table */ | |
8461 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8462 | int idx = i % sizeof(val); | |
8463 | ||
5efeeea1 | 8464 | ent[idx] = i % (tp->irq_cnt - 1); |
baf8a94a MC |
8465 | if (idx == sizeof(val) - 1) { |
8466 | tw32(reg, val); | |
8467 | reg += 4; | |
8468 | } | |
8469 | } | |
8470 | ||
8471 | /* Setup the "secret" hash key. */ | |
8472 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8473 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8474 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8475 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8476 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8477 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8478 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8479 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8480 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8481 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8482 | } | |
8483 | ||
1da177e4 | 8484 | tp->rx_mode = RX_MODE_ENABLE; |
321d32a0 | 8485 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
af36e6b6 MC |
8486 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8487 | ||
baf8a94a MC |
8488 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
8489 | tp->rx_mode |= RX_MODE_RSS_ENABLE | | |
8490 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8491 | RX_MODE_RSS_IPV6_HASH_EN | | |
8492 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8493 | RX_MODE_RSS_IPV4_HASH_EN | | |
8494 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8495 | ||
1da177e4 LT |
8496 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8497 | udelay(10); | |
8498 | ||
1da177e4 LT |
8499 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8500 | ||
8501 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
f07e9af3 | 8502 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 LT |
8503 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8504 | udelay(10); | |
8505 | } | |
8506 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8507 | udelay(10); | |
8508 | ||
f07e9af3 | 8509 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
1da177e4 | 8510 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
f07e9af3 | 8511 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
1da177e4 LT |
8512 | /* Set drive transmission level to 1.2V */ |
8513 | /* only if the signal pre-emphasis bit is not set */ | |
8514 | val = tr32(MAC_SERDES_CFG); | |
8515 | val &= 0xfffff000; | |
8516 | val |= 0x880; | |
8517 | tw32(MAC_SERDES_CFG, val); | |
8518 | } | |
8519 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8520 | tw32(MAC_SERDES_CFG, 0x616000); | |
8521 | } | |
8522 | ||
8523 | /* Prevent chip from dropping frames when flow control | |
8524 | * is enabled. | |
8525 | */ | |
666bc831 MC |
8526 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8527 | val = 1; | |
8528 | else | |
8529 | val = 2; | |
8530 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
8531 | |
8532 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
f07e9af3 | 8533 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
1da177e4 LT |
8534 | /* Use hardware link auto-negotiation */ |
8535 | tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; | |
8536 | } | |
8537 | ||
f07e9af3 | 8538 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
d4d2c558 MC |
8539 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { |
8540 | u32 tmp; | |
8541 | ||
8542 | tmp = tr32(SERDES_RX_CTRL); | |
8543 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8544 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8545 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8546 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8547 | } | |
8548 | ||
dd477003 | 8549 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
80096068 MC |
8550 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
8551 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | |
dd477003 MC |
8552 | tp->link_config.speed = tp->link_config.orig_speed; |
8553 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8554 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8555 | } | |
1da177e4 | 8556 | |
dd477003 MC |
8557 | err = tg3_setup_phy(tp, 0); |
8558 | if (err) | |
8559 | return err; | |
1da177e4 | 8560 | |
f07e9af3 MC |
8561 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
8562 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { | |
dd477003 MC |
8563 | u32 tmp; |
8564 | ||
8565 | /* Clear CRC stats. */ | |
8566 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8567 | tg3_writephy(tp, MII_TG3_TEST1, | |
8568 | tmp | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 8569 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
dd477003 | 8570 | } |
1da177e4 LT |
8571 | } |
8572 | } | |
8573 | ||
8574 | __tg3_set_rx_mode(tp->dev); | |
8575 | ||
8576 | /* Initialize receive rules. */ | |
8577 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8578 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8579 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8580 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8581 | ||
4cf78e4f | 8582 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
a4e2b347 | 8583 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
1da177e4 LT |
8584 | limit = 8; |
8585 | else | |
8586 | limit = 16; | |
8587 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
8588 | limit -= 4; | |
8589 | switch (limit) { | |
8590 | case 16: | |
8591 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8592 | case 15: | |
8593 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8594 | case 14: | |
8595 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8596 | case 13: | |
8597 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8598 | case 12: | |
8599 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8600 | case 11: | |
8601 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8602 | case 10: | |
8603 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8604 | case 9: | |
8605 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8606 | case 8: | |
8607 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8608 | case 7: | |
8609 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8610 | case 6: | |
8611 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8612 | case 5: | |
8613 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8614 | case 4: | |
8615 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8616 | case 3: | |
8617 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8618 | case 2: | |
8619 | case 1: | |
8620 | ||
8621 | default: | |
8622 | break; | |
855e1111 | 8623 | } |
1da177e4 | 8624 | |
9ce768ea MC |
8625 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
8626 | /* Write our heartbeat update interval to APE. */ | |
8627 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8628 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 8629 | |
1da177e4 LT |
8630 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
8631 | ||
1da177e4 LT |
8632 | return 0; |
8633 | } | |
8634 | ||
8635 | /* Called at device open time to get the chip ready for | |
8636 | * packet processing. Invoked with tp->lock held. | |
8637 | */ | |
8e7a22e3 | 8638 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 8639 | { |
1da177e4 LT |
8640 | tg3_switch_clocks(tp); |
8641 | ||
8642 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8643 | ||
2f751b67 | 8644 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
8645 | } |
8646 | ||
8647 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8648 | do { u32 __val = tr32(REG); \ | |
8649 | (PSTAT)->low += __val; \ | |
8650 | if ((PSTAT)->low < __val) \ | |
8651 | (PSTAT)->high += 1; \ | |
8652 | } while (0) | |
8653 | ||
8654 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8655 | { | |
8656 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8657 | ||
8658 | if (!netif_carrier_ok(tp->dev)) | |
8659 | return; | |
8660 | ||
8661 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
8662 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
8663 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
8664 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
8665 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
8666 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
8667 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
8668 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
8669 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
8670 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
8671 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
8672 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
8673 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
8674 | ||
8675 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
8676 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
8677 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
8678 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
8679 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
8680 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
8681 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
8682 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
8683 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
8684 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
8685 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
8686 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
8687 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
8688 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
8689 | |
8690 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
8691 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
8692 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); | |
1da177e4 LT |
8693 | } |
8694 | ||
8695 | static void tg3_timer(unsigned long __opaque) | |
8696 | { | |
8697 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 8698 | |
f475f163 MC |
8699 | if (tp->irq_sync) |
8700 | goto restart_timer; | |
8701 | ||
f47c11ee | 8702 | spin_lock(&tp->lock); |
1da177e4 | 8703 | |
fac9b83e DM |
8704 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { |
8705 | /* All of this garbage is because when using non-tagged | |
8706 | * IRQ status the mailbox/status_block protocol the chip | |
8707 | * uses with the cpu is race prone. | |
8708 | */ | |
898a56f8 | 8709 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
8710 | tw32(GRC_LOCAL_CTRL, |
8711 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
8712 | } else { | |
8713 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 8714 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 8715 | } |
1da177e4 | 8716 | |
fac9b83e DM |
8717 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
8718 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | |
f47c11ee | 8719 | spin_unlock(&tp->lock); |
fac9b83e DM |
8720 | schedule_work(&tp->reset_task); |
8721 | return; | |
8722 | } | |
1da177e4 LT |
8723 | } |
8724 | ||
1da177e4 LT |
8725 | /* This part only runs once per second. */ |
8726 | if (!--tp->timer_counter) { | |
fac9b83e DM |
8727 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
8728 | tg3_periodic_fetch_stats(tp); | |
8729 | ||
52b02d04 MC |
8730 | if (tp->setlpicnt && !--tp->setlpicnt) { |
8731 | u32 val = tr32(TG3_CPMU_EEE_MODE); | |
8732 | tw32(TG3_CPMU_EEE_MODE, | |
8733 | val | TG3_CPMU_EEEMD_LPI_ENABLE); | |
8734 | } | |
8735 | ||
1da177e4 LT |
8736 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
8737 | u32 mac_stat; | |
8738 | int phy_event; | |
8739 | ||
8740 | mac_stat = tr32(MAC_STATUS); | |
8741 | ||
8742 | phy_event = 0; | |
f07e9af3 | 8743 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
1da177e4 LT |
8744 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
8745 | phy_event = 1; | |
8746 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
8747 | phy_event = 1; | |
8748 | ||
8749 | if (phy_event) | |
8750 | tg3_setup_phy(tp, 0); | |
8751 | } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { | |
8752 | u32 mac_stat = tr32(MAC_STATUS); | |
8753 | int need_setup = 0; | |
8754 | ||
8755 | if (netif_carrier_ok(tp->dev) && | |
8756 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
8757 | need_setup = 1; | |
8758 | } | |
be98da6a | 8759 | if (!netif_carrier_ok(tp->dev) && |
1da177e4 LT |
8760 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
8761 | MAC_STATUS_SIGNAL_DET))) { | |
8762 | need_setup = 1; | |
8763 | } | |
8764 | if (need_setup) { | |
3d3ebe74 MC |
8765 | if (!tp->serdes_counter) { |
8766 | tw32_f(MAC_MODE, | |
8767 | (tp->mac_mode & | |
8768 | ~MAC_MODE_PORT_MODE_MASK)); | |
8769 | udelay(40); | |
8770 | tw32_f(MAC_MODE, tp->mac_mode); | |
8771 | udelay(40); | |
8772 | } | |
1da177e4 LT |
8773 | tg3_setup_phy(tp, 0); |
8774 | } | |
f07e9af3 | 8775 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
2138c002 | 8776 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
747e8f8b | 8777 | tg3_serdes_parallel_detect(tp); |
57d8b880 | 8778 | } |
1da177e4 LT |
8779 | |
8780 | tp->timer_counter = tp->timer_multiplier; | |
8781 | } | |
8782 | ||
130b8e4d MC |
8783 | /* Heartbeat is only sent once every 2 seconds. |
8784 | * | |
8785 | * The heartbeat is to tell the ASF firmware that the host | |
8786 | * driver is still alive. In the event that the OS crashes, | |
8787 | * ASF needs to reset the hardware to free up the FIFO space | |
8788 | * that may be filled with rx packets destined for the host. | |
8789 | * If the FIFO is full, ASF will no longer function properly. | |
8790 | * | |
8791 | * Unintended resets have been reported on real time kernels | |
8792 | * where the timer doesn't run on time. Netpoll will also have | |
8793 | * same problem. | |
8794 | * | |
8795 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
8796 | * to check the ring condition when the heartbeat is expiring | |
8797 | * before doing the reset. This will prevent most unintended | |
8798 | * resets. | |
8799 | */ | |
1da177e4 | 8800 | if (!--tp->asf_counter) { |
bc7959b2 MC |
8801 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
8802 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
8803 | tg3_wait_for_event_ack(tp); |
8804 | ||
bbadf503 | 8805 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 8806 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 8807 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
8808 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
8809 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
8810 | |
8811 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
8812 | } |
8813 | tp->asf_counter = tp->asf_multiplier; | |
8814 | } | |
8815 | ||
f47c11ee | 8816 | spin_unlock(&tp->lock); |
1da177e4 | 8817 | |
f475f163 | 8818 | restart_timer: |
1da177e4 LT |
8819 | tp->timer.expires = jiffies + tp->timer_offset; |
8820 | add_timer(&tp->timer); | |
8821 | } | |
8822 | ||
4f125f42 | 8823 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 8824 | { |
7d12e780 | 8825 | irq_handler_t fn; |
fcfa0a32 | 8826 | unsigned long flags; |
4f125f42 MC |
8827 | char *name; |
8828 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
8829 | ||
8830 | if (tp->irq_cnt == 1) | |
8831 | name = tp->dev->name; | |
8832 | else { | |
8833 | name = &tnapi->irq_lbl[0]; | |
8834 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
8835 | name[IFNAMSIZ-1] = 0; | |
8836 | } | |
fcfa0a32 | 8837 | |
679563f4 | 8838 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { |
fcfa0a32 MC |
8839 | fn = tg3_msi; |
8840 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
8841 | fn = tg3_msi_1shot; | |
ab392d2d | 8842 | flags = 0; |
fcfa0a32 MC |
8843 | } else { |
8844 | fn = tg3_interrupt; | |
8845 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
8846 | fn = tg3_interrupt_tagged; | |
ab392d2d | 8847 | flags = IRQF_SHARED; |
fcfa0a32 | 8848 | } |
4f125f42 MC |
8849 | |
8850 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
8851 | } |
8852 | ||
7938109f MC |
8853 | static int tg3_test_interrupt(struct tg3 *tp) |
8854 | { | |
09943a18 | 8855 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 8856 | struct net_device *dev = tp->dev; |
b16250e3 | 8857 | int err, i, intr_ok = 0; |
f6eb9b1f | 8858 | u32 val; |
7938109f | 8859 | |
d4bc3927 MC |
8860 | if (!netif_running(dev)) |
8861 | return -ENODEV; | |
8862 | ||
7938109f MC |
8863 | tg3_disable_ints(tp); |
8864 | ||
4f125f42 | 8865 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 8866 | |
f6eb9b1f MC |
8867 | /* |
8868 | * Turn off MSI one shot mode. Otherwise this test has no | |
8869 | * observable way to know whether the interrupt was delivered. | |
8870 | */ | |
1407deb1 | 8871 | if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
f6eb9b1f MC |
8872 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
8873 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; | |
8874 | tw32(MSGINT_MODE, val); | |
8875 | } | |
8876 | ||
4f125f42 | 8877 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 8878 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
8879 | if (err) |
8880 | return err; | |
8881 | ||
898a56f8 | 8882 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
8883 | tg3_enable_ints(tp); |
8884 | ||
8885 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 8886 | tnapi->coal_now); |
7938109f MC |
8887 | |
8888 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
8889 | u32 int_mbox, misc_host_ctrl; |
8890 | ||
898a56f8 | 8891 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
8892 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
8893 | ||
8894 | if ((int_mbox != 0) || | |
8895 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
8896 | intr_ok = 1; | |
7938109f | 8897 | break; |
b16250e3 MC |
8898 | } |
8899 | ||
7938109f MC |
8900 | msleep(10); |
8901 | } | |
8902 | ||
8903 | tg3_disable_ints(tp); | |
8904 | ||
4f125f42 | 8905 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 8906 | |
4f125f42 | 8907 | err = tg3_request_irq(tp, 0); |
7938109f MC |
8908 | |
8909 | if (err) | |
8910 | return err; | |
8911 | ||
f6eb9b1f MC |
8912 | if (intr_ok) { |
8913 | /* Reenable MSI one shot mode. */ | |
1407deb1 | 8914 | if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
f6eb9b1f MC |
8915 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
8916 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; | |
8917 | tw32(MSGINT_MODE, val); | |
8918 | } | |
7938109f | 8919 | return 0; |
f6eb9b1f | 8920 | } |
7938109f MC |
8921 | |
8922 | return -EIO; | |
8923 | } | |
8924 | ||
8925 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
8926 | * successfully restored | |
8927 | */ | |
8928 | static int tg3_test_msi(struct tg3 *tp) | |
8929 | { | |
7938109f MC |
8930 | int err; |
8931 | u16 pci_cmd; | |
8932 | ||
8933 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) | |
8934 | return 0; | |
8935 | ||
8936 | /* Turn off SERR reporting in case MSI terminates with Master | |
8937 | * Abort. | |
8938 | */ | |
8939 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
8940 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
8941 | pci_cmd & ~PCI_COMMAND_SERR); | |
8942 | ||
8943 | err = tg3_test_interrupt(tp); | |
8944 | ||
8945 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
8946 | ||
8947 | if (!err) | |
8948 | return 0; | |
8949 | ||
8950 | /* other failures */ | |
8951 | if (err != -EIO) | |
8952 | return err; | |
8953 | ||
8954 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
8955 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
8956 | "to INTx mode. Please report this failure to the PCI " | |
8957 | "maintainer and include system chipset information\n"); | |
7938109f | 8958 | |
4f125f42 | 8959 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 8960 | |
7938109f MC |
8961 | pci_disable_msi(tp->pdev); |
8962 | ||
8963 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
dc8bf1b1 | 8964 | tp->napi[0].irq_vec = tp->pdev->irq; |
7938109f | 8965 | |
4f125f42 | 8966 | err = tg3_request_irq(tp, 0); |
7938109f MC |
8967 | if (err) |
8968 | return err; | |
8969 | ||
8970 | /* Need to reset the chip because the MSI cycle may have terminated | |
8971 | * with Master Abort. | |
8972 | */ | |
f47c11ee | 8973 | tg3_full_lock(tp, 1); |
7938109f | 8974 | |
944d980e | 8975 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 8976 | err = tg3_init_hw(tp, 1); |
7938109f | 8977 | |
f47c11ee | 8978 | tg3_full_unlock(tp); |
7938109f MC |
8979 | |
8980 | if (err) | |
4f125f42 | 8981 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
8982 | |
8983 | return err; | |
8984 | } | |
8985 | ||
9e9fd12d MC |
8986 | static int tg3_request_firmware(struct tg3 *tp) |
8987 | { | |
8988 | const __be32 *fw_data; | |
8989 | ||
8990 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
8991 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
8992 | tp->fw_needed); | |
9e9fd12d MC |
8993 | return -ENOENT; |
8994 | } | |
8995 | ||
8996 | fw_data = (void *)tp->fw->data; | |
8997 | ||
8998 | /* Firmware blob starts with version numbers, followed by | |
8999 | * start address and _full_ length including BSS sections | |
9000 | * (which must be longer than the actual data, of course | |
9001 | */ | |
9002 | ||
9003 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
9004 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
9005 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
9006 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
9007 | release_firmware(tp->fw); |
9008 | tp->fw = NULL; | |
9009 | return -EINVAL; | |
9010 | } | |
9011 | ||
9012 | /* We no longer need firmware; we have it. */ | |
9013 | tp->fw_needed = NULL; | |
9014 | return 0; | |
9015 | } | |
9016 | ||
679563f4 MC |
9017 | static bool tg3_enable_msix(struct tg3 *tp) |
9018 | { | |
9019 | int i, rc, cpus = num_online_cpus(); | |
9020 | struct msix_entry msix_ent[tp->irq_max]; | |
9021 | ||
9022 | if (cpus == 1) | |
9023 | /* Just fallback to the simpler MSI mode. */ | |
9024 | return false; | |
9025 | ||
9026 | /* | |
9027 | * We want as many rx rings enabled as there are cpus. | |
9028 | * The first MSIX vector only deals with link interrupts, etc, | |
9029 | * so we add one to the number of vectors we are requesting. | |
9030 | */ | |
9031 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
9032 | ||
9033 | for (i = 0; i < tp->irq_max; i++) { | |
9034 | msix_ent[i].entry = i; | |
9035 | msix_ent[i].vector = 0; | |
9036 | } | |
9037 | ||
9038 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
2430b031 MC |
9039 | if (rc < 0) { |
9040 | return false; | |
9041 | } else if (rc != 0) { | |
679563f4 MC |
9042 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
9043 | return false; | |
05dbe005 JP |
9044 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
9045 | tp->irq_cnt, rc); | |
679563f4 MC |
9046 | tp->irq_cnt = rc; |
9047 | } | |
9048 | ||
9049 | for (i = 0; i < tp->irq_max; i++) | |
9050 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
9051 | ||
2ddaad39 BH |
9052 | netif_set_real_num_tx_queues(tp->dev, 1); |
9053 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; | |
9054 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { | |
9055 | pci_disable_msix(tp->pdev); | |
9056 | return false; | |
9057 | } | |
b92b9040 MC |
9058 | |
9059 | if (tp->irq_cnt > 1) { | |
2430b031 | 9060 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS; |
d78b59f5 MC |
9061 | |
9062 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | |
9063 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | |
b92b9040 MC |
9064 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS; |
9065 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); | |
9066 | } | |
9067 | } | |
2430b031 | 9068 | |
679563f4 MC |
9069 | return true; |
9070 | } | |
9071 | ||
07b0173c MC |
9072 | static void tg3_ints_init(struct tg3 *tp) |
9073 | { | |
679563f4 MC |
9074 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) && |
9075 | !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
07b0173c MC |
9076 | /* All MSI supporting chips should support tagged |
9077 | * status. Assert that this is the case. | |
9078 | */ | |
5129c3a3 MC |
9079 | netdev_warn(tp->dev, |
9080 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 9081 | goto defcfg; |
07b0173c | 9082 | } |
4f125f42 | 9083 | |
679563f4 MC |
9084 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp)) |
9085 | tp->tg3_flags2 |= TG3_FLG2_USING_MSIX; | |
9086 | else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) && | |
9087 | pci_enable_msi(tp->pdev) == 0) | |
9088 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | |
9089 | ||
9090 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { | |
9091 | u32 msi_mode = tr32(MSGINT_MODE); | |
0583d521 MC |
9092 | if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && |
9093 | tp->irq_cnt > 1) | |
baf8a94a | 9094 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
679563f4 MC |
9095 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
9096 | } | |
9097 | defcfg: | |
9098 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { | |
9099 | tp->irq_cnt = 1; | |
9100 | tp->napi[0].irq_vec = tp->pdev->irq; | |
2ddaad39 | 9101 | netif_set_real_num_tx_queues(tp->dev, 1); |
85407885 | 9102 | netif_set_real_num_rx_queues(tp->dev, 1); |
679563f4 | 9103 | } |
07b0173c MC |
9104 | } |
9105 | ||
9106 | static void tg3_ints_fini(struct tg3 *tp) | |
9107 | { | |
679563f4 MC |
9108 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) |
9109 | pci_disable_msix(tp->pdev); | |
9110 | else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | |
9111 | pci_disable_msi(tp->pdev); | |
9112 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX; | |
774ee752 | 9113 | tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS); |
07b0173c MC |
9114 | } |
9115 | ||
1da177e4 LT |
9116 | static int tg3_open(struct net_device *dev) |
9117 | { | |
9118 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 9119 | int i, err; |
1da177e4 | 9120 | |
9e9fd12d MC |
9121 | if (tp->fw_needed) { |
9122 | err = tg3_request_firmware(tp); | |
9123 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
9124 | if (err) | |
9125 | return err; | |
9126 | } else if (err) { | |
05dbe005 | 9127 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
9e9fd12d MC |
9128 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
9129 | } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
05dbe005 | 9130 | netdev_notice(tp->dev, "TSO capability restored\n"); |
9e9fd12d MC |
9131 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
9132 | } | |
9133 | } | |
9134 | ||
c49a1561 MC |
9135 | netif_carrier_off(tp->dev); |
9136 | ||
c866b7ea | 9137 | err = tg3_power_up(tp); |
2f751b67 | 9138 | if (err) |
bc1c7567 | 9139 | return err; |
2f751b67 MC |
9140 | |
9141 | tg3_full_lock(tp, 0); | |
bc1c7567 | 9142 | |
1da177e4 LT |
9143 | tg3_disable_ints(tp); |
9144 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
9145 | ||
f47c11ee | 9146 | tg3_full_unlock(tp); |
1da177e4 | 9147 | |
679563f4 MC |
9148 | /* |
9149 | * Setup interrupts first so we know how | |
9150 | * many NAPI resources to allocate | |
9151 | */ | |
9152 | tg3_ints_init(tp); | |
9153 | ||
1da177e4 LT |
9154 | /* The placement of this call is tied |
9155 | * to the setup and use of Host TX descriptors. | |
9156 | */ | |
9157 | err = tg3_alloc_consistent(tp); | |
9158 | if (err) | |
679563f4 | 9159 | goto err_out1; |
88b06bc2 | 9160 | |
66cfd1bd MC |
9161 | tg3_napi_init(tp); |
9162 | ||
fed97810 | 9163 | tg3_napi_enable(tp); |
1da177e4 | 9164 | |
4f125f42 MC |
9165 | for (i = 0; i < tp->irq_cnt; i++) { |
9166 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9167 | err = tg3_request_irq(tp, i); | |
9168 | if (err) { | |
9169 | for (i--; i >= 0; i--) | |
9170 | free_irq(tnapi->irq_vec, tnapi); | |
9171 | break; | |
9172 | } | |
9173 | } | |
1da177e4 | 9174 | |
07b0173c | 9175 | if (err) |
679563f4 | 9176 | goto err_out2; |
bea3348e | 9177 | |
f47c11ee | 9178 | tg3_full_lock(tp, 0); |
1da177e4 | 9179 | |
8e7a22e3 | 9180 | err = tg3_init_hw(tp, 1); |
1da177e4 | 9181 | if (err) { |
944d980e | 9182 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
9183 | tg3_free_rings(tp); |
9184 | } else { | |
fac9b83e DM |
9185 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) |
9186 | tp->timer_offset = HZ; | |
9187 | else | |
9188 | tp->timer_offset = HZ / 10; | |
9189 | ||
9190 | BUG_ON(tp->timer_offset > HZ); | |
9191 | tp->timer_counter = tp->timer_multiplier = | |
9192 | (HZ / tp->timer_offset); | |
9193 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 9194 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
9195 | |
9196 | init_timer(&tp->timer); | |
9197 | tp->timer.expires = jiffies + tp->timer_offset; | |
9198 | tp->timer.data = (unsigned long) tp; | |
9199 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
9200 | } |
9201 | ||
f47c11ee | 9202 | tg3_full_unlock(tp); |
1da177e4 | 9203 | |
07b0173c | 9204 | if (err) |
679563f4 | 9205 | goto err_out3; |
1da177e4 | 9206 | |
7938109f MC |
9207 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { |
9208 | err = tg3_test_msi(tp); | |
fac9b83e | 9209 | |
7938109f | 9210 | if (err) { |
f47c11ee | 9211 | tg3_full_lock(tp, 0); |
944d980e | 9212 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 9213 | tg3_free_rings(tp); |
f47c11ee | 9214 | tg3_full_unlock(tp); |
7938109f | 9215 | |
679563f4 | 9216 | goto err_out2; |
7938109f | 9217 | } |
fcfa0a32 | 9218 | |
1407deb1 | 9219 | if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
c885e824 | 9220 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
f6eb9b1f | 9221 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
fcfa0a32 | 9222 | |
f6eb9b1f MC |
9223 | tw32(PCIE_TRANSACTION_CFG, |
9224 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 9225 | } |
7938109f MC |
9226 | } |
9227 | ||
b02fd9e3 MC |
9228 | tg3_phy_start(tp); |
9229 | ||
f47c11ee | 9230 | tg3_full_lock(tp, 0); |
1da177e4 | 9231 | |
7938109f MC |
9232 | add_timer(&tp->timer); |
9233 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
1da177e4 LT |
9234 | tg3_enable_ints(tp); |
9235 | ||
f47c11ee | 9236 | tg3_full_unlock(tp); |
1da177e4 | 9237 | |
fe5f5787 | 9238 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
9239 | |
9240 | return 0; | |
07b0173c | 9241 | |
679563f4 | 9242 | err_out3: |
4f125f42 MC |
9243 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9244 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9245 | free_irq(tnapi->irq_vec, tnapi); | |
9246 | } | |
07b0173c | 9247 | |
679563f4 | 9248 | err_out2: |
fed97810 | 9249 | tg3_napi_disable(tp); |
66cfd1bd | 9250 | tg3_napi_fini(tp); |
07b0173c | 9251 | tg3_free_consistent(tp); |
679563f4 MC |
9252 | |
9253 | err_out1: | |
9254 | tg3_ints_fini(tp); | |
07b0173c | 9255 | return err; |
1da177e4 LT |
9256 | } |
9257 | ||
511d2224 ED |
9258 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
9259 | struct rtnl_link_stats64 *); | |
1da177e4 LT |
9260 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); |
9261 | ||
9262 | static int tg3_close(struct net_device *dev) | |
9263 | { | |
4f125f42 | 9264 | int i; |
1da177e4 LT |
9265 | struct tg3 *tp = netdev_priv(dev); |
9266 | ||
fed97810 | 9267 | tg3_napi_disable(tp); |
28e53bdd | 9268 | cancel_work_sync(&tp->reset_task); |
7faa006f | 9269 | |
fe5f5787 | 9270 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
9271 | |
9272 | del_timer_sync(&tp->timer); | |
9273 | ||
24bb4fb6 MC |
9274 | tg3_phy_stop(tp); |
9275 | ||
f47c11ee | 9276 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9277 | |
9278 | tg3_disable_ints(tp); | |
9279 | ||
944d980e | 9280 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9281 | tg3_free_rings(tp); |
5cf64b8a | 9282 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
1da177e4 | 9283 | |
f47c11ee | 9284 | tg3_full_unlock(tp); |
1da177e4 | 9285 | |
4f125f42 MC |
9286 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9287 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9288 | free_irq(tnapi->irq_vec, tnapi); | |
9289 | } | |
07b0173c MC |
9290 | |
9291 | tg3_ints_fini(tp); | |
1da177e4 | 9292 | |
511d2224 ED |
9293 | tg3_get_stats64(tp->dev, &tp->net_stats_prev); |
9294 | ||
1da177e4 LT |
9295 | memcpy(&tp->estats_prev, tg3_get_estats(tp), |
9296 | sizeof(tp->estats_prev)); | |
9297 | ||
66cfd1bd MC |
9298 | tg3_napi_fini(tp); |
9299 | ||
1da177e4 LT |
9300 | tg3_free_consistent(tp); |
9301 | ||
c866b7ea | 9302 | tg3_power_down(tp); |
bc1c7567 MC |
9303 | |
9304 | netif_carrier_off(tp->dev); | |
9305 | ||
1da177e4 LT |
9306 | return 0; |
9307 | } | |
9308 | ||
511d2224 | 9309 | static inline u64 get_stat64(tg3_stat64_t *val) |
816f8b86 SB |
9310 | { |
9311 | return ((u64)val->high << 32) | ((u64)val->low); | |
9312 | } | |
9313 | ||
511d2224 | 9314 | static u64 calc_crc_errors(struct tg3 *tp) |
1da177e4 LT |
9315 | { |
9316 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9317 | ||
f07e9af3 | 9318 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
1da177e4 LT |
9319 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
9320 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9321 | u32 val; |
9322 | ||
f47c11ee | 9323 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9324 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9325 | tg3_writephy(tp, MII_TG3_TEST1, | |
9326 | val | MII_TG3_TEST1_CRC_EN); | |
f08aa1a8 | 9327 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
1da177e4 LT |
9328 | } else |
9329 | val = 0; | |
f47c11ee | 9330 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9331 | |
9332 | tp->phy_crc_errors += val; | |
9333 | ||
9334 | return tp->phy_crc_errors; | |
9335 | } | |
9336 | ||
9337 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9338 | } | |
9339 | ||
9340 | #define ESTAT_ADD(member) \ | |
9341 | estats->member = old_estats->member + \ | |
511d2224 | 9342 | get_stat64(&hw_stats->member) |
1da177e4 LT |
9343 | |
9344 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9345 | { | |
9346 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9347 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9348 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9349 | ||
9350 | if (!hw_stats) | |
9351 | return old_estats; | |
9352 | ||
9353 | ESTAT_ADD(rx_octets); | |
9354 | ESTAT_ADD(rx_fragments); | |
9355 | ESTAT_ADD(rx_ucast_packets); | |
9356 | ESTAT_ADD(rx_mcast_packets); | |
9357 | ESTAT_ADD(rx_bcast_packets); | |
9358 | ESTAT_ADD(rx_fcs_errors); | |
9359 | ESTAT_ADD(rx_align_errors); | |
9360 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9361 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9362 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9363 | ESTAT_ADD(rx_xoff_entered); | |
9364 | ESTAT_ADD(rx_frame_too_long_errors); | |
9365 | ESTAT_ADD(rx_jabbers); | |
9366 | ESTAT_ADD(rx_undersize_packets); | |
9367 | ESTAT_ADD(rx_in_length_errors); | |
9368 | ESTAT_ADD(rx_out_length_errors); | |
9369 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9370 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9371 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9372 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9373 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9374 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9375 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9376 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9377 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9378 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9379 | ||
9380 | ESTAT_ADD(tx_octets); | |
9381 | ESTAT_ADD(tx_collisions); | |
9382 | ESTAT_ADD(tx_xon_sent); | |
9383 | ESTAT_ADD(tx_xoff_sent); | |
9384 | ESTAT_ADD(tx_flow_control); | |
9385 | ESTAT_ADD(tx_mac_errors); | |
9386 | ESTAT_ADD(tx_single_collisions); | |
9387 | ESTAT_ADD(tx_mult_collisions); | |
9388 | ESTAT_ADD(tx_deferred); | |
9389 | ESTAT_ADD(tx_excessive_collisions); | |
9390 | ESTAT_ADD(tx_late_collisions); | |
9391 | ESTAT_ADD(tx_collide_2times); | |
9392 | ESTAT_ADD(tx_collide_3times); | |
9393 | ESTAT_ADD(tx_collide_4times); | |
9394 | ESTAT_ADD(tx_collide_5times); | |
9395 | ESTAT_ADD(tx_collide_6times); | |
9396 | ESTAT_ADD(tx_collide_7times); | |
9397 | ESTAT_ADD(tx_collide_8times); | |
9398 | ESTAT_ADD(tx_collide_9times); | |
9399 | ESTAT_ADD(tx_collide_10times); | |
9400 | ESTAT_ADD(tx_collide_11times); | |
9401 | ESTAT_ADD(tx_collide_12times); | |
9402 | ESTAT_ADD(tx_collide_13times); | |
9403 | ESTAT_ADD(tx_collide_14times); | |
9404 | ESTAT_ADD(tx_collide_15times); | |
9405 | ESTAT_ADD(tx_ucast_packets); | |
9406 | ESTAT_ADD(tx_mcast_packets); | |
9407 | ESTAT_ADD(tx_bcast_packets); | |
9408 | ESTAT_ADD(tx_carrier_sense_errors); | |
9409 | ESTAT_ADD(tx_discards); | |
9410 | ESTAT_ADD(tx_errors); | |
9411 | ||
9412 | ESTAT_ADD(dma_writeq_full); | |
9413 | ESTAT_ADD(dma_write_prioq_full); | |
9414 | ESTAT_ADD(rxbds_empty); | |
9415 | ESTAT_ADD(rx_discards); | |
9416 | ESTAT_ADD(rx_errors); | |
9417 | ESTAT_ADD(rx_threshold_hit); | |
9418 | ||
9419 | ESTAT_ADD(dma_readq_full); | |
9420 | ESTAT_ADD(dma_read_prioq_full); | |
9421 | ESTAT_ADD(tx_comp_queue_full); | |
9422 | ||
9423 | ESTAT_ADD(ring_set_send_prod_index); | |
9424 | ESTAT_ADD(ring_status_update); | |
9425 | ESTAT_ADD(nic_irqs); | |
9426 | ESTAT_ADD(nic_avoided_irqs); | |
9427 | ESTAT_ADD(nic_tx_threshold_hit); | |
9428 | ||
9429 | return estats; | |
9430 | } | |
9431 | ||
511d2224 ED |
9432 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
9433 | struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
9434 | { |
9435 | struct tg3 *tp = netdev_priv(dev); | |
511d2224 | 9436 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
1da177e4 LT |
9437 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
9438 | ||
9439 | if (!hw_stats) | |
9440 | return old_stats; | |
9441 | ||
9442 | stats->rx_packets = old_stats->rx_packets + | |
9443 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9444 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9445 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9446 | |
1da177e4 LT |
9447 | stats->tx_packets = old_stats->tx_packets + |
9448 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9449 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9450 | get_stat64(&hw_stats->tx_bcast_packets); | |
9451 | ||
9452 | stats->rx_bytes = old_stats->rx_bytes + | |
9453 | get_stat64(&hw_stats->rx_octets); | |
9454 | stats->tx_bytes = old_stats->tx_bytes + | |
9455 | get_stat64(&hw_stats->tx_octets); | |
9456 | ||
9457 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9458 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9459 | stats->tx_errors = old_stats->tx_errors + |
9460 | get_stat64(&hw_stats->tx_errors) + | |
9461 | get_stat64(&hw_stats->tx_mac_errors) + | |
9462 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9463 | get_stat64(&hw_stats->tx_discards); | |
9464 | ||
9465 | stats->multicast = old_stats->multicast + | |
9466 | get_stat64(&hw_stats->rx_mcast_packets); | |
9467 | stats->collisions = old_stats->collisions + | |
9468 | get_stat64(&hw_stats->tx_collisions); | |
9469 | ||
9470 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9471 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9472 | get_stat64(&hw_stats->rx_undersize_packets); | |
9473 | ||
9474 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9475 | get_stat64(&hw_stats->rxbds_empty); | |
9476 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9477 | get_stat64(&hw_stats->rx_align_errors); | |
9478 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9479 | get_stat64(&hw_stats->tx_discards); | |
9480 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9481 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9482 | ||
9483 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9484 | calc_crc_errors(tp); | |
9485 | ||
4f63b877 JL |
9486 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
9487 | get_stat64(&hw_stats->rx_discards); | |
9488 | ||
b0057c51 ED |
9489 | stats->rx_dropped = tp->rx_dropped; |
9490 | ||
1da177e4 LT |
9491 | return stats; |
9492 | } | |
9493 | ||
9494 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9495 | { | |
9496 | u32 reg; | |
9497 | u32 tmp; | |
9498 | int j, k; | |
9499 | ||
9500 | reg = 0xffffffff; | |
9501 | ||
9502 | for (j = 0; j < len; j++) { | |
9503 | reg ^= buf[j]; | |
9504 | ||
9505 | for (k = 0; k < 8; k++) { | |
9506 | tmp = reg & 0x01; | |
9507 | ||
9508 | reg >>= 1; | |
9509 | ||
859a5887 | 9510 | if (tmp) |
1da177e4 | 9511 | reg ^= 0xedb88320; |
1da177e4 LT |
9512 | } |
9513 | } | |
9514 | ||
9515 | return ~reg; | |
9516 | } | |
9517 | ||
9518 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9519 | { | |
9520 | /* accept or reject all multicast frames */ | |
9521 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9522 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9523 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9524 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9525 | } | |
9526 | ||
9527 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9528 | { | |
9529 | struct tg3 *tp = netdev_priv(dev); | |
9530 | u32 rx_mode; | |
9531 | ||
9532 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9533 | RX_MODE_KEEP_VLAN_TAG); | |
9534 | ||
bf933c80 | 9535 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
1da177e4 LT |
9536 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
9537 | * flag clear. | |
9538 | */ | |
1da177e4 LT |
9539 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
9540 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9541 | #endif | |
9542 | ||
9543 | if (dev->flags & IFF_PROMISC) { | |
9544 | /* Promiscuous mode. */ | |
9545 | rx_mode |= RX_MODE_PROMISC; | |
9546 | } else if (dev->flags & IFF_ALLMULTI) { | |
9547 | /* Accept all multicast. */ | |
de6f31eb | 9548 | tg3_set_multi(tp, 1); |
4cd24eaf | 9549 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 9550 | /* Reject all multicast. */ |
de6f31eb | 9551 | tg3_set_multi(tp, 0); |
1da177e4 LT |
9552 | } else { |
9553 | /* Accept one or more multicast(s). */ | |
22bedad3 | 9554 | struct netdev_hw_addr *ha; |
1da177e4 LT |
9555 | u32 mc_filter[4] = { 0, }; |
9556 | u32 regidx; | |
9557 | u32 bit; | |
9558 | u32 crc; | |
9559 | ||
22bedad3 JP |
9560 | netdev_for_each_mc_addr(ha, dev) { |
9561 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
9562 | bit = ~crc & 0x7f; |
9563 | regidx = (bit & 0x60) >> 5; | |
9564 | bit &= 0x1f; | |
9565 | mc_filter[regidx] |= (1 << bit); | |
9566 | } | |
9567 | ||
9568 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9569 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9570 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9571 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9572 | } | |
9573 | ||
9574 | if (rx_mode != tp->rx_mode) { | |
9575 | tp->rx_mode = rx_mode; | |
9576 | tw32_f(MAC_RX_MODE, rx_mode); | |
9577 | udelay(10); | |
9578 | } | |
9579 | } | |
9580 | ||
9581 | static void tg3_set_rx_mode(struct net_device *dev) | |
9582 | { | |
9583 | struct tg3 *tp = netdev_priv(dev); | |
9584 | ||
e75f7c90 MC |
9585 | if (!netif_running(dev)) |
9586 | return; | |
9587 | ||
f47c11ee | 9588 | tg3_full_lock(tp, 0); |
1da177e4 | 9589 | __tg3_set_rx_mode(dev); |
f47c11ee | 9590 | tg3_full_unlock(tp); |
1da177e4 LT |
9591 | } |
9592 | ||
9593 | #define TG3_REGDUMP_LEN (32 * 1024) | |
9594 | ||
9595 | static int tg3_get_regs_len(struct net_device *dev) | |
9596 | { | |
9597 | return TG3_REGDUMP_LEN; | |
9598 | } | |
9599 | ||
9600 | static void tg3_get_regs(struct net_device *dev, | |
9601 | struct ethtool_regs *regs, void *_p) | |
9602 | { | |
9603 | u32 *p = _p; | |
9604 | struct tg3 *tp = netdev_priv(dev); | |
9605 | u8 *orig_p = _p; | |
9606 | int i; | |
9607 | ||
9608 | regs->version = 0; | |
9609 | ||
9610 | memset(p, 0, TG3_REGDUMP_LEN); | |
9611 | ||
80096068 | 9612 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9613 | return; |
9614 | ||
f47c11ee | 9615 | tg3_full_lock(tp, 0); |
1da177e4 LT |
9616 | |
9617 | #define __GET_REG32(reg) (*(p)++ = tr32(reg)) | |
be98da6a | 9618 | #define GET_REG32_LOOP(base, len) \ |
1da177e4 LT |
9619 | do { p = (u32 *)(orig_p + (base)); \ |
9620 | for (i = 0; i < len; i += 4) \ | |
9621 | __GET_REG32((base) + i); \ | |
9622 | } while (0) | |
9623 | #define GET_REG32_1(reg) \ | |
9624 | do { p = (u32 *)(orig_p + (reg)); \ | |
9625 | __GET_REG32((reg)); \ | |
9626 | } while (0) | |
9627 | ||
9628 | GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0); | |
9629 | GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200); | |
9630 | GET_REG32_LOOP(MAC_MODE, 0x4f0); | |
9631 | GET_REG32_LOOP(SNDDATAI_MODE, 0xe0); | |
9632 | GET_REG32_1(SNDDATAC_MODE); | |
9633 | GET_REG32_LOOP(SNDBDS_MODE, 0x80); | |
9634 | GET_REG32_LOOP(SNDBDI_MODE, 0x48); | |
9635 | GET_REG32_1(SNDBDC_MODE); | |
9636 | GET_REG32_LOOP(RCVLPC_MODE, 0x20); | |
9637 | GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c); | |
9638 | GET_REG32_LOOP(RCVDBDI_MODE, 0x0c); | |
9639 | GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c); | |
9640 | GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44); | |
9641 | GET_REG32_1(RCVDCC_MODE); | |
9642 | GET_REG32_LOOP(RCVBDI_MODE, 0x20); | |
9643 | GET_REG32_LOOP(RCVCC_MODE, 0x14); | |
9644 | GET_REG32_LOOP(RCVLSC_MODE, 0x08); | |
9645 | GET_REG32_1(MBFREE_MODE); | |
9646 | GET_REG32_LOOP(HOSTCC_MODE, 0x100); | |
9647 | GET_REG32_LOOP(MEMARB_MODE, 0x10); | |
9648 | GET_REG32_LOOP(BUFMGR_MODE, 0x58); | |
9649 | GET_REG32_LOOP(RDMAC_MODE, 0x08); | |
9650 | GET_REG32_LOOP(WDMAC_MODE, 0x08); | |
091465d7 CE |
9651 | GET_REG32_1(RX_CPU_MODE); |
9652 | GET_REG32_1(RX_CPU_STATE); | |
9653 | GET_REG32_1(RX_CPU_PGMCTR); | |
9654 | GET_REG32_1(RX_CPU_HWBKPT); | |
9655 | GET_REG32_1(TX_CPU_MODE); | |
9656 | GET_REG32_1(TX_CPU_STATE); | |
9657 | GET_REG32_1(TX_CPU_PGMCTR); | |
1da177e4 LT |
9658 | GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110); |
9659 | GET_REG32_LOOP(FTQ_RESET, 0x120); | |
9660 | GET_REG32_LOOP(MSGINT_MODE, 0x0c); | |
9661 | GET_REG32_1(DMAC_MODE); | |
9662 | GET_REG32_LOOP(GRC_MODE, 0x4c); | |
9663 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
9664 | GET_REG32_LOOP(NVRAM_CMD, 0x24); | |
9665 | ||
9666 | #undef __GET_REG32 | |
9667 | #undef GET_REG32_LOOP | |
9668 | #undef GET_REG32_1 | |
9669 | ||
f47c11ee | 9670 | tg3_full_unlock(tp); |
1da177e4 LT |
9671 | } |
9672 | ||
9673 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9674 | { | |
9675 | struct tg3 *tp = netdev_priv(dev); | |
9676 | ||
9677 | return tp->nvram_size; | |
9678 | } | |
9679 | ||
1da177e4 LT |
9680 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
9681 | { | |
9682 | struct tg3 *tp = netdev_priv(dev); | |
9683 | int ret; | |
9684 | u8 *pd; | |
b9fc7dc5 | 9685 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 9686 | __be32 val; |
1da177e4 | 9687 | |
df259d8c MC |
9688 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
9689 | return -EINVAL; | |
9690 | ||
80096068 | 9691 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9692 | return -EAGAIN; |
9693 | ||
1da177e4 LT |
9694 | offset = eeprom->offset; |
9695 | len = eeprom->len; | |
9696 | eeprom->len = 0; | |
9697 | ||
9698 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9699 | ||
9700 | if (offset & 3) { | |
9701 | /* adjustments to start on required 4 byte boundary */ | |
9702 | b_offset = offset & 3; | |
9703 | b_count = 4 - b_offset; | |
9704 | if (b_count > len) { | |
9705 | /* i.e. offset=1 len=2 */ | |
9706 | b_count = len; | |
9707 | } | |
a9dc529d | 9708 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
9709 | if (ret) |
9710 | return ret; | |
be98da6a | 9711 | memcpy(data, ((char *)&val) + b_offset, b_count); |
1da177e4 LT |
9712 | len -= b_count; |
9713 | offset += b_count; | |
c6cdf436 | 9714 | eeprom->len += b_count; |
1da177e4 LT |
9715 | } |
9716 | ||
9717 | /* read bytes upto the last 4 byte boundary */ | |
9718 | pd = &data[eeprom->len]; | |
9719 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 9720 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
9721 | if (ret) { |
9722 | eeprom->len += i; | |
9723 | return ret; | |
9724 | } | |
1da177e4 LT |
9725 | memcpy(pd + i, &val, 4); |
9726 | } | |
9727 | eeprom->len += i; | |
9728 | ||
9729 | if (len & 3) { | |
9730 | /* read last bytes not ending on 4 byte boundary */ | |
9731 | pd = &data[eeprom->len]; | |
9732 | b_count = len & 3; | |
9733 | b_offset = offset + len - b_count; | |
a9dc529d | 9734 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
9735 | if (ret) |
9736 | return ret; | |
b9fc7dc5 | 9737 | memcpy(pd, &val, b_count); |
1da177e4 LT |
9738 | eeprom->len += b_count; |
9739 | } | |
9740 | return 0; | |
9741 | } | |
9742 | ||
6aa20a22 | 9743 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
9744 | |
9745 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9746 | { | |
9747 | struct tg3 *tp = netdev_priv(dev); | |
9748 | int ret; | |
b9fc7dc5 | 9749 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 9750 | u8 *buf; |
a9dc529d | 9751 | __be32 start, end; |
1da177e4 | 9752 | |
80096068 | 9753 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
bc1c7567 MC |
9754 | return -EAGAIN; |
9755 | ||
df259d8c MC |
9756 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
9757 | eeprom->magic != TG3_EEPROM_MAGIC) | |
1da177e4 LT |
9758 | return -EINVAL; |
9759 | ||
9760 | offset = eeprom->offset; | |
9761 | len = eeprom->len; | |
9762 | ||
9763 | if ((b_offset = (offset & 3))) { | |
9764 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 9765 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
9766 | if (ret) |
9767 | return ret; | |
1da177e4 LT |
9768 | len += b_offset; |
9769 | offset &= ~3; | |
1c8594b4 MC |
9770 | if (len < 4) |
9771 | len = 4; | |
1da177e4 LT |
9772 | } |
9773 | ||
9774 | odd_len = 0; | |
1c8594b4 | 9775 | if (len & 3) { |
1da177e4 LT |
9776 | /* adjustments to end on required 4 byte boundary */ |
9777 | odd_len = 1; | |
9778 | len = (len + 3) & ~3; | |
a9dc529d | 9779 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
9780 | if (ret) |
9781 | return ret; | |
1da177e4 LT |
9782 | } |
9783 | ||
9784 | buf = data; | |
9785 | if (b_offset || odd_len) { | |
9786 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 9787 | if (!buf) |
1da177e4 LT |
9788 | return -ENOMEM; |
9789 | if (b_offset) | |
9790 | memcpy(buf, &start, 4); | |
9791 | if (odd_len) | |
9792 | memcpy(buf+len-4, &end, 4); | |
9793 | memcpy(buf + b_offset, data, eeprom->len); | |
9794 | } | |
9795 | ||
9796 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
9797 | ||
9798 | if (buf != data) | |
9799 | kfree(buf); | |
9800 | ||
9801 | return ret; | |
9802 | } | |
9803 | ||
9804 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9805 | { | |
b02fd9e3 MC |
9806 | struct tg3 *tp = netdev_priv(dev); |
9807 | ||
9808 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
3f0e3ad7 | 9809 | struct phy_device *phydev; |
f07e9af3 | 9810 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 9811 | return -EAGAIN; |
3f0e3ad7 MC |
9812 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9813 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 9814 | } |
6aa20a22 | 9815 | |
1da177e4 LT |
9816 | cmd->supported = (SUPPORTED_Autoneg); |
9817 | ||
f07e9af3 | 9818 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
9819 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
9820 | SUPPORTED_1000baseT_Full); | |
9821 | ||
f07e9af3 | 9822 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
1da177e4 LT |
9823 | cmd->supported |= (SUPPORTED_100baseT_Half | |
9824 | SUPPORTED_100baseT_Full | | |
9825 | SUPPORTED_10baseT_Half | | |
9826 | SUPPORTED_10baseT_Full | | |
3bebab59 | 9827 | SUPPORTED_TP); |
ef348144 KK |
9828 | cmd->port = PORT_TP; |
9829 | } else { | |
1da177e4 | 9830 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
9831 | cmd->port = PORT_FIBRE; |
9832 | } | |
6aa20a22 | 9833 | |
1da177e4 LT |
9834 | cmd->advertising = tp->link_config.advertising; |
9835 | if (netif_running(dev)) { | |
9836 | cmd->speed = tp->link_config.active_speed; | |
9837 | cmd->duplex = tp->link_config.active_duplex; | |
64c22182 MC |
9838 | } else { |
9839 | cmd->speed = SPEED_INVALID; | |
9840 | cmd->duplex = DUPLEX_INVALID; | |
1da177e4 | 9841 | } |
882e9793 | 9842 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 9843 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
9844 | cmd->autoneg = tp->link_config.autoneg; |
9845 | cmd->maxtxpkt = 0; | |
9846 | cmd->maxrxpkt = 0; | |
9847 | return 0; | |
9848 | } | |
6aa20a22 | 9849 | |
1da177e4 LT |
9850 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
9851 | { | |
9852 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9853 | |
b02fd9e3 | 9854 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 9855 | struct phy_device *phydev; |
f07e9af3 | 9856 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 9857 | return -EAGAIN; |
3f0e3ad7 MC |
9858 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9859 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
9860 | } |
9861 | ||
7e5856bd MC |
9862 | if (cmd->autoneg != AUTONEG_ENABLE && |
9863 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 9864 | return -EINVAL; |
7e5856bd MC |
9865 | |
9866 | if (cmd->autoneg == AUTONEG_DISABLE && | |
9867 | cmd->duplex != DUPLEX_FULL && | |
9868 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 9869 | return -EINVAL; |
1da177e4 | 9870 | |
7e5856bd MC |
9871 | if (cmd->autoneg == AUTONEG_ENABLE) { |
9872 | u32 mask = ADVERTISED_Autoneg | | |
9873 | ADVERTISED_Pause | | |
9874 | ADVERTISED_Asym_Pause; | |
9875 | ||
f07e9af3 | 9876 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
7e5856bd MC |
9877 | mask |= ADVERTISED_1000baseT_Half | |
9878 | ADVERTISED_1000baseT_Full; | |
9879 | ||
f07e9af3 | 9880 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
7e5856bd MC |
9881 | mask |= ADVERTISED_100baseT_Half | |
9882 | ADVERTISED_100baseT_Full | | |
9883 | ADVERTISED_10baseT_Half | | |
9884 | ADVERTISED_10baseT_Full | | |
9885 | ADVERTISED_TP; | |
9886 | else | |
9887 | mask |= ADVERTISED_FIBRE; | |
9888 | ||
9889 | if (cmd->advertising & ~mask) | |
9890 | return -EINVAL; | |
9891 | ||
9892 | mask &= (ADVERTISED_1000baseT_Half | | |
9893 | ADVERTISED_1000baseT_Full | | |
9894 | ADVERTISED_100baseT_Half | | |
9895 | ADVERTISED_100baseT_Full | | |
9896 | ADVERTISED_10baseT_Half | | |
9897 | ADVERTISED_10baseT_Full); | |
9898 | ||
9899 | cmd->advertising &= mask; | |
9900 | } else { | |
f07e9af3 | 9901 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
7e5856bd MC |
9902 | if (cmd->speed != SPEED_1000) |
9903 | return -EINVAL; | |
9904 | ||
9905 | if (cmd->duplex != DUPLEX_FULL) | |
9906 | return -EINVAL; | |
9907 | } else { | |
9908 | if (cmd->speed != SPEED_100 && | |
9909 | cmd->speed != SPEED_10) | |
9910 | return -EINVAL; | |
9911 | } | |
9912 | } | |
9913 | ||
f47c11ee | 9914 | tg3_full_lock(tp, 0); |
1da177e4 LT |
9915 | |
9916 | tp->link_config.autoneg = cmd->autoneg; | |
9917 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
9918 | tp->link_config.advertising = (cmd->advertising | |
9919 | ADVERTISED_Autoneg); | |
1da177e4 LT |
9920 | tp->link_config.speed = SPEED_INVALID; |
9921 | tp->link_config.duplex = DUPLEX_INVALID; | |
9922 | } else { | |
9923 | tp->link_config.advertising = 0; | |
9924 | tp->link_config.speed = cmd->speed; | |
9925 | tp->link_config.duplex = cmd->duplex; | |
b02fd9e3 | 9926 | } |
6aa20a22 | 9927 | |
24fcad6b MC |
9928 | tp->link_config.orig_speed = tp->link_config.speed; |
9929 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
9930 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
9931 | ||
1da177e4 LT |
9932 | if (netif_running(dev)) |
9933 | tg3_setup_phy(tp, 1); | |
9934 | ||
f47c11ee | 9935 | tg3_full_unlock(tp); |
6aa20a22 | 9936 | |
1da177e4 LT |
9937 | return 0; |
9938 | } | |
6aa20a22 | 9939 | |
1da177e4 LT |
9940 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
9941 | { | |
9942 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9943 | |
1da177e4 LT |
9944 | strcpy(info->driver, DRV_MODULE_NAME); |
9945 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 9946 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
9947 | strcpy(info->bus_info, pci_name(tp->pdev)); |
9948 | } | |
6aa20a22 | 9949 | |
1da177e4 LT |
9950 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
9951 | { | |
9952 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9953 | |
12dac075 RW |
9954 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
9955 | device_can_wakeup(&tp->pdev->dev)) | |
a85feb8c GZ |
9956 | wol->supported = WAKE_MAGIC; |
9957 | else | |
9958 | wol->supported = 0; | |
1da177e4 | 9959 | wol->wolopts = 0; |
05ac4cb7 MC |
9960 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && |
9961 | device_can_wakeup(&tp->pdev->dev)) | |
1da177e4 LT |
9962 | wol->wolopts = WAKE_MAGIC; |
9963 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
9964 | } | |
6aa20a22 | 9965 | |
1da177e4 LT |
9966 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
9967 | { | |
9968 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 9969 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 9970 | |
1da177e4 LT |
9971 | if (wol->wolopts & ~WAKE_MAGIC) |
9972 | return -EINVAL; | |
9973 | if ((wol->wolopts & WAKE_MAGIC) && | |
12dac075 | 9974 | !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 9975 | return -EINVAL; |
6aa20a22 | 9976 | |
f2dc0d18 RW |
9977 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
9978 | ||
f47c11ee | 9979 | spin_lock_bh(&tp->lock); |
f2dc0d18 | 9980 | if (device_may_wakeup(dp)) |
1da177e4 | 9981 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
f2dc0d18 | 9982 | else |
1da177e4 | 9983 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; |
f47c11ee | 9984 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 9985 | |
f2dc0d18 | 9986 | |
1da177e4 LT |
9987 | return 0; |
9988 | } | |
6aa20a22 | 9989 | |
1da177e4 LT |
9990 | static u32 tg3_get_msglevel(struct net_device *dev) |
9991 | { | |
9992 | struct tg3 *tp = netdev_priv(dev); | |
9993 | return tp->msg_enable; | |
9994 | } | |
6aa20a22 | 9995 | |
1da177e4 LT |
9996 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
9997 | { | |
9998 | struct tg3 *tp = netdev_priv(dev); | |
9999 | tp->msg_enable = value; | |
10000 | } | |
6aa20a22 | 10001 | |
1da177e4 LT |
10002 | static int tg3_set_tso(struct net_device *dev, u32 value) |
10003 | { | |
10004 | struct tg3 *tp = netdev_priv(dev); | |
10005 | ||
10006 | if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
10007 | if (value) | |
10008 | return -EINVAL; | |
10009 | return 0; | |
10010 | } | |
027455ad | 10011 | if ((dev->features & NETIF_F_IPV6_CSUM) && |
e849cdc3 MC |
10012 | ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || |
10013 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) { | |
9936bcf6 | 10014 | if (value) { |
b0026624 | 10015 | dev->features |= NETIF_F_TSO6; |
e849cdc3 MC |
10016 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
10017 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
10018 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
10019 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 10020 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
e849cdc3 | 10021 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
9936bcf6 MC |
10022 | dev->features |= NETIF_F_TSO_ECN; |
10023 | } else | |
10024 | dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); | |
b0026624 | 10025 | } |
1da177e4 LT |
10026 | return ethtool_op_set_tso(dev, value); |
10027 | } | |
6aa20a22 | 10028 | |
1da177e4 LT |
10029 | static int tg3_nway_reset(struct net_device *dev) |
10030 | { | |
10031 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 10032 | int r; |
6aa20a22 | 10033 | |
1da177e4 LT |
10034 | if (!netif_running(dev)) |
10035 | return -EAGAIN; | |
10036 | ||
f07e9af3 | 10037 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
c94e3941 MC |
10038 | return -EINVAL; |
10039 | ||
b02fd9e3 | 10040 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
f07e9af3 | 10041 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 10042 | return -EAGAIN; |
3f0e3ad7 | 10043 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
10044 | } else { |
10045 | u32 bmcr; | |
10046 | ||
10047 | spin_lock_bh(&tp->lock); | |
10048 | r = -EINVAL; | |
10049 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
10050 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
10051 | ((bmcr & BMCR_ANENABLE) || | |
f07e9af3 | 10052 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
b02fd9e3 MC |
10053 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
10054 | BMCR_ANENABLE); | |
10055 | r = 0; | |
10056 | } | |
10057 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 10058 | } |
6aa20a22 | 10059 | |
1da177e4 LT |
10060 | return r; |
10061 | } | |
6aa20a22 | 10062 | |
1da177e4 LT |
10063 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10064 | { | |
10065 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10066 | |
2c49a44d | 10067 | ering->rx_max_pending = tp->rx_std_ring_mask; |
1da177e4 | 10068 | ering->rx_mini_max_pending = 0; |
4f81c32b | 10069 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
2c49a44d | 10070 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
4f81c32b MC |
10071 | else |
10072 | ering->rx_jumbo_max_pending = 0; | |
10073 | ||
10074 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
10075 | |
10076 | ering->rx_pending = tp->rx_pending; | |
10077 | ering->rx_mini_pending = 0; | |
4f81c32b MC |
10078 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
10079 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
10080 | else | |
10081 | ering->rx_jumbo_pending = 0; | |
10082 | ||
f3f3f27e | 10083 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 10084 | } |
6aa20a22 | 10085 | |
1da177e4 LT |
10086 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
10087 | { | |
10088 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 10089 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 10090 | |
2c49a44d MC |
10091 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
10092 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || | |
bc3a9254 MC |
10093 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
10094 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
7f62ad5d | 10095 | ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && |
bc3a9254 | 10096 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 10097 | return -EINVAL; |
6aa20a22 | 10098 | |
bbe832c0 | 10099 | if (netif_running(dev)) { |
b02fd9e3 | 10100 | tg3_phy_stop(tp); |
1da177e4 | 10101 | tg3_netif_stop(tp); |
bbe832c0 MC |
10102 | irq_sync = 1; |
10103 | } | |
1da177e4 | 10104 | |
bbe832c0 | 10105 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 10106 | |
1da177e4 LT |
10107 | tp->rx_pending = ering->rx_pending; |
10108 | ||
10109 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | |
10110 | tp->rx_pending > 63) | |
10111 | tp->rx_pending = 63; | |
10112 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd | 10113 | |
6fd45cb8 | 10114 | for (i = 0; i < tp->irq_max; i++) |
646c9edd | 10115 | tp->napi[i].tx_pending = ering->tx_pending; |
1da177e4 LT |
10116 | |
10117 | if (netif_running(dev)) { | |
944d980e | 10118 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
10119 | err = tg3_restart_hw(tp, 1); |
10120 | if (!err) | |
10121 | tg3_netif_start(tp); | |
1da177e4 LT |
10122 | } |
10123 | ||
f47c11ee | 10124 | tg3_full_unlock(tp); |
6aa20a22 | 10125 | |
b02fd9e3 MC |
10126 | if (irq_sync && !err) |
10127 | tg3_phy_start(tp); | |
10128 | ||
b9ec6c1b | 10129 | return err; |
1da177e4 | 10130 | } |
6aa20a22 | 10131 | |
1da177e4 LT |
10132 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10133 | { | |
10134 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10135 | |
1da177e4 | 10136 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; |
8d018621 | 10137 | |
e18ce346 | 10138 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
10139 | epause->rx_pause = 1; |
10140 | else | |
10141 | epause->rx_pause = 0; | |
10142 | ||
e18ce346 | 10143 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
10144 | epause->tx_pause = 1; |
10145 | else | |
10146 | epause->tx_pause = 0; | |
1da177e4 | 10147 | } |
6aa20a22 | 10148 | |
1da177e4 LT |
10149 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
10150 | { | |
10151 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 10152 | int err = 0; |
6aa20a22 | 10153 | |
b02fd9e3 | 10154 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
2712168f MC |
10155 | u32 newadv; |
10156 | struct phy_device *phydev; | |
1da177e4 | 10157 | |
2712168f | 10158 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 10159 | |
2712168f MC |
10160 | if (!(phydev->supported & SUPPORTED_Pause) || |
10161 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
2259dca3 | 10162 | (epause->rx_pause != epause->tx_pause))) |
2712168f | 10163 | return -EINVAL; |
1da177e4 | 10164 | |
2712168f MC |
10165 | tp->link_config.flowctrl = 0; |
10166 | if (epause->rx_pause) { | |
10167 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
10168 | ||
10169 | if (epause->tx_pause) { | |
10170 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10171 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 10172 | } else |
2712168f MC |
10173 | newadv = ADVERTISED_Pause | |
10174 | ADVERTISED_Asym_Pause; | |
10175 | } else if (epause->tx_pause) { | |
10176 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
10177 | newadv = ADVERTISED_Asym_Pause; | |
10178 | } else | |
10179 | newadv = 0; | |
10180 | ||
10181 | if (epause->autoneg) | |
10182 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
10183 | else | |
10184 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
10185 | ||
f07e9af3 | 10186 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
2712168f MC |
10187 | u32 oldadv = phydev->advertising & |
10188 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
10189 | if (oldadv != newadv) { | |
10190 | phydev->advertising &= | |
10191 | ~(ADVERTISED_Pause | | |
10192 | ADVERTISED_Asym_Pause); | |
10193 | phydev->advertising |= newadv; | |
10194 | if (phydev->autoneg) { | |
10195 | /* | |
10196 | * Always renegotiate the link to | |
10197 | * inform our link partner of our | |
10198 | * flow control settings, even if the | |
10199 | * flow control is forced. Let | |
10200 | * tg3_adjust_link() do the final | |
10201 | * flow control setup. | |
10202 | */ | |
10203 | return phy_start_aneg(phydev); | |
b02fd9e3 | 10204 | } |
b02fd9e3 | 10205 | } |
b02fd9e3 | 10206 | |
2712168f | 10207 | if (!epause->autoneg) |
b02fd9e3 | 10208 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
10209 | } else { |
10210 | tp->link_config.orig_advertising &= | |
10211 | ~(ADVERTISED_Pause | | |
10212 | ADVERTISED_Asym_Pause); | |
10213 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
10214 | } |
10215 | } else { | |
10216 | int irq_sync = 0; | |
10217 | ||
10218 | if (netif_running(dev)) { | |
10219 | tg3_netif_stop(tp); | |
10220 | irq_sync = 1; | |
10221 | } | |
10222 | ||
10223 | tg3_full_lock(tp, irq_sync); | |
10224 | ||
10225 | if (epause->autoneg) | |
10226 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
10227 | else | |
10228 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
10229 | if (epause->rx_pause) | |
e18ce346 | 10230 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 10231 | else |
e18ce346 | 10232 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 10233 | if (epause->tx_pause) |
e18ce346 | 10234 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 10235 | else |
e18ce346 | 10236 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
10237 | |
10238 | if (netif_running(dev)) { | |
10239 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
10240 | err = tg3_restart_hw(tp, 1); | |
10241 | if (!err) | |
10242 | tg3_netif_start(tp); | |
10243 | } | |
10244 | ||
10245 | tg3_full_unlock(tp); | |
10246 | } | |
6aa20a22 | 10247 | |
b9ec6c1b | 10248 | return err; |
1da177e4 | 10249 | } |
6aa20a22 | 10250 | |
1da177e4 LT |
10251 | static u32 tg3_get_rx_csum(struct net_device *dev) |
10252 | { | |
10253 | struct tg3 *tp = netdev_priv(dev); | |
10254 | return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0; | |
10255 | } | |
6aa20a22 | 10256 | |
1da177e4 LT |
10257 | static int tg3_set_rx_csum(struct net_device *dev, u32 data) |
10258 | { | |
10259 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10260 | |
1da177e4 LT |
10261 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
10262 | if (data != 0) | |
10263 | return -EINVAL; | |
c6cdf436 MC |
10264 | return 0; |
10265 | } | |
6aa20a22 | 10266 | |
f47c11ee | 10267 | spin_lock_bh(&tp->lock); |
1da177e4 LT |
10268 | if (data) |
10269 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
10270 | else | |
10271 | tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; | |
f47c11ee | 10272 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10273 | |
1da177e4 LT |
10274 | return 0; |
10275 | } | |
6aa20a22 | 10276 | |
1da177e4 LT |
10277 | static int tg3_set_tx_csum(struct net_device *dev, u32 data) |
10278 | { | |
10279 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10280 | |
1da177e4 LT |
10281 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
10282 | if (data != 0) | |
10283 | return -EINVAL; | |
c6cdf436 MC |
10284 | return 0; |
10285 | } | |
6aa20a22 | 10286 | |
321d32a0 | 10287 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
6460d948 | 10288 | ethtool_op_set_tx_ipv6_csum(dev, data); |
1da177e4 | 10289 | else |
9c27dbdf | 10290 | ethtool_op_set_tx_csum(dev, data); |
1da177e4 LT |
10291 | |
10292 | return 0; | |
10293 | } | |
10294 | ||
de6f31eb | 10295 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10296 | { |
b9f2c044 JG |
10297 | switch (sset) { |
10298 | case ETH_SS_TEST: | |
10299 | return TG3_NUM_TEST; | |
10300 | case ETH_SS_STATS: | |
10301 | return TG3_NUM_STATS; | |
10302 | default: | |
10303 | return -EOPNOTSUPP; | |
10304 | } | |
4cafd3f5 MC |
10305 | } |
10306 | ||
de6f31eb | 10307 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10308 | { |
10309 | switch (stringset) { | |
10310 | case ETH_SS_STATS: | |
10311 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10312 | break; | |
4cafd3f5 MC |
10313 | case ETH_SS_TEST: |
10314 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10315 | break; | |
1da177e4 LT |
10316 | default: |
10317 | WARN_ON(1); /* we need a WARN() */ | |
10318 | break; | |
10319 | } | |
10320 | } | |
10321 | ||
4009a93d MC |
10322 | static int tg3_phys_id(struct net_device *dev, u32 data) |
10323 | { | |
10324 | struct tg3 *tp = netdev_priv(dev); | |
10325 | int i; | |
10326 | ||
10327 | if (!netif_running(tp->dev)) | |
10328 | return -EAGAIN; | |
10329 | ||
10330 | if (data == 0) | |
759afc31 | 10331 | data = UINT_MAX / 2; |
4009a93d MC |
10332 | |
10333 | for (i = 0; i < (data * 2); i++) { | |
10334 | if ((i % 2) == 0) | |
10335 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10336 | LED_CTRL_1000MBPS_ON | | |
10337 | LED_CTRL_100MBPS_ON | | |
10338 | LED_CTRL_10MBPS_ON | | |
10339 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10340 | LED_CTRL_TRAFFIC_BLINK | | |
10341 | LED_CTRL_TRAFFIC_LED); | |
6aa20a22 | 10342 | |
4009a93d MC |
10343 | else |
10344 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10345 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10346 | ||
10347 | if (msleep_interruptible(500)) | |
10348 | break; | |
10349 | } | |
10350 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10351 | return 0; | |
10352 | } | |
10353 | ||
de6f31eb | 10354 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10355 | struct ethtool_stats *estats, u64 *tmp_stats) |
10356 | { | |
10357 | struct tg3 *tp = netdev_priv(dev); | |
10358 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10359 | } | |
10360 | ||
566f86ad | 10361 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10362 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10363 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10364 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
b16250e3 MC |
10365 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10366 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10367 | |
10368 | static int tg3_test_nvram(struct tg3 *tp) | |
10369 | { | |
b9fc7dc5 | 10370 | u32 csum, magic; |
a9dc529d | 10371 | __be32 *buf; |
ab0049b4 | 10372 | int i, j, k, err = 0, size; |
566f86ad | 10373 | |
df259d8c MC |
10374 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
10375 | return 0; | |
10376 | ||
e4f34110 | 10377 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10378 | return -EIO; |
10379 | ||
1b27777a MC |
10380 | if (magic == TG3_EEPROM_MAGIC) |
10381 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10382 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10383 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10384 | TG3_EEPROM_SB_FORMAT_1) { | |
10385 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10386 | case TG3_EEPROM_SB_REVISION_0: | |
10387 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10388 | break; | |
10389 | case TG3_EEPROM_SB_REVISION_2: | |
10390 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10391 | break; | |
10392 | case TG3_EEPROM_SB_REVISION_3: | |
10393 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10394 | break; | |
10395 | default: | |
10396 | return 0; | |
10397 | } | |
10398 | } else | |
1b27777a | 10399 | return 0; |
b16250e3 MC |
10400 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10401 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10402 | else | |
1b27777a MC |
10403 | return -EIO; |
10404 | ||
10405 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10406 | if (buf == NULL) |
10407 | return -ENOMEM; | |
10408 | ||
1b27777a MC |
10409 | err = -EIO; |
10410 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10411 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10412 | if (err) | |
566f86ad | 10413 | break; |
566f86ad | 10414 | } |
1b27777a | 10415 | if (i < size) |
566f86ad MC |
10416 | goto out; |
10417 | ||
1b27777a | 10418 | /* Selfboot format */ |
a9dc529d | 10419 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10420 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10421 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10422 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10423 | ||
b9fc7dc5 | 10424 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10425 | TG3_EEPROM_SB_REVISION_2) { |
10426 | /* For rev 2, the csum doesn't include the MBA. */ | |
10427 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10428 | csum8 += buf8[i]; | |
10429 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10430 | csum8 += buf8[i]; | |
10431 | } else { | |
10432 | for (i = 0; i < size; i++) | |
10433 | csum8 += buf8[i]; | |
10434 | } | |
1b27777a | 10435 | |
ad96b485 AB |
10436 | if (csum8 == 0) { |
10437 | err = 0; | |
10438 | goto out; | |
10439 | } | |
10440 | ||
10441 | err = -EIO; | |
10442 | goto out; | |
1b27777a | 10443 | } |
566f86ad | 10444 | |
b9fc7dc5 | 10445 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10446 | TG3_EEPROM_MAGIC_HW) { |
10447 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10448 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10449 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10450 | |
10451 | /* Separate the parity bits and the data bytes. */ | |
10452 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10453 | if ((i == 0) || (i == 8)) { | |
10454 | int l; | |
10455 | u8 msk; | |
10456 | ||
10457 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10458 | parity[k++] = buf8[i] & msk; | |
10459 | i++; | |
859a5887 | 10460 | } else if (i == 16) { |
b16250e3 MC |
10461 | int l; |
10462 | u8 msk; | |
10463 | ||
10464 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10465 | parity[k++] = buf8[i] & msk; | |
10466 | i++; | |
10467 | ||
10468 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10469 | parity[k++] = buf8[i] & msk; | |
10470 | i++; | |
10471 | } | |
10472 | data[j++] = buf8[i]; | |
10473 | } | |
10474 | ||
10475 | err = -EIO; | |
10476 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10477 | u8 hw8 = hweight8(data[i]); | |
10478 | ||
10479 | if ((hw8 & 0x1) && parity[i]) | |
10480 | goto out; | |
10481 | else if (!(hw8 & 0x1) && !parity[i]) | |
10482 | goto out; | |
10483 | } | |
10484 | err = 0; | |
10485 | goto out; | |
10486 | } | |
10487 | ||
01c3a392 MC |
10488 | err = -EIO; |
10489 | ||
566f86ad MC |
10490 | /* Bootstrap checksum at offset 0x10 */ |
10491 | csum = calc_crc((unsigned char *) buf, 0x10); | |
01c3a392 | 10492 | if (csum != le32_to_cpu(buf[0x10/4])) |
566f86ad MC |
10493 | goto out; |
10494 | ||
10495 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10496 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
01c3a392 | 10497 | if (csum != le32_to_cpu(buf[0xfc/4])) |
a9dc529d | 10498 | goto out; |
566f86ad | 10499 | |
d4894f3e MC |
10500 | for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) { |
10501 | /* The data is in little-endian format in NVRAM. | |
10502 | * Use the big-endian read routines to preserve | |
10503 | * the byte order as it exists in NVRAM. | |
10504 | */ | |
10505 | if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4])) | |
10506 | goto out; | |
10507 | } | |
10508 | ||
10509 | i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN, | |
10510 | PCI_VPD_LRDT_RO_DATA); | |
10511 | if (i > 0) { | |
10512 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); | |
10513 | if (j < 0) | |
10514 | goto out; | |
10515 | ||
10516 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN) | |
10517 | goto out; | |
10518 | ||
10519 | i += PCI_VPD_LRDT_TAG_SIZE; | |
10520 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, | |
10521 | PCI_VPD_RO_KEYWORD_CHKSUM); | |
10522 | if (j > 0) { | |
10523 | u8 csum8 = 0; | |
10524 | ||
10525 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
10526 | ||
10527 | for (i = 0; i <= j; i++) | |
10528 | csum8 += ((u8 *)buf)[i]; | |
10529 | ||
10530 | if (csum8) | |
10531 | goto out; | |
10532 | } | |
10533 | } | |
10534 | ||
566f86ad MC |
10535 | err = 0; |
10536 | ||
10537 | out: | |
10538 | kfree(buf); | |
10539 | return err; | |
10540 | } | |
10541 | ||
ca43007a MC |
10542 | #define TG3_SERDES_TIMEOUT_SEC 2 |
10543 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10544 | ||
10545 | static int tg3_test_link(struct tg3 *tp) | |
10546 | { | |
10547 | int i, max; | |
10548 | ||
10549 | if (!netif_running(tp->dev)) | |
10550 | return -ENODEV; | |
10551 | ||
f07e9af3 | 10552 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
ca43007a MC |
10553 | max = TG3_SERDES_TIMEOUT_SEC; |
10554 | else | |
10555 | max = TG3_COPPER_TIMEOUT_SEC; | |
10556 | ||
10557 | for (i = 0; i < max; i++) { | |
10558 | if (netif_carrier_ok(tp->dev)) | |
10559 | return 0; | |
10560 | ||
10561 | if (msleep_interruptible(1000)) | |
10562 | break; | |
10563 | } | |
10564 | ||
10565 | return -EIO; | |
10566 | } | |
10567 | ||
a71116d1 | 10568 | /* Only test the commonly used registers */ |
30ca3e37 | 10569 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 10570 | { |
b16250e3 | 10571 | int i, is_5705, is_5750; |
a71116d1 MC |
10572 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
10573 | static struct { | |
10574 | u16 offset; | |
10575 | u16 flags; | |
10576 | #define TG3_FL_5705 0x1 | |
10577 | #define TG3_FL_NOT_5705 0x2 | |
10578 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 10579 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
10580 | u32 read_mask; |
10581 | u32 write_mask; | |
10582 | } reg_tbl[] = { | |
10583 | /* MAC Control Registers */ | |
10584 | { MAC_MODE, TG3_FL_NOT_5705, | |
10585 | 0x00000000, 0x00ef6f8c }, | |
10586 | { MAC_MODE, TG3_FL_5705, | |
10587 | 0x00000000, 0x01ef6b8c }, | |
10588 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10589 | 0x03800107, 0x00000000 }, | |
10590 | { MAC_STATUS, TG3_FL_5705, | |
10591 | 0x03800100, 0x00000000 }, | |
10592 | { MAC_ADDR_0_HIGH, 0x0000, | |
10593 | 0x00000000, 0x0000ffff }, | |
10594 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 10595 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
10596 | { MAC_RX_MTU_SIZE, 0x0000, |
10597 | 0x00000000, 0x0000ffff }, | |
10598 | { MAC_TX_MODE, 0x0000, | |
10599 | 0x00000000, 0x00000070 }, | |
10600 | { MAC_TX_LENGTHS, 0x0000, | |
10601 | 0x00000000, 0x00003fff }, | |
10602 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10603 | 0x00000000, 0x000007fc }, | |
10604 | { MAC_RX_MODE, TG3_FL_5705, | |
10605 | 0x00000000, 0x000007dc }, | |
10606 | { MAC_HASH_REG_0, 0x0000, | |
10607 | 0x00000000, 0xffffffff }, | |
10608 | { MAC_HASH_REG_1, 0x0000, | |
10609 | 0x00000000, 0xffffffff }, | |
10610 | { MAC_HASH_REG_2, 0x0000, | |
10611 | 0x00000000, 0xffffffff }, | |
10612 | { MAC_HASH_REG_3, 0x0000, | |
10613 | 0x00000000, 0xffffffff }, | |
10614 | ||
10615 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10616 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10617 | 0x00000000, 0xffffffff }, | |
10618 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10619 | 0x00000000, 0xffffffff }, | |
10620 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10621 | 0x00000000, 0x00000003 }, | |
10622 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10623 | 0x00000000, 0xffffffff }, | |
10624 | { RCVDBDI_STD_BD+0, 0x0000, | |
10625 | 0x00000000, 0xffffffff }, | |
10626 | { RCVDBDI_STD_BD+4, 0x0000, | |
10627 | 0x00000000, 0xffffffff }, | |
10628 | { RCVDBDI_STD_BD+8, 0x0000, | |
10629 | 0x00000000, 0xffff0002 }, | |
10630 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10631 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10632 | |
a71116d1 MC |
10633 | /* Receive BD Initiator Control Registers. */ |
10634 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10635 | 0x00000000, 0xffffffff }, | |
10636 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10637 | 0x00000000, 0x000003ff }, | |
10638 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10639 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10640 | |
a71116d1 MC |
10641 | /* Host Coalescing Control Registers. */ |
10642 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10643 | 0x00000000, 0x00000004 }, | |
10644 | { HOSTCC_MODE, TG3_FL_5705, | |
10645 | 0x00000000, 0x000000f6 }, | |
10646 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10647 | 0x00000000, 0xffffffff }, | |
10648 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10649 | 0x00000000, 0x000003ff }, | |
10650 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10651 | 0x00000000, 0xffffffff }, | |
10652 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10653 | 0x00000000, 0x000003ff }, | |
10654 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10655 | 0x00000000, 0xffffffff }, | |
10656 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10657 | 0x00000000, 0x000000ff }, | |
10658 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10659 | 0x00000000, 0xffffffff }, | |
10660 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10661 | 0x00000000, 0x000000ff }, | |
10662 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10663 | 0x00000000, 0xffffffff }, | |
10664 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10665 | 0x00000000, 0xffffffff }, | |
10666 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10667 | 0x00000000, 0xffffffff }, | |
10668 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10669 | 0x00000000, 0x000000ff }, | |
10670 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10671 | 0x00000000, 0xffffffff }, | |
10672 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10673 | 0x00000000, 0x000000ff }, | |
10674 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10675 | 0x00000000, 0xffffffff }, | |
10676 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10677 | 0x00000000, 0xffffffff }, | |
10678 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10679 | 0x00000000, 0xffffffff }, | |
10680 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10681 | 0x00000000, 0xffffffff }, | |
10682 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10683 | 0x00000000, 0xffffffff }, | |
10684 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10685 | 0xffffffff, 0x00000000 }, | |
10686 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10687 | 0xffffffff, 0x00000000 }, | |
10688 | ||
10689 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 10690 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 10691 | 0x00000000, 0x007fff80 }, |
b16250e3 | 10692 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
10693 | 0x00000000, 0x007fffff }, |
10694 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10695 | 0x00000000, 0x0000003f }, | |
10696 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10697 | 0x00000000, 0x000001ff }, | |
10698 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10699 | 0x00000000, 0x000001ff }, | |
10700 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10701 | 0xffffffff, 0x00000000 }, | |
10702 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10703 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 10704 | |
a71116d1 MC |
10705 | /* Mailbox Registers */ |
10706 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10707 | 0x00000000, 0x000001ff }, | |
10708 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10709 | 0x00000000, 0x000001ff }, | |
10710 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10711 | 0x00000000, 0x000007ff }, | |
10712 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10713 | 0x00000000, 0x000001ff }, | |
10714 | ||
10715 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10716 | }; | |
10717 | ||
b16250e3 MC |
10718 | is_5705 = is_5750 = 0; |
10719 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
a71116d1 | 10720 | is_5705 = 1; |
b16250e3 MC |
10721 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
10722 | is_5750 = 1; | |
10723 | } | |
a71116d1 MC |
10724 | |
10725 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10726 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
10727 | continue; | |
10728 | ||
10729 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
10730 | continue; | |
10731 | ||
10732 | if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
10733 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
10734 | continue; | |
10735 | ||
b16250e3 MC |
10736 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
10737 | continue; | |
10738 | ||
a71116d1 MC |
10739 | offset = (u32) reg_tbl[i].offset; |
10740 | read_mask = reg_tbl[i].read_mask; | |
10741 | write_mask = reg_tbl[i].write_mask; | |
10742 | ||
10743 | /* Save the original register content */ | |
10744 | save_val = tr32(offset); | |
10745 | ||
10746 | /* Determine the read-only value. */ | |
10747 | read_val = save_val & read_mask; | |
10748 | ||
10749 | /* Write zero to the register, then make sure the read-only bits | |
10750 | * are not changed and the read/write bits are all zeros. | |
10751 | */ | |
10752 | tw32(offset, 0); | |
10753 | ||
10754 | val = tr32(offset); | |
10755 | ||
10756 | /* Test the read-only and read/write bits. */ | |
10757 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
10758 | goto out; | |
10759 | ||
10760 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
10761 | * make sure the read-only bits are not changed and the | |
10762 | * read/write bits are all ones. | |
10763 | */ | |
10764 | tw32(offset, read_mask | write_mask); | |
10765 | ||
10766 | val = tr32(offset); | |
10767 | ||
10768 | /* Test the read-only bits. */ | |
10769 | if ((val & read_mask) != read_val) | |
10770 | goto out; | |
10771 | ||
10772 | /* Test the read/write bits. */ | |
10773 | if ((val & write_mask) != write_mask) | |
10774 | goto out; | |
10775 | ||
10776 | tw32(offset, save_val); | |
10777 | } | |
10778 | ||
10779 | return 0; | |
10780 | ||
10781 | out: | |
9f88f29f | 10782 | if (netif_msg_hw(tp)) |
2445e461 MC |
10783 | netdev_err(tp->dev, |
10784 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
10785 | tw32(offset, save_val); |
10786 | return -EIO; | |
10787 | } | |
10788 | ||
7942e1db MC |
10789 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
10790 | { | |
f71e1309 | 10791 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
10792 | int i; |
10793 | u32 j; | |
10794 | ||
e9edda69 | 10795 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
10796 | for (j = 0; j < len; j += 4) { |
10797 | u32 val; | |
10798 | ||
10799 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
10800 | tg3_read_mem(tp, offset + j, &val); | |
10801 | if (val != test_pattern[i]) | |
10802 | return -EIO; | |
10803 | } | |
10804 | } | |
10805 | return 0; | |
10806 | } | |
10807 | ||
10808 | static int tg3_test_memory(struct tg3 *tp) | |
10809 | { | |
10810 | static struct mem_entry { | |
10811 | u32 offset; | |
10812 | u32 len; | |
10813 | } mem_tbl_570x[] = { | |
38690194 | 10814 | { 0x00000000, 0x00b50}, |
7942e1db MC |
10815 | { 0x00002000, 0x1c000}, |
10816 | { 0xffffffff, 0x00000} | |
10817 | }, mem_tbl_5705[] = { | |
10818 | { 0x00000100, 0x0000c}, | |
10819 | { 0x00000200, 0x00008}, | |
7942e1db MC |
10820 | { 0x00004000, 0x00800}, |
10821 | { 0x00006000, 0x01000}, | |
10822 | { 0x00008000, 0x02000}, | |
10823 | { 0x00010000, 0x0e000}, | |
10824 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
10825 | }, mem_tbl_5755[] = { |
10826 | { 0x00000200, 0x00008}, | |
10827 | { 0x00004000, 0x00800}, | |
10828 | { 0x00006000, 0x00800}, | |
10829 | { 0x00008000, 0x02000}, | |
10830 | { 0x00010000, 0x0c000}, | |
10831 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
10832 | }, mem_tbl_5906[] = { |
10833 | { 0x00000200, 0x00008}, | |
10834 | { 0x00004000, 0x00400}, | |
10835 | { 0x00006000, 0x00400}, | |
10836 | { 0x00008000, 0x01000}, | |
10837 | { 0x00010000, 0x01000}, | |
10838 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
10839 | }, mem_tbl_5717[] = { |
10840 | { 0x00000200, 0x00008}, | |
10841 | { 0x00010000, 0x0a000}, | |
10842 | { 0x00020000, 0x13c00}, | |
10843 | { 0xffffffff, 0x00000} | |
10844 | }, mem_tbl_57765[] = { | |
10845 | { 0x00000200, 0x00008}, | |
10846 | { 0x00004000, 0x00800}, | |
10847 | { 0x00006000, 0x09800}, | |
10848 | { 0x00010000, 0x0a000}, | |
10849 | { 0xffffffff, 0x00000} | |
7942e1db MC |
10850 | }; |
10851 | struct mem_entry *mem_tbl; | |
10852 | int err = 0; | |
10853 | int i; | |
10854 | ||
0a58d668 | 10855 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
8b5a6c42 MC |
10856 | mem_tbl = mem_tbl_5717; |
10857 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
10858 | mem_tbl = mem_tbl_57765; | |
10859 | else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
321d32a0 MC |
10860 | mem_tbl = mem_tbl_5755; |
10861 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
10862 | mem_tbl = mem_tbl_5906; | |
10863 | else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
10864 | mem_tbl = mem_tbl_5705; | |
10865 | else | |
7942e1db MC |
10866 | mem_tbl = mem_tbl_570x; |
10867 | ||
10868 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
be98da6a MC |
10869 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
10870 | if (err) | |
7942e1db MC |
10871 | break; |
10872 | } | |
6aa20a22 | 10873 | |
7942e1db MC |
10874 | return err; |
10875 | } | |
10876 | ||
9f40dead MC |
10877 | #define TG3_MAC_LOOPBACK 0 |
10878 | #define TG3_PHY_LOOPBACK 1 | |
10879 | ||
10880 | static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |
c76949a6 | 10881 | { |
9f40dead | 10882 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
fd2ce37f | 10883 | u32 desc_idx, coal_now; |
c76949a6 MC |
10884 | struct sk_buff *skb, *rx_skb; |
10885 | u8 *tx_data; | |
10886 | dma_addr_t map; | |
10887 | int num_pkts, tx_len, rx_len, i, err; | |
10888 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 10889 | struct tg3_napi *tnapi, *rnapi; |
8fea32b9 | 10890 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
c76949a6 | 10891 | |
c8873405 MC |
10892 | tnapi = &tp->napi[0]; |
10893 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 10894 | if (tp->irq_cnt > 1) { |
1da85aa3 MC |
10895 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
10896 | rnapi = &tp->napi[1]; | |
c8873405 MC |
10897 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
10898 | tnapi = &tp->napi[1]; | |
0c1d0e2b | 10899 | } |
fd2ce37f | 10900 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 10901 | |
9f40dead | 10902 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
c94e3941 MC |
10903 | /* HW errata - mac loopback fails in some cases on 5780. |
10904 | * Normal traffic and PHY loopback are not affected by | |
aba49f24 MC |
10905 | * errata. Also, the MAC loopback test is deprecated for |
10906 | * all newer ASIC revisions. | |
c94e3941 | 10907 | */ |
aba49f24 MC |
10908 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
10909 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) | |
c94e3941 MC |
10910 | return 0; |
10911 | ||
49692ca1 MC |
10912 | mac_mode = tp->mac_mode & |
10913 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
10914 | mac_mode |= MAC_MODE_PORT_INT_LPBACK; | |
e8f3f6ca MC |
10915 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
10916 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
f07e9af3 | 10917 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
3f7045c1 MC |
10918 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
10919 | else | |
10920 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9f40dead MC |
10921 | tw32(MAC_MODE, mac_mode); |
10922 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | |
3f7045c1 MC |
10923 | u32 val; |
10924 | ||
f07e9af3 | 10925 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
7f97a4bd | 10926 | tg3_phy_fet_toggle_apd(tp, false); |
5d64ad34 MC |
10927 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
10928 | } else | |
10929 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 10930 | |
9ef8ca99 MC |
10931 | tg3_phy_toggle_automdix(tp, 0); |
10932 | ||
3f7045c1 | 10933 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 10934 | udelay(40); |
5d64ad34 | 10935 | |
49692ca1 MC |
10936 | mac_mode = tp->mac_mode & |
10937 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
f07e9af3 | 10938 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
1061b7c5 MC |
10939 | tg3_writephy(tp, MII_TG3_FET_PTEST, |
10940 | MII_TG3_FET_PTEST_FRC_TX_LINK | | |
10941 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
10942 | /* The write needs to be flushed for the AC131 */ | |
10943 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
10944 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
5d64ad34 MC |
10945 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
10946 | } else | |
10947 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 10948 | |
c94e3941 | 10949 | /* reset to prevent losing 1st rx packet intermittently */ |
f07e9af3 | 10950 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
c94e3941 MC |
10951 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
10952 | udelay(10); | |
10953 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
10954 | } | |
e8f3f6ca | 10955 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
79eb6904 MC |
10956 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
10957 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
e8f3f6ca | 10958 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
79eb6904 | 10959 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) |
e8f3f6ca | 10960 | mac_mode |= MAC_MODE_LINK_POLARITY; |
ff18ff02 MC |
10961 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
10962 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
10963 | } | |
9f40dead | 10964 | tw32(MAC_MODE, mac_mode); |
49692ca1 MC |
10965 | |
10966 | /* Wait for link */ | |
10967 | for (i = 0; i < 100; i++) { | |
10968 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
10969 | break; | |
10970 | mdelay(1); | |
10971 | } | |
859a5887 | 10972 | } else { |
9f40dead | 10973 | return -EINVAL; |
859a5887 | 10974 | } |
c76949a6 MC |
10975 | |
10976 | err = -EIO; | |
10977 | ||
c76949a6 | 10978 | tx_len = 1514; |
a20e9c62 | 10979 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
10980 | if (!skb) |
10981 | return -ENOMEM; | |
10982 | ||
c76949a6 MC |
10983 | tx_data = skb_put(skb, tx_len); |
10984 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
10985 | memset(tx_data + 6, 0x0, 8); | |
10986 | ||
10987 | tw32(MAC_RX_MTU_SIZE, tx_len + 4); | |
10988 | ||
10989 | for (i = 14; i < tx_len; i++) | |
10990 | tx_data[i] = (u8) (i & 0xff); | |
10991 | ||
f4188d8a AD |
10992 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
10993 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
10994 | dev_kfree_skb(skb); |
10995 | return -EIO; | |
10996 | } | |
c76949a6 MC |
10997 | |
10998 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 10999 | rnapi->coal_now); |
c76949a6 MC |
11000 | |
11001 | udelay(10); | |
11002 | ||
898a56f8 | 11003 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 11004 | |
c76949a6 MC |
11005 | num_pkts = 0; |
11006 | ||
f4188d8a | 11007 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1); |
c76949a6 | 11008 | |
f3f3f27e | 11009 | tnapi->tx_prod++; |
c76949a6 MC |
11010 | num_pkts++; |
11011 | ||
f3f3f27e MC |
11012 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
11013 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
11014 | |
11015 | udelay(10); | |
11016 | ||
303fc921 MC |
11017 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
11018 | for (i = 0; i < 35; i++) { | |
c76949a6 | 11019 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 11020 | coal_now); |
c76949a6 MC |
11021 | |
11022 | udelay(10); | |
11023 | ||
898a56f8 MC |
11024 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
11025 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 11026 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
11027 | (rx_idx == (rx_start_idx + num_pkts))) |
11028 | break; | |
11029 | } | |
11030 | ||
f4188d8a | 11031 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); |
c76949a6 MC |
11032 | dev_kfree_skb(skb); |
11033 | ||
f3f3f27e | 11034 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
11035 | goto out; |
11036 | ||
11037 | if (rx_idx != rx_start_idx + num_pkts) | |
11038 | goto out; | |
11039 | ||
72334482 | 11040 | desc = &rnapi->rx_rcb[rx_start_idx]; |
c76949a6 MC |
11041 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
11042 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
11043 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
11044 | goto out; | |
11045 | ||
11046 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
11047 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
11048 | goto out; | |
11049 | ||
11050 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; | |
11051 | if (rx_len != tx_len) | |
11052 | goto out; | |
11053 | ||
21f581a5 | 11054 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; |
c76949a6 | 11055 | |
4e5e4f0d | 11056 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping); |
c76949a6 MC |
11057 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); |
11058 | ||
11059 | for (i = 14; i < tx_len; i++) { | |
11060 | if (*(rx_skb->data + i) != (u8) (i & 0xff)) | |
11061 | goto out; | |
11062 | } | |
11063 | err = 0; | |
6aa20a22 | 11064 | |
c76949a6 MC |
11065 | /* tg3_free_rings will unmap and free the rx_skb */ |
11066 | out: | |
11067 | return err; | |
11068 | } | |
11069 | ||
9f40dead MC |
11070 | #define TG3_MAC_LOOPBACK_FAILED 1 |
11071 | #define TG3_PHY_LOOPBACK_FAILED 2 | |
11072 | #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \ | |
11073 | TG3_PHY_LOOPBACK_FAILED) | |
11074 | ||
11075 | static int tg3_test_loopback(struct tg3 *tp) | |
11076 | { | |
11077 | int err = 0; | |
ab789046 | 11078 | u32 eee_cap, cpmuctrl = 0; |
9f40dead MC |
11079 | |
11080 | if (!netif_running(tp->dev)) | |
11081 | return TG3_LOOPBACK_FAILED; | |
11082 | ||
ab789046 MC |
11083 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
11084 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | |
11085 | ||
b9ec6c1b | 11086 | err = tg3_reset_hw(tp, 1); |
ab789046 MC |
11087 | if (err) { |
11088 | err = TG3_LOOPBACK_FAILED; | |
11089 | goto done; | |
11090 | } | |
9f40dead | 11091 | |
6833c043 | 11092 | /* Turn off gphy autopowerdown. */ |
f07e9af3 | 11093 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11094 | tg3_phy_toggle_apd(tp, false); |
11095 | ||
321d32a0 | 11096 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
11097 | int i; |
11098 | u32 status; | |
11099 | ||
11100 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
11101 | ||
11102 | /* Wait for up to 40 microseconds to acquire lock. */ | |
11103 | for (i = 0; i < 4; i++) { | |
11104 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
11105 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
11106 | break; | |
11107 | udelay(10); | |
11108 | } | |
11109 | ||
ab789046 MC |
11110 | if (status != CPMU_MUTEX_GNT_DRIVER) { |
11111 | err = TG3_LOOPBACK_FAILED; | |
11112 | goto done; | |
11113 | } | |
9936bcf6 | 11114 | |
b2a5c19c | 11115 | /* Turn off link-based power management. */ |
e875093c | 11116 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
109115e1 MC |
11117 | tw32(TG3_CPMU_CTRL, |
11118 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
11119 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9936bcf6 MC |
11120 | } |
11121 | ||
9f40dead MC |
11122 | if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) |
11123 | err |= TG3_MAC_LOOPBACK_FAILED; | |
9936bcf6 | 11124 | |
321d32a0 | 11125 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
11126 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
11127 | ||
11128 | /* Release the mutex */ | |
11129 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
11130 | } | |
11131 | ||
f07e9af3 | 11132 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
dd477003 | 11133 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
9f40dead MC |
11134 | if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) |
11135 | err |= TG3_PHY_LOOPBACK_FAILED; | |
11136 | } | |
11137 | ||
6833c043 | 11138 | /* Re-enable gphy autopowerdown. */ |
f07e9af3 | 11139 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
6833c043 MC |
11140 | tg3_phy_toggle_apd(tp, true); |
11141 | ||
ab789046 MC |
11142 | done: |
11143 | tp->phy_flags |= eee_cap; | |
11144 | ||
9f40dead MC |
11145 | return err; |
11146 | } | |
11147 | ||
4cafd3f5 MC |
11148 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
11149 | u64 *data) | |
11150 | { | |
566f86ad MC |
11151 | struct tg3 *tp = netdev_priv(dev); |
11152 | ||
80096068 | 11153 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11154 | tg3_power_up(tp); |
bc1c7567 | 11155 | |
566f86ad MC |
11156 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
11157 | ||
11158 | if (tg3_test_nvram(tp) != 0) { | |
11159 | etest->flags |= ETH_TEST_FL_FAILED; | |
11160 | data[0] = 1; | |
11161 | } | |
ca43007a MC |
11162 | if (tg3_test_link(tp) != 0) { |
11163 | etest->flags |= ETH_TEST_FL_FAILED; | |
11164 | data[1] = 1; | |
11165 | } | |
a71116d1 | 11166 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 11167 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
11168 | |
11169 | if (netif_running(dev)) { | |
b02fd9e3 | 11170 | tg3_phy_stop(tp); |
a71116d1 | 11171 | tg3_netif_stop(tp); |
bbe832c0 MC |
11172 | irq_sync = 1; |
11173 | } | |
a71116d1 | 11174 | |
bbe832c0 | 11175 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
11176 | |
11177 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 11178 | err = tg3_nvram_lock(tp); |
a71116d1 MC |
11179 | tg3_halt_cpu(tp, RX_CPU_BASE); |
11180 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
11181 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
ec41c7df MC |
11182 | if (!err) |
11183 | tg3_nvram_unlock(tp); | |
a71116d1 | 11184 | |
f07e9af3 | 11185 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
d9ab5ad1 MC |
11186 | tg3_phy_reset(tp); |
11187 | ||
a71116d1 MC |
11188 | if (tg3_test_registers(tp) != 0) { |
11189 | etest->flags |= ETH_TEST_FL_FAILED; | |
11190 | data[2] = 1; | |
11191 | } | |
7942e1db MC |
11192 | if (tg3_test_memory(tp) != 0) { |
11193 | etest->flags |= ETH_TEST_FL_FAILED; | |
11194 | data[3] = 1; | |
11195 | } | |
9f40dead | 11196 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 11197 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 11198 | |
f47c11ee DM |
11199 | tg3_full_unlock(tp); |
11200 | ||
d4bc3927 MC |
11201 | if (tg3_test_interrupt(tp) != 0) { |
11202 | etest->flags |= ETH_TEST_FL_FAILED; | |
11203 | data[5] = 1; | |
11204 | } | |
f47c11ee DM |
11205 | |
11206 | tg3_full_lock(tp, 0); | |
d4bc3927 | 11207 | |
a71116d1 MC |
11208 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
11209 | if (netif_running(dev)) { | |
11210 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
b02fd9e3 MC |
11211 | err2 = tg3_restart_hw(tp, 1); |
11212 | if (!err2) | |
b9ec6c1b | 11213 | tg3_netif_start(tp); |
a71116d1 | 11214 | } |
f47c11ee DM |
11215 | |
11216 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
11217 | |
11218 | if (irq_sync && !err2) | |
11219 | tg3_phy_start(tp); | |
a71116d1 | 11220 | } |
80096068 | 11221 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
c866b7ea | 11222 | tg3_power_down(tp); |
bc1c7567 | 11223 | |
4cafd3f5 MC |
11224 | } |
11225 | ||
1da177e4 LT |
11226 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
11227 | { | |
11228 | struct mii_ioctl_data *data = if_mii(ifr); | |
11229 | struct tg3 *tp = netdev_priv(dev); | |
11230 | int err; | |
11231 | ||
b02fd9e3 | 11232 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 11233 | struct phy_device *phydev; |
f07e9af3 | 11234 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
b02fd9e3 | 11235 | return -EAGAIN; |
3f0e3ad7 | 11236 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
28b04113 | 11237 | return phy_mii_ioctl(phydev, ifr, cmd); |
b02fd9e3 MC |
11238 | } |
11239 | ||
33f401ae | 11240 | switch (cmd) { |
1da177e4 | 11241 | case SIOCGMIIPHY: |
882e9793 | 11242 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
11243 | |
11244 | /* fallthru */ | |
11245 | case SIOCGMIIREG: { | |
11246 | u32 mii_regval; | |
11247 | ||
f07e9af3 | 11248 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11249 | break; /* We have no PHY */ |
11250 | ||
f746a313 MC |
11251 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) || |
11252 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
11253 | !netif_running(dev))) | |
bc1c7567 MC |
11254 | return -EAGAIN; |
11255 | ||
f47c11ee | 11256 | spin_lock_bh(&tp->lock); |
1da177e4 | 11257 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 11258 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11259 | |
11260 | data->val_out = mii_regval; | |
11261 | ||
11262 | return err; | |
11263 | } | |
11264 | ||
11265 | case SIOCSMIIREG: | |
f07e9af3 | 11266 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
11267 | break; /* We have no PHY */ |
11268 | ||
f746a313 MC |
11269 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) || |
11270 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && | |
11271 | !netif_running(dev))) | |
bc1c7567 MC |
11272 | return -EAGAIN; |
11273 | ||
f47c11ee | 11274 | spin_lock_bh(&tp->lock); |
1da177e4 | 11275 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 11276 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
11277 | |
11278 | return err; | |
11279 | ||
11280 | default: | |
11281 | /* do nothing */ | |
11282 | break; | |
11283 | } | |
11284 | return -EOPNOTSUPP; | |
11285 | } | |
11286 | ||
15f9850d DM |
11287 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11288 | { | |
11289 | struct tg3 *tp = netdev_priv(dev); | |
11290 | ||
11291 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
11292 | return 0; | |
11293 | } | |
11294 | ||
d244c892 MC |
11295 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
11296 | { | |
11297 | struct tg3 *tp = netdev_priv(dev); | |
11298 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
11299 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11300 | ||
11301 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
11302 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
11303 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11304 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11305 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11306 | } | |
11307 | ||
11308 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11309 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11310 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11311 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11312 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11313 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11314 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11315 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11316 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11317 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11318 | return -EINVAL; | |
11319 | ||
11320 | /* No rx interrupts will be generated if both are zero */ | |
11321 | if ((ec->rx_coalesce_usecs == 0) && | |
11322 | (ec->rx_max_coalesced_frames == 0)) | |
11323 | return -EINVAL; | |
11324 | ||
11325 | /* No tx interrupts will be generated if both are zero */ | |
11326 | if ((ec->tx_coalesce_usecs == 0) && | |
11327 | (ec->tx_max_coalesced_frames == 0)) | |
11328 | return -EINVAL; | |
11329 | ||
11330 | /* Only copy relevant parameters, ignore all others. */ | |
11331 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11332 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11333 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11334 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11335 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11336 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11337 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11338 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11339 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11340 | ||
11341 | if (netif_running(dev)) { | |
11342 | tg3_full_lock(tp, 0); | |
11343 | __tg3_set_coalesce(tp, &tp->coal); | |
11344 | tg3_full_unlock(tp); | |
11345 | } | |
11346 | return 0; | |
11347 | } | |
11348 | ||
7282d491 | 11349 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11350 | .get_settings = tg3_get_settings, |
11351 | .set_settings = tg3_set_settings, | |
11352 | .get_drvinfo = tg3_get_drvinfo, | |
11353 | .get_regs_len = tg3_get_regs_len, | |
11354 | .get_regs = tg3_get_regs, | |
11355 | .get_wol = tg3_get_wol, | |
11356 | .set_wol = tg3_set_wol, | |
11357 | .get_msglevel = tg3_get_msglevel, | |
11358 | .set_msglevel = tg3_set_msglevel, | |
11359 | .nway_reset = tg3_nway_reset, | |
11360 | .get_link = ethtool_op_get_link, | |
11361 | .get_eeprom_len = tg3_get_eeprom_len, | |
11362 | .get_eeprom = tg3_get_eeprom, | |
11363 | .set_eeprom = tg3_set_eeprom, | |
11364 | .get_ringparam = tg3_get_ringparam, | |
11365 | .set_ringparam = tg3_set_ringparam, | |
11366 | .get_pauseparam = tg3_get_pauseparam, | |
11367 | .set_pauseparam = tg3_set_pauseparam, | |
11368 | .get_rx_csum = tg3_get_rx_csum, | |
11369 | .set_rx_csum = tg3_set_rx_csum, | |
1da177e4 | 11370 | .set_tx_csum = tg3_set_tx_csum, |
1da177e4 | 11371 | .set_sg = ethtool_op_set_sg, |
1da177e4 | 11372 | .set_tso = tg3_set_tso, |
4cafd3f5 | 11373 | .self_test = tg3_self_test, |
1da177e4 | 11374 | .get_strings = tg3_get_strings, |
4009a93d | 11375 | .phys_id = tg3_phys_id, |
1da177e4 | 11376 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11377 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11378 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11379 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11380 | }; |
11381 | ||
11382 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11383 | { | |
1b27777a | 11384 | u32 cursize, val, magic; |
1da177e4 LT |
11385 | |
11386 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11387 | ||
e4f34110 | 11388 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11389 | return; |
11390 | ||
b16250e3 MC |
11391 | if ((magic != TG3_EEPROM_MAGIC) && |
11392 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11393 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11394 | return; |
11395 | ||
11396 | /* | |
11397 | * Size the chip by reading offsets at increasing powers of two. | |
11398 | * When we encounter our validation signature, we know the addressing | |
11399 | * has wrapped around, and thus have our chip size. | |
11400 | */ | |
1b27777a | 11401 | cursize = 0x10; |
1da177e4 LT |
11402 | |
11403 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11404 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11405 | return; |
11406 | ||
1820180b | 11407 | if (val == magic) |
1da177e4 LT |
11408 | break; |
11409 | ||
11410 | cursize <<= 1; | |
11411 | } | |
11412 | ||
11413 | tp->nvram_size = cursize; | |
11414 | } | |
6aa20a22 | 11415 | |
1da177e4 LT |
11416 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11417 | { | |
11418 | u32 val; | |
11419 | ||
df259d8c MC |
11420 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
11421 | tg3_nvram_read(tp, 0, &val) != 0) | |
1b27777a MC |
11422 | return; |
11423 | ||
11424 | /* Selfboot format */ | |
1820180b | 11425 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11426 | tg3_get_eeprom_size(tp); |
11427 | return; | |
11428 | } | |
11429 | ||
6d348f2c | 11430 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 11431 | if (val != 0) { |
6d348f2c MC |
11432 | /* This is confusing. We want to operate on the |
11433 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11434 | * call will read from NVRAM and byteswap the data | |
11435 | * according to the byteswapping settings for all | |
11436 | * other register accesses. This ensures the data we | |
11437 | * want will always reside in the lower 16-bits. | |
11438 | * However, the data in NVRAM is in LE format, which | |
11439 | * means the data from the NVRAM read will always be | |
11440 | * opposite the endianness of the CPU. The 16-bit | |
11441 | * byteswap then brings the data to CPU endianness. | |
11442 | */ | |
11443 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
11444 | return; |
11445 | } | |
11446 | } | |
fd1122a2 | 11447 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
11448 | } |
11449 | ||
11450 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11451 | { | |
11452 | u32 nvcfg1; | |
11453 | ||
11454 | nvcfg1 = tr32(NVRAM_CFG1); | |
11455 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
11456 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
8590a603 | 11457 | } else { |
1da177e4 LT |
11458 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11459 | tw32(NVRAM_CFG1, nvcfg1); | |
11460 | } | |
11461 | ||
4c987487 | 11462 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || |
a4e2b347 | 11463 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 | 11464 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
11465 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
11466 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11467 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11468 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11469 | break; | |
11470 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11471 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11472 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11473 | break; | |
11474 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11475 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11476 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11477 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11478 | break; | |
11479 | case FLASH_VENDOR_ST: | |
11480 | tp->nvram_jedecnum = JEDEC_ST; | |
11481 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
11482 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11483 | break; | |
11484 | case FLASH_VENDOR_SAIFUN: | |
11485 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11486 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11487 | break; | |
11488 | case FLASH_VENDOR_SST_SMALL: | |
11489 | case FLASH_VENDOR_SST_LARGE: | |
11490 | tp->nvram_jedecnum = JEDEC_SST; | |
11491 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11492 | break; | |
1da177e4 | 11493 | } |
8590a603 | 11494 | } else { |
1da177e4 LT |
11495 | tp->nvram_jedecnum = JEDEC_ATMEL; |
11496 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11497 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11498 | } | |
11499 | } | |
11500 | ||
a1b950d5 MC |
11501 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
11502 | { | |
11503 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11504 | case FLASH_5752PAGE_SIZE_256: | |
11505 | tp->nvram_pagesize = 256; | |
11506 | break; | |
11507 | case FLASH_5752PAGE_SIZE_512: | |
11508 | tp->nvram_pagesize = 512; | |
11509 | break; | |
11510 | case FLASH_5752PAGE_SIZE_1K: | |
11511 | tp->nvram_pagesize = 1024; | |
11512 | break; | |
11513 | case FLASH_5752PAGE_SIZE_2K: | |
11514 | tp->nvram_pagesize = 2048; | |
11515 | break; | |
11516 | case FLASH_5752PAGE_SIZE_4K: | |
11517 | tp->nvram_pagesize = 4096; | |
11518 | break; | |
11519 | case FLASH_5752PAGE_SIZE_264: | |
11520 | tp->nvram_pagesize = 264; | |
11521 | break; | |
11522 | case FLASH_5752PAGE_SIZE_528: | |
11523 | tp->nvram_pagesize = 528; | |
11524 | break; | |
11525 | } | |
11526 | } | |
11527 | ||
361b4ac2 MC |
11528 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
11529 | { | |
11530 | u32 nvcfg1; | |
11531 | ||
11532 | nvcfg1 = tr32(NVRAM_CFG1); | |
11533 | ||
e6af301b MC |
11534 | /* NVRAM protection for TPM */ |
11535 | if (nvcfg1 & (1 << 27)) | |
f66a29b0 | 11536 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
e6af301b | 11537 | |
361b4ac2 | 11538 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
11539 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
11540 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11541 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11542 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11543 | break; | |
11544 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11545 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11546 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11547 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11548 | break; | |
11549 | case FLASH_5752VENDOR_ST_M45PE10: | |
11550 | case FLASH_5752VENDOR_ST_M45PE20: | |
11551 | case FLASH_5752VENDOR_ST_M45PE40: | |
11552 | tp->nvram_jedecnum = JEDEC_ST; | |
11553 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11554 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11555 | break; | |
361b4ac2 MC |
11556 | } |
11557 | ||
11558 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | |
a1b950d5 | 11559 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 11560 | } else { |
361b4ac2 MC |
11561 | /* For eeprom, set pagesize to maximum eeprom size */ |
11562 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11563 | ||
11564 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11565 | tw32(NVRAM_CFG1, nvcfg1); | |
11566 | } | |
11567 | } | |
11568 | ||
d3c7b886 MC |
11569 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
11570 | { | |
989a9d23 | 11571 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
11572 | |
11573 | nvcfg1 = tr32(NVRAM_CFG1); | |
11574 | ||
11575 | /* NVRAM protection for TPM */ | |
989a9d23 | 11576 | if (nvcfg1 & (1 << 27)) { |
f66a29b0 | 11577 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
989a9d23 MC |
11578 | protect = 1; |
11579 | } | |
d3c7b886 | 11580 | |
989a9d23 MC |
11581 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
11582 | switch (nvcfg1) { | |
8590a603 MC |
11583 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
11584 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11585 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11586 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11587 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11588 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11589 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11590 | tp->nvram_pagesize = 264; | |
11591 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11592 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11593 | tp->nvram_size = (protect ? 0x3e200 : | |
11594 | TG3_NVRAM_SIZE_512KB); | |
11595 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11596 | tp->nvram_size = (protect ? 0x1f200 : | |
11597 | TG3_NVRAM_SIZE_256KB); | |
11598 | else | |
11599 | tp->nvram_size = (protect ? 0x1f200 : | |
11600 | TG3_NVRAM_SIZE_128KB); | |
11601 | break; | |
11602 | case FLASH_5752VENDOR_ST_M45PE10: | |
11603 | case FLASH_5752VENDOR_ST_M45PE20: | |
11604 | case FLASH_5752VENDOR_ST_M45PE40: | |
11605 | tp->nvram_jedecnum = JEDEC_ST; | |
11606 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11607 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11608 | tp->nvram_pagesize = 256; | |
11609 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11610 | tp->nvram_size = (protect ? | |
11611 | TG3_NVRAM_SIZE_64KB : | |
11612 | TG3_NVRAM_SIZE_128KB); | |
11613 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
11614 | tp->nvram_size = (protect ? | |
11615 | TG3_NVRAM_SIZE_64KB : | |
11616 | TG3_NVRAM_SIZE_256KB); | |
11617 | else | |
11618 | tp->nvram_size = (protect ? | |
11619 | TG3_NVRAM_SIZE_128KB : | |
11620 | TG3_NVRAM_SIZE_512KB); | |
11621 | break; | |
d3c7b886 MC |
11622 | } |
11623 | } | |
11624 | ||
1b27777a MC |
11625 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
11626 | { | |
11627 | u32 nvcfg1; | |
11628 | ||
11629 | nvcfg1 = tr32(NVRAM_CFG1); | |
11630 | ||
11631 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
11632 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
11633 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11634 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
11635 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11636 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11637 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11638 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
1b27777a | 11639 | |
8590a603 MC |
11640 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11641 | tw32(NVRAM_CFG1, nvcfg1); | |
11642 | break; | |
11643 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11644 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11645 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11646 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11647 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11648 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11649 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11650 | tp->nvram_pagesize = 264; | |
11651 | break; | |
11652 | case FLASH_5752VENDOR_ST_M45PE10: | |
11653 | case FLASH_5752VENDOR_ST_M45PE20: | |
11654 | case FLASH_5752VENDOR_ST_M45PE40: | |
11655 | tp->nvram_jedecnum = JEDEC_ST; | |
11656 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11657 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11658 | tp->nvram_pagesize = 256; | |
11659 | break; | |
1b27777a MC |
11660 | } |
11661 | } | |
11662 | ||
6b91fa02 MC |
11663 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
11664 | { | |
11665 | u32 nvcfg1, protect = 0; | |
11666 | ||
11667 | nvcfg1 = tr32(NVRAM_CFG1); | |
11668 | ||
11669 | /* NVRAM protection for TPM */ | |
11670 | if (nvcfg1 & (1 << 27)) { | |
f66a29b0 | 11671 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
6b91fa02 MC |
11672 | protect = 1; |
11673 | } | |
11674 | ||
11675 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11676 | switch (nvcfg1) { | |
8590a603 MC |
11677 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
11678 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11679 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11680 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11681 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11682 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11683 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11684 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11685 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11686 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11687 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11688 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
11689 | tp->nvram_pagesize = 256; | |
11690 | break; | |
11691 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11692 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11693 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11694 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11695 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11696 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11697 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11698 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11699 | tp->nvram_jedecnum = JEDEC_ST; | |
11700 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11701 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11702 | tp->nvram_pagesize = 256; | |
11703 | break; | |
6b91fa02 MC |
11704 | } |
11705 | ||
11706 | if (protect) { | |
11707 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
11708 | } else { | |
11709 | switch (nvcfg1) { | |
8590a603 MC |
11710 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
11711 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11712 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11713 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11714 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
11715 | break; | |
11716 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11717 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11718 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11719 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11720 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11721 | break; | |
11722 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11723 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11724 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11725 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11726 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11727 | break; | |
11728 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11729 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11730 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11731 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11732 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11733 | break; | |
6b91fa02 MC |
11734 | } |
11735 | } | |
11736 | } | |
11737 | ||
b5d3772c MC |
11738 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
11739 | { | |
11740 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11741 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11742 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11743 | } | |
11744 | ||
321d32a0 MC |
11745 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
11746 | { | |
11747 | u32 nvcfg1; | |
11748 | ||
11749 | nvcfg1 = tr32(NVRAM_CFG1); | |
11750 | ||
11751 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11752 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11753 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11754 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11755 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11756 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11757 | ||
11758 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11759 | tw32(NVRAM_CFG1, nvcfg1); | |
11760 | return; | |
11761 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11762 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11763 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11764 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11765 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11766 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11767 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11768 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11769 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11770 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11771 | ||
11772 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11773 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11774 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11775 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11776 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11777 | break; | |
11778 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11779 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11780 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11781 | break; | |
11782 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11783 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11784 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11785 | break; | |
11786 | } | |
11787 | break; | |
11788 | case FLASH_5752VENDOR_ST_M45PE10: | |
11789 | case FLASH_5752VENDOR_ST_M45PE20: | |
11790 | case FLASH_5752VENDOR_ST_M45PE40: | |
11791 | tp->nvram_jedecnum = JEDEC_ST; | |
11792 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11793 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11794 | ||
11795 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11796 | case FLASH_5752VENDOR_ST_M45PE10: | |
11797 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11798 | break; | |
11799 | case FLASH_5752VENDOR_ST_M45PE20: | |
11800 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11801 | break; | |
11802 | case FLASH_5752VENDOR_ST_M45PE40: | |
11803 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11804 | break; | |
11805 | } | |
11806 | break; | |
11807 | default: | |
df259d8c | 11808 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; |
321d32a0 MC |
11809 | return; |
11810 | } | |
11811 | ||
a1b950d5 MC |
11812 | tg3_nvram_get_pagesize(tp, nvcfg1); |
11813 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
321d32a0 | 11814 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; |
a1b950d5 MC |
11815 | } |
11816 | ||
11817 | ||
11818 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
11819 | { | |
11820 | u32 nvcfg1; | |
11821 | ||
11822 | nvcfg1 = tr32(NVRAM_CFG1); | |
11823 | ||
11824 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11825 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
11826 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
11827 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11828 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11829 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11830 | ||
11831 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11832 | tw32(NVRAM_CFG1, nvcfg1); | |
11833 | return; | |
11834 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
11835 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
11836 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
11837 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11838 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11839 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11840 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
11841 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11842 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11843 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11844 | ||
11845 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11846 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11847 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11848 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11849 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11850 | break; | |
11851 | default: | |
11852 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11853 | break; | |
11854 | } | |
321d32a0 | 11855 | break; |
a1b950d5 MC |
11856 | case FLASH_5717VENDOR_ST_M_M25PE10: |
11857 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
11858 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
11859 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
11860 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11861 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11862 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11863 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11864 | case FLASH_5717VENDOR_ST_25USPT: | |
11865 | case FLASH_5717VENDOR_ST_45USPT: | |
11866 | tp->nvram_jedecnum = JEDEC_ST; | |
11867 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11868 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11869 | ||
11870 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11871 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11872 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11873 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11874 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11875 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11876 | break; | |
11877 | default: | |
11878 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11879 | break; | |
11880 | } | |
321d32a0 | 11881 | break; |
a1b950d5 MC |
11882 | default: |
11883 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
11884 | return; | |
321d32a0 | 11885 | } |
a1b950d5 MC |
11886 | |
11887 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
11888 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
11889 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
321d32a0 MC |
11890 | } |
11891 | ||
9b91b5f1 MC |
11892 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
11893 | { | |
11894 | u32 nvcfg1, nvmpinstrp; | |
11895 | ||
11896 | nvcfg1 = tr32(NVRAM_CFG1); | |
11897 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | |
11898 | ||
11899 | switch (nvmpinstrp) { | |
11900 | case FLASH_5720_EEPROM_HD: | |
11901 | case FLASH_5720_EEPROM_LD: | |
11902 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11903 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11904 | ||
11905 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11906 | tw32(NVRAM_CFG1, nvcfg1); | |
11907 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) | |
11908 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11909 | else | |
11910 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; | |
11911 | return; | |
11912 | case FLASH_5720VENDOR_M_ATMEL_DB011D: | |
11913 | case FLASH_5720VENDOR_A_ATMEL_DB011B: | |
11914 | case FLASH_5720VENDOR_A_ATMEL_DB011D: | |
11915 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
11916 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
11917 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
11918 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
11919 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
11920 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
11921 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
11922 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
11923 | case FLASH_5720VENDOR_ATMEL_45USPT: | |
11924 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11925 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11926 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11927 | ||
11928 | switch (nvmpinstrp) { | |
11929 | case FLASH_5720VENDOR_M_ATMEL_DB021D: | |
11930 | case FLASH_5720VENDOR_A_ATMEL_DB021B: | |
11931 | case FLASH_5720VENDOR_A_ATMEL_DB021D: | |
11932 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11933 | break; | |
11934 | case FLASH_5720VENDOR_M_ATMEL_DB041D: | |
11935 | case FLASH_5720VENDOR_A_ATMEL_DB041B: | |
11936 | case FLASH_5720VENDOR_A_ATMEL_DB041D: | |
11937 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11938 | break; | |
11939 | case FLASH_5720VENDOR_M_ATMEL_DB081D: | |
11940 | case FLASH_5720VENDOR_A_ATMEL_DB081D: | |
11941 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11942 | break; | |
11943 | default: | |
11944 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11945 | break; | |
11946 | } | |
11947 | break; | |
11948 | case FLASH_5720VENDOR_M_ST_M25PE10: | |
11949 | case FLASH_5720VENDOR_M_ST_M45PE10: | |
11950 | case FLASH_5720VENDOR_A_ST_M25PE10: | |
11951 | case FLASH_5720VENDOR_A_ST_M45PE10: | |
11952 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
11953 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
11954 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
11955 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
11956 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
11957 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
11958 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
11959 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
11960 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
11961 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
11962 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
11963 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
11964 | case FLASH_5720VENDOR_ST_25USPT: | |
11965 | case FLASH_5720VENDOR_ST_45USPT: | |
11966 | tp->nvram_jedecnum = JEDEC_ST; | |
11967 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11968 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11969 | ||
11970 | switch (nvmpinstrp) { | |
11971 | case FLASH_5720VENDOR_M_ST_M25PE20: | |
11972 | case FLASH_5720VENDOR_M_ST_M45PE20: | |
11973 | case FLASH_5720VENDOR_A_ST_M25PE20: | |
11974 | case FLASH_5720VENDOR_A_ST_M45PE20: | |
11975 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11976 | break; | |
11977 | case FLASH_5720VENDOR_M_ST_M25PE40: | |
11978 | case FLASH_5720VENDOR_M_ST_M45PE40: | |
11979 | case FLASH_5720VENDOR_A_ST_M25PE40: | |
11980 | case FLASH_5720VENDOR_A_ST_M45PE40: | |
11981 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11982 | break; | |
11983 | case FLASH_5720VENDOR_M_ST_M25PE80: | |
11984 | case FLASH_5720VENDOR_M_ST_M45PE80: | |
11985 | case FLASH_5720VENDOR_A_ST_M25PE80: | |
11986 | case FLASH_5720VENDOR_A_ST_M45PE80: | |
11987 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11988 | break; | |
11989 | default: | |
11990 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11991 | break; | |
11992 | } | |
11993 | break; | |
11994 | default: | |
11995 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
11996 | return; | |
11997 | } | |
11998 | ||
11999 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
12000 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
12001 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
12002 | } | |
12003 | ||
1da177e4 LT |
12004 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
12005 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
12006 | { | |
1da177e4 LT |
12007 | tw32_f(GRC_EEPROM_ADDR, |
12008 | (EEPROM_ADDR_FSM_RESET | | |
12009 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
12010 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
12011 | ||
9d57f01c | 12012 | msleep(1); |
1da177e4 LT |
12013 | |
12014 | /* Enable seeprom accesses. */ | |
12015 | tw32_f(GRC_LOCAL_CTRL, | |
12016 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
12017 | udelay(100); | |
12018 | ||
12019 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
12020 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
12021 | tp->tg3_flags |= TG3_FLAG_NVRAM; | |
12022 | ||
ec41c7df | 12023 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
12024 | netdev_warn(tp->dev, |
12025 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 12026 | __func__); |
ec41c7df MC |
12027 | return; |
12028 | } | |
e6af301b | 12029 | tg3_enable_nvram_access(tp); |
1da177e4 | 12030 | |
989a9d23 MC |
12031 | tp->nvram_size = 0; |
12032 | ||
361b4ac2 MC |
12033 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
12034 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
12035 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
12036 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 12037 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
12038 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
12039 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 12040 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
12041 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
12042 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
12043 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12044 | tg3_get_5906_nvram_info(tp); | |
b703df6f MC |
12045 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12046 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 | 12047 | tg3_get_57780_nvram_info(tp); |
9b91b5f1 MC |
12048 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12049 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | |
a1b950d5 | 12050 | tg3_get_5717_nvram_info(tp); |
9b91b5f1 MC |
12051 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
12052 | tg3_get_5720_nvram_info(tp); | |
361b4ac2 MC |
12053 | else |
12054 | tg3_get_nvram_info(tp); | |
12055 | ||
989a9d23 MC |
12056 | if (tp->nvram_size == 0) |
12057 | tg3_get_nvram_size(tp); | |
1da177e4 | 12058 | |
e6af301b | 12059 | tg3_disable_nvram_access(tp); |
381291b7 | 12060 | tg3_nvram_unlock(tp); |
1da177e4 LT |
12061 | |
12062 | } else { | |
12063 | tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); | |
12064 | ||
12065 | tg3_get_eeprom_size(tp); | |
12066 | } | |
12067 | } | |
12068 | ||
1da177e4 LT |
12069 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
12070 | u32 offset, u32 len, u8 *buf) | |
12071 | { | |
12072 | int i, j, rc = 0; | |
12073 | u32 val; | |
12074 | ||
12075 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 12076 | u32 addr; |
a9dc529d | 12077 | __be32 data; |
1da177e4 LT |
12078 | |
12079 | addr = offset + i; | |
12080 | ||
12081 | memcpy(&data, buf + i, 4); | |
12082 | ||
62cedd11 MC |
12083 | /* |
12084 | * The SEEPROM interface expects the data to always be opposite | |
12085 | * the native endian format. We accomplish this by reversing | |
12086 | * all the operations that would have been performed on the | |
12087 | * data from a call to tg3_nvram_read_be32(). | |
12088 | */ | |
12089 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
12090 | |
12091 | val = tr32(GRC_EEPROM_ADDR); | |
12092 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
12093 | ||
12094 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
12095 | EEPROM_ADDR_READ); | |
12096 | tw32(GRC_EEPROM_ADDR, val | | |
12097 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
12098 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
12099 | EEPROM_ADDR_START | | |
12100 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 12101 | |
9d57f01c | 12102 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
12103 | val = tr32(GRC_EEPROM_ADDR); |
12104 | ||
12105 | if (val & EEPROM_ADDR_COMPLETE) | |
12106 | break; | |
9d57f01c | 12107 | msleep(1); |
1da177e4 LT |
12108 | } |
12109 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
12110 | rc = -EBUSY; | |
12111 | break; | |
12112 | } | |
12113 | } | |
12114 | ||
12115 | return rc; | |
12116 | } | |
12117 | ||
12118 | /* offset and length are dword aligned */ | |
12119 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
12120 | u8 *buf) | |
12121 | { | |
12122 | int ret = 0; | |
12123 | u32 pagesize = tp->nvram_pagesize; | |
12124 | u32 pagemask = pagesize - 1; | |
12125 | u32 nvram_cmd; | |
12126 | u8 *tmp; | |
12127 | ||
12128 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
12129 | if (tmp == NULL) | |
12130 | return -ENOMEM; | |
12131 | ||
12132 | while (len) { | |
12133 | int j; | |
e6af301b | 12134 | u32 phy_addr, page_off, size; |
1da177e4 LT |
12135 | |
12136 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 12137 | |
1da177e4 | 12138 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
12139 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
12140 | (__be32 *) (tmp + j)); | |
12141 | if (ret) | |
1da177e4 LT |
12142 | break; |
12143 | } | |
12144 | if (ret) | |
12145 | break; | |
12146 | ||
c6cdf436 | 12147 | page_off = offset & pagemask; |
1da177e4 LT |
12148 | size = pagesize; |
12149 | if (len < size) | |
12150 | size = len; | |
12151 | ||
12152 | len -= size; | |
12153 | ||
12154 | memcpy(tmp + page_off, buf, size); | |
12155 | ||
12156 | offset = offset + (pagesize - page_off); | |
12157 | ||
e6af301b | 12158 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
12159 | |
12160 | /* | |
12161 | * Before we can erase the flash page, we need | |
12162 | * to issue a special "write enable" command. | |
12163 | */ | |
12164 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12165 | ||
12166 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12167 | break; | |
12168 | ||
12169 | /* Erase the target page */ | |
12170 | tw32(NVRAM_ADDR, phy_addr); | |
12171 | ||
12172 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
12173 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
12174 | ||
c6cdf436 | 12175 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
12176 | break; |
12177 | ||
12178 | /* Issue another write enable to start the write. */ | |
12179 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12180 | ||
12181 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
12182 | break; | |
12183 | ||
12184 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 12185 | __be32 data; |
1da177e4 | 12186 | |
b9fc7dc5 | 12187 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 12188 | |
b9fc7dc5 | 12189 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
12190 | |
12191 | tw32(NVRAM_ADDR, phy_addr + j); | |
12192 | ||
12193 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
12194 | NVRAM_CMD_WR; | |
12195 | ||
12196 | if (j == 0) | |
12197 | nvram_cmd |= NVRAM_CMD_FIRST; | |
12198 | else if (j == (pagesize - 4)) | |
12199 | nvram_cmd |= NVRAM_CMD_LAST; | |
12200 | ||
12201 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12202 | break; | |
12203 | } | |
12204 | if (ret) | |
12205 | break; | |
12206 | } | |
12207 | ||
12208 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
12209 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
12210 | ||
12211 | kfree(tmp); | |
12212 | ||
12213 | return ret; | |
12214 | } | |
12215 | ||
12216 | /* offset and length are dword aligned */ | |
12217 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
12218 | u8 *buf) | |
12219 | { | |
12220 | int i, ret = 0; | |
12221 | ||
12222 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
12223 | u32 page_off, phy_addr, nvram_cmd; |
12224 | __be32 data; | |
1da177e4 LT |
12225 | |
12226 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 12227 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 12228 | |
c6cdf436 | 12229 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 12230 | |
1820180b | 12231 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
12232 | |
12233 | tw32(NVRAM_ADDR, phy_addr); | |
12234 | ||
12235 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
12236 | ||
c6cdf436 | 12237 | if (page_off == 0 || i == 0) |
1da177e4 | 12238 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 12239 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
12240 | nvram_cmd |= NVRAM_CMD_LAST; |
12241 | ||
12242 | if (i == (len - 4)) | |
12243 | nvram_cmd |= NVRAM_CMD_LAST; | |
12244 | ||
321d32a0 MC |
12245 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
12246 | !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
4c987487 MC |
12247 | (tp->nvram_jedecnum == JEDEC_ST) && |
12248 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
12249 | |
12250 | if ((ret = tg3_nvram_exec_cmd(tp, | |
12251 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
12252 | NVRAM_CMD_DONE))) | |
12253 | ||
12254 | break; | |
12255 | } | |
12256 | if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12257 | /* We always do complete word writes to eeprom. */ | |
12258 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
12259 | } | |
12260 | ||
12261 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
12262 | break; | |
12263 | } | |
12264 | return ret; | |
12265 | } | |
12266 | ||
12267 | /* offset and length are dword aligned */ | |
12268 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
12269 | { | |
12270 | int ret; | |
12271 | ||
1da177e4 | 12272 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
314fba34 MC |
12273 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
12274 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
12275 | udelay(40); |
12276 | } | |
12277 | ||
12278 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { | |
12279 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
859a5887 | 12280 | } else { |
1da177e4 LT |
12281 | u32 grc_mode; |
12282 | ||
ec41c7df MC |
12283 | ret = tg3_nvram_lock(tp); |
12284 | if (ret) | |
12285 | return ret; | |
1da177e4 | 12286 | |
e6af301b MC |
12287 | tg3_enable_nvram_access(tp); |
12288 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 12289 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) |
1da177e4 | 12290 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
12291 | |
12292 | grc_mode = tr32(GRC_MODE); | |
12293 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
12294 | ||
12295 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || | |
12296 | !(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
12297 | ||
12298 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
12299 | buf); | |
859a5887 | 12300 | } else { |
1da177e4 LT |
12301 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
12302 | buf); | |
12303 | } | |
12304 | ||
12305 | grc_mode = tr32(GRC_MODE); | |
12306 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
12307 | ||
e6af301b | 12308 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
12309 | tg3_nvram_unlock(tp); |
12310 | } | |
12311 | ||
12312 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
314fba34 | 12313 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
12314 | udelay(40); |
12315 | } | |
12316 | ||
12317 | return ret; | |
12318 | } | |
12319 | ||
12320 | struct subsys_tbl_ent { | |
12321 | u16 subsys_vendor, subsys_devid; | |
12322 | u32 phy_id; | |
12323 | }; | |
12324 | ||
24daf2b0 | 12325 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 12326 | /* Broadcom boards. */ |
24daf2b0 | 12327 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12328 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12329 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12330 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12331 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12332 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
12333 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12334 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
12335 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12336 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12337 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12338 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12339 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
12340 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
12341 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 12342 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12343 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12344 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12345 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12346 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 12347 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 12348 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
12349 | |
12350 | /* 3com boards. */ | |
24daf2b0 | 12351 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12352 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12353 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12354 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12355 | { TG3PCI_SUBVENDOR_ID_3COM, |
12356 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
12357 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 12358 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12359 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 12360 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12361 | |
12362 | /* DELL boards. */ | |
24daf2b0 | 12363 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12364 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12365 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12366 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 12367 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12368 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 12369 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 12370 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
12371 | |
12372 | /* Compaq boards. */ | |
24daf2b0 | 12373 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12374 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12375 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12376 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
12377 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
12378 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
12379 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 12380 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 12381 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 12382 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
12383 | |
12384 | /* IBM boards. */ | |
24daf2b0 MC |
12385 | { TG3PCI_SUBVENDOR_ID_IBM, |
12386 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
12387 | }; |
12388 | ||
24daf2b0 | 12389 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
12390 | { |
12391 | int i; | |
12392 | ||
12393 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
12394 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
12395 | tp->pdev->subsystem_vendor) && | |
12396 | (subsys_id_to_phy_id[i].subsys_devid == | |
12397 | tp->pdev->subsystem_device)) | |
12398 | return &subsys_id_to_phy_id[i]; | |
12399 | } | |
12400 | return NULL; | |
12401 | } | |
12402 | ||
7d0c41ef | 12403 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 12404 | { |
1da177e4 | 12405 | u32 val; |
caf636c7 MC |
12406 | u16 pmcsr; |
12407 | ||
12408 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
12409 | * so need make sure we're in D0. | |
12410 | */ | |
12411 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
12412 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
12413 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
12414 | msleep(1); | |
7d0c41ef MC |
12415 | |
12416 | /* Make sure register accesses (indirect or otherwise) | |
12417 | * will function correctly. | |
12418 | */ | |
12419 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12420 | tp->misc_host_ctrl); | |
1da177e4 | 12421 | |
f49639e6 DM |
12422 | /* The memory arbiter has to be enabled in order for SRAM accesses |
12423 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
12424 | * sure it is enabled, but other entities such as system netboot | |
12425 | * code might disable it. | |
12426 | */ | |
12427 | val = tr32(MEMARB_MODE); | |
12428 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
12429 | ||
79eb6904 | 12430 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12431 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12432 | ||
a85feb8c GZ |
12433 | /* Assume an onboard device and WOL capable by default. */ |
12434 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; | |
72b845e0 | 12435 | |
b5d3772c | 12436 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12437 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
b5d3772c | 12438 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12439 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12440 | } | |
0527ba35 MC |
12441 | val = tr32(VCPU_CFGSHDW); |
12442 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
8ed5d97e | 12443 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; |
0527ba35 | 12444 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
2023276e | 12445 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) |
0527ba35 | 12446 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
05ac4cb7 | 12447 | goto done; |
b5d3772c MC |
12448 | } |
12449 | ||
1da177e4 LT |
12450 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
12451 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12452 | u32 nic_cfg, led_cfg; | |
a9daf367 | 12453 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 12454 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
12455 | |
12456 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12457 | tp->nic_sram_data_cfg = nic_cfg; | |
12458 | ||
12459 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12460 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
12461 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && | |
12462 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && | |
12463 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) && | |
12464 | (ver > 0) && (ver < 0x100)) | |
12465 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12466 | ||
a9daf367 MC |
12467 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
12468 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12469 | ||
1da177e4 LT |
12470 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
12471 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12472 | eeprom_phy_serdes = 1; | |
12473 | ||
12474 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12475 | if (nic_phy_id != 0) { | |
12476 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12477 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12478 | ||
12479 | eeprom_phy_id = (id1 >> 16) << 10; | |
12480 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12481 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12482 | } else | |
12483 | eeprom_phy_id = 0; | |
12484 | ||
7d0c41ef | 12485 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 12486 | if (eeprom_phy_serdes) { |
a50d0796 | 12487 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
f07e9af3 | 12488 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
a50d0796 | 12489 | else |
f07e9af3 | 12490 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
747e8f8b | 12491 | } |
7d0c41ef | 12492 | |
cbf46853 | 12493 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12494 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
12495 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 12496 | else |
1da177e4 LT |
12497 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
12498 | ||
12499 | switch (led_cfg) { | |
12500 | default: | |
12501 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12502 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12503 | break; | |
12504 | ||
12505 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12506 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12507 | break; | |
12508 | ||
12509 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12510 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
12511 | |
12512 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12513 | * read on some older 5700/5701 bootcode. | |
12514 | */ | |
12515 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12516 | ASIC_REV_5700 || | |
12517 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12518 | ASIC_REV_5701) | |
12519 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12520 | ||
1da177e4 LT |
12521 | break; |
12522 | ||
12523 | case SHASTA_EXT_LED_SHARED: | |
12524 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12525 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12526 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12527 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12528 | LED_CTRL_MODE_PHY_2); | |
12529 | break; | |
12530 | ||
12531 | case SHASTA_EXT_LED_MAC: | |
12532 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12533 | break; | |
12534 | ||
12535 | case SHASTA_EXT_LED_COMBO: | |
12536 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12537 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12538 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12539 | LED_CTRL_MODE_PHY_2); | |
12540 | break; | |
12541 | ||
855e1111 | 12542 | } |
1da177e4 LT |
12543 | |
12544 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12545 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12546 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12547 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12548 | ||
b2a5c19c MC |
12549 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
12550 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 12551 | |
9d26e213 | 12552 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
1da177e4 | 12553 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12554 | if ((tp->pdev->subsystem_vendor == |
12555 | PCI_VENDOR_ID_ARIMA) && | |
12556 | (tp->pdev->subsystem_device == 0x205a || | |
12557 | tp->pdev->subsystem_device == 0x2063)) | |
12558 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
12559 | } else { | |
f49639e6 | 12560 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12561 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12562 | } | |
1da177e4 LT |
12563 | |
12564 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
12565 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
cbf46853 | 12566 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12567 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
12568 | } | |
b2b98d4a MC |
12569 | |
12570 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
12571 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
0d3031d9 | 12572 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; |
b2b98d4a | 12573 | |
f07e9af3 | 12574 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
a85feb8c GZ |
12575 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
12576 | tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; | |
1da177e4 | 12577 | |
12dac075 | 12578 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
05ac4cb7 | 12579 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) |
0527ba35 MC |
12580 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
12581 | ||
1da177e4 | 12582 | if (cfg2 & (1 << 17)) |
f07e9af3 | 12583 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
1da177e4 LT |
12584 | |
12585 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
12586 | /* bootcode if bit 18 is set */ | |
12587 | if (cfg2 & (1 << 18)) | |
f07e9af3 | 12588 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
8ed5d97e | 12589 | |
1407deb1 | 12590 | if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) || |
2e1e3291 MC |
12591 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
12592 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) && | |
6833c043 | 12593 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
f07e9af3 | 12594 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
6833c043 | 12595 | |
8c69b1e7 MC |
12596 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
12597 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
1407deb1 | 12598 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
8ed5d97e MC |
12599 | u32 cfg3; |
12600 | ||
12601 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
12602 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
12603 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
12604 | } | |
a9daf367 | 12605 | |
14417063 MC |
12606 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
12607 | tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE; | |
a9daf367 MC |
12608 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
12609 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; | |
12610 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
12611 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; | |
1da177e4 | 12612 | } |
05ac4cb7 | 12613 | done: |
43067ed8 RW |
12614 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
12615 | device_set_wakeup_enable(&tp->pdev->dev, | |
05ac4cb7 | 12616 | tp->tg3_flags & TG3_FLAG_WOL_ENABLE); |
43067ed8 RW |
12617 | else |
12618 | device_set_wakeup_capable(&tp->pdev->dev, false); | |
7d0c41ef MC |
12619 | } |
12620 | ||
b2a5c19c MC |
12621 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
12622 | { | |
12623 | int i; | |
12624 | u32 val; | |
12625 | ||
12626 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
12627 | tw32(OTP_CTRL, cmd); | |
12628 | ||
12629 | /* Wait for up to 1 ms for command to execute. */ | |
12630 | for (i = 0; i < 100; i++) { | |
12631 | val = tr32(OTP_STATUS); | |
12632 | if (val & OTP_STATUS_CMD_DONE) | |
12633 | break; | |
12634 | udelay(10); | |
12635 | } | |
12636 | ||
12637 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
12638 | } | |
12639 | ||
12640 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
12641 | * configuration is a 32-bit value that straddles the alignment boundary. | |
12642 | * We do two 32-bit reads and then shift and merge the results. | |
12643 | */ | |
12644 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
12645 | { | |
12646 | u32 bhalf_otp, thalf_otp; | |
12647 | ||
12648 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
12649 | ||
12650 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
12651 | return 0; | |
12652 | ||
12653 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
12654 | ||
12655 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12656 | return 0; | |
12657 | ||
12658 | thalf_otp = tr32(OTP_READ_DATA); | |
12659 | ||
12660 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
12661 | ||
12662 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12663 | return 0; | |
12664 | ||
12665 | bhalf_otp = tr32(OTP_READ_DATA); | |
12666 | ||
12667 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
12668 | } | |
12669 | ||
e256f8a3 MC |
12670 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
12671 | { | |
12672 | u32 adv = ADVERTISED_Autoneg | | |
12673 | ADVERTISED_Pause; | |
12674 | ||
12675 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | |
12676 | adv |= ADVERTISED_1000baseT_Half | | |
12677 | ADVERTISED_1000baseT_Full; | |
12678 | ||
12679 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
12680 | adv |= ADVERTISED_100baseT_Half | | |
12681 | ADVERTISED_100baseT_Full | | |
12682 | ADVERTISED_10baseT_Half | | |
12683 | ADVERTISED_10baseT_Full | | |
12684 | ADVERTISED_TP; | |
12685 | else | |
12686 | adv |= ADVERTISED_FIBRE; | |
12687 | ||
12688 | tp->link_config.advertising = adv; | |
12689 | tp->link_config.speed = SPEED_INVALID; | |
12690 | tp->link_config.duplex = DUPLEX_INVALID; | |
12691 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
12692 | tp->link_config.active_speed = SPEED_INVALID; | |
12693 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
12694 | tp->link_config.orig_speed = SPEED_INVALID; | |
12695 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
12696 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
12697 | } | |
12698 | ||
7d0c41ef MC |
12699 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
12700 | { | |
12701 | u32 hw_phy_id_1, hw_phy_id_2; | |
12702 | u32 hw_phy_id, hw_phy_id_masked; | |
12703 | int err; | |
1da177e4 | 12704 | |
e256f8a3 MC |
12705 | /* flow control autonegotiation is default behavior */ |
12706 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
12707 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | |
12708 | ||
b02fd9e3 MC |
12709 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
12710 | return tg3_phy_init(tp); | |
12711 | ||
1da177e4 | 12712 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 12713 | * firmware access to the PHY hardware. |
1da177e4 LT |
12714 | */ |
12715 | err = 0; | |
0d3031d9 MC |
12716 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || |
12717 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
79eb6904 | 12718 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
12719 | } else { |
12720 | /* Now read the physical PHY_ID from the chip and verify | |
12721 | * that it is sane. If it doesn't look good, we fall back | |
12722 | * to either the hard-coded table based PHY_ID and failing | |
12723 | * that the value found in the eeprom area. | |
12724 | */ | |
12725 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
12726 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
12727 | ||
12728 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
12729 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
12730 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
12731 | ||
79eb6904 | 12732 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
12733 | } |
12734 | ||
79eb6904 | 12735 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 12736 | tp->phy_id = hw_phy_id; |
79eb6904 | 12737 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
f07e9af3 | 12738 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
da6b2d01 | 12739 | else |
f07e9af3 | 12740 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
1da177e4 | 12741 | } else { |
79eb6904 | 12742 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
12743 | /* Do nothing, phy ID already set up in |
12744 | * tg3_get_eeprom_hw_cfg(). | |
12745 | */ | |
1da177e4 LT |
12746 | } else { |
12747 | struct subsys_tbl_ent *p; | |
12748 | ||
12749 | /* No eeprom signature? Try the hardcoded | |
12750 | * subsys device table. | |
12751 | */ | |
24daf2b0 | 12752 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
12753 | if (!p) |
12754 | return -ENODEV; | |
12755 | ||
12756 | tp->phy_id = p->phy_id; | |
12757 | if (!tp->phy_id || | |
79eb6904 | 12758 | tp->phy_id == TG3_PHY_ID_BCM8002) |
f07e9af3 | 12759 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
1da177e4 LT |
12760 | } |
12761 | } | |
12762 | ||
a6b68dab MC |
12763 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
12764 | ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && | |
12765 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || | |
12766 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
12767 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | |
52b02d04 MC |
12768 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
12769 | ||
e256f8a3 MC |
12770 | tg3_phy_init_link_config(tp); |
12771 | ||
f07e9af3 | 12772 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
0d3031d9 | 12773 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && |
1da177e4 | 12774 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
3600d918 | 12775 | u32 bmsr, adv_reg, tg3_ctrl, mask; |
1da177e4 LT |
12776 | |
12777 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
12778 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
12779 | (bmsr & BMSR_LSTATUS)) | |
12780 | goto skip_phy_reset; | |
6aa20a22 | 12781 | |
1da177e4 LT |
12782 | err = tg3_phy_reset(tp); |
12783 | if (err) | |
12784 | return err; | |
12785 | ||
12786 | adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
12787 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
12788 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
12789 | tg3_ctrl = 0; | |
f07e9af3 | 12790 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
1da177e4 LT |
12791 | tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | |
12792 | MII_TG3_CTRL_ADV_1000_FULL); | |
12793 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
12794 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
12795 | tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER | | |
12796 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
12797 | } | |
12798 | ||
3600d918 MC |
12799 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
12800 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
12801 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
12802 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
1da177e4 LT |
12803 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); |
12804 | ||
f07e9af3 | 12805 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
12806 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); |
12807 | ||
12808 | tg3_writephy(tp, MII_BMCR, | |
12809 | BMCR_ANENABLE | BMCR_ANRESTART); | |
12810 | } | |
12811 | tg3_phy_set_wirespeed(tp); | |
12812 | ||
12813 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
f07e9af3 | 12814 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
1da177e4 LT |
12815 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); |
12816 | } | |
12817 | ||
12818 | skip_phy_reset: | |
79eb6904 | 12819 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
12820 | err = tg3_init_5401phy_dsp(tp); |
12821 | if (err) | |
12822 | return err; | |
1da177e4 | 12823 | |
1da177e4 LT |
12824 | err = tg3_init_5401phy_dsp(tp); |
12825 | } | |
12826 | ||
1da177e4 LT |
12827 | return err; |
12828 | } | |
12829 | ||
184b8904 | 12830 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 12831 | { |
a4a8bb15 | 12832 | u8 *vpd_data; |
4181b2c8 | 12833 | unsigned int block_end, rosize, len; |
184b8904 | 12834 | int j, i = 0; |
1b27777a | 12835 | u32 magic; |
1da177e4 | 12836 | |
df259d8c MC |
12837 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
12838 | tg3_nvram_read(tp, 0x0, &magic)) | |
a4a8bb15 MC |
12839 | goto out_no_vpd; |
12840 | ||
12841 | vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL); | |
12842 | if (!vpd_data) | |
12843 | goto out_no_vpd; | |
1da177e4 | 12844 | |
1820180b | 12845 | if (magic == TG3_EEPROM_MAGIC) { |
141518c9 | 12846 | for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) { |
1b27777a | 12847 | u32 tmp; |
1da177e4 | 12848 | |
6d348f2c MC |
12849 | /* The data is in little-endian format in NVRAM. |
12850 | * Use the big-endian read routines to preserve | |
12851 | * the byte order as it exists in NVRAM. | |
12852 | */ | |
141518c9 | 12853 | if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp)) |
1b27777a MC |
12854 | goto out_not_found; |
12855 | ||
6d348f2c | 12856 | memcpy(&vpd_data[i], &tmp, sizeof(tmp)); |
1b27777a MC |
12857 | } |
12858 | } else { | |
94c982bd | 12859 | ssize_t cnt; |
4181b2c8 | 12860 | unsigned int pos = 0; |
94c982bd MC |
12861 | |
12862 | for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) { | |
12863 | cnt = pci_read_vpd(tp->pdev, pos, | |
12864 | TG3_NVM_VPD_LEN - pos, | |
12865 | &vpd_data[pos]); | |
824f5f38 | 12866 | if (cnt == -ETIMEDOUT || cnt == -EINTR) |
94c982bd MC |
12867 | cnt = 0; |
12868 | else if (cnt < 0) | |
f49639e6 | 12869 | goto out_not_found; |
1b27777a | 12870 | } |
94c982bd MC |
12871 | if (pos != TG3_NVM_VPD_LEN) |
12872 | goto out_not_found; | |
1da177e4 LT |
12873 | } |
12874 | ||
4181b2c8 MC |
12875 | i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN, |
12876 | PCI_VPD_LRDT_RO_DATA); | |
12877 | if (i < 0) | |
12878 | goto out_not_found; | |
1da177e4 | 12879 | |
4181b2c8 MC |
12880 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
12881 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
12882 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 12883 | |
4181b2c8 MC |
12884 | if (block_end > TG3_NVM_VPD_LEN) |
12885 | goto out_not_found; | |
af2c6a4a | 12886 | |
184b8904 MC |
12887 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
12888 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
12889 | if (j > 0) { | |
12890 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
12891 | ||
12892 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12893 | if (j + len > block_end || len != 4 || | |
12894 | memcmp(&vpd_data[j], "1028", 4)) | |
12895 | goto partno; | |
12896 | ||
12897 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
12898 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
12899 | if (j < 0) | |
12900 | goto partno; | |
12901 | ||
12902 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
12903 | ||
12904 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12905 | if (j + len > block_end) | |
12906 | goto partno; | |
12907 | ||
12908 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
12909 | strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1); | |
12910 | } | |
12911 | ||
12912 | partno: | |
4181b2c8 MC |
12913 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
12914 | PCI_VPD_RO_KEYWORD_PARTNO); | |
12915 | if (i < 0) | |
12916 | goto out_not_found; | |
af2c6a4a | 12917 | |
4181b2c8 | 12918 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 12919 | |
4181b2c8 MC |
12920 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
12921 | if (len > TG3_BPN_SIZE || | |
12922 | (len + i) > TG3_NVM_VPD_LEN) | |
12923 | goto out_not_found; | |
1da177e4 | 12924 | |
4181b2c8 | 12925 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 12926 | |
1da177e4 | 12927 | out_not_found: |
a4a8bb15 | 12928 | kfree(vpd_data); |
37a949c5 | 12929 | if (tp->board_part_number[0]) |
a4a8bb15 MC |
12930 | return; |
12931 | ||
12932 | out_no_vpd: | |
37a949c5 MC |
12933 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
12934 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) | |
12935 | strcpy(tp->board_part_number, "BCM5717"); | |
12936 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) | |
12937 | strcpy(tp->board_part_number, "BCM5718"); | |
12938 | else | |
12939 | goto nomatch; | |
12940 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | |
12941 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
12942 | strcpy(tp->board_part_number, "BCM57780"); | |
12943 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
12944 | strcpy(tp->board_part_number, "BCM57760"); | |
12945 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
12946 | strcpy(tp->board_part_number, "BCM57790"); | |
12947 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
12948 | strcpy(tp->board_part_number, "BCM57788"); | |
12949 | else | |
12950 | goto nomatch; | |
12951 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
12952 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
12953 | strcpy(tp->board_part_number, "BCM57761"); | |
12954 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
12955 | strcpy(tp->board_part_number, "BCM57765"); | |
12956 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
12957 | strcpy(tp->board_part_number, "BCM57781"); | |
12958 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
12959 | strcpy(tp->board_part_number, "BCM57785"); | |
12960 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
12961 | strcpy(tp->board_part_number, "BCM57791"); | |
12962 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
12963 | strcpy(tp->board_part_number, "BCM57795"); | |
12964 | else | |
12965 | goto nomatch; | |
12966 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | |
b5d3772c | 12967 | strcpy(tp->board_part_number, "BCM95906"); |
37a949c5 MC |
12968 | } else { |
12969 | nomatch: | |
b5d3772c | 12970 | strcpy(tp->board_part_number, "none"); |
37a949c5 | 12971 | } |
1da177e4 LT |
12972 | } |
12973 | ||
9c8a620e MC |
12974 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
12975 | { | |
12976 | u32 val; | |
12977 | ||
e4f34110 | 12978 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 12979 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 12980 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
12981 | val != 0) |
12982 | return 0; | |
12983 | ||
12984 | return 1; | |
12985 | } | |
12986 | ||
acd9c119 MC |
12987 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
12988 | { | |
ff3a7cb2 | 12989 | u32 val, offset, start, ver_offset; |
75f9936e | 12990 | int i, dst_off; |
ff3a7cb2 | 12991 | bool newver = false; |
acd9c119 MC |
12992 | |
12993 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
12994 | tg3_nvram_read(tp, 0x4, &start)) | |
12995 | return; | |
12996 | ||
12997 | offset = tg3_nvram_logical_addr(tp, offset); | |
12998 | ||
ff3a7cb2 | 12999 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
13000 | return; |
13001 | ||
ff3a7cb2 MC |
13002 | if ((val & 0xfc000000) == 0x0c000000) { |
13003 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
13004 | return; |
13005 | ||
ff3a7cb2 MC |
13006 | if (val == 0) |
13007 | newver = true; | |
13008 | } | |
13009 | ||
75f9936e MC |
13010 | dst_off = strlen(tp->fw_ver); |
13011 | ||
ff3a7cb2 | 13012 | if (newver) { |
75f9936e MC |
13013 | if (TG3_VER_SIZE - dst_off < 16 || |
13014 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
13015 | return; |
13016 | ||
13017 | offset = offset + ver_offset - start; | |
13018 | for (i = 0; i < 16; i += 4) { | |
13019 | __be32 v; | |
13020 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
13021 | return; | |
13022 | ||
75f9936e | 13023 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
13024 | } |
13025 | } else { | |
13026 | u32 major, minor; | |
13027 | ||
13028 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
13029 | return; | |
13030 | ||
13031 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
13032 | TG3_NVM_BCVER_MAJSFT; | |
13033 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
13034 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
13035 | "v%d.%02d", major, minor); | |
acd9c119 MC |
13036 | } |
13037 | } | |
13038 | ||
a6f6cb1c MC |
13039 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
13040 | { | |
13041 | u32 val, major, minor; | |
13042 | ||
13043 | /* Use native endian representation */ | |
13044 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
13045 | return; | |
13046 | ||
13047 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
13048 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
13049 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
13050 | TG3_NVM_HWSB_CFG1_MINSFT; | |
13051 | ||
13052 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
13053 | } | |
13054 | ||
dfe00d7d MC |
13055 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
13056 | { | |
13057 | u32 offset, major, minor, build; | |
13058 | ||
75f9936e | 13059 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
13060 | |
13061 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
13062 | return; | |
13063 | ||
13064 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
13065 | case TG3_EEPROM_SB_REVISION_0: | |
13066 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
13067 | break; | |
13068 | case TG3_EEPROM_SB_REVISION_2: | |
13069 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
13070 | break; | |
13071 | case TG3_EEPROM_SB_REVISION_3: | |
13072 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
13073 | break; | |
a4153d40 MC |
13074 | case TG3_EEPROM_SB_REVISION_4: |
13075 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
13076 | break; | |
13077 | case TG3_EEPROM_SB_REVISION_5: | |
13078 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
13079 | break; | |
bba226ac MC |
13080 | case TG3_EEPROM_SB_REVISION_6: |
13081 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; | |
13082 | break; | |
dfe00d7d MC |
13083 | default: |
13084 | return; | |
13085 | } | |
13086 | ||
e4f34110 | 13087 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
13088 | return; |
13089 | ||
13090 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
13091 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
13092 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
13093 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
13094 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
13095 | ||
13096 | if (minor > 99 || build > 26) | |
13097 | return; | |
13098 | ||
75f9936e MC |
13099 | offset = strlen(tp->fw_ver); |
13100 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
13101 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
13102 | |
13103 | if (build > 0) { | |
75f9936e MC |
13104 | offset = strlen(tp->fw_ver); |
13105 | if (offset < TG3_VER_SIZE - 1) | |
13106 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
13107 | } |
13108 | } | |
13109 | ||
acd9c119 | 13110 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
13111 | { |
13112 | u32 val, offset, start; | |
acd9c119 | 13113 | int i, vlen; |
9c8a620e MC |
13114 | |
13115 | for (offset = TG3_NVM_DIR_START; | |
13116 | offset < TG3_NVM_DIR_END; | |
13117 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 13118 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
13119 | return; |
13120 | ||
9c8a620e MC |
13121 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
13122 | break; | |
13123 | } | |
13124 | ||
13125 | if (offset == TG3_NVM_DIR_END) | |
13126 | return; | |
13127 | ||
13128 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
13129 | start = 0x08000000; | |
e4f34110 | 13130 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
13131 | return; |
13132 | ||
e4f34110 | 13133 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 13134 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 13135 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
13136 | return; |
13137 | ||
13138 | offset += val - start; | |
13139 | ||
acd9c119 | 13140 | vlen = strlen(tp->fw_ver); |
9c8a620e | 13141 | |
acd9c119 MC |
13142 | tp->fw_ver[vlen++] = ','; |
13143 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
13144 | |
13145 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
13146 | __be32 v; |
13147 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
13148 | return; |
13149 | ||
b9fc7dc5 | 13150 | offset += sizeof(v); |
c4e6575c | 13151 | |
acd9c119 MC |
13152 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
13153 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 13154 | break; |
c4e6575c | 13155 | } |
9c8a620e | 13156 | |
acd9c119 MC |
13157 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
13158 | vlen += sizeof(v); | |
c4e6575c | 13159 | } |
acd9c119 MC |
13160 | } |
13161 | ||
7fd76445 MC |
13162 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
13163 | { | |
13164 | int vlen; | |
13165 | u32 apedata; | |
ecc79648 | 13166 | char *fwtype; |
7fd76445 MC |
13167 | |
13168 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || | |
13169 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
13170 | return; | |
13171 | ||
13172 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
13173 | if (apedata != APE_SEG_SIG_MAGIC) | |
13174 | return; | |
13175 | ||
13176 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
13177 | if (!(apedata & APE_FW_STATUS_READY)) | |
13178 | return; | |
13179 | ||
13180 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
13181 | ||
dc6d0744 MC |
13182 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
13183 | tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI; | |
ecc79648 | 13184 | fwtype = "NCSI"; |
dc6d0744 | 13185 | } else { |
ecc79648 | 13186 | fwtype = "DASH"; |
dc6d0744 | 13187 | } |
ecc79648 | 13188 | |
7fd76445 MC |
13189 | vlen = strlen(tp->fw_ver); |
13190 | ||
ecc79648 MC |
13191 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
13192 | fwtype, | |
7fd76445 MC |
13193 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
13194 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
13195 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
13196 | (apedata & APE_FW_VERSION_BLDMSK)); | |
13197 | } | |
13198 | ||
acd9c119 MC |
13199 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
13200 | { | |
13201 | u32 val; | |
75f9936e | 13202 | bool vpd_vers = false; |
acd9c119 | 13203 | |
75f9936e MC |
13204 | if (tp->fw_ver[0] != 0) |
13205 | vpd_vers = true; | |
df259d8c | 13206 | |
75f9936e MC |
13207 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { |
13208 | strcat(tp->fw_ver, "sb"); | |
df259d8c MC |
13209 | return; |
13210 | } | |
13211 | ||
acd9c119 MC |
13212 | if (tg3_nvram_read(tp, 0, &val)) |
13213 | return; | |
13214 | ||
13215 | if (val == TG3_EEPROM_MAGIC) | |
13216 | tg3_read_bc_ver(tp); | |
13217 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
13218 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
13219 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
13220 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
13221 | else |
13222 | return; | |
13223 | ||
13224 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
75f9936e MC |
13225 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers) |
13226 | goto done; | |
acd9c119 MC |
13227 | |
13228 | tg3_read_mgmtfw_ver(tp); | |
9c8a620e | 13229 | |
75f9936e | 13230 | done: |
9c8a620e | 13231 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
13232 | } |
13233 | ||
7544b097 MC |
13234 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
13235 | ||
6303e6e8 | 13236 | static inline void vlan_features_add(struct net_device *dev, unsigned long flags) |
7fe876af | 13237 | { |
7fe876af | 13238 | dev->vlan_features |= flags; |
7fe876af ED |
13239 | } |
13240 | ||
7cb32cf2 MC |
13241 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
13242 | { | |
de9f5230 MC |
13243 | if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) |
13244 | return TG3_RX_RET_MAX_SIZE_5717; | |
7cb32cf2 MC |
13245 | else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
13246 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
de9f5230 | 13247 | return TG3_RX_RET_MAX_SIZE_5700; |
7cb32cf2 | 13248 | else |
de9f5230 | 13249 | return TG3_RX_RET_MAX_SIZE_5705; |
7cb32cf2 MC |
13250 | } |
13251 | ||
4143470c | 13252 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
895950c2 JP |
13253 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
13254 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, | |
13255 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, | |
13256 | { }, | |
13257 | }; | |
13258 | ||
1da177e4 LT |
13259 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
13260 | { | |
1da177e4 | 13261 | u32 misc_ctrl_reg; |
1da177e4 LT |
13262 | u32 pci_state_reg, grc_misc_cfg; |
13263 | u32 val; | |
13264 | u16 pci_cmd; | |
5e7dfd0f | 13265 | int err; |
1da177e4 | 13266 | |
1da177e4 LT |
13267 | /* Force memory write invalidate off. If we leave it on, |
13268 | * then on 5700_BX chips we have to enable a workaround. | |
13269 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
13270 | * to match the cacheline size. The Broadcom driver have this | |
13271 | * workaround but turns MWI off all the times so never uses | |
13272 | * it. This seems to suggest that the workaround is insufficient. | |
13273 | */ | |
13274 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13275 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
13276 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13277 | ||
13278 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
13279 | * has the register indirect write enable bit set before | |
13280 | * we try to access any of the MMIO registers. It is also | |
13281 | * critical that the PCI-X hw workaround situation is decided | |
13282 | * before that as well. | |
13283 | */ | |
13284 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13285 | &misc_ctrl_reg); | |
13286 | ||
13287 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
13288 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
13289 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
13290 | u32 prod_id_asic_rev; | |
13291 | ||
5001e2f6 MC |
13292 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
13293 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
d78b59f5 MC |
13294 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
13295 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) | |
f6eb9b1f MC |
13296 | pci_read_config_dword(tp->pdev, |
13297 | TG3PCI_GEN2_PRODID_ASICREV, | |
13298 | &prod_id_asic_rev); | |
b703df6f MC |
13299 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
13300 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
13301 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
13302 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
13303 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
13304 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
13305 | pci_read_config_dword(tp->pdev, | |
13306 | TG3PCI_GEN15_PRODID_ASICREV, | |
13307 | &prod_id_asic_rev); | |
f6eb9b1f MC |
13308 | else |
13309 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
13310 | &prod_id_asic_rev); | |
13311 | ||
321d32a0 | 13312 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 13313 | } |
1da177e4 | 13314 | |
ff645bec MC |
13315 | /* Wrong chip ID in 5752 A0. This code can be removed later |
13316 | * as A0 is not in production. | |
13317 | */ | |
13318 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
13319 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
13320 | ||
6892914f MC |
13321 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
13322 | * we need to disable memory and use config. cycles | |
13323 | * only to access all registers. The 5702/03 chips | |
13324 | * can mistakenly decode the special cycles from the | |
13325 | * ICH chipsets as memory write cycles, causing corruption | |
13326 | * of register and memory space. Only certain ICH bridges | |
13327 | * will drive special cycles with non-zero data during the | |
13328 | * address phase which can fall within the 5703's address | |
13329 | * range. This is not an ICH bug as the PCI spec allows | |
13330 | * non-zero address during special cycles. However, only | |
13331 | * these ICH bridges are known to drive non-zero addresses | |
13332 | * during special cycles. | |
13333 | * | |
13334 | * Since special cycles do not cross PCI bridges, we only | |
13335 | * enable this workaround if the 5703 is on the secondary | |
13336 | * bus of these ICH bridges. | |
13337 | */ | |
13338 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
13339 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
13340 | static struct tg3_dev_id { | |
13341 | u32 vendor; | |
13342 | u32 device; | |
13343 | u32 rev; | |
13344 | } ich_chipsets[] = { | |
13345 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
13346 | PCI_ANY_ID }, | |
13347 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
13348 | PCI_ANY_ID }, | |
13349 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
13350 | 0xa }, | |
13351 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
13352 | PCI_ANY_ID }, | |
13353 | { }, | |
13354 | }; | |
13355 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
13356 | struct pci_dev *bridge = NULL; | |
13357 | ||
13358 | while (pci_id->vendor != 0) { | |
13359 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
13360 | bridge); | |
13361 | if (!bridge) { | |
13362 | pci_id++; | |
13363 | continue; | |
13364 | } | |
13365 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 13366 | if (bridge->revision > pci_id->rev) |
6892914f MC |
13367 | continue; |
13368 | } | |
13369 | if (bridge->subordinate && | |
13370 | (bridge->subordinate->number == | |
13371 | tp->pdev->bus->number)) { | |
13372 | ||
13373 | tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND; | |
13374 | pci_dev_put(bridge); | |
13375 | break; | |
13376 | } | |
13377 | } | |
13378 | } | |
13379 | ||
41588ba1 MC |
13380 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { |
13381 | static struct tg3_dev_id { | |
13382 | u32 vendor; | |
13383 | u32 device; | |
13384 | } bridge_chipsets[] = { | |
13385 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
13386 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
13387 | { }, | |
13388 | }; | |
13389 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
13390 | struct pci_dev *bridge = NULL; | |
13391 | ||
13392 | while (pci_id->vendor != 0) { | |
13393 | bridge = pci_get_device(pci_id->vendor, | |
13394 | pci_id->device, | |
13395 | bridge); | |
13396 | if (!bridge) { | |
13397 | pci_id++; | |
13398 | continue; | |
13399 | } | |
13400 | if (bridge->subordinate && | |
13401 | (bridge->subordinate->number <= | |
13402 | tp->pdev->bus->number) && | |
13403 | (bridge->subordinate->subordinate >= | |
13404 | tp->pdev->bus->number)) { | |
13405 | tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; | |
13406 | pci_dev_put(bridge); | |
13407 | break; | |
13408 | } | |
13409 | } | |
13410 | } | |
13411 | ||
4a29cc2e MC |
13412 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
13413 | * DMA addresses > 40-bit. This bridge may have other additional | |
13414 | * 57xx devices behind it in some 4-port NIC designs for example. | |
13415 | * Any tg3 device found behind the bridge will also need the 40-bit | |
13416 | * DMA workaround. | |
13417 | */ | |
a4e2b347 MC |
13418 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
13419 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
13420 | tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; | |
4a29cc2e | 13421 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; |
4cf78e4f | 13422 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 13423 | } else { |
4a29cc2e MC |
13424 | struct pci_dev *bridge = NULL; |
13425 | ||
13426 | do { | |
13427 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
13428 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
13429 | bridge); | |
13430 | if (bridge && bridge->subordinate && | |
13431 | (bridge->subordinate->number <= | |
13432 | tp->pdev->bus->number) && | |
13433 | (bridge->subordinate->subordinate >= | |
13434 | tp->pdev->bus->number)) { | |
13435 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
13436 | pci_dev_put(bridge); | |
13437 | break; | |
13438 | } | |
13439 | } while (bridge); | |
13440 | } | |
4cf78e4f | 13441 | |
1da177e4 LT |
13442 | /* Initialize misc host control in PCI block. */ |
13443 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
13444 | MISC_HOST_CTRL_CHIPREV); | |
13445 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13446 | tp->misc_host_ctrl); | |
13447 | ||
f6eb9b1f MC |
13448 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
13449 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
d78b59f5 MC |
13450 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13451 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
7544b097 MC |
13452 | tp->pdev_peer = tg3_find_peer(tp); |
13453 | ||
c885e824 | 13454 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
d78b59f5 MC |
13455 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13456 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
0a58d668 MC |
13457 | tp->tg3_flags3 |= TG3_FLG3_5717_PLUS; |
13458 | ||
13459 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | |
13460 | (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) | |
1407deb1 | 13461 | tp->tg3_flags3 |= TG3_FLG3_57765_PLUS; |
c885e824 | 13462 | |
321d32a0 MC |
13463 | /* Intentionally exclude ASIC_REV_5906 */ |
13464 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 13465 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 13466 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 13467 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 13468 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13469 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
1407deb1 | 13470 | (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) |
321d32a0 MC |
13471 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; |
13472 | ||
13473 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13474 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 13475 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
321d32a0 | 13476 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
a4e2b347 | 13477 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
6708e5cc JL |
13478 | tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; |
13479 | ||
1b440c56 JL |
13480 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || |
13481 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
13482 | tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; | |
13483 | ||
027455ad MC |
13484 | /* 5700 B0 chips do not support checksumming correctly due |
13485 | * to hardware bugs. | |
13486 | */ | |
13487 | if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0) | |
13488 | tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS; | |
13489 | else { | |
7fe876af ED |
13490 | unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO; |
13491 | ||
027455ad | 13492 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; |
027455ad | 13493 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
7fe876af ED |
13494 | features |= NETIF_F_IPV6_CSUM; |
13495 | tp->dev->features |= features; | |
13496 | vlan_features_add(tp->dev, features); | |
027455ad MC |
13497 | } |
13498 | ||
507399f1 | 13499 | /* Determine TSO capabilities */ |
2866d956 | 13500 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
4d163b75 | 13501 | ; /* Do nothing. HW bug. */ |
1407deb1 | 13502 | else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) |
e849cdc3 MC |
13503 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; |
13504 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
13505 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
507399f1 MC |
13506 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; |
13507 | else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
13508 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; | |
13509 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && | |
13510 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
13511 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; | |
13512 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13513 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13514 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
13515 | tp->tg3_flags2 |= TG3_FLG2_TSO_BUG; | |
13516 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | |
13517 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13518 | else | |
13519 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13520 | } | |
13521 | ||
13522 | tp->irq_max = 1; | |
13523 | ||
5a6f3074 | 13524 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7544b097 MC |
13525 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; |
13526 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
13527 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13528 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13529 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13530 | tp->pdev_peer == tp->pdev)) | |
13531 | tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; | |
13532 | ||
321d32a0 | 13533 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
b5d3772c | 13534 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
fcfa0a32 | 13535 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; |
52c0fd83 | 13536 | } |
4f125f42 | 13537 | |
1407deb1 | 13538 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
507399f1 MC |
13539 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; |
13540 | tp->irq_max = TG3_IRQ_MAX_VECS; | |
13541 | } | |
f6eb9b1f | 13542 | } |
0e1406dd | 13543 | |
615774fe | 13544 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
a50d0796 | 13545 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
615774fe MC |
13546 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
13547 | tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG; | |
13548 | else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) { | |
13549 | tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG; | |
13550 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | |
0e1406dd | 13551 | } |
f6eb9b1f | 13552 | |
0a58d668 | 13553 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
de9f5230 MC |
13554 | tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP; |
13555 | ||
1407deb1 | 13556 | if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && |
2866d956 | 13557 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) |
b703df6f MC |
13558 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; |
13559 | ||
f51f3562 | 13560 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
c6cdf436 MC |
13561 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
13562 | (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG)) | |
8f666b07 | 13563 | tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; |
0f893dc6 | 13564 | |
52f4490c MC |
13565 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13566 | &pci_state_reg); | |
13567 | ||
5e7dfd0f MC |
13568 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); |
13569 | if (tp->pcie_cap != 0) { | |
13570 | u16 lnkctl; | |
13571 | ||
1da177e4 | 13572 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
5f5c51e3 | 13573 | |
cf79003d | 13574 | tp->pcie_readrq = 4096; |
d78b59f5 MC |
13575 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
13576 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | |
b4495ed8 | 13577 | tp->pcie_readrq = 2048; |
cf79003d MC |
13578 | |
13579 | pcie_set_readrq(tp->pdev, tp->pcie_readrq); | |
5f5c51e3 | 13580 | |
5e7dfd0f MC |
13581 | pci_read_config_word(tp->pdev, |
13582 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
13583 | &lnkctl); | |
13584 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
13585 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
c7835a77 | 13586 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; |
5e7dfd0f | 13587 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 13588 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
13589 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
13590 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
5e7dfd0f | 13591 | tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; |
614b0590 MC |
13592 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
13593 | tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN; | |
c7835a77 | 13594 | } |
52f4490c | 13595 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
fcb389df | 13596 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
52f4490c MC |
13597 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
13598 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
13599 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
13600 | if (!tp->pcix_cap) { | |
2445e461 MC |
13601 | dev_err(&tp->pdev->dev, |
13602 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
13603 | return -EIO; |
13604 | } | |
13605 | ||
13606 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
13607 | tp->tg3_flags |= TG3_FLAG_PCIX_MODE; | |
13608 | } | |
1da177e4 | 13609 | |
399de50b MC |
13610 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
13611 | * reordering to the mailbox registers done by the host | |
13612 | * controller can cause major troubles. We read back from | |
13613 | * every mailbox register write to force the writes to be | |
13614 | * posted to the chip in order. | |
13615 | */ | |
4143470c | 13616 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
399de50b MC |
13617 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) |
13618 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
13619 | ||
69fc4053 MC |
13620 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
13621 | &tp->pci_cacheline_sz); | |
13622 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13623 | &tp->pci_lat_timer); | |
1da177e4 LT |
13624 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
13625 | tp->pci_lat_timer < 64) { | |
13626 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
13627 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
13628 | tp->pci_lat_timer); | |
1da177e4 LT |
13629 | } |
13630 | ||
52f4490c MC |
13631 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
13632 | /* 5700 BX chips need to have their TX producer index | |
13633 | * mailboxes written twice to workaround a bug. | |
13634 | */ | |
13635 | tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; | |
1da177e4 | 13636 | |
52f4490c | 13637 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
13638 | * |
13639 | * The workaround is to use indirect register accesses | |
13640 | * for all chip writes not to mailbox registers. | |
13641 | */ | |
52f4490c | 13642 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
1da177e4 | 13643 | u32 pm_reg; |
1da177e4 LT |
13644 | |
13645 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13646 | ||
13647 | /* The chip can have it's power management PCI config | |
13648 | * space registers clobbered due to this bug. | |
13649 | * So explicitly force the chip into D0 here. | |
13650 | */ | |
9974a356 MC |
13651 | pci_read_config_dword(tp->pdev, |
13652 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13653 | &pm_reg); |
13654 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
13655 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
13656 | pci_write_config_dword(tp->pdev, |
13657 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13658 | pm_reg); |
13659 | ||
13660 | /* Also, force SERR#/PERR# in PCI command. */ | |
13661 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13662 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
13663 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13664 | } | |
13665 | } | |
13666 | ||
1da177e4 LT |
13667 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
13668 | tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; | |
13669 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
13670 | tp->tg3_flags |= TG3_FLAG_PCI_32BIT; | |
13671 | ||
13672 | /* Chip-specific fixup from Broadcom driver */ | |
13673 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
13674 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
13675 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
13676 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
13677 | } | |
13678 | ||
1ee582d8 | 13679 | /* Default fast path register access methods */ |
20094930 | 13680 | tp->read32 = tg3_read32; |
1ee582d8 | 13681 | tp->write32 = tg3_write32; |
09ee929c | 13682 | tp->read32_mbox = tg3_read32; |
20094930 | 13683 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
13684 | tp->write32_tx_mbox = tg3_write32; |
13685 | tp->write32_rx_mbox = tg3_write32; | |
13686 | ||
13687 | /* Various workaround register access methods */ | |
13688 | if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) | |
13689 | tp->write32 = tg3_write_indirect_reg32; | |
98efd8a6 MC |
13690 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
13691 | ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
13692 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
13693 | /* | |
13694 | * Back to back register writes can cause problems on these | |
13695 | * chips, the workaround is to read back all reg writes | |
13696 | * except those to mailbox regs. | |
13697 | * | |
13698 | * See tg3_write_indirect_reg32(). | |
13699 | */ | |
1ee582d8 | 13700 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
13701 | } |
13702 | ||
1ee582d8 MC |
13703 | if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || |
13704 | (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { | |
13705 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
13706 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
13707 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
13708 | } | |
20094930 | 13709 | |
6892914f MC |
13710 | if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { |
13711 | tp->read32 = tg3_read_indirect_reg32; | |
13712 | tp->write32 = tg3_write_indirect_reg32; | |
13713 | tp->read32_mbox = tg3_read_indirect_mbox; | |
13714 | tp->write32_mbox = tg3_write_indirect_mbox; | |
13715 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
13716 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
13717 | ||
13718 | iounmap(tp->regs); | |
22abe310 | 13719 | tp->regs = NULL; |
6892914f MC |
13720 | |
13721 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13722 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
13723 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13724 | } | |
b5d3772c MC |
13725 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
13726 | tp->read32_mbox = tg3_read32_mbox_5906; | |
13727 | tp->write32_mbox = tg3_write32_mbox_5906; | |
13728 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
13729 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
13730 | } | |
6892914f | 13731 | |
bbadf503 MC |
13732 | if (tp->write32 == tg3_write_indirect_reg32 || |
13733 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13734 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
f49639e6 | 13735 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
bbadf503 MC |
13736 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; |
13737 | ||
7d0c41ef | 13738 | /* Get eeprom hw config before calling tg3_set_power_state(). |
9d26e213 | 13739 | * In particular, the TG3_FLG2_IS_NIC flag must be |
7d0c41ef MC |
13740 | * determined before calling tg3_set_power_state() so that |
13741 | * we know whether or not to switch out of Vaux power. | |
13742 | * When the flag is set, it means that GPIO1 is used for eeprom | |
13743 | * write protect and also implies that it is a LOM where GPIOs | |
13744 | * are not used to switch power. | |
6aa20a22 | 13745 | */ |
7d0c41ef MC |
13746 | tg3_get_eeprom_hw_cfg(tp); |
13747 | ||
0d3031d9 MC |
13748 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
13749 | /* Allow reads and writes to the | |
13750 | * APE register and memory space. | |
13751 | */ | |
13752 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
f92d9dc1 MC |
13753 | PCISTATE_ALLOW_APE_SHMEM_WR | |
13754 | PCISTATE_ALLOW_APE_PSPACE_WR; | |
0d3031d9 MC |
13755 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13756 | pci_state_reg); | |
13757 | } | |
13758 | ||
9936bcf6 | 13759 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 13760 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 13761 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13762 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
1407deb1 | 13763 | (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) |
d30cdd28 MC |
13764 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; |
13765 | ||
c866b7ea | 13766 | /* Set up tp->grc_local_ctrl before calling tg_power_up(). |
314fba34 MC |
13767 | * GPIO1 driven high will bring 5700's external PHY out of reset. |
13768 | * It is also used as eeprom write protect on LOMs. | |
13769 | */ | |
13770 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
13771 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13772 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | |
13773 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
13774 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
13775 | /* Unused GPIO3 must be driven as output on 5752 because there |
13776 | * are no pull-up resistors on unused GPIO pins. | |
13777 | */ | |
13778 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
13779 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 13780 | |
321d32a0 | 13781 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd MC |
13782 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
13783 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
af36e6b6 MC |
13784 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
13785 | ||
8d519ab2 MC |
13786 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
13787 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
13788 | /* Turn off the debug UART. */ |
13789 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
13790 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
13791 | /* Keep VMain power. */ | |
13792 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
13793 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
13794 | } | |
13795 | ||
1da177e4 | 13796 | /* Force the chip into D0. */ |
c866b7ea | 13797 | err = tg3_power_up(tp); |
1da177e4 | 13798 | if (err) { |
2445e461 | 13799 | dev_err(&tp->pdev->dev, "Transition to D0 failed\n"); |
1da177e4 LT |
13800 | return err; |
13801 | } | |
13802 | ||
1da177e4 LT |
13803 | /* Derive initial jumbo mode from MTU assigned in |
13804 | * ether_setup() via the alloc_etherdev() call | |
13805 | */ | |
0f893dc6 | 13806 | if (tp->dev->mtu > ETH_DATA_LEN && |
a4e2b347 | 13807 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
0f893dc6 | 13808 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
1da177e4 LT |
13809 | |
13810 | /* Determine WakeOnLan speed to use. */ | |
13811 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13812 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
13813 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
13814 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
13815 | tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); | |
13816 | } else { | |
13817 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | |
13818 | } | |
13819 | ||
7f97a4bd | 13820 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
f07e9af3 | 13821 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
7f97a4bd | 13822 | |
1da177e4 LT |
13823 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
13824 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13825 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
13826 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
747e8f8b | 13827 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
f07e9af3 MC |
13828 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
13829 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | |
13830 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | |
1da177e4 LT |
13831 | |
13832 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
13833 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
f07e9af3 | 13834 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
1da177e4 | 13835 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
f07e9af3 | 13836 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
1da177e4 | 13837 | |
321d32a0 | 13838 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
f07e9af3 | 13839 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
321d32a0 | 13840 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 13841 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
1407deb1 | 13842 | !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { |
c424cb24 | 13843 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 13844 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
13845 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
13846 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
13847 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
13848 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
f07e9af3 | 13849 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
c1d2a196 | 13850 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
f07e9af3 | 13851 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
321d32a0 | 13852 | } else |
f07e9af3 | 13853 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
c424cb24 | 13854 | } |
1da177e4 | 13855 | |
b2a5c19c MC |
13856 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
13857 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
13858 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
13859 | if (tp->phy_otp == 0) | |
13860 | tp->phy_otp = TG3_OTP_DEFAULT; | |
13861 | } | |
13862 | ||
f51f3562 | 13863 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) |
8ef21428 MC |
13864 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
13865 | else | |
13866 | tp->mi_mode = MAC_MI_MODE_BASE; | |
13867 | ||
1da177e4 | 13868 | tp->coalesce_mode = 0; |
1da177e4 LT |
13869 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
13870 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
13871 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
13872 | ||
321d32a0 MC |
13873 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
13874 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
57e6983c MC |
13875 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; |
13876 | ||
158d7abd MC |
13877 | err = tg3_mdio_init(tp); |
13878 | if (err) | |
13879 | return err; | |
1da177e4 LT |
13880 | |
13881 | /* Initialize data/descriptor byte/word swapping. */ | |
13882 | val = tr32(GRC_MODE); | |
13883 | val &= GRC_MODE_HOST_STACKUP; | |
13884 | tw32(GRC_MODE, val | tp->grc_mode); | |
13885 | ||
13886 | tg3_switch_clocks(tp); | |
13887 | ||
13888 | /* Clear this out for sanity. */ | |
13889 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
13890 | ||
13891 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13892 | &pci_state_reg); | |
13893 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
13894 | (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { | |
13895 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
13896 | ||
13897 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
13898 | chiprevid == CHIPREV_ID_5701_B0 || | |
13899 | chiprevid == CHIPREV_ID_5701_B2 || | |
13900 | chiprevid == CHIPREV_ID_5701_B5) { | |
13901 | void __iomem *sram_base; | |
13902 | ||
13903 | /* Write some dummy words into the SRAM status block | |
13904 | * area, see if it reads back correctly. If the return | |
13905 | * value is bad, force enable the PCIX workaround. | |
13906 | */ | |
13907 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
13908 | ||
13909 | writel(0x00000000, sram_base); | |
13910 | writel(0x00000000, sram_base + 4); | |
13911 | writel(0xffffffff, sram_base + 4); | |
13912 | if (readl(sram_base) != 0x00000000) | |
13913 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13914 | } | |
13915 | } | |
13916 | ||
13917 | udelay(50); | |
13918 | tg3_nvram_init(tp); | |
13919 | ||
13920 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
13921 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
13922 | ||
1da177e4 LT |
13923 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
13924 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
13925 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
13926 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | |
13927 | ||
fac9b83e DM |
13928 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && |
13929 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | |
13930 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | |
13931 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
13932 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
13933 | HOSTCC_MODE_CLRTICK_TXBD); | |
13934 | ||
13935 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
13936 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13937 | tp->misc_host_ctrl); | |
13938 | } | |
13939 | ||
3bda1258 MC |
13940 | /* Preserve the APE MAC_MODE bits */ |
13941 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
d2394e6b | 13942 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
3bda1258 MC |
13943 | else |
13944 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
13945 | ||
1da177e4 LT |
13946 | /* these are limited to 10/100 only */ |
13947 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
13948 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
13949 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
13950 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13951 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
13952 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
13953 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
13954 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13955 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
13956 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
13957 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 13958 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
13959 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
13960 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
f07e9af3 MC |
13961 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
13962 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; | |
1da177e4 LT |
13963 | |
13964 | err = tg3_phy_probe(tp); | |
13965 | if (err) { | |
2445e461 | 13966 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 13967 | /* ... but do not return immediately ... */ |
b02fd9e3 | 13968 | tg3_mdio_fini(tp); |
1da177e4 LT |
13969 | } |
13970 | ||
184b8904 | 13971 | tg3_read_vpd(tp); |
c4e6575c | 13972 | tg3_read_fw_ver(tp); |
1da177e4 | 13973 | |
f07e9af3 MC |
13974 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
13975 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | |
1da177e4 LT |
13976 | } else { |
13977 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
f07e9af3 | 13978 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 | 13979 | else |
f07e9af3 | 13980 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
1da177e4 LT |
13981 | } |
13982 | ||
13983 | /* 5700 {AX,BX} chips have a broken status block link | |
13984 | * change bit implementation, so we must use the | |
13985 | * status register in those cases. | |
13986 | */ | |
13987 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
13988 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
13989 | else | |
13990 | tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; | |
13991 | ||
13992 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
13993 | * have to force the link status polling mechanism based | |
13994 | * upon subsystem IDs. | |
13995 | */ | |
13996 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 13997 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
f07e9af3 MC |
13998 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
13999 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | |
14000 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
1da177e4 LT |
14001 | } |
14002 | ||
14003 | /* For all SERDES we poll the MAC status register. */ | |
f07e9af3 | 14004 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
1da177e4 LT |
14005 | tp->tg3_flags |= TG3_FLAG_POLL_SERDES; |
14006 | else | |
14007 | tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; | |
14008 | ||
bf933c80 | 14009 | tp->rx_offset = NET_IP_ALIGN; |
d2757fc4 | 14010 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 14011 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
d2757fc4 | 14012 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { |
bf933c80 | 14013 | tp->rx_offset = 0; |
d2757fc4 | 14014 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 14015 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
14016 | #endif |
14017 | } | |
1da177e4 | 14018 | |
2c49a44d MC |
14019 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
14020 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; | |
7cb32cf2 MC |
14021 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
14022 | ||
2c49a44d | 14023 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
f92905de MC |
14024 | |
14025 | /* Increment the rx prod index on the rx std ring by at most | |
14026 | * 8 for these chips to workaround hw errata. | |
14027 | */ | |
14028 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
14029 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
14030 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
14031 | tp->rx_std_max_post = 8; | |
14032 | ||
8ed5d97e MC |
14033 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) |
14034 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
14035 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
14036 | ||
1da177e4 LT |
14037 | return err; |
14038 | } | |
14039 | ||
49b6e95f | 14040 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14041 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
14042 | { | |
14043 | struct net_device *dev = tp->dev; | |
14044 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 14045 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 14046 | const unsigned char *addr; |
49b6e95f DM |
14047 | int len; |
14048 | ||
14049 | addr = of_get_property(dp, "local-mac-address", &len); | |
14050 | if (addr && len == 6) { | |
14051 | memcpy(dev->dev_addr, addr, 6); | |
14052 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
14053 | return 0; | |
1da177e4 LT |
14054 | } |
14055 | return -ENODEV; | |
14056 | } | |
14057 | ||
14058 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
14059 | { | |
14060 | struct net_device *dev = tp->dev; | |
14061 | ||
14062 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 14063 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
14064 | return 0; |
14065 | } | |
14066 | #endif | |
14067 | ||
14068 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
14069 | { | |
14070 | struct net_device *dev = tp->dev; | |
14071 | u32 hi, lo, mac_offset; | |
008652b3 | 14072 | int addr_ok = 0; |
1da177e4 | 14073 | |
49b6e95f | 14074 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14075 | if (!tg3_get_macaddr_sparc(tp)) |
14076 | return 0; | |
14077 | #endif | |
14078 | ||
14079 | mac_offset = 0x7c; | |
f49639e6 | 14080 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
a4e2b347 | 14081 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
14082 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
14083 | mac_offset = 0xcc; | |
14084 | if (tg3_nvram_lock(tp)) | |
14085 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
14086 | else | |
14087 | tg3_nvram_unlock(tp); | |
0a58d668 | 14088 | } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
a50d0796 | 14089 | if (PCI_FUNC(tp->pdev->devfn) & 1) |
a1b950d5 | 14090 | mac_offset = 0xcc; |
a50d0796 MC |
14091 | if (PCI_FUNC(tp->pdev->devfn) > 1) |
14092 | mac_offset += 0x18c; | |
a1b950d5 | 14093 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
b5d3772c | 14094 | mac_offset = 0x10; |
1da177e4 LT |
14095 | |
14096 | /* First try to get it from MAC address mailbox. */ | |
14097 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
14098 | if ((hi >> 16) == 0x484b) { | |
14099 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14100 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
14101 | ||
14102 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
14103 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14104 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14105 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14106 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 14107 | |
008652b3 MC |
14108 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
14109 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
14110 | } | |
14111 | if (!addr_ok) { | |
14112 | /* Next, try NVRAM. */ | |
df259d8c MC |
14113 | if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && |
14114 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && | |
6d348f2c | 14115 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
14116 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
14117 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
14118 | } |
14119 | /* Finally just fetch it out of the MAC control regs. */ | |
14120 | else { | |
14121 | hi = tr32(MAC_ADDR_0_HIGH); | |
14122 | lo = tr32(MAC_ADDR_0_LOW); | |
14123 | ||
14124 | dev->dev_addr[5] = lo & 0xff; | |
14125 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
14126 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
14127 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
14128 | dev->dev_addr[1] = hi & 0xff; | |
14129 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
14130 | } | |
1da177e4 LT |
14131 | } |
14132 | ||
14133 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 14134 | #ifdef CONFIG_SPARC |
1da177e4 LT |
14135 | if (!tg3_get_default_macaddr_sparc(tp)) |
14136 | return 0; | |
14137 | #endif | |
14138 | return -EINVAL; | |
14139 | } | |
2ff43697 | 14140 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
14141 | return 0; |
14142 | } | |
14143 | ||
59e6b434 DM |
14144 | #define BOUNDARY_SINGLE_CACHELINE 1 |
14145 | #define BOUNDARY_MULTI_CACHELINE 2 | |
14146 | ||
14147 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
14148 | { | |
14149 | int cacheline_size; | |
14150 | u8 byte; | |
14151 | int goal; | |
14152 | ||
14153 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
14154 | if (byte == 0) | |
14155 | cacheline_size = 1024; | |
14156 | else | |
14157 | cacheline_size = (int) byte * 4; | |
14158 | ||
14159 | /* On 5703 and later chips, the boundary bits have no | |
14160 | * effect. | |
14161 | */ | |
14162 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
14163 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
14164 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
14165 | goto out; | |
14166 | ||
14167 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
14168 | goal = BOUNDARY_MULTI_CACHELINE; | |
14169 | #else | |
14170 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
14171 | goal = BOUNDARY_SINGLE_CACHELINE; | |
14172 | #else | |
14173 | goal = 0; | |
14174 | #endif | |
14175 | #endif | |
14176 | ||
1407deb1 | 14177 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
cbf9ca6c MC |
14178 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
14179 | goto out; | |
14180 | } | |
14181 | ||
59e6b434 DM |
14182 | if (!goal) |
14183 | goto out; | |
14184 | ||
14185 | /* PCI controllers on most RISC systems tend to disconnect | |
14186 | * when a device tries to burst across a cache-line boundary. | |
14187 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
14188 | * | |
14189 | * Unfortunately, for PCI-E there are only limited | |
14190 | * write-side controls for this, and thus for reads | |
14191 | * we will still get the disconnects. We'll also waste | |
14192 | * these PCI cycles for both read and write for chips | |
14193 | * other than 5700 and 5701 which do not implement the | |
14194 | * boundary bits. | |
14195 | */ | |
14196 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
14197 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
14198 | switch (cacheline_size) { | |
14199 | case 16: | |
14200 | case 32: | |
14201 | case 64: | |
14202 | case 128: | |
14203 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14204 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
14205 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
14206 | } else { | |
14207 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14208 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14209 | } | |
14210 | break; | |
14211 | ||
14212 | case 256: | |
14213 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
14214 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
14215 | break; | |
14216 | ||
14217 | default: | |
14218 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
14219 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
14220 | break; | |
855e1111 | 14221 | } |
59e6b434 DM |
14222 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
14223 | switch (cacheline_size) { | |
14224 | case 16: | |
14225 | case 32: | |
14226 | case 64: | |
14227 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14228 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14229 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
14230 | break; | |
14231 | } | |
14232 | /* fallthrough */ | |
14233 | case 128: | |
14234 | default: | |
14235 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
14236 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
14237 | break; | |
855e1111 | 14238 | } |
59e6b434 DM |
14239 | } else { |
14240 | switch (cacheline_size) { | |
14241 | case 16: | |
14242 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14243 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
14244 | DMA_RWCTRL_WRITE_BNDRY_16); | |
14245 | break; | |
14246 | } | |
14247 | /* fallthrough */ | |
14248 | case 32: | |
14249 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14250 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
14251 | DMA_RWCTRL_WRITE_BNDRY_32); | |
14252 | break; | |
14253 | } | |
14254 | /* fallthrough */ | |
14255 | case 64: | |
14256 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14257 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
14258 | DMA_RWCTRL_WRITE_BNDRY_64); | |
14259 | break; | |
14260 | } | |
14261 | /* fallthrough */ | |
14262 | case 128: | |
14263 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
14264 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
14265 | DMA_RWCTRL_WRITE_BNDRY_128); | |
14266 | break; | |
14267 | } | |
14268 | /* fallthrough */ | |
14269 | case 256: | |
14270 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
14271 | DMA_RWCTRL_WRITE_BNDRY_256); | |
14272 | break; | |
14273 | case 512: | |
14274 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
14275 | DMA_RWCTRL_WRITE_BNDRY_512); | |
14276 | break; | |
14277 | case 1024: | |
14278 | default: | |
14279 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
14280 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
14281 | break; | |
855e1111 | 14282 | } |
59e6b434 DM |
14283 | } |
14284 | ||
14285 | out: | |
14286 | return val; | |
14287 | } | |
14288 | ||
1da177e4 LT |
14289 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
14290 | { | |
14291 | struct tg3_internal_buffer_desc test_desc; | |
14292 | u32 sram_dma_descs; | |
14293 | int i, ret; | |
14294 | ||
14295 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
14296 | ||
14297 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
14298 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
14299 | tw32(RDMAC_STATUS, 0); | |
14300 | tw32(WDMAC_STATUS, 0); | |
14301 | ||
14302 | tw32(BUFMGR_MODE, 0); | |
14303 | tw32(FTQ_RESET, 0); | |
14304 | ||
14305 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
14306 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
14307 | test_desc.nic_mbuf = 0x00002100; | |
14308 | test_desc.len = size; | |
14309 | ||
14310 | /* | |
14311 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
14312 | * the *second* time the tg3 driver was getting loaded after an | |
14313 | * initial scan. | |
14314 | * | |
14315 | * Broadcom tells me: | |
14316 | * ...the DMA engine is connected to the GRC block and a DMA | |
14317 | * reset may affect the GRC block in some unpredictable way... | |
14318 | * The behavior of resets to individual blocks has not been tested. | |
14319 | * | |
14320 | * Broadcom noted the GRC reset will also reset all sub-components. | |
14321 | */ | |
14322 | if (to_device) { | |
14323 | test_desc.cqid_sqid = (13 << 8) | 2; | |
14324 | ||
14325 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
14326 | udelay(40); | |
14327 | } else { | |
14328 | test_desc.cqid_sqid = (16 << 8) | 7; | |
14329 | ||
14330 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
14331 | udelay(40); | |
14332 | } | |
14333 | test_desc.flags = 0x00000005; | |
14334 | ||
14335 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
14336 | u32 val; | |
14337 | ||
14338 | val = *(((u32 *)&test_desc) + i); | |
14339 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
14340 | sram_dma_descs + (i * sizeof(u32))); | |
14341 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
14342 | } | |
14343 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
14344 | ||
859a5887 | 14345 | if (to_device) |
1da177e4 | 14346 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 14347 | else |
1da177e4 | 14348 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
14349 | |
14350 | ret = -ENODEV; | |
14351 | for (i = 0; i < 40; i++) { | |
14352 | u32 val; | |
14353 | ||
14354 | if (to_device) | |
14355 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
14356 | else | |
14357 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
14358 | if ((val & 0xffff) == sram_dma_descs) { | |
14359 | ret = 0; | |
14360 | break; | |
14361 | } | |
14362 | ||
14363 | udelay(100); | |
14364 | } | |
14365 | ||
14366 | return ret; | |
14367 | } | |
14368 | ||
ded7340d | 14369 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 | 14370 | |
4143470c | 14371 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
895950c2 JP |
14372 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
14373 | { }, | |
14374 | }; | |
14375 | ||
1da177e4 LT |
14376 | static int __devinit tg3_test_dma(struct tg3 *tp) |
14377 | { | |
14378 | dma_addr_t buf_dma; | |
59e6b434 | 14379 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 14380 | int ret = 0; |
1da177e4 | 14381 | |
4bae65c8 MC |
14382 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
14383 | &buf_dma, GFP_KERNEL); | |
1da177e4 LT |
14384 | if (!buf) { |
14385 | ret = -ENOMEM; | |
14386 | goto out_nofree; | |
14387 | } | |
14388 | ||
14389 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
14390 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
14391 | ||
59e6b434 | 14392 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 14393 | |
1407deb1 | 14394 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) |
cbf9ca6c MC |
14395 | goto out; |
14396 | ||
1da177e4 LT |
14397 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
14398 | /* DMA read watermark not used on PCIE */ | |
14399 | tp->dma_rwctrl |= 0x00180000; | |
14400 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
85e94ced MC |
14401 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
14402 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
14403 | tp->dma_rwctrl |= 0x003f0000; |
14404 | else | |
14405 | tp->dma_rwctrl |= 0x003f000f; | |
14406 | } else { | |
14407 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14408 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
14409 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 14410 | u32 read_water = 0x7; |
1da177e4 | 14411 | |
4a29cc2e MC |
14412 | /* If the 5704 is behind the EPB bridge, we can |
14413 | * do the less restrictive ONE_DMA workaround for | |
14414 | * better performance. | |
14415 | */ | |
14416 | if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && | |
14417 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14418 | tp->dma_rwctrl |= 0x8000; | |
14419 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
14420 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
14421 | ||
49afdeb6 MC |
14422 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
14423 | read_water = 4; | |
59e6b434 | 14424 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
14425 | tp->dma_rwctrl |= |
14426 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
14427 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
14428 | (1 << 23); | |
4cf78e4f MC |
14429 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
14430 | /* 5780 always in PCIX mode */ | |
14431 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
14432 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
14433 | /* 5714 always in PCIX mode */ | |
14434 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
14435 | } else { |
14436 | tp->dma_rwctrl |= 0x001b000f; | |
14437 | } | |
14438 | } | |
14439 | ||
14440 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
14441 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
14442 | tp->dma_rwctrl &= 0xfffffff0; | |
14443 | ||
14444 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
14445 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
14446 | /* Remove this if it causes problems for some boards. */ | |
14447 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
14448 | ||
14449 | /* On 5700/5701 chips, we need to set this bit. | |
14450 | * Otherwise the chip will issue cacheline transactions | |
14451 | * to streamable DMA memory with not all the byte | |
14452 | * enables turned on. This is an error on several | |
14453 | * RISC PCI controllers, in particular sparc64. | |
14454 | * | |
14455 | * On 5703/5704 chips, this bit has been reassigned | |
14456 | * a different meaning. In particular, it is used | |
14457 | * on those chips to enable a PCI-X workaround. | |
14458 | */ | |
14459 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
14460 | } | |
14461 | ||
14462 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14463 | ||
14464 | #if 0 | |
14465 | /* Unneeded, already done by tg3_get_invariants. */ | |
14466 | tg3_switch_clocks(tp); | |
14467 | #endif | |
14468 | ||
1da177e4 LT |
14469 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
14470 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
14471 | goto out; | |
14472 | ||
59e6b434 DM |
14473 | /* It is best to perform DMA test with maximum write burst size |
14474 | * to expose the 5700/5701 write DMA bug. | |
14475 | */ | |
14476 | saved_dma_rwctrl = tp->dma_rwctrl; | |
14477 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14478 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14479 | ||
1da177e4 LT |
14480 | while (1) { |
14481 | u32 *p = buf, i; | |
14482 | ||
14483 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
14484 | p[i] = i; | |
14485 | ||
14486 | /* Send the buffer to the chip. */ | |
14487 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
14488 | if (ret) { | |
2445e461 MC |
14489 | dev_err(&tp->pdev->dev, |
14490 | "%s: Buffer write failed. err = %d\n", | |
14491 | __func__, ret); | |
1da177e4 LT |
14492 | break; |
14493 | } | |
14494 | ||
14495 | #if 0 | |
14496 | /* validate data reached card RAM correctly. */ | |
14497 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14498 | u32 val; | |
14499 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
14500 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
14501 | dev_err(&tp->pdev->dev, |
14502 | "%s: Buffer corrupted on device! " | |
14503 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
14504 | /* ret = -ENODEV here? */ |
14505 | } | |
14506 | p[i] = 0; | |
14507 | } | |
14508 | #endif | |
14509 | /* Now read it back. */ | |
14510 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
14511 | if (ret) { | |
5129c3a3 MC |
14512 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
14513 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
14514 | break; |
14515 | } | |
14516 | ||
14517 | /* Verify it. */ | |
14518 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14519 | if (p[i] == i) | |
14520 | continue; | |
14521 | ||
59e6b434 DM |
14522 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14523 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14524 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
14525 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
14526 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14527 | break; | |
14528 | } else { | |
2445e461 MC |
14529 | dev_err(&tp->pdev->dev, |
14530 | "%s: Buffer corrupted on read back! " | |
14531 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
14532 | ret = -ENODEV; |
14533 | goto out; | |
14534 | } | |
14535 | } | |
14536 | ||
14537 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14538 | /* Success. */ | |
14539 | ret = 0; | |
14540 | break; | |
14541 | } | |
14542 | } | |
59e6b434 DM |
14543 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14544 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
6d1cfbab | 14545 | |
59e6b434 | 14546 | /* DMA test passed without adjusting DMA boundary, |
6d1cfbab MC |
14547 | * now look for chipsets that are known to expose the |
14548 | * DMA bug without failing the test. | |
59e6b434 | 14549 | */ |
4143470c | 14550 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
6d1cfbab MC |
14551 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
14552 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 14553 | } else { |
6d1cfbab MC |
14554 | /* Safe to use the calculated DMA boundary. */ |
14555 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 14556 | } |
6d1cfbab | 14557 | |
59e6b434 DM |
14558 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
14559 | } | |
1da177e4 LT |
14560 | |
14561 | out: | |
4bae65c8 | 14562 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
1da177e4 LT |
14563 | out_nofree: |
14564 | return ret; | |
14565 | } | |
14566 | ||
1da177e4 LT |
14567 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
14568 | { | |
1407deb1 | 14569 | if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { |
666bc831 MC |
14570 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14571 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14572 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14573 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14574 | tp->bufmgr_config.mbuf_high_water = | |
14575 | DEFAULT_MB_HIGH_WATER_57765; | |
14576 | ||
14577 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14578 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14579 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14580 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14581 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14582 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
14583 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
fdfec172 MC |
14584 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14585 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14586 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14587 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14588 | tp->bufmgr_config.mbuf_high_water = | |
14589 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
14590 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14591 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14592 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14593 | tp->bufmgr_config.mbuf_high_water = | |
14594 | DEFAULT_MB_HIGH_WATER_5906; | |
14595 | } | |
fdfec172 MC |
14596 | |
14597 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14598 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
14599 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14600 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
14601 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14602 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
14603 | } else { | |
14604 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14605 | DEFAULT_MB_RDMA_LOW_WATER; | |
14606 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14607 | DEFAULT_MB_MACRX_LOW_WATER; | |
14608 | tp->bufmgr_config.mbuf_high_water = | |
14609 | DEFAULT_MB_HIGH_WATER; | |
14610 | ||
14611 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14612 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
14613 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14614 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
14615 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14616 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
14617 | } | |
1da177e4 LT |
14618 | |
14619 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
14620 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
14621 | } | |
14622 | ||
14623 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
14624 | { | |
79eb6904 MC |
14625 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
14626 | case TG3_PHY_ID_BCM5400: return "5400"; | |
14627 | case TG3_PHY_ID_BCM5401: return "5401"; | |
14628 | case TG3_PHY_ID_BCM5411: return "5411"; | |
14629 | case TG3_PHY_ID_BCM5701: return "5701"; | |
14630 | case TG3_PHY_ID_BCM5703: return "5703"; | |
14631 | case TG3_PHY_ID_BCM5704: return "5704"; | |
14632 | case TG3_PHY_ID_BCM5705: return "5705"; | |
14633 | case TG3_PHY_ID_BCM5750: return "5750"; | |
14634 | case TG3_PHY_ID_BCM5752: return "5752"; | |
14635 | case TG3_PHY_ID_BCM5714: return "5714"; | |
14636 | case TG3_PHY_ID_BCM5780: return "5780"; | |
14637 | case TG3_PHY_ID_BCM5755: return "5755"; | |
14638 | case TG3_PHY_ID_BCM5787: return "5787"; | |
14639 | case TG3_PHY_ID_BCM5784: return "5784"; | |
14640 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
14641 | case TG3_PHY_ID_BCM5906: return "5906"; | |
14642 | case TG3_PHY_ID_BCM5761: return "5761"; | |
14643 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
14644 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
14645 | case TG3_PHY_ID_BCM57765: return "57765"; | |
302b500b | 14646 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
79eb6904 | 14647 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
1da177e4 LT |
14648 | case 0: return "serdes"; |
14649 | default: return "unknown"; | |
855e1111 | 14650 | } |
1da177e4 LT |
14651 | } |
14652 | ||
f9804ddb MC |
14653 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
14654 | { | |
14655 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
14656 | strcpy(str, "PCI Express"); | |
14657 | return str; | |
14658 | } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
14659 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
14660 | ||
14661 | strcpy(str, "PCIX:"); | |
14662 | ||
14663 | if ((clock_ctrl == 7) || | |
14664 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
14665 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
14666 | strcat(str, "133MHz"); | |
14667 | else if (clock_ctrl == 0) | |
14668 | strcat(str, "33MHz"); | |
14669 | else if (clock_ctrl == 2) | |
14670 | strcat(str, "50MHz"); | |
14671 | else if (clock_ctrl == 4) | |
14672 | strcat(str, "66MHz"); | |
14673 | else if (clock_ctrl == 6) | |
14674 | strcat(str, "100MHz"); | |
f9804ddb MC |
14675 | } else { |
14676 | strcpy(str, "PCI:"); | |
14677 | if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) | |
14678 | strcat(str, "66MHz"); | |
14679 | else | |
14680 | strcat(str, "33MHz"); | |
14681 | } | |
14682 | if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) | |
14683 | strcat(str, ":32-bit"); | |
14684 | else | |
14685 | strcat(str, ":64-bit"); | |
14686 | return str; | |
14687 | } | |
14688 | ||
8c2dc7e1 | 14689 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
14690 | { |
14691 | struct pci_dev *peer; | |
14692 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14693 | ||
14694 | for (func = 0; func < 8; func++) { | |
14695 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14696 | if (peer && peer != tp->pdev) | |
14697 | break; | |
14698 | pci_dev_put(peer); | |
14699 | } | |
16fe9d74 MC |
14700 | /* 5704 can be configured in single-port mode, set peer to |
14701 | * tp->pdev in that case. | |
14702 | */ | |
14703 | if (!peer) { | |
14704 | peer = tp->pdev; | |
14705 | return peer; | |
14706 | } | |
1da177e4 LT |
14707 | |
14708 | /* | |
14709 | * We don't need to keep the refcount elevated; there's no way | |
14710 | * to remove one half of this device without removing the other | |
14711 | */ | |
14712 | pci_dev_put(peer); | |
14713 | ||
14714 | return peer; | |
14715 | } | |
14716 | ||
15f9850d DM |
14717 | static void __devinit tg3_init_coal(struct tg3 *tp) |
14718 | { | |
14719 | struct ethtool_coalesce *ec = &tp->coal; | |
14720 | ||
14721 | memset(ec, 0, sizeof(*ec)); | |
14722 | ec->cmd = ETHTOOL_GCOALESCE; | |
14723 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
14724 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
14725 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
14726 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
14727 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
14728 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
14729 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
14730 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
14731 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
14732 | ||
14733 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
14734 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
14735 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
14736 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
14737 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
14738 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
14739 | } | |
d244c892 MC |
14740 | |
14741 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
14742 | ec->rx_coalesce_usecs_irq = 0; | |
14743 | ec->tx_coalesce_usecs_irq = 0; | |
14744 | ec->stats_block_coalesce_usecs = 0; | |
14745 | } | |
15f9850d DM |
14746 | } |
14747 | ||
7c7d64b8 SH |
14748 | static const struct net_device_ops tg3_netdev_ops = { |
14749 | .ndo_open = tg3_open, | |
14750 | .ndo_stop = tg3_close, | |
00829823 | 14751 | .ndo_start_xmit = tg3_start_xmit, |
511d2224 | 14752 | .ndo_get_stats64 = tg3_get_stats64, |
00829823 SH |
14753 | .ndo_validate_addr = eth_validate_addr, |
14754 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14755 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14756 | .ndo_do_ioctl = tg3_ioctl, | |
14757 | .ndo_tx_timeout = tg3_tx_timeout, | |
14758 | .ndo_change_mtu = tg3_change_mtu, | |
00829823 SH |
14759 | #ifdef CONFIG_NET_POLL_CONTROLLER |
14760 | .ndo_poll_controller = tg3_poll_controller, | |
14761 | #endif | |
14762 | }; | |
14763 | ||
14764 | static const struct net_device_ops tg3_netdev_ops_dma_bug = { | |
14765 | .ndo_open = tg3_open, | |
14766 | .ndo_stop = tg3_close, | |
14767 | .ndo_start_xmit = tg3_start_xmit_dma_bug, | |
511d2224 | 14768 | .ndo_get_stats64 = tg3_get_stats64, |
7c7d64b8 SH |
14769 | .ndo_validate_addr = eth_validate_addr, |
14770 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14771 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14772 | .ndo_do_ioctl = tg3_ioctl, | |
14773 | .ndo_tx_timeout = tg3_tx_timeout, | |
14774 | .ndo_change_mtu = tg3_change_mtu, | |
7c7d64b8 SH |
14775 | #ifdef CONFIG_NET_POLL_CONTROLLER |
14776 | .ndo_poll_controller = tg3_poll_controller, | |
14777 | #endif | |
14778 | }; | |
14779 | ||
1da177e4 LT |
14780 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
14781 | const struct pci_device_id *ent) | |
14782 | { | |
1da177e4 LT |
14783 | struct net_device *dev; |
14784 | struct tg3 *tp; | |
646c9edd MC |
14785 | int i, err, pm_cap; |
14786 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 14787 | char str[40]; |
72f2afb8 | 14788 | u64 dma_mask, persist_dma_mask; |
1da177e4 | 14789 | |
05dbe005 | 14790 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
14791 | |
14792 | err = pci_enable_device(pdev); | |
14793 | if (err) { | |
2445e461 | 14794 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
14795 | return err; |
14796 | } | |
14797 | ||
1da177e4 LT |
14798 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
14799 | if (err) { | |
2445e461 | 14800 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
14801 | goto err_out_disable_pdev; |
14802 | } | |
14803 | ||
14804 | pci_set_master(pdev); | |
14805 | ||
14806 | /* Find power-management capability. */ | |
14807 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
14808 | if (pm_cap == 0) { | |
2445e461 MC |
14809 | dev_err(&pdev->dev, |
14810 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
14811 | err = -EIO; |
14812 | goto err_out_free_res; | |
14813 | } | |
14814 | ||
fe5f5787 | 14815 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 14816 | if (!dev) { |
2445e461 | 14817 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 LT |
14818 | err = -ENOMEM; |
14819 | goto err_out_free_res; | |
14820 | } | |
14821 | ||
1da177e4 LT |
14822 | SET_NETDEV_DEV(dev, &pdev->dev); |
14823 | ||
1da177e4 | 14824 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
1da177e4 LT |
14825 | |
14826 | tp = netdev_priv(dev); | |
14827 | tp->pdev = pdev; | |
14828 | tp->dev = dev; | |
14829 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
14830 | tp->rx_mode = TG3_DEF_RX_MODE; |
14831 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 14832 | |
1da177e4 LT |
14833 | if (tg3_debug > 0) |
14834 | tp->msg_enable = tg3_debug; | |
14835 | else | |
14836 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
14837 | ||
14838 | /* The word/byte swap controls here control register access byte | |
14839 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
14840 | * setting below. | |
14841 | */ | |
14842 | tp->misc_host_ctrl = | |
14843 | MISC_HOST_CTRL_MASK_PCI_INT | | |
14844 | MISC_HOST_CTRL_WORD_SWAP | | |
14845 | MISC_HOST_CTRL_INDIR_ACCESS | | |
14846 | MISC_HOST_CTRL_PCISTATE_RW; | |
14847 | ||
14848 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
14849 | * on descriptor entries, anything which isn't packet data. | |
14850 | * | |
14851 | * The StrongARM chips on the board (one for tx, one for rx) | |
14852 | * are running in big-endian mode. | |
14853 | */ | |
14854 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
14855 | GRC_MODE_WSWAP_NONFRM_DATA); | |
14856 | #ifdef __BIG_ENDIAN | |
14857 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
14858 | #endif | |
14859 | spin_lock_init(&tp->lock); | |
1da177e4 | 14860 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 14861 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 14862 | |
d5fe488a | 14863 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 14864 | if (!tp->regs) { |
ab96b241 | 14865 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
14866 | err = -ENOMEM; |
14867 | goto err_out_free_dev; | |
14868 | } | |
14869 | ||
1da177e4 LT |
14870 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
14871 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 14872 | |
1da177e4 | 14873 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 14874 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
1da177e4 | 14875 | dev->irq = pdev->irq; |
1da177e4 LT |
14876 | |
14877 | err = tg3_get_invariants(tp); | |
14878 | if (err) { | |
ab96b241 MC |
14879 | dev_err(&pdev->dev, |
14880 | "Problem fetching invariants of chip, aborting\n"); | |
1da177e4 LT |
14881 | goto err_out_iounmap; |
14882 | } | |
14883 | ||
615774fe | 14884 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && |
0a58d668 | 14885 | !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
00829823 SH |
14886 | dev->netdev_ops = &tg3_netdev_ops; |
14887 | else | |
14888 | dev->netdev_ops = &tg3_netdev_ops_dma_bug; | |
14889 | ||
14890 | ||
4a29cc2e MC |
14891 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
14892 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
14893 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
14894 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
14895 | * do DMA address check in tg3_start_xmit(). | |
14896 | */ | |
4a29cc2e | 14897 | if (tp->tg3_flags2 & TG3_FLG2_IS_5788) |
284901a9 | 14898 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
4a29cc2e | 14899 | else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { |
50cf156a | 14900 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 14901 | #ifdef CONFIG_HIGHMEM |
6a35528a | 14902 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 14903 | #endif |
4a29cc2e | 14904 | } else |
6a35528a | 14905 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
14906 | |
14907 | /* Configure DMA attributes. */ | |
284901a9 | 14908 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
14909 | err = pci_set_dma_mask(pdev, dma_mask); |
14910 | if (!err) { | |
14911 | dev->features |= NETIF_F_HIGHDMA; | |
14912 | err = pci_set_consistent_dma_mask(pdev, | |
14913 | persist_dma_mask); | |
14914 | if (err < 0) { | |
ab96b241 MC |
14915 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
14916 | "DMA for consistent allocations\n"); | |
72f2afb8 MC |
14917 | goto err_out_iounmap; |
14918 | } | |
14919 | } | |
14920 | } | |
284901a9 YH |
14921 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
14922 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 14923 | if (err) { |
ab96b241 MC |
14924 | dev_err(&pdev->dev, |
14925 | "No usable DMA configuration, aborting\n"); | |
72f2afb8 MC |
14926 | goto err_out_iounmap; |
14927 | } | |
14928 | } | |
14929 | ||
fdfec172 | 14930 | tg3_init_bufmgr_config(tp); |
1da177e4 | 14931 | |
507399f1 MC |
14932 | /* Selectively allow TSO based on operating conditions */ |
14933 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || | |
14934 | (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) | |
1da177e4 | 14935 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
507399f1 MC |
14936 | else { |
14937 | tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG); | |
14938 | tp->fw_needed = NULL; | |
1da177e4 | 14939 | } |
507399f1 MC |
14940 | |
14941 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
14942 | tp->fw_needed = FIRMWARE_TG3; | |
1da177e4 | 14943 | |
4e3a7aaa MC |
14944 | /* TSO is on by default on chips that support hardware TSO. |
14945 | * Firmware TSO on older chips gives lower performance, so it | |
14946 | * is off by default, but can be enabled using ethtool. | |
14947 | */ | |
e849cdc3 | 14948 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) && |
7fe876af | 14949 | (dev->features & NETIF_F_IP_CSUM)) { |
e849cdc3 | 14950 | dev->features |= NETIF_F_TSO; |
7fe876af ED |
14951 | vlan_features_add(dev, NETIF_F_TSO); |
14952 | } | |
e849cdc3 MC |
14953 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || |
14954 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) { | |
7fe876af | 14955 | if (dev->features & NETIF_F_IPV6_CSUM) { |
b0026624 | 14956 | dev->features |= NETIF_F_TSO6; |
7fe876af ED |
14957 | vlan_features_add(dev, NETIF_F_TSO6); |
14958 | } | |
e849cdc3 MC |
14959 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
14960 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
14961 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14962 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 14963 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
7fe876af | 14964 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
9936bcf6 | 14965 | dev->features |= NETIF_F_TSO_ECN; |
7fe876af ED |
14966 | vlan_features_add(dev, NETIF_F_TSO_ECN); |
14967 | } | |
b0026624 | 14968 | } |
1da177e4 | 14969 | |
1da177e4 LT |
14970 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
14971 | !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
14972 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
14973 | tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; | |
14974 | tp->rx_pending = 63; | |
14975 | } | |
14976 | ||
1da177e4 LT |
14977 | err = tg3_get_device_address(tp); |
14978 | if (err) { | |
ab96b241 MC |
14979 | dev_err(&pdev->dev, |
14980 | "Could not obtain valid ethernet address, aborting\n"); | |
026a6c21 | 14981 | goto err_out_iounmap; |
1da177e4 LT |
14982 | } |
14983 | ||
c88864df | 14984 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
63532394 | 14985 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); |
79ea13ce | 14986 | if (!tp->aperegs) { |
ab96b241 MC |
14987 | dev_err(&pdev->dev, |
14988 | "Cannot map APE registers, aborting\n"); | |
c88864df | 14989 | err = -ENOMEM; |
026a6c21 | 14990 | goto err_out_iounmap; |
c88864df MC |
14991 | } |
14992 | ||
14993 | tg3_ape_lock_init(tp); | |
7fd76445 MC |
14994 | |
14995 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
14996 | tg3_read_dash_ver(tp); | |
c88864df MC |
14997 | } |
14998 | ||
1da177e4 LT |
14999 | /* |
15000 | * Reset chip in case UNDI or EFI driver did not shutdown | |
15001 | * DMA self test will enable WDMAC and we'll see (spurious) | |
15002 | * pending DMA on the PCI bus at that point. | |
15003 | */ | |
15004 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
15005 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 15006 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 15007 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
15008 | } |
15009 | ||
15010 | err = tg3_test_dma(tp); | |
15011 | if (err) { | |
ab96b241 | 15012 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 15013 | goto err_out_apeunmap; |
1da177e4 LT |
15014 | } |
15015 | ||
78f90dcf MC |
15016 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
15017 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
15018 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
6fd45cb8 | 15019 | for (i = 0; i < tp->irq_max; i++) { |
78f90dcf MC |
15020 | struct tg3_napi *tnapi = &tp->napi[i]; |
15021 | ||
15022 | tnapi->tp = tp; | |
15023 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
15024 | ||
15025 | tnapi->int_mbox = intmbx; | |
15026 | if (i < 4) | |
15027 | intmbx += 0x8; | |
15028 | else | |
15029 | intmbx += 0x4; | |
15030 | ||
15031 | tnapi->consmbox = rcvmbx; | |
15032 | tnapi->prodmbox = sndmbx; | |
15033 | ||
66cfd1bd | 15034 | if (i) |
78f90dcf | 15035 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
66cfd1bd | 15036 | else |
78f90dcf | 15037 | tnapi->coal_now = HOSTCC_MODE_NOW; |
78f90dcf MC |
15038 | |
15039 | if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)) | |
15040 | break; | |
15041 | ||
15042 | /* | |
15043 | * If we support MSIX, we'll be using RSS. If we're using | |
15044 | * RSS, the first vector only handles link interrupts and the | |
15045 | * remaining vectors handle rx and tx interrupts. Reuse the | |
15046 | * mailbox values for the next iteration. The values we setup | |
15047 | * above are still useful for the single vectored mode. | |
15048 | */ | |
15049 | if (!i) | |
15050 | continue; | |
15051 | ||
15052 | rcvmbx += 0x8; | |
15053 | ||
15054 | if (sndmbx & 0x4) | |
15055 | sndmbx -= 0x4; | |
15056 | else | |
15057 | sndmbx += 0xc; | |
15058 | } | |
15059 | ||
15f9850d DM |
15060 | tg3_init_coal(tp); |
15061 | ||
c49a1561 MC |
15062 | pci_set_drvdata(pdev, dev); |
15063 | ||
1da177e4 LT |
15064 | err = register_netdev(dev); |
15065 | if (err) { | |
ab96b241 | 15066 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 15067 | goto err_out_apeunmap; |
1da177e4 LT |
15068 | } |
15069 | ||
05dbe005 JP |
15070 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
15071 | tp->board_part_number, | |
15072 | tp->pci_chip_rev_id, | |
15073 | tg3_bus_string(tp, str), | |
15074 | dev->dev_addr); | |
1da177e4 | 15075 | |
f07e9af3 | 15076 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
3f0e3ad7 MC |
15077 | struct phy_device *phydev; |
15078 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
15079 | netdev_info(dev, |
15080 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 15081 | phydev->drv->name, dev_name(&phydev->dev)); |
f07e9af3 MC |
15082 | } else { |
15083 | char *ethtype; | |
15084 | ||
15085 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) | |
15086 | ethtype = "10/100Base-TX"; | |
15087 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | |
15088 | ethtype = "1000Base-SX"; | |
15089 | else | |
15090 | ethtype = "10/100/1000Base-T"; | |
15091 | ||
5129c3a3 | 15092 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
f07e9af3 MC |
15093 | "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype, |
15094 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0); | |
15095 | } | |
05dbe005 JP |
15096 | |
15097 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
15098 | (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0, | |
15099 | (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, | |
f07e9af3 | 15100 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
05dbe005 JP |
15101 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, |
15102 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); | |
15103 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", | |
15104 | tp->dma_rwctrl, | |
15105 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
15106 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 LT |
15107 | |
15108 | return 0; | |
15109 | ||
0d3031d9 MC |
15110 | err_out_apeunmap: |
15111 | if (tp->aperegs) { | |
15112 | iounmap(tp->aperegs); | |
15113 | tp->aperegs = NULL; | |
15114 | } | |
15115 | ||
1da177e4 | 15116 | err_out_iounmap: |
6892914f MC |
15117 | if (tp->regs) { |
15118 | iounmap(tp->regs); | |
22abe310 | 15119 | tp->regs = NULL; |
6892914f | 15120 | } |
1da177e4 LT |
15121 | |
15122 | err_out_free_dev: | |
15123 | free_netdev(dev); | |
15124 | ||
15125 | err_out_free_res: | |
15126 | pci_release_regions(pdev); | |
15127 | ||
15128 | err_out_disable_pdev: | |
15129 | pci_disable_device(pdev); | |
15130 | pci_set_drvdata(pdev, NULL); | |
15131 | return err; | |
15132 | } | |
15133 | ||
15134 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
15135 | { | |
15136 | struct net_device *dev = pci_get_drvdata(pdev); | |
15137 | ||
15138 | if (dev) { | |
15139 | struct tg3 *tp = netdev_priv(dev); | |
15140 | ||
077f849d JSR |
15141 | if (tp->fw) |
15142 | release_firmware(tp->fw); | |
15143 | ||
23f333a2 | 15144 | cancel_work_sync(&tp->reset_task); |
158d7abd | 15145 | |
b02fd9e3 MC |
15146 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
15147 | tg3_phy_fini(tp); | |
158d7abd | 15148 | tg3_mdio_fini(tp); |
b02fd9e3 | 15149 | } |
158d7abd | 15150 | |
1da177e4 | 15151 | unregister_netdev(dev); |
0d3031d9 MC |
15152 | if (tp->aperegs) { |
15153 | iounmap(tp->aperegs); | |
15154 | tp->aperegs = NULL; | |
15155 | } | |
6892914f MC |
15156 | if (tp->regs) { |
15157 | iounmap(tp->regs); | |
22abe310 | 15158 | tp->regs = NULL; |
6892914f | 15159 | } |
1da177e4 LT |
15160 | free_netdev(dev); |
15161 | pci_release_regions(pdev); | |
15162 | pci_disable_device(pdev); | |
15163 | pci_set_drvdata(pdev, NULL); | |
15164 | } | |
15165 | } | |
15166 | ||
aa6027ca | 15167 | #ifdef CONFIG_PM_SLEEP |
c866b7ea | 15168 | static int tg3_suspend(struct device *device) |
1da177e4 | 15169 | { |
c866b7ea | 15170 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15171 | struct net_device *dev = pci_get_drvdata(pdev); |
15172 | struct tg3 *tp = netdev_priv(dev); | |
15173 | int err; | |
15174 | ||
15175 | if (!netif_running(dev)) | |
15176 | return 0; | |
15177 | ||
23f333a2 | 15178 | flush_work_sync(&tp->reset_task); |
b02fd9e3 | 15179 | tg3_phy_stop(tp); |
1da177e4 LT |
15180 | tg3_netif_stop(tp); |
15181 | ||
15182 | del_timer_sync(&tp->timer); | |
15183 | ||
f47c11ee | 15184 | tg3_full_lock(tp, 1); |
1da177e4 | 15185 | tg3_disable_ints(tp); |
f47c11ee | 15186 | tg3_full_unlock(tp); |
1da177e4 LT |
15187 | |
15188 | netif_device_detach(dev); | |
15189 | ||
f47c11ee | 15190 | tg3_full_lock(tp, 0); |
944d980e | 15191 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
6a9eba15 | 15192 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
f47c11ee | 15193 | tg3_full_unlock(tp); |
1da177e4 | 15194 | |
c866b7ea | 15195 | err = tg3_power_down_prepare(tp); |
1da177e4 | 15196 | if (err) { |
b02fd9e3 MC |
15197 | int err2; |
15198 | ||
f47c11ee | 15199 | tg3_full_lock(tp, 0); |
1da177e4 | 15200 | |
6a9eba15 | 15201 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b02fd9e3 MC |
15202 | err2 = tg3_restart_hw(tp, 1); |
15203 | if (err2) | |
b9ec6c1b | 15204 | goto out; |
1da177e4 LT |
15205 | |
15206 | tp->timer.expires = jiffies + tp->timer_offset; | |
15207 | add_timer(&tp->timer); | |
15208 | ||
15209 | netif_device_attach(dev); | |
15210 | tg3_netif_start(tp); | |
15211 | ||
b9ec6c1b | 15212 | out: |
f47c11ee | 15213 | tg3_full_unlock(tp); |
b02fd9e3 MC |
15214 | |
15215 | if (!err2) | |
15216 | tg3_phy_start(tp); | |
1da177e4 LT |
15217 | } |
15218 | ||
15219 | return err; | |
15220 | } | |
15221 | ||
c866b7ea | 15222 | static int tg3_resume(struct device *device) |
1da177e4 | 15223 | { |
c866b7ea | 15224 | struct pci_dev *pdev = to_pci_dev(device); |
1da177e4 LT |
15225 | struct net_device *dev = pci_get_drvdata(pdev); |
15226 | struct tg3 *tp = netdev_priv(dev); | |
15227 | int err; | |
15228 | ||
15229 | if (!netif_running(dev)) | |
15230 | return 0; | |
15231 | ||
1da177e4 LT |
15232 | netif_device_attach(dev); |
15233 | ||
f47c11ee | 15234 | tg3_full_lock(tp, 0); |
1da177e4 | 15235 | |
6a9eba15 | 15236 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b9ec6c1b MC |
15237 | err = tg3_restart_hw(tp, 1); |
15238 | if (err) | |
15239 | goto out; | |
1da177e4 LT |
15240 | |
15241 | tp->timer.expires = jiffies + tp->timer_offset; | |
15242 | add_timer(&tp->timer); | |
15243 | ||
1da177e4 LT |
15244 | tg3_netif_start(tp); |
15245 | ||
b9ec6c1b | 15246 | out: |
f47c11ee | 15247 | tg3_full_unlock(tp); |
1da177e4 | 15248 | |
b02fd9e3 MC |
15249 | if (!err) |
15250 | tg3_phy_start(tp); | |
15251 | ||
b9ec6c1b | 15252 | return err; |
1da177e4 LT |
15253 | } |
15254 | ||
c866b7ea | 15255 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
aa6027ca ED |
15256 | #define TG3_PM_OPS (&tg3_pm_ops) |
15257 | ||
15258 | #else | |
15259 | ||
15260 | #define TG3_PM_OPS NULL | |
15261 | ||
15262 | #endif /* CONFIG_PM_SLEEP */ | |
c866b7ea | 15263 | |
1da177e4 LT |
15264 | static struct pci_driver tg3_driver = { |
15265 | .name = DRV_MODULE_NAME, | |
15266 | .id_table = tg3_pci_tbl, | |
15267 | .probe = tg3_init_one, | |
15268 | .remove = __devexit_p(tg3_remove_one), | |
aa6027ca | 15269 | .driver.pm = TG3_PM_OPS, |
1da177e4 LT |
15270 | }; |
15271 | ||
15272 | static int __init tg3_init(void) | |
15273 | { | |
29917620 | 15274 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
15275 | } |
15276 | ||
15277 | static void __exit tg3_cleanup(void) | |
15278 | { | |
15279 | pci_unregister_driver(&tg3_driver); | |
15280 | } | |
15281 | ||
15282 | module_init(tg3_init); | |
15283 | module_exit(tg3_cleanup); |