]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/tg3.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tg3 / broadcom: Add APD support for GPHYs
[mirror_ubuntu-artful-kernel.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
daf09de8
MC		 71#define DRV_MODULE_VERSION "3.102"
72#define DRV_MODULE_RELDATE "September 1, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 139
140/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 141#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 142
ad829268
MC		 143#define TG3_RAW_IP_ALIGN 2
144
1da177e4
LT		 145/* number of ETHTOOL_GSTATS u64's */
146#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
4cafd3f5
MC		 148#define TG3_NUM_TEST 6
149
077f849d
JSR		 150#define FIRMWARE_TG3 "tigon/tg3.bin"
151#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
1da177e4
LT		 154static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 161MODULE_FIRMWARE(FIRMWARE_TG3);
162MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
679563f4 165#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 166
167static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168module_param(tg3_debug, int, 0);
169MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
1da177e4
LT		 246};
247
248MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
50da859d 250static const struct {
1da177e4
LT		 251 const char string[ETH_GSTRING_LEN];
252} ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329};
330
50da859d 331static const struct {
4cafd3f5
MC		 332 const char string[ETH_GSTRING_LEN];
333} ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340};
341
b401e9e2
MC		 342static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->regs + off);
345}
346
347static u32 tg3_read32(struct tg3 *tp, u32 off)
348{
6aa20a22 349 return (readl(tp->regs + off));
b401e9e2
MC		 350}
351
0d3031d9
MC		 352static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353{
354 writel(val, tp->aperegs + off);
355}
356
357static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358{
359 return (readl(tp->aperegs + off));
360}
361
1da177e4
LT		 362static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363{
6892914f
MC		 364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 370}
371
372static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373{
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
1da177e4
LT		 376}
377
6892914f 378static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 379{
6892914f
MC		 380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388}
389
390static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391{
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
1da177e4 403 }
6892914f
MC		 404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418}
419
420static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421{
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430}
431
b401e9e2
MC		 432/* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 438{
b401e9e2
MC		 439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
1da177e4
LT		 455}
456
09ee929c
MC		 457static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458{
459 tp->write32_mbox(tp, off, val);
6892914f
MC		 460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
09ee929c
MC		 463}
464
20094930 465static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 466{
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473}
474
b5d3772c
MC		 475static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476{
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478}
479
480static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481{
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483}
484
20094930 485#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 486#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 487#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 489#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 490
491#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 492#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 494#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 495
496static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497{
6892914f
MC		 498 unsigned long flags;
499
b5d3772c
MC		 500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
6892914f 504 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 508
bbadf503
MC		 509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 514
bbadf503
MC		 515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 519}
520
1da177e4
LT		 521static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522{
6892914f
MC		 523 unsigned long flags;
524
b5d3772c
MC		 525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
6892914f 531 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 535
bbadf503
MC		 536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
6892914f 545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 546}
547
0d3031d9
MC		 548static void tg3_ape_lock_init(struct tg3 *tp)
549{
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556}
557
558static int tg3_ape_lock(struct tg3 *tp, int locknum)
559{
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
77b483f1 568 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596}
597
598static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599{
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
77b483f1 606 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615}
616
1da177e4
LT		 617static void tg3_disable_ints(struct tg3 *tp)
618{
89aeb3bc
MC		 619 int i;
620
1da177e4
LT		 621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 625}
626
1da177e4
LT		 627static void tg3_enable_ints(struct tg3 *tp)
628{
89aeb3bc
MC		 629 int i;
630 u32 coal_now = 0;
631
bbe832c0
MC		 632 tp->irq_sync = 0;
633 wmb();
634
1da177e4
LT		 635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 643
89aeb3bc
MC		 644 coal_now |= tnapi->coal_now;
645 }
f19af9c2
MC		 646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 654}
655
17375d25 656static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 657{
17375d25 658 struct tg3 *tp = tnapi->tp;
898a56f8 659 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
f3f3f27e 670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 672 work_exists = 1;
673
674 return work_exists;
675}
676
17375d25 677/* tg3_int_reenable
04237ddd
MC		 678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
6aa20a22 680 * which reenables interrupts
1da177e4 681 */
17375d25 682static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 683{
17375d25
MC		 684 struct tg3 *tp = tnapi->tp;
685
898a56f8 686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 687 mmiowb();
688
fac9b83e
DM		 689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 694 tg3_has_work(tnapi))
04237ddd 695 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 697}
698
fed97810
MC		 699static void tg3_napi_disable(struct tg3 *tp)
700{
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705}
706
707static void tg3_napi_enable(struct tg3 *tp)
708{
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713}
714
1da177e4
LT		 715static inline void tg3_netif_stop(struct tg3 *tp)
716{
bbe832c0 717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 718 tg3_napi_disable(tp);
1da177e4
LT		 719 netif_tx_disable(tp->dev);
720}
721
722static inline void tg3_netif_start(struct tg3 *tp)
723{
fe5f5787
MC		 724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
1da177e4 727 */
fe5f5787
MC		 728 netif_tx_wake_all_queues(tp->dev);
729
fed97810
MC		 730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 732 tg3_enable_ints(tp);
1da177e4
LT		 733}
734
735static void tg3_switch_clocks(struct tg3 *tp)
736{
f6eb9b1f 737 u32 clock_ctrl;
1da177e4
LT		 738 u32 orig_clock_ctrl;
739
795d01c5
MC		 740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 742 return;
743
f6eb9b1f
MC		 744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
1da177e4
LT		 746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
1da177e4 765 }
b401e9e2 766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 767}
768
769#define PHY_BUSY_LOOPS 5000
770
771static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772{
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
882e9793 785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 790
1da177e4
LT		 791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818}
819
820static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821{
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
7f97a4bd 826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
1da177e4
LT		 830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
882e9793 836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 842
1da177e4
LT		 843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867}
868
95e2869a
MC		 869static int tg3_bmcr_reset(struct tg3 *tp)
870{
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
d4675b52 894 if (limit < 0)
95e2869a
MC		 895 return -EBUSY;
896
897 return 0;
898}
899
158d7abd
MC		 900static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901{
3d16543d 902 struct tg3 *tp = bp->priv;
158d7abd
MC		 903 u32 val;
904
24bb4fb6 905 spin_lock_bh(&tp->lock);
158d7abd
MC		 906
907 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
158d7abd
MC		 911
912 return val;
913}
914
915static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916{
3d16543d 917 struct tg3 *tp = bp->priv;
24bb4fb6 918 u32 ret = 0;
158d7abd 919
24bb4fb6 920 spin_lock_bh(&tp->lock);
158d7abd
MC		 921
922 if (tg3_writephy(tp, reg, val))
24bb4fb6 923 ret = -EIO;
158d7abd 924
24bb4fb6
MC		 925 spin_unlock_bh(&tp->lock);
926
927 return ret;
158d7abd
MC		 928}
929
930static int tg3_mdio_reset(struct mii_bus *bp)
931{
932 return 0;
933}
934
9c61d6bc 935static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 936{
937 u32 val;
fcb389df 938 struct phy_device *phydev;
a9daf367 939
3f0e3ad7 940 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
c73430d0 943 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 944 val = MAC_PHYCFG2_50610_LED_MODES;
945 break;
946 case TG3_PHY_ID_BCMAC131:
947 val = MAC_PHYCFG2_AC131_LED_MODES;
948 break;
949 case TG3_PHY_ID_RTL8211C:
950 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
951 break;
952 case TG3_PHY_ID_RTL8201E:
953 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
954 break;
955 default:
a9daf367 956 return;
fcb389df
MC		 957 }
958
959 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
960 tw32(MAC_PHYCFG2, val);
961
962 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 963 val &= ~(MAC_PHYCFG1_RGMII_INT |
964 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
965 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 966 tw32(MAC_PHYCFG1, val);
967
968 return;
969 }
970
971 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
972 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
973 MAC_PHYCFG2_FMODE_MASK_MASK |
974 MAC_PHYCFG2_GMODE_MASK_MASK |
975 MAC_PHYCFG2_ACT_MASK_MASK |
976 MAC_PHYCFG2_QUAL_MASK_MASK |
977 MAC_PHYCFG2_INBAND_ENABLE;
978
979 tw32(MAC_PHYCFG2, val);
a9daf367 980
bb85fbb6
MC		 981 val = tr32(MAC_PHYCFG1);
982 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
983 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
984 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 985 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
986 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
987 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
988 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
989 }
bb85fbb6
MC		 990 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
991 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
992 tw32(MAC_PHYCFG1, val);
a9daf367 993
a9daf367
MC		 994 val = tr32(MAC_EXT_RGMII_MODE);
995 val &= ~(MAC_RGMII_MODE_RX_INT_B |
996 MAC_RGMII_MODE_RX_QUALITY |
997 MAC_RGMII_MODE_RX_ACTIVITY |
998 MAC_RGMII_MODE_RX_ENG_DET |
999 MAC_RGMII_MODE_TX_ENABLE |
1000 MAC_RGMII_MODE_TX_LOWPWR |
1001 MAC_RGMII_MODE_TX_RESET);
fcb389df 1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET;
1008 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009 val |= MAC_RGMII_MODE_TX_ENABLE |
1010 MAC_RGMII_MODE_TX_LOWPWR |
1011 MAC_RGMII_MODE_TX_RESET;
1012 }
1013 tw32(MAC_EXT_RGMII_MODE, val);
1014}
1015
158d7abd
MC		 1016static void tg3_mdio_start(struct tg3 *tp)
1017{
158d7abd
MC		 1018 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019 tw32_f(MAC_MI_MODE, tp->mi_mode);
1020 udelay(80);
a9daf367 1021
882e9793
MC		 1022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023 u32 funcnum, is_serdes;
1024
1025 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026 if (funcnum)
1027 tp->phy_addr = 2;
1028 else
1029 tp->phy_addr = 1;
1030
1031 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032 if (is_serdes)
1033 tp->phy_addr += 7;
1034 } else
3f0e3ad7 1035 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1036
9c61d6bc
MC		 1037 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039 tg3_mdio_config_5785(tp);
158d7abd
MC		 1040}
1041
158d7abd
MC		 1042static int tg3_mdio_init(struct tg3 *tp)
1043{
1044 int i;
1045 u32 reg;
a9daf367 1046 struct phy_device *phydev;
158d7abd
MC		 1047
1048 tg3_mdio_start(tp);
1049
1050 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052 return 0;
1053
298cf9be
LB		 1054 tp->mdio_bus = mdiobus_alloc();
1055 if (tp->mdio_bus == NULL)
1056 return -ENOMEM;
158d7abd 1057
298cf9be
LB		 1058 tp->mdio_bus->name = "tg3 mdio bus";
1059 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1060 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1061 tp->mdio_bus->priv = tp;
1062 tp->mdio_bus->parent = &tp->pdev->dev;
1063 tp->mdio_bus->read = &tg3_mdio_read;
1064 tp->mdio_bus->write = &tg3_mdio_write;
1065 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1066 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1067 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1068
1069 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1070 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1071
1072 /* The bus registration will look for all the PHYs on the mdio bus.
1073 * Unfortunately, it does not ensure the PHY is powered up before
1074 * accessing the PHY ID registers. A chip reset is the
1075 * quickest way to bring the device back to an operational state..
1076 */
1077 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078 tg3_bmcr_reset(tp);
1079
298cf9be 1080 i = mdiobus_register(tp->mdio_bus);
a9daf367 1081 if (i) {
158d7abd
MC		 1082 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083 tp->dev->name, i);
9c61d6bc 1084 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1085 return i;
1086 }
158d7abd 1087
3f0e3ad7 1088 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1089
9c61d6bc
MC		 1090 if (!phydev || !phydev->drv) {
1091 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092 mdiobus_unregister(tp->mdio_bus);
1093 mdiobus_free(tp->mdio_bus);
1094 return -ENODEV;
1095 }
1096
1097 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1098 case TG3_PHY_ID_BCM57780:
1099 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1100 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1101 break;
a9daf367 1102 case TG3_PHY_ID_BCM50610:
c73430d0 1103 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1104 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23
MC		 1105 PHY_BRCM_RX_REFCLK_UNUSED |
1106 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1107 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1108 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1109 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1110 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1111 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1112 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1113 /* fallthru */
1114 case TG3_PHY_ID_RTL8211C:
1115 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1116 break;
fcb389df 1117 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1118 case TG3_PHY_ID_BCMAC131:
1119 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1120 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1121 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1122 break;
1123 }
1124
9c61d6bc
MC		 1125 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1126
1127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1128 tg3_mdio_config_5785(tp);
a9daf367
MC		 1129
1130 return 0;
158d7abd
MC		 1131}
1132
1133static void tg3_mdio_fini(struct tg3 *tp)
1134{
1135 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1136 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1137 mdiobus_unregister(tp->mdio_bus);
1138 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1139 }
1140}
1141
4ba526ce
MC		 1142/* tp->lock is held. */
1143static inline void tg3_generate_fw_event(struct tg3 *tp)
1144{
1145 u32 val;
1146
1147 val = tr32(GRC_RX_CPU_EVENT);
1148 val |= GRC_RX_CPU_DRIVER_EVENT;
1149 tw32_f(GRC_RX_CPU_EVENT, val);
1150
1151 tp->last_event_jiffies = jiffies;
1152}
1153
1154#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1155
95e2869a
MC		 1156/* tp->lock is held. */
1157static void tg3_wait_for_event_ack(struct tg3 *tp)
1158{
1159 int i;
4ba526ce
MC		 1160 unsigned int delay_cnt;
1161 long time_remain;
1162
1163 /* If enough time has passed, no wait is necessary. */
1164 time_remain = (long)(tp->last_event_jiffies + 1 +
1165 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1166 (long)jiffies;
1167 if (time_remain < 0)
1168 return;
1169
1170 /* Check if we can shorten the wait time. */
1171 delay_cnt = jiffies_to_usecs(time_remain);
1172 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1173 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1174 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1175
4ba526ce 1176 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1177 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1178 break;
4ba526ce 1179 udelay(8);
95e2869a
MC		 1180 }
1181}
1182
1183/* tp->lock is held. */
1184static void tg3_ump_link_report(struct tg3 *tp)
1185{
1186 u32 reg;
1187 u32 val;
1188
1189 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1190 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1191 return;
1192
1193 tg3_wait_for_event_ack(tp);
1194
1195 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1196
1197 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1198
1199 val = 0;
1200 if (!tg3_readphy(tp, MII_BMCR, &reg))
1201 val = reg << 16;
1202 if (!tg3_readphy(tp, MII_BMSR, &reg))
1203 val |= (reg & 0xffff);
1204 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1205
1206 val = 0;
1207 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1208 val = reg << 16;
1209 if (!tg3_readphy(tp, MII_LPA, &reg))
1210 val |= (reg & 0xffff);
1211 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1212
1213 val = 0;
1214 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1215 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1216 val = reg << 16;
1217 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1218 val |= (reg & 0xffff);
1219 }
1220 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1221
1222 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1223 val = reg << 16;
1224 else
1225 val = 0;
1226 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1227
4ba526ce 1228 tg3_generate_fw_event(tp);
95e2869a
MC		 1229}
1230
1231static void tg3_link_report(struct tg3 *tp)
1232{
1233 if (!netif_carrier_ok(tp->dev)) {
1234 if (netif_msg_link(tp))
1235 printk(KERN_INFO PFX "%s: Link is down.\n",
1236 tp->dev->name);
1237 tg3_ump_link_report(tp);
1238 } else if (netif_msg_link(tp)) {
1239 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1240 tp->dev->name,
1241 (tp->link_config.active_speed == SPEED_1000 ?
1242 1000 :
1243 (tp->link_config.active_speed == SPEED_100 ?
1244 100 : 10)),
1245 (tp->link_config.active_duplex == DUPLEX_FULL ?
1246 "full" : "half"));
1247
1248 printk(KERN_INFO PFX
1249 "%s: Flow control is %s for TX and %s for RX.\n",
1250 tp->dev->name,
e18ce346 1251 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1252 "on" : "off",
e18ce346 1253 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1254 "on" : "off");
1255 tg3_ump_link_report(tp);
1256 }
1257}
1258
1259static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1260{
1261 u16 miireg;
1262
e18ce346 1263 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1264 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1265 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1266 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1267 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1268 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1269 else
1270 miireg = 0;
1271
1272 return miireg;
1273}
1274
1275static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1276{
1277 u16 miireg;
1278
e18ce346 1279 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1280 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1281 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1282 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1283 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1284 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1285 else
1286 miireg = 0;
1287
1288 return miireg;
1289}
1290
95e2869a
MC		 1291static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1292{
1293 u8 cap = 0;
1294
1295 if (lcladv & ADVERTISE_1000XPAUSE) {
1296 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1297 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1298 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1299 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1300 cap = FLOW_CTRL_RX;
95e2869a
MC		 1301 } else {
1302 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1303 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1304 }
1305 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1306 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1307 cap = FLOW_CTRL_TX;
95e2869a
MC		 1308 }
1309
1310 return cap;
1311}
1312
f51f3562 1313static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1314{
b02fd9e3 1315 u8 autoneg;
f51f3562 1316 u8 flowctrl = 0;
95e2869a
MC		 1317 u32 old_rx_mode = tp->rx_mode;
1318 u32 old_tx_mode = tp->tx_mode;
1319
b02fd9e3 1320 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1321 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1322 else
1323 autoneg = tp->link_config.autoneg;
1324
1325 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1326 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1327 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1328 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1329 else
bc02ff95 1330 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1331 } else
1332 flowctrl = tp->link_config.flowctrl;
95e2869a 1333
f51f3562 1334 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1335
e18ce346 1336 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1337 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1338 else
1339 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1340
f51f3562 1341 if (old_rx_mode != tp->rx_mode)
95e2869a 1342 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1343
e18ce346 1344 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1345 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1346 else
1347 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1348
f51f3562 1349 if (old_tx_mode != tp->tx_mode)
95e2869a 1350 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1351}
1352
b02fd9e3
MC		 1353static void tg3_adjust_link(struct net_device *dev)
1354{
1355 u8 oldflowctrl, linkmesg = 0;
1356 u32 mac_mode, lcl_adv, rmt_adv;
1357 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1358 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1359
24bb4fb6 1360 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1361
1362 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1363 MAC_MODE_HALF_DUPLEX);
1364
1365 oldflowctrl = tp->link_config.active_flowctrl;
1366
1367 if (phydev->link) {
1368 lcl_adv = 0;
1369 rmt_adv = 0;
1370
1371 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1372 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1373 else if (phydev->speed == SPEED_1000 ||
1374 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1375 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1376 else
1377 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1378
1379 if (phydev->duplex == DUPLEX_HALF)
1380 mac_mode |= MAC_MODE_HALF_DUPLEX;
1381 else {
1382 lcl_adv = tg3_advert_flowctrl_1000T(
1383 tp->link_config.flowctrl);
1384
1385 if (phydev->pause)
1386 rmt_adv = LPA_PAUSE_CAP;
1387 if (phydev->asym_pause)
1388 rmt_adv |= LPA_PAUSE_ASYM;
1389 }
1390
1391 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1392 } else
1393 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1394
1395 if (mac_mode != tp->mac_mode) {
1396 tp->mac_mode = mac_mode;
1397 tw32_f(MAC_MODE, tp->mac_mode);
1398 udelay(40);
1399 }
1400
fcb389df
MC		 1401 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1402 if (phydev->speed == SPEED_10)
1403 tw32(MAC_MI_STAT,
1404 MAC_MI_STAT_10MBPS_MODE |
1405 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1406 else
1407 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1408 }
1409
b02fd9e3
MC		 1410 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1411 tw32(MAC_TX_LENGTHS,
1412 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1413 (6 << TX_LENGTHS_IPG_SHIFT) |
1414 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1415 else
1416 tw32(MAC_TX_LENGTHS,
1417 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1418 (6 << TX_LENGTHS_IPG_SHIFT) |
1419 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1420
1421 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1422 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1423 phydev->speed != tp->link_config.active_speed ||
1424 phydev->duplex != tp->link_config.active_duplex ||
1425 oldflowctrl != tp->link_config.active_flowctrl)
1426 linkmesg = 1;
1427
1428 tp->link_config.active_speed = phydev->speed;
1429 tp->link_config.active_duplex = phydev->duplex;
1430
24bb4fb6 1431 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1432
1433 if (linkmesg)
1434 tg3_link_report(tp);
1435}
1436
1437static int tg3_phy_init(struct tg3 *tp)
1438{
1439 struct phy_device *phydev;
1440
1441 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1442 return 0;
1443
1444 /* Bring the PHY back to a known state. */
1445 tg3_bmcr_reset(tp);
1446
3f0e3ad7 1447 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1448
1449 /* Attach the MAC to the PHY. */
fb28ad35 1450 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1451 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1452 if (IS_ERR(phydev)) {
1453 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1454 return PTR_ERR(phydev);
1455 }
1456
b02fd9e3 1457 /* Mask with MAC supported features. */
9c61d6bc
MC		 1458 switch (phydev->interface) {
1459 case PHY_INTERFACE_MODE_GMII:
1460 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1461 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1462 phydev->supported &= (PHY_GBIT_FEATURES |
1463 SUPPORTED_Pause |
1464 SUPPORTED_Asym_Pause);
1465 break;
1466 }
1467 /* fallthru */
9c61d6bc
MC		 1468 case PHY_INTERFACE_MODE_MII:
1469 phydev->supported &= (PHY_BASIC_FEATURES |
1470 SUPPORTED_Pause |
1471 SUPPORTED_Asym_Pause);
1472 break;
1473 default:
3f0e3ad7 1474 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1475 return -EINVAL;
1476 }
1477
1478 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1479
1480 phydev->advertising = phydev->supported;
1481
b02fd9e3
MC		 1482 return 0;
1483}
1484
1485static void tg3_phy_start(struct tg3 *tp)
1486{
1487 struct phy_device *phydev;
1488
1489 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1490 return;
1491
3f0e3ad7 1492 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1493
1494 if (tp->link_config.phy_is_low_power) {
1495 tp->link_config.phy_is_low_power = 0;
1496 phydev->speed = tp->link_config.orig_speed;
1497 phydev->duplex = tp->link_config.orig_duplex;
1498 phydev->autoneg = tp->link_config.orig_autoneg;
1499 phydev->advertising = tp->link_config.orig_advertising;
1500 }
1501
1502 phy_start(phydev);
1503
1504 phy_start_aneg(phydev);
1505}
1506
1507static void tg3_phy_stop(struct tg3 *tp)
1508{
1509 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1510 return;
1511
3f0e3ad7 1512 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1513}
1514
1515static void tg3_phy_fini(struct tg3 *tp)
1516{
1517 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1518 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1519 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1520 }
1521}
1522
b2a5c19c
MC		 1523static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1524{
1525 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1526 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1527}
1528
7f97a4bd
MC		 1529static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1530{
1531 u32 phytest;
1532
1533 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1534 u32 phy;
1535
1536 tg3_writephy(tp, MII_TG3_FET_TEST,
1537 phytest | MII_TG3_FET_SHADOW_EN);
1538 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1539 if (enable)
1540 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1541 else
1542 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1543 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1544 }
1545 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1546 }
1547}
1548
6833c043
MC		 1549static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1550{
1551 u32 reg;
1552
7f97a4bd 1553 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1554 return;
1555
7f97a4bd
MC		 1556 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1557 tg3_phy_fet_toggle_apd(tp, enable);
1558 return;
1559 }
1560
6833c043
MC		 1561 reg = MII_TG3_MISC_SHDW_WREN |
1562 MII_TG3_MISC_SHDW_SCR5_SEL |
1563 MII_TG3_MISC_SHDW_SCR5_LPED |
1564 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1565 MII_TG3_MISC_SHDW_SCR5_SDTL |
1566 MII_TG3_MISC_SHDW_SCR5_C125OE;
1567 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1568 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1569
1570 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1571
1572
1573 reg = MII_TG3_MISC_SHDW_WREN |
1574 MII_TG3_MISC_SHDW_APD_SEL |
1575 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1576 if (enable)
1577 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1578
1579 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1580}
1581
9ef8ca99
MC		 1582static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1583{
1584 u32 phy;
1585
1586 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1587 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1588 return;
1589
7f97a4bd 1590 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1591 u32 ephy;
1592
535ef6e1
MC		 1593 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1594 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1595
1596 tg3_writephy(tp, MII_TG3_FET_TEST,
1597 ephy | MII_TG3_FET_SHADOW_EN);
1598 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1599 if (enable)
535ef6e1 1600 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1601 else
535ef6e1
MC		 1602 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1603 tg3_writephy(tp, reg, phy);
9ef8ca99 1604 }
535ef6e1 1605 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1606 }
1607 } else {
1608 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1609 MII_TG3_AUXCTL_SHDWSEL_MISC;
1610 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1611 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1612 if (enable)
1613 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1614 else
1615 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1616 phy |= MII_TG3_AUXCTL_MISC_WREN;
1617 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1618 }
1619 }
1620}
1621
1da177e4
LT		 1622static void tg3_phy_set_wirespeed(struct tg3 *tp)
1623{
1624 u32 val;
1625
1626 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1627 return;
1628
1629 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1630 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1631 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1632 (val | (1 << 15) | (1 << 4)));
1633}
1634
b2a5c19c
MC		 1635static void tg3_phy_apply_otp(struct tg3 *tp)
1636{
1637 u32 otp, phy;
1638
1639 if (!tp->phy_otp)
1640 return;
1641
1642 otp = tp->phy_otp;
1643
1644 /* Enable SM_DSP clock and tx 6dB coding. */
1645 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1646 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1647 MII_TG3_AUXCTL_ACTL_TX_6DB;
1648 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1649
1650 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1651 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1652 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1653
1654 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1655 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1656 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1657
1658 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1659 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1660 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1661
1662 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1663 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1664
1665 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1666 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1667
1668 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1669 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1670 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1671
1672 /* Turn off SM_DSP clock. */
1673 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1674 MII_TG3_AUXCTL_ACTL_TX_6DB;
1675 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1676}
1677
1da177e4
LT		 1678static int tg3_wait_macro_done(struct tg3 *tp)
1679{
1680 int limit = 100;
1681
1682 while (limit--) {
1683 u32 tmp32;
1684
1685 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1686 if ((tmp32 & 0x1000) == 0)
1687 break;
1688 }
1689 }
d4675b52 1690 if (limit < 0)
1da177e4
LT		 1691 return -EBUSY;
1692
1693 return 0;
1694}
1695
1696static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1697{
1698 static const u32 test_pat[4][6] = {
1699 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1700 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1701 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1702 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1703 };
1704 int chan;
1705
1706 for (chan = 0; chan < 4; chan++) {
1707 int i;
1708
1709 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1710 (chan * 0x2000) | 0x0200);
1711 tg3_writephy(tp, 0x16, 0x0002);
1712
1713 for (i = 0; i < 6; i++)
1714 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1715 test_pat[chan][i]);
1716
1717 tg3_writephy(tp, 0x16, 0x0202);
1718 if (tg3_wait_macro_done(tp)) {
1719 *resetp = 1;
1720 return -EBUSY;
1721 }
1722
1723 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1724 (chan * 0x2000) | 0x0200);
1725 tg3_writephy(tp, 0x16, 0x0082);
1726 if (tg3_wait_macro_done(tp)) {
1727 *resetp = 1;
1728 return -EBUSY;
1729 }
1730
1731 tg3_writephy(tp, 0x16, 0x0802);
1732 if (tg3_wait_macro_done(tp)) {
1733 *resetp = 1;
1734 return -EBUSY;
1735 }
1736
1737 for (i = 0; i < 6; i += 2) {
1738 u32 low, high;
1739
1740 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1741 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1742 tg3_wait_macro_done(tp)) {
1743 *resetp = 1;
1744 return -EBUSY;
1745 }
1746 low &= 0x7fff;
1747 high &= 0x000f;
1748 if (low != test_pat[chan][i] ||
1749 high != test_pat[chan][i+1]) {
1750 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1751 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1752 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1753
1754 return -EBUSY;
1755 }
1756 }
1757 }
1758
1759 return 0;
1760}
1761
1762static int tg3_phy_reset_chanpat(struct tg3 *tp)
1763{
1764 int chan;
1765
1766 for (chan = 0; chan < 4; chan++) {
1767 int i;
1768
1769 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1770 (chan * 0x2000) | 0x0200);
1771 tg3_writephy(tp, 0x16, 0x0002);
1772 for (i = 0; i < 6; i++)
1773 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1774 tg3_writephy(tp, 0x16, 0x0202);
1775 if (tg3_wait_macro_done(tp))
1776 return -EBUSY;
1777 }
1778
1779 return 0;
1780}
1781
1782static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1783{
1784 u32 reg32, phy9_orig;
1785 int retries, do_phy_reset, err;
1786
1787 retries = 10;
1788 do_phy_reset = 1;
1789 do {
1790 if (do_phy_reset) {
1791 err = tg3_bmcr_reset(tp);
1792 if (err)
1793 return err;
1794 do_phy_reset = 0;
1795 }
1796
1797 /* Disable transmitter and interrupt. */
1798 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1799 continue;
1800
1801 reg32 |= 0x3000;
1802 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1803
1804 /* Set full-duplex, 1000 mbps. */
1805 tg3_writephy(tp, MII_BMCR,
1806 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1807
1808 /* Set to master mode. */
1809 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1810 continue;
1811
1812 tg3_writephy(tp, MII_TG3_CTRL,
1813 (MII_TG3_CTRL_AS_MASTER |
1814 MII_TG3_CTRL_ENABLE_AS_MASTER));
1815
1816 /* Enable SM_DSP_CLOCK and 6dB. */
1817 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1818
1819 /* Block the PHY control access. */
1820 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1821 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1822
1823 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1824 if (!err)
1825 break;
1826 } while (--retries);
1827
1828 err = tg3_phy_reset_chanpat(tp);
1829 if (err)
1830 return err;
1831
1832 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1834
1835 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1836 tg3_writephy(tp, 0x16, 0x0000);
1837
1838 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1839 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1840 /* Set Extended packet length bit for jumbo frames */
1841 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1842 }
1843 else {
1844 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1845 }
1846
1847 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1848
1849 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1850 reg32 &= ~0x3000;
1851 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1852 } else if (!err)
1853 err = -EBUSY;
1854
1855 return err;
1856}
1857
1858/* This will reset the tigon3 PHY if there is no valid
1859 * link unless the FORCE argument is non-zero.
1860 */
1861static int tg3_phy_reset(struct tg3 *tp)
1862{
b2a5c19c 1863 u32 cpmuctrl;
1da177e4
LT		 1864 u32 phy_status;
1865 int err;
1866
60189ddf
MC		 1867 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1868 u32 val;
1869
1870 val = tr32(GRC_MISC_CFG);
1871 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1872 udelay(40);
1873 }
1da177e4
LT		 1874 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1875 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1876 if (err != 0)
1877 return -EBUSY;
1878
c8e1e82b
MC		 1879 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1880 netif_carrier_off(tp->dev);
1881 tg3_link_report(tp);
1882 }
1883
1da177e4
LT		 1884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1885 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1887 err = tg3_phy_reset_5703_4_5(tp);
1888 if (err)
1889 return err;
1890 goto out;
1891 }
1892
b2a5c19c
MC		 1893 cpmuctrl = 0;
1894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1895 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1896 cpmuctrl = tr32(TG3_CPMU_CTRL);
1897 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1898 tw32(TG3_CPMU_CTRL,
1899 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1900 }
1901
1da177e4
LT		 1902 err = tg3_bmcr_reset(tp);
1903 if (err)
1904 return err;
1905
b2a5c19c
MC		 1906 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1907 u32 phy;
1908
1909 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1910 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1911
1912 tw32(TG3_CPMU_CTRL, cpmuctrl);
1913 }
1914
bcb37f6c
MC		 1915 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1916 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1917 u32 val;
1918
1919 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1920 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1921 CPMU_LSPD_1000MB_MACCLK_12_5) {
1922 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1923 udelay(40);
1924 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1925 }
1926 }
1927
b2a5c19c
MC		 1928 tg3_phy_apply_otp(tp);
1929
6833c043
MC		 1930 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1931 tg3_phy_toggle_apd(tp, true);
1932 else
1933 tg3_phy_toggle_apd(tp, false);
1934
1da177e4
LT		 1935out:
1936 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1937 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1938 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1939 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1940 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1941 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1942 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1943 }
1944 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1945 tg3_writephy(tp, 0x1c, 0x8d68);
1946 tg3_writephy(tp, 0x1c, 0x8d68);
1947 }
1948 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1949 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1952 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1953 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1954 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1955 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1956 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1957 }
c424cb24
MC		 1958 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1959 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1961 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1962 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1963 tg3_writephy(tp, MII_TG3_TEST1,
1964 MII_TG3_TEST1_TRIM_EN | 0x4);
1965 } else
1966 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1967 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1968 }
1da177e4
LT		 1969 /* Set Extended packet length bit (bit 14) on all chips that */
1970 /* support jumbo frames */
1971 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1972 /* Cannot do read-modify-write on 5401 */
1973 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1974 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1975 u32 phy_reg;
1976
1977 /* Set bit 14 with read-modify-write to preserve other bits */
1978 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1979 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1980 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1981 }
1982
1983 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1984 * jumbo frames transmission.
1985 */
8f666b07 1986 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1987 u32 phy_reg;
1988
1989 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1990 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1991 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1992 }
1993
715116a1 1994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1995 /* adjust output voltage */
535ef6e1 1996 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1997 }
1998
9ef8ca99 1999 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2000 tg3_phy_set_wirespeed(tp);
2001 return 0;
2002}
2003
2004static void tg3_frob_aux_power(struct tg3 *tp)
2005{
2006 struct tg3 *tp_peer = tp;
2007
9d26e213 2008 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2009 return;
2010
f6eb9b1f
MC		 2011 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2012 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2014 struct net_device *dev_peer;
2015
2016 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2017 /* remove_one() may have been run on the peer. */
8c2dc7e1 2018 if (!dev_peer)
bc1c7567
MC		 2019 tp_peer = tp;
2020 else
2021 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2022 }
2023
1da177e4 2024 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2025 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2026 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2027 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2030 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2031 (GRC_LCLCTRL_GPIO_OE0 |
2032 GRC_LCLCTRL_GPIO_OE1 |
2033 GRC_LCLCTRL_GPIO_OE2 |
2034 GRC_LCLCTRL_GPIO_OUTPUT0 |
2035 GRC_LCLCTRL_GPIO_OUTPUT1),
2036 100);
8d519ab2
MC		 2037 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2038 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2039 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2040 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2041 GRC_LCLCTRL_GPIO_OE1 |
2042 GRC_LCLCTRL_GPIO_OE2 |
2043 GRC_LCLCTRL_GPIO_OUTPUT0 |
2044 GRC_LCLCTRL_GPIO_OUTPUT1 |
2045 tp->grc_local_ctrl;
2046 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2047
2048 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2049 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2050
2051 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2052 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2053 } else {
2054 u32 no_gpio2;
dc56b7d4 2055 u32 grc_local_ctrl = 0;
1da177e4
LT		 2056
2057 if (tp_peer != tp &&
2058 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2059 return;
2060
dc56b7d4
MC		 2061 /* Workaround to prevent overdrawing Amps. */
2062 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2063 ASIC_REV_5714) {
2064 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2065 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2066 grc_local_ctrl, 100);
dc56b7d4
MC		 2067 }
2068
1da177e4
LT		 2069 /* On 5753 and variants, GPIO2 cannot be used. */
2070 no_gpio2 = tp->nic_sram_data_cfg &
2071 NIC_SRAM_DATA_CFG_NO_GPIO2;
2072
dc56b7d4 2073 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2074 GRC_LCLCTRL_GPIO_OE1 |
2075 GRC_LCLCTRL_GPIO_OE2 |
2076 GRC_LCLCTRL_GPIO_OUTPUT1 |
2077 GRC_LCLCTRL_GPIO_OUTPUT2;
2078 if (no_gpio2) {
2079 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2080 GRC_LCLCTRL_GPIO_OUTPUT2);
2081 }
b401e9e2
MC		 2082 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2083 grc_local_ctrl, 100);
1da177e4
LT		 2084
2085 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2086
b401e9e2
MC		 2087 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2088 grc_local_ctrl, 100);
1da177e4
LT		 2089
2090 if (!no_gpio2) {
2091 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2093 grc_local_ctrl, 100);
1da177e4
LT		 2094 }
2095 }
2096 } else {
2097 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2098 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2099 if (tp_peer != tp &&
2100 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2101 return;
2102
b401e9e2
MC		 2103 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104 (GRC_LCLCTRL_GPIO_OE1 |
2105 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2106
b401e9e2
MC		 2107 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2108 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2109
b401e9e2
MC		 2110 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2111 (GRC_LCLCTRL_GPIO_OE1 |
2112 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2113 }
2114 }
2115}
2116
e8f3f6ca
MC		 2117static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2118{
2119 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2120 return 1;
2121 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2122 if (speed != SPEED_10)
2123 return 1;
2124 } else if (speed == SPEED_10)
2125 return 1;
2126
2127 return 0;
2128}
2129
1da177e4
LT		 2130static int tg3_setup_phy(struct tg3 *, int);
2131
2132#define RESET_KIND_SHUTDOWN 0
2133#define RESET_KIND_INIT 1
2134#define RESET_KIND_SUSPEND 2
2135
2136static void tg3_write_sig_post_reset(struct tg3 *, int);
2137static int tg3_halt_cpu(struct tg3 *, u32);
2138
0a459aac 2139static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2140{
ce057f01
MC		 2141 u32 val;
2142
5129724a
MC		 2143 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2145 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2146 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2147
2148 sg_dig_ctrl |=
2149 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2150 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2151 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2152 }
3f7045c1 2153 return;
5129724a 2154 }
3f7045c1 2155
60189ddf 2156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2157 tg3_bmcr_reset(tp);
2158 val = tr32(GRC_MISC_CFG);
2159 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2160 udelay(40);
2161 return;
0e5f784c
MC		 2162 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2163 u32 phytest;
2164 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2165 u32 phy;
2166
2167 tg3_writephy(tp, MII_ADVERTISE, 0);
2168 tg3_writephy(tp, MII_BMCR,
2169 BMCR_ANENABLE | BMCR_ANRESTART);
2170
2171 tg3_writephy(tp, MII_TG3_FET_TEST,
2172 phytest | MII_TG3_FET_SHADOW_EN);
2173 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2174 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2175 tg3_writephy(tp,
2176 MII_TG3_FET_SHDW_AUXMODE4,
2177 phy);
2178 }
2179 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2180 }
2181 return;
0a459aac 2182 } else if (do_low_power) {
715116a1
MC		 2183 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2184 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2185
2186 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2187 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2188 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2189 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2190 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2191 }
3f7045c1 2192
15c3b696
MC		 2193 /* The PHY should not be powered down on some chips because
2194 * of bugs.
2195 */
2196 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2197 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2198 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2199 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2200 return;
ce057f01 2201
bcb37f6c
MC		 2202 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2203 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2204 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2205 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2206 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2207 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2208 }
2209
15c3b696
MC		 2210 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2211}
2212
ffbcfed4
MC		 2213/* tp->lock is held. */
2214static int tg3_nvram_lock(struct tg3 *tp)
2215{
2216 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2217 int i;
2218
2219 if (tp->nvram_lock_cnt == 0) {
2220 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2221 for (i = 0; i < 8000; i++) {
2222 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2223 break;
2224 udelay(20);
2225 }
2226 if (i == 8000) {
2227 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2228 return -ENODEV;
2229 }
2230 }
2231 tp->nvram_lock_cnt++;
2232 }
2233 return 0;
2234}
2235
2236/* tp->lock is held. */
2237static void tg3_nvram_unlock(struct tg3 *tp)
2238{
2239 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2240 if (tp->nvram_lock_cnt > 0)
2241 tp->nvram_lock_cnt--;
2242 if (tp->nvram_lock_cnt == 0)
2243 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2244 }
2245}
2246
2247/* tp->lock is held. */
2248static void tg3_enable_nvram_access(struct tg3 *tp)
2249{
2250 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2251 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2252 u32 nvaccess = tr32(NVRAM_ACCESS);
2253
2254 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2255 }
2256}
2257
2258/* tp->lock is held. */
2259static void tg3_disable_nvram_access(struct tg3 *tp)
2260{
2261 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2262 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2263 u32 nvaccess = tr32(NVRAM_ACCESS);
2264
2265 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2266 }
2267}
2268
2269static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2270 u32 offset, u32 *val)
2271{
2272 u32 tmp;
2273 int i;
2274
2275 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2276 return -EINVAL;
2277
2278 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2279 EEPROM_ADDR_DEVID_MASK |
2280 EEPROM_ADDR_READ);
2281 tw32(GRC_EEPROM_ADDR,
2282 tmp |
2283 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2284 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2285 EEPROM_ADDR_ADDR_MASK) |
2286 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2287
2288 for (i = 0; i < 1000; i++) {
2289 tmp = tr32(GRC_EEPROM_ADDR);
2290
2291 if (tmp & EEPROM_ADDR_COMPLETE)
2292 break;
2293 msleep(1);
2294 }
2295 if (!(tmp & EEPROM_ADDR_COMPLETE))
2296 return -EBUSY;
2297
62cedd11
MC		 2298 tmp = tr32(GRC_EEPROM_DATA);
2299
2300 /*
2301 * The data will always be opposite the native endian
2302 * format. Perform a blind byteswap to compensate.
2303 */
2304 *val = swab32(tmp);
2305
ffbcfed4
MC		 2306 return 0;
2307}
2308
2309#define NVRAM_CMD_TIMEOUT 10000
2310
2311static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2312{
2313 int i;
2314
2315 tw32(NVRAM_CMD, nvram_cmd);
2316 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2317 udelay(10);
2318 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2319 udelay(10);
2320 break;
2321 }
2322 }
2323
2324 if (i == NVRAM_CMD_TIMEOUT)
2325 return -EBUSY;
2326
2327 return 0;
2328}
2329
2330static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2331{
2332 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2333 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2334 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2335 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2336 (tp->nvram_jedecnum == JEDEC_ATMEL))
2337
2338 addr = ((addr / tp->nvram_pagesize) <<
2339 ATMEL_AT45DB0X1B_PAGE_POS) +
2340 (addr % tp->nvram_pagesize);
2341
2342 return addr;
2343}
2344
2345static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2346{
2347 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2348 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2349 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2350 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2351 (tp->nvram_jedecnum == JEDEC_ATMEL))
2352
2353 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2354 tp->nvram_pagesize) +
2355 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2356
2357 return addr;
2358}
2359
e4f34110
MC		 2360/* NOTE: Data read in from NVRAM is byteswapped according to
2361 * the byteswapping settings for all other register accesses.
2362 * tg3 devices are BE devices, so on a BE machine, the data
2363 * returned will be exactly as it is seen in NVRAM. On a LE
2364 * machine, the 32-bit value will be byteswapped.
2365 */
ffbcfed4
MC		 2366static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2367{
2368 int ret;
2369
2370 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2371 return tg3_nvram_read_using_eeprom(tp, offset, val);
2372
2373 offset = tg3_nvram_phys_addr(tp, offset);
2374
2375 if (offset > NVRAM_ADDR_MSK)
2376 return -EINVAL;
2377
2378 ret = tg3_nvram_lock(tp);
2379 if (ret)
2380 return ret;
2381
2382 tg3_enable_nvram_access(tp);
2383
2384 tw32(NVRAM_ADDR, offset);
2385 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2386 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2387
2388 if (ret == 0)
e4f34110 2389 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2390
2391 tg3_disable_nvram_access(tp);
2392
2393 tg3_nvram_unlock(tp);
2394
2395 return ret;
2396}
2397
a9dc529d
MC		 2398/* Ensures NVRAM data is in bytestream format. */
2399static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2400{
2401 u32 v;
a9dc529d 2402 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2403 if (!res)
a9dc529d 2404 *val = cpu_to_be32(v);
ffbcfed4
MC		 2405 return res;
2406}
2407
3f007891
MC		 2408/* tp->lock is held. */
2409static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2410{
2411 u32 addr_high, addr_low;
2412 int i;
2413
2414 addr_high = ((tp->dev->dev_addr[0] << 8) |
2415 tp->dev->dev_addr[1]);
2416 addr_low = ((tp->dev->dev_addr[2] << 24) |
2417 (tp->dev->dev_addr[3] << 16) |
2418 (tp->dev->dev_addr[4] << 8) |
2419 (tp->dev->dev_addr[5] << 0));
2420 for (i = 0; i < 4; i++) {
2421 if (i == 1 && skip_mac_1)
2422 continue;
2423 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2424 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2425 }
2426
2427 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2428 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2429 for (i = 0; i < 12; i++) {
2430 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2431 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2432 }
2433 }
2434
2435 addr_high = (tp->dev->dev_addr[0] +
2436 tp->dev->dev_addr[1] +
2437 tp->dev->dev_addr[2] +
2438 tp->dev->dev_addr[3] +
2439 tp->dev->dev_addr[4] +
2440 tp->dev->dev_addr[5]) &
2441 TX_BACKOFF_SEED_MASK;
2442 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2443}
2444
bc1c7567 2445static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2446{
2447 u32 misc_host_ctrl;
0a459aac 2448 bool device_should_wake, do_low_power;
1da177e4
LT		 2449
2450 /* Make sure register accesses (indirect or otherwise)
2451 * will function correctly.
2452 */
2453 pci_write_config_dword(tp->pdev,
2454 TG3PCI_MISC_HOST_CTRL,
2455 tp->misc_host_ctrl);
2456
1da177e4 2457 switch (state) {
bc1c7567 2458 case PCI_D0:
12dac075
RW		 2459 pci_enable_wake(tp->pdev, state, false);
2460 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2461
9d26e213
MC		 2462 /* Switch out of Vaux if it is a NIC */
2463 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2464 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2465
2466 return 0;
2467
bc1c7567 2468 case PCI_D1:
bc1c7567 2469 case PCI_D2:
bc1c7567 2470 case PCI_D3hot:
1da177e4
LT		 2471 break;
2472
2473 default:
12dac075
RW		 2474 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2475 tp->dev->name, state);
1da177e4 2476 return -EINVAL;
855e1111 2477 }
5e7dfd0f
MC		 2478
2479 /* Restore the CLKREQ setting. */
2480 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2481 u16 lnkctl;
2482
2483 pci_read_config_word(tp->pdev,
2484 tp->pcie_cap + PCI_EXP_LNKCTL,
2485 &lnkctl);
2486 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2487 pci_write_config_word(tp->pdev,
2488 tp->pcie_cap + PCI_EXP_LNKCTL,
2489 lnkctl);
2490 }
2491
1da177e4
LT		 2492 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2493 tw32(TG3PCI_MISC_HOST_CTRL,
2494 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2495
05ac4cb7
MC		 2496 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2497 device_may_wakeup(&tp->pdev->dev) &&
2498 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2499
dd477003 2500 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2501 do_low_power = false;
b02fd9e3
MC		 2502 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2503 !tp->link_config.phy_is_low_power) {
2504 struct phy_device *phydev;
0a459aac 2505 u32 phyid, advertising;
b02fd9e3 2506
3f0e3ad7 2507 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2508
2509 tp->link_config.phy_is_low_power = 1;
2510
2511 tp->link_config.orig_speed = phydev->speed;
2512 tp->link_config.orig_duplex = phydev->duplex;
2513 tp->link_config.orig_autoneg = phydev->autoneg;
2514 tp->link_config.orig_advertising = phydev->advertising;
2515
2516 advertising = ADVERTISED_TP |
2517 ADVERTISED_Pause |
2518 ADVERTISED_Autoneg |
2519 ADVERTISED_10baseT_Half;
2520
2521 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2522 device_should_wake) {
b02fd9e3
MC		 2523 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2524 advertising |=
2525 ADVERTISED_100baseT_Half |
2526 ADVERTISED_100baseT_Full |
2527 ADVERTISED_10baseT_Full;
2528 else
2529 advertising |= ADVERTISED_10baseT_Full;
2530 }
2531
2532 phydev->advertising = advertising;
2533
2534 phy_start_aneg(phydev);
0a459aac
MC		 2535
2536 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2537 if (phyid != TG3_PHY_ID_BCMAC131) {
2538 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2539 if (phyid == TG3_PHY_OUI_1 ||
2540 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2541 phyid == TG3_PHY_OUI_3)
2542 do_low_power = true;
2543 }
b02fd9e3 2544 }
dd477003 2545 } else {
2023276e 2546 do_low_power = true;
0a459aac 2547
dd477003
MC		 2548 if (tp->link_config.phy_is_low_power == 0) {
2549 tp->link_config.phy_is_low_power = 1;
2550 tp->link_config.orig_speed = tp->link_config.speed;
2551 tp->link_config.orig_duplex = tp->link_config.duplex;
2552 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2553 }
1da177e4 2554
dd477003
MC		 2555 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2556 tp->link_config.speed = SPEED_10;
2557 tp->link_config.duplex = DUPLEX_HALF;
2558 tp->link_config.autoneg = AUTONEG_ENABLE;
2559 tg3_setup_phy(tp, 0);
2560 }
1da177e4
LT		 2561 }
2562
b5d3772c
MC		 2563 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2564 u32 val;
2565
2566 val = tr32(GRC_VCPU_EXT_CTRL);
2567 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2568 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2569 int i;
2570 u32 val;
2571
2572 for (i = 0; i < 200; i++) {
2573 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2574 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2575 break;
2576 msleep(1);
2577 }
2578 }
a85feb8c
GZ		 2579 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2580 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2581 WOL_DRV_STATE_SHUTDOWN |
2582 WOL_DRV_WOL |
2583 WOL_SET_MAGIC_PKT);
6921d201 2584
05ac4cb7 2585 if (device_should_wake) {
1da177e4
LT		 2586 u32 mac_mode;
2587
2588 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2589 if (do_low_power) {
dd477003
MC		 2590 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2591 udelay(40);
2592 }
1da177e4 2593
3f7045c1
MC		 2594 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2595 mac_mode = MAC_MODE_PORT_MODE_GMII;
2596 else
2597 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2598
e8f3f6ca
MC		 2599 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2600 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2601 ASIC_REV_5700) {
2602 u32 speed = (tp->tg3_flags &
2603 TG3_FLAG_WOL_SPEED_100MB) ?
2604 SPEED_100 : SPEED_10;
2605 if (tg3_5700_link_polarity(tp, speed))
2606 mac_mode |= MAC_MODE_LINK_POLARITY;
2607 else
2608 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2609 }
1da177e4
LT		 2610 } else {
2611 mac_mode = MAC_MODE_PORT_MODE_TBI;
2612 }
2613
cbf46853 2614 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2615 tw32(MAC_LED_CTRL, tp->led_ctrl);
2616
05ac4cb7
MC		 2617 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2618 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2619 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2620 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2621 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2622 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2623
3bda1258
MC		 2624 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2625 mac_mode |= tp->mac_mode &
2626 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2627 if (mac_mode & MAC_MODE_APE_TX_EN)
2628 mac_mode |= MAC_MODE_TDE_ENABLE;
2629 }
2630
1da177e4
LT		 2631 tw32_f(MAC_MODE, mac_mode);
2632 udelay(100);
2633
2634 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2635 udelay(10);
2636 }
2637
2638 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2639 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2641 u32 base_val;
2642
2643 base_val = tp->pci_clock_ctrl;
2644 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2645 CLOCK_CTRL_TXCLK_DISABLE);
2646
b401e9e2
MC		 2647 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2648 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2649 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2650 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2651 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2652 /* do nothing */
85e94ced 2653 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2654 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2655 u32 newbits1, newbits2;
2656
2657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2658 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2659 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2660 CLOCK_CTRL_TXCLK_DISABLE |
2661 CLOCK_CTRL_ALTCLK);
2662 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2663 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2664 newbits1 = CLOCK_CTRL_625_CORE;
2665 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2666 } else {
2667 newbits1 = CLOCK_CTRL_ALTCLK;
2668 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2669 }
2670
b401e9e2
MC		 2671 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2672 40);
1da177e4 2673
b401e9e2
MC		 2674 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2675 40);
1da177e4
LT		 2676
2677 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2678 u32 newbits3;
2679
2680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2682 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2683 CLOCK_CTRL_TXCLK_DISABLE |
2684 CLOCK_CTRL_44MHZ_CORE);
2685 } else {
2686 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2687 }
2688
b401e9e2
MC		 2689 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2690 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2691 }
2692 }
2693
05ac4cb7 2694 if (!(device_should_wake) &&
22435849 2695 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2696 tg3_power_down_phy(tp, do_low_power);
6921d201 2697
1da177e4
LT		 2698 tg3_frob_aux_power(tp);
2699
2700 /* Workaround for unstable PLL clock */
2701 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2702 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2703 u32 val = tr32(0x7d00);
2704
2705 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2706 tw32(0x7d00, val);
6921d201 2707 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2708 int err;
2709
2710 err = tg3_nvram_lock(tp);
1da177e4 2711 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2712 if (!err)
2713 tg3_nvram_unlock(tp);
6921d201 2714 }
1da177e4
LT		 2715 }
2716
bbadf503
MC		 2717 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2718
05ac4cb7 2719 if (device_should_wake)
12dac075
RW		 2720 pci_enable_wake(tp->pdev, state, true);
2721
1da177e4 2722 /* Finally, set the new power state. */
12dac075 2723 pci_set_power_state(tp->pdev, state);
1da177e4 2724
1da177e4
LT		 2725 return 0;
2726}
2727
1da177e4
LT		 2728static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2729{
2730 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2731 case MII_TG3_AUX_STAT_10HALF:
2732 *speed = SPEED_10;
2733 *duplex = DUPLEX_HALF;
2734 break;
2735
2736 case MII_TG3_AUX_STAT_10FULL:
2737 *speed = SPEED_10;
2738 *duplex = DUPLEX_FULL;
2739 break;
2740
2741 case MII_TG3_AUX_STAT_100HALF:
2742 *speed = SPEED_100;
2743 *duplex = DUPLEX_HALF;
2744 break;
2745
2746 case MII_TG3_AUX_STAT_100FULL:
2747 *speed = SPEED_100;
2748 *duplex = DUPLEX_FULL;
2749 break;
2750
2751 case MII_TG3_AUX_STAT_1000HALF:
2752 *speed = SPEED_1000;
2753 *duplex = DUPLEX_HALF;
2754 break;
2755
2756 case MII_TG3_AUX_STAT_1000FULL:
2757 *speed = SPEED_1000;
2758 *duplex = DUPLEX_FULL;
2759 break;
2760
2761 default:
7f97a4bd 2762 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2763 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2764 SPEED_10;
2765 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2766 DUPLEX_HALF;
2767 break;
2768 }
1da177e4
LT		 2769 *speed = SPEED_INVALID;
2770 *duplex = DUPLEX_INVALID;
2771 break;
855e1111 2772 }
1da177e4
LT		 2773}
2774
2775static void tg3_phy_copper_begin(struct tg3 *tp)
2776{
2777 u32 new_adv;
2778 int i;
2779
2780 if (tp->link_config.phy_is_low_power) {
2781 /* Entering low power mode. Disable gigabit and
2782 * 100baseT advertisements.
2783 */
2784 tg3_writephy(tp, MII_TG3_CTRL, 0);
2785
2786 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2787 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2788 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2789 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2790
2791 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2792 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2793 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2794 tp->link_config.advertising &=
2795 ~(ADVERTISED_1000baseT_Half |
2796 ADVERTISED_1000baseT_Full);
2797
ba4d07a8 2798 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2799 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2800 new_adv |= ADVERTISE_10HALF;
2801 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2802 new_adv |= ADVERTISE_10FULL;
2803 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2804 new_adv |= ADVERTISE_100HALF;
2805 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2806 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2807
2808 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2809
1da177e4
LT		 2810 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2811
2812 if (tp->link_config.advertising &
2813 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2814 new_adv = 0;
2815 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2816 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2817 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2818 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2819 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2820 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2821 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2822 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2823 MII_TG3_CTRL_ENABLE_AS_MASTER);
2824 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2825 } else {
2826 tg3_writephy(tp, MII_TG3_CTRL, 0);
2827 }
2828 } else {
ba4d07a8
MC		 2829 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2830 new_adv |= ADVERTISE_CSMA;
2831
1da177e4
LT		 2832 /* Asking for a specific link mode. */
2833 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2834 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2835
2836 if (tp->link_config.duplex == DUPLEX_FULL)
2837 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2838 else
2839 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2840 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2841 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2842 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2843 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2844 } else {
1da177e4
LT		 2845 if (tp->link_config.speed == SPEED_100) {
2846 if (tp->link_config.duplex == DUPLEX_FULL)
2847 new_adv |= ADVERTISE_100FULL;
2848 else
2849 new_adv |= ADVERTISE_100HALF;
2850 } else {
2851 if (tp->link_config.duplex == DUPLEX_FULL)
2852 new_adv |= ADVERTISE_10FULL;
2853 else
2854 new_adv |= ADVERTISE_10HALF;
2855 }
2856 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2857
2858 new_adv = 0;
1da177e4 2859 }
ba4d07a8
MC		 2860
2861 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2862 }
2863
2864 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2865 tp->link_config.speed != SPEED_INVALID) {
2866 u32 bmcr, orig_bmcr;
2867
2868 tp->link_config.active_speed = tp->link_config.speed;
2869 tp->link_config.active_duplex = tp->link_config.duplex;
2870
2871 bmcr = 0;
2872 switch (tp->link_config.speed) {
2873 default:
2874 case SPEED_10:
2875 break;
2876
2877 case SPEED_100:
2878 bmcr |= BMCR_SPEED100;
2879 break;
2880
2881 case SPEED_1000:
2882 bmcr |= TG3_BMCR_SPEED1000;
2883 break;
855e1111 2884 }
1da177e4
LT		 2885
2886 if (tp->link_config.duplex == DUPLEX_FULL)
2887 bmcr |= BMCR_FULLDPLX;
2888
2889 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2890 (bmcr != orig_bmcr)) {
2891 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2892 for (i = 0; i < 1500; i++) {
2893 u32 tmp;
2894
2895 udelay(10);
2896 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2897 tg3_readphy(tp, MII_BMSR, &tmp))
2898 continue;
2899 if (!(tmp & BMSR_LSTATUS)) {
2900 udelay(40);
2901 break;
2902 }
2903 }
2904 tg3_writephy(tp, MII_BMCR, bmcr);
2905 udelay(40);
2906 }
2907 } else {
2908 tg3_writephy(tp, MII_BMCR,
2909 BMCR_ANENABLE | BMCR_ANRESTART);
2910 }
2911}
2912
2913static int tg3_init_5401phy_dsp(struct tg3 *tp)
2914{
2915 int err;
2916
2917 /* Turn off tap power management. */
2918 /* Set Extended packet length bit */
2919 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2920
2921 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2922 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2923
2924 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2925 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2926
2927 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2928 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2929
2930 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2931 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2932
2933 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2934 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2935
2936 udelay(40);
2937
2938 return err;
2939}
2940
3600d918 2941static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2942{
3600d918
MC		 2943 u32 adv_reg, all_mask = 0;
2944
2945 if (mask & ADVERTISED_10baseT_Half)
2946 all_mask |= ADVERTISE_10HALF;
2947 if (mask & ADVERTISED_10baseT_Full)
2948 all_mask |= ADVERTISE_10FULL;
2949 if (mask & ADVERTISED_100baseT_Half)
2950 all_mask |= ADVERTISE_100HALF;
2951 if (mask & ADVERTISED_100baseT_Full)
2952 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2953
2954 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2955 return 0;
2956
1da177e4
LT		 2957 if ((adv_reg & all_mask) != all_mask)
2958 return 0;
2959 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2960 u32 tg3_ctrl;
2961
3600d918
MC		 2962 all_mask = 0;
2963 if (mask & ADVERTISED_1000baseT_Half)
2964 all_mask |= ADVERTISE_1000HALF;
2965 if (mask & ADVERTISED_1000baseT_Full)
2966 all_mask |= ADVERTISE_1000FULL;
2967
1da177e4
LT		 2968 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2969 return 0;
2970
1da177e4
LT		 2971 if ((tg3_ctrl & all_mask) != all_mask)
2972 return 0;
2973 }
2974 return 1;
2975}
2976
ef167e27
MC		 2977static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2978{
2979 u32 curadv, reqadv;
2980
2981 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2982 return 1;
2983
2984 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2985 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2986
2987 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2988 if (curadv != reqadv)
2989 return 0;
2990
2991 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2992 tg3_readphy(tp, MII_LPA, rmtadv);
2993 } else {
2994 /* Reprogram the advertisement register, even if it
2995 * does not affect the current link. If the link
2996 * gets renegotiated in the future, we can save an
2997 * additional renegotiation cycle by advertising
2998 * it correctly in the first place.
2999 */
3000 if (curadv != reqadv) {
3001 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3002 ADVERTISE_PAUSE_ASYM);
3003 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3004 }
3005 }
3006
3007 return 1;
3008}
3009
1da177e4
LT		 3010static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3011{
3012 int current_link_up;
3013 u32 bmsr, dummy;
ef167e27 3014 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3015 u16 current_speed;
3016 u8 current_duplex;
3017 int i, err;
3018
3019 tw32(MAC_EVENT, 0);
3020
3021 tw32_f(MAC_STATUS,
3022 (MAC_STATUS_SYNC_CHANGED |
3023 MAC_STATUS_CFG_CHANGED |
3024 MAC_STATUS_MI_COMPLETION |
3025 MAC_STATUS_LNKSTATE_CHANGED));
3026 udelay(40);
3027
8ef21428
MC		 3028 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3029 tw32_f(MAC_MI_MODE,
3030 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3031 udelay(80);
3032 }
1da177e4
LT		 3033
3034 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3035
3036 /* Some third-party PHYs need to be reset on link going
3037 * down.
3038 */
3039 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3040 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3042 netif_carrier_ok(tp->dev)) {
3043 tg3_readphy(tp, MII_BMSR, &bmsr);
3044 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3045 !(bmsr & BMSR_LSTATUS))
3046 force_reset = 1;
3047 }
3048 if (force_reset)
3049 tg3_phy_reset(tp);
3050
3051 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3052 tg3_readphy(tp, MII_BMSR, &bmsr);
3053 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3054 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3055 bmsr = 0;
3056
3057 if (!(bmsr & BMSR_LSTATUS)) {
3058 err = tg3_init_5401phy_dsp(tp);
3059 if (err)
3060 return err;
3061
3062 tg3_readphy(tp, MII_BMSR, &bmsr);
3063 for (i = 0; i < 1000; i++) {
3064 udelay(10);
3065 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3066 (bmsr & BMSR_LSTATUS)) {
3067 udelay(40);
3068 break;
3069 }
3070 }
3071
3072 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3073 !(bmsr & BMSR_LSTATUS) &&
3074 tp->link_config.active_speed == SPEED_1000) {
3075 err = tg3_phy_reset(tp);
3076 if (!err)
3077 err = tg3_init_5401phy_dsp(tp);
3078 if (err)
3079 return err;
3080 }
3081 }
3082 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3083 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3084 /* 5701 {A0,B0} CRC bug workaround */
3085 tg3_writephy(tp, 0x15, 0x0a75);
3086 tg3_writephy(tp, 0x1c, 0x8c68);
3087 tg3_writephy(tp, 0x1c, 0x8d68);
3088 tg3_writephy(tp, 0x1c, 0x8c68);
3089 }
3090
3091 /* Clear pending interrupts... */
3092 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3093 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3094
3095 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3096 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3097 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3098 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3099
3100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3102 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3103 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3104 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3105 else
3106 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3107 }
3108
3109 current_link_up = 0;
3110 current_speed = SPEED_INVALID;
3111 current_duplex = DUPLEX_INVALID;
3112
3113 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3114 u32 val;
3115
3116 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3117 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3118 if (!(val & (1 << 10))) {
3119 val |= (1 << 10);
3120 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3121 goto relink;
3122 }
3123 }
3124
3125 bmsr = 0;
3126 for (i = 0; i < 100; i++) {
3127 tg3_readphy(tp, MII_BMSR, &bmsr);
3128 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3129 (bmsr & BMSR_LSTATUS))
3130 break;
3131 udelay(40);
3132 }
3133
3134 if (bmsr & BMSR_LSTATUS) {
3135 u32 aux_stat, bmcr;
3136
3137 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3138 for (i = 0; i < 2000; i++) {
3139 udelay(10);
3140 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3141 aux_stat)
3142 break;
3143 }
3144
3145 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3146 &current_speed,
3147 &current_duplex);
3148
3149 bmcr = 0;
3150 for (i = 0; i < 200; i++) {
3151 tg3_readphy(tp, MII_BMCR, &bmcr);
3152 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3153 continue;
3154 if (bmcr && bmcr != 0x7fff)
3155 break;
3156 udelay(10);
3157 }
3158
ef167e27
MC		 3159 lcl_adv = 0;
3160 rmt_adv = 0;
1da177e4 3161
ef167e27
MC		 3162 tp->link_config.active_speed = current_speed;
3163 tp->link_config.active_duplex = current_duplex;
3164
3165 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3166 if ((bmcr & BMCR_ANENABLE) &&
3167 tg3_copper_is_advertising_all(tp,
3168 tp->link_config.advertising)) {
3169 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3170 &rmt_adv))
3171 current_link_up = 1;
1da177e4
LT		 3172 }
3173 } else {
3174 if (!(bmcr & BMCR_ANENABLE) &&
3175 tp->link_config.speed == current_speed &&
ef167e27
MC		 3176 tp->link_config.duplex == current_duplex &&
3177 tp->link_config.flowctrl ==
3178 tp->link_config.active_flowctrl) {
1da177e4 3179 current_link_up = 1;
1da177e4
LT		 3180 }
3181 }
3182
ef167e27
MC		 3183 if (current_link_up == 1 &&
3184 tp->link_config.active_duplex == DUPLEX_FULL)
3185 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3186 }
3187
1da177e4 3188relink:
6921d201 3189 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3190 u32 tmp;
3191
3192 tg3_phy_copper_begin(tp);
3193
3194 tg3_readphy(tp, MII_BMSR, &tmp);
3195 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3196 (tmp & BMSR_LSTATUS))
3197 current_link_up = 1;
3198 }
3199
3200 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3201 if (current_link_up == 1) {
3202 if (tp->link_config.active_speed == SPEED_100 ||
3203 tp->link_config.active_speed == SPEED_10)
3204 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3205 else
3206 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3207 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3208 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3209 else
1da177e4
LT		 3210 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3211
3212 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3213 if (tp->link_config.active_duplex == DUPLEX_HALF)
3214 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3215
1da177e4 3216 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3217 if (current_link_up == 1 &&
3218 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3219 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3220 else
3221 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3222 }
3223
3224 /* ??? Without this setting Netgear GA302T PHY does not
3225 * ??? send/receive packets...
3226 */
3227 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3228 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3229 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3230 tw32_f(MAC_MI_MODE, tp->mi_mode);
3231 udelay(80);
3232 }
3233
3234 tw32_f(MAC_MODE, tp->mac_mode);
3235 udelay(40);
3236
3237 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3238 /* Polled via timer. */
3239 tw32_f(MAC_EVENT, 0);
3240 } else {
3241 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3242 }
3243 udelay(40);
3244
3245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3246 current_link_up == 1 &&
3247 tp->link_config.active_speed == SPEED_1000 &&
3248 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3249 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3250 udelay(120);
3251 tw32_f(MAC_STATUS,
3252 (MAC_STATUS_SYNC_CHANGED |
3253 MAC_STATUS_CFG_CHANGED));
3254 udelay(40);
3255 tg3_write_mem(tp,
3256 NIC_SRAM_FIRMWARE_MBOX,
3257 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3258 }
3259
5e7dfd0f
MC		 3260 /* Prevent send BD corruption. */
3261 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3262 u16 oldlnkctl, newlnkctl;
3263
3264 pci_read_config_word(tp->pdev,
3265 tp->pcie_cap + PCI_EXP_LNKCTL,
3266 &oldlnkctl);
3267 if (tp->link_config.active_speed == SPEED_100 ||
3268 tp->link_config.active_speed == SPEED_10)
3269 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3270 else
3271 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3272 if (newlnkctl != oldlnkctl)
3273 pci_write_config_word(tp->pdev,
3274 tp->pcie_cap + PCI_EXP_LNKCTL,
3275 newlnkctl);
3276 }
3277
1da177e4
LT		 3278 if (current_link_up != netif_carrier_ok(tp->dev)) {
3279 if (current_link_up)
3280 netif_carrier_on(tp->dev);
3281 else
3282 netif_carrier_off(tp->dev);
3283 tg3_link_report(tp);
3284 }
3285
3286 return 0;
3287}
3288
3289struct tg3_fiber_aneginfo {
3290 int state;
3291#define ANEG_STATE_UNKNOWN 0
3292#define ANEG_STATE_AN_ENABLE 1
3293#define ANEG_STATE_RESTART_INIT 2
3294#define ANEG_STATE_RESTART 3
3295#define ANEG_STATE_DISABLE_LINK_OK 4
3296#define ANEG_STATE_ABILITY_DETECT_INIT 5
3297#define ANEG_STATE_ABILITY_DETECT 6
3298#define ANEG_STATE_ACK_DETECT_INIT 7
3299#define ANEG_STATE_ACK_DETECT 8
3300#define ANEG_STATE_COMPLETE_ACK_INIT 9
3301#define ANEG_STATE_COMPLETE_ACK 10
3302#define ANEG_STATE_IDLE_DETECT_INIT 11
3303#define ANEG_STATE_IDLE_DETECT 12
3304#define ANEG_STATE_LINK_OK 13
3305#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3306#define ANEG_STATE_NEXT_PAGE_WAIT 15
3307
3308 u32 flags;
3309#define MR_AN_ENABLE 0x00000001
3310#define MR_RESTART_AN 0x00000002
3311#define MR_AN_COMPLETE 0x00000004
3312#define MR_PAGE_RX 0x00000008
3313#define MR_NP_LOADED 0x00000010
3314#define MR_TOGGLE_TX 0x00000020
3315#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3316#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3317#define MR_LP_ADV_SYM_PAUSE 0x00000100
3318#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3319#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3320#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3321#define MR_LP_ADV_NEXT_PAGE 0x00001000
3322#define MR_TOGGLE_RX 0x00002000
3323#define MR_NP_RX 0x00004000
3324
3325#define MR_LINK_OK 0x80000000
3326
3327 unsigned long link_time, cur_time;
3328
3329 u32 ability_match_cfg;
3330 int ability_match_count;
3331
3332 char ability_match, idle_match, ack_match;
3333
3334 u32 txconfig, rxconfig;
3335#define ANEG_CFG_NP 0x00000080
3336#define ANEG_CFG_ACK 0x00000040
3337#define ANEG_CFG_RF2 0x00000020
3338#define ANEG_CFG_RF1 0x00000010
3339#define ANEG_CFG_PS2 0x00000001
3340#define ANEG_CFG_PS1 0x00008000
3341#define ANEG_CFG_HD 0x00004000
3342#define ANEG_CFG_FD 0x00002000
3343#define ANEG_CFG_INVAL 0x00001f06
3344
3345};
3346#define ANEG_OK 0
3347#define ANEG_DONE 1
3348#define ANEG_TIMER_ENAB 2
3349#define ANEG_FAILED -1
3350
3351#define ANEG_STATE_SETTLE_TIME 10000
3352
3353static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3354 struct tg3_fiber_aneginfo *ap)
3355{
5be73b47 3356 u16 flowctrl;
1da177e4
LT		 3357 unsigned long delta;
3358 u32 rx_cfg_reg;
3359 int ret;
3360
3361 if (ap->state == ANEG_STATE_UNKNOWN) {
3362 ap->rxconfig = 0;
3363 ap->link_time = 0;
3364 ap->cur_time = 0;
3365 ap->ability_match_cfg = 0;
3366 ap->ability_match_count = 0;
3367 ap->ability_match = 0;
3368 ap->idle_match = 0;
3369 ap->ack_match = 0;
3370 }
3371 ap->cur_time++;
3372
3373 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3374 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3375
3376 if (rx_cfg_reg != ap->ability_match_cfg) {
3377 ap->ability_match_cfg = rx_cfg_reg;
3378 ap->ability_match = 0;
3379 ap->ability_match_count = 0;
3380 } else {
3381 if (++ap->ability_match_count > 1) {
3382 ap->ability_match = 1;
3383 ap->ability_match_cfg = rx_cfg_reg;
3384 }
3385 }
3386 if (rx_cfg_reg & ANEG_CFG_ACK)
3387 ap->ack_match = 1;
3388 else
3389 ap->ack_match = 0;
3390
3391 ap->idle_match = 0;
3392 } else {
3393 ap->idle_match = 1;
3394 ap->ability_match_cfg = 0;
3395 ap->ability_match_count = 0;
3396 ap->ability_match = 0;
3397 ap->ack_match = 0;
3398
3399 rx_cfg_reg = 0;
3400 }
3401
3402 ap->rxconfig = rx_cfg_reg;
3403 ret = ANEG_OK;
3404
3405 switch(ap->state) {
3406 case ANEG_STATE_UNKNOWN:
3407 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3408 ap->state = ANEG_STATE_AN_ENABLE;
3409
3410 /* fallthru */
3411 case ANEG_STATE_AN_ENABLE:
3412 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3413 if (ap->flags & MR_AN_ENABLE) {
3414 ap->link_time = 0;
3415 ap->cur_time = 0;
3416 ap->ability_match_cfg = 0;
3417 ap->ability_match_count = 0;
3418 ap->ability_match = 0;
3419 ap->idle_match = 0;
3420 ap->ack_match = 0;
3421
3422 ap->state = ANEG_STATE_RESTART_INIT;
3423 } else {
3424 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3425 }
3426 break;
3427
3428 case ANEG_STATE_RESTART_INIT:
3429 ap->link_time = ap->cur_time;
3430 ap->flags &= ~(MR_NP_LOADED);
3431 ap->txconfig = 0;
3432 tw32(MAC_TX_AUTO_NEG, 0);
3433 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3434 tw32_f(MAC_MODE, tp->mac_mode);
3435 udelay(40);
3436
3437 ret = ANEG_TIMER_ENAB;
3438 ap->state = ANEG_STATE_RESTART;
3439
3440 /* fallthru */
3441 case ANEG_STATE_RESTART:
3442 delta = ap->cur_time - ap->link_time;
3443 if (delta > ANEG_STATE_SETTLE_TIME) {
3444 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3445 } else {
3446 ret = ANEG_TIMER_ENAB;
3447 }
3448 break;
3449
3450 case ANEG_STATE_DISABLE_LINK_OK:
3451 ret = ANEG_DONE;
3452 break;
3453
3454 case ANEG_STATE_ABILITY_DETECT_INIT:
3455 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3456 ap->txconfig = ANEG_CFG_FD;
3457 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3458 if (flowctrl & ADVERTISE_1000XPAUSE)
3459 ap->txconfig |= ANEG_CFG_PS1;
3460 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3461 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3462 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3463 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3464 tw32_f(MAC_MODE, tp->mac_mode);
3465 udelay(40);
3466
3467 ap->state = ANEG_STATE_ABILITY_DETECT;
3468 break;
3469
3470 case ANEG_STATE_ABILITY_DETECT:
3471 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3472 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3473 }
3474 break;
3475
3476 case ANEG_STATE_ACK_DETECT_INIT:
3477 ap->txconfig |= ANEG_CFG_ACK;
3478 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3479 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3480 tw32_f(MAC_MODE, tp->mac_mode);
3481 udelay(40);
3482
3483 ap->state = ANEG_STATE_ACK_DETECT;
3484
3485 /* fallthru */
3486 case ANEG_STATE_ACK_DETECT:
3487 if (ap->ack_match != 0) {
3488 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3489 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3490 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3491 } else {
3492 ap->state = ANEG_STATE_AN_ENABLE;
3493 }
3494 } else if (ap->ability_match != 0 &&
3495 ap->rxconfig == 0) {
3496 ap->state = ANEG_STATE_AN_ENABLE;
3497 }
3498 break;
3499
3500 case ANEG_STATE_COMPLETE_ACK_INIT:
3501 if (ap->rxconfig & ANEG_CFG_INVAL) {
3502 ret = ANEG_FAILED;
3503 break;
3504 }
3505 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3506 MR_LP_ADV_HALF_DUPLEX |
3507 MR_LP_ADV_SYM_PAUSE |
3508 MR_LP_ADV_ASYM_PAUSE |
3509 MR_LP_ADV_REMOTE_FAULT1 |
3510 MR_LP_ADV_REMOTE_FAULT2 |
3511 MR_LP_ADV_NEXT_PAGE |
3512 MR_TOGGLE_RX |
3513 MR_NP_RX);
3514 if (ap->rxconfig & ANEG_CFG_FD)
3515 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3516 if (ap->rxconfig & ANEG_CFG_HD)
3517 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3518 if (ap->rxconfig & ANEG_CFG_PS1)
3519 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3520 if (ap->rxconfig & ANEG_CFG_PS2)
3521 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3522 if (ap->rxconfig & ANEG_CFG_RF1)
3523 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3524 if (ap->rxconfig & ANEG_CFG_RF2)
3525 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3526 if (ap->rxconfig & ANEG_CFG_NP)
3527 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3528
3529 ap->link_time = ap->cur_time;
3530
3531 ap->flags ^= (MR_TOGGLE_TX);
3532 if (ap->rxconfig & 0x0008)
3533 ap->flags |= MR_TOGGLE_RX;
3534 if (ap->rxconfig & ANEG_CFG_NP)
3535 ap->flags |= MR_NP_RX;
3536 ap->flags |= MR_PAGE_RX;
3537
3538 ap->state = ANEG_STATE_COMPLETE_ACK;
3539 ret = ANEG_TIMER_ENAB;
3540 break;
3541
3542 case ANEG_STATE_COMPLETE_ACK:
3543 if (ap->ability_match != 0 &&
3544 ap->rxconfig == 0) {
3545 ap->state = ANEG_STATE_AN_ENABLE;
3546 break;
3547 }
3548 delta = ap->cur_time - ap->link_time;
3549 if (delta > ANEG_STATE_SETTLE_TIME) {
3550 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3551 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3552 } else {
3553 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3554 !(ap->flags & MR_NP_RX)) {
3555 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3556 } else {
3557 ret = ANEG_FAILED;
3558 }
3559 }
3560 }
3561 break;
3562
3563 case ANEG_STATE_IDLE_DETECT_INIT:
3564 ap->link_time = ap->cur_time;
3565 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3566 tw32_f(MAC_MODE, tp->mac_mode);
3567 udelay(40);
3568
3569 ap->state = ANEG_STATE_IDLE_DETECT;
3570 ret = ANEG_TIMER_ENAB;
3571 break;
3572
3573 case ANEG_STATE_IDLE_DETECT:
3574 if (ap->ability_match != 0 &&
3575 ap->rxconfig == 0) {
3576 ap->state = ANEG_STATE_AN_ENABLE;
3577 break;
3578 }
3579 delta = ap->cur_time - ap->link_time;
3580 if (delta > ANEG_STATE_SETTLE_TIME) {
3581 /* XXX another gem from the Broadcom driver :( */
3582 ap->state = ANEG_STATE_LINK_OK;
3583 }
3584 break;
3585
3586 case ANEG_STATE_LINK_OK:
3587 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3588 ret = ANEG_DONE;
3589 break;
3590
3591 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3592 /* ??? unimplemented */
3593 break;
3594
3595 case ANEG_STATE_NEXT_PAGE_WAIT:
3596 /* ??? unimplemented */
3597 break;
3598
3599 default:
3600 ret = ANEG_FAILED;
3601 break;
855e1111 3602 }
1da177e4
LT		 3603
3604 return ret;
3605}
3606
5be73b47 3607static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3608{
3609 int res = 0;
3610 struct tg3_fiber_aneginfo aninfo;
3611 int status = ANEG_FAILED;
3612 unsigned int tick;
3613 u32 tmp;
3614
3615 tw32_f(MAC_TX_AUTO_NEG, 0);
3616
3617 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3618 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3619 udelay(40);
3620
3621 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3622 udelay(40);
3623
3624 memset(&aninfo, 0, sizeof(aninfo));
3625 aninfo.flags |= MR_AN_ENABLE;
3626 aninfo.state = ANEG_STATE_UNKNOWN;
3627 aninfo.cur_time = 0;
3628 tick = 0;
3629 while (++tick < 195000) {
3630 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3631 if (status == ANEG_DONE || status == ANEG_FAILED)
3632 break;
3633
3634 udelay(1);
3635 }
3636
3637 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3638 tw32_f(MAC_MODE, tp->mac_mode);
3639 udelay(40);
3640
5be73b47
MC		 3641 *txflags = aninfo.txconfig;
3642 *rxflags = aninfo.flags;
1da177e4
LT		 3643
3644 if (status == ANEG_DONE &&
3645 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3646 MR_LP_ADV_FULL_DUPLEX)))
3647 res = 1;
3648
3649 return res;
3650}
3651
3652static void tg3_init_bcm8002(struct tg3 *tp)
3653{
3654 u32 mac_status = tr32(MAC_STATUS);
3655 int i;
3656
3657 /* Reset when initting first time or we have a link. */
3658 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3659 !(mac_status & MAC_STATUS_PCS_SYNCED))
3660 return;
3661
3662 /* Set PLL lock range. */
3663 tg3_writephy(tp, 0x16, 0x8007);
3664
3665 /* SW reset */
3666 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3667
3668 /* Wait for reset to complete. */
3669 /* XXX schedule_timeout() ... */
3670 for (i = 0; i < 500; i++)
3671 udelay(10);
3672
3673 /* Config mode; select PMA/Ch 1 regs. */
3674 tg3_writephy(tp, 0x10, 0x8411);
3675
3676 /* Enable auto-lock and comdet, select txclk for tx. */
3677 tg3_writephy(tp, 0x11, 0x0a10);
3678
3679 tg3_writephy(tp, 0x18, 0x00a0);
3680 tg3_writephy(tp, 0x16, 0x41ff);
3681
3682 /* Assert and deassert POR. */
3683 tg3_writephy(tp, 0x13, 0x0400);
3684 udelay(40);
3685 tg3_writephy(tp, 0x13, 0x0000);
3686
3687 tg3_writephy(tp, 0x11, 0x0a50);
3688 udelay(40);
3689 tg3_writephy(tp, 0x11, 0x0a10);
3690
3691 /* Wait for signal to stabilize */
3692 /* XXX schedule_timeout() ... */
3693 for (i = 0; i < 15000; i++)
3694 udelay(10);
3695
3696 /* Deselect the channel register so we can read the PHYID
3697 * later.
3698 */
3699 tg3_writephy(tp, 0x10, 0x8011);
3700}
3701
3702static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3703{
82cd3d11 3704 u16 flowctrl;
1da177e4
LT		 3705 u32 sg_dig_ctrl, sg_dig_status;
3706 u32 serdes_cfg, expected_sg_dig_ctrl;
3707 int workaround, port_a;
3708 int current_link_up;
3709
3710 serdes_cfg = 0;
3711 expected_sg_dig_ctrl = 0;
3712 workaround = 0;
3713 port_a = 1;
3714 current_link_up = 0;
3715
3716 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3717 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3718 workaround = 1;
3719 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3720 port_a = 0;
3721
3722 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3723 /* preserve bits 20-23 for voltage regulator */
3724 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3725 }
3726
3727 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3728
3729 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3730 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3731 if (workaround) {
3732 u32 val = serdes_cfg;
3733
3734 if (port_a)
3735 val |= 0xc010000;
3736 else
3737 val |= 0x4010000;
3738 tw32_f(MAC_SERDES_CFG, val);
3739 }
c98f6e3b
MC		 3740
3741 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3742 }
3743 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3744 tg3_setup_flow_control(tp, 0, 0);
3745 current_link_up = 1;
3746 }
3747 goto out;
3748 }
3749
3750 /* Want auto-negotiation. */
c98f6e3b 3751 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3752
82cd3d11
MC		 3753 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3754 if (flowctrl & ADVERTISE_1000XPAUSE)
3755 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3756 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3757 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3758
3759 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3760 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3761 tp->serdes_counter &&
3762 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3763 MAC_STATUS_RCVD_CFG)) ==
3764 MAC_STATUS_PCS_SYNCED)) {
3765 tp->serdes_counter--;
3766 current_link_up = 1;
3767 goto out;
3768 }
3769restart_autoneg:
1da177e4
LT		 3770 if (workaround)
3771 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3772 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3773 udelay(5);
3774 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3775
3d3ebe74
MC		 3776 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3777 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3778 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3779 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3780 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3781 mac_status = tr32(MAC_STATUS);
3782
c98f6e3b 3783 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3784 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3785 u32 local_adv = 0, remote_adv = 0;
3786
3787 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3788 local_adv |= ADVERTISE_1000XPAUSE;
3789 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3790 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3791
c98f6e3b 3792 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3793 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3794 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3795 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3796
3797 tg3_setup_flow_control(tp, local_adv, remote_adv);
3798 current_link_up = 1;
3d3ebe74
MC		 3799 tp->serdes_counter = 0;
3800 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3801 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3802 if (tp->serdes_counter)
3803 tp->serdes_counter--;
1da177e4
LT		 3804 else {
3805 if (workaround) {
3806 u32 val = serdes_cfg;
3807
3808 if (port_a)
3809 val |= 0xc010000;
3810 else
3811 val |= 0x4010000;
3812
3813 tw32_f(MAC_SERDES_CFG, val);
3814 }
3815
c98f6e3b 3816 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3817 udelay(40);
3818
3819 /* Link parallel detection - link is up */
3820 /* only if we have PCS_SYNC and not */
3821 /* receiving config code words */
3822 mac_status = tr32(MAC_STATUS);
3823 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3824 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3825 tg3_setup_flow_control(tp, 0, 0);
3826 current_link_up = 1;
3d3ebe74
MC		 3827 tp->tg3_flags2 |=
3828 TG3_FLG2_PARALLEL_DETECT;
3829 tp->serdes_counter =
3830 SERDES_PARALLEL_DET_TIMEOUT;
3831 } else
3832 goto restart_autoneg;
1da177e4
LT		 3833 }
3834 }
3d3ebe74
MC		 3835 } else {
3836 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3837 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3838 }
3839
3840out:
3841 return current_link_up;
3842}
3843
3844static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3845{
3846 int current_link_up = 0;
3847
5cf64b8a 3848 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3849 goto out;
1da177e4
LT		 3850
3851 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3852 u32 txflags, rxflags;
1da177e4 3853 int i;
6aa20a22 3854
5be73b47
MC		 3855 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3856 u32 local_adv = 0, remote_adv = 0;
1da177e4 3857
5be73b47
MC		 3858 if (txflags & ANEG_CFG_PS1)
3859 local_adv |= ADVERTISE_1000XPAUSE;
3860 if (txflags & ANEG_CFG_PS2)
3861 local_adv |= ADVERTISE_1000XPSE_ASYM;
3862
3863 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3864 remote_adv |= LPA_1000XPAUSE;
3865 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3866 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3867
3868 tg3_setup_flow_control(tp, local_adv, remote_adv);
3869
1da177e4
LT		 3870 current_link_up = 1;
3871 }
3872 for (i = 0; i < 30; i++) {
3873 udelay(20);
3874 tw32_f(MAC_STATUS,
3875 (MAC_STATUS_SYNC_CHANGED |
3876 MAC_STATUS_CFG_CHANGED));
3877 udelay(40);
3878 if ((tr32(MAC_STATUS) &
3879 (MAC_STATUS_SYNC_CHANGED |
3880 MAC_STATUS_CFG_CHANGED)) == 0)
3881 break;
3882 }
3883
3884 mac_status = tr32(MAC_STATUS);
3885 if (current_link_up == 0 &&
3886 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3887 !(mac_status & MAC_STATUS_RCVD_CFG))
3888 current_link_up = 1;
3889 } else {
5be73b47
MC		 3890 tg3_setup_flow_control(tp, 0, 0);
3891
1da177e4
LT		 3892 /* Forcing 1000FD link up. */
3893 current_link_up = 1;
1da177e4
LT		 3894
3895 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3896 udelay(40);
e8f3f6ca
MC		 3897
3898 tw32_f(MAC_MODE, tp->mac_mode);
3899 udelay(40);
1da177e4
LT		 3900 }
3901
3902out:
3903 return current_link_up;
3904}
3905
3906static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3907{
3908 u32 orig_pause_cfg;
3909 u16 orig_active_speed;
3910 u8 orig_active_duplex;
3911 u32 mac_status;
3912 int current_link_up;
3913 int i;
3914
8d018621 3915 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3916 orig_active_speed = tp->link_config.active_speed;
3917 orig_active_duplex = tp->link_config.active_duplex;
3918
3919 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3920 netif_carrier_ok(tp->dev) &&
3921 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3922 mac_status = tr32(MAC_STATUS);
3923 mac_status &= (MAC_STATUS_PCS_SYNCED |
3924 MAC_STATUS_SIGNAL_DET |
3925 MAC_STATUS_CFG_CHANGED |
3926 MAC_STATUS_RCVD_CFG);
3927 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3928 MAC_STATUS_SIGNAL_DET)) {
3929 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3930 MAC_STATUS_CFG_CHANGED));
3931 return 0;
3932 }
3933 }
3934
3935 tw32_f(MAC_TX_AUTO_NEG, 0);
3936
3937 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3938 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3939 tw32_f(MAC_MODE, tp->mac_mode);
3940 udelay(40);
3941
3942 if (tp->phy_id == PHY_ID_BCM8002)
3943 tg3_init_bcm8002(tp);
3944
3945 /* Enable link change event even when serdes polling. */
3946 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3947 udelay(40);
3948
3949 current_link_up = 0;
3950 mac_status = tr32(MAC_STATUS);
3951
3952 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3953 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3954 else
3955 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3956
898a56f8 3957 tp->napi[0].hw_status->status =
1da177e4 3958 (SD_STATUS_UPDATED |
898a56f8 3959 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3960
3961 for (i = 0; i < 100; i++) {
3962 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3963 MAC_STATUS_CFG_CHANGED));
3964 udelay(5);
3965 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3966 MAC_STATUS_CFG_CHANGED |
3967 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3968 break;
3969 }
3970
3971 mac_status = tr32(MAC_STATUS);
3972 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3973 current_link_up = 0;
3d3ebe74
MC		 3974 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3975 tp->serdes_counter == 0) {
1da177e4
LT		 3976 tw32_f(MAC_MODE, (tp->mac_mode |
3977 MAC_MODE_SEND_CONFIGS));
3978 udelay(1);
3979 tw32_f(MAC_MODE, tp->mac_mode);
3980 }
3981 }
3982
3983 if (current_link_up == 1) {
3984 tp->link_config.active_speed = SPEED_1000;
3985 tp->link_config.active_duplex = DUPLEX_FULL;
3986 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3987 LED_CTRL_LNKLED_OVERRIDE |
3988 LED_CTRL_1000MBPS_ON));
3989 } else {
3990 tp->link_config.active_speed = SPEED_INVALID;
3991 tp->link_config.active_duplex = DUPLEX_INVALID;
3992 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3993 LED_CTRL_LNKLED_OVERRIDE |
3994 LED_CTRL_TRAFFIC_OVERRIDE));
3995 }
3996
3997 if (current_link_up != netif_carrier_ok(tp->dev)) {
3998 if (current_link_up)
3999 netif_carrier_on(tp->dev);
4000 else
4001 netif_carrier_off(tp->dev);
4002 tg3_link_report(tp);
4003 } else {
8d018621 4004 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4005 if (orig_pause_cfg != now_pause_cfg ||
4006 orig_active_speed != tp->link_config.active_speed ||
4007 orig_active_duplex != tp->link_config.active_duplex)
4008 tg3_link_report(tp);
4009 }
4010
4011 return 0;
4012}
4013
747e8f8b
MC		 4014static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4015{
4016 int current_link_up, err = 0;
4017 u32 bmsr, bmcr;
4018 u16 current_speed;
4019 u8 current_duplex;
ef167e27 4020 u32 local_adv, remote_adv;
747e8f8b
MC		 4021
4022 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4023 tw32_f(MAC_MODE, tp->mac_mode);
4024 udelay(40);
4025
4026 tw32(MAC_EVENT, 0);
4027
4028 tw32_f(MAC_STATUS,
4029 (MAC_STATUS_SYNC_CHANGED |
4030 MAC_STATUS_CFG_CHANGED |
4031 MAC_STATUS_MI_COMPLETION |
4032 MAC_STATUS_LNKSTATE_CHANGED));
4033 udelay(40);
4034
4035 if (force_reset)
4036 tg3_phy_reset(tp);
4037
4038 current_link_up = 0;
4039 current_speed = SPEED_INVALID;
4040 current_duplex = DUPLEX_INVALID;
4041
4042 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4043 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4045 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4046 bmsr |= BMSR_LSTATUS;
4047 else
4048 bmsr &= ~BMSR_LSTATUS;
4049 }
747e8f8b
MC		 4050
4051 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4052
4053 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4054 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4055 /* do nothing, just check for link up at the end */
4056 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4057 u32 adv, new_adv;
4058
4059 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4060 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4061 ADVERTISE_1000XPAUSE |
4062 ADVERTISE_1000XPSE_ASYM |
4063 ADVERTISE_SLCT);
4064
ba4d07a8 4065 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4066
4067 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4068 new_adv |= ADVERTISE_1000XHALF;
4069 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4070 new_adv |= ADVERTISE_1000XFULL;
4071
4072 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4073 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4074 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4075 tg3_writephy(tp, MII_BMCR, bmcr);
4076
4077 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4078 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4079 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4080
4081 return err;
4082 }
4083 } else {
4084 u32 new_bmcr;
4085
4086 bmcr &= ~BMCR_SPEED1000;
4087 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4088
4089 if (tp->link_config.duplex == DUPLEX_FULL)
4090 new_bmcr |= BMCR_FULLDPLX;
4091
4092 if (new_bmcr != bmcr) {
4093 /* BMCR_SPEED1000 is a reserved bit that needs
4094 * to be set on write.
4095 */
4096 new_bmcr |= BMCR_SPEED1000;
4097
4098 /* Force a linkdown */
4099 if (netif_carrier_ok(tp->dev)) {
4100 u32 adv;
4101
4102 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4103 adv &= ~(ADVERTISE_1000XFULL |
4104 ADVERTISE_1000XHALF |
4105 ADVERTISE_SLCT);
4106 tg3_writephy(tp, MII_ADVERTISE, adv);
4107 tg3_writephy(tp, MII_BMCR, bmcr |
4108 BMCR_ANRESTART |
4109 BMCR_ANENABLE);
4110 udelay(10);
4111 netif_carrier_off(tp->dev);
4112 }
4113 tg3_writephy(tp, MII_BMCR, new_bmcr);
4114 bmcr = new_bmcr;
4115 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4116 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4117 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4118 ASIC_REV_5714) {
4119 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4120 bmsr |= BMSR_LSTATUS;
4121 else
4122 bmsr &= ~BMSR_LSTATUS;
4123 }
747e8f8b
MC		 4124 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4125 }
4126 }
4127
4128 if (bmsr & BMSR_LSTATUS) {
4129 current_speed = SPEED_1000;
4130 current_link_up = 1;
4131 if (bmcr & BMCR_FULLDPLX)
4132 current_duplex = DUPLEX_FULL;
4133 else
4134 current_duplex = DUPLEX_HALF;
4135
ef167e27
MC		 4136 local_adv = 0;
4137 remote_adv = 0;
4138
747e8f8b 4139 if (bmcr & BMCR_ANENABLE) {
ef167e27 4140 u32 common;
747e8f8b
MC		 4141
4142 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4143 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4144 common = local_adv & remote_adv;
4145 if (common & (ADVERTISE_1000XHALF |
4146 ADVERTISE_1000XFULL)) {
4147 if (common & ADVERTISE_1000XFULL)
4148 current_duplex = DUPLEX_FULL;
4149 else
4150 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4151 }
4152 else
4153 current_link_up = 0;
4154 }
4155 }
4156
ef167e27
MC		 4157 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4158 tg3_setup_flow_control(tp, local_adv, remote_adv);
4159
747e8f8b
MC		 4160 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4161 if (tp->link_config.active_duplex == DUPLEX_HALF)
4162 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4163
4164 tw32_f(MAC_MODE, tp->mac_mode);
4165 udelay(40);
4166
4167 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4168
4169 tp->link_config.active_speed = current_speed;
4170 tp->link_config.active_duplex = current_duplex;
4171
4172 if (current_link_up != netif_carrier_ok(tp->dev)) {
4173 if (current_link_up)
4174 netif_carrier_on(tp->dev);
4175 else {
4176 netif_carrier_off(tp->dev);
4177 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4178 }
4179 tg3_link_report(tp);
4180 }
4181 return err;
4182}
4183
4184static void tg3_serdes_parallel_detect(struct tg3 *tp)
4185{
3d3ebe74 4186 if (tp->serdes_counter) {
747e8f8b 4187 /* Give autoneg time to complete. */
3d3ebe74 4188 tp->serdes_counter--;
747e8f8b
MC		 4189 return;
4190 }
4191 if (!netif_carrier_ok(tp->dev) &&
4192 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4193 u32 bmcr;
4194
4195 tg3_readphy(tp, MII_BMCR, &bmcr);
4196 if (bmcr & BMCR_ANENABLE) {
4197 u32 phy1, phy2;
4198
4199 /* Select shadow register 0x1f */
4200 tg3_writephy(tp, 0x1c, 0x7c00);
4201 tg3_readphy(tp, 0x1c, &phy1);
4202
4203 /* Select expansion interrupt status register */
4204 tg3_writephy(tp, 0x17, 0x0f01);
4205 tg3_readphy(tp, 0x15, &phy2);
4206 tg3_readphy(tp, 0x15, &phy2);
4207
4208 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4209 /* We have signal detect and not receiving
4210 * config code words, link is up by parallel
4211 * detection.
4212 */
4213
4214 bmcr &= ~BMCR_ANENABLE;
4215 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4216 tg3_writephy(tp, MII_BMCR, bmcr);
4217 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4218 }
4219 }
4220 }
4221 else if (netif_carrier_ok(tp->dev) &&
4222 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4223 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4224 u32 phy2;
4225
4226 /* Select expansion interrupt status register */
4227 tg3_writephy(tp, 0x17, 0x0f01);
4228 tg3_readphy(tp, 0x15, &phy2);
4229 if (phy2 & 0x20) {
4230 u32 bmcr;
4231
4232 /* Config code words received, turn on autoneg. */
4233 tg3_readphy(tp, MII_BMCR, &bmcr);
4234 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4235
4236 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4237
4238 }
4239 }
4240}
4241
1da177e4
LT		 4242static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4243{
4244 int err;
4245
4246 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4247 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4248 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4249 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4250 } else {
4251 err = tg3_setup_copper_phy(tp, force_reset);
4252 }
4253
bcb37f6c 4254 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4255 u32 val, scale;
4256
4257 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4258 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4259 scale = 65;
4260 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4261 scale = 6;
4262 else
4263 scale = 12;
4264
4265 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4266 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4267 tw32(GRC_MISC_CFG, val);
4268 }
4269
1da177e4
LT		 4270 if (tp->link_config.active_speed == SPEED_1000 &&
4271 tp->link_config.active_duplex == DUPLEX_HALF)
4272 tw32(MAC_TX_LENGTHS,
4273 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4274 (6 << TX_LENGTHS_IPG_SHIFT) |
4275 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4276 else
4277 tw32(MAC_TX_LENGTHS,
4278 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4279 (6 << TX_LENGTHS_IPG_SHIFT) |
4280 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4281
4282 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4283 if (netif_carrier_ok(tp->dev)) {
4284 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4285 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4286 } else {
4287 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4288 }
4289 }
4290
8ed5d97e
MC		 4291 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4292 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4293 if (!netif_carrier_ok(tp->dev))
4294 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4295 tp->pwrmgmt_thresh;
4296 else
4297 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4298 tw32(PCIE_PWR_MGMT_THRESH, val);
4299 }
4300
1da177e4
LT		 4301 return err;
4302}
4303
df3e6548
MC		 4304/* This is called whenever we suspect that the system chipset is re-
4305 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4306 * is bogus tx completions. We try to recover by setting the
4307 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4308 * in the workqueue.
4309 */
4310static void tg3_tx_recover(struct tg3 *tp)
4311{
4312 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4313 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4314
4315 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4316 "mapped I/O cycles to the network device, attempting to "
4317 "recover. Please report the problem to the driver maintainer "
4318 "and include system chipset information.\n", tp->dev->name);
4319
4320 spin_lock(&tp->lock);
df3e6548 4321 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4322 spin_unlock(&tp->lock);
4323}
4324
f3f3f27e 4325static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4326{
4327 smp_mb();
f3f3f27e
MC		 4328 return tnapi->tx_pending -
4329 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4330}
4331
1da177e4
LT		 4332/* Tigon3 never reports partial packet sends. So we do not
4333 * need special logic to handle SKBs that have not had all
4334 * of their frags sent yet, like SunGEM does.
4335 */
17375d25 4336static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4337{
17375d25 4338 struct tg3 *tp = tnapi->tp;
898a56f8 4339 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4340 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4341 struct netdev_queue *txq;
4342 int index = tnapi - tp->napi;
4343
4344 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4345 index--;
4346
4347 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4348
4349 while (sw_idx != hw_idx) {
f3f3f27e 4350 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4351 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4352 int i, tx_bug = 0;
4353
4354 if (unlikely(skb == NULL)) {
4355 tg3_tx_recover(tp);
4356 return;
4357 }
1da177e4 4358
90079ce8 4359 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4360
4361 ri->skb = NULL;
4362
4363 sw_idx = NEXT_TX(sw_idx);
4364
4365 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4366 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4367 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4368 tx_bug = 1;
1da177e4
LT		 4369 sw_idx = NEXT_TX(sw_idx);
4370 }
4371
f47c11ee 4372 dev_kfree_skb(skb);
df3e6548
MC		 4373
4374 if (unlikely(tx_bug)) {
4375 tg3_tx_recover(tp);
4376 return;
4377 }
1da177e4
LT		 4378 }
4379
f3f3f27e 4380 tnapi->tx_cons = sw_idx;
1da177e4 4381
1b2a7205
MC		 4382 /* Need to make the tx_cons update visible to tg3_start_xmit()
4383 * before checking for netif_queue_stopped(). Without the
4384 * memory barrier, there is a small possibility that tg3_start_xmit()
4385 * will miss it and cause the queue to be stopped forever.
4386 */
4387 smp_mb();
4388
fe5f5787 4389 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4390 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4391 __netif_tx_lock(txq, smp_processor_id());
4392 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4393 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4394 netif_tx_wake_queue(txq);
4395 __netif_tx_unlock(txq);
51b91468 4396 }
1da177e4
LT		 4397}
4398
4399/* Returns size of skb allocated or < 0 on error.
4400 *
4401 * We only need to fill in the address because the other members
4402 * of the RX descriptor are invariant, see tg3_init_rings.
4403 *
4404 * Note the purposeful assymetry of cpu vs. chip accesses. For
4405 * posting buffers we only dirty the first cache line of the RX
4406 * descriptor (containing the address). Whereas for the RX status
4407 * buffers the cpu only reads the last cacheline of the RX descriptor
4408 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4409 */
17375d25 4410static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4411 int src_idx, u32 dest_idx_unmasked)
4412{
17375d25 4413 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4414 struct tg3_rx_buffer_desc *desc;
4415 struct ring_info *map, *src_map;
4416 struct sk_buff *skb;
4417 dma_addr_t mapping;
4418 int skb_size, dest_idx;
21f581a5 4419 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4420
4421 src_map = NULL;
4422 switch (opaque_key) {
4423 case RXD_OPAQUE_RING_STD:
4424 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4425 desc = &tpr->rx_std[dest_idx];
4426 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4427 if (src_idx >= 0)
21f581a5 4428 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4429 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4430 break;
4431
4432 case RXD_OPAQUE_RING_JUMBO:
4433 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4434 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4435 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4436 if (src_idx >= 0)
21f581a5 4437 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4438 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4439 break;
4440
4441 default:
4442 return -EINVAL;
855e1111 4443 }
1da177e4
LT		 4444
4445 /* Do not overwrite any of the map or rp information
4446 * until we are sure we can commit to a new buffer.
4447 *
4448 * Callers depend upon this behavior and assume that
4449 * we leave everything unchanged if we fail.
4450 */
287be12e 4451 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4452 if (skb == NULL)
4453 return -ENOMEM;
4454
1da177e4
LT		 4455 skb_reserve(skb, tp->rx_offset);
4456
287be12e 4457 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4458 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4459 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4460 dev_kfree_skb(skb);
4461 return -EIO;
4462 }
1da177e4
LT		 4463
4464 map->skb = skb;
4465 pci_unmap_addr_set(map, mapping, mapping);
4466
4467 if (src_map != NULL)
4468 src_map->skb = NULL;
4469
4470 desc->addr_hi = ((u64)mapping >> 32);
4471 desc->addr_lo = ((u64)mapping & 0xffffffff);
4472
4473 return skb_size;
4474}
4475
4476/* We only need to move over in the address because the other
4477 * members of the RX descriptor are invariant. See notes above
4478 * tg3_alloc_rx_skb for full details.
4479 */
17375d25 4480static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4481 int src_idx, u32 dest_idx_unmasked)
4482{
17375d25 4483 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4484 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4485 struct ring_info *src_map, *dest_map;
4486 int dest_idx;
21f581a5 4487 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4488
4489 switch (opaque_key) {
4490 case RXD_OPAQUE_RING_STD:
4491 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4492 dest_desc = &tpr->rx_std[dest_idx];
4493 dest_map = &tpr->rx_std_buffers[dest_idx];
4494 src_desc = &tpr->rx_std[src_idx];
4495 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4496 break;
4497
4498 case RXD_OPAQUE_RING_JUMBO:
4499 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4500 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4501 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4502 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4503 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4504 break;
4505
4506 default:
4507 return;
855e1111 4508 }
1da177e4
LT		 4509
4510 dest_map->skb = src_map->skb;
4511 pci_unmap_addr_set(dest_map, mapping,
4512 pci_unmap_addr(src_map, mapping));
4513 dest_desc->addr_hi = src_desc->addr_hi;
4514 dest_desc->addr_lo = src_desc->addr_lo;
4515
4516 src_map->skb = NULL;
4517}
4518
1da177e4
LT		 4519/* The RX ring scheme is composed of multiple rings which post fresh
4520 * buffers to the chip, and one special ring the chip uses to report
4521 * status back to the host.
4522 *
4523 * The special ring reports the status of received packets to the
4524 * host. The chip does not write into the original descriptor the
4525 * RX buffer was obtained from. The chip simply takes the original
4526 * descriptor as provided by the host, updates the status and length
4527 * field, then writes this into the next status ring entry.
4528 *
4529 * Each ring the host uses to post buffers to the chip is described
4530 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4531 * it is first placed into the on-chip ram. When the packet's length
4532 * is known, it walks down the TG3_BDINFO entries to select the ring.
4533 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4534 * which is within the range of the new packet's length is chosen.
4535 *
4536 * The "separate ring for rx status" scheme may sound queer, but it makes
4537 * sense from a cache coherency perspective. If only the host writes
4538 * to the buffer post rings, and only the chip writes to the rx status
4539 * rings, then cache lines never move beyond shared-modified state.
4540 * If both the host and chip were to write into the same ring, cache line
4541 * eviction could occur since both entities want it in an exclusive state.
4542 */
17375d25 4543static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4544{
17375d25 4545 struct tg3 *tp = tnapi->tp;
f92905de 4546 u32 work_mask, rx_std_posted = 0;
72334482 4547 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4548 u16 hw_idx;
1da177e4 4549 int received;
21f581a5 4550 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4551
8d9d7cfc 4552 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4553 /*
4554 * We need to order the read of hw_idx and the read of
4555 * the opaque cookie.
4556 */
4557 rmb();
1da177e4
LT		 4558 work_mask = 0;
4559 received = 0;
4560 while (sw_idx != hw_idx && budget > 0) {
72334482 4561 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4562 unsigned int len;
4563 struct sk_buff *skb;
4564 dma_addr_t dma_addr;
4565 u32 opaque_key, desc_idx, *post_ptr;
4566
4567 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4568 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4569 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4570 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4571 dma_addr = pci_unmap_addr(ri, mapping);
4572 skb = ri->skb;
4573 post_ptr = &tpr->rx_std_ptr;
f92905de 4574 rx_std_posted++;
1da177e4 4575 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4576 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4577 dma_addr = pci_unmap_addr(ri, mapping);
4578 skb = ri->skb;
4579 post_ptr = &tpr->rx_jmb_ptr;
4580 } else
1da177e4 4581 goto next_pkt_nopost;
1da177e4
LT		 4582
4583 work_mask |= opaque_key;
4584
4585 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4586 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4587 drop_it:
17375d25 4588 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4589 desc_idx, *post_ptr);
4590 drop_it_no_recycle:
4591 /* Other statistics kept track of by card. */
4592 tp->net_stats.rx_dropped++;
4593 goto next_pkt;
4594 }
4595
ad829268
MC		 4596 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4597 ETH_FCS_LEN;
1da177e4 4598
6aa20a22 4599 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4600 && tp->rx_offset == NET_IP_ALIGN
4601 /* rx_offset will likely not equal NET_IP_ALIGN
4602 * if this is a 5701 card running in PCI-X mode
4603 * [see tg3_get_invariants()]
4604 */
1da177e4
LT		 4605 ) {
4606 int skb_size;
4607
17375d25 4608 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT		 4609 desc_idx, *post_ptr);
4610 if (skb_size < 0)
4611 goto drop_it;
4612
287be12e 4613 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4614 PCI_DMA_FROMDEVICE);
4615
4616 skb_put(skb, len);
4617 } else {
4618 struct sk_buff *copy_skb;
4619
17375d25 4620 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4621 desc_idx, *post_ptr);
4622
ad829268
MC		 4623 copy_skb = netdev_alloc_skb(tp->dev,
4624 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4625 if (copy_skb == NULL)
4626 goto drop_it_no_recycle;
4627
ad829268 4628 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4629 skb_put(copy_skb, len);
4630 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4631 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4632 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4633
4634 /* We'll reuse the original ring buffer. */
4635 skb = copy_skb;
4636 }
4637
4638 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4639 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4640 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4641 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4642 skb->ip_summed = CHECKSUM_UNNECESSARY;
4643 else
4644 skb->ip_summed = CHECKSUM_NONE;
4645
4646 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4647
4648 if (len > (tp->dev->mtu + ETH_HLEN) &&
4649 skb->protocol != htons(ETH_P_8021Q)) {
4650 dev_kfree_skb(skb);
4651 goto next_pkt;
4652 }
4653
1da177e4
LT		 4654#if TG3_VLAN_TAG_USED
4655 if (tp->vlgrp != NULL &&
4656 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4657 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4658 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4659 } else
4660#endif
17375d25 4661 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4662
1da177e4
LT		 4663 received++;
4664 budget--;
4665
4666next_pkt:
4667 (*post_ptr)++;
f92905de
MC		 4668
4669 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4670 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4671
4672 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4673 TG3_64BIT_REG_LOW, idx);
4674 work_mask &= ~RXD_OPAQUE_RING_STD;
4675 rx_std_posted = 0;
4676 }
1da177e4 4677next_pkt_nopost:
483ba50b 4678 sw_idx++;
6b31a515 4679 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4680
4681 /* Refresh hw_idx to see if there is new work */
4682 if (sw_idx == hw_idx) {
8d9d7cfc 4683 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4684 rmb();
4685 }
1da177e4
LT		 4686 }
4687
4688 /* ACK the status ring. */
72334482
MC		 4689 tnapi->rx_rcb_ptr = sw_idx;
4690 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4691
4692 /* Refill RX ring(s). */
4693 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4694 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4695 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4696 sw_idx);
4697 }
4698 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4699 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4700 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4701 sw_idx);
4702 }
4703 mmiowb();
4704
4705 return received;
4706}
4707
17375d25 4708static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4709{
17375d25 4710 struct tg3 *tp = tnapi->tp;
898a56f8 4711 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4712
1da177e4
LT		 4713 /* handle link change and other phy events */
4714 if (!(tp->tg3_flags &
4715 (TG3_FLAG_USE_LINKCHG_REG |
4716 TG3_FLAG_POLL_SERDES))) {
4717 if (sblk->status & SD_STATUS_LINK_CHG) {
4718 sblk->status = SD_STATUS_UPDATED |
4719 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4720 spin_lock(&tp->lock);
dd477003
MC		 4721 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4722 tw32_f(MAC_STATUS,
4723 (MAC_STATUS_SYNC_CHANGED |
4724 MAC_STATUS_CFG_CHANGED |
4725 MAC_STATUS_MI_COMPLETION |
4726 MAC_STATUS_LNKSTATE_CHANGED));
4727 udelay(40);
4728 } else
4729 tg3_setup_phy(tp, 0);
f47c11ee 4730 spin_unlock(&tp->lock);
1da177e4
LT		 4731 }
4732 }
4733
4734 /* run TX completion thread */
f3f3f27e 4735 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4736 tg3_tx(tnapi);
6f535763 4737 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4738 return work_done;
1da177e4
LT		 4739 }
4740
1da177e4
LT		 4741 /* run RX thread, within the bounds set by NAPI.
4742 * All RX "locking" is done by ensuring outside
bea3348e 4743 * code synchronizes with tg3->napi.poll()
1da177e4 4744 */
8d9d7cfc 4745 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4746 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4747
6f535763
DM		 4748 return work_done;
4749}
4750
4751static int tg3_poll(struct napi_struct *napi, int budget)
4752{
8ef0442f
MC		 4753 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4754 struct tg3 *tp = tnapi->tp;
6f535763 4755 int work_done = 0;
898a56f8 4756 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4757
4758 while (1) {
17375d25 4759 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4760
4761 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4762 goto tx_recovery;
4763
4764 if (unlikely(work_done >= budget))
4765 break;
4766
4fd7ab59 4767 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4768 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4769 * to tell the hw how much work has been processed,
4770 * so we must read it before checking for more work.
4771 */
898a56f8
MC		 4772 tnapi->last_tag = sblk->status_tag;
4773 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4774 rmb();
4775 } else
4776 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4777
17375d25 4778 if (likely(!tg3_has_work(tnapi))) {
288379f0 4779 napi_complete(napi);
17375d25 4780 tg3_int_reenable(tnapi);
6f535763
DM		 4781 break;
4782 }
1da177e4
LT		 4783 }
4784
bea3348e 4785 return work_done;
6f535763
DM		 4786
4787tx_recovery:
4fd7ab59 4788 /* work_done is guaranteed to be less than budget. */
288379f0 4789 napi_complete(napi);
6f535763 4790 schedule_work(&tp->reset_task);
4fd7ab59 4791 return work_done;
1da177e4
LT		 4792}
4793
f47c11ee
DM		 4794static void tg3_irq_quiesce(struct tg3 *tp)
4795{
4f125f42
MC		 4796 int i;
4797
f47c11ee
DM		 4798 BUG_ON(tp->irq_sync);
4799
4800 tp->irq_sync = 1;
4801 smp_mb();
4802
4f125f42
MC		 4803 for (i = 0; i < tp->irq_cnt; i++)
4804 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4805}
4806
4807static inline int tg3_irq_sync(struct tg3 *tp)
4808{
4809 return tp->irq_sync;
4810}
4811
4812/* Fully shutdown all tg3 driver activity elsewhere in the system.
4813 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4814 * with as well. Most of the time, this is not necessary except when
4815 * shutting down the device.
4816 */
4817static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4818{
46966545 4819 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4820 if (irq_sync)
4821 tg3_irq_quiesce(tp);
f47c11ee
DM		 4822}
4823
4824static inline void tg3_full_unlock(struct tg3 *tp)
4825{
f47c11ee
DM		 4826 spin_unlock_bh(&tp->lock);
4827}
4828
fcfa0a32
MC		 4829/* One-shot MSI handler - Chip automatically disables interrupt
4830 * after sending MSI so driver doesn't have to do it.
4831 */
7d12e780 4832static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4833{
09943a18
MC		 4834 struct tg3_napi *tnapi = dev_id;
4835 struct tg3 *tp = tnapi->tp;
fcfa0a32 4836
898a56f8 4837 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4838 if (tnapi->rx_rcb)
4839 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4840
4841 if (likely(!tg3_irq_sync(tp)))
09943a18 4842 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4843
4844 return IRQ_HANDLED;
4845}
4846
88b06bc2
MC		 4847/* MSI ISR - No need to check for interrupt sharing and no need to
4848 * flush status block and interrupt mailbox. PCI ordering rules
4849 * guarantee that MSI will arrive after the status block.
4850 */
7d12e780 4851static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4852{
09943a18
MC		 4853 struct tg3_napi *tnapi = dev_id;
4854 struct tg3 *tp = tnapi->tp;
88b06bc2 4855
898a56f8 4856 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4857 if (tnapi->rx_rcb)
4858 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4859 /*
fac9b83e 4860 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4861 * chip-internal interrupt pending events.
fac9b83e 4862 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4863 * NIC to stop sending us irqs, engaging "in-intr-handler"
4864 * event coalescing.
4865 */
4866 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4867 if (likely(!tg3_irq_sync(tp)))
09943a18 4868 napi_schedule(&tnapi->napi);
61487480 4869
88b06bc2
MC		 4870 return IRQ_RETVAL(1);
4871}
4872
7d12e780 4873static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4874{
09943a18
MC		 4875 struct tg3_napi *tnapi = dev_id;
4876 struct tg3 *tp = tnapi->tp;
898a56f8 4877 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4878 unsigned int handled = 1;
4879
1da177e4
LT		 4880 /* In INTx mode, it is possible for the interrupt to arrive at
4881 * the CPU before the status block posted prior to the interrupt.
4882 * Reading the PCI State register will confirm whether the
4883 * interrupt is ours and will flush the status block.
4884 */
d18edcb2
MC		 4885 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4886 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4887 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4888 handled = 0;
f47c11ee 4889 goto out;
fac9b83e 4890 }
d18edcb2
MC		 4891 }
4892
4893 /*
4894 * Writing any value to intr-mbox-0 clears PCI INTA# and
4895 * chip-internal interrupt pending events.
4896 * Writing non-zero to intr-mbox-0 additional tells the
4897 * NIC to stop sending us irqs, engaging "in-intr-handler"
4898 * event coalescing.
c04cb347
MC		 4899 *
4900 * Flush the mailbox to de-assert the IRQ immediately to prevent
4901 * spurious interrupts. The flush impacts performance but
4902 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4903 */
c04cb347 4904 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4905 if (tg3_irq_sync(tp))
4906 goto out;
4907 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4908 if (likely(tg3_has_work(tnapi))) {
72334482 4909 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4910 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4911 } else {
4912 /* No work, shared interrupt perhaps? re-enable
4913 * interrupts, and flush that PCI write
4914 */
4915 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4916 0x00000000);
fac9b83e 4917 }
f47c11ee 4918out:
fac9b83e
DM		 4919 return IRQ_RETVAL(handled);
4920}
4921
7d12e780 4922static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4923{
09943a18
MC		 4924 struct tg3_napi *tnapi = dev_id;
4925 struct tg3 *tp = tnapi->tp;
898a56f8 4926 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4927 unsigned int handled = 1;
4928
fac9b83e
DM		 4929 /* In INTx mode, it is possible for the interrupt to arrive at
4930 * the CPU before the status block posted prior to the interrupt.
4931 * Reading the PCI State register will confirm whether the
4932 * interrupt is ours and will flush the status block.
4933 */
898a56f8 4934 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4935 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4936 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4937 handled = 0;
f47c11ee 4938 goto out;
1da177e4 4939 }
d18edcb2
MC		 4940 }
4941
4942 /*
4943 * writing any value to intr-mbox-0 clears PCI INTA# and
4944 * chip-internal interrupt pending events.
4945 * writing non-zero to intr-mbox-0 additional tells the
4946 * NIC to stop sending us irqs, engaging "in-intr-handler"
4947 * event coalescing.
c04cb347
MC		 4948 *
4949 * Flush the mailbox to de-assert the IRQ immediately to prevent
4950 * spurious interrupts. The flush impacts performance but
4951 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4952 */
c04cb347 4953 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4954
4955 /*
4956 * In a shared interrupt configuration, sometimes other devices'
4957 * interrupts will scream. We record the current status tag here
4958 * so that the above check can report that the screaming interrupts
4959 * are unhandled. Eventually they will be silenced.
4960 */
898a56f8 4961 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4962
d18edcb2
MC		 4963 if (tg3_irq_sync(tp))
4964 goto out;
624f8e50 4965
72334482 4966 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 4967
09943a18 4968 napi_schedule(&tnapi->napi);
624f8e50 4969
f47c11ee 4970out:
1da177e4
LT		 4971 return IRQ_RETVAL(handled);
4972}
4973
7938109f 4974/* ISR for interrupt test */
7d12e780 4975static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4976{
09943a18
MC		 4977 struct tg3_napi *tnapi = dev_id;
4978 struct tg3 *tp = tnapi->tp;
898a56f8 4979 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4980
f9804ddb
MC		 4981 if ((sblk->status & SD_STATUS_UPDATED) ||
4982 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4983 tg3_disable_ints(tp);
7938109f
MC		 4984 return IRQ_RETVAL(1);
4985 }
4986 return IRQ_RETVAL(0);
4987}
4988
8e7a22e3 4989static int tg3_init_hw(struct tg3 *, int);
944d980e 4990static int tg3_halt(struct tg3 *, int, int);
1da177e4 4991
b9ec6c1b
MC		 4992/* Restart hardware after configuration changes, self-test, etc.
4993 * Invoked with tp->lock held.
4994 */
4995static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4996 __releases(tp->lock)
4997 __acquires(tp->lock)
b9ec6c1b
MC		 4998{
4999 int err;
5000
5001 err = tg3_init_hw(tp, reset_phy);
5002 if (err) {
5003 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5004 "aborting.\n", tp->dev->name);
5005 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5006 tg3_full_unlock(tp);
5007 del_timer_sync(&tp->timer);
5008 tp->irq_sync = 0;
fed97810 5009 tg3_napi_enable(tp);
b9ec6c1b
MC		 5010 dev_close(tp->dev);
5011 tg3_full_lock(tp, 0);
5012 }
5013 return err;
5014}
5015
1da177e4
LT		 5016#ifdef CONFIG_NET_POLL_CONTROLLER
5017static void tg3_poll_controller(struct net_device *dev)
5018{
4f125f42 5019 int i;
88b06bc2
MC		 5020 struct tg3 *tp = netdev_priv(dev);
5021
4f125f42
MC		 5022 for (i = 0; i < tp->irq_cnt; i++)
5023 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5024}
5025#endif
5026
c4028958 5027static void tg3_reset_task(struct work_struct *work)
1da177e4 5028{
c4028958 5029 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5030 int err;
1da177e4
LT		 5031 unsigned int restart_timer;
5032
7faa006f 5033 tg3_full_lock(tp, 0);
7faa006f
MC		 5034
5035 if (!netif_running(tp->dev)) {
7faa006f
MC		 5036 tg3_full_unlock(tp);
5037 return;
5038 }
5039
5040 tg3_full_unlock(tp);
5041
b02fd9e3
MC		 5042 tg3_phy_stop(tp);
5043
1da177e4
LT		 5044 tg3_netif_stop(tp);
5045
f47c11ee 5046 tg3_full_lock(tp, 1);
1da177e4
LT		 5047
5048 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5049 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5050
df3e6548
MC		 5051 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5052 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5053 tp->write32_rx_mbox = tg3_write_flush_reg32;
5054 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5055 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5056 }
5057
944d980e 5058 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5059 err = tg3_init_hw(tp, 1);
5060 if (err)
b9ec6c1b 5061 goto out;
1da177e4
LT		 5062
5063 tg3_netif_start(tp);
5064
1da177e4
LT		 5065 if (restart_timer)
5066 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5067
b9ec6c1b 5068out:
7faa006f 5069 tg3_full_unlock(tp);
b02fd9e3
MC		 5070
5071 if (!err)
5072 tg3_phy_start(tp);
1da177e4
LT		 5073}
5074
b0408751
MC		 5075static void tg3_dump_short_state(struct tg3 *tp)
5076{
5077 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5078 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5079 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5080 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5081}
5082
1da177e4
LT		 5083static void tg3_tx_timeout(struct net_device *dev)
5084{
5085 struct tg3 *tp = netdev_priv(dev);
5086
b0408751 5087 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5088 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5089 dev->name);
b0408751
MC		 5090 tg3_dump_short_state(tp);
5091 }
1da177e4
LT		 5092
5093 schedule_work(&tp->reset_task);
5094}
5095
c58ec932
MC		 5096/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5097static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5098{
5099 u32 base = (u32) mapping & 0xffffffff;
5100
5101 return ((base > 0xffffdcc0) &&
5102 (base + len + 8 < base));
5103}
5104
72f2afb8
MC		 5105/* Test for DMA addresses > 40-bit */
5106static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5107 int len)
5108{
5109#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5110 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5111 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5112 return 0;
5113#else
5114 return 0;
5115#endif
5116}
5117
f3f3f27e 5118static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5119
72f2afb8
MC		 5120/* Workaround 4GB and 40-bit hardware DMA bugs. */
5121static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5122 u32 last_plus_one, u32 *start,
5123 u32 base_flags, u32 mss)
1da177e4 5124{
f3f3f27e 5125 struct tg3_napi *tnapi = &tp->napi[0];
41588ba1 5126 struct sk_buff *new_skb;
c58ec932 5127 dma_addr_t new_addr = 0;
1da177e4 5128 u32 entry = *start;
c58ec932 5129 int i, ret = 0;
1da177e4 5130
41588ba1
MC		 5131 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5132 new_skb = skb_copy(skb, GFP_ATOMIC);
5133 else {
5134 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5135
5136 new_skb = skb_copy_expand(skb,
5137 skb_headroom(skb) + more_headroom,
5138 skb_tailroom(skb), GFP_ATOMIC);
5139 }
5140
1da177e4 5141 if (!new_skb) {
c58ec932
MC		 5142 ret = -1;
5143 } else {
5144 /* New SKB is guaranteed to be linear. */
5145 entry = *start;
90079ce8 5146 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5147 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5148
c58ec932
MC		 5149 /* Make sure new skb does not cross any 4G boundaries.
5150 * Drop the packet if it does.
5151 */
0e1406dd
MC		 5152 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5153 tg3_4g_overflow_test(new_addr, new_skb->len))) {
638266f7
DM		 5154 if (!ret)
5155 skb_dma_unmap(&tp->pdev->dev, new_skb,
5156 DMA_TO_DEVICE);
c58ec932
MC		 5157 ret = -1;
5158 dev_kfree_skb(new_skb);
5159 new_skb = NULL;
5160 } else {
f3f3f27e 5161 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5162 base_flags, 1 | (mss << 1));
5163 *start = NEXT_TX(entry);
5164 }
1da177e4
LT		 5165 }
5166
1da177e4
LT		 5167 /* Now clean up the sw ring entries. */
5168 i = 0;
5169 while (entry != last_plus_one) {
f3f3f27e
MC		 5170 if (i == 0)
5171 tnapi->tx_buffers[entry].skb = new_skb;
5172 else
5173 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5174 entry = NEXT_TX(entry);
5175 i++;
5176 }
5177
90079ce8 5178 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5179 dev_kfree_skb(skb);
5180
c58ec932 5181 return ret;
1da177e4
LT		 5182}
5183
f3f3f27e 5184static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5185 dma_addr_t mapping, int len, u32 flags,
5186 u32 mss_and_is_end)
5187{
f3f3f27e 5188 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5189 int is_end = (mss_and_is_end & 0x1);
5190 u32 mss = (mss_and_is_end >> 1);
5191 u32 vlan_tag = 0;
5192
5193 if (is_end)
5194 flags |= TXD_FLAG_END;
5195 if (flags & TXD_FLAG_VLAN) {
5196 vlan_tag = flags >> 16;
5197 flags &= 0xffff;
5198 }
5199 vlan_tag |= (mss << TXD_MSS_SHIFT);
5200
5201 txd->addr_hi = ((u64) mapping >> 32);
5202 txd->addr_lo = ((u64) mapping & 0xffffffff);
5203 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5204 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5205}
5206
5a6f3074
MC		 5207/* hard_start_xmit for devices that don't have any bugs and
5208 * support TG3_FLG2_HW_TSO_2 only.
5209 */
61357325
SH		 5210static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5211 struct net_device *dev)
5a6f3074
MC		 5212{
5213 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5214 u32 len, entry, base_flags, mss;
90079ce8
DM		 5215 struct skb_shared_info *sp;
5216 dma_addr_t mapping;
fe5f5787
MC		 5217 struct tg3_napi *tnapi;
5218 struct netdev_queue *txq;
5a6f3074 5219
fe5f5787
MC		 5220 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5221 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5222 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5223 tnapi++;
5a6f3074 5224
00b70504 5225 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5226 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5227 * interrupt. Furthermore, IRQ processing runs lockless so we have
5228 * no IRQ context deadlocks to worry about either. Rejoice!
5229 */
f3f3f27e 5230 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5231 if (!netif_tx_queue_stopped(txq)) {
5232 netif_tx_stop_queue(txq);
5a6f3074
MC		 5233
5234 /* This is a hard error, log it. */
5235 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5236 "queue awake!\n", dev->name);
5237 }
5a6f3074
MC		 5238 return NETDEV_TX_BUSY;
5239 }
5240
f3f3f27e 5241 entry = tnapi->tx_prod;
5a6f3074 5242 base_flags = 0;
5a6f3074 5243 mss = 0;
c13e3713 5244 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5245 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5246 u32 hdrlen;
5a6f3074
MC		 5247
5248 if (skb_header_cloned(skb) &&
5249 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5250 dev_kfree_skb(skb);
5251 goto out_unlock;
5252 }
5253
b0026624 5254 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5255 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5256 else {
eddc9ec5
ACM		 5257 struct iphdr *iph = ip_hdr(skb);
5258
ab6a5bb6 5259 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5260 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5261
eddc9ec5
ACM		 5262 iph->check = 0;
5263 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5264 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5265 }
5a6f3074 5266
f6eb9b1f
MC		 5267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5268 mss |= (hdrlen & 0xc) << 12;
5269 if (hdrlen & 0x10)
5270 base_flags |= 0x00000010;
5271 base_flags |= (hdrlen & 0x3e0) << 5;
5272 } else
5273 mss |= hdrlen << 9;
5274
5a6f3074
MC		 5275 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5276 TXD_FLAG_CPU_POST_DMA);
5277
aa8223c7 5278 tcp_hdr(skb)->check = 0;
5a6f3074 5279
5a6f3074 5280 }
84fa7933 5281 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5282 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5283#if TG3_VLAN_TAG_USED
5284 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5285 base_flags |= (TXD_FLAG_VLAN |
5286 (vlan_tx_tag_get(skb) << 16));
5287#endif
5288
90079ce8
DM		 5289 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5290 dev_kfree_skb(skb);
5291 goto out_unlock;
5292 }
5293
5294 sp = skb_shinfo(skb);
5295
042a53a9 5296 mapping = sp->dma_head;
5a6f3074 5297
f3f3f27e 5298 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5299
fe5f5787
MC		 5300 len = skb_headlen(skb);
5301
f6eb9b1f
MC		 5302 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5303 !mss && skb->len > ETH_DATA_LEN)
5304 base_flags |= TXD_FLAG_JMB_PKT;
5305
f3f3f27e 5306 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5307 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5308
5309 entry = NEXT_TX(entry);
5310
5311 /* Now loop through additional data fragments, and queue them. */
5312 if (skb_shinfo(skb)->nr_frags > 0) {
5313 unsigned int i, last;
5314
5315 last = skb_shinfo(skb)->nr_frags - 1;
5316 for (i = 0; i <= last; i++) {
5317 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5318
5319 len = frag->size;
042a53a9 5320 mapping = sp->dma_maps[i];
f3f3f27e 5321 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5322
f3f3f27e 5323 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5324 base_flags, (i == last) | (mss << 1));
5325
5326 entry = NEXT_TX(entry);
5327 }
5328 }
5329
5330 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5331 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5332
f3f3f27e
MC		 5333 tnapi->tx_prod = entry;
5334 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5335 netif_tx_stop_queue(txq);
f3f3f27e 5336 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5337 netif_tx_wake_queue(txq);
5a6f3074
MC		 5338 }
5339
5340out_unlock:
cdd0db05 5341 mmiowb();
5a6f3074
MC		 5342
5343 return NETDEV_TX_OK;
5344}
5345
61357325
SH		 5346static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5347 struct net_device *);
52c0fd83
MC		 5348
5349/* Use GSO to workaround a rare TSO bug that may be triggered when the
5350 * TSO header is greater than 80 bytes.
5351 */
5352static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5353{
5354 struct sk_buff *segs, *nskb;
f3f3f27e 5355 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5356
5357 /* Estimate the number of fragments in the worst case */
f3f3f27e 5358 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5359 netif_stop_queue(tp->dev);
f3f3f27e 5360 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5361 return NETDEV_TX_BUSY;
5362
5363 netif_wake_queue(tp->dev);
52c0fd83
MC		 5364 }
5365
5366 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5367 if (IS_ERR(segs))
52c0fd83
MC		 5368 goto tg3_tso_bug_end;
5369
5370 do {
5371 nskb = segs;
5372 segs = segs->next;
5373 nskb->next = NULL;
5374 tg3_start_xmit_dma_bug(nskb, tp->dev);
5375 } while (segs);
5376
5377tg3_tso_bug_end:
5378 dev_kfree_skb(skb);
5379
5380 return NETDEV_TX_OK;
5381}
52c0fd83 5382
5a6f3074
MC		 5383/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5384 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5385 */
61357325
SH		 5386static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5387 struct net_device *dev)
1da177e4
LT		 5388{
5389 struct tg3 *tp = netdev_priv(dev);
1da177e4 5390 u32 len, entry, base_flags, mss;
90079ce8 5391 struct skb_shared_info *sp;
1da177e4 5392 int would_hit_hwbug;
90079ce8 5393 dma_addr_t mapping;
f3f3f27e 5394 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5395
5396 len = skb_headlen(skb);
5397
00b70504 5398 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5399 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5400 * interrupt. Furthermore, IRQ processing runs lockless so we have
5401 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5402 */
f3f3f27e 5403 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5404 if (!netif_queue_stopped(dev)) {
5405 netif_stop_queue(dev);
5406
5407 /* This is a hard error, log it. */
5408 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5409 "queue awake!\n", dev->name);
5410 }
1da177e4
LT		 5411 return NETDEV_TX_BUSY;
5412 }
5413
f3f3f27e 5414 entry = tnapi->tx_prod;
1da177e4 5415 base_flags = 0;
84fa7933 5416 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5417 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5418 mss = 0;
c13e3713 5419 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5420 struct iphdr *iph;
92c6b8d1 5421 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5422
5423 if (skb_header_cloned(skb) &&
5424 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5425 dev_kfree_skb(skb);
5426 goto out_unlock;
5427 }
5428
ab6a5bb6 5429 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5430 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5431
52c0fd83
MC		 5432 hdr_len = ip_tcp_len + tcp_opt_len;
5433 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5434 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5435 return (tg3_tso_bug(tp, skb));
5436
1da177e4
LT		 5437 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5438 TXD_FLAG_CPU_POST_DMA);
5439
eddc9ec5
ACM		 5440 iph = ip_hdr(skb);
5441 iph->check = 0;
5442 iph->tot_len = htons(mss + hdr_len);
1da177e4 5443 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5444 tcp_hdr(skb)->check = 0;
1da177e4 5445 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5446 } else
5447 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5448 iph->daddr, 0,
5449 IPPROTO_TCP,
5450 0);
1da177e4 5451
92c6b8d1
MC		 5452 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5453 mss |= hdr_len << 9;
5454 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5455 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5456 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5457 int tsflags;
5458
eddc9ec5 5459 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5460 mss |= (tsflags << 11);
5461 }
5462 } else {
eddc9ec5 5463 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5464 int tsflags;
5465
eddc9ec5 5466 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5467 base_flags |= tsflags << 12;
5468 }
5469 }
5470 }
1da177e4
LT		 5471#if TG3_VLAN_TAG_USED
5472 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5473 base_flags |= (TXD_FLAG_VLAN |
5474 (vlan_tx_tag_get(skb) << 16));
5475#endif
5476
90079ce8
DM		 5477 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5478 dev_kfree_skb(skb);
5479 goto out_unlock;
5480 }
5481
5482 sp = skb_shinfo(skb);
5483
042a53a9 5484 mapping = sp->dma_head;
1da177e4 5485
f3f3f27e 5486 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5487
5488 would_hit_hwbug = 0;
5489
92c6b8d1
MC		 5490 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5491 would_hit_hwbug = 1;
5492
0e1406dd
MC		 5493 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5494 tg3_4g_overflow_test(mapping, len))
5495 would_hit_hwbug = 1;
5496
5497 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5498 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5499 would_hit_hwbug = 1;
0e1406dd
MC		 5500
5501 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5502 would_hit_hwbug = 1;
1da177e4 5503
f3f3f27e 5504 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5505 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5506
5507 entry = NEXT_TX(entry);
5508
5509 /* Now loop through additional data fragments, and queue them. */
5510 if (skb_shinfo(skb)->nr_frags > 0) {
5511 unsigned int i, last;
5512
5513 last = skb_shinfo(skb)->nr_frags - 1;
5514 for (i = 0; i <= last; i++) {
5515 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5516
5517 len = frag->size;
042a53a9 5518 mapping = sp->dma_maps[i];
1da177e4 5519
f3f3f27e 5520 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5521
92c6b8d1
MC		 5522 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5523 len <= 8)
5524 would_hit_hwbug = 1;
5525
0e1406dd
MC		 5526 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5527 tg3_4g_overflow_test(mapping, len))
c58ec932 5528 would_hit_hwbug = 1;
1da177e4 5529
0e1406dd
MC		 5530 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5531 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5532 would_hit_hwbug = 1;
5533
1da177e4 5534 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5535 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5536 base_flags, (i == last)|(mss << 1));
5537 else
f3f3f27e 5538 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5539 base_flags, (i == last));
5540
5541 entry = NEXT_TX(entry);
5542 }
5543 }
5544
5545 if (would_hit_hwbug) {
5546 u32 last_plus_one = entry;
5547 u32 start;
1da177e4 5548
c58ec932
MC		 5549 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5550 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5551
5552 /* If the workaround fails due to memory/mapping
5553 * failure, silently drop this packet.
5554 */
72f2afb8 5555 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5556 &start, base_flags, mss))
1da177e4
LT		 5557 goto out_unlock;
5558
5559 entry = start;
5560 }
5561
5562 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5563 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
1da177e4 5564
f3f3f27e
MC		 5565 tnapi->tx_prod = entry;
5566 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5567 netif_stop_queue(dev);
f3f3f27e 5568 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
51b91468
MC		 5569 netif_wake_queue(tp->dev);
5570 }
1da177e4
LT		 5571
5572out_unlock:
cdd0db05 5573 mmiowb();
1da177e4
LT		 5574
5575 return NETDEV_TX_OK;
5576}
5577
5578static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5579 int new_mtu)
5580{
5581 dev->mtu = new_mtu;
5582
ef7f5ec0 5583 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5584 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5585 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5586 ethtool_op_set_tso(dev, 0);
5587 }
5588 else
5589 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5590 } else {
a4e2b347 5591 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5592 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5593 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5594 }
1da177e4
LT		 5595}
5596
5597static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5598{
5599 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5600 int err;
1da177e4
LT		 5601
5602 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5603 return -EINVAL;
5604
5605 if (!netif_running(dev)) {
5606 /* We'll just catch it later when the
5607 * device is up'd.
5608 */
5609 tg3_set_mtu(dev, tp, new_mtu);
5610 return 0;
5611 }
5612
b02fd9e3
MC		 5613 tg3_phy_stop(tp);
5614
1da177e4 5615 tg3_netif_stop(tp);
f47c11ee
DM		 5616
5617 tg3_full_lock(tp, 1);
1da177e4 5618
944d980e 5619 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5620
5621 tg3_set_mtu(dev, tp, new_mtu);
5622
b9ec6c1b 5623 err = tg3_restart_hw(tp, 0);
1da177e4 5624
b9ec6c1b
MC		 5625 if (!err)
5626 tg3_netif_start(tp);
1da177e4 5627
f47c11ee 5628 tg3_full_unlock(tp);
1da177e4 5629
b02fd9e3
MC		 5630 if (!err)
5631 tg3_phy_start(tp);
5632
b9ec6c1b 5633 return err;
1da177e4
LT		 5634}
5635
21f581a5
MC		 5636static void tg3_rx_prodring_free(struct tg3 *tp,
5637 struct tg3_rx_prodring_set *tpr)
1da177e4 5638{
1da177e4 5639 int i;
f3f3f27e 5640 struct ring_info *rxp;
1da177e4
LT		 5641
5642 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5643 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5644
5645 if (rxp->skb == NULL)
5646 continue;
1da177e4 5647
1da177e4
LT		 5648 pci_unmap_single(tp->pdev,
5649 pci_unmap_addr(rxp, mapping),
cf7a7298 5650 tp->rx_pkt_map_sz,
1da177e4
LT		 5651 PCI_DMA_FROMDEVICE);
5652 dev_kfree_skb_any(rxp->skb);
5653 rxp->skb = NULL;
5654 }
5655
cf7a7298
MC		 5656 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5657 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5658 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5659
cf7a7298
MC		 5660 if (rxp->skb == NULL)
5661 continue;
1da177e4 5662
cf7a7298
MC		 5663 pci_unmap_single(tp->pdev,
5664 pci_unmap_addr(rxp, mapping),
5665 TG3_RX_JMB_MAP_SZ,
5666 PCI_DMA_FROMDEVICE);
5667 dev_kfree_skb_any(rxp->skb);
5668 rxp->skb = NULL;
1da177e4 5669 }
1da177e4
LT		 5670 }
5671}
5672
5673/* Initialize tx/rx rings for packet processing.
5674 *
5675 * The chip has been shut down and the driver detached from
5676 * the networking, so no interrupts or new tx packets will
5677 * end up in the driver. tp->{tx,}lock are held and thus
5678 * we may not sleep.
5679 */
21f581a5
MC		 5680static int tg3_rx_prodring_alloc(struct tg3 *tp,
5681 struct tg3_rx_prodring_set *tpr)
1da177e4 5682{
287be12e 5683 u32 i, rx_pkt_dma_sz;
17375d25 5684 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5685
1da177e4 5686 /* Zero out all descriptors. */
21f581a5 5687 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5688
287be12e 5689 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5690 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5691 tp->dev->mtu > ETH_DATA_LEN)
5692 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5693 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5694
1da177e4
LT		 5695 /* Initialize invariants of the rings, we only set this
5696 * stuff once. This works because the card does not
5697 * write into the rx buffer posting rings.
5698 */
5699 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5700 struct tg3_rx_buffer_desc *rxd;
5701
21f581a5 5702 rxd = &tpr->rx_std[i];
287be12e 5703 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5704 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5705 rxd->opaque = (RXD_OPAQUE_RING_STD |
5706 (i << RXD_OPAQUE_INDEX_SHIFT));
5707 }
5708
1da177e4
LT		 5709 /* Now allocate fresh SKBs for each rx ring. */
5710 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5711 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC		 5712 printk(KERN_WARNING PFX
5713 "%s: Using a smaller RX standard ring, "
5714 "only %d out of %d buffers were allocated "
5715 "successfully.\n",
5716 tp->dev->name, i, tp->rx_pending);
5717 if (i == 0)
cf7a7298 5718 goto initfail;
32d8c572 5719 tp->rx_pending = i;
1da177e4 5720 break;
32d8c572 5721 }
1da177e4
LT		 5722 }
5723
cf7a7298
MC		 5724 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5725 goto done;
5726
21f581a5 5727 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5728
0f893dc6 5729 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5730 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5731 struct tg3_rx_buffer_desc *rxd;
5732
79ed5ac7 5733 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5734 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5735 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5736 RXD_FLAG_JUMBO;
5737 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5738 (i << RXD_OPAQUE_INDEX_SHIFT));
5739 }
5740
1da177e4 5741 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5742 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5743 -1, i) < 0) {
5744 printk(KERN_WARNING PFX
5745 "%s: Using a smaller RX jumbo ring, "
5746 "only %d out of %d buffers were "
5747 "allocated successfully.\n",
5748 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5749 if (i == 0)
5750 goto initfail;
32d8c572 5751 tp->rx_jumbo_pending = i;
1da177e4 5752 break;
32d8c572 5753 }
1da177e4
LT		 5754 }
5755 }
cf7a7298
MC		 5756
5757done:
32d8c572 5758 return 0;
cf7a7298
MC		 5759
5760initfail:
21f581a5 5761 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5762 return -ENOMEM;
1da177e4
LT		 5763}
5764
21f581a5
MC		 5765static void tg3_rx_prodring_fini(struct tg3 *tp,
5766 struct tg3_rx_prodring_set *tpr)
1da177e4 5767{
21f581a5
MC		 5768 kfree(tpr->rx_std_buffers);
5769 tpr->rx_std_buffers = NULL;
5770 kfree(tpr->rx_jmb_buffers);
5771 tpr->rx_jmb_buffers = NULL;
5772 if (tpr->rx_std) {
1da177e4 5773 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5774 tpr->rx_std, tpr->rx_std_mapping);
5775 tpr->rx_std = NULL;
1da177e4 5776 }
21f581a5 5777 if (tpr->rx_jmb) {
1da177e4 5778 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5779 tpr->rx_jmb, tpr->rx_jmb_mapping);
5780 tpr->rx_jmb = NULL;
1da177e4 5781 }
cf7a7298
MC		 5782}
5783
21f581a5
MC		 5784static int tg3_rx_prodring_init(struct tg3 *tp,
5785 struct tg3_rx_prodring_set *tpr)
cf7a7298 5786{
21f581a5
MC		 5787 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5788 TG3_RX_RING_SIZE, GFP_KERNEL);
5789 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5790 return -ENOMEM;
5791
21f581a5
MC		 5792 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5793 &tpr->rx_std_mapping);
5794 if (!tpr->rx_std)
cf7a7298
MC		 5795 goto err_out;
5796
5797 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5798 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5799 TG3_RX_JUMBO_RING_SIZE,
5800 GFP_KERNEL);
5801 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5802 goto err_out;
5803
21f581a5
MC		 5804 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5805 TG3_RX_JUMBO_RING_BYTES,
5806 &tpr->rx_jmb_mapping);
5807 if (!tpr->rx_jmb)
cf7a7298
MC		 5808 goto err_out;
5809 }
5810
5811 return 0;
5812
5813err_out:
21f581a5 5814 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5815 return -ENOMEM;
5816}
5817
5818/* Free up pending packets in all rx/tx rings.
5819 *
5820 * The chip has been shut down and the driver detached from
5821 * the networking, so no interrupts or new tx packets will
5822 * end up in the driver. tp->{tx,}lock is not held and we are not
5823 * in an interrupt context and thus may sleep.
5824 */
5825static void tg3_free_rings(struct tg3 *tp)
5826{
f77a6a8e 5827 int i, j;
cf7a7298 5828
f77a6a8e
MC		 5829 for (j = 0; j < tp->irq_cnt; j++) {
5830 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 5831
0c1d0e2b
MC		 5832 if (!tnapi->tx_buffers)
5833 continue;
5834
f77a6a8e
MC		 5835 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5836 struct tx_ring_info *txp;
5837 struct sk_buff *skb;
cf7a7298 5838
f77a6a8e
MC		 5839 txp = &tnapi->tx_buffers[i];
5840 skb = txp->skb;
cf7a7298 5841
f77a6a8e
MC		 5842 if (skb == NULL) {
5843 i++;
5844 continue;
5845 }
cf7a7298 5846
f77a6a8e 5847 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
cf7a7298 5848
f77a6a8e 5849 txp->skb = NULL;
cf7a7298 5850
f77a6a8e
MC		 5851 i += skb_shinfo(skb)->nr_frags + 1;
5852
5853 dev_kfree_skb_any(skb);
5854 }
cf7a7298
MC		 5855 }
5856
21f581a5 5857 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5858}
5859
5860/* Initialize tx/rx rings for packet processing.
5861 *
5862 * The chip has been shut down and the driver detached from
5863 * the networking, so no interrupts or new tx packets will
5864 * end up in the driver. tp->{tx,}lock are held and thus
5865 * we may not sleep.
5866 */
5867static int tg3_init_rings(struct tg3 *tp)
5868{
f77a6a8e 5869 int i;
72334482 5870
cf7a7298
MC		 5871 /* Free up all the SKBs. */
5872 tg3_free_rings(tp);
5873
f77a6a8e
MC		 5874 for (i = 0; i < tp->irq_cnt; i++) {
5875 struct tg3_napi *tnapi = &tp->napi[i];
5876
5877 tnapi->last_tag = 0;
5878 tnapi->last_irq_tag = 0;
5879 tnapi->hw_status->status = 0;
5880 tnapi->hw_status->status_tag = 0;
5881 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 5882
f77a6a8e
MC		 5883 tnapi->tx_prod = 0;
5884 tnapi->tx_cons = 0;
0c1d0e2b
MC		 5885 if (tnapi->tx_ring)
5886 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 5887
5888 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 5889 if (tnapi->rx_rcb)
5890 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 5891 }
72334482 5892
21f581a5 5893 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5894}
5895
5896/*
5897 * Must not be invoked with interrupt sources disabled and
5898 * the hardware shutdown down.
5899 */
5900static void tg3_free_consistent(struct tg3 *tp)
5901{
f77a6a8e 5902 int i;
898a56f8 5903
f77a6a8e
MC		 5904 for (i = 0; i < tp->irq_cnt; i++) {
5905 struct tg3_napi *tnapi = &tp->napi[i];
5906
5907 if (tnapi->tx_ring) {
5908 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5909 tnapi->tx_ring, tnapi->tx_desc_mapping);
5910 tnapi->tx_ring = NULL;
5911 }
5912
5913 kfree(tnapi->tx_buffers);
5914 tnapi->tx_buffers = NULL;
5915
5916 if (tnapi->rx_rcb) {
5917 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5918 tnapi->rx_rcb,
5919 tnapi->rx_rcb_mapping);
5920 tnapi->rx_rcb = NULL;
5921 }
5922
5923 if (tnapi->hw_status) {
5924 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5925 tnapi->hw_status,
5926 tnapi->status_mapping);
5927 tnapi->hw_status = NULL;
5928 }
1da177e4 5929 }
f77a6a8e 5930
1da177e4
LT		 5931 if (tp->hw_stats) {
5932 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5933 tp->hw_stats, tp->stats_mapping);
5934 tp->hw_stats = NULL;
5935 }
f77a6a8e 5936
21f581a5 5937 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5938}
5939
5940/*
5941 * Must not be invoked with interrupt sources disabled and
5942 * the hardware shutdown down. Can sleep.
5943 */
5944static int tg3_alloc_consistent(struct tg3 *tp)
5945{
f77a6a8e 5946 int i;
898a56f8 5947
21f581a5 5948 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5949 return -ENOMEM;
5950
f77a6a8e
MC		 5951 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5952 sizeof(struct tg3_hw_stats),
5953 &tp->stats_mapping);
5954 if (!tp->hw_stats)
1da177e4
LT		 5955 goto err_out;
5956
f77a6a8e 5957 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 5958
f77a6a8e
MC		 5959 for (i = 0; i < tp->irq_cnt; i++) {
5960 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 5961 struct tg3_hw_status *sblk;
1da177e4 5962
f77a6a8e
MC		 5963 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5964 TG3_HW_STATUS_SIZE,
5965 &tnapi->status_mapping);
5966 if (!tnapi->hw_status)
5967 goto err_out;
898a56f8 5968
f77a6a8e 5969 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 5970 sblk = tnapi->hw_status;
5971
5972 /*
5973 * When RSS is enabled, the status block format changes
5974 * slightly. The "rx_jumbo_consumer", "reserved",
5975 * and "rx_mini_consumer" members get mapped to the
5976 * other three rx return ring producer indexes.
5977 */
5978 switch (i) {
5979 default:
5980 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5981 break;
5982 case 2:
5983 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5984 break;
5985 case 3:
5986 tnapi->rx_rcb_prod_idx = &sblk->reserved;
5987 break;
5988 case 4:
5989 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5990 break;
5991 }
72334482 5992
0c1d0e2b
MC		 5993 /*
5994 * If multivector RSS is enabled, vector 0 does not handle
5995 * rx or tx interrupts. Don't allocate any resources for it.
5996 */
5997 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5998 continue;
5999
f77a6a8e
MC		 6000 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6001 TG3_RX_RCB_RING_BYTES(tp),
6002 &tnapi->rx_rcb_mapping);
6003 if (!tnapi->rx_rcb)
6004 goto err_out;
72334482 6005
f77a6a8e 6006 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 6007
f77a6a8e
MC		 6008 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6009 TG3_TX_RING_SIZE, GFP_KERNEL);
6010 if (!tnapi->tx_buffers)
6011 goto err_out;
6012
6013 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6014 TG3_TX_RING_BYTES,
6015 &tnapi->tx_desc_mapping);
6016 if (!tnapi->tx_ring)
6017 goto err_out;
6018 }
1da177e4
LT		 6019
6020 return 0;
6021
6022err_out:
6023 tg3_free_consistent(tp);
6024 return -ENOMEM;
6025}
6026
6027#define MAX_WAIT_CNT 1000
6028
6029/* To stop a block, clear the enable bit and poll till it
6030 * clears. tp->lock is held.
6031 */
b3b7d6be 6032static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6033{
6034 unsigned int i;
6035 u32 val;
6036
6037 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6038 switch (ofs) {
6039 case RCVLSC_MODE:
6040 case DMAC_MODE:
6041 case MBFREE_MODE:
6042 case BUFMGR_MODE:
6043 case MEMARB_MODE:
6044 /* We can't enable/disable these bits of the
6045 * 5705/5750, just say success.
6046 */
6047 return 0;
6048
6049 default:
6050 break;
855e1111 6051 }
1da177e4
LT		 6052 }
6053
6054 val = tr32(ofs);
6055 val &= ~enable_bit;
6056 tw32_f(ofs, val);
6057
6058 for (i = 0; i < MAX_WAIT_CNT; i++) {
6059 udelay(100);
6060 val = tr32(ofs);
6061 if ((val & enable_bit) == 0)
6062 break;
6063 }
6064
b3b7d6be 6065 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6066 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6067 "ofs=%lx enable_bit=%x\n",
6068 ofs, enable_bit);
6069 return -ENODEV;
6070 }
6071
6072 return 0;
6073}
6074
6075/* tp->lock is held. */
b3b7d6be 6076static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6077{
6078 int i, err;
6079
6080 tg3_disable_ints(tp);
6081
6082 tp->rx_mode &= ~RX_MODE_ENABLE;
6083 tw32_f(MAC_RX_MODE, tp->rx_mode);
6084 udelay(10);
6085
b3b7d6be
DM		 6086 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6087 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6088 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6089 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6090 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6091 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6092
6093 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6094 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6095 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6096 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6097 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6098 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6099 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6100
6101 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6102 tw32_f(MAC_MODE, tp->mac_mode);
6103 udelay(40);
6104
6105 tp->tx_mode &= ~TX_MODE_ENABLE;
6106 tw32_f(MAC_TX_MODE, tp->tx_mode);
6107
6108 for (i = 0; i < MAX_WAIT_CNT; i++) {
6109 udelay(100);
6110 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6111 break;
6112 }
6113 if (i >= MAX_WAIT_CNT) {
6114 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6115 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6116 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6117 err |= -ENODEV;
1da177e4
LT		 6118 }
6119
e6de8ad1 6120 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6121 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6122 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6123
6124 tw32(FTQ_RESET, 0xffffffff);
6125 tw32(FTQ_RESET, 0x00000000);
6126
b3b7d6be
DM		 6127 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6128 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6129
f77a6a8e
MC		 6130 for (i = 0; i < tp->irq_cnt; i++) {
6131 struct tg3_napi *tnapi = &tp->napi[i];
6132 if (tnapi->hw_status)
6133 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6134 }
1da177e4
LT		 6135 if (tp->hw_stats)
6136 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6137
1da177e4
LT		 6138 return err;
6139}
6140
0d3031d9
MC		 6141static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6142{
6143 int i;
6144 u32 apedata;
6145
6146 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6147 if (apedata != APE_SEG_SIG_MAGIC)
6148 return;
6149
6150 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6151 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6152 return;
6153
6154 /* Wait for up to 1 millisecond for APE to service previous event. */
6155 for (i = 0; i < 10; i++) {
6156 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6157 return;
6158
6159 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6160
6161 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6162 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6163 event | APE_EVENT_STATUS_EVENT_PENDING);
6164
6165 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6166
6167 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6168 break;
6169
6170 udelay(100);
6171 }
6172
6173 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6174 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6175}
6176
6177static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6178{
6179 u32 event;
6180 u32 apedata;
6181
6182 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6183 return;
6184
6185 switch (kind) {
6186 case RESET_KIND_INIT:
6187 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6188 APE_HOST_SEG_SIG_MAGIC);
6189 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6190 APE_HOST_SEG_LEN_MAGIC);
6191 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6192 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6193 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6194 APE_HOST_DRIVER_ID_MAGIC);
6195 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6196 APE_HOST_BEHAV_NO_PHYLOCK);
6197
6198 event = APE_EVENT_STATUS_STATE_START;
6199 break;
6200 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6201 /* With the interface we are currently using,
6202 * APE does not track driver state. Wiping
6203 * out the HOST SEGMENT SIGNATURE forces
6204 * the APE to assume OS absent status.
6205 */
6206 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6207
0d3031d9
MC		 6208 event = APE_EVENT_STATUS_STATE_UNLOAD;
6209 break;
6210 case RESET_KIND_SUSPEND:
6211 event = APE_EVENT_STATUS_STATE_SUSPEND;
6212 break;
6213 default:
6214 return;
6215 }
6216
6217 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6218
6219 tg3_ape_send_event(tp, event);
6220}
6221
1da177e4
LT		 6222/* tp->lock is held. */
6223static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6224{
f49639e6
DM		 6225 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6226 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6227
6228 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6229 switch (kind) {
6230 case RESET_KIND_INIT:
6231 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6232 DRV_STATE_START);
6233 break;
6234
6235 case RESET_KIND_SHUTDOWN:
6236 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6237 DRV_STATE_UNLOAD);
6238 break;
6239
6240 case RESET_KIND_SUSPEND:
6241 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6242 DRV_STATE_SUSPEND);
6243 break;
6244
6245 default:
6246 break;
855e1111 6247 }
1da177e4 6248 }
0d3031d9
MC		 6249
6250 if (kind == RESET_KIND_INIT ||
6251 kind == RESET_KIND_SUSPEND)
6252 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6253}
6254
6255/* tp->lock is held. */
6256static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6257{
6258 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6259 switch (kind) {
6260 case RESET_KIND_INIT:
6261 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6262 DRV_STATE_START_DONE);
6263 break;
6264
6265 case RESET_KIND_SHUTDOWN:
6266 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6267 DRV_STATE_UNLOAD_DONE);
6268 break;
6269
6270 default:
6271 break;
855e1111 6272 }
1da177e4 6273 }
0d3031d9
MC		 6274
6275 if (kind == RESET_KIND_SHUTDOWN)
6276 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6277}
6278
6279/* tp->lock is held. */
6280static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6281{
6282 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6283 switch (kind) {
6284 case RESET_KIND_INIT:
6285 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6286 DRV_STATE_START);
6287 break;
6288
6289 case RESET_KIND_SHUTDOWN:
6290 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6291 DRV_STATE_UNLOAD);
6292 break;
6293
6294 case RESET_KIND_SUSPEND:
6295 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6296 DRV_STATE_SUSPEND);
6297 break;
6298
6299 default:
6300 break;
855e1111 6301 }
1da177e4
LT		 6302 }
6303}
6304
7a6f4369
MC		 6305static int tg3_poll_fw(struct tg3 *tp)
6306{
6307 int i;
6308 u32 val;
6309
b5d3772c 6310 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6311 /* Wait up to 20ms for init done. */
6312 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6313 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6314 return 0;
0ccead18 6315 udelay(100);
b5d3772c
MC		 6316 }
6317 return -ENODEV;
6318 }
6319
7a6f4369
MC		 6320 /* Wait for firmware initialization to complete. */
6321 for (i = 0; i < 100000; i++) {
6322 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6323 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6324 break;
6325 udelay(10);
6326 }
6327
6328 /* Chip might not be fitted with firmware. Some Sun onboard
6329 * parts are configured like that. So don't signal the timeout
6330 * of the above loop as an error, but do report the lack of
6331 * running firmware once.
6332 */
6333 if (i >= 100000 &&
6334 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6335 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6336
6337 printk(KERN_INFO PFX "%s: No firmware running.\n",
6338 tp->dev->name);
6339 }
6340
6341 return 0;
6342}
6343
ee6a99b5
MC		 6344/* Save PCI command register before chip reset */
6345static void tg3_save_pci_state(struct tg3 *tp)
6346{
8a6eac90 6347 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6348}
6349
6350/* Restore PCI state after chip reset */
6351static void tg3_restore_pci_state(struct tg3 *tp)
6352{
6353 u32 val;
6354
6355 /* Re-enable indirect register accesses. */
6356 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6357 tp->misc_host_ctrl);
6358
6359 /* Set MAX PCI retry to zero. */
6360 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6361 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6362 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6363 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6364 /* Allow reads and writes to the APE register and memory space. */
6365 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6366 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6367 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6368 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6369
8a6eac90 6370 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6371
fcb389df
MC		 6372 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6373 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6374 pcie_set_readrq(tp->pdev, 4096);
6375 else {
6376 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6377 tp->pci_cacheline_sz);
6378 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6379 tp->pci_lat_timer);
6380 }
114342f2 6381 }
5f5c51e3 6382
ee6a99b5 6383 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6384 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6385 u16 pcix_cmd;
6386
6387 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6388 &pcix_cmd);
6389 pcix_cmd &= ~PCI_X_CMD_ERO;
6390 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6391 pcix_cmd);
6392 }
ee6a99b5
MC		 6393
6394 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6395
6396 /* Chip reset on 5780 will reset MSI enable bit,
6397 * so need to restore it.
6398 */
6399 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6400 u16 ctrl;
6401
6402 pci_read_config_word(tp->pdev,
6403 tp->msi_cap + PCI_MSI_FLAGS,
6404 &ctrl);
6405 pci_write_config_word(tp->pdev,
6406 tp->msi_cap + PCI_MSI_FLAGS,
6407 ctrl | PCI_MSI_FLAGS_ENABLE);
6408 val = tr32(MSGINT_MODE);
6409 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6410 }
6411 }
6412}
6413
1da177e4
LT		 6414static void tg3_stop_fw(struct tg3 *);
6415
6416/* tp->lock is held. */
6417static int tg3_chip_reset(struct tg3 *tp)
6418{
6419 u32 val;
1ee582d8 6420 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6421 int i, err;
1da177e4 6422
f49639e6
DM		 6423 tg3_nvram_lock(tp);
6424
77b483f1
MC		 6425 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6426
f49639e6
DM		 6427 /* No matching tg3_nvram_unlock() after this because
6428 * chip reset below will undo the nvram lock.
6429 */
6430 tp->nvram_lock_cnt = 0;
1da177e4 6431
ee6a99b5
MC		 6432 /* GRC_MISC_CFG core clock reset will clear the memory
6433 * enable bit in PCI register 4 and the MSI enable bit
6434 * on some chips, so we save relevant registers here.
6435 */
6436 tg3_save_pci_state(tp);
6437
d9ab5ad1 6438 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6439 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6440 tw32(GRC_FASTBOOT_PC, 0);
6441
1da177e4
LT		 6442 /*
6443 * We must avoid the readl() that normally takes place.
6444 * It locks machines, causes machine checks, and other
6445 * fun things. So, temporarily disable the 5701
6446 * hardware workaround, while we do the reset.
6447 */
1ee582d8
MC		 6448 write_op = tp->write32;
6449 if (write_op == tg3_write_flush_reg32)
6450 tp->write32 = tg3_write32;
1da177e4 6451
d18edcb2
MC		 6452 /* Prevent the irq handler from reading or writing PCI registers
6453 * during chip reset when the memory enable bit in the PCI command
6454 * register may be cleared. The chip does not generate interrupt
6455 * at this time, but the irq handler may still be called due to irq
6456 * sharing or irqpoll.
6457 */
6458 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6459 for (i = 0; i < tp->irq_cnt; i++) {
6460 struct tg3_napi *tnapi = &tp->napi[i];
6461 if (tnapi->hw_status) {
6462 tnapi->hw_status->status = 0;
6463 tnapi->hw_status->status_tag = 0;
6464 }
6465 tnapi->last_tag = 0;
6466 tnapi->last_irq_tag = 0;
b8fa2f3a 6467 }
d18edcb2 6468 smp_mb();
4f125f42
MC		 6469
6470 for (i = 0; i < tp->irq_cnt; i++)
6471 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6472
255ca311
MC		 6473 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6474 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6475 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6476 }
6477
1da177e4
LT		 6478 /* do the reset */
6479 val = GRC_MISC_CFG_CORECLK_RESET;
6480
6481 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6482 if (tr32(0x7e2c) == 0x60) {
6483 tw32(0x7e2c, 0x20);
6484 }
6485 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6486 tw32(GRC_MISC_CFG, (1 << 29));
6487 val |= (1 << 29);
6488 }
6489 }
6490
b5d3772c
MC		 6491 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6492 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6493 tw32(GRC_VCPU_EXT_CTRL,
6494 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6495 }
6496
1da177e4
LT		 6497 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6498 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6499 tw32(GRC_MISC_CFG, val);
6500
1ee582d8
MC		 6501 /* restore 5701 hardware bug workaround write method */
6502 tp->write32 = write_op;
1da177e4
LT		 6503
6504 /* Unfortunately, we have to delay before the PCI read back.
6505 * Some 575X chips even will not respond to a PCI cfg access
6506 * when the reset command is given to the chip.
6507 *
6508 * How do these hardware designers expect things to work
6509 * properly if the PCI write is posted for a long period
6510 * of time? It is always necessary to have some method by
6511 * which a register read back can occur to push the write
6512 * out which does the reset.
6513 *
6514 * For most tg3 variants the trick below was working.
6515 * Ho hum...
6516 */
6517 udelay(120);
6518
6519 /* Flush PCI posted writes. The normal MMIO registers
6520 * are inaccessible at this time so this is the only
6521 * way to make this reliably (actually, this is no longer
6522 * the case, see above). I tried to use indirect
6523 * register read/write but this upset some 5701 variants.
6524 */
6525 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6526
6527 udelay(120);
6528
5e7dfd0f 6529 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6530 u16 val16;
6531
1da177e4
LT		 6532 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6533 int i;
6534 u32 cfg_val;
6535
6536 /* Wait for link training to complete. */
6537 for (i = 0; i < 5000; i++)
6538 udelay(100);
6539
6540 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6541 pci_write_config_dword(tp->pdev, 0xc4,
6542 cfg_val | (1 << 15));
6543 }
5e7dfd0f 6544
e7126997
MC		 6545 /* Clear the "no snoop" and "relaxed ordering" bits. */
6546 pci_read_config_word(tp->pdev,
6547 tp->pcie_cap + PCI_EXP_DEVCTL,
6548 &val16);
6549 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6550 PCI_EXP_DEVCTL_NOSNOOP_EN);
6551 /*
6552 * Older PCIe devices only support the 128 byte
6553 * MPS setting. Enforce the restriction.
5e7dfd0f 6554 */
e7126997
MC		 6555 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6556 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6557 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6558 pci_write_config_word(tp->pdev,
6559 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6560 val16);
5e7dfd0f
MC		 6561
6562 pcie_set_readrq(tp->pdev, 4096);
6563
6564 /* Clear error status */
6565 pci_write_config_word(tp->pdev,
6566 tp->pcie_cap + PCI_EXP_DEVSTA,
6567 PCI_EXP_DEVSTA_CED |
6568 PCI_EXP_DEVSTA_NFED |
6569 PCI_EXP_DEVSTA_FED |
6570 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6571 }
6572
ee6a99b5 6573 tg3_restore_pci_state(tp);
1da177e4 6574
d18edcb2
MC		 6575 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6576
ee6a99b5
MC		 6577 val = 0;
6578 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6579 val = tr32(MEMARB_MODE);
ee6a99b5 6580 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6581
6582 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6583 tg3_stop_fw(tp);
6584 tw32(0x5000, 0x400);
6585 }
6586
6587 tw32(GRC_MODE, tp->grc_mode);
6588
6589 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6590 val = tr32(0xc4);
1da177e4
LT		 6591
6592 tw32(0xc4, val | (1 << 15));
6593 }
6594
6595 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6596 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6597 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6598 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6599 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6600 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6601 }
6602
6603 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6604 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6605 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6606 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6607 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6608 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6609 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6610 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6611 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6612 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6613 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6614 } else
6615 tw32_f(MAC_MODE, 0);
6616 udelay(40);
6617
77b483f1
MC		 6618 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6619
7a6f4369
MC		 6620 err = tg3_poll_fw(tp);
6621 if (err)
6622 return err;
1da177e4 6623
0a9140cf
MC		 6624 tg3_mdio_start(tp);
6625
52cdf852
MC		 6626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6627 u8 phy_addr;
6628
6629 phy_addr = tp->phy_addr;
6630 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6631
6632 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6633 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6634 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6635 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6636 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6637 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6638 udelay(10);
6639
6640 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6641 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6642 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6643 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6644 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6645 udelay(10);
6646
6647 tp->phy_addr = phy_addr;
6648 }
6649
1da177e4 6650 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6651 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6652 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6653 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6654 val = tr32(0x7c00);
1da177e4
LT		 6655
6656 tw32(0x7c00, val | (1 << 25));
6657 }
6658
6659 /* Reprobe ASF enable state. */
6660 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6661 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6662 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6663 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6664 u32 nic_cfg;
6665
6666 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6667 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6668 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6669 tp->last_event_jiffies = jiffies;
cbf46853 6670 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6671 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6672 }
6673 }
6674
6675 return 0;
6676}
6677
6678/* tp->lock is held. */
6679static void tg3_stop_fw(struct tg3 *tp)
6680{
0d3031d9
MC		 6681 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6682 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6683 /* Wait for RX cpu to ACK the previous event. */
6684 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6685
6686 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6687
6688 tg3_generate_fw_event(tp);
1da177e4 6689
7c5026aa
MC		 6690 /* Wait for RX cpu to ACK this event. */
6691 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6692 }
6693}
6694
6695/* tp->lock is held. */
944d980e 6696static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6697{
6698 int err;
6699
6700 tg3_stop_fw(tp);
6701
944d980e 6702 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6703
b3b7d6be 6704 tg3_abort_hw(tp, silent);
1da177e4
LT		 6705 err = tg3_chip_reset(tp);
6706
daba2a63
MC		 6707 __tg3_set_mac_addr(tp, 0);
6708
944d980e
MC		 6709 tg3_write_sig_legacy(tp, kind);
6710 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6711
6712 if (err)
6713 return err;
6714
6715 return 0;
6716}
6717
1da177e4
LT		 6718#define RX_CPU_SCRATCH_BASE 0x30000
6719#define RX_CPU_SCRATCH_SIZE 0x04000
6720#define TX_CPU_SCRATCH_BASE 0x34000
6721#define TX_CPU_SCRATCH_SIZE 0x04000
6722
6723/* tp->lock is held. */
6724static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6725{
6726 int i;
6727
5d9428de
ES		 6728 BUG_ON(offset == TX_CPU_BASE &&
6729 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6730
b5d3772c
MC		 6731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6732 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6733
6734 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6735 return 0;
6736 }
1da177e4
LT		 6737 if (offset == RX_CPU_BASE) {
6738 for (i = 0; i < 10000; i++) {
6739 tw32(offset + CPU_STATE, 0xffffffff);
6740 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6741 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6742 break;
6743 }
6744
6745 tw32(offset + CPU_STATE, 0xffffffff);
6746 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6747 udelay(10);
6748 } else {
6749 for (i = 0; i < 10000; i++) {
6750 tw32(offset + CPU_STATE, 0xffffffff);
6751 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6752 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6753 break;
6754 }
6755 }
6756
6757 if (i >= 10000) {
6758 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6759 "and %s CPU\n",
6760 tp->dev->name,
6761 (offset == RX_CPU_BASE ? "RX" : "TX"));
6762 return -ENODEV;
6763 }
ec41c7df
MC		 6764
6765 /* Clear firmware's nvram arbitration. */
6766 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6767 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6768 return 0;
6769}
6770
6771struct fw_info {
077f849d
JSR		 6772 unsigned int fw_base;
6773 unsigned int fw_len;
6774 const __be32 *fw_data;
1da177e4
LT		 6775};
6776
6777/* tp->lock is held. */
6778static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6779 int cpu_scratch_size, struct fw_info *info)
6780{
ec41c7df 6781 int err, lock_err, i;
1da177e4
LT		 6782 void (*write_op)(struct tg3 *, u32, u32);
6783
6784 if (cpu_base == TX_CPU_BASE &&
6785 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6786 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6787 "TX cpu firmware on %s which is 5705.\n",
6788 tp->dev->name);
6789 return -EINVAL;
6790 }
6791
6792 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6793 write_op = tg3_write_mem;
6794 else
6795 write_op = tg3_write_indirect_reg32;
6796
1b628151
MC		 6797 /* It is possible that bootcode is still loading at this point.
6798 * Get the nvram lock first before halting the cpu.
6799 */
ec41c7df 6800 lock_err = tg3_nvram_lock(tp);
1da177e4 6801 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6802 if (!lock_err)
6803 tg3_nvram_unlock(tp);
1da177e4
LT		 6804 if (err)
6805 goto out;
6806
6807 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6808 write_op(tp, cpu_scratch_base + i, 0);
6809 tw32(cpu_base + CPU_STATE, 0xffffffff);
6810 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6811 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6812 write_op(tp, (cpu_scratch_base +
077f849d 6813 (info->fw_base & 0xffff) +
1da177e4 6814 (i * sizeof(u32))),
077f849d 6815 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6816
6817 err = 0;
6818
6819out:
1da177e4
LT		 6820 return err;
6821}
6822
6823/* tp->lock is held. */
6824static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6825{
6826 struct fw_info info;
077f849d 6827 const __be32 *fw_data;
1da177e4
LT		 6828 int err, i;
6829
077f849d
JSR		 6830 fw_data = (void *)tp->fw->data;
6831
6832 /* Firmware blob starts with version numbers, followed by
6833 start address and length. We are setting complete length.
6834 length = end_address_of_bss - start_address_of_text.
6835 Remainder is the blob to be loaded contiguously
6836 from start address. */
6837
6838 info.fw_base = be32_to_cpu(fw_data[1]);
6839 info.fw_len = tp->fw->size - 12;
6840 info.fw_data = &fw_data[3];
1da177e4
LT		 6841
6842 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6843 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6844 &info);
6845 if (err)
6846 return err;
6847
6848 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6849 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6850 &info);
6851 if (err)
6852 return err;
6853
6854 /* Now startup only the RX cpu. */
6855 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6856 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6857
6858 for (i = 0; i < 5; i++) {
077f849d 6859 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6860 break;
6861 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6862 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6863 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6864 udelay(1000);
6865 }
6866 if (i >= 5) {
6867 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6868 "to set RX CPU PC, is %08x should be %08x\n",
6869 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6870 info.fw_base);
1da177e4
LT		 6871 return -ENODEV;
6872 }
6873 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6874 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6875
6876 return 0;
6877}
6878
1da177e4 6879/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6880
6881/* tp->lock is held. */
6882static int tg3_load_tso_firmware(struct tg3 *tp)
6883{
6884 struct fw_info info;
077f849d 6885 const __be32 *fw_data;
1da177e4
LT		 6886 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6887 int err, i;
6888
6889 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6890 return 0;
6891
077f849d
JSR		 6892 fw_data = (void *)tp->fw->data;
6893
6894 /* Firmware blob starts with version numbers, followed by
6895 start address and length. We are setting complete length.
6896 length = end_address_of_bss - start_address_of_text.
6897 Remainder is the blob to be loaded contiguously
6898 from start address. */
6899
6900 info.fw_base = be32_to_cpu(fw_data[1]);
6901 cpu_scratch_size = tp->fw_len;
6902 info.fw_len = tp->fw->size - 12;
6903 info.fw_data = &fw_data[3];
6904
1da177e4 6905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6906 cpu_base = RX_CPU_BASE;
6907 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6908 } else {
1da177e4
LT		 6909 cpu_base = TX_CPU_BASE;
6910 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6911 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6912 }
6913
6914 err = tg3_load_firmware_cpu(tp, cpu_base,
6915 cpu_scratch_base, cpu_scratch_size,
6916 &info);
6917 if (err)
6918 return err;
6919
6920 /* Now startup the cpu. */
6921 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6922 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6923
6924 for (i = 0; i < 5; i++) {
077f849d 6925 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6926 break;
6927 tw32(cpu_base + CPU_STATE, 0xffffffff);
6928 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6929 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6930 udelay(1000);
6931 }
6932 if (i >= 5) {
6933 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6934 "to set CPU PC, is %08x should be %08x\n",
6935 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6936 info.fw_base);
1da177e4
LT		 6937 return -ENODEV;
6938 }
6939 tw32(cpu_base + CPU_STATE, 0xffffffff);
6940 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6941 return 0;
6942}
6943
1da177e4 6944
1da177e4
LT		 6945static int tg3_set_mac_addr(struct net_device *dev, void *p)
6946{
6947 struct tg3 *tp = netdev_priv(dev);
6948 struct sockaddr *addr = p;
986e0aeb 6949 int err = 0, skip_mac_1 = 0;
1da177e4 6950
f9804ddb
MC		 6951 if (!is_valid_ether_addr(addr->sa_data))
6952 return -EINVAL;
6953
1da177e4
LT		 6954 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6955
e75f7c90
MC		 6956 if (!netif_running(dev))
6957 return 0;
6958
58712ef9 6959 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6960 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6961
986e0aeb
MC		 6962 addr0_high = tr32(MAC_ADDR_0_HIGH);
6963 addr0_low = tr32(MAC_ADDR_0_LOW);
6964 addr1_high = tr32(MAC_ADDR_1_HIGH);
6965 addr1_low = tr32(MAC_ADDR_1_LOW);
6966
6967 /* Skip MAC addr 1 if ASF is using it. */
6968 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6969 !(addr1_high == 0 && addr1_low == 0))
6970 skip_mac_1 = 1;
58712ef9 6971 }
986e0aeb
MC		 6972 spin_lock_bh(&tp->lock);
6973 __tg3_set_mac_addr(tp, skip_mac_1);
6974 spin_unlock_bh(&tp->lock);
1da177e4 6975
b9ec6c1b 6976 return err;
1da177e4
LT		 6977}
6978
6979/* tp->lock is held. */
6980static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6981 dma_addr_t mapping, u32 maxlen_flags,
6982 u32 nic_addr)
6983{
6984 tg3_write_mem(tp,
6985 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6986 ((u64) mapping >> 32));
6987 tg3_write_mem(tp,
6988 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6989 ((u64) mapping & 0xffffffff));
6990 tg3_write_mem(tp,
6991 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6992 maxlen_flags);
6993
6994 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6995 tg3_write_mem(tp,
6996 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6997 nic_addr);
6998}
6999
7000static void __tg3_set_rx_mode(struct net_device *);
d244c892 7001static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7002{
b6080e12
MC		 7003 int i;
7004
7005 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7006 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7007 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7008 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7009
7010 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7011 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7012 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7013 } else {
7014 tw32(HOSTCC_TXCOL_TICKS, 0);
7015 tw32(HOSTCC_TXMAX_FRAMES, 0);
7016 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7017
7018 tw32(HOSTCC_RXCOL_TICKS, 0);
7019 tw32(HOSTCC_RXMAX_FRAMES, 0);
7020 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7021 }
b6080e12 7022
15f9850d
DM		 7023 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7024 u32 val = ec->stats_block_coalesce_usecs;
7025
b6080e12
MC		 7026 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7027 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7028
15f9850d
DM		 7029 if (!netif_carrier_ok(tp->dev))
7030 val = 0;
7031
7032 tw32(HOSTCC_STAT_COAL_TICKS, val);
7033 }
b6080e12
MC		 7034
7035 for (i = 0; i < tp->irq_cnt - 1; i++) {
7036 u32 reg;
7037
7038 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7039 tw32(reg, ec->rx_coalesce_usecs);
7040 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7041 tw32(reg, ec->tx_coalesce_usecs);
7042 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7043 tw32(reg, ec->rx_max_coalesced_frames);
7044 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7045 tw32(reg, ec->tx_max_coalesced_frames);
7046 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7047 tw32(reg, ec->rx_max_coalesced_frames_irq);
7048 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7049 tw32(reg, ec->tx_max_coalesced_frames_irq);
7050 }
7051
7052 for (; i < tp->irq_max - 1; i++) {
7053 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7054 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7055 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7056 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7057 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7058 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7059 }
15f9850d 7060}
1da177e4 7061
2d31ecaf
MC		 7062/* tp->lock is held. */
7063static void tg3_rings_reset(struct tg3 *tp)
7064{
7065 int i;
f77a6a8e 7066 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7067 struct tg3_napi *tnapi = &tp->napi[0];
7068
7069 /* Disable all transmit rings but the first. */
7070 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7071 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7072 else
7073 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7074
7075 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7076 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7077 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7078 BDINFO_FLAGS_DISABLED);
7079
7080
7081 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7082 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7083 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7084 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7085 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7086 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7087 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7088 else
7089 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7090
7091 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7092 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7093 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7094 BDINFO_FLAGS_DISABLED);
7095
7096 /* Disable interrupts */
7097 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7098
7099 /* Zero mailbox registers. */
f77a6a8e
MC		 7100 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7101 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7102 tp->napi[i].tx_prod = 0;
7103 tp->napi[i].tx_cons = 0;
7104 tw32_mailbox(tp->napi[i].prodmbox, 0);
7105 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7106 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7107 }
7108 } else {
7109 tp->napi[0].tx_prod = 0;
7110 tp->napi[0].tx_cons = 0;
7111 tw32_mailbox(tp->napi[0].prodmbox, 0);
7112 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7113 }
2d31ecaf
MC		 7114
7115 /* Make sure the NIC-based send BD rings are disabled. */
7116 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7117 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7118 for (i = 0; i < 16; i++)
7119 tw32_tx_mbox(mbox + i * 8, 0);
7120 }
7121
7122 txrcb = NIC_SRAM_SEND_RCB;
7123 rxrcb = NIC_SRAM_RCV_RET_RCB;
7124
7125 /* Clear status block in ram. */
7126 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7127
7128 /* Set status block DMA address */
7129 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7130 ((u64) tnapi->status_mapping >> 32));
7131 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7132 ((u64) tnapi->status_mapping & 0xffffffff));
7133
f77a6a8e
MC		 7134 if (tnapi->tx_ring) {
7135 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7136 (TG3_TX_RING_SIZE <<
7137 BDINFO_FLAGS_MAXLEN_SHIFT),
7138 NIC_SRAM_TX_BUFFER_DESC);
7139 txrcb += TG3_BDINFO_SIZE;
7140 }
7141
7142 if (tnapi->rx_rcb) {
7143 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7144 (TG3_RX_RCB_RING_SIZE(tp) <<
7145 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7146 rxrcb += TG3_BDINFO_SIZE;
7147 }
7148
7149 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7150
f77a6a8e
MC		 7151 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7152 u64 mapping = (u64)tnapi->status_mapping;
7153 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7154 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7155
7156 /* Clear status block in ram. */
7157 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7158
7159 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7160 (TG3_TX_RING_SIZE <<
7161 BDINFO_FLAGS_MAXLEN_SHIFT),
7162 NIC_SRAM_TX_BUFFER_DESC);
7163
7164 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7165 (TG3_RX_RCB_RING_SIZE(tp) <<
7166 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7167
7168 stblk += 8;
7169 txrcb += TG3_BDINFO_SIZE;
7170 rxrcb += TG3_BDINFO_SIZE;
7171 }
2d31ecaf
MC		 7172}
7173
1da177e4 7174/* tp->lock is held. */
8e7a22e3 7175static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7176{
7177 u32 val, rdmac_mode;
7178 int i, err, limit;
21f581a5 7179 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7180
7181 tg3_disable_ints(tp);
7182
7183 tg3_stop_fw(tp);
7184
7185 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7186
7187 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7188 tg3_abort_hw(tp, 1);
1da177e4
LT		 7189 }
7190
dd477003
MC		 7191 if (reset_phy &&
7192 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7193 tg3_phy_reset(tp);
7194
1da177e4
LT		 7195 err = tg3_chip_reset(tp);
7196 if (err)
7197 return err;
7198
7199 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7200
bcb37f6c 7201 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7202 val = tr32(TG3_CPMU_CTRL);
7203 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7204 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7205
7206 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7207 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7208 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7209 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7210
7211 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7212 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7213 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7214 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7215
7216 val = tr32(TG3_CPMU_HST_ACC);
7217 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7218 val |= CPMU_HST_ACC_MACCLK_6_25;
7219 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7220 }
7221
33466d93
MC		 7222 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7223 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7224 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7225 PCIE_PWR_MGMT_L1_THRESH_4MS;
7226 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7227
7228 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7229 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7230
7231 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7232
f40386c8
MC		 7233 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7234 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7235 }
7236
1da177e4
LT		 7237 /* This works around an issue with Athlon chipsets on
7238 * B3 tigon3 silicon. This bit has no effect on any
7239 * other revision. But do not set this on PCI Express
795d01c5 7240 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7241 */
795d01c5
MC		 7242 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7243 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7244 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7245 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7246 }
1da177e4
LT		 7247
7248 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7249 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7250 val = tr32(TG3PCI_PCISTATE);
7251 val |= PCISTATE_RETRY_SAME_DMA;
7252 tw32(TG3PCI_PCISTATE, val);
7253 }
7254
0d3031d9
MC		 7255 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7256 /* Allow reads and writes to the
7257 * APE register and memory space.
7258 */
7259 val = tr32(TG3PCI_PCISTATE);
7260 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7261 PCISTATE_ALLOW_APE_SHMEM_WR;
7262 tw32(TG3PCI_PCISTATE, val);
7263 }
7264
1da177e4
LT		 7265 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7266 /* Enable some hw fixes. */
7267 val = tr32(TG3PCI_MSI_DATA);
7268 val |= (1 << 26) | (1 << 28) | (1 << 29);
7269 tw32(TG3PCI_MSI_DATA, val);
7270 }
7271
7272 /* Descriptor ring init may make accesses to the
7273 * NIC SRAM area to setup the TX descriptors, so we
7274 * can only do this after the hardware has been
7275 * successfully reset.
7276 */
32d8c572
MC		 7277 err = tg3_init_rings(tp);
7278 if (err)
7279 return err;
1da177e4 7280
9936bcf6 7281 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
f6eb9b1f
MC		 7282 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7283 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
d30cdd28
MC		 7284 /* This value is determined during the probe time DMA
7285 * engine test, tg3_test_dma.
7286 */
7287 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7288 }
1da177e4
LT		 7289
7290 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7291 GRC_MODE_4X_NIC_SEND_RINGS |
7292 GRC_MODE_NO_TX_PHDR_CSUM |
7293 GRC_MODE_NO_RX_PHDR_CSUM);
7294 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7295
7296 /* Pseudo-header checksum is done by hardware logic and not
7297 * the offload processers, so make the chip do the pseudo-
7298 * header checksums on receive. For transmit it is more
7299 * convenient to do the pseudo-header checksum in software
7300 * as Linux does that on transmit for us in all cases.
7301 */
7302 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7303
7304 tw32(GRC_MODE,
7305 tp->grc_mode |
7306 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7307
7308 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7309 val = tr32(GRC_MISC_CFG);
7310 val &= ~0xff;
7311 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7312 tw32(GRC_MISC_CFG, val);
7313
7314 /* Initialize MBUF/DESC pool. */
cbf46853 7315 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7316 /* Do nothing. */
7317 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7318 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7319 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7320 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7321 else
7322 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7323 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7324 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7325 }
1da177e4
LT		 7326 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7327 int fw_len;
7328
077f849d 7329 fw_len = tp->fw_len;
1da177e4
LT		 7330 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7331 tw32(BUFMGR_MB_POOL_ADDR,
7332 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7333 tw32(BUFMGR_MB_POOL_SIZE,
7334 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7335 }
1da177e4 7336
0f893dc6 7337 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7338 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7339 tp->bufmgr_config.mbuf_read_dma_low_water);
7340 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7341 tp->bufmgr_config.mbuf_mac_rx_low_water);
7342 tw32(BUFMGR_MB_HIGH_WATER,
7343 tp->bufmgr_config.mbuf_high_water);
7344 } else {
7345 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7346 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7347 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7348 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7349 tw32(BUFMGR_MB_HIGH_WATER,
7350 tp->bufmgr_config.mbuf_high_water_jumbo);
7351 }
7352 tw32(BUFMGR_DMA_LOW_WATER,
7353 tp->bufmgr_config.dma_low_water);
7354 tw32(BUFMGR_DMA_HIGH_WATER,
7355 tp->bufmgr_config.dma_high_water);
7356
7357 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7358 for (i = 0; i < 2000; i++) {
7359 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7360 break;
7361 udelay(10);
7362 }
7363 if (i >= 2000) {
7364 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7365 tp->dev->name);
7366 return -ENODEV;
7367 }
7368
7369 /* Setup replenish threshold. */
f92905de
MC		 7370 val = tp->rx_pending / 8;
7371 if (val == 0)
7372 val = 1;
7373 else if (val > tp->rx_std_max_post)
7374 val = tp->rx_std_max_post;
b5d3772c
MC		 7375 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7376 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7377 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7378
7379 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7380 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7381 }
f92905de
MC		 7382
7383 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7384
7385 /* Initialize TG3_BDINFO's at:
7386 * RCVDBDI_STD_BD: standard eth size rx ring
7387 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7388 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7389 *
7390 * like so:
7391 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7392 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7393 * ring attribute flags
7394 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7395 *
7396 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7397 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7398 *
7399 * The size of each ring is fixed in the firmware, but the location is
7400 * configurable.
7401 */
7402 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7403 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7404 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7405 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7406 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7407 NIC_SRAM_RX_BUFFER_DESC);
7408
fdb72b38
MC		 7409 /* Disable the mini ring */
7410 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7411 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7412 BDINFO_FLAGS_DISABLED);
7413
fdb72b38
MC		 7414 /* Program the jumbo buffer descriptor ring control
7415 * blocks on those devices that have them.
7416 */
8f666b07 7417 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7418 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7419 /* Setup replenish threshold. */
7420 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7421
0f893dc6 7422 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7423 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7424 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7425 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7426 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7427 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7428 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7429 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7430 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7431 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7432 } else {
7433 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7434 BDINFO_FLAGS_DISABLED);
7435 }
7436
f6eb9b1f
MC		 7437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7438 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7439 (RX_STD_MAX_SIZE << 2);
7440 else
7441 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7442 } else
7443 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7444
7445 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7446
21f581a5 7447 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7448 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7449 tpr->rx_std_ptr);
1da177e4 7450
21f581a5
MC		 7451 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7452 tp->rx_jumbo_pending : 0;
1da177e4 7453 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7454 tpr->rx_jmb_ptr);
1da177e4 7455
f6eb9b1f
MC		 7456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7457 tw32(STD_REPLENISH_LWM, 32);
7458 tw32(JMB_REPLENISH_LWM, 16);
7459 }
7460
2d31ecaf
MC		 7461 tg3_rings_reset(tp);
7462
1da177e4 7463 /* Initialize MAC address and backoff seed. */
986e0aeb 7464 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7465
7466 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7467 tw32(MAC_RX_MTU_SIZE,
7468 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7469
7470 /* The slot time is changed by tg3_setup_phy if we
7471 * run at gigabit with half duplex.
7472 */
7473 tw32(MAC_TX_LENGTHS,
7474 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7475 (6 << TX_LENGTHS_IPG_SHIFT) |
7476 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7477
7478 /* Receive rules. */
7479 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7480 tw32(RCVLPC_CONFIG, 0x0181);
7481
7482 /* Calculate RDMAC_MODE setting early, we need it to determine
7483 * the RCVLPC_STATE_ENABLE mask.
7484 */
7485 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7486 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7487 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7488 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7489 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7490
57e6983c 7491 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7492 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7493 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7494 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7495 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7496 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7497
85e94ced
MC		 7498 /* If statement applies to 5705 and 5750 PCI devices only */
7499 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7500 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7501 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7502 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7503 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7504 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7505 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7506 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7507 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7508 }
7509 }
7510
85e94ced
MC		 7511 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7512 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7513
1da177e4 7514 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7515 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7516
7517 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7518 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7519 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7520
7521 /* Receive/send statistics. */
1661394e
MC		 7522 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7523 val = tr32(RCVLPC_STATS_ENABLE);
7524 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7525 tw32(RCVLPC_STATS_ENABLE, val);
7526 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7527 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7528 val = tr32(RCVLPC_STATS_ENABLE);
7529 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7530 tw32(RCVLPC_STATS_ENABLE, val);
7531 } else {
7532 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7533 }
7534 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7535 tw32(SNDDATAI_STATSENAB, 0xffffff);
7536 tw32(SNDDATAI_STATSCTRL,
7537 (SNDDATAI_SCTRL_ENABLE |
7538 SNDDATAI_SCTRL_FASTUPD));
7539
7540 /* Setup host coalescing engine. */
7541 tw32(HOSTCC_MODE, 0);
7542 for (i = 0; i < 2000; i++) {
7543 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7544 break;
7545 udelay(10);
7546 }
7547
d244c892 7548 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7549
1da177e4
LT		 7550 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7551 /* Status/statistics block address. See tg3_timer,
7552 * the tg3_periodic_fetch_stats call there, and
7553 * tg3_get_stats to see how this works for 5705/5750 chips.
7554 */
1da177e4
LT		 7555 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7556 ((u64) tp->stats_mapping >> 32));
7557 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7558 ((u64) tp->stats_mapping & 0xffffffff));
7559 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7560
1da177e4 7561 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7562
7563 /* Clear statistics and status block memory areas */
7564 for (i = NIC_SRAM_STATS_BLK;
7565 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7566 i += sizeof(u32)) {
7567 tg3_write_mem(tp, i, 0);
7568 udelay(40);
7569 }
1da177e4
LT		 7570 }
7571
7572 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7573
7574 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7575 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7576 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7577 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7578
c94e3941
MC		 7579 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7580 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7581 /* reset to prevent losing 1st rx packet intermittently */
7582 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7583 udelay(10);
7584 }
7585
3bda1258
MC		 7586 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7587 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7588 else
7589 tp->mac_mode = 0;
7590 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7591 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7592 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7593 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7594 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7595 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7596 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7597 udelay(40);
7598
314fba34 7599 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7600 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7601 * register to preserve the GPIO settings for LOMs. The GPIOs,
7602 * whether used as inputs or outputs, are set by boot code after
7603 * reset.
7604 */
9d26e213 7605 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7606 u32 gpio_mask;
7607
9d26e213
MC		 7608 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7609 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7610 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7611
7612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7613 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7614 GRC_LCLCTRL_GPIO_OUTPUT3;
7615
af36e6b6
MC		 7616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7617 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7618
aaf84465 7619 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7620 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7621
7622 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7623 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7624 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7625 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7626 }
1da177e4
LT		 7627 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7628 udelay(100);
7629
baf8a94a
MC		 7630 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7631 val = tr32(MSGINT_MODE);
7632 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7633 tw32(MSGINT_MODE, val);
7634 }
7635
1da177e4
LT		 7636 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7637 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7638 udelay(40);
7639 }
7640
7641 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7642 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7643 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7644 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7645 WDMAC_MODE_LNGREAD_ENAB);
7646
85e94ced
MC		 7647 /* If statement applies to 5705 and 5750 PCI devices only */
7648 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7649 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7651 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7652 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7653 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7654 /* nothing */
7655 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7656 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7657 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7658 val |= WDMAC_MODE_RX_ACCEL;
7659 }
7660 }
7661
d9ab5ad1 7662 /* Enable host coalescing bug fix */
321d32a0 7663 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7664 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7665
788a035e
MC		 7666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7667 val |= WDMAC_MODE_BURST_ALL_DATA;
7668
1da177e4
LT		 7669 tw32_f(WDMAC_MODE, val);
7670 udelay(40);
7671
9974a356
MC		 7672 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7673 u16 pcix_cmd;
7674
7675 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7676 &pcix_cmd);
1da177e4 7677 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7678 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7679 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7680 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7681 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7682 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7683 }
9974a356
MC		 7684 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7685 pcix_cmd);
1da177e4
LT		 7686 }
7687
7688 tw32_f(RDMAC_MODE, rdmac_mode);
7689 udelay(40);
7690
7691 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7692 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7693 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7694
7695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7696 tw32(SNDDATAC_MODE,
7697 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7698 else
7699 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7700
1da177e4
LT		 7701 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7702 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7703 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7704 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7705 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7706 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 7707 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7708 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7709 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7710 tw32(SNDBDI_MODE, val);
1da177e4
LT		 7711 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7712
7713 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7714 err = tg3_load_5701_a0_firmware_fix(tp);
7715 if (err)
7716 return err;
7717 }
7718
1da177e4
LT		 7719 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7720 err = tg3_load_tso_firmware(tp);
7721 if (err)
7722 return err;
7723 }
1da177e4
LT		 7724
7725 tp->tx_mode = TX_MODE_ENABLE;
7726 tw32_f(MAC_TX_MODE, tp->tx_mode);
7727 udelay(100);
7728
baf8a94a
MC		 7729 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7730 u32 reg = MAC_RSS_INDIR_TBL_0;
7731 u8 *ent = (u8 *)&val;
7732
7733 /* Setup the indirection table */
7734 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7735 int idx = i % sizeof(val);
7736
7737 ent[idx] = i % (tp->irq_cnt - 1);
7738 if (idx == sizeof(val) - 1) {
7739 tw32(reg, val);
7740 reg += 4;
7741 }
7742 }
7743
7744 /* Setup the "secret" hash key. */
7745 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7746 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7747 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7748 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7749 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7750 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7751 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7752 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7753 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7754 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7755 }
7756
1da177e4 7757 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7758 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7759 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7760
baf8a94a
MC		 7761 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7762 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7763 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7764 RX_MODE_RSS_IPV6_HASH_EN |
7765 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7766 RX_MODE_RSS_IPV4_HASH_EN |
7767 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7768
1da177e4
LT		 7769 tw32_f(MAC_RX_MODE, tp->rx_mode);
7770 udelay(10);
7771
1da177e4
LT		 7772 tw32(MAC_LED_CTRL, tp->led_ctrl);
7773
7774 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7775 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7776 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7777 udelay(10);
7778 }
7779 tw32_f(MAC_RX_MODE, tp->rx_mode);
7780 udelay(10);
7781
7782 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7783 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7784 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7785 /* Set drive transmission level to 1.2V */
7786 /* only if the signal pre-emphasis bit is not set */
7787 val = tr32(MAC_SERDES_CFG);
7788 val &= 0xfffff000;
7789 val |= 0x880;
7790 tw32(MAC_SERDES_CFG, val);
7791 }
7792 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7793 tw32(MAC_SERDES_CFG, 0x616000);
7794 }
7795
7796 /* Prevent chip from dropping frames when flow control
7797 * is enabled.
7798 */
7799 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7800
7801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7802 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7803 /* Use hardware link auto-negotiation */
7804 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7805 }
7806
d4d2c558
MC		 7807 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7808 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7809 u32 tmp;
7810
7811 tmp = tr32(SERDES_RX_CTRL);
7812 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7813 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7814 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7815 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7816 }
7817
dd477003
MC		 7818 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7819 if (tp->link_config.phy_is_low_power) {
7820 tp->link_config.phy_is_low_power = 0;
7821 tp->link_config.speed = tp->link_config.orig_speed;
7822 tp->link_config.duplex = tp->link_config.orig_duplex;
7823 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7824 }
1da177e4 7825
dd477003
MC		 7826 err = tg3_setup_phy(tp, 0);
7827 if (err)
7828 return err;
1da177e4 7829
dd477003 7830 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7831 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7832 u32 tmp;
7833
7834 /* Clear CRC stats. */
7835 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7836 tg3_writephy(tp, MII_TG3_TEST1,
7837 tmp | MII_TG3_TEST1_CRC_EN);
7838 tg3_readphy(tp, 0x14, &tmp);
7839 }
1da177e4
LT		 7840 }
7841 }
7842
7843 __tg3_set_rx_mode(tp->dev);
7844
7845 /* Initialize receive rules. */
7846 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7847 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7848 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7849 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7850
4cf78e4f 7851 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7852 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7853 limit = 8;
7854 else
7855 limit = 16;
7856 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7857 limit -= 4;
7858 switch (limit) {
7859 case 16:
7860 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7861 case 15:
7862 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7863 case 14:
7864 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7865 case 13:
7866 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7867 case 12:
7868 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7869 case 11:
7870 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7871 case 10:
7872 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7873 case 9:
7874 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7875 case 8:
7876 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7877 case 7:
7878 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7879 case 6:
7880 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7881 case 5:
7882 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7883 case 4:
7884 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7885 case 3:
7886 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7887 case 2:
7888 case 1:
7889
7890 default:
7891 break;
855e1111 7892 }
1da177e4 7893
9ce768ea
MC		 7894 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7895 /* Write our heartbeat update interval to APE. */
7896 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7897 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7898
1da177e4
LT		 7899 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7900
1da177e4
LT		 7901 return 0;
7902}
7903
7904/* Called at device open time to get the chip ready for
7905 * packet processing. Invoked with tp->lock held.
7906 */
8e7a22e3 7907static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7908{
1da177e4
LT		 7909 tg3_switch_clocks(tp);
7910
7911 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7912
2f751b67 7913 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7914}
7915
7916#define TG3_STAT_ADD32(PSTAT, REG) \
7917do { u32 __val = tr32(REG); \
7918 (PSTAT)->low += __val; \
7919 if ((PSTAT)->low < __val) \
7920 (PSTAT)->high += 1; \
7921} while (0)
7922
7923static void tg3_periodic_fetch_stats(struct tg3 *tp)
7924{
7925 struct tg3_hw_stats *sp = tp->hw_stats;
7926
7927 if (!netif_carrier_ok(tp->dev))
7928 return;
7929
7930 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7931 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7932 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7933 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7934 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7935 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7936 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7937 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7938 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7939 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7940 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7941 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7942 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7943
7944 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7945 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7946 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7947 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7948 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7949 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7950 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7951 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7952 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7953 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7954 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7955 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7956 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7957 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7958
7959 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7960 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7961 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7962}
7963
7964static void tg3_timer(unsigned long __opaque)
7965{
7966 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7967
f475f163
MC		 7968 if (tp->irq_sync)
7969 goto restart_timer;
7970
f47c11ee 7971 spin_lock(&tp->lock);
1da177e4 7972
fac9b83e
DM		 7973 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7974 /* All of this garbage is because when using non-tagged
7975 * IRQ status the mailbox/status_block protocol the chip
7976 * uses with the cpu is race prone.
7977 */
898a56f8 7978 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 7979 tw32(GRC_LOCAL_CTRL,
7980 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7981 } else {
7982 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 7983 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 7984 }
1da177e4 7985
fac9b83e
DM		 7986 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7987 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7988 spin_unlock(&tp->lock);
fac9b83e
DM		 7989 schedule_work(&tp->reset_task);
7990 return;
7991 }
1da177e4
LT		 7992 }
7993
1da177e4
LT		 7994 /* This part only runs once per second. */
7995 if (!--tp->timer_counter) {
fac9b83e
DM		 7996 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7997 tg3_periodic_fetch_stats(tp);
7998
1da177e4
LT		 7999 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8000 u32 mac_stat;
8001 int phy_event;
8002
8003 mac_stat = tr32(MAC_STATUS);
8004
8005 phy_event = 0;
8006 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8007 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8008 phy_event = 1;
8009 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8010 phy_event = 1;
8011
8012 if (phy_event)
8013 tg3_setup_phy(tp, 0);
8014 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8015 u32 mac_stat = tr32(MAC_STATUS);
8016 int need_setup = 0;
8017
8018 if (netif_carrier_ok(tp->dev) &&
8019 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8020 need_setup = 1;
8021 }
8022 if (! netif_carrier_ok(tp->dev) &&
8023 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8024 MAC_STATUS_SIGNAL_DET))) {
8025 need_setup = 1;
8026 }
8027 if (need_setup) {
3d3ebe74
MC		 8028 if (!tp->serdes_counter) {
8029 tw32_f(MAC_MODE,
8030 (tp->mac_mode &
8031 ~MAC_MODE_PORT_MODE_MASK));
8032 udelay(40);
8033 tw32_f(MAC_MODE, tp->mac_mode);
8034 udelay(40);
8035 }
1da177e4
LT		 8036 tg3_setup_phy(tp, 0);
8037 }
747e8f8b
MC		 8038 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8039 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8040
8041 tp->timer_counter = tp->timer_multiplier;
8042 }
8043
130b8e4d
MC		 8044 /* Heartbeat is only sent once every 2 seconds.
8045 *
8046 * The heartbeat is to tell the ASF firmware that the host
8047 * driver is still alive. In the event that the OS crashes,
8048 * ASF needs to reset the hardware to free up the FIFO space
8049 * that may be filled with rx packets destined for the host.
8050 * If the FIFO is full, ASF will no longer function properly.
8051 *
8052 * Unintended resets have been reported on real time kernels
8053 * where the timer doesn't run on time. Netpoll will also have
8054 * same problem.
8055 *
8056 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8057 * to check the ring condition when the heartbeat is expiring
8058 * before doing the reset. This will prevent most unintended
8059 * resets.
8060 */
1da177e4 8061 if (!--tp->asf_counter) {
bc7959b2
MC		 8062 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8063 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8064 tg3_wait_for_event_ack(tp);
8065
bbadf503 8066 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8067 FWCMD_NICDRV_ALIVE3);
bbadf503 8068 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8069 /* 5 seconds timeout */
bbadf503 8070 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8071
8072 tg3_generate_fw_event(tp);
1da177e4
LT		 8073 }
8074 tp->asf_counter = tp->asf_multiplier;
8075 }
8076
f47c11ee 8077 spin_unlock(&tp->lock);
1da177e4 8078
f475f163 8079restart_timer:
1da177e4
LT		 8080 tp->timer.expires = jiffies + tp->timer_offset;
8081 add_timer(&tp->timer);
8082}
8083
4f125f42 8084static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8085{
7d12e780 8086 irq_handler_t fn;
fcfa0a32 8087 unsigned long flags;
4f125f42
MC		 8088 char *name;
8089 struct tg3_napi *tnapi = &tp->napi[irq_num];
8090
8091 if (tp->irq_cnt == 1)
8092 name = tp->dev->name;
8093 else {
8094 name = &tnapi->irq_lbl[0];
8095 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8096 name[IFNAMSIZ-1] = 0;
8097 }
fcfa0a32 8098
679563f4 8099 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8100 fn = tg3_msi;
8101 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8102 fn = tg3_msi_1shot;
1fb9df5d 8103 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8104 } else {
8105 fn = tg3_interrupt;
8106 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8107 fn = tg3_interrupt_tagged;
1fb9df5d 8108 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8109 }
4f125f42
MC		 8110
8111 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8112}
8113
7938109f
MC		 8114static int tg3_test_interrupt(struct tg3 *tp)
8115{
09943a18 8116 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8117 struct net_device *dev = tp->dev;
b16250e3 8118 int err, i, intr_ok = 0;
f6eb9b1f 8119 u32 val;
7938109f 8120
d4bc3927
MC		 8121 if (!netif_running(dev))
8122 return -ENODEV;
8123
7938109f
MC		 8124 tg3_disable_ints(tp);
8125
4f125f42 8126 free_irq(tnapi->irq_vec, tnapi);
7938109f 8127
f6eb9b1f
MC		 8128 /*
8129 * Turn off MSI one shot mode. Otherwise this test has no
8130 * observable way to know whether the interrupt was delivered.
8131 */
8132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8133 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8134 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8135 tw32(MSGINT_MODE, val);
8136 }
8137
4f125f42 8138 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8139 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8140 if (err)
8141 return err;
8142
898a56f8 8143 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8144 tg3_enable_ints(tp);
8145
8146 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8147 tnapi->coal_now);
7938109f
MC		 8148
8149 for (i = 0; i < 5; i++) {
b16250e3
MC		 8150 u32 int_mbox, misc_host_ctrl;
8151
898a56f8 8152 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8153 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8154
8155 if ((int_mbox != 0) ||
8156 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8157 intr_ok = 1;
7938109f 8158 break;
b16250e3
MC		 8159 }
8160
7938109f
MC		 8161 msleep(10);
8162 }
8163
8164 tg3_disable_ints(tp);
8165
4f125f42 8166 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8167
4f125f42 8168 err = tg3_request_irq(tp, 0);
7938109f
MC		 8169
8170 if (err)
8171 return err;
8172
f6eb9b1f
MC		 8173 if (intr_ok) {
8174 /* Reenable MSI one shot mode. */
8175 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8176 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8177 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8178 tw32(MSGINT_MODE, val);
8179 }
7938109f 8180 return 0;
f6eb9b1f 8181 }
7938109f
MC		 8182
8183 return -EIO;
8184}
8185
8186/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8187 * successfully restored
8188 */
8189static int tg3_test_msi(struct tg3 *tp)
8190{
7938109f
MC		 8191 int err;
8192 u16 pci_cmd;
8193
8194 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8195 return 0;
8196
8197 /* Turn off SERR reporting in case MSI terminates with Master
8198 * Abort.
8199 */
8200 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8201 pci_write_config_word(tp->pdev, PCI_COMMAND,
8202 pci_cmd & ~PCI_COMMAND_SERR);
8203
8204 err = tg3_test_interrupt(tp);
8205
8206 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8207
8208 if (!err)
8209 return 0;
8210
8211 /* other failures */
8212 if (err != -EIO)
8213 return err;
8214
8215 /* MSI test failed, go back to INTx mode */
8216 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8217 "switching to INTx mode. Please report this failure to "
8218 "the PCI maintainer and include system chipset information.\n",
8219 tp->dev->name);
8220
4f125f42 8221 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8222
7938109f
MC		 8223 pci_disable_msi(tp->pdev);
8224
8225 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8226
4f125f42 8227 err = tg3_request_irq(tp, 0);
7938109f
MC		 8228 if (err)
8229 return err;
8230
8231 /* Need to reset the chip because the MSI cycle may have terminated
8232 * with Master Abort.
8233 */
f47c11ee 8234 tg3_full_lock(tp, 1);
7938109f 8235
944d980e 8236 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8237 err = tg3_init_hw(tp, 1);
7938109f 8238
f47c11ee 8239 tg3_full_unlock(tp);
7938109f
MC		 8240
8241 if (err)
4f125f42 8242 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8243
8244 return err;
8245}
8246
9e9fd12d
MC		 8247static int tg3_request_firmware(struct tg3 *tp)
8248{
8249 const __be32 *fw_data;
8250
8251 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8252 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8253 tp->dev->name, tp->fw_needed);
8254 return -ENOENT;
8255 }
8256
8257 fw_data = (void *)tp->fw->data;
8258
8259 /* Firmware blob starts with version numbers, followed by
8260 * start address and _full_ length including BSS sections
8261 * (which must be longer than the actual data, of course
8262 */
8263
8264 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8265 if (tp->fw_len < (tp->fw->size - 12)) {
8266 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8267 tp->dev->name, tp->fw_len, tp->fw_needed);
8268 release_firmware(tp->fw);
8269 tp->fw = NULL;
8270 return -EINVAL;
8271 }
8272
8273 /* We no longer need firmware; we have it. */
8274 tp->fw_needed = NULL;
8275 return 0;
8276}
8277
679563f4
MC		 8278static bool tg3_enable_msix(struct tg3 *tp)
8279{
8280 int i, rc, cpus = num_online_cpus();
8281 struct msix_entry msix_ent[tp->irq_max];
8282
8283 if (cpus == 1)
8284 /* Just fallback to the simpler MSI mode. */
8285 return false;
8286
8287 /*
8288 * We want as many rx rings enabled as there are cpus.
8289 * The first MSIX vector only deals with link interrupts, etc,
8290 * so we add one to the number of vectors we are requesting.
8291 */
8292 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8293
8294 for (i = 0; i < tp->irq_max; i++) {
8295 msix_ent[i].entry = i;
8296 msix_ent[i].vector = 0;
8297 }
8298
8299 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8300 if (rc != 0) {
8301 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8302 return false;
8303 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8304 return false;
8305 printk(KERN_NOTICE
8306 "%s: Requested %d MSI-X vectors, received %d\n",
8307 tp->dev->name, tp->irq_cnt, rc);
8308 tp->irq_cnt = rc;
8309 }
8310
baf8a94a
MC		 8311 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8312
679563f4
MC		 8313 for (i = 0; i < tp->irq_max; i++)
8314 tp->napi[i].irq_vec = msix_ent[i].vector;
8315
fe5f5787
MC		 8316 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8317
679563f4
MC		 8318 return true;
8319}
8320
07b0173c
MC		 8321static void tg3_ints_init(struct tg3 *tp)
8322{
679563f4
MC		 8323 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8324 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8325 /* All MSI supporting chips should support tagged
8326 * status. Assert that this is the case.
8327 */
679563f4
MC		 8328 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8329 "Not using MSI.\n", tp->dev->name);
8330 goto defcfg;
07b0173c 8331 }
4f125f42 8332
679563f4
MC		 8333 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8334 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8335 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8336 pci_enable_msi(tp->pdev) == 0)
8337 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8338
8339 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8340 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8341 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8342 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8343 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8344 }
8345defcfg:
8346 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8347 tp->irq_cnt = 1;
8348 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8349 tp->dev->real_num_tx_queues = 1;
679563f4 8350 }
07b0173c
MC		 8351}
8352
8353static void tg3_ints_fini(struct tg3 *tp)
8354{
679563f4
MC		 8355 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8356 pci_disable_msix(tp->pdev);
8357 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8358 pci_disable_msi(tp->pdev);
8359 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8360 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8361}
8362
1da177e4
LT		 8363static int tg3_open(struct net_device *dev)
8364{
8365 struct tg3 *tp = netdev_priv(dev);
4f125f42 8366 int i, err;
1da177e4 8367
9e9fd12d
MC		 8368 if (tp->fw_needed) {
8369 err = tg3_request_firmware(tp);
8370 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8371 if (err)
8372 return err;
8373 } else if (err) {
8374 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8375 tp->dev->name);
8376 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8377 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8378 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8379 tp->dev->name);
8380 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8381 }
8382 }
8383
c49a1561
MC		 8384 netif_carrier_off(tp->dev);
8385
bc1c7567 8386 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8387 if (err)
bc1c7567 8388 return err;
2f751b67
MC		 8389
8390 tg3_full_lock(tp, 0);
bc1c7567 8391
1da177e4
LT		 8392 tg3_disable_ints(tp);
8393 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8394
f47c11ee 8395 tg3_full_unlock(tp);
1da177e4 8396
679563f4
MC		 8397 /*
8398 * Setup interrupts first so we know how
8399 * many NAPI resources to allocate
8400 */
8401 tg3_ints_init(tp);
8402
1da177e4
LT		 8403 /* The placement of this call is tied
8404 * to the setup and use of Host TX descriptors.
8405 */
8406 err = tg3_alloc_consistent(tp);
8407 if (err)
679563f4 8408 goto err_out1;
88b06bc2 8409
fed97810 8410 tg3_napi_enable(tp);
1da177e4 8411
4f125f42
MC		 8412 for (i = 0; i < tp->irq_cnt; i++) {
8413 struct tg3_napi *tnapi = &tp->napi[i];
8414 err = tg3_request_irq(tp, i);
8415 if (err) {
8416 for (i--; i >= 0; i--)
8417 free_irq(tnapi->irq_vec, tnapi);
8418 break;
8419 }
8420 }
1da177e4 8421
07b0173c 8422 if (err)
679563f4 8423 goto err_out2;
bea3348e 8424
f47c11ee 8425 tg3_full_lock(tp, 0);
1da177e4 8426
8e7a22e3 8427 err = tg3_init_hw(tp, 1);
1da177e4 8428 if (err) {
944d980e 8429 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8430 tg3_free_rings(tp);
8431 } else {
fac9b83e
DM		 8432 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8433 tp->timer_offset = HZ;
8434 else
8435 tp->timer_offset = HZ / 10;
8436
8437 BUG_ON(tp->timer_offset > HZ);
8438 tp->timer_counter = tp->timer_multiplier =
8439 (HZ / tp->timer_offset);
8440 tp->asf_counter = tp->asf_multiplier =
28fbef78 8441 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8442
8443 init_timer(&tp->timer);
8444 tp->timer.expires = jiffies + tp->timer_offset;
8445 tp->timer.data = (unsigned long) tp;
8446 tp->timer.function = tg3_timer;
1da177e4
LT		 8447 }
8448
f47c11ee 8449 tg3_full_unlock(tp);
1da177e4 8450
07b0173c 8451 if (err)
679563f4 8452 goto err_out3;
1da177e4 8453
7938109f
MC		 8454 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8455 err = tg3_test_msi(tp);
fac9b83e 8456
7938109f 8457 if (err) {
f47c11ee 8458 tg3_full_lock(tp, 0);
944d980e 8459 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8460 tg3_free_rings(tp);
f47c11ee 8461 tg3_full_unlock(tp);
7938109f 8462
679563f4 8463 goto err_out2;
7938109f 8464 }
fcfa0a32 8465
f6eb9b1f
MC		 8466 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8467 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8468 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8469 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8470
f6eb9b1f
MC		 8471 tw32(PCIE_TRANSACTION_CFG,
8472 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8473 }
7938109f
MC		 8474 }
8475
b02fd9e3
MC		 8476 tg3_phy_start(tp);
8477
f47c11ee 8478 tg3_full_lock(tp, 0);
1da177e4 8479
7938109f
MC		 8480 add_timer(&tp->timer);
8481 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8482 tg3_enable_ints(tp);
8483
f47c11ee 8484 tg3_full_unlock(tp);
1da177e4 8485
fe5f5787 8486 netif_tx_start_all_queues(dev);
1da177e4
LT		 8487
8488 return 0;
07b0173c 8489
679563f4 8490err_out3:
4f125f42
MC		 8491 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8492 struct tg3_napi *tnapi = &tp->napi[i];
8493 free_irq(tnapi->irq_vec, tnapi);
8494 }
07b0173c 8495
679563f4 8496err_out2:
fed97810 8497 tg3_napi_disable(tp);
07b0173c 8498 tg3_free_consistent(tp);
679563f4
MC		 8499
8500err_out1:
8501 tg3_ints_fini(tp);
07b0173c 8502 return err;
1da177e4
LT		 8503}
8504
8505#if 0
8506/*static*/ void tg3_dump_state(struct tg3 *tp)
8507{
8508 u32 val32, val32_2, val32_3, val32_4, val32_5;
8509 u16 val16;
8510 int i;
898a56f8 8511 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8512
8513 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8514 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8515 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8516 val16, val32);
8517
8518 /* MAC block */
8519 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8520 tr32(MAC_MODE), tr32(MAC_STATUS));
8521 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8522 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8523 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8524 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8525 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8526 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8527
8528 /* Send data initiator control block */
8529 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8530 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8531 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8532 tr32(SNDDATAI_STATSCTRL));
8533
8534 /* Send data completion control block */
8535 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8536
8537 /* Send BD ring selector block */
8538 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8539 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8540
8541 /* Send BD initiator control block */
8542 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8543 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8544
8545 /* Send BD completion control block */
8546 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8547
8548 /* Receive list placement control block */
8549 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8550 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8551 printk(" RCVLPC_STATSCTRL[%08x]\n",
8552 tr32(RCVLPC_STATSCTRL));
8553
8554 /* Receive data and receive BD initiator control block */
8555 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8556 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8557
8558 /* Receive data completion control block */
8559 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8560 tr32(RCVDCC_MODE));
8561
8562 /* Receive BD initiator control block */
8563 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8564 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8565
8566 /* Receive BD completion control block */
8567 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8568 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8569
8570 /* Receive list selector control block */
8571 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8572 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8573
8574 /* Mbuf cluster free block */
8575 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8576 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8577
8578 /* Host coalescing control block */
8579 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8580 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8581 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8582 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8583 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8584 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8585 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8586 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8587 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8588 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8589 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8590 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8591
8592 /* Memory arbiter control block */
8593 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8594 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8595
8596 /* Buffer manager control block */
8597 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8598 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8599 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8600 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8601 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8602 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8603 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8604 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8605
8606 /* Read DMA control block */
8607 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8608 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8609
8610 /* Write DMA control block */
8611 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8612 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8613
8614 /* DMA completion block */
8615 printk("DEBUG: DMAC_MODE[%08x]\n",
8616 tr32(DMAC_MODE));
8617
8618 /* GRC block */
8619 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8620 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8621 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8622 tr32(GRC_LOCAL_CTRL));
8623
8624 /* TG3_BDINFOs */
8625 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8626 tr32(RCVDBDI_JUMBO_BD + 0x0),
8627 tr32(RCVDBDI_JUMBO_BD + 0x4),
8628 tr32(RCVDBDI_JUMBO_BD + 0x8),
8629 tr32(RCVDBDI_JUMBO_BD + 0xc));
8630 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8631 tr32(RCVDBDI_STD_BD + 0x0),
8632 tr32(RCVDBDI_STD_BD + 0x4),
8633 tr32(RCVDBDI_STD_BD + 0x8),
8634 tr32(RCVDBDI_STD_BD + 0xc));
8635 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8636 tr32(RCVDBDI_MINI_BD + 0x0),
8637 tr32(RCVDBDI_MINI_BD + 0x4),
8638 tr32(RCVDBDI_MINI_BD + 0x8),
8639 tr32(RCVDBDI_MINI_BD + 0xc));
8640
8641 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8642 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8643 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8644 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8645 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8646 val32, val32_2, val32_3, val32_4);
8647
8648 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8649 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8650 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8651 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8652 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8653 val32, val32_2, val32_3, val32_4);
8654
8655 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8656 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8657 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8658 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8659 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8660 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8661 val32, val32_2, val32_3, val32_4, val32_5);
8662
8663 /* SW status block */
898a56f8
MC		 8664 printk(KERN_DEBUG
8665 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8666 sblk->status,
8667 sblk->status_tag,
8668 sblk->rx_jumbo_consumer,
8669 sblk->rx_consumer,
8670 sblk->rx_mini_consumer,
8671 sblk->idx[0].rx_producer,
8672 sblk->idx[0].tx_consumer);
1da177e4
LT		 8673
8674 /* SW statistics block */
8675 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8676 ((u32 *)tp->hw_stats)[0],
8677 ((u32 *)tp->hw_stats)[1],
8678 ((u32 *)tp->hw_stats)[2],
8679 ((u32 *)tp->hw_stats)[3]);
8680
8681 /* Mailboxes */
8682 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8683 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8684 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8685 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8686 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8687
8688 /* NIC side send descriptors. */
8689 for (i = 0; i < 6; i++) {
8690 unsigned long txd;
8691
8692 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8693 + (i * sizeof(struct tg3_tx_buffer_desc));
8694 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8695 i,
8696 readl(txd + 0x0), readl(txd + 0x4),
8697 readl(txd + 0x8), readl(txd + 0xc));
8698 }
8699
8700 /* NIC side RX descriptors. */
8701 for (i = 0; i < 6; i++) {
8702 unsigned long rxd;
8703
8704 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8705 + (i * sizeof(struct tg3_rx_buffer_desc));
8706 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8707 i,
8708 readl(rxd + 0x0), readl(rxd + 0x4),
8709 readl(rxd + 0x8), readl(rxd + 0xc));
8710 rxd += (4 * sizeof(u32));
8711 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8712 i,
8713 readl(rxd + 0x0), readl(rxd + 0x4),
8714 readl(rxd + 0x8), readl(rxd + 0xc));
8715 }
8716
8717 for (i = 0; i < 6; i++) {
8718 unsigned long rxd;
8719
8720 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8721 + (i * sizeof(struct tg3_rx_buffer_desc));
8722 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8723 i,
8724 readl(rxd + 0x0), readl(rxd + 0x4),
8725 readl(rxd + 0x8), readl(rxd + 0xc));
8726 rxd += (4 * sizeof(u32));
8727 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8728 i,
8729 readl(rxd + 0x0), readl(rxd + 0x4),
8730 readl(rxd + 0x8), readl(rxd + 0xc));
8731 }
8732}
8733#endif
8734
8735static struct net_device_stats *tg3_get_stats(struct net_device *);
8736static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8737
8738static int tg3_close(struct net_device *dev)
8739{
4f125f42 8740 int i;
1da177e4
LT		 8741 struct tg3 *tp = netdev_priv(dev);
8742
fed97810 8743 tg3_napi_disable(tp);
28e53bdd 8744 cancel_work_sync(&tp->reset_task);
7faa006f 8745
fe5f5787 8746 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8747
8748 del_timer_sync(&tp->timer);
8749
24bb4fb6
MC		 8750 tg3_phy_stop(tp);
8751
f47c11ee 8752 tg3_full_lock(tp, 1);
1da177e4
LT		 8753#if 0
8754 tg3_dump_state(tp);
8755#endif
8756
8757 tg3_disable_ints(tp);
8758
944d980e 8759 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8760 tg3_free_rings(tp);
5cf64b8a 8761 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8762
f47c11ee 8763 tg3_full_unlock(tp);
1da177e4 8764
4f125f42
MC		 8765 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8766 struct tg3_napi *tnapi = &tp->napi[i];
8767 free_irq(tnapi->irq_vec, tnapi);
8768 }
07b0173c
MC		 8769
8770 tg3_ints_fini(tp);
1da177e4
LT		 8771
8772 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8773 sizeof(tp->net_stats_prev));
8774 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8775 sizeof(tp->estats_prev));
8776
8777 tg3_free_consistent(tp);
8778
bc1c7567
MC		 8779 tg3_set_power_state(tp, PCI_D3hot);
8780
8781 netif_carrier_off(tp->dev);
8782
1da177e4
LT		 8783 return 0;
8784}
8785
8786static inline unsigned long get_stat64(tg3_stat64_t *val)
8787{
8788 unsigned long ret;
8789
8790#if (BITS_PER_LONG == 32)
8791 ret = val->low;
8792#else
8793 ret = ((u64)val->high << 32) | ((u64)val->low);
8794#endif
8795 return ret;
8796}
8797
816f8b86
SB		 8798static inline u64 get_estat64(tg3_stat64_t *val)
8799{
8800 return ((u64)val->high << 32) | ((u64)val->low);
8801}
8802
1da177e4
LT		 8803static unsigned long calc_crc_errors(struct tg3 *tp)
8804{
8805 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8806
8807 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8808 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8809 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8810 u32 val;
8811
f47c11ee 8812 spin_lock_bh(&tp->lock);
569a5df8
MC		 8813 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8814 tg3_writephy(tp, MII_TG3_TEST1,
8815 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8816 tg3_readphy(tp, 0x14, &val);
8817 } else
8818 val = 0;
f47c11ee 8819 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8820
8821 tp->phy_crc_errors += val;
8822
8823 return tp->phy_crc_errors;
8824 }
8825
8826 return get_stat64(&hw_stats->rx_fcs_errors);
8827}
8828
8829#define ESTAT_ADD(member) \
8830 estats->member = old_estats->member + \
816f8b86 8831 get_estat64(&hw_stats->member)
1da177e4
LT		 8832
8833static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8834{
8835 struct tg3_ethtool_stats *estats = &tp->estats;
8836 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8837 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8838
8839 if (!hw_stats)
8840 return old_estats;
8841
8842 ESTAT_ADD(rx_octets);
8843 ESTAT_ADD(rx_fragments);
8844 ESTAT_ADD(rx_ucast_packets);
8845 ESTAT_ADD(rx_mcast_packets);
8846 ESTAT_ADD(rx_bcast_packets);
8847 ESTAT_ADD(rx_fcs_errors);
8848 ESTAT_ADD(rx_align_errors);
8849 ESTAT_ADD(rx_xon_pause_rcvd);
8850 ESTAT_ADD(rx_xoff_pause_rcvd);
8851 ESTAT_ADD(rx_mac_ctrl_rcvd);
8852 ESTAT_ADD(rx_xoff_entered);
8853 ESTAT_ADD(rx_frame_too_long_errors);
8854 ESTAT_ADD(rx_jabbers);
8855 ESTAT_ADD(rx_undersize_packets);
8856 ESTAT_ADD(rx_in_length_errors);
8857 ESTAT_ADD(rx_out_length_errors);
8858 ESTAT_ADD(rx_64_or_less_octet_packets);
8859 ESTAT_ADD(rx_65_to_127_octet_packets);
8860 ESTAT_ADD(rx_128_to_255_octet_packets);
8861 ESTAT_ADD(rx_256_to_511_octet_packets);
8862 ESTAT_ADD(rx_512_to_1023_octet_packets);
8863 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8864 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8865 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8866 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8867 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8868
8869 ESTAT_ADD(tx_octets);
8870 ESTAT_ADD(tx_collisions);
8871 ESTAT_ADD(tx_xon_sent);
8872 ESTAT_ADD(tx_xoff_sent);
8873 ESTAT_ADD(tx_flow_control);
8874 ESTAT_ADD(tx_mac_errors);
8875 ESTAT_ADD(tx_single_collisions);
8876 ESTAT_ADD(tx_mult_collisions);
8877 ESTAT_ADD(tx_deferred);
8878 ESTAT_ADD(tx_excessive_collisions);
8879 ESTAT_ADD(tx_late_collisions);
8880 ESTAT_ADD(tx_collide_2times);
8881 ESTAT_ADD(tx_collide_3times);
8882 ESTAT_ADD(tx_collide_4times);
8883 ESTAT_ADD(tx_collide_5times);
8884 ESTAT_ADD(tx_collide_6times);
8885 ESTAT_ADD(tx_collide_7times);
8886 ESTAT_ADD(tx_collide_8times);
8887 ESTAT_ADD(tx_collide_9times);
8888 ESTAT_ADD(tx_collide_10times);
8889 ESTAT_ADD(tx_collide_11times);
8890 ESTAT_ADD(tx_collide_12times);
8891 ESTAT_ADD(tx_collide_13times);
8892 ESTAT_ADD(tx_collide_14times);
8893 ESTAT_ADD(tx_collide_15times);
8894 ESTAT_ADD(tx_ucast_packets);
8895 ESTAT_ADD(tx_mcast_packets);
8896 ESTAT_ADD(tx_bcast_packets);
8897 ESTAT_ADD(tx_carrier_sense_errors);
8898 ESTAT_ADD(tx_discards);
8899 ESTAT_ADD(tx_errors);
8900
8901 ESTAT_ADD(dma_writeq_full);
8902 ESTAT_ADD(dma_write_prioq_full);
8903 ESTAT_ADD(rxbds_empty);
8904 ESTAT_ADD(rx_discards);
8905 ESTAT_ADD(rx_errors);
8906 ESTAT_ADD(rx_threshold_hit);
8907
8908 ESTAT_ADD(dma_readq_full);
8909 ESTAT_ADD(dma_read_prioq_full);
8910 ESTAT_ADD(tx_comp_queue_full);
8911
8912 ESTAT_ADD(ring_set_send_prod_index);
8913 ESTAT_ADD(ring_status_update);
8914 ESTAT_ADD(nic_irqs);
8915 ESTAT_ADD(nic_avoided_irqs);
8916 ESTAT_ADD(nic_tx_threshold_hit);
8917
8918 return estats;
8919}
8920
8921static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8922{
8923 struct tg3 *tp = netdev_priv(dev);
8924 struct net_device_stats *stats = &tp->net_stats;
8925 struct net_device_stats *old_stats = &tp->net_stats_prev;
8926 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8927
8928 if (!hw_stats)
8929 return old_stats;
8930
8931 stats->rx_packets = old_stats->rx_packets +
8932 get_stat64(&hw_stats->rx_ucast_packets) +
8933 get_stat64(&hw_stats->rx_mcast_packets) +
8934 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8935
1da177e4
LT		 8936 stats->tx_packets = old_stats->tx_packets +
8937 get_stat64(&hw_stats->tx_ucast_packets) +
8938 get_stat64(&hw_stats->tx_mcast_packets) +
8939 get_stat64(&hw_stats->tx_bcast_packets);
8940
8941 stats->rx_bytes = old_stats->rx_bytes +
8942 get_stat64(&hw_stats->rx_octets);
8943 stats->tx_bytes = old_stats->tx_bytes +
8944 get_stat64(&hw_stats->tx_octets);
8945
8946 stats->rx_errors = old_stats->rx_errors +
4f63b877 8947 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8948 stats->tx_errors = old_stats->tx_errors +
8949 get_stat64(&hw_stats->tx_errors) +
8950 get_stat64(&hw_stats->tx_mac_errors) +
8951 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8952 get_stat64(&hw_stats->tx_discards);
8953
8954 stats->multicast = old_stats->multicast +
8955 get_stat64(&hw_stats->rx_mcast_packets);
8956 stats->collisions = old_stats->collisions +
8957 get_stat64(&hw_stats->tx_collisions);
8958
8959 stats->rx_length_errors = old_stats->rx_length_errors +
8960 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8961 get_stat64(&hw_stats->rx_undersize_packets);
8962
8963 stats->rx_over_errors = old_stats->rx_over_errors +
8964 get_stat64(&hw_stats->rxbds_empty);
8965 stats->rx_frame_errors = old_stats->rx_frame_errors +
8966 get_stat64(&hw_stats->rx_align_errors);
8967 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8968 get_stat64(&hw_stats->tx_discards);
8969 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8970 get_stat64(&hw_stats->tx_carrier_sense_errors);
8971
8972 stats->rx_crc_errors = old_stats->rx_crc_errors +
8973 calc_crc_errors(tp);
8974
4f63b877
JL		 8975 stats->rx_missed_errors = old_stats->rx_missed_errors +
8976 get_stat64(&hw_stats->rx_discards);
8977
1da177e4
LT		 8978 return stats;
8979}
8980
8981static inline u32 calc_crc(unsigned char *buf, int len)
8982{
8983 u32 reg;
8984 u32 tmp;
8985 int j, k;
8986
8987 reg = 0xffffffff;
8988
8989 for (j = 0; j < len; j++) {
8990 reg ^= buf[j];
8991
8992 for (k = 0; k < 8; k++) {
8993 tmp = reg & 0x01;
8994
8995 reg >>= 1;
8996
8997 if (tmp) {
8998 reg ^= 0xedb88320;
8999 }
9000 }
9001 }
9002
9003 return ~reg;
9004}
9005
9006static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9007{
9008 /* accept or reject all multicast frames */
9009 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9010 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9011 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9012 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9013}
9014
9015static void __tg3_set_rx_mode(struct net_device *dev)
9016{
9017 struct tg3 *tp = netdev_priv(dev);
9018 u32 rx_mode;
9019
9020 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9021 RX_MODE_KEEP_VLAN_TAG);
9022
9023 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9024 * flag clear.
9025 */
9026#if TG3_VLAN_TAG_USED
9027 if (!tp->vlgrp &&
9028 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9029 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9030#else
9031 /* By definition, VLAN is disabled always in this
9032 * case.
9033 */
9034 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9035 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9036#endif
9037
9038 if (dev->flags & IFF_PROMISC) {
9039 /* Promiscuous mode. */
9040 rx_mode |= RX_MODE_PROMISC;
9041 } else if (dev->flags & IFF_ALLMULTI) {
9042 /* Accept all multicast. */
9043 tg3_set_multi (tp, 1);
9044 } else if (dev->mc_count < 1) {
9045 /* Reject all multicast. */
9046 tg3_set_multi (tp, 0);
9047 } else {
9048 /* Accept one or more multicast(s). */
9049 struct dev_mc_list *mclist;
9050 unsigned int i;
9051 u32 mc_filter[4] = { 0, };
9052 u32 regidx;
9053 u32 bit;
9054 u32 crc;
9055
9056 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9057 i++, mclist = mclist->next) {
9058
9059 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9060 bit = ~crc & 0x7f;
9061 regidx = (bit & 0x60) >> 5;
9062 bit &= 0x1f;
9063 mc_filter[regidx] |= (1 << bit);
9064 }
9065
9066 tw32(MAC_HASH_REG_0, mc_filter[0]);
9067 tw32(MAC_HASH_REG_1, mc_filter[1]);
9068 tw32(MAC_HASH_REG_2, mc_filter[2]);
9069 tw32(MAC_HASH_REG_3, mc_filter[3]);
9070 }
9071
9072 if (rx_mode != tp->rx_mode) {
9073 tp->rx_mode = rx_mode;
9074 tw32_f(MAC_RX_MODE, rx_mode);
9075 udelay(10);
9076 }
9077}
9078
9079static void tg3_set_rx_mode(struct net_device *dev)
9080{
9081 struct tg3 *tp = netdev_priv(dev);
9082
e75f7c90
MC		 9083 if (!netif_running(dev))
9084 return;
9085
f47c11ee 9086 tg3_full_lock(tp, 0);
1da177e4 9087 __tg3_set_rx_mode(dev);
f47c11ee 9088 tg3_full_unlock(tp);
1da177e4
LT		 9089}
9090
9091#define TG3_REGDUMP_LEN (32 * 1024)
9092
9093static int tg3_get_regs_len(struct net_device *dev)
9094{
9095 return TG3_REGDUMP_LEN;
9096}
9097
9098static void tg3_get_regs(struct net_device *dev,
9099 struct ethtool_regs *regs, void *_p)
9100{
9101 u32 *p = _p;
9102 struct tg3 *tp = netdev_priv(dev);
9103 u8 *orig_p = _p;
9104 int i;
9105
9106 regs->version = 0;
9107
9108 memset(p, 0, TG3_REGDUMP_LEN);
9109
bc1c7567
MC		 9110 if (tp->link_config.phy_is_low_power)
9111 return;
9112
f47c11ee 9113 tg3_full_lock(tp, 0);
1da177e4
LT		 9114
9115#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9116#define GET_REG32_LOOP(base,len) \
9117do { p = (u32 *)(orig_p + (base)); \
9118 for (i = 0; i < len; i += 4) \
9119 __GET_REG32((base) + i); \
9120} while (0)
9121#define GET_REG32_1(reg) \
9122do { p = (u32 *)(orig_p + (reg)); \
9123 __GET_REG32((reg)); \
9124} while (0)
9125
9126 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9127 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9128 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9129 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9130 GET_REG32_1(SNDDATAC_MODE);
9131 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9132 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9133 GET_REG32_1(SNDBDC_MODE);
9134 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9135 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9136 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9137 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9138 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9139 GET_REG32_1(RCVDCC_MODE);
9140 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9141 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9142 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9143 GET_REG32_1(MBFREE_MODE);
9144 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9145 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9146 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9147 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9148 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9149 GET_REG32_1(RX_CPU_MODE);
9150 GET_REG32_1(RX_CPU_STATE);
9151 GET_REG32_1(RX_CPU_PGMCTR);
9152 GET_REG32_1(RX_CPU_HWBKPT);
9153 GET_REG32_1(TX_CPU_MODE);
9154 GET_REG32_1(TX_CPU_STATE);
9155 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9156 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9157 GET_REG32_LOOP(FTQ_RESET, 0x120);
9158 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9159 GET_REG32_1(DMAC_MODE);
9160 GET_REG32_LOOP(GRC_MODE, 0x4c);
9161 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9162 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9163
9164#undef __GET_REG32
9165#undef GET_REG32_LOOP
9166#undef GET_REG32_1
9167
f47c11ee 9168 tg3_full_unlock(tp);
1da177e4
LT		 9169}
9170
9171static int tg3_get_eeprom_len(struct net_device *dev)
9172{
9173 struct tg3 *tp = netdev_priv(dev);
9174
9175 return tp->nvram_size;
9176}
9177
1da177e4
LT		 9178static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9179{
9180 struct tg3 *tp = netdev_priv(dev);
9181 int ret;
9182 u8 *pd;
b9fc7dc5 9183 u32 i, offset, len, b_offset, b_count;
a9dc529d 9184 __be32 val;
1da177e4 9185
df259d8c
MC		 9186 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9187 return -EINVAL;
9188
bc1c7567
MC		 9189 if (tp->link_config.phy_is_low_power)
9190 return -EAGAIN;
9191
1da177e4
LT		 9192 offset = eeprom->offset;
9193 len = eeprom->len;
9194 eeprom->len = 0;
9195
9196 eeprom->magic = TG3_EEPROM_MAGIC;
9197
9198 if (offset & 3) {
9199 /* adjustments to start on required 4 byte boundary */
9200 b_offset = offset & 3;
9201 b_count = 4 - b_offset;
9202 if (b_count > len) {
9203 /* i.e. offset=1 len=2 */
9204 b_count = len;
9205 }
a9dc529d 9206 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9207 if (ret)
9208 return ret;
1da177e4
LT		 9209 memcpy(data, ((char*)&val) + b_offset, b_count);
9210 len -= b_count;
9211 offset += b_count;
9212 eeprom->len += b_count;
9213 }
9214
9215 /* read bytes upto the last 4 byte boundary */
9216 pd = &data[eeprom->len];
9217 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9218 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9219 if (ret) {
9220 eeprom->len += i;
9221 return ret;
9222 }
1da177e4
LT		 9223 memcpy(pd + i, &val, 4);
9224 }
9225 eeprom->len += i;
9226
9227 if (len & 3) {
9228 /* read last bytes not ending on 4 byte boundary */
9229 pd = &data[eeprom->len];
9230 b_count = len & 3;
9231 b_offset = offset + len - b_count;
a9dc529d 9232 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9233 if (ret)
9234 return ret;
b9fc7dc5 9235 memcpy(pd, &val, b_count);
1da177e4
LT		 9236 eeprom->len += b_count;
9237 }
9238 return 0;
9239}
9240
6aa20a22 9241static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9242
9243static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9244{
9245 struct tg3 *tp = netdev_priv(dev);
9246 int ret;
b9fc7dc5 9247 u32 offset, len, b_offset, odd_len;
1da177e4 9248 u8 *buf;
a9dc529d 9249 __be32 start, end;
1da177e4 9250
bc1c7567
MC		 9251 if (tp->link_config.phy_is_low_power)
9252 return -EAGAIN;
9253
df259d8c
MC		 9254 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9255 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9256 return -EINVAL;
9257
9258 offset = eeprom->offset;
9259 len = eeprom->len;
9260
9261 if ((b_offset = (offset & 3))) {
9262 /* adjustments to start on required 4 byte boundary */
a9dc529d 9263 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9264 if (ret)
9265 return ret;
1da177e4
LT		 9266 len += b_offset;
9267 offset &= ~3;
1c8594b4
MC		 9268 if (len < 4)
9269 len = 4;
1da177e4
LT		 9270 }
9271
9272 odd_len = 0;
1c8594b4 9273 if (len & 3) {
1da177e4
LT		 9274 /* adjustments to end on required 4 byte boundary */
9275 odd_len = 1;
9276 len = (len + 3) & ~3;
a9dc529d 9277 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9278 if (ret)
9279 return ret;
1da177e4
LT		 9280 }
9281
9282 buf = data;
9283 if (b_offset || odd_len) {
9284 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9285 if (!buf)
1da177e4
LT		 9286 return -ENOMEM;
9287 if (b_offset)
9288 memcpy(buf, &start, 4);
9289 if (odd_len)
9290 memcpy(buf+len-4, &end, 4);
9291 memcpy(buf + b_offset, data, eeprom->len);
9292 }
9293
9294 ret = tg3_nvram_write_block(tp, offset, len, buf);
9295
9296 if (buf != data)
9297 kfree(buf);
9298
9299 return ret;
9300}
9301
9302static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9303{
b02fd9e3
MC		 9304 struct tg3 *tp = netdev_priv(dev);
9305
9306 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9307 struct phy_device *phydev;
b02fd9e3
MC		 9308 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9309 return -EAGAIN;
3f0e3ad7
MC		 9310 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9311 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9312 }
6aa20a22 9313
1da177e4
LT		 9314 cmd->supported = (SUPPORTED_Autoneg);
9315
9316 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9317 cmd->supported |= (SUPPORTED_1000baseT_Half |
9318 SUPPORTED_1000baseT_Full);
9319
ef348144 9320 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9321 cmd->supported |= (SUPPORTED_100baseT_Half |
9322 SUPPORTED_100baseT_Full |
9323 SUPPORTED_10baseT_Half |
9324 SUPPORTED_10baseT_Full |
3bebab59 9325 SUPPORTED_TP);
ef348144
KK		 9326 cmd->port = PORT_TP;
9327 } else {
1da177e4 9328 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9329 cmd->port = PORT_FIBRE;
9330 }
6aa20a22 9331
1da177e4
LT		 9332 cmd->advertising = tp->link_config.advertising;
9333 if (netif_running(dev)) {
9334 cmd->speed = tp->link_config.active_speed;
9335 cmd->duplex = tp->link_config.active_duplex;
9336 }
882e9793 9337 cmd->phy_address = tp->phy_addr;
7e5856bd 9338 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9339 cmd->autoneg = tp->link_config.autoneg;
9340 cmd->maxtxpkt = 0;
9341 cmd->maxrxpkt = 0;
9342 return 0;
9343}
6aa20a22 9344
1da177e4
LT		 9345static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9346{
9347 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9348
b02fd9e3 9349 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9350 struct phy_device *phydev;
b02fd9e3
MC		 9351 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9352 return -EAGAIN;
3f0e3ad7
MC		 9353 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9354 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9355 }
9356
7e5856bd
MC		 9357 if (cmd->autoneg != AUTONEG_ENABLE &&
9358 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9359 return -EINVAL;
7e5856bd
MC		 9360
9361 if (cmd->autoneg == AUTONEG_DISABLE &&
9362 cmd->duplex != DUPLEX_FULL &&
9363 cmd->duplex != DUPLEX_HALF)
37ff238d 9364 return -EINVAL;
1da177e4 9365
7e5856bd
MC		 9366 if (cmd->autoneg == AUTONEG_ENABLE) {
9367 u32 mask = ADVERTISED_Autoneg |
9368 ADVERTISED_Pause |
9369 ADVERTISED_Asym_Pause;
9370
9371 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9372 mask |= ADVERTISED_1000baseT_Half |
9373 ADVERTISED_1000baseT_Full;
9374
9375 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9376 mask |= ADVERTISED_100baseT_Half |
9377 ADVERTISED_100baseT_Full |
9378 ADVERTISED_10baseT_Half |
9379 ADVERTISED_10baseT_Full |
9380 ADVERTISED_TP;
9381 else
9382 mask |= ADVERTISED_FIBRE;
9383
9384 if (cmd->advertising & ~mask)
9385 return -EINVAL;
9386
9387 mask &= (ADVERTISED_1000baseT_Half |
9388 ADVERTISED_1000baseT_Full |
9389 ADVERTISED_100baseT_Half |
9390 ADVERTISED_100baseT_Full |
9391 ADVERTISED_10baseT_Half |
9392 ADVERTISED_10baseT_Full);
9393
9394 cmd->advertising &= mask;
9395 } else {
9396 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9397 if (cmd->speed != SPEED_1000)
9398 return -EINVAL;
9399
9400 if (cmd->duplex != DUPLEX_FULL)
9401 return -EINVAL;
9402 } else {
9403 if (cmd->speed != SPEED_100 &&
9404 cmd->speed != SPEED_10)
9405 return -EINVAL;
9406 }
9407 }
9408
f47c11ee 9409 tg3_full_lock(tp, 0);
1da177e4
LT		 9410
9411 tp->link_config.autoneg = cmd->autoneg;
9412 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9413 tp->link_config.advertising = (cmd->advertising |
9414 ADVERTISED_Autoneg);
1da177e4
LT		 9415 tp->link_config.speed = SPEED_INVALID;
9416 tp->link_config.duplex = DUPLEX_INVALID;
9417 } else {
9418 tp->link_config.advertising = 0;
9419 tp->link_config.speed = cmd->speed;
9420 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9421 }
6aa20a22 9422
24fcad6b
MC		 9423 tp->link_config.orig_speed = tp->link_config.speed;
9424 tp->link_config.orig_duplex = tp->link_config.duplex;
9425 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9426
1da177e4
LT		 9427 if (netif_running(dev))
9428 tg3_setup_phy(tp, 1);
9429
f47c11ee 9430 tg3_full_unlock(tp);
6aa20a22 9431
1da177e4
LT		 9432 return 0;
9433}
6aa20a22 9434
1da177e4
LT		 9435static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9436{
9437 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9438
1da177e4
LT		 9439 strcpy(info->driver, DRV_MODULE_NAME);
9440 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9441 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9442 strcpy(info->bus_info, pci_name(tp->pdev));
9443}
6aa20a22 9444
1da177e4
LT		 9445static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9446{
9447 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9448
12dac075
RW		 9449 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9450 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9451 wol->supported = WAKE_MAGIC;
9452 else
9453 wol->supported = 0;
1da177e4 9454 wol->wolopts = 0;
05ac4cb7
MC		 9455 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9456 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9457 wol->wolopts = WAKE_MAGIC;
9458 memset(&wol->sopass, 0, sizeof(wol->sopass));
9459}
6aa20a22 9460
1da177e4
LT		 9461static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9462{
9463 struct tg3 *tp = netdev_priv(dev);
12dac075 9464 struct device *dp = &tp->pdev->dev;
6aa20a22 9465
1da177e4
LT		 9466 if (wol->wolopts & ~WAKE_MAGIC)
9467 return -EINVAL;
9468 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9469 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9470 return -EINVAL;
6aa20a22 9471
f47c11ee 9472 spin_lock_bh(&tp->lock);
12dac075 9473 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9474 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9475 device_set_wakeup_enable(dp, true);
9476 } else {
1da177e4 9477 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9478 device_set_wakeup_enable(dp, false);
9479 }
f47c11ee 9480 spin_unlock_bh(&tp->lock);
6aa20a22 9481
1da177e4
LT		 9482 return 0;
9483}
6aa20a22 9484
1da177e4
LT		 9485static u32 tg3_get_msglevel(struct net_device *dev)
9486{
9487 struct tg3 *tp = netdev_priv(dev);
9488 return tp->msg_enable;
9489}
6aa20a22 9490
1da177e4
LT		 9491static void tg3_set_msglevel(struct net_device *dev, u32 value)
9492{
9493 struct tg3 *tp = netdev_priv(dev);
9494 tp->msg_enable = value;
9495}
6aa20a22 9496
1da177e4
LT		 9497static int tg3_set_tso(struct net_device *dev, u32 value)
9498{
9499 struct tg3 *tp = netdev_priv(dev);
9500
9501 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9502 if (value)
9503 return -EINVAL;
9504 return 0;
9505 }
027455ad
MC		 9506 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9507 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9508 if (value) {
b0026624 9509 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9511 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9512 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9513 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 9514 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9515 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6
MC		 9516 dev->features |= NETIF_F_TSO_ECN;
9517 } else
9518 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9519 }
1da177e4
LT		 9520 return ethtool_op_set_tso(dev, value);
9521}
6aa20a22 9522
1da177e4
LT		 9523static int tg3_nway_reset(struct net_device *dev)
9524{
9525 struct tg3 *tp = netdev_priv(dev);
1da177e4 9526 int r;
6aa20a22 9527
1da177e4
LT		 9528 if (!netif_running(dev))
9529 return -EAGAIN;
9530
c94e3941
MC		 9531 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9532 return -EINVAL;
9533
b02fd9e3
MC		 9534 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9535 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9536 return -EAGAIN;
3f0e3ad7 9537 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9538 } else {
9539 u32 bmcr;
9540
9541 spin_lock_bh(&tp->lock);
9542 r = -EINVAL;
9543 tg3_readphy(tp, MII_BMCR, &bmcr);
9544 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9545 ((bmcr & BMCR_ANENABLE) ||
9546 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9547 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9548 BMCR_ANENABLE);
9549 r = 0;
9550 }
9551 spin_unlock_bh(&tp->lock);
1da177e4 9552 }
6aa20a22 9553
1da177e4
LT		 9554 return r;
9555}
6aa20a22 9556
1da177e4
LT		 9557static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9558{
9559 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9560
1da177e4
LT		 9561 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9562 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9563 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9564 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9565 else
9566 ering->rx_jumbo_max_pending = 0;
9567
9568 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9569
9570 ering->rx_pending = tp->rx_pending;
9571 ering->rx_mini_pending = 0;
4f81c32b
MC		 9572 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9573 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9574 else
9575 ering->rx_jumbo_pending = 0;
9576
f3f3f27e 9577 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9578}
6aa20a22 9579
1da177e4
LT		 9580static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9581{
9582 struct tg3 *tp = netdev_priv(dev);
646c9edd 9583 int i, irq_sync = 0, err = 0;
6aa20a22 9584
1da177e4
LT		 9585 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9586 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9587 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9588 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9589 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9590 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9591 return -EINVAL;
6aa20a22 9592
bbe832c0 9593 if (netif_running(dev)) {
b02fd9e3 9594 tg3_phy_stop(tp);
1da177e4 9595 tg3_netif_stop(tp);
bbe832c0
MC		 9596 irq_sync = 1;
9597 }
1da177e4 9598
bbe832c0 9599 tg3_full_lock(tp, irq_sync);
6aa20a22 9600
1da177e4
LT		 9601 tp->rx_pending = ering->rx_pending;
9602
9603 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9604 tp->rx_pending > 63)
9605 tp->rx_pending = 63;
9606 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9607
9608 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9609 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9610
9611 if (netif_running(dev)) {
944d980e 9612 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9613 err = tg3_restart_hw(tp, 1);
9614 if (!err)
9615 tg3_netif_start(tp);
1da177e4
LT		 9616 }
9617
f47c11ee 9618 tg3_full_unlock(tp);
6aa20a22 9619
b02fd9e3
MC		 9620 if (irq_sync && !err)
9621 tg3_phy_start(tp);
9622
b9ec6c1b 9623 return err;
1da177e4 9624}
6aa20a22 9625
1da177e4
LT		 9626static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9627{
9628 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9629
1da177e4 9630 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9631
e18ce346 9632 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9633 epause->rx_pause = 1;
9634 else
9635 epause->rx_pause = 0;
9636
e18ce346 9637 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9638 epause->tx_pause = 1;
9639 else
9640 epause->tx_pause = 0;
1da177e4 9641}
6aa20a22 9642
1da177e4
LT		 9643static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9644{
9645 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9646 int err = 0;
6aa20a22 9647
b02fd9e3
MC		 9648 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9649 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9650 return -EAGAIN;
1da177e4 9651
b02fd9e3
MC		 9652 if (epause->autoneg) {
9653 u32 newadv;
9654 struct phy_device *phydev;
f47c11ee 9655
3f0e3ad7 9656 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 9657
b02fd9e3
MC		 9658 if (epause->rx_pause) {
9659 if (epause->tx_pause)
9660 newadv = ADVERTISED_Pause;
9661 else
9662 newadv = ADVERTISED_Pause |
9663 ADVERTISED_Asym_Pause;
9664 } else if (epause->tx_pause) {
9665 newadv = ADVERTISED_Asym_Pause;
9666 } else
9667 newadv = 0;
9668
9669 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9670 u32 oldadv = phydev->advertising &
9671 (ADVERTISED_Pause |
9672 ADVERTISED_Asym_Pause);
9673 if (oldadv != newadv) {
9674 phydev->advertising &=
9675 ~(ADVERTISED_Pause |
9676 ADVERTISED_Asym_Pause);
9677 phydev->advertising |= newadv;
9678 err = phy_start_aneg(phydev);
9679 }
9680 } else {
9681 tp->link_config.advertising &=
9682 ~(ADVERTISED_Pause |
9683 ADVERTISED_Asym_Pause);
9684 tp->link_config.advertising |= newadv;
9685 }
9686 } else {
9687 if (epause->rx_pause)
e18ce346 9688 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9689 else
e18ce346 9690 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9691
b02fd9e3 9692 if (epause->tx_pause)
e18ce346 9693 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9694 else
e18ce346 9695 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9696
9697 if (netif_running(dev))
9698 tg3_setup_flow_control(tp, 0, 0);
9699 }
9700 } else {
9701 int irq_sync = 0;
9702
9703 if (netif_running(dev)) {
9704 tg3_netif_stop(tp);
9705 irq_sync = 1;
9706 }
9707
9708 tg3_full_lock(tp, irq_sync);
9709
9710 if (epause->autoneg)
9711 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9712 else
9713 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9714 if (epause->rx_pause)
e18ce346 9715 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9716 else
e18ce346 9717 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9718 if (epause->tx_pause)
e18ce346 9719 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9720 else
e18ce346 9721 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9722
9723 if (netif_running(dev)) {
9724 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9725 err = tg3_restart_hw(tp, 1);
9726 if (!err)
9727 tg3_netif_start(tp);
9728 }
9729
9730 tg3_full_unlock(tp);
9731 }
6aa20a22 9732
b9ec6c1b 9733 return err;
1da177e4 9734}
6aa20a22 9735
1da177e4
LT		 9736static u32 tg3_get_rx_csum(struct net_device *dev)
9737{
9738 struct tg3 *tp = netdev_priv(dev);
9739 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9740}
6aa20a22 9741
1da177e4
LT		 9742static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9743{
9744 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9745
1da177e4
LT		 9746 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9747 if (data != 0)
9748 return -EINVAL;
9749 return 0;
9750 }
6aa20a22 9751
f47c11ee 9752 spin_lock_bh(&tp->lock);
1da177e4
LT		 9753 if (data)
9754 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9755 else
9756 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9757 spin_unlock_bh(&tp->lock);
6aa20a22 9758
1da177e4
LT		 9759 return 0;
9760}
6aa20a22 9761
1da177e4
LT		 9762static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9763{
9764 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9765
1da177e4
LT		 9766 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9767 if (data != 0)
9768 return -EINVAL;
9769 return 0;
9770 }
6aa20a22 9771
321d32a0 9772 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9773 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9774 else
9c27dbdf 9775 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9776
9777 return 0;
9778}
9779
b9f2c044 9780static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9781{
b9f2c044
JG		 9782 switch (sset) {
9783 case ETH_SS_TEST:
9784 return TG3_NUM_TEST;
9785 case ETH_SS_STATS:
9786 return TG3_NUM_STATS;
9787 default:
9788 return -EOPNOTSUPP;
9789 }
4cafd3f5
MC		 9790}
9791
1da177e4
LT		 9792static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9793{
9794 switch (stringset) {
9795 case ETH_SS_STATS:
9796 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9797 break;
4cafd3f5
MC		 9798 case ETH_SS_TEST:
9799 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9800 break;
1da177e4
LT		 9801 default:
9802 WARN_ON(1); /* we need a WARN() */
9803 break;
9804 }
9805}
9806
4009a93d
MC		 9807static int tg3_phys_id(struct net_device *dev, u32 data)
9808{
9809 struct tg3 *tp = netdev_priv(dev);
9810 int i;
9811
9812 if (!netif_running(tp->dev))
9813 return -EAGAIN;
9814
9815 if (data == 0)
759afc31 9816 data = UINT_MAX / 2;
4009a93d
MC		 9817
9818 for (i = 0; i < (data * 2); i++) {
9819 if ((i % 2) == 0)
9820 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9821 LED_CTRL_1000MBPS_ON |
9822 LED_CTRL_100MBPS_ON |
9823 LED_CTRL_10MBPS_ON |
9824 LED_CTRL_TRAFFIC_OVERRIDE |
9825 LED_CTRL_TRAFFIC_BLINK |
9826 LED_CTRL_TRAFFIC_LED);
6aa20a22 9827
4009a93d
MC		 9828 else
9829 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9830 LED_CTRL_TRAFFIC_OVERRIDE);
9831
9832 if (msleep_interruptible(500))
9833 break;
9834 }
9835 tw32(MAC_LED_CTRL, tp->led_ctrl);
9836 return 0;
9837}
9838
1da177e4
LT		 9839static void tg3_get_ethtool_stats (struct net_device *dev,
9840 struct ethtool_stats *estats, u64 *tmp_stats)
9841{
9842 struct tg3 *tp = netdev_priv(dev);
9843 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9844}
9845
566f86ad 9846#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9847#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9848#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9849#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9850#define NVRAM_SELFBOOT_HW_SIZE 0x20
9851#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9852
9853static int tg3_test_nvram(struct tg3 *tp)
9854{
b9fc7dc5 9855 u32 csum, magic;
a9dc529d 9856 __be32 *buf;
ab0049b4 9857 int i, j, k, err = 0, size;
566f86ad 9858
df259d8c
MC		 9859 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9860 return 0;
9861
e4f34110 9862 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9863 return -EIO;
9864
1b27777a
MC		 9865 if (magic == TG3_EEPROM_MAGIC)
9866 size = NVRAM_TEST_SIZE;
b16250e3 9867 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9868 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9869 TG3_EEPROM_SB_FORMAT_1) {
9870 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9871 case TG3_EEPROM_SB_REVISION_0:
9872 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9873 break;
9874 case TG3_EEPROM_SB_REVISION_2:
9875 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9876 break;
9877 case TG3_EEPROM_SB_REVISION_3:
9878 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9879 break;
9880 default:
9881 return 0;
9882 }
9883 } else
1b27777a 9884 return 0;
b16250e3
MC		 9885 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9886 size = NVRAM_SELFBOOT_HW_SIZE;
9887 else
1b27777a
MC		 9888 return -EIO;
9889
9890 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9891 if (buf == NULL)
9892 return -ENOMEM;
9893
1b27777a
MC		 9894 err = -EIO;
9895 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9896 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9897 if (err)
566f86ad 9898 break;
566f86ad 9899 }
1b27777a 9900 if (i < size)
566f86ad
MC		 9901 goto out;
9902
1b27777a 9903 /* Selfboot format */
a9dc529d 9904 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9905 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9906 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9907 u8 *buf8 = (u8 *) buf, csum8 = 0;
9908
b9fc7dc5 9909 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9910 TG3_EEPROM_SB_REVISION_2) {
9911 /* For rev 2, the csum doesn't include the MBA. */
9912 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9913 csum8 += buf8[i];
9914 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9915 csum8 += buf8[i];
9916 } else {
9917 for (i = 0; i < size; i++)
9918 csum8 += buf8[i];
9919 }
1b27777a 9920
ad96b485
AB		 9921 if (csum8 == 0) {
9922 err = 0;
9923 goto out;
9924 }
9925
9926 err = -EIO;
9927 goto out;
1b27777a 9928 }
566f86ad 9929
b9fc7dc5 9930 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9931 TG3_EEPROM_MAGIC_HW) {
9932 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9933 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9934 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9935
9936 /* Separate the parity bits and the data bytes. */
9937 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9938 if ((i == 0) || (i == 8)) {
9939 int l;
9940 u8 msk;
9941
9942 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9943 parity[k++] = buf8[i] & msk;
9944 i++;
9945 }
9946 else if (i == 16) {
9947 int l;
9948 u8 msk;
9949
9950 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9951 parity[k++] = buf8[i] & msk;
9952 i++;
9953
9954 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9955 parity[k++] = buf8[i] & msk;
9956 i++;
9957 }
9958 data[j++] = buf8[i];
9959 }
9960
9961 err = -EIO;
9962 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9963 u8 hw8 = hweight8(data[i]);
9964
9965 if ((hw8 & 0x1) && parity[i])
9966 goto out;
9967 else if (!(hw8 & 0x1) && !parity[i])
9968 goto out;
9969 }
9970 err = 0;
9971 goto out;
9972 }
9973
566f86ad
MC		 9974 /* Bootstrap checksum at offset 0x10 */
9975 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9976 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9977 goto out;
9978
9979 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9980 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9981 if (csum != be32_to_cpu(buf[0xfc/4]))
9982 goto out;
566f86ad
MC		 9983
9984 err = 0;
9985
9986out:
9987 kfree(buf);
9988 return err;
9989}
9990
ca43007a
MC		 9991#define TG3_SERDES_TIMEOUT_SEC 2
9992#define TG3_COPPER_TIMEOUT_SEC 6
9993
9994static int tg3_test_link(struct tg3 *tp)
9995{
9996 int i, max;
9997
9998 if (!netif_running(tp->dev))
9999 return -ENODEV;
10000
4c987487 10001 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10002 max = TG3_SERDES_TIMEOUT_SEC;
10003 else
10004 max = TG3_COPPER_TIMEOUT_SEC;
10005
10006 for (i = 0; i < max; i++) {
10007 if (netif_carrier_ok(tp->dev))
10008 return 0;
10009
10010 if (msleep_interruptible(1000))
10011 break;
10012 }
10013
10014 return -EIO;
10015}
10016
a71116d1 10017/* Only test the commonly used registers */
30ca3e37 10018static int tg3_test_registers(struct tg3 *tp)
a71116d1 10019{
b16250e3 10020 int i, is_5705, is_5750;
a71116d1
MC		 10021 u32 offset, read_mask, write_mask, val, save_val, read_val;
10022 static struct {
10023 u16 offset;
10024 u16 flags;
10025#define TG3_FL_5705 0x1
10026#define TG3_FL_NOT_5705 0x2
10027#define TG3_FL_NOT_5788 0x4
b16250e3 10028#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10029 u32 read_mask;
10030 u32 write_mask;
10031 } reg_tbl[] = {
10032 /* MAC Control Registers */
10033 { MAC_MODE, TG3_FL_NOT_5705,
10034 0x00000000, 0x00ef6f8c },
10035 { MAC_MODE, TG3_FL_5705,
10036 0x00000000, 0x01ef6b8c },
10037 { MAC_STATUS, TG3_FL_NOT_5705,
10038 0x03800107, 0x00000000 },
10039 { MAC_STATUS, TG3_FL_5705,
10040 0x03800100, 0x00000000 },
10041 { MAC_ADDR_0_HIGH, 0x0000,
10042 0x00000000, 0x0000ffff },
10043 { MAC_ADDR_0_LOW, 0x0000,
10044 0x00000000, 0xffffffff },
10045 { MAC_RX_MTU_SIZE, 0x0000,
10046 0x00000000, 0x0000ffff },
10047 { MAC_TX_MODE, 0x0000,
10048 0x00000000, 0x00000070 },
10049 { MAC_TX_LENGTHS, 0x0000,
10050 0x00000000, 0x00003fff },
10051 { MAC_RX_MODE, TG3_FL_NOT_5705,
10052 0x00000000, 0x000007fc },
10053 { MAC_RX_MODE, TG3_FL_5705,
10054 0x00000000, 0x000007dc },
10055 { MAC_HASH_REG_0, 0x0000,
10056 0x00000000, 0xffffffff },
10057 { MAC_HASH_REG_1, 0x0000,
10058 0x00000000, 0xffffffff },
10059 { MAC_HASH_REG_2, 0x0000,
10060 0x00000000, 0xffffffff },
10061 { MAC_HASH_REG_3, 0x0000,
10062 0x00000000, 0xffffffff },
10063
10064 /* Receive Data and Receive BD Initiator Control Registers. */
10065 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10066 0x00000000, 0xffffffff },
10067 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10068 0x00000000, 0xffffffff },
10069 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10070 0x00000000, 0x00000003 },
10071 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10072 0x00000000, 0xffffffff },
10073 { RCVDBDI_STD_BD+0, 0x0000,
10074 0x00000000, 0xffffffff },
10075 { RCVDBDI_STD_BD+4, 0x0000,
10076 0x00000000, 0xffffffff },
10077 { RCVDBDI_STD_BD+8, 0x0000,
10078 0x00000000, 0xffff0002 },
10079 { RCVDBDI_STD_BD+0xc, 0x0000,
10080 0x00000000, 0xffffffff },
6aa20a22 10081
a71116d1
MC		 10082 /* Receive BD Initiator Control Registers. */
10083 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10084 0x00000000, 0xffffffff },
10085 { RCVBDI_STD_THRESH, TG3_FL_5705,
10086 0x00000000, 0x000003ff },
10087 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10088 0x00000000, 0xffffffff },
6aa20a22 10089
a71116d1
MC		 10090 /* Host Coalescing Control Registers. */
10091 { HOSTCC_MODE, TG3_FL_NOT_5705,
10092 0x00000000, 0x00000004 },
10093 { HOSTCC_MODE, TG3_FL_5705,
10094 0x00000000, 0x000000f6 },
10095 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10096 0x00000000, 0xffffffff },
10097 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10098 0x00000000, 0x000003ff },
10099 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10100 0x00000000, 0xffffffff },
10101 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10102 0x00000000, 0x000003ff },
10103 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10104 0x00000000, 0xffffffff },
10105 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10106 0x00000000, 0x000000ff },
10107 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10108 0x00000000, 0xffffffff },
10109 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10110 0x00000000, 0x000000ff },
10111 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10112 0x00000000, 0xffffffff },
10113 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10114 0x00000000, 0xffffffff },
10115 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10116 0x00000000, 0xffffffff },
10117 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10118 0x00000000, 0x000000ff },
10119 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10120 0x00000000, 0xffffffff },
10121 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10122 0x00000000, 0x000000ff },
10123 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10124 0x00000000, 0xffffffff },
10125 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10126 0x00000000, 0xffffffff },
10127 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10128 0x00000000, 0xffffffff },
10129 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10130 0x00000000, 0xffffffff },
10131 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10132 0x00000000, 0xffffffff },
10133 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10134 0xffffffff, 0x00000000 },
10135 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10136 0xffffffff, 0x00000000 },
10137
10138 /* Buffer Manager Control Registers. */
b16250e3 10139 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10140 0x00000000, 0x007fff80 },
b16250e3 10141 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10142 0x00000000, 0x007fffff },
10143 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10144 0x00000000, 0x0000003f },
10145 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10146 0x00000000, 0x000001ff },
10147 { BUFMGR_MB_HIGH_WATER, 0x0000,
10148 0x00000000, 0x000001ff },
10149 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10150 0xffffffff, 0x00000000 },
10151 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10152 0xffffffff, 0x00000000 },
6aa20a22 10153
a71116d1
MC		 10154 /* Mailbox Registers */
10155 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10156 0x00000000, 0x000001ff },
10157 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10158 0x00000000, 0x000001ff },
10159 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10160 0x00000000, 0x000007ff },
10161 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10162 0x00000000, 0x000001ff },
10163
10164 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10165 };
10166
b16250e3
MC		 10167 is_5705 = is_5750 = 0;
10168 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10169 is_5705 = 1;
b16250e3
MC		 10170 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10171 is_5750 = 1;
10172 }
a71116d1
MC		 10173
10174 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10175 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10176 continue;
10177
10178 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10179 continue;
10180
10181 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10182 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10183 continue;
10184
b16250e3
MC		 10185 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10186 continue;
10187
a71116d1
MC		 10188 offset = (u32) reg_tbl[i].offset;
10189 read_mask = reg_tbl[i].read_mask;
10190 write_mask = reg_tbl[i].write_mask;
10191
10192 /* Save the original register content */
10193 save_val = tr32(offset);
10194
10195 /* Determine the read-only value. */
10196 read_val = save_val & read_mask;
10197
10198 /* Write zero to the register, then make sure the read-only bits
10199 * are not changed and the read/write bits are all zeros.
10200 */
10201 tw32(offset, 0);
10202
10203 val = tr32(offset);
10204
10205 /* Test the read-only and read/write bits. */
10206 if (((val & read_mask) != read_val) || (val & write_mask))
10207 goto out;
10208
10209 /* Write ones to all the bits defined by RdMask and WrMask, then
10210 * make sure the read-only bits are not changed and the
10211 * read/write bits are all ones.
10212 */
10213 tw32(offset, read_mask | write_mask);
10214
10215 val = tr32(offset);
10216
10217 /* Test the read-only bits. */
10218 if ((val & read_mask) != read_val)
10219 goto out;
10220
10221 /* Test the read/write bits. */
10222 if ((val & write_mask) != write_mask)
10223 goto out;
10224
10225 tw32(offset, save_val);
10226 }
10227
10228 return 0;
10229
10230out:
9f88f29f
MC		 10231 if (netif_msg_hw(tp))
10232 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10233 offset);
a71116d1
MC		 10234 tw32(offset, save_val);
10235 return -EIO;
10236}
10237
7942e1db
MC		 10238static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10239{
f71e1309 10240 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10241 int i;
10242 u32 j;
10243
e9edda69 10244 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10245 for (j = 0; j < len; j += 4) {
10246 u32 val;
10247
10248 tg3_write_mem(tp, offset + j, test_pattern[i]);
10249 tg3_read_mem(tp, offset + j, &val);
10250 if (val != test_pattern[i])
10251 return -EIO;
10252 }
10253 }
10254 return 0;
10255}
10256
10257static int tg3_test_memory(struct tg3 *tp)
10258{
10259 static struct mem_entry {
10260 u32 offset;
10261 u32 len;
10262 } mem_tbl_570x[] = {
38690194 10263 { 0x00000000, 0x00b50},
7942e1db
MC		 10264 { 0x00002000, 0x1c000},
10265 { 0xffffffff, 0x00000}
10266 }, mem_tbl_5705[] = {
10267 { 0x00000100, 0x0000c},
10268 { 0x00000200, 0x00008},
7942e1db
MC		 10269 { 0x00004000, 0x00800},
10270 { 0x00006000, 0x01000},
10271 { 0x00008000, 0x02000},
10272 { 0x00010000, 0x0e000},
10273 { 0xffffffff, 0x00000}
79f4d13a
MC		 10274 }, mem_tbl_5755[] = {
10275 { 0x00000200, 0x00008},
10276 { 0x00004000, 0x00800},
10277 { 0x00006000, 0x00800},
10278 { 0x00008000, 0x02000},
10279 { 0x00010000, 0x0c000},
10280 { 0xffffffff, 0x00000}
b16250e3
MC		 10281 }, mem_tbl_5906[] = {
10282 { 0x00000200, 0x00008},
10283 { 0x00004000, 0x00400},
10284 { 0x00006000, 0x00400},
10285 { 0x00008000, 0x01000},
10286 { 0x00010000, 0x01000},
10287 { 0xffffffff, 0x00000}
7942e1db
MC		 10288 };
10289 struct mem_entry *mem_tbl;
10290 int err = 0;
10291 int i;
10292
321d32a0
MC		 10293 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10294 mem_tbl = mem_tbl_5755;
10295 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10296 mem_tbl = mem_tbl_5906;
10297 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10298 mem_tbl = mem_tbl_5705;
10299 else
7942e1db
MC		 10300 mem_tbl = mem_tbl_570x;
10301
10302 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10303 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10304 mem_tbl[i].len)) != 0)
10305 break;
10306 }
6aa20a22 10307
7942e1db
MC		 10308 return err;
10309}
10310
9f40dead
MC		 10311#define TG3_MAC_LOOPBACK 0
10312#define TG3_PHY_LOOPBACK 1
10313
10314static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10315{
9f40dead 10316 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10317 u32 desc_idx, coal_now;
c76949a6
MC		 10318 struct sk_buff *skb, *rx_skb;
10319 u8 *tx_data;
10320 dma_addr_t map;
10321 int num_pkts, tx_len, rx_len, i, err;
10322 struct tg3_rx_buffer_desc *desc;
898a56f8 10323 struct tg3_napi *tnapi, *rnapi;
21f581a5 10324 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10325
0c1d0e2b
MC		 10326 if (tp->irq_cnt > 1) {
10327 tnapi = &tp->napi[1];
10328 rnapi = &tp->napi[1];
10329 } else {
10330 tnapi = &tp->napi[0];
10331 rnapi = &tp->napi[0];
10332 }
fd2ce37f 10333 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10334
9f40dead 10335 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10336 /* HW errata - mac loopback fails in some cases on 5780.
10337 * Normal traffic and PHY loopback are not affected by
10338 * errata.
10339 */
10340 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10341 return 0;
10342
9f40dead 10343 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10344 MAC_MODE_PORT_INT_LPBACK;
10345 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10346 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10347 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10348 mac_mode |= MAC_MODE_PORT_MODE_MII;
10349 else
10350 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10351 tw32(MAC_MODE, mac_mode);
10352 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10353 u32 val;
10354
7f97a4bd
MC		 10355 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10356 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10357 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10358 } else
10359 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10360
9ef8ca99
MC		 10361 tg3_phy_toggle_automdix(tp, 0);
10362
3f7045c1 10363 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10364 udelay(40);
5d64ad34 10365
e8f3f6ca 10366 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10367 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10368 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10369 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10370 mac_mode |= MAC_MODE_PORT_MODE_MII;
10371 } else
10372 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10373
c94e3941
MC		 10374 /* reset to prevent losing 1st rx packet intermittently */
10375 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10376 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10377 udelay(10);
10378 tw32_f(MAC_RX_MODE, tp->rx_mode);
10379 }
e8f3f6ca
MC		 10380 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10381 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10382 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10383 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10384 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10385 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10386 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10387 }
9f40dead 10388 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10389 }
10390 else
10391 return -EINVAL;
c76949a6
MC		 10392
10393 err = -EIO;
10394
c76949a6 10395 tx_len = 1514;
a20e9c62 10396 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10397 if (!skb)
10398 return -ENOMEM;
10399
c76949a6
MC		 10400 tx_data = skb_put(skb, tx_len);
10401 memcpy(tx_data, tp->dev->dev_addr, 6);
10402 memset(tx_data + 6, 0x0, 8);
10403
10404 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10405
10406 for (i = 14; i < tx_len; i++)
10407 tx_data[i] = (u8) (i & 0xff);
10408
a21771dd
MC		 10409 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10410 dev_kfree_skb(skb);
10411 return -EIO;
10412 }
c76949a6
MC		 10413
10414 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10415 rnapi->coal_now);
c76949a6
MC		 10416
10417 udelay(10);
10418
898a56f8 10419 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10420
c76949a6
MC		 10421 num_pkts = 0;
10422
a21771dd
MC		 10423 tg3_set_txd(tnapi, tnapi->tx_prod,
10424 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
c76949a6 10425
f3f3f27e 10426 tnapi->tx_prod++;
c76949a6
MC		 10427 num_pkts++;
10428
f3f3f27e
MC		 10429 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10430 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10431
10432 udelay(10);
10433
303fc921
MC		 10434 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10435 for (i = 0; i < 35; i++) {
c76949a6 10436 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10437 coal_now);
c76949a6
MC		 10438
10439 udelay(10);
10440
898a56f8
MC		 10441 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10442 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10443 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10444 (rx_idx == (rx_start_idx + num_pkts)))
10445 break;
10446 }
10447
a21771dd 10448 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
c76949a6
MC		 10449 dev_kfree_skb(skb);
10450
f3f3f27e 10451 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10452 goto out;
10453
10454 if (rx_idx != rx_start_idx + num_pkts)
10455 goto out;
10456
72334482 10457 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10458 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10459 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10460 if (opaque_key != RXD_OPAQUE_RING_STD)
10461 goto out;
10462
10463 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10464 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10465 goto out;
10466
10467 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10468 if (rx_len != tx_len)
10469 goto out;
10470
21f581a5 10471 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10472
21f581a5 10473 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10474 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10475
10476 for (i = 14; i < tx_len; i++) {
10477 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10478 goto out;
10479 }
10480 err = 0;
6aa20a22 10481
c76949a6
MC		 10482 /* tg3_free_rings will unmap and free the rx_skb */
10483out:
10484 return err;
10485}
10486
9f40dead
MC		 10487#define TG3_MAC_LOOPBACK_FAILED 1
10488#define TG3_PHY_LOOPBACK_FAILED 2
10489#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10490 TG3_PHY_LOOPBACK_FAILED)
10491
10492static int tg3_test_loopback(struct tg3 *tp)
10493{
10494 int err = 0;
9936bcf6 10495 u32 cpmuctrl = 0;
9f40dead
MC		 10496
10497 if (!netif_running(tp->dev))
10498 return TG3_LOOPBACK_FAILED;
10499
b9ec6c1b
MC		 10500 err = tg3_reset_hw(tp, 1);
10501 if (err)
10502 return TG3_LOOPBACK_FAILED;
9f40dead 10503
6833c043
MC		 10504 /* Turn off gphy autopowerdown. */
10505 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10506 tg3_phy_toggle_apd(tp, false);
10507
321d32a0 10508 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10509 int i;
10510 u32 status;
10511
10512 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10513
10514 /* Wait for up to 40 microseconds to acquire lock. */
10515 for (i = 0; i < 4; i++) {
10516 status = tr32(TG3_CPMU_MUTEX_GNT);
10517 if (status == CPMU_MUTEX_GNT_DRIVER)
10518 break;
10519 udelay(10);
10520 }
10521
10522 if (status != CPMU_MUTEX_GNT_DRIVER)
10523 return TG3_LOOPBACK_FAILED;
10524
b2a5c19c 10525 /* Turn off link-based power management. */
e875093c 10526 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10527 tw32(TG3_CPMU_CTRL,
10528 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10529 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10530 }
10531
9f40dead
MC		 10532 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10533 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10534
321d32a0 10535 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10536 tw32(TG3_CPMU_CTRL, cpmuctrl);
10537
10538 /* Release the mutex */
10539 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10540 }
10541
dd477003
MC		 10542 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10543 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10544 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10545 err |= TG3_PHY_LOOPBACK_FAILED;
10546 }
10547
6833c043
MC		 10548 /* Re-enable gphy autopowerdown. */
10549 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10550 tg3_phy_toggle_apd(tp, true);
10551
9f40dead
MC		 10552 return err;
10553}
10554
4cafd3f5
MC		 10555static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10556 u64 *data)
10557{
566f86ad
MC		 10558 struct tg3 *tp = netdev_priv(dev);
10559
bc1c7567
MC		 10560 if (tp->link_config.phy_is_low_power)
10561 tg3_set_power_state(tp, PCI_D0);
10562
566f86ad
MC		 10563 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10564
10565 if (tg3_test_nvram(tp) != 0) {
10566 etest->flags |= ETH_TEST_FL_FAILED;
10567 data[0] = 1;
10568 }
ca43007a
MC		 10569 if (tg3_test_link(tp) != 0) {
10570 etest->flags |= ETH_TEST_FL_FAILED;
10571 data[1] = 1;
10572 }
a71116d1 10573 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10574 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10575
10576 if (netif_running(dev)) {
b02fd9e3 10577 tg3_phy_stop(tp);
a71116d1 10578 tg3_netif_stop(tp);
bbe832c0
MC		 10579 irq_sync = 1;
10580 }
a71116d1 10581
bbe832c0 10582 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10583
10584 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10585 err = tg3_nvram_lock(tp);
a71116d1
MC		 10586 tg3_halt_cpu(tp, RX_CPU_BASE);
10587 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10588 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10589 if (!err)
10590 tg3_nvram_unlock(tp);
a71116d1 10591
d9ab5ad1
MC		 10592 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10593 tg3_phy_reset(tp);
10594
a71116d1
MC		 10595 if (tg3_test_registers(tp) != 0) {
10596 etest->flags |= ETH_TEST_FL_FAILED;
10597 data[2] = 1;
10598 }
7942e1db
MC		 10599 if (tg3_test_memory(tp) != 0) {
10600 etest->flags |= ETH_TEST_FL_FAILED;
10601 data[3] = 1;
10602 }
9f40dead 10603 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10604 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10605
f47c11ee
DM		 10606 tg3_full_unlock(tp);
10607
d4bc3927
MC		 10608 if (tg3_test_interrupt(tp) != 0) {
10609 etest->flags |= ETH_TEST_FL_FAILED;
10610 data[5] = 1;
10611 }
f47c11ee
DM		 10612
10613 tg3_full_lock(tp, 0);
d4bc3927 10614
a71116d1
MC		 10615 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10616 if (netif_running(dev)) {
10617 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10618 err2 = tg3_restart_hw(tp, 1);
10619 if (!err2)
b9ec6c1b 10620 tg3_netif_start(tp);
a71116d1 10621 }
f47c11ee
DM		 10622
10623 tg3_full_unlock(tp);
b02fd9e3
MC		 10624
10625 if (irq_sync && !err2)
10626 tg3_phy_start(tp);
a71116d1 10627 }
bc1c7567
MC		 10628 if (tp->link_config.phy_is_low_power)
10629 tg3_set_power_state(tp, PCI_D3hot);
10630
4cafd3f5
MC		 10631}
10632
1da177e4
LT		 10633static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10634{
10635 struct mii_ioctl_data *data = if_mii(ifr);
10636 struct tg3 *tp = netdev_priv(dev);
10637 int err;
10638
b02fd9e3 10639 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10640 struct phy_device *phydev;
b02fd9e3
MC		 10641 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10642 return -EAGAIN;
3f0e3ad7
MC		 10643 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10644 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10645 }
10646
1da177e4
LT		 10647 switch(cmd) {
10648 case SIOCGMIIPHY:
882e9793 10649 data->phy_id = tp->phy_addr;
1da177e4
LT		 10650
10651 /* fallthru */
10652 case SIOCGMIIREG: {
10653 u32 mii_regval;
10654
10655 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10656 break; /* We have no PHY */
10657
bc1c7567
MC		 10658 if (tp->link_config.phy_is_low_power)
10659 return -EAGAIN;
10660
f47c11ee 10661 spin_lock_bh(&tp->lock);
1da177e4 10662 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10663 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10664
10665 data->val_out = mii_regval;
10666
10667 return err;
10668 }
10669
10670 case SIOCSMIIREG:
10671 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10672 break; /* We have no PHY */
10673
bc1c7567
MC		 10674 if (tp->link_config.phy_is_low_power)
10675 return -EAGAIN;
10676
f47c11ee 10677 spin_lock_bh(&tp->lock);
1da177e4 10678 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10679 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10680
10681 return err;
10682
10683 default:
10684 /* do nothing */
10685 break;
10686 }
10687 return -EOPNOTSUPP;
10688}
10689
10690#if TG3_VLAN_TAG_USED
10691static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10692{
10693 struct tg3 *tp = netdev_priv(dev);
10694
844b3eed
MC		 10695 if (!netif_running(dev)) {
10696 tp->vlgrp = grp;
10697 return;
10698 }
10699
10700 tg3_netif_stop(tp);
29315e87 10701
f47c11ee 10702 tg3_full_lock(tp, 0);
1da177e4
LT		 10703
10704 tp->vlgrp = grp;
10705
10706 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10707 __tg3_set_rx_mode(dev);
10708
844b3eed 10709 tg3_netif_start(tp);
46966545
MC		 10710
10711 tg3_full_unlock(tp);
1da177e4 10712}
1da177e4
LT		 10713#endif
10714
15f9850d
DM		 10715static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10716{
10717 struct tg3 *tp = netdev_priv(dev);
10718
10719 memcpy(ec, &tp->coal, sizeof(*ec));
10720 return 0;
10721}
10722
d244c892
MC		 10723static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10724{
10725 struct tg3 *tp = netdev_priv(dev);
10726 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10727 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10728
10729 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10730 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10731 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10732 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10733 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10734 }
10735
10736 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10737 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10738 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10739 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10740 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10741 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10742 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10743 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10744 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10745 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10746 return -EINVAL;
10747
10748 /* No rx interrupts will be generated if both are zero */
10749 if ((ec->rx_coalesce_usecs == 0) &&
10750 (ec->rx_max_coalesced_frames == 0))
10751 return -EINVAL;
10752
10753 /* No tx interrupts will be generated if both are zero */
10754 if ((ec->tx_coalesce_usecs == 0) &&
10755 (ec->tx_max_coalesced_frames == 0))
10756 return -EINVAL;
10757
10758 /* Only copy relevant parameters, ignore all others. */
10759 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10760 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10761 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10762 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10763 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10764 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10765 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10766 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10767 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10768
10769 if (netif_running(dev)) {
10770 tg3_full_lock(tp, 0);
10771 __tg3_set_coalesce(tp, &tp->coal);
10772 tg3_full_unlock(tp);
10773 }
10774 return 0;
10775}
10776
7282d491 10777static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10778 .get_settings = tg3_get_settings,
10779 .set_settings = tg3_set_settings,
10780 .get_drvinfo = tg3_get_drvinfo,
10781 .get_regs_len = tg3_get_regs_len,
10782 .get_regs = tg3_get_regs,
10783 .get_wol = tg3_get_wol,
10784 .set_wol = tg3_set_wol,
10785 .get_msglevel = tg3_get_msglevel,
10786 .set_msglevel = tg3_set_msglevel,
10787 .nway_reset = tg3_nway_reset,
10788 .get_link = ethtool_op_get_link,
10789 .get_eeprom_len = tg3_get_eeprom_len,
10790 .get_eeprom = tg3_get_eeprom,
10791 .set_eeprom = tg3_set_eeprom,
10792 .get_ringparam = tg3_get_ringparam,
10793 .set_ringparam = tg3_set_ringparam,
10794 .get_pauseparam = tg3_get_pauseparam,
10795 .set_pauseparam = tg3_set_pauseparam,
10796 .get_rx_csum = tg3_get_rx_csum,
10797 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10798 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10799 .set_sg = ethtool_op_set_sg,
1da177e4 10800 .set_tso = tg3_set_tso,
4cafd3f5 10801 .self_test = tg3_self_test,
1da177e4 10802 .get_strings = tg3_get_strings,
4009a93d 10803 .phys_id = tg3_phys_id,
1da177e4 10804 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10805 .get_coalesce = tg3_get_coalesce,
d244c892 10806 .set_coalesce = tg3_set_coalesce,
b9f2c044 10807 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10808};
10809
10810static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10811{
1b27777a 10812 u32 cursize, val, magic;
1da177e4
LT		 10813
10814 tp->nvram_size = EEPROM_CHIP_SIZE;
10815
e4f34110 10816 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10817 return;
10818
b16250e3
MC		 10819 if ((magic != TG3_EEPROM_MAGIC) &&
10820 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10821 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10822 return;
10823
10824 /*
10825 * Size the chip by reading offsets at increasing powers of two.
10826 * When we encounter our validation signature, we know the addressing
10827 * has wrapped around, and thus have our chip size.
10828 */
1b27777a 10829 cursize = 0x10;
1da177e4
LT		 10830
10831 while (cursize < tp->nvram_size) {
e4f34110 10832 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10833 return;
10834
1820180b 10835 if (val == magic)
1da177e4
LT		 10836 break;
10837
10838 cursize <<= 1;
10839 }
10840
10841 tp->nvram_size = cursize;
10842}
6aa20a22 10843
1da177e4
LT		 10844static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10845{
10846 u32 val;
10847
df259d8c
MC		 10848 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10849 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10850 return;
10851
10852 /* Selfboot format */
1820180b 10853 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10854 tg3_get_eeprom_size(tp);
10855 return;
10856 }
10857
6d348f2c 10858 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10859 if (val != 0) {
6d348f2c
MC		 10860 /* This is confusing. We want to operate on the
10861 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10862 * call will read from NVRAM and byteswap the data
10863 * according to the byteswapping settings for all
10864 * other register accesses. This ensures the data we
10865 * want will always reside in the lower 16-bits.
10866 * However, the data in NVRAM is in LE format, which
10867 * means the data from the NVRAM read will always be
10868 * opposite the endianness of the CPU. The 16-bit
10869 * byteswap then brings the data to CPU endianness.
10870 */
10871 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10872 return;
10873 }
10874 }
fd1122a2 10875 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10876}
10877
10878static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10879{
10880 u32 nvcfg1;
10881
10882 nvcfg1 = tr32(NVRAM_CFG1);
10883 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10884 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10885 } else {
1da177e4
LT		 10886 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10887 tw32(NVRAM_CFG1, nvcfg1);
10888 }
10889
4c987487 10890 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10891 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10892 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10893 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10894 tp->nvram_jedecnum = JEDEC_ATMEL;
10895 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10896 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10897 break;
10898 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10899 tp->nvram_jedecnum = JEDEC_ATMEL;
10900 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10901 break;
10902 case FLASH_VENDOR_ATMEL_EEPROM:
10903 tp->nvram_jedecnum = JEDEC_ATMEL;
10904 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10905 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10906 break;
10907 case FLASH_VENDOR_ST:
10908 tp->nvram_jedecnum = JEDEC_ST;
10909 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10910 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10911 break;
10912 case FLASH_VENDOR_SAIFUN:
10913 tp->nvram_jedecnum = JEDEC_SAIFUN;
10914 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10915 break;
10916 case FLASH_VENDOR_SST_SMALL:
10917 case FLASH_VENDOR_SST_LARGE:
10918 tp->nvram_jedecnum = JEDEC_SST;
10919 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10920 break;
1da177e4 10921 }
8590a603 10922 } else {
1da177e4
LT		 10923 tp->nvram_jedecnum = JEDEC_ATMEL;
10924 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10925 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10926 }
10927}
10928
a1b950d5
MC		 10929static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10930{
10931 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10932 case FLASH_5752PAGE_SIZE_256:
10933 tp->nvram_pagesize = 256;
10934 break;
10935 case FLASH_5752PAGE_SIZE_512:
10936 tp->nvram_pagesize = 512;
10937 break;
10938 case FLASH_5752PAGE_SIZE_1K:
10939 tp->nvram_pagesize = 1024;
10940 break;
10941 case FLASH_5752PAGE_SIZE_2K:
10942 tp->nvram_pagesize = 2048;
10943 break;
10944 case FLASH_5752PAGE_SIZE_4K:
10945 tp->nvram_pagesize = 4096;
10946 break;
10947 case FLASH_5752PAGE_SIZE_264:
10948 tp->nvram_pagesize = 264;
10949 break;
10950 case FLASH_5752PAGE_SIZE_528:
10951 tp->nvram_pagesize = 528;
10952 break;
10953 }
10954}
10955
361b4ac2
MC		 10956static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10957{
10958 u32 nvcfg1;
10959
10960 nvcfg1 = tr32(NVRAM_CFG1);
10961
e6af301b
MC		 10962 /* NVRAM protection for TPM */
10963 if (nvcfg1 & (1 << 27))
10964 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10965
361b4ac2 10966 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10967 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10968 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10969 tp->nvram_jedecnum = JEDEC_ATMEL;
10970 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10971 break;
10972 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10973 tp->nvram_jedecnum = JEDEC_ATMEL;
10974 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10975 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10976 break;
10977 case FLASH_5752VENDOR_ST_M45PE10:
10978 case FLASH_5752VENDOR_ST_M45PE20:
10979 case FLASH_5752VENDOR_ST_M45PE40:
10980 tp->nvram_jedecnum = JEDEC_ST;
10981 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10982 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10983 break;
361b4ac2
MC		 10984 }
10985
10986 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 10987 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 10988 } else {
361b4ac2
MC		 10989 /* For eeprom, set pagesize to maximum eeprom size */
10990 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10991
10992 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10993 tw32(NVRAM_CFG1, nvcfg1);
10994 }
10995}
10996
d3c7b886
MC		 10997static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10998{
989a9d23 10999 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11000
11001 nvcfg1 = tr32(NVRAM_CFG1);
11002
11003 /* NVRAM protection for TPM */
989a9d23 11004 if (nvcfg1 & (1 << 27)) {
d3c7b886 11005 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 11006 protect = 1;
11007 }
d3c7b886 11008
989a9d23
MC		 11009 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11010 switch (nvcfg1) {
8590a603
MC		 11011 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11012 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11013 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11014 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11015 tp->nvram_jedecnum = JEDEC_ATMEL;
11016 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11017 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11018 tp->nvram_pagesize = 264;
11019 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11020 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11021 tp->nvram_size = (protect ? 0x3e200 :
11022 TG3_NVRAM_SIZE_512KB);
11023 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11024 tp->nvram_size = (protect ? 0x1f200 :
11025 TG3_NVRAM_SIZE_256KB);
11026 else
11027 tp->nvram_size = (protect ? 0x1f200 :
11028 TG3_NVRAM_SIZE_128KB);
11029 break;
11030 case FLASH_5752VENDOR_ST_M45PE10:
11031 case FLASH_5752VENDOR_ST_M45PE20:
11032 case FLASH_5752VENDOR_ST_M45PE40:
11033 tp->nvram_jedecnum = JEDEC_ST;
11034 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11035 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11036 tp->nvram_pagesize = 256;
11037 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11038 tp->nvram_size = (protect ?
11039 TG3_NVRAM_SIZE_64KB :
11040 TG3_NVRAM_SIZE_128KB);
11041 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11042 tp->nvram_size = (protect ?
11043 TG3_NVRAM_SIZE_64KB :
11044 TG3_NVRAM_SIZE_256KB);
11045 else
11046 tp->nvram_size = (protect ?
11047 TG3_NVRAM_SIZE_128KB :
11048 TG3_NVRAM_SIZE_512KB);
11049 break;
d3c7b886
MC		 11050 }
11051}
11052
1b27777a
MC		 11053static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11054{
11055 u32 nvcfg1;
11056
11057 nvcfg1 = tr32(NVRAM_CFG1);
11058
11059 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11060 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11061 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11062 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11063 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11064 tp->nvram_jedecnum = JEDEC_ATMEL;
11065 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11066 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11067
8590a603
MC		 11068 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11069 tw32(NVRAM_CFG1, nvcfg1);
11070 break;
11071 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11072 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11073 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11074 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11075 tp->nvram_jedecnum = JEDEC_ATMEL;
11076 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11077 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11078 tp->nvram_pagesize = 264;
11079 break;
11080 case FLASH_5752VENDOR_ST_M45PE10:
11081 case FLASH_5752VENDOR_ST_M45PE20:
11082 case FLASH_5752VENDOR_ST_M45PE40:
11083 tp->nvram_jedecnum = JEDEC_ST;
11084 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11085 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11086 tp->nvram_pagesize = 256;
11087 break;
1b27777a
MC		 11088 }
11089}
11090
6b91fa02
MC		 11091static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11092{
11093 u32 nvcfg1, protect = 0;
11094
11095 nvcfg1 = tr32(NVRAM_CFG1);
11096
11097 /* NVRAM protection for TPM */
11098 if (nvcfg1 & (1 << 27)) {
11099 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11100 protect = 1;
11101 }
11102
11103 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11104 switch (nvcfg1) {
8590a603
MC		 11105 case FLASH_5761VENDOR_ATMEL_ADB021D:
11106 case FLASH_5761VENDOR_ATMEL_ADB041D:
11107 case FLASH_5761VENDOR_ATMEL_ADB081D:
11108 case FLASH_5761VENDOR_ATMEL_ADB161D:
11109 case FLASH_5761VENDOR_ATMEL_MDB021D:
11110 case FLASH_5761VENDOR_ATMEL_MDB041D:
11111 case FLASH_5761VENDOR_ATMEL_MDB081D:
11112 case FLASH_5761VENDOR_ATMEL_MDB161D:
11113 tp->nvram_jedecnum = JEDEC_ATMEL;
11114 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11115 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11116 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11117 tp->nvram_pagesize = 256;
11118 break;
11119 case FLASH_5761VENDOR_ST_A_M45PE20:
11120 case FLASH_5761VENDOR_ST_A_M45PE40:
11121 case FLASH_5761VENDOR_ST_A_M45PE80:
11122 case FLASH_5761VENDOR_ST_A_M45PE16:
11123 case FLASH_5761VENDOR_ST_M_M45PE20:
11124 case FLASH_5761VENDOR_ST_M_M45PE40:
11125 case FLASH_5761VENDOR_ST_M_M45PE80:
11126 case FLASH_5761VENDOR_ST_M_M45PE16:
11127 tp->nvram_jedecnum = JEDEC_ST;
11128 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11129 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11130 tp->nvram_pagesize = 256;
11131 break;
6b91fa02
MC		 11132 }
11133
11134 if (protect) {
11135 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11136 } else {
11137 switch (nvcfg1) {
8590a603
MC		 11138 case FLASH_5761VENDOR_ATMEL_ADB161D:
11139 case FLASH_5761VENDOR_ATMEL_MDB161D:
11140 case FLASH_5761VENDOR_ST_A_M45PE16:
11141 case FLASH_5761VENDOR_ST_M_M45PE16:
11142 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11143 break;
11144 case FLASH_5761VENDOR_ATMEL_ADB081D:
11145 case FLASH_5761VENDOR_ATMEL_MDB081D:
11146 case FLASH_5761VENDOR_ST_A_M45PE80:
11147 case FLASH_5761VENDOR_ST_M_M45PE80:
11148 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11149 break;
11150 case FLASH_5761VENDOR_ATMEL_ADB041D:
11151 case FLASH_5761VENDOR_ATMEL_MDB041D:
11152 case FLASH_5761VENDOR_ST_A_M45PE40:
11153 case FLASH_5761VENDOR_ST_M_M45PE40:
11154 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11155 break;
11156 case FLASH_5761VENDOR_ATMEL_ADB021D:
11157 case FLASH_5761VENDOR_ATMEL_MDB021D:
11158 case FLASH_5761VENDOR_ST_A_M45PE20:
11159 case FLASH_5761VENDOR_ST_M_M45PE20:
11160 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11161 break;
6b91fa02
MC		 11162 }
11163 }
11164}
11165
b5d3772c
MC		 11166static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11167{
11168 tp->nvram_jedecnum = JEDEC_ATMEL;
11169 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11170 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11171}
11172
321d32a0
MC		 11173static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11174{
11175 u32 nvcfg1;
11176
11177 nvcfg1 = tr32(NVRAM_CFG1);
11178
11179 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11180 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11181 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11182 tp->nvram_jedecnum = JEDEC_ATMEL;
11183 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11184 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11185
11186 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11187 tw32(NVRAM_CFG1, nvcfg1);
11188 return;
11189 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11190 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11191 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11192 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11193 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11194 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11195 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11196 tp->nvram_jedecnum = JEDEC_ATMEL;
11197 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11198 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11199
11200 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11201 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11202 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11203 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11204 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11205 break;
11206 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11207 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11208 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11209 break;
11210 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11211 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11212 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11213 break;
11214 }
11215 break;
11216 case FLASH_5752VENDOR_ST_M45PE10:
11217 case FLASH_5752VENDOR_ST_M45PE20:
11218 case FLASH_5752VENDOR_ST_M45PE40:
11219 tp->nvram_jedecnum = JEDEC_ST;
11220 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11221 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11222
11223 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11224 case FLASH_5752VENDOR_ST_M45PE10:
11225 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11226 break;
11227 case FLASH_5752VENDOR_ST_M45PE20:
11228 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11229 break;
11230 case FLASH_5752VENDOR_ST_M45PE40:
11231 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11232 break;
11233 }
11234 break;
11235 default:
df259d8c 11236 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11237 return;
11238 }
11239
a1b950d5
MC		 11240 tg3_nvram_get_pagesize(tp, nvcfg1);
11241 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11242 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11243}
11244
11245
11246static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11247{
11248 u32 nvcfg1;
11249
11250 nvcfg1 = tr32(NVRAM_CFG1);
11251
11252 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11253 case FLASH_5717VENDOR_ATMEL_EEPROM:
11254 case FLASH_5717VENDOR_MICRO_EEPROM:
11255 tp->nvram_jedecnum = JEDEC_ATMEL;
11256 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11257 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11258
11259 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11260 tw32(NVRAM_CFG1, nvcfg1);
11261 return;
11262 case FLASH_5717VENDOR_ATMEL_MDB011D:
11263 case FLASH_5717VENDOR_ATMEL_ADB011B:
11264 case FLASH_5717VENDOR_ATMEL_ADB011D:
11265 case FLASH_5717VENDOR_ATMEL_MDB021D:
11266 case FLASH_5717VENDOR_ATMEL_ADB021B:
11267 case FLASH_5717VENDOR_ATMEL_ADB021D:
11268 case FLASH_5717VENDOR_ATMEL_45USPT:
11269 tp->nvram_jedecnum = JEDEC_ATMEL;
11270 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11271 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11272
11273 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11274 case FLASH_5717VENDOR_ATMEL_MDB021D:
11275 case FLASH_5717VENDOR_ATMEL_ADB021B:
11276 case FLASH_5717VENDOR_ATMEL_ADB021D:
11277 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11278 break;
11279 default:
11280 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11281 break;
11282 }
321d32a0 11283 break;
a1b950d5
MC		 11284 case FLASH_5717VENDOR_ST_M_M25PE10:
11285 case FLASH_5717VENDOR_ST_A_M25PE10:
11286 case FLASH_5717VENDOR_ST_M_M45PE10:
11287 case FLASH_5717VENDOR_ST_A_M45PE10:
11288 case FLASH_5717VENDOR_ST_M_M25PE20:
11289 case FLASH_5717VENDOR_ST_A_M25PE20:
11290 case FLASH_5717VENDOR_ST_M_M45PE20:
11291 case FLASH_5717VENDOR_ST_A_M45PE20:
11292 case FLASH_5717VENDOR_ST_25USPT:
11293 case FLASH_5717VENDOR_ST_45USPT:
11294 tp->nvram_jedecnum = JEDEC_ST;
11295 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11296 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11297
11298 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11299 case FLASH_5717VENDOR_ST_M_M25PE20:
11300 case FLASH_5717VENDOR_ST_A_M25PE20:
11301 case FLASH_5717VENDOR_ST_M_M45PE20:
11302 case FLASH_5717VENDOR_ST_A_M45PE20:
11303 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11304 break;
11305 default:
11306 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11307 break;
11308 }
321d32a0 11309 break;
a1b950d5
MC		 11310 default:
11311 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11312 return;
321d32a0 11313 }
a1b950d5
MC		 11314
11315 tg3_nvram_get_pagesize(tp, nvcfg1);
11316 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11317 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11318}
11319
1da177e4
LT		 11320/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11321static void __devinit tg3_nvram_init(struct tg3 *tp)
11322{
1da177e4
LT		 11323 tw32_f(GRC_EEPROM_ADDR,
11324 (EEPROM_ADDR_FSM_RESET |
11325 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11326 EEPROM_ADDR_CLKPERD_SHIFT)));
11327
9d57f01c 11328 msleep(1);
1da177e4
LT		 11329
11330 /* Enable seeprom accesses. */
11331 tw32_f(GRC_LOCAL_CTRL,
11332 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11333 udelay(100);
11334
11335 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11336 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11337 tp->tg3_flags |= TG3_FLAG_NVRAM;
11338
ec41c7df
MC		 11339 if (tg3_nvram_lock(tp)) {
11340 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11341 "tg3_nvram_init failed.\n", tp->dev->name);
11342 return;
11343 }
e6af301b 11344 tg3_enable_nvram_access(tp);
1da177e4 11345
989a9d23
MC		 11346 tp->nvram_size = 0;
11347
361b4ac2
MC		 11348 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11349 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11350 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11351 tg3_get_5755_nvram_info(tp);
d30cdd28 11352 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11353 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11355 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11356 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11357 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11358 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11359 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11360 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11361 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11362 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11363 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11364 else
11365 tg3_get_nvram_info(tp);
11366
989a9d23
MC		 11367 if (tp->nvram_size == 0)
11368 tg3_get_nvram_size(tp);
1da177e4 11369
e6af301b 11370 tg3_disable_nvram_access(tp);
381291b7 11371 tg3_nvram_unlock(tp);
1da177e4
LT		 11372
11373 } else {
11374 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11375
11376 tg3_get_eeprom_size(tp);
11377 }
11378}
11379
1da177e4
LT		 11380static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11381 u32 offset, u32 len, u8 *buf)
11382{
11383 int i, j, rc = 0;
11384 u32 val;
11385
11386 for (i = 0; i < len; i += 4) {
b9fc7dc5 11387 u32 addr;
a9dc529d 11388 __be32 data;
1da177e4
LT		 11389
11390 addr = offset + i;
11391
11392 memcpy(&data, buf + i, 4);
11393
62cedd11
MC		 11394 /*
11395 * The SEEPROM interface expects the data to always be opposite
11396 * the native endian format. We accomplish this by reversing
11397 * all the operations that would have been performed on the
11398 * data from a call to tg3_nvram_read_be32().
11399 */
11400 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11401
11402 val = tr32(GRC_EEPROM_ADDR);
11403 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11404
11405 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11406 EEPROM_ADDR_READ);
11407 tw32(GRC_EEPROM_ADDR, val |
11408 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11409 (addr & EEPROM_ADDR_ADDR_MASK) |
11410 EEPROM_ADDR_START |
11411 EEPROM_ADDR_WRITE);
6aa20a22 11412
9d57f01c 11413 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11414 val = tr32(GRC_EEPROM_ADDR);
11415
11416 if (val & EEPROM_ADDR_COMPLETE)
11417 break;
9d57f01c 11418 msleep(1);
1da177e4
LT		 11419 }
11420 if (!(val & EEPROM_ADDR_COMPLETE)) {
11421 rc = -EBUSY;
11422 break;
11423 }
11424 }
11425
11426 return rc;
11427}
11428
11429/* offset and length are dword aligned */
11430static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11431 u8 *buf)
11432{
11433 int ret = 0;
11434 u32 pagesize = tp->nvram_pagesize;
11435 u32 pagemask = pagesize - 1;
11436 u32 nvram_cmd;
11437 u8 *tmp;
11438
11439 tmp = kmalloc(pagesize, GFP_KERNEL);
11440 if (tmp == NULL)
11441 return -ENOMEM;
11442
11443 while (len) {
11444 int j;
e6af301b 11445 u32 phy_addr, page_off, size;
1da177e4
LT		 11446
11447 phy_addr = offset & ~pagemask;
6aa20a22 11448
1da177e4 11449 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11450 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11451 (__be32 *) (tmp + j));
11452 if (ret)
1da177e4
LT		 11453 break;
11454 }
11455 if (ret)
11456 break;
11457
11458 page_off = offset & pagemask;
11459 size = pagesize;
11460 if (len < size)
11461 size = len;
11462
11463 len -= size;
11464
11465 memcpy(tmp + page_off, buf, size);
11466
11467 offset = offset + (pagesize - page_off);
11468
e6af301b 11469 tg3_enable_nvram_access(tp);
1da177e4
LT		 11470
11471 /*
11472 * Before we can erase the flash page, we need
11473 * to issue a special "write enable" command.
11474 */
11475 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11476
11477 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11478 break;
11479
11480 /* Erase the target page */
11481 tw32(NVRAM_ADDR, phy_addr);
11482
11483 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11484 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11485
11486 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11487 break;
11488
11489 /* Issue another write enable to start the write. */
11490 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11491
11492 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11493 break;
11494
11495 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11496 __be32 data;
1da177e4 11497
b9fc7dc5 11498 data = *((__be32 *) (tmp + j));
a9dc529d 11499
b9fc7dc5 11500 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11501
11502 tw32(NVRAM_ADDR, phy_addr + j);
11503
11504 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11505 NVRAM_CMD_WR;
11506
11507 if (j == 0)
11508 nvram_cmd |= NVRAM_CMD_FIRST;
11509 else if (j == (pagesize - 4))
11510 nvram_cmd |= NVRAM_CMD_LAST;
11511
11512 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11513 break;
11514 }
11515 if (ret)
11516 break;
11517 }
11518
11519 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11520 tg3_nvram_exec_cmd(tp, nvram_cmd);
11521
11522 kfree(tmp);
11523
11524 return ret;
11525}
11526
11527/* offset and length are dword aligned */
11528static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11529 u8 *buf)
11530{
11531 int i, ret = 0;
11532
11533 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11534 u32 page_off, phy_addr, nvram_cmd;
11535 __be32 data;
1da177e4
LT		 11536
11537 memcpy(&data, buf + i, 4);
b9fc7dc5 11538 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11539
11540 page_off = offset % tp->nvram_pagesize;
11541
1820180b 11542 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11543
11544 tw32(NVRAM_ADDR, phy_addr);
11545
11546 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11547
11548 if ((page_off == 0) || (i == 0))
11549 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11550 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11551 nvram_cmd |= NVRAM_CMD_LAST;
11552
11553 if (i == (len - 4))
11554 nvram_cmd |= NVRAM_CMD_LAST;
11555
321d32a0
MC		 11556 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11557 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11558 (tp->nvram_jedecnum == JEDEC_ST) &&
11559 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11560
11561 if ((ret = tg3_nvram_exec_cmd(tp,
11562 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11563 NVRAM_CMD_DONE)))
11564
11565 break;
11566 }
11567 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11568 /* We always do complete word writes to eeprom. */
11569 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11570 }
11571
11572 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11573 break;
11574 }
11575 return ret;
11576}
11577
11578/* offset and length are dword aligned */
11579static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11580{
11581 int ret;
11582
1da177e4 11583 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11584 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11585 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11586 udelay(40);
11587 }
11588
11589 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11590 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11591 }
11592 else {
11593 u32 grc_mode;
11594
ec41c7df
MC		 11595 ret = tg3_nvram_lock(tp);
11596 if (ret)
11597 return ret;
1da177e4 11598
e6af301b
MC		 11599 tg3_enable_nvram_access(tp);
11600 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11601 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11602 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11603
11604 grc_mode = tr32(GRC_MODE);
11605 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11606
11607 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11608 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11609
11610 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11611 buf);
11612 }
11613 else {
11614 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11615 buf);
11616 }
11617
11618 grc_mode = tr32(GRC_MODE);
11619 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11620
e6af301b 11621 tg3_disable_nvram_access(tp);
1da177e4
LT		 11622 tg3_nvram_unlock(tp);
11623 }
11624
11625 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11626 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11627 udelay(40);
11628 }
11629
11630 return ret;
11631}
11632
11633struct subsys_tbl_ent {
11634 u16 subsys_vendor, subsys_devid;
11635 u32 phy_id;
11636};
11637
11638static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11639 /* Broadcom boards. */
11640 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11641 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11642 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11643 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11644 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11645 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11646 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11647 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11648 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11649 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11650 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11651
11652 /* 3com boards. */
11653 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11654 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11655 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11656 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11657 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11658
11659 /* DELL boards. */
11660 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11661 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11662 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11663 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11664
11665 /* Compaq boards. */
11666 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11667 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11668 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11669 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11670 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11671
11672 /* IBM boards. */
11673 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11674};
11675
11676static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11677{
11678 int i;
11679
11680 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11681 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11682 tp->pdev->subsystem_vendor) &&
11683 (subsys_id_to_phy_id[i].subsys_devid ==
11684 tp->pdev->subsystem_device))
11685 return &subsys_id_to_phy_id[i];
11686 }
11687 return NULL;
11688}
11689
7d0c41ef 11690static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11691{
1da177e4 11692 u32 val;
caf636c7
MC		 11693 u16 pmcsr;
11694
11695 /* On some early chips the SRAM cannot be accessed in D3hot state,
11696 * so need make sure we're in D0.
11697 */
11698 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11699 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11700 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11701 msleep(1);
7d0c41ef
MC		 11702
11703 /* Make sure register accesses (indirect or otherwise)
11704 * will function correctly.
11705 */
11706 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11707 tp->misc_host_ctrl);
1da177e4 11708
f49639e6
DM		 11709 /* The memory arbiter has to be enabled in order for SRAM accesses
11710 * to succeed. Normally on powerup the tg3 chip firmware will make
11711 * sure it is enabled, but other entities such as system netboot
11712 * code might disable it.
11713 */
11714 val = tr32(MEMARB_MODE);
11715 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11716
1da177e4 11717 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11718 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11719
a85feb8c
GZ		 11720 /* Assume an onboard device and WOL capable by default. */
11721 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11722
b5d3772c 11723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11724 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11725 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11726 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11727 }
0527ba35
MC		 11728 val = tr32(VCPU_CFGSHDW);
11729 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11730 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11731 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11732 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11733 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11734 goto done;
b5d3772c
MC		 11735 }
11736
1da177e4
LT		 11737 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11738 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11739 u32 nic_cfg, led_cfg;
a9daf367 11740 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11741 int eeprom_phy_serdes = 0;
1da177e4
LT		 11742
11743 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11744 tp->nic_sram_data_cfg = nic_cfg;
11745
11746 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11747 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11748 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11749 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11750 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11751 (ver > 0) && (ver < 0x100))
11752 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11753
a9daf367
MC		 11754 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11755 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11756
1da177e4
LT		 11757 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11758 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11759 eeprom_phy_serdes = 1;
11760
11761 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11762 if (nic_phy_id != 0) {
11763 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11764 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11765
11766 eeprom_phy_id = (id1 >> 16) << 10;
11767 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11768 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11769 } else
11770 eeprom_phy_id = 0;
11771
7d0c41ef 11772 tp->phy_id = eeprom_phy_id;
747e8f8b 11773 if (eeprom_phy_serdes) {
a4e2b347 11774 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11775 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11776 else
11777 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11778 }
7d0c41ef 11779
cbf46853 11780 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11781 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11782 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11783 else
1da177e4
LT		 11784 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11785
11786 switch (led_cfg) {
11787 default:
11788 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11789 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11790 break;
11791
11792 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11793 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11794 break;
11795
11796 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11797 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11798
11799 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11800 * read on some older 5700/5701 bootcode.
11801 */
11802 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11803 ASIC_REV_5700 ||
11804 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11805 ASIC_REV_5701)
11806 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11807
1da177e4
LT		 11808 break;
11809
11810 case SHASTA_EXT_LED_SHARED:
11811 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11812 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11813 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11814 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11815 LED_CTRL_MODE_PHY_2);
11816 break;
11817
11818 case SHASTA_EXT_LED_MAC:
11819 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11820 break;
11821
11822 case SHASTA_EXT_LED_COMBO:
11823 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11824 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11825 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11826 LED_CTRL_MODE_PHY_2);
11827 break;
11828
855e1111 11829 }
1da177e4
LT		 11830
11831 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11832 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11833 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11834 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11835
b2a5c19c
MC		 11836 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11837 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11838
9d26e213 11839 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11840 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11841 if ((tp->pdev->subsystem_vendor ==
11842 PCI_VENDOR_ID_ARIMA) &&
11843 (tp->pdev->subsystem_device == 0x205a ||
11844 tp->pdev->subsystem_device == 0x2063))
11845 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11846 } else {
f49639e6 11847 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11848 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11849 }
1da177e4
LT		 11850
11851 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11852 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11853 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11854 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11855 }
b2b98d4a
MC		 11856
11857 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11858 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11859 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11860
a85feb8c
GZ		 11861 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11862 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11863 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11864
12dac075 11865 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11866 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11867 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11868
1da177e4
LT		 11869 if (cfg2 & (1 << 17))
11870 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11871
11872 /* serdes signal pre-emphasis in register 0x590 set by */
11873 /* bootcode if bit 18 is set */
11874 if (cfg2 & (1 << 18))
11875 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11876
321d32a0
MC		 11877 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11878 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11879 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11880 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11881
8ed5d97e
MC		 11882 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11883 u32 cfg3;
11884
11885 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11886 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11887 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11888 }
a9daf367
MC		 11889
11890 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11891 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11892 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11893 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11894 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11895 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11896 }
05ac4cb7
MC		 11897done:
11898 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11899 device_set_wakeup_enable(&tp->pdev->dev,
11900 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11901}
11902
b2a5c19c
MC		 11903static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11904{
11905 int i;
11906 u32 val;
11907
11908 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11909 tw32(OTP_CTRL, cmd);
11910
11911 /* Wait for up to 1 ms for command to execute. */
11912 for (i = 0; i < 100; i++) {
11913 val = tr32(OTP_STATUS);
11914 if (val & OTP_STATUS_CMD_DONE)
11915 break;
11916 udelay(10);
11917 }
11918
11919 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11920}
11921
11922/* Read the gphy configuration from the OTP region of the chip. The gphy
11923 * configuration is a 32-bit value that straddles the alignment boundary.
11924 * We do two 32-bit reads and then shift and merge the results.
11925 */
11926static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11927{
11928 u32 bhalf_otp, thalf_otp;
11929
11930 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11931
11932 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11933 return 0;
11934
11935 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11936
11937 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11938 return 0;
11939
11940 thalf_otp = tr32(OTP_READ_DATA);
11941
11942 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11943
11944 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11945 return 0;
11946
11947 bhalf_otp = tr32(OTP_READ_DATA);
11948
11949 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11950}
11951
7d0c41ef
MC		 11952static int __devinit tg3_phy_probe(struct tg3 *tp)
11953{
11954 u32 hw_phy_id_1, hw_phy_id_2;
11955 u32 hw_phy_id, hw_phy_id_masked;
11956 int err;
1da177e4 11957
b02fd9e3
MC		 11958 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11959 return tg3_phy_init(tp);
11960
1da177e4 11961 /* Reading the PHY ID register can conflict with ASF
877d0310 11962 * firmware access to the PHY hardware.
1da177e4
LT		 11963 */
11964 err = 0;
0d3031d9
MC		 11965 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11966 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11967 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11968 } else {
11969 /* Now read the physical PHY_ID from the chip and verify
11970 * that it is sane. If it doesn't look good, we fall back
11971 * to either the hard-coded table based PHY_ID and failing
11972 * that the value found in the eeprom area.
11973 */
11974 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11975 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11976
11977 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11978 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11979 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11980
11981 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11982 }
11983
11984 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11985 tp->phy_id = hw_phy_id;
11986 if (hw_phy_id_masked == PHY_ID_BCM8002)
11987 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11988 else
11989 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11990 } else {
7d0c41ef
MC		 11991 if (tp->phy_id != PHY_ID_INVALID) {
11992 /* Do nothing, phy ID already set up in
11993 * tg3_get_eeprom_hw_cfg().
11994 */
1da177e4
LT		 11995 } else {
11996 struct subsys_tbl_ent *p;
11997
11998 /* No eeprom signature? Try the hardcoded
11999 * subsys device table.
12000 */
12001 p = lookup_by_subsys(tp);
12002 if (!p)
12003 return -ENODEV;
12004
12005 tp->phy_id = p->phy_id;
12006 if (!tp->phy_id ||
12007 tp->phy_id == PHY_ID_BCM8002)
12008 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12009 }
12010 }
12011
747e8f8b 12012 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12013 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12014 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12015 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12016
12017 tg3_readphy(tp, MII_BMSR, &bmsr);
12018 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12019 (bmsr & BMSR_LSTATUS))
12020 goto skip_phy_reset;
6aa20a22 12021
1da177e4
LT		 12022 err = tg3_phy_reset(tp);
12023 if (err)
12024 return err;
12025
12026 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12027 ADVERTISE_100HALF | ADVERTISE_100FULL |
12028 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12029 tg3_ctrl = 0;
12030 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12031 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12032 MII_TG3_CTRL_ADV_1000_FULL);
12033 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12034 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12035 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12036 MII_TG3_CTRL_ENABLE_AS_MASTER);
12037 }
12038
3600d918
MC		 12039 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12040 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12041 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12042 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12043 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12044
12045 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12046 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12047
12048 tg3_writephy(tp, MII_BMCR,
12049 BMCR_ANENABLE | BMCR_ANRESTART);
12050 }
12051 tg3_phy_set_wirespeed(tp);
12052
12053 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12054 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12055 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12056 }
12057
12058skip_phy_reset:
12059 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12060 err = tg3_init_5401phy_dsp(tp);
12061 if (err)
12062 return err;
12063 }
12064
12065 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12066 err = tg3_init_5401phy_dsp(tp);
12067 }
12068
747e8f8b 12069 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12070 tp->link_config.advertising =
12071 (ADVERTISED_1000baseT_Half |
12072 ADVERTISED_1000baseT_Full |
12073 ADVERTISED_Autoneg |
12074 ADVERTISED_FIBRE);
12075 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12076 tp->link_config.advertising &=
12077 ~(ADVERTISED_1000baseT_Half |
12078 ADVERTISED_1000baseT_Full);
12079
12080 return err;
12081}
12082
12083static void __devinit tg3_read_partno(struct tg3 *tp)
12084{
6d348f2c 12085 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12086 unsigned int i;
1b27777a 12087 u32 magic;
1da177e4 12088
df259d8c
MC		 12089 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12090 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12091 goto out_not_found;
1da177e4 12092
1820180b 12093 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12094 for (i = 0; i < 256; i += 4) {
12095 u32 tmp;
1da177e4 12096
6d348f2c
MC		 12097 /* The data is in little-endian format in NVRAM.
12098 * Use the big-endian read routines to preserve
12099 * the byte order as it exists in NVRAM.
12100 */
12101 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12102 goto out_not_found;
12103
6d348f2c 12104 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12105 }
12106 } else {
12107 int vpd_cap;
12108
12109 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12110 for (i = 0; i < 256; i += 4) {
12111 u32 tmp, j = 0;
b9fc7dc5 12112 __le32 v;
1b27777a
MC		 12113 u16 tmp16;
12114
12115 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12116 i);
12117 while (j++ < 100) {
12118 pci_read_config_word(tp->pdev, vpd_cap +
12119 PCI_VPD_ADDR, &tmp16);
12120 if (tmp16 & 0x8000)
12121 break;
12122 msleep(1);
12123 }
f49639e6
DM		 12124 if (!(tmp16 & 0x8000))
12125 goto out_not_found;
12126
1b27777a
MC		 12127 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12128 &tmp);
b9fc7dc5 12129 v = cpu_to_le32(tmp);
6d348f2c 12130 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12131 }
1da177e4
LT		 12132 }
12133
12134 /* Now parse and find the part number. */
af2c6a4a 12135 for (i = 0; i < 254; ) {
1da177e4 12136 unsigned char val = vpd_data[i];
af2c6a4a 12137 unsigned int block_end;
1da177e4
LT		 12138
12139 if (val == 0x82 || val == 0x91) {
12140 i = (i + 3 +
12141 (vpd_data[i + 1] +
12142 (vpd_data[i + 2] << 8)));
12143 continue;
12144 }
12145
12146 if (val != 0x90)
12147 goto out_not_found;
12148
12149 block_end = (i + 3 +
12150 (vpd_data[i + 1] +
12151 (vpd_data[i + 2] << 8)));
12152 i += 3;
af2c6a4a
MC		 12153
12154 if (block_end > 256)
12155 goto out_not_found;
12156
12157 while (i < (block_end - 2)) {
1da177e4
LT		 12158 if (vpd_data[i + 0] == 'P' &&
12159 vpd_data[i + 1] == 'N') {
12160 int partno_len = vpd_data[i + 2];
12161
af2c6a4a
MC		 12162 i += 3;
12163 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12164 goto out_not_found;
12165
12166 memcpy(tp->board_part_number,
af2c6a4a 12167 &vpd_data[i], partno_len);
1da177e4
LT		 12168
12169 /* Success. */
12170 return;
12171 }
af2c6a4a 12172 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12173 }
12174
12175 /* Part number not found. */
12176 goto out_not_found;
12177 }
12178
12179out_not_found:
b5d3772c
MC		 12180 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12181 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12182 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12183 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12184 strcpy(tp->board_part_number, "BCM57780");
12185 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12186 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12187 strcpy(tp->board_part_number, "BCM57760");
12188 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12189 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12190 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12191 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12192 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12193 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12194 else
12195 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12196}
12197
9c8a620e
MC		 12198static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12199{
12200 u32 val;
12201
e4f34110 12202 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12203 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12204 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12205 val != 0)
12206 return 0;
12207
12208 return 1;
12209}
12210
acd9c119
MC		 12211static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12212{
ff3a7cb2 12213 u32 val, offset, start, ver_offset;
acd9c119 12214 int i;
ff3a7cb2 12215 bool newver = false;
acd9c119
MC		 12216
12217 if (tg3_nvram_read(tp, 0xc, &offset) ||
12218 tg3_nvram_read(tp, 0x4, &start))
12219 return;
12220
12221 offset = tg3_nvram_logical_addr(tp, offset);
12222
ff3a7cb2 12223 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12224 return;
12225
ff3a7cb2
MC		 12226 if ((val & 0xfc000000) == 0x0c000000) {
12227 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12228 return;
12229
ff3a7cb2
MC		 12230 if (val == 0)
12231 newver = true;
12232 }
12233
12234 if (newver) {
12235 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12236 return;
12237
12238 offset = offset + ver_offset - start;
12239 for (i = 0; i < 16; i += 4) {
12240 __be32 v;
12241 if (tg3_nvram_read_be32(tp, offset + i, &v))
12242 return;
12243
12244 memcpy(tp->fw_ver + i, &v, sizeof(v));
12245 }
12246 } else {
12247 u32 major, minor;
12248
12249 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12250 return;
12251
12252 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12253 TG3_NVM_BCVER_MAJSFT;
12254 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12255 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12256 }
12257}
12258
a6f6cb1c
MC		 12259static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12260{
12261 u32 val, major, minor;
12262
12263 /* Use native endian representation */
12264 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12265 return;
12266
12267 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12268 TG3_NVM_HWSB_CFG1_MAJSFT;
12269 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12270 TG3_NVM_HWSB_CFG1_MINSFT;
12271
12272 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12273}
12274
dfe00d7d
MC		 12275static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12276{
12277 u32 offset, major, minor, build;
12278
12279 tp->fw_ver[0] = 's';
12280 tp->fw_ver[1] = 'b';
12281 tp->fw_ver[2] = '\0';
12282
12283 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12284 return;
12285
12286 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12287 case TG3_EEPROM_SB_REVISION_0:
12288 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12289 break;
12290 case TG3_EEPROM_SB_REVISION_2:
12291 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12292 break;
12293 case TG3_EEPROM_SB_REVISION_3:
12294 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12295 break;
12296 default:
12297 return;
12298 }
12299
e4f34110 12300 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12301 return;
12302
12303 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12304 TG3_EEPROM_SB_EDH_BLD_SHFT;
12305 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12306 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12307 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12308
12309 if (minor > 99 || build > 26)
12310 return;
12311
12312 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12313
12314 if (build > 0) {
12315 tp->fw_ver[8] = 'a' + build - 1;
12316 tp->fw_ver[9] = '\0';
12317 }
12318}
12319
acd9c119 12320static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12321{
12322 u32 val, offset, start;
acd9c119 12323 int i, vlen;
9c8a620e
MC		 12324
12325 for (offset = TG3_NVM_DIR_START;
12326 offset < TG3_NVM_DIR_END;
12327 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12328 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12329 return;
12330
9c8a620e
MC		 12331 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12332 break;
12333 }
12334
12335 if (offset == TG3_NVM_DIR_END)
12336 return;
12337
12338 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12339 start = 0x08000000;
e4f34110 12340 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12341 return;
12342
e4f34110 12343 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12344 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12345 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12346 return;
12347
12348 offset += val - start;
12349
acd9c119 12350 vlen = strlen(tp->fw_ver);
9c8a620e 12351
acd9c119
MC		 12352 tp->fw_ver[vlen++] = ',';
12353 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12354
12355 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12356 __be32 v;
12357 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12358 return;
12359
b9fc7dc5 12360 offset += sizeof(v);
c4e6575c 12361
acd9c119
MC		 12362 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12363 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12364 break;
c4e6575c 12365 }
9c8a620e 12366
acd9c119
MC		 12367 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12368 vlen += sizeof(v);
c4e6575c 12369 }
acd9c119
MC		 12370}
12371
7fd76445
MC		 12372static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12373{
12374 int vlen;
12375 u32 apedata;
12376
12377 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12378 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12379 return;
12380
12381 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12382 if (apedata != APE_SEG_SIG_MAGIC)
12383 return;
12384
12385 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12386 if (!(apedata & APE_FW_STATUS_READY))
12387 return;
12388
12389 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12390
12391 vlen = strlen(tp->fw_ver);
12392
12393 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12394 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12395 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12396 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12397 (apedata & APE_FW_VERSION_BLDMSK));
12398}
12399
acd9c119
MC		 12400static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12401{
12402 u32 val;
12403
df259d8c
MC		 12404 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12405 tp->fw_ver[0] = 's';
12406 tp->fw_ver[1] = 'b';
12407 tp->fw_ver[2] = '\0';
12408
12409 return;
12410 }
12411
acd9c119
MC		 12412 if (tg3_nvram_read(tp, 0, &val))
12413 return;
12414
12415 if (val == TG3_EEPROM_MAGIC)
12416 tg3_read_bc_ver(tp);
12417 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12418 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12419 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12420 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12421 else
12422 return;
12423
12424 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12425 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12426 return;
12427
12428 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12429
12430 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12431}
12432
7544b097
MC		 12433static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12434
1da177e4
LT		 12435static int __devinit tg3_get_invariants(struct tg3 *tp)
12436{
12437 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12438 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12439 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12440 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12441 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12442 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12443 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12444 { },
12445 };
12446 u32 misc_ctrl_reg;
1da177e4
LT		 12447 u32 pci_state_reg, grc_misc_cfg;
12448 u32 val;
12449 u16 pci_cmd;
5e7dfd0f 12450 int err;
1da177e4 12451
1da177e4
LT		 12452 /* Force memory write invalidate off. If we leave it on,
12453 * then on 5700_BX chips we have to enable a workaround.
12454 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12455 * to match the cacheline size. The Broadcom driver have this
12456 * workaround but turns MWI off all the times so never uses
12457 * it. This seems to suggest that the workaround is insufficient.
12458 */
12459 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12460 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12461 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12462
12463 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12464 * has the register indirect write enable bit set before
12465 * we try to access any of the MMIO registers. It is also
12466 * critical that the PCI-X hw workaround situation is decided
12467 * before that as well.
12468 */
12469 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12470 &misc_ctrl_reg);
12471
12472 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12473 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12475 u32 prod_id_asic_rev;
12476
f6eb9b1f
MC		 12477 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12478 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12479 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12480 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12481 pci_read_config_dword(tp->pdev,
12482 TG3PCI_GEN2_PRODID_ASICREV,
12483 &prod_id_asic_rev);
12484 else
12485 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12486 &prod_id_asic_rev);
12487
321d32a0 12488 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12489 }
1da177e4 12490
ff645bec
MC		 12491 /* Wrong chip ID in 5752 A0. This code can be removed later
12492 * as A0 is not in production.
12493 */
12494 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12495 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12496
6892914f
MC		 12497 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12498 * we need to disable memory and use config. cycles
12499 * only to access all registers. The 5702/03 chips
12500 * can mistakenly decode the special cycles from the
12501 * ICH chipsets as memory write cycles, causing corruption
12502 * of register and memory space. Only certain ICH bridges
12503 * will drive special cycles with non-zero data during the
12504 * address phase which can fall within the 5703's address
12505 * range. This is not an ICH bug as the PCI spec allows
12506 * non-zero address during special cycles. However, only
12507 * these ICH bridges are known to drive non-zero addresses
12508 * during special cycles.
12509 *
12510 * Since special cycles do not cross PCI bridges, we only
12511 * enable this workaround if the 5703 is on the secondary
12512 * bus of these ICH bridges.
12513 */
12514 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12515 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12516 static struct tg3_dev_id {
12517 u32 vendor;
12518 u32 device;
12519 u32 rev;
12520 } ich_chipsets[] = {
12521 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12522 PCI_ANY_ID },
12523 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12524 PCI_ANY_ID },
12525 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12526 0xa },
12527 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12528 PCI_ANY_ID },
12529 { },
12530 };
12531 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12532 struct pci_dev *bridge = NULL;
12533
12534 while (pci_id->vendor != 0) {
12535 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12536 bridge);
12537 if (!bridge) {
12538 pci_id++;
12539 continue;
12540 }
12541 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12542 if (bridge->revision > pci_id->rev)
6892914f
MC		 12543 continue;
12544 }
12545 if (bridge->subordinate &&
12546 (bridge->subordinate->number ==
12547 tp->pdev->bus->number)) {
12548
12549 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12550 pci_dev_put(bridge);
12551 break;
12552 }
12553 }
12554 }
12555
41588ba1
MC		 12556 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12557 static struct tg3_dev_id {
12558 u32 vendor;
12559 u32 device;
12560 } bridge_chipsets[] = {
12561 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12562 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12563 { },
12564 };
12565 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12566 struct pci_dev *bridge = NULL;
12567
12568 while (pci_id->vendor != 0) {
12569 bridge = pci_get_device(pci_id->vendor,
12570 pci_id->device,
12571 bridge);
12572 if (!bridge) {
12573 pci_id++;
12574 continue;
12575 }
12576 if (bridge->subordinate &&
12577 (bridge->subordinate->number <=
12578 tp->pdev->bus->number) &&
12579 (bridge->subordinate->subordinate >=
12580 tp->pdev->bus->number)) {
12581 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12582 pci_dev_put(bridge);
12583 break;
12584 }
12585 }
12586 }
12587
4a29cc2e
MC		 12588 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12589 * DMA addresses > 40-bit. This bridge may have other additional
12590 * 57xx devices behind it in some 4-port NIC designs for example.
12591 * Any tg3 device found behind the bridge will also need the 40-bit
12592 * DMA workaround.
12593 */
a4e2b347
MC		 12594 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12595 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12596 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12597 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12598 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12599 }
4a29cc2e
MC		 12600 else {
12601 struct pci_dev *bridge = NULL;
12602
12603 do {
12604 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12605 PCI_DEVICE_ID_SERVERWORKS_EPB,
12606 bridge);
12607 if (bridge && bridge->subordinate &&
12608 (bridge->subordinate->number <=
12609 tp->pdev->bus->number) &&
12610 (bridge->subordinate->subordinate >=
12611 tp->pdev->bus->number)) {
12612 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12613 pci_dev_put(bridge);
12614 break;
12615 }
12616 } while (bridge);
12617 }
4cf78e4f 12618
1da177e4
LT		 12619 /* Initialize misc host control in PCI block. */
12620 tp->misc_host_ctrl |= (misc_ctrl_reg &
12621 MISC_HOST_CTRL_CHIPREV);
12622 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12623 tp->misc_host_ctrl);
12624
f6eb9b1f
MC		 12625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12626 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12627 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12628 tp->pdev_peer = tg3_find_peer(tp);
12629
321d32a0
MC		 12630 /* Intentionally exclude ASIC_REV_5906 */
12631 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12633 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12634 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12635 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12638 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12639
12640 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12641 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12642 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12643 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12644 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12645 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12646
1b440c56
JL		 12647 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12648 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12649 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12650
027455ad
MC		 12651 /* 5700 B0 chips do not support checksumming correctly due
12652 * to hardware bugs.
12653 */
12654 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12655 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12656 else {
12657 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12658 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12659 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12660 tp->dev->features |= NETIF_F_IPV6_CSUM;
12661 }
12662
5a6f3074 12663 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12664 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12665 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12666 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12667 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12668 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12669 tp->pdev_peer == tp->pdev))
12670 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12671
321d32a0 12672 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12673 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12674 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12675 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12676 } else {
7f62ad5d 12677 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12678 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12679 ASIC_REV_5750 &&
12680 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12681 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12682 }
5a6f3074 12683 }
1da177e4 12684
4f125f42
MC		 12685 tp->irq_max = 1;
12686
f6eb9b1f
MC		 12687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12688 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12689 tp->irq_max = TG3_IRQ_MAX_VECS;
12690 }
0e1406dd
MC		 12691
12692 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
92c6b8d1
MC		 12693 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12694 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12695 else {
12696 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12697 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12698 }
0e1406dd 12699 }
f6eb9b1f 12700
f51f3562 12701 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 12702 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12703 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 12704 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12705
52f4490c
MC		 12706 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12707 &pci_state_reg);
12708
5e7dfd0f
MC		 12709 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12710 if (tp->pcie_cap != 0) {
12711 u16 lnkctl;
12712
1da177e4 12713 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12714
12715 pcie_set_readrq(tp->pdev, 4096);
12716
5e7dfd0f
MC		 12717 pci_read_config_word(tp->pdev,
12718 tp->pcie_cap + PCI_EXP_LNKCTL,
12719 &lnkctl);
12720 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12722 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12724 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12725 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12726 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12727 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12728 }
52f4490c 12729 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12730 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12731 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12732 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12733 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12734 if (!tp->pcix_cap) {
12735 printk(KERN_ERR PFX "Cannot find PCI-X "
12736 "capability, aborting.\n");
12737 return -EIO;
12738 }
12739
12740 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12741 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12742 }
1da177e4 12743
399de50b
MC		 12744 /* If we have an AMD 762 or VIA K8T800 chipset, write
12745 * reordering to the mailbox registers done by the host
12746 * controller can cause major troubles. We read back from
12747 * every mailbox register write to force the writes to be
12748 * posted to the chip in order.
12749 */
12750 if (pci_dev_present(write_reorder_chipsets) &&
12751 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12752 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12753
69fc4053
MC		 12754 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12755 &tp->pci_cacheline_sz);
12756 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12757 &tp->pci_lat_timer);
1da177e4
LT		 12758 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12759 tp->pci_lat_timer < 64) {
12760 tp->pci_lat_timer = 64;
69fc4053
MC		 12761 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12762 tp->pci_lat_timer);
1da177e4
LT		 12763 }
12764
52f4490c
MC		 12765 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12766 /* 5700 BX chips need to have their TX producer index
12767 * mailboxes written twice to workaround a bug.
12768 */
12769 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12770
52f4490c 12771 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12772 *
12773 * The workaround is to use indirect register accesses
12774 * for all chip writes not to mailbox registers.
12775 */
52f4490c 12776 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12777 u32 pm_reg;
1da177e4
LT		 12778
12779 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12780
12781 /* The chip can have it's power management PCI config
12782 * space registers clobbered due to this bug.
12783 * So explicitly force the chip into D0 here.
12784 */
9974a356
MC		 12785 pci_read_config_dword(tp->pdev,
12786 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12787 &pm_reg);
12788 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12789 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12790 pci_write_config_dword(tp->pdev,
12791 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12792 pm_reg);
12793
12794 /* Also, force SERR#/PERR# in PCI command. */
12795 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12796 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12797 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12798 }
12799 }
12800
1da177e4
LT		 12801 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12802 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12803 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12804 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12805
12806 /* Chip-specific fixup from Broadcom driver */
12807 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12808 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12809 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12810 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12811 }
12812
1ee582d8 12813 /* Default fast path register access methods */
20094930 12814 tp->read32 = tg3_read32;
1ee582d8 12815 tp->write32 = tg3_write32;
09ee929c 12816 tp->read32_mbox = tg3_read32;
20094930 12817 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12818 tp->write32_tx_mbox = tg3_write32;
12819 tp->write32_rx_mbox = tg3_write32;
12820
12821 /* Various workaround register access methods */
12822 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12823 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12824 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12825 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12826 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12827 /*
12828 * Back to back register writes can cause problems on these
12829 * chips, the workaround is to read back all reg writes
12830 * except those to mailbox regs.
12831 *
12832 * See tg3_write_indirect_reg32().
12833 */
1ee582d8 12834 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12835 }
12836
1ee582d8
MC		 12837 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12838 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12839 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12840 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12841 tp->write32_rx_mbox = tg3_write_flush_reg32;
12842 }
20094930 12843
6892914f
MC		 12844 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12845 tp->read32 = tg3_read_indirect_reg32;
12846 tp->write32 = tg3_write_indirect_reg32;
12847 tp->read32_mbox = tg3_read_indirect_mbox;
12848 tp->write32_mbox = tg3_write_indirect_mbox;
12849 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12850 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12851
12852 iounmap(tp->regs);
22abe310 12853 tp->regs = NULL;
6892914f
MC		 12854
12855 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12856 pci_cmd &= ~PCI_COMMAND_MEMORY;
12857 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12858 }
b5d3772c
MC		 12859 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12860 tp->read32_mbox = tg3_read32_mbox_5906;
12861 tp->write32_mbox = tg3_write32_mbox_5906;
12862 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12863 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12864 }
6892914f 12865
bbadf503
MC		 12866 if (tp->write32 == tg3_write_indirect_reg32 ||
12867 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12868 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12869 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12870 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12871
7d0c41ef 12872 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12873 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12874 * determined before calling tg3_set_power_state() so that
12875 * we know whether or not to switch out of Vaux power.
12876 * When the flag is set, it means that GPIO1 is used for eeprom
12877 * write protect and also implies that it is a LOM where GPIOs
12878 * are not used to switch power.
6aa20a22 12879 */
7d0c41ef
MC		 12880 tg3_get_eeprom_hw_cfg(tp);
12881
0d3031d9
MC		 12882 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12883 /* Allow reads and writes to the
12884 * APE register and memory space.
12885 */
12886 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12887 PCISTATE_ALLOW_APE_SHMEM_WR;
12888 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12889 pci_state_reg);
12890 }
12891
9936bcf6 12892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 12894 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12895 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 12897 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12898
314fba34
MC		 12899 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12900 * GPIO1 driven high will bring 5700's external PHY out of reset.
12901 * It is also used as eeprom write protect on LOMs.
12902 */
12903 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12904 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12905 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12906 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12907 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12908 /* Unused GPIO3 must be driven as output on 5752 because there
12909 * are no pull-up resistors on unused GPIO pins.
12910 */
12911 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12912 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12913
321d32a0
MC		 12914 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12916 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12917
8d519ab2
MC		 12918 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12919 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12920 /* Turn off the debug UART. */
12921 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12922 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12923 /* Keep VMain power. */
12924 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12925 GRC_LCLCTRL_GPIO_OUTPUT0;
12926 }
12927
1da177e4 12928 /* Force the chip into D0. */
bc1c7567 12929 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12930 if (err) {
12931 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12932 pci_name(tp->pdev));
12933 return err;
12934 }
12935
1da177e4
LT		 12936 /* Derive initial jumbo mode from MTU assigned in
12937 * ether_setup() via the alloc_etherdev() call
12938 */
0f893dc6 12939 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12940 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12941 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12942
12943 /* Determine WakeOnLan speed to use. */
12944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12945 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12946 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12947 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12948 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12949 } else {
12950 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12951 }
12952
7f97a4bd
MC		 12953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12954 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12955
1da177e4
LT		 12956 /* A few boards don't want Ethernet@WireSpeed phy feature */
12957 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12958 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12959 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12960 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12961 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12962 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12963 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12964
12965 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12966 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12967 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12968 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12969 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12970
321d32a0 12971 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12972 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 12973 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 12974 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12975 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 12976 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12980 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12981 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12982 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12983 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12984 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12985 } else
c424cb24
MC		 12986 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12987 }
1da177e4 12988
b2a5c19c
MC		 12989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12990 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12991 tp->phy_otp = tg3_read_otp_phycfg(tp);
12992 if (tp->phy_otp == 0)
12993 tp->phy_otp = TG3_OTP_DEFAULT;
12994 }
12995
f51f3562 12996 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12997 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12998 else
12999 tp->mi_mode = MAC_MI_MODE_BASE;
13000
1da177e4 13001 tp->coalesce_mode = 0;
1da177e4
LT		 13002 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13003 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13004 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13005
321d32a0
MC		 13006 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13008 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13009
158d7abd
MC		 13010 err = tg3_mdio_init(tp);
13011 if (err)
13012 return err;
1da177e4
LT		 13013
13014 /* Initialize data/descriptor byte/word swapping. */
13015 val = tr32(GRC_MODE);
13016 val &= GRC_MODE_HOST_STACKUP;
13017 tw32(GRC_MODE, val | tp->grc_mode);
13018
13019 tg3_switch_clocks(tp);
13020
13021 /* Clear this out for sanity. */
13022 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13023
13024 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13025 &pci_state_reg);
13026 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13027 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13028 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13029
13030 if (chiprevid == CHIPREV_ID_5701_A0 ||
13031 chiprevid == CHIPREV_ID_5701_B0 ||
13032 chiprevid == CHIPREV_ID_5701_B2 ||
13033 chiprevid == CHIPREV_ID_5701_B5) {
13034 void __iomem *sram_base;
13035
13036 /* Write some dummy words into the SRAM status block
13037 * area, see if it reads back correctly. If the return
13038 * value is bad, force enable the PCIX workaround.
13039 */
13040 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13041
13042 writel(0x00000000, sram_base);
13043 writel(0x00000000, sram_base + 4);
13044 writel(0xffffffff, sram_base + 4);
13045 if (readl(sram_base) != 0x00000000)
13046 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13047 }
13048 }
13049
13050 udelay(50);
13051 tg3_nvram_init(tp);
13052
13053 grc_misc_cfg = tr32(GRC_MISC_CFG);
13054 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13055
1da177e4
LT		 13056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13057 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13058 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13059 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13060
fac9b83e
DM		 13061 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13062 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13063 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13064 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13065 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13066 HOSTCC_MODE_CLRTICK_TXBD);
13067
13068 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13069 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13070 tp->misc_host_ctrl);
13071 }
13072
3bda1258
MC		 13073 /* Preserve the APE MAC_MODE bits */
13074 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13075 tp->mac_mode = tr32(MAC_MODE) |
13076 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13077 else
13078 tp->mac_mode = TG3_DEF_MAC_MODE;
13079
1da177e4
LT		 13080 /* these are limited to 10/100 only */
13081 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13082 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13083 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13084 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13085 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13086 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13087 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13088 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13089 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13090 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13091 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13092 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13093 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13094 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13095
13096 err = tg3_phy_probe(tp);
13097 if (err) {
13098 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13099 pci_name(tp->pdev), err);
13100 /* ... but do not return immediately ... */
b02fd9e3 13101 tg3_mdio_fini(tp);
1da177e4
LT		 13102 }
13103
13104 tg3_read_partno(tp);
c4e6575c 13105 tg3_read_fw_ver(tp);
1da177e4
LT		 13106
13107 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13108 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13109 } else {
13110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13111 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13112 else
13113 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13114 }
13115
13116 /* 5700 {AX,BX} chips have a broken status block link
13117 * change bit implementation, so we must use the
13118 * status register in those cases.
13119 */
13120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13121 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13122 else
13123 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13124
13125 /* The led_ctrl is set during tg3_phy_probe, here we might
13126 * have to force the link status polling mechanism based
13127 * upon subsystem IDs.
13128 */
13129 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13131 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13132 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13133 TG3_FLAG_USE_LINKCHG_REG);
13134 }
13135
13136 /* For all SERDES we poll the MAC status register. */
13137 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13138 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13139 else
13140 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13141
ad829268 13142 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13144 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13145 tp->rx_offset = 0;
13146
f92905de
MC		 13147 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13148
13149 /* Increment the rx prod index on the rx std ring by at most
13150 * 8 for these chips to workaround hw errata.
13151 */
13152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13153 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13154 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13155 tp->rx_std_max_post = 8;
13156
8ed5d97e
MC		 13157 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13158 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13159 PCIE_PWR_MGMT_L1_THRESH_MSK;
13160
1da177e4
LT		 13161 return err;
13162}
13163
49b6e95f 13164#ifdef CONFIG_SPARC
1da177e4
LT		 13165static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13166{
13167 struct net_device *dev = tp->dev;
13168 struct pci_dev *pdev = tp->pdev;
49b6e95f 13169 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13170 const unsigned char *addr;
49b6e95f
DM		 13171 int len;
13172
13173 addr = of_get_property(dp, "local-mac-address", &len);
13174 if (addr && len == 6) {
13175 memcpy(dev->dev_addr, addr, 6);
13176 memcpy(dev->perm_addr, dev->dev_addr, 6);
13177 return 0;
1da177e4
LT		 13178 }
13179 return -ENODEV;
13180}
13181
13182static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13183{
13184 struct net_device *dev = tp->dev;
13185
13186 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13187 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13188 return 0;
13189}
13190#endif
13191
13192static int __devinit tg3_get_device_address(struct tg3 *tp)
13193{
13194 struct net_device *dev = tp->dev;
13195 u32 hi, lo, mac_offset;
008652b3 13196 int addr_ok = 0;
1da177e4 13197
49b6e95f 13198#ifdef CONFIG_SPARC
1da177e4
LT		 13199 if (!tg3_get_macaddr_sparc(tp))
13200 return 0;
13201#endif
13202
13203 mac_offset = 0x7c;
f49639e6 13204 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13205 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13206 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13207 mac_offset = 0xcc;
13208 if (tg3_nvram_lock(tp))
13209 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13210 else
13211 tg3_nvram_unlock(tp);
a1b950d5
MC		 13212 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13213 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13214 mac_offset = 0xcc;
13215 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13216 mac_offset = 0x10;
1da177e4
LT		 13217
13218 /* First try to get it from MAC address mailbox. */
13219 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13220 if ((hi >> 16) == 0x484b) {
13221 dev->dev_addr[0] = (hi >> 8) & 0xff;
13222 dev->dev_addr[1] = (hi >> 0) & 0xff;
13223
13224 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13225 dev->dev_addr[2] = (lo >> 24) & 0xff;
13226 dev->dev_addr[3] = (lo >> 16) & 0xff;
13227 dev->dev_addr[4] = (lo >> 8) & 0xff;
13228 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13229
008652b3
MC		 13230 /* Some old bootcode may report a 0 MAC address in SRAM */
13231 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13232 }
13233 if (!addr_ok) {
13234 /* Next, try NVRAM. */
df259d8c
MC		 13235 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13236 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13237 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13238 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13239 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13240 }
13241 /* Finally just fetch it out of the MAC control regs. */
13242 else {
13243 hi = tr32(MAC_ADDR_0_HIGH);
13244 lo = tr32(MAC_ADDR_0_LOW);
13245
13246 dev->dev_addr[5] = lo & 0xff;
13247 dev->dev_addr[4] = (lo >> 8) & 0xff;
13248 dev->dev_addr[3] = (lo >> 16) & 0xff;
13249 dev->dev_addr[2] = (lo >> 24) & 0xff;
13250 dev->dev_addr[1] = hi & 0xff;
13251 dev->dev_addr[0] = (hi >> 8) & 0xff;
13252 }
1da177e4
LT		 13253 }
13254
13255 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13256#ifdef CONFIG_SPARC
1da177e4
LT		 13257 if (!tg3_get_default_macaddr_sparc(tp))
13258 return 0;
13259#endif
13260 return -EINVAL;
13261 }
2ff43697 13262 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13263 return 0;
13264}
13265
59e6b434
DM		 13266#define BOUNDARY_SINGLE_CACHELINE 1
13267#define BOUNDARY_MULTI_CACHELINE 2
13268
13269static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13270{
13271 int cacheline_size;
13272 u8 byte;
13273 int goal;
13274
13275 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13276 if (byte == 0)
13277 cacheline_size = 1024;
13278 else
13279 cacheline_size = (int) byte * 4;
13280
13281 /* On 5703 and later chips, the boundary bits have no
13282 * effect.
13283 */
13284 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13285 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13286 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13287 goto out;
13288
13289#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13290 goal = BOUNDARY_MULTI_CACHELINE;
13291#else
13292#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13293 goal = BOUNDARY_SINGLE_CACHELINE;
13294#else
13295 goal = 0;
13296#endif
13297#endif
13298
13299 if (!goal)
13300 goto out;
13301
13302 /* PCI controllers on most RISC systems tend to disconnect
13303 * when a device tries to burst across a cache-line boundary.
13304 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13305 *
13306 * Unfortunately, for PCI-E there are only limited
13307 * write-side controls for this, and thus for reads
13308 * we will still get the disconnects. We'll also waste
13309 * these PCI cycles for both read and write for chips
13310 * other than 5700 and 5701 which do not implement the
13311 * boundary bits.
13312 */
13313 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13314 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13315 switch (cacheline_size) {
13316 case 16:
13317 case 32:
13318 case 64:
13319 case 128:
13320 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13321 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13322 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13323 } else {
13324 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13325 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13326 }
13327 break;
13328
13329 case 256:
13330 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13331 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13332 break;
13333
13334 default:
13335 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13336 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13337 break;
855e1111 13338 }
59e6b434
DM		 13339 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13340 switch (cacheline_size) {
13341 case 16:
13342 case 32:
13343 case 64:
13344 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13345 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13346 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13347 break;
13348 }
13349 /* fallthrough */
13350 case 128:
13351 default:
13352 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13353 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13354 break;
855e1111 13355 }
59e6b434
DM		 13356 } else {
13357 switch (cacheline_size) {
13358 case 16:
13359 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13360 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13361 DMA_RWCTRL_WRITE_BNDRY_16);
13362 break;
13363 }
13364 /* fallthrough */
13365 case 32:
13366 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13367 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13368 DMA_RWCTRL_WRITE_BNDRY_32);
13369 break;
13370 }
13371 /* fallthrough */
13372 case 64:
13373 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13374 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13375 DMA_RWCTRL_WRITE_BNDRY_64);
13376 break;
13377 }
13378 /* fallthrough */
13379 case 128:
13380 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13381 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13382 DMA_RWCTRL_WRITE_BNDRY_128);
13383 break;
13384 }
13385 /* fallthrough */
13386 case 256:
13387 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13388 DMA_RWCTRL_WRITE_BNDRY_256);
13389 break;
13390 case 512:
13391 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13392 DMA_RWCTRL_WRITE_BNDRY_512);
13393 break;
13394 case 1024:
13395 default:
13396 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13397 DMA_RWCTRL_WRITE_BNDRY_1024);
13398 break;
855e1111 13399 }
59e6b434
DM		 13400 }
13401
13402out:
13403 return val;
13404}
13405
1da177e4
LT		 13406static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13407{
13408 struct tg3_internal_buffer_desc test_desc;
13409 u32 sram_dma_descs;
13410 int i, ret;
13411
13412 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13413
13414 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13415 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13416 tw32(RDMAC_STATUS, 0);
13417 tw32(WDMAC_STATUS, 0);
13418
13419 tw32(BUFMGR_MODE, 0);
13420 tw32(FTQ_RESET, 0);
13421
13422 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13423 test_desc.addr_lo = buf_dma & 0xffffffff;
13424 test_desc.nic_mbuf = 0x00002100;
13425 test_desc.len = size;
13426
13427 /*
13428 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13429 * the *second* time the tg3 driver was getting loaded after an
13430 * initial scan.
13431 *
13432 * Broadcom tells me:
13433 * ...the DMA engine is connected to the GRC block and a DMA
13434 * reset may affect the GRC block in some unpredictable way...
13435 * The behavior of resets to individual blocks has not been tested.
13436 *
13437 * Broadcom noted the GRC reset will also reset all sub-components.
13438 */
13439 if (to_device) {
13440 test_desc.cqid_sqid = (13 << 8) | 2;
13441
13442 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13443 udelay(40);
13444 } else {
13445 test_desc.cqid_sqid = (16 << 8) | 7;
13446
13447 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13448 udelay(40);
13449 }
13450 test_desc.flags = 0x00000005;
13451
13452 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13453 u32 val;
13454
13455 val = *(((u32 *)&test_desc) + i);
13456 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13457 sram_dma_descs + (i * sizeof(u32)));
13458 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13459 }
13460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13461
13462 if (to_device) {
13463 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13464 } else {
13465 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13466 }
13467
13468 ret = -ENODEV;
13469 for (i = 0; i < 40; i++) {
13470 u32 val;
13471
13472 if (to_device)
13473 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13474 else
13475 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13476 if ((val & 0xffff) == sram_dma_descs) {
13477 ret = 0;
13478 break;
13479 }
13480
13481 udelay(100);
13482 }
13483
13484 return ret;
13485}
13486
ded7340d 13487#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13488
13489static int __devinit tg3_test_dma(struct tg3 *tp)
13490{
13491 dma_addr_t buf_dma;
59e6b434 13492 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 13493 int ret;
13494
13495 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13496 if (!buf) {
13497 ret = -ENOMEM;
13498 goto out_nofree;
13499 }
13500
13501 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13502 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13503
59e6b434 13504 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 13505
13506 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13507 /* DMA read watermark not used on PCIE */
13508 tp->dma_rwctrl |= 0x00180000;
13509 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13512 tp->dma_rwctrl |= 0x003f0000;
13513 else
13514 tp->dma_rwctrl |= 0x003f000f;
13515 } else {
13516 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13517 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13518 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13519 u32 read_water = 0x7;
1da177e4 13520
4a29cc2e
MC		 13521 /* If the 5704 is behind the EPB bridge, we can
13522 * do the less restrictive ONE_DMA workaround for
13523 * better performance.
13524 */
13525 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13526 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13527 tp->dma_rwctrl |= 0x8000;
13528 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13529 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13530
49afdeb6
MC		 13531 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13532 read_water = 4;
59e6b434 13533 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13534 tp->dma_rwctrl |=
13535 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13536 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13537 (1 << 23);
4cf78e4f
MC		 13538 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13539 /* 5780 always in PCIX mode */
13540 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13541 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13542 /* 5714 always in PCIX mode */
13543 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13544 } else {
13545 tp->dma_rwctrl |= 0x001b000f;
13546 }
13547 }
13548
13549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13550 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13551 tp->dma_rwctrl &= 0xfffffff0;
13552
13553 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13554 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13555 /* Remove this if it causes problems for some boards. */
13556 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13557
13558 /* On 5700/5701 chips, we need to set this bit.
13559 * Otherwise the chip will issue cacheline transactions
13560 * to streamable DMA memory with not all the byte
13561 * enables turned on. This is an error on several
13562 * RISC PCI controllers, in particular sparc64.
13563 *
13564 * On 5703/5704 chips, this bit has been reassigned
13565 * a different meaning. In particular, it is used
13566 * on those chips to enable a PCI-X workaround.
13567 */
13568 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13569 }
13570
13571 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13572
13573#if 0
13574 /* Unneeded, already done by tg3_get_invariants. */
13575 tg3_switch_clocks(tp);
13576#endif
13577
13578 ret = 0;
13579 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13580 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13581 goto out;
13582
59e6b434
DM		 13583 /* It is best to perform DMA test with maximum write burst size
13584 * to expose the 5700/5701 write DMA bug.
13585 */
13586 saved_dma_rwctrl = tp->dma_rwctrl;
13587 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13588 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13589
1da177e4
LT		 13590 while (1) {
13591 u32 *p = buf, i;
13592
13593 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13594 p[i] = i;
13595
13596 /* Send the buffer to the chip. */
13597 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13598 if (ret) {
13599 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13600 break;
13601 }
13602
13603#if 0
13604 /* validate data reached card RAM correctly. */
13605 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13606 u32 val;
13607 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13608 if (le32_to_cpu(val) != p[i]) {
13609 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13610 /* ret = -ENODEV here? */
13611 }
13612 p[i] = 0;
13613 }
13614#endif
13615 /* Now read it back. */
13616 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13617 if (ret) {
13618 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13619
13620 break;
13621 }
13622
13623 /* Verify it. */
13624 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13625 if (p[i] == i)
13626 continue;
13627
59e6b434
DM		 13628 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13629 DMA_RWCTRL_WRITE_BNDRY_16) {
13630 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13631 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13632 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13633 break;
13634 } else {
13635 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13636 ret = -ENODEV;
13637 goto out;
13638 }
13639 }
13640
13641 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13642 /* Success. */
13643 ret = 0;
13644 break;
13645 }
13646 }
59e6b434
DM		 13647 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13648 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13649 static struct pci_device_id dma_wait_state_chipsets[] = {
13650 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13651 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13652 { },
13653 };
13654
59e6b434 13655 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13656 * now look for chipsets that are known to expose the
13657 * DMA bug without failing the test.
59e6b434 13658 */
6d1cfbab
MC		 13659 if (pci_dev_present(dma_wait_state_chipsets)) {
13660 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13661 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13662 }
13663 else
13664 /* Safe to use the calculated DMA boundary. */
13665 tp->dma_rwctrl = saved_dma_rwctrl;
13666
59e6b434
DM		 13667 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13668 }
1da177e4
LT		 13669
13670out:
13671 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13672out_nofree:
13673 return ret;
13674}
13675
13676static void __devinit tg3_init_link_config(struct tg3 *tp)
13677{
13678 tp->link_config.advertising =
13679 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13680 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13681 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13682 ADVERTISED_Autoneg | ADVERTISED_MII);
13683 tp->link_config.speed = SPEED_INVALID;
13684 tp->link_config.duplex = DUPLEX_INVALID;
13685 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13686 tp->link_config.active_speed = SPEED_INVALID;
13687 tp->link_config.active_duplex = DUPLEX_INVALID;
13688 tp->link_config.phy_is_low_power = 0;
13689 tp->link_config.orig_speed = SPEED_INVALID;
13690 tp->link_config.orig_duplex = DUPLEX_INVALID;
13691 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13692}
13693
13694static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13695{
f6eb9b1f
MC		 13696 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13697 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 13698 tp->bufmgr_config.mbuf_read_dma_low_water =
13699 DEFAULT_MB_RDMA_LOW_WATER_5705;
13700 tp->bufmgr_config.mbuf_mac_rx_low_water =
13701 DEFAULT_MB_MACRX_LOW_WATER_5705;
13702 tp->bufmgr_config.mbuf_high_water =
13703 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13704 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13705 tp->bufmgr_config.mbuf_mac_rx_low_water =
13706 DEFAULT_MB_MACRX_LOW_WATER_5906;
13707 tp->bufmgr_config.mbuf_high_water =
13708 DEFAULT_MB_HIGH_WATER_5906;
13709 }
fdfec172
MC		 13710
13711 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13712 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13713 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13714 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13715 tp->bufmgr_config.mbuf_high_water_jumbo =
13716 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13717 } else {
13718 tp->bufmgr_config.mbuf_read_dma_low_water =
13719 DEFAULT_MB_RDMA_LOW_WATER;
13720 tp->bufmgr_config.mbuf_mac_rx_low_water =
13721 DEFAULT_MB_MACRX_LOW_WATER;
13722 tp->bufmgr_config.mbuf_high_water =
13723 DEFAULT_MB_HIGH_WATER;
13724
13725 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13726 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13727 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13728 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13729 tp->bufmgr_config.mbuf_high_water_jumbo =
13730 DEFAULT_MB_HIGH_WATER_JUMBO;
13731 }
1da177e4
LT		 13732
13733 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13734 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13735}
13736
13737static char * __devinit tg3_phy_string(struct tg3 *tp)
13738{
13739 switch (tp->phy_id & PHY_ID_MASK) {
13740 case PHY_ID_BCM5400: return "5400";
13741 case PHY_ID_BCM5401: return "5401";
13742 case PHY_ID_BCM5411: return "5411";
13743 case PHY_ID_BCM5701: return "5701";
13744 case PHY_ID_BCM5703: return "5703";
13745 case PHY_ID_BCM5704: return "5704";
13746 case PHY_ID_BCM5705: return "5705";
13747 case PHY_ID_BCM5750: return "5750";
85e94ced 13748 case PHY_ID_BCM5752: return "5752";
a4e2b347 13749 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13750 case PHY_ID_BCM5780: return "5780";
af36e6b6 13751 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13752 case PHY_ID_BCM5787: return "5787";
d30cdd28 13753 case PHY_ID_BCM5784: return "5784";
126a3368 13754 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13755 case PHY_ID_BCM5906: return "5906";
9936bcf6 13756 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13757 case PHY_ID_BCM8002: return "8002/serdes";
13758 case 0: return "serdes";
13759 default: return "unknown";
855e1111 13760 }
1da177e4
LT		 13761}
13762
f9804ddb
MC		 13763static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13764{
13765 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13766 strcpy(str, "PCI Express");
13767 return str;
13768 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13769 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13770
13771 strcpy(str, "PCIX:");
13772
13773 if ((clock_ctrl == 7) ||
13774 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13775 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13776 strcat(str, "133MHz");
13777 else if (clock_ctrl == 0)
13778 strcat(str, "33MHz");
13779 else if (clock_ctrl == 2)
13780 strcat(str, "50MHz");
13781 else if (clock_ctrl == 4)
13782 strcat(str, "66MHz");
13783 else if (clock_ctrl == 6)
13784 strcat(str, "100MHz");
f9804ddb
MC		 13785 } else {
13786 strcpy(str, "PCI:");
13787 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13788 strcat(str, "66MHz");
13789 else
13790 strcat(str, "33MHz");
13791 }
13792 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13793 strcat(str, ":32-bit");
13794 else
13795 strcat(str, ":64-bit");
13796 return str;
13797}
13798
8c2dc7e1 13799static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13800{
13801 struct pci_dev *peer;
13802 unsigned int func, devnr = tp->pdev->devfn & ~7;
13803
13804 for (func = 0; func < 8; func++) {
13805 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13806 if (peer && peer != tp->pdev)
13807 break;
13808 pci_dev_put(peer);
13809 }
16fe9d74
MC		 13810 /* 5704 can be configured in single-port mode, set peer to
13811 * tp->pdev in that case.
13812 */
13813 if (!peer) {
13814 peer = tp->pdev;
13815 return peer;
13816 }
1da177e4
LT		 13817
13818 /*
13819 * We don't need to keep the refcount elevated; there's no way
13820 * to remove one half of this device without removing the other
13821 */
13822 pci_dev_put(peer);
13823
13824 return peer;
13825}
13826
15f9850d
DM		 13827static void __devinit tg3_init_coal(struct tg3 *tp)
13828{
13829 struct ethtool_coalesce *ec = &tp->coal;
13830
13831 memset(ec, 0, sizeof(*ec));
13832 ec->cmd = ETHTOOL_GCOALESCE;
13833 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13834 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13835 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13836 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13837 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13838 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13839 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13840 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13841 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13842
13843 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13844 HOSTCC_MODE_CLRTICK_TXBD)) {
13845 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13846 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13847 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13848 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13849 }
d244c892
MC		 13850
13851 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13852 ec->rx_coalesce_usecs_irq = 0;
13853 ec->tx_coalesce_usecs_irq = 0;
13854 ec->stats_block_coalesce_usecs = 0;
13855 }
15f9850d
DM		 13856}
13857
7c7d64b8
SH		 13858static const struct net_device_ops tg3_netdev_ops = {
13859 .ndo_open = tg3_open,
13860 .ndo_stop = tg3_close,
00829823
SH		 13861 .ndo_start_xmit = tg3_start_xmit,
13862 .ndo_get_stats = tg3_get_stats,
13863 .ndo_validate_addr = eth_validate_addr,
13864 .ndo_set_multicast_list = tg3_set_rx_mode,
13865 .ndo_set_mac_address = tg3_set_mac_addr,
13866 .ndo_do_ioctl = tg3_ioctl,
13867 .ndo_tx_timeout = tg3_tx_timeout,
13868 .ndo_change_mtu = tg3_change_mtu,
13869#if TG3_VLAN_TAG_USED
13870 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13871#endif
13872#ifdef CONFIG_NET_POLL_CONTROLLER
13873 .ndo_poll_controller = tg3_poll_controller,
13874#endif
13875};
13876
13877static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13878 .ndo_open = tg3_open,
13879 .ndo_stop = tg3_close,
13880 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13881 .ndo_get_stats = tg3_get_stats,
13882 .ndo_validate_addr = eth_validate_addr,
13883 .ndo_set_multicast_list = tg3_set_rx_mode,
13884 .ndo_set_mac_address = tg3_set_mac_addr,
13885 .ndo_do_ioctl = tg3_ioctl,
13886 .ndo_tx_timeout = tg3_tx_timeout,
13887 .ndo_change_mtu = tg3_change_mtu,
13888#if TG3_VLAN_TAG_USED
13889 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13890#endif
13891#ifdef CONFIG_NET_POLL_CONTROLLER
13892 .ndo_poll_controller = tg3_poll_controller,
13893#endif
13894};
13895
1da177e4
LT		 13896static int __devinit tg3_init_one(struct pci_dev *pdev,
13897 const struct pci_device_id *ent)
13898{
13899 static int tg3_version_printed = 0;
1da177e4
LT		 13900 struct net_device *dev;
13901 struct tg3 *tp;
646c9edd
MC		 13902 int i, err, pm_cap;
13903 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 13904 char str[40];
72f2afb8 13905 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13906
13907 if (tg3_version_printed++ == 0)
13908 printk(KERN_INFO "%s", version);
13909
13910 err = pci_enable_device(pdev);
13911 if (err) {
13912 printk(KERN_ERR PFX "Cannot enable PCI device, "
13913 "aborting.\n");
13914 return err;
13915 }
13916
1da177e4
LT		 13917 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13918 if (err) {
13919 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13920 "aborting.\n");
13921 goto err_out_disable_pdev;
13922 }
13923
13924 pci_set_master(pdev);
13925
13926 /* Find power-management capability. */
13927 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13928 if (pm_cap == 0) {
13929 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13930 "aborting.\n");
13931 err = -EIO;
13932 goto err_out_free_res;
13933 }
13934
fe5f5787 13935 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 13936 if (!dev) {
13937 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13938 err = -ENOMEM;
13939 goto err_out_free_res;
13940 }
13941
1da177e4
LT		 13942 SET_NETDEV_DEV(dev, &pdev->dev);
13943
1da177e4
LT		 13944#if TG3_VLAN_TAG_USED
13945 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13946#endif
13947
13948 tp = netdev_priv(dev);
13949 tp->pdev = pdev;
13950 tp->dev = dev;
13951 tp->pm_cap = pm_cap;
1da177e4
LT		 13952 tp->rx_mode = TG3_DEF_RX_MODE;
13953 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13954
1da177e4
LT		 13955 if (tg3_debug > 0)
13956 tp->msg_enable = tg3_debug;
13957 else
13958 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13959
13960 /* The word/byte swap controls here control register access byte
13961 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13962 * setting below.
13963 */
13964 tp->misc_host_ctrl =
13965 MISC_HOST_CTRL_MASK_PCI_INT |
13966 MISC_HOST_CTRL_WORD_SWAP |
13967 MISC_HOST_CTRL_INDIR_ACCESS |
13968 MISC_HOST_CTRL_PCISTATE_RW;
13969
13970 /* The NONFRM (non-frame) byte/word swap controls take effect
13971 * on descriptor entries, anything which isn't packet data.
13972 *
13973 * The StrongARM chips on the board (one for tx, one for rx)
13974 * are running in big-endian mode.
13975 */
13976 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13977 GRC_MODE_WSWAP_NONFRM_DATA);
13978#ifdef __BIG_ENDIAN
13979 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13980#endif
13981 spin_lock_init(&tp->lock);
1da177e4 13982 spin_lock_init(&tp->indirect_lock);
c4028958 13983 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13984
d5fe488a 13985 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13986 if (!tp->regs) {
1da177e4
LT		 13987 printk(KERN_ERR PFX "Cannot map device registers, "
13988 "aborting.\n");
13989 err = -ENOMEM;
13990 goto err_out_free_dev;
13991 }
13992
13993 tg3_init_link_config(tp);
13994
1da177e4
LT		 13995 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13996 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 13997
646c9edd
MC		 13998 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13999 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14000 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14001 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14002 struct tg3_napi *tnapi = &tp->napi[i];
14003
14004 tnapi->tp = tp;
14005 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14006
14007 tnapi->int_mbox = intmbx;
14008 if (i < 4)
14009 intmbx += 0x8;
14010 else
14011 intmbx += 0x4;
14012
14013 tnapi->consmbox = rcvmbx;
14014 tnapi->prodmbox = sndmbx;
14015
14016 if (i)
14017 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14018 else
14019 tnapi->coal_now = HOSTCC_MODE_NOW;
14020
14021 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14022 break;
14023
14024 /*
14025 * If we support MSIX, we'll be using RSS. If we're using
14026 * RSS, the first vector only handles link interrupts and the
14027 * remaining vectors handle rx and tx interrupts. Reuse the
14028 * mailbox values for the next iteration. The values we setup
14029 * above are still useful for the single vectored mode.
14030 */
14031 if (!i)
14032 continue;
14033
14034 rcvmbx += 0x8;
14035
14036 if (sndmbx & 0x4)
14037 sndmbx -= 0x4;
14038 else
14039 sndmbx += 0xc;
14040 }
14041
8ef0442f 14042 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 14043 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14044 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14045 dev->irq = pdev->irq;
1da177e4
LT		 14046
14047 err = tg3_get_invariants(tp);
14048 if (err) {
14049 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14050 "aborting.\n");
14051 goto err_out_iounmap;
14052 }
14053
92c6b8d1 14054 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
00829823
SH		 14055 dev->netdev_ops = &tg3_netdev_ops;
14056 else
14057 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14058
14059
4a29cc2e
MC		 14060 /* The EPB bridge inside 5714, 5715, and 5780 and any
14061 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14062 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14063 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14064 * do DMA address check in tg3_start_xmit().
14065 */
4a29cc2e 14066 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14067 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14068 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14069 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14070#ifdef CONFIG_HIGHMEM
6a35528a 14071 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14072#endif
4a29cc2e 14073 } else
6a35528a 14074 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14075
14076 /* Configure DMA attributes. */
284901a9 14077 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14078 err = pci_set_dma_mask(pdev, dma_mask);
14079 if (!err) {
14080 dev->features |= NETIF_F_HIGHDMA;
14081 err = pci_set_consistent_dma_mask(pdev,
14082 persist_dma_mask);
14083 if (err < 0) {
14084 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14085 "DMA for consistent allocations\n");
14086 goto err_out_iounmap;
14087 }
14088 }
14089 }
284901a9
YH		 14090 if (err || dma_mask == DMA_BIT_MASK(32)) {
14091 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14092 if (err) {
14093 printk(KERN_ERR PFX "No usable DMA configuration, "
14094 "aborting.\n");
14095 goto err_out_iounmap;
14096 }
14097 }
14098
fdfec172 14099 tg3_init_bufmgr_config(tp);
1da177e4 14100
077f849d 14101 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 14102 tp->fw_needed = FIRMWARE_TG3;
077f849d 14103
1da177e4
LT		 14104 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14105 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14106 }
14107 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14108 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14109 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 14110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 14111 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14112 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14113 } else {
7f62ad5d 14114 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 14115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 14116 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 14117 else
9e9fd12d 14118 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 14119 }
1da177e4 14120
4e3a7aaa
MC		 14121 /* TSO is on by default on chips that support hardware TSO.
14122 * Firmware TSO on older chips gives lower performance, so it
14123 * is off by default, but can be enabled using ethtool.
14124 */
b0026624 14125 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 14126 if (dev->features & NETIF_F_IP_CSUM)
14127 dev->features |= NETIF_F_TSO;
14128 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14129 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 14130 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 14131 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14132 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14133 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14134 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 14135 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6 14137 dev->features |= NETIF_F_TSO_ECN;
b0026624 14138 }
1da177e4 14139
1da177e4
LT		 14140
14141 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14142 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14143 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14144 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14145 tp->rx_pending = 63;
14146 }
14147
1da177e4
LT		 14148 err = tg3_get_device_address(tp);
14149 if (err) {
14150 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14151 "aborting.\n");
077f849d 14152 goto err_out_fw;
1da177e4
LT		 14153 }
14154
c88864df 14155 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14156 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14157 if (!tp->aperegs) {
c88864df
MC		 14158 printk(KERN_ERR PFX "Cannot map APE registers, "
14159 "aborting.\n");
14160 err = -ENOMEM;
077f849d 14161 goto err_out_fw;
c88864df
MC		 14162 }
14163
14164 tg3_ape_lock_init(tp);
7fd76445
MC		 14165
14166 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14167 tg3_read_dash_ver(tp);
c88864df
MC		 14168 }
14169
1da177e4
LT		 14170 /*
14171 * Reset chip in case UNDI or EFI driver did not shutdown
14172 * DMA self test will enable WDMAC and we'll see (spurious)
14173 * pending DMA on the PCI bus at that point.
14174 */
14175 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14176 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14177 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14178 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14179 }
14180
14181 err = tg3_test_dma(tp);
14182 if (err) {
14183 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14184 goto err_out_apeunmap;
1da177e4
LT		 14185 }
14186
1da177e4
LT		 14187 /* flow control autonegotiation is default behavior */
14188 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14189 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14190
15f9850d
DM		 14191 tg3_init_coal(tp);
14192
c49a1561
MC		 14193 pci_set_drvdata(pdev, dev);
14194
1da177e4
LT		 14195 err = register_netdev(dev);
14196 if (err) {
14197 printk(KERN_ERR PFX "Cannot register net device, "
14198 "aborting.\n");
0d3031d9 14199 goto err_out_apeunmap;
1da177e4
LT		 14200 }
14201
df59c940 14202 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14203 dev->name,
14204 tp->board_part_number,
14205 tp->pci_chip_rev_id,
f9804ddb 14206 tg3_bus_string(tp, str),
e174961c 14207 dev->dev_addr);
1da177e4 14208
3f0e3ad7
MC		 14209 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14210 struct phy_device *phydev;
14211 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14212 printk(KERN_INFO
14213 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14214 tp->dev->name, phydev->drv->name,
14215 dev_name(&phydev->dev));
14216 } else
df59c940
MC		 14217 printk(KERN_INFO
14218 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14219 tp->dev->name, tg3_phy_string(tp),
14220 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14221 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14222 "10/100/1000Base-T")),
14223 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14224
14225 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14226 dev->name,
14227 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14228 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14229 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14230 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14231 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14232 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14233 dev->name, tp->dma_rwctrl,
284901a9 14234 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14235 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14236
14237 return 0;
14238
0d3031d9
MC		 14239err_out_apeunmap:
14240 if (tp->aperegs) {
14241 iounmap(tp->aperegs);
14242 tp->aperegs = NULL;
14243 }
14244
077f849d
JSR		 14245err_out_fw:
14246 if (tp->fw)
14247 release_firmware(tp->fw);
14248
1da177e4 14249err_out_iounmap:
6892914f
MC		 14250 if (tp->regs) {
14251 iounmap(tp->regs);
22abe310 14252 tp->regs = NULL;
6892914f 14253 }
1da177e4
LT		 14254
14255err_out_free_dev:
14256 free_netdev(dev);
14257
14258err_out_free_res:
14259 pci_release_regions(pdev);
14260
14261err_out_disable_pdev:
14262 pci_disable_device(pdev);
14263 pci_set_drvdata(pdev, NULL);
14264 return err;
14265}
14266
14267static void __devexit tg3_remove_one(struct pci_dev *pdev)
14268{
14269 struct net_device *dev = pci_get_drvdata(pdev);
14270
14271 if (dev) {
14272 struct tg3 *tp = netdev_priv(dev);
14273
077f849d
JSR		 14274 if (tp->fw)
14275 release_firmware(tp->fw);
14276
7faa006f 14277 flush_scheduled_work();
158d7abd 14278
b02fd9e3
MC		 14279 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14280 tg3_phy_fini(tp);
158d7abd 14281 tg3_mdio_fini(tp);
b02fd9e3 14282 }
158d7abd 14283
1da177e4 14284 unregister_netdev(dev);
0d3031d9
MC		 14285 if (tp->aperegs) {
14286 iounmap(tp->aperegs);
14287 tp->aperegs = NULL;
14288 }
6892914f
MC		 14289 if (tp->regs) {
14290 iounmap(tp->regs);
22abe310 14291 tp->regs = NULL;
6892914f 14292 }
1da177e4
LT		 14293 free_netdev(dev);
14294 pci_release_regions(pdev);
14295 pci_disable_device(pdev);
14296 pci_set_drvdata(pdev, NULL);
14297 }
14298}
14299
14300static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14301{
14302 struct net_device *dev = pci_get_drvdata(pdev);
14303 struct tg3 *tp = netdev_priv(dev);
12dac075 14304 pci_power_t target_state;
1da177e4
LT		 14305 int err;
14306
3e0c95fd
MC		 14307 /* PCI register 4 needs to be saved whether netif_running() or not.
14308 * MSI address and data need to be saved if using MSI and
14309 * netif_running().
14310 */
14311 pci_save_state(pdev);
14312
1da177e4
LT		 14313 if (!netif_running(dev))
14314 return 0;
14315
7faa006f 14316 flush_scheduled_work();
b02fd9e3 14317 tg3_phy_stop(tp);
1da177e4
LT		 14318 tg3_netif_stop(tp);
14319
14320 del_timer_sync(&tp->timer);
14321
f47c11ee 14322 tg3_full_lock(tp, 1);
1da177e4 14323 tg3_disable_ints(tp);
f47c11ee 14324 tg3_full_unlock(tp);
1da177e4
LT		 14325
14326 netif_device_detach(dev);
14327
f47c11ee 14328 tg3_full_lock(tp, 0);
944d980e 14329 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14330 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14331 tg3_full_unlock(tp);
1da177e4 14332
12dac075
RW		 14333 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14334
14335 err = tg3_set_power_state(tp, target_state);
1da177e4 14336 if (err) {
b02fd9e3
MC		 14337 int err2;
14338
f47c11ee 14339 tg3_full_lock(tp, 0);
1da177e4 14340
6a9eba15 14341 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14342 err2 = tg3_restart_hw(tp, 1);
14343 if (err2)
b9ec6c1b 14344 goto out;
1da177e4
LT		 14345
14346 tp->timer.expires = jiffies + tp->timer_offset;
14347 add_timer(&tp->timer);
14348
14349 netif_device_attach(dev);
14350 tg3_netif_start(tp);
14351
b9ec6c1b 14352out:
f47c11ee 14353 tg3_full_unlock(tp);
b02fd9e3
MC		 14354
14355 if (!err2)
14356 tg3_phy_start(tp);
1da177e4
LT		 14357 }
14358
14359 return err;
14360}
14361
14362static int tg3_resume(struct pci_dev *pdev)
14363{
14364 struct net_device *dev = pci_get_drvdata(pdev);
14365 struct tg3 *tp = netdev_priv(dev);
14366 int err;
14367
3e0c95fd
MC		 14368 pci_restore_state(tp->pdev);
14369
1da177e4
LT		 14370 if (!netif_running(dev))
14371 return 0;
14372
bc1c7567 14373 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14374 if (err)
14375 return err;
14376
14377 netif_device_attach(dev);
14378
f47c11ee 14379 tg3_full_lock(tp, 0);
1da177e4 14380
6a9eba15 14381 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14382 err = tg3_restart_hw(tp, 1);
14383 if (err)
14384 goto out;
1da177e4
LT		 14385
14386 tp->timer.expires = jiffies + tp->timer_offset;
14387 add_timer(&tp->timer);
14388
1da177e4
LT		 14389 tg3_netif_start(tp);
14390
b9ec6c1b 14391out:
f47c11ee 14392 tg3_full_unlock(tp);
1da177e4 14393
b02fd9e3
MC		 14394 if (!err)
14395 tg3_phy_start(tp);
14396
b9ec6c1b 14397 return err;
1da177e4
LT		 14398}
14399
14400static struct pci_driver tg3_driver = {
14401 .name = DRV_MODULE_NAME,
14402 .id_table = tg3_pci_tbl,
14403 .probe = tg3_init_one,
14404 .remove = __devexit_p(tg3_remove_one),
14405 .suspend = tg3_suspend,
14406 .resume = tg3_resume
14407};
14408
14409static int __init tg3_init(void)
14410{
29917620 14411 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14412}
14413
14414static void __exit tg3_cleanup(void)
14415{
14416 pci_unregister_driver(&tg3_driver);
14417}
14418
14419module_init(tg3_init);
14420module_exit(tg3_cleanup);
Ubuntu Artful kernel mirror