]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved | |
3 | * | |
4 | * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC | |
5 | * | |
6 | * Base Driver Olympic: | |
7 | * Written 1999 Peter De Schrijver & Mike Phillips | |
8 | * | |
9 | * This software may be used and distributed according to the terms | |
10 | * of the GNU General Public License, incorporated herein by reference. | |
11 | * | |
12 | * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world. | |
13 | * | |
14 | * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel. | |
15 | * 3/05/01 - Last clean up stuff before submission. | |
16 | * 2/15/01 - Finally, update to new pci api. | |
17 | * | |
18 | * To Do: | |
19 | */ | |
20 | ||
21 | /* | |
22 | * Technical Card Details | |
23 | * | |
24 | * All access to data is done with 16/8 bit transfers. The transfer | |
25 | * method really sucks. You can only read or write one location at a time. | |
26 | * | |
27 | * Also, the microcode for the card must be uploaded if the card does not have | |
28 | * the flashrom on board. This is a 28K bloat in the driver when compiled | |
29 | * as a module. | |
30 | * | |
31 | * Rx is very simple, status into a ring of descriptors, dma data transfer, | |
32 | * interrupts to tell us when a packet is received. | |
33 | * | |
34 | * Tx is a little more interesting. Similar scenario, descriptor and dma data | |
35 | * transfers, but we don't have to interrupt the card to tell it another packet | |
36 | * is ready for transmission, we are just doing simple memory writes, not io or mmio | |
37 | * writes. The card can be set up to simply poll on the next | |
38 | * descriptor pointer and when this value is non-zero will automatically download | |
39 | * the next packet. The card then interrupts us when the packet is done. | |
40 | * | |
41 | */ | |
42 | ||
43 | #define XL_DEBUG 0 | |
44 | ||
b7aa6909 | 45 | #include <linux/jiffies.h> |
1da177e4 LT |
46 | #include <linux/module.h> |
47 | #include <linux/kernel.h> | |
48 | #include <linux/errno.h> | |
49 | #include <linux/timer.h> | |
50 | #include <linux/in.h> | |
51 | #include <linux/ioport.h> | |
52 | #include <linux/string.h> | |
53 | #include <linux/proc_fs.h> | |
54 | #include <linux/ptrace.h> | |
55 | #include <linux/skbuff.h> | |
56 | #include <linux/interrupt.h> | |
57 | #include <linux/delay.h> | |
58 | #include <linux/netdevice.h> | |
59 | #include <linux/trdevice.h> | |
60 | #include <linux/stddef.h> | |
61 | #include <linux/init.h> | |
62 | #include <linux/pci.h> | |
63 | #include <linux/spinlock.h> | |
64 | #include <linux/bitops.h> | |
4b6ece97 | 65 | #include <linux/firmware.h> |
5a0e3ad6 | 66 | #include <linux/slab.h> |
1da177e4 LT |
67 | |
68 | #include <net/checksum.h> | |
69 | ||
70 | #include <asm/io.h> | |
71 | #include <asm/system.h> | |
72 | ||
73 | #include "3c359.h" | |
74 | ||
75 | static char version[] __devinitdata = | |
76 | "3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ; | |
77 | ||
4b6ece97 | 78 | #define FW_NAME "3com/3C359.bin" |
1da177e4 | 79 | MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ; |
014e4668 | 80 | MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver\n") ; |
4b6ece97 | 81 | MODULE_FIRMWARE(FW_NAME); |
1da177e4 | 82 | |
98a1708d | 83 | /* Module parameters */ |
1da177e4 LT |
84 | |
85 | /* Ring Speed 0,4,16 | |
86 | * 0 = Autosense | |
87 | * 4,16 = Selected speed only, no autosense | |
88 | * This allows the card to be the first on the ring | |
89 | * and become the active monitor. | |
90 | * | |
91 | * WARNING: Some hubs will allow you to insert | |
92 | * at the wrong speed. | |
93 | * | |
94 | * The adapter will _not_ fail to open if there are no | |
95 | * active monitors on the ring, it will simply open up in | |
96 | * its last known ringspeed if no ringspeed is specified. | |
97 | */ | |
98 | ||
99 | static int ringspeed[XL_MAX_ADAPTERS] = {0,} ; | |
100 | ||
101 | module_param_array(ringspeed, int, NULL, 0); | |
61a2d07d | 102 | MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ; |
1da177e4 LT |
103 | |
104 | /* Packet buffer size */ | |
105 | ||
106 | static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ; | |
107 | ||
108 | module_param_array(pkt_buf_sz, int, NULL, 0) ; | |
61a2d07d | 109 | MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ; |
1da177e4 LT |
110 | /* Message Level */ |
111 | ||
61a2d07d | 112 | static int message_level[XL_MAX_ADAPTERS] = {0,} ; |
1da177e4 LT |
113 | |
114 | module_param_array(message_level, int, NULL, 0) ; | |
61a2d07d | 115 | MODULE_PARM_DESC(message_level, "3c359: Level of reported messages") ; |
1da177e4 LT |
116 | /* |
117 | * This is a real nasty way of doing this, but otherwise you | |
118 | * will be stuck with 1555 lines of hex #'s in the code. | |
119 | */ | |
120 | ||
a3aa1884 | 121 | static DEFINE_PCI_DEVICE_TABLE(xl_pci_tbl) = |
1da177e4 LT |
122 | { |
123 | {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, }, | |
124 | { } /* terminate list */ | |
125 | }; | |
126 | MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ; | |
127 | ||
128 | static int xl_init(struct net_device *dev); | |
129 | static int xl_open(struct net_device *dev); | |
130 | static int xl_open_hw(struct net_device *dev) ; | |
131 | static int xl_hw_reset(struct net_device *dev); | |
61a84108 | 132 | static netdev_tx_t xl_xmit(struct sk_buff *skb, struct net_device *dev); |
1da177e4 LT |
133 | static void xl_dn_comp(struct net_device *dev); |
134 | static int xl_close(struct net_device *dev); | |
135 | static void xl_set_rx_mode(struct net_device *dev); | |
7d12e780 | 136 | static irqreturn_t xl_interrupt(int irq, void *dev_id); |
1da177e4 LT |
137 | static int xl_set_mac_address(struct net_device *dev, void *addr) ; |
138 | static void xl_arb_cmd(struct net_device *dev); | |
139 | static void xl_asb_cmd(struct net_device *dev) ; | |
140 | static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ; | |
141 | static void xl_wait_misr_flags(struct net_device *dev) ; | |
142 | static int xl_change_mtu(struct net_device *dev, int mtu); | |
143 | static void xl_srb_bh(struct net_device *dev) ; | |
144 | static void xl_asb_bh(struct net_device *dev) ; | |
145 | static void xl_reset(struct net_device *dev) ; | |
146 | static void xl_freemem(struct net_device *dev) ; | |
147 | ||
148 | ||
149 | /* EEProm Access Functions */ | |
150 | static u16 xl_ee_read(struct net_device *dev, int ee_addr) ; | |
151 | static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ; | |
152 | ||
153 | /* Debugging functions */ | |
154 | #if XL_DEBUG | |
155 | static void print_tx_state(struct net_device *dev) ; | |
156 | static void print_rx_state(struct net_device *dev) ; | |
157 | ||
158 | static void print_tx_state(struct net_device *dev) | |
159 | { | |
160 | ||
eda10531 | 161 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
162 | struct xl_tx_desc *txd ; |
163 | u8 __iomem *xl_mmio = xl_priv->xl_mmio ; | |
164 | int i ; | |
165 | ||
014e4668 | 166 | printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d\n",xl_priv->tx_ring_head, |
1da177e4 | 167 | xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ; |
014e4668 | 168 | printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len\n"); |
1da177e4 LT |
169 | for (i = 0; i < 16; i++) { |
170 | txd = &(xl_priv->xl_tx_ring[i]) ; | |
014e4668 | 171 | printk("%d, %08lx, %08x, %08x, %08x, %08x\n", i, virt_to_bus(txd), |
1da177e4 LT |
172 | txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ; |
173 | } | |
174 | ||
014e4668 | 175 | printk("DNLISTPTR = %04x\n", readl(xl_mmio + MMIO_DNLISTPTR) ); |
1da177e4 | 176 | |
014e4668 FP |
177 | printk("DmaCtl = %04x\n", readl(xl_mmio + MMIO_DMA_CTRL) ); |
178 | printk("Queue status = %0x\n",netif_running(dev) ) ; | |
1da177e4 LT |
179 | } |
180 | ||
181 | static void print_rx_state(struct net_device *dev) | |
182 | { | |
183 | ||
eda10531 | 184 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
185 | struct xl_rx_desc *rxd ; |
186 | u8 __iomem *xl_mmio = xl_priv->xl_mmio ; | |
187 | int i ; | |
188 | ||
014e4668 FP |
189 | printk("rx_ring_tail: %d\n", xl_priv->rx_ring_tail); |
190 | printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len\n"); | |
1da177e4 LT |
191 | for (i = 0; i < 16; i++) { |
192 | /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */ | |
193 | rxd = &(xl_priv->xl_rx_ring[i]) ; | |
014e4668 | 194 | printk("%d, %08lx, %08x, %08x, %08x, %08x\n", i, virt_to_bus(rxd), |
1da177e4 LT |
195 | rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ; |
196 | } | |
197 | ||
014e4668 | 198 | printk("UPLISTPTR = %04x\n", readl(xl_mmio + MMIO_UPLISTPTR)); |
1da177e4 | 199 | |
014e4668 FP |
200 | printk("DmaCtl = %04x\n", readl(xl_mmio + MMIO_DMA_CTRL)); |
201 | printk("Queue status = %0x\n",netif_running(dev)); | |
1da177e4 LT |
202 | } |
203 | #endif | |
204 | ||
205 | /* | |
206 | * Read values from the on-board EEProm. This looks very strange | |
207 | * but you have to wait for the EEProm to get/set the value before | |
208 | * passing/getting the next value from the nic. As with all requests | |
209 | * on this nic it has to be done in two stages, a) tell the nic which | |
210 | * memory address you want to access and b) pass/get the value from the nic. | |
25985edc | 211 | * With the EEProm, you have to wait before and between access a) and b). |
1da177e4 LT |
212 | * As this is only read at initialization time and the wait period is very |
213 | * small we shouldn't have to worry about scheduling issues. | |
214 | */ | |
215 | ||
216 | static u16 xl_ee_read(struct net_device *dev, int ee_addr) | |
217 | { | |
eda10531 | 218 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
219 | u8 __iomem *xl_mmio = xl_priv->xl_mmio ; |
220 | ||
221 | /* Wait for EEProm to not be busy */ | |
222 | writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
223 | while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; | |
224 | ||
225 | /* Tell EEProm what we want to do and where */ | |
226 | writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
227 | writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ; | |
228 | ||
229 | /* Wait for EEProm to not be busy */ | |
230 | writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
231 | while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; | |
232 | ||
233 | /* Tell EEProm what we want to do and where */ | |
234 | writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
235 | writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ; | |
236 | ||
237 | /* Finally read the value from the EEProm */ | |
238 | writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
239 | return readw(xl_mmio + MMIO_MACDATA) ; | |
240 | } | |
241 | ||
242 | /* | |
243 | * Write values to the onboard eeprom. As with eeprom read you need to | |
244 | * set which location to write, wait, value to write, wait, with the | |
245 | * added twist of having to enable eeprom writes as well. | |
246 | */ | |
247 | ||
248 | static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) | |
249 | { | |
eda10531 | 250 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
251 | u8 __iomem *xl_mmio = xl_priv->xl_mmio ; |
252 | ||
253 | /* Wait for EEProm to not be busy */ | |
254 | writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
255 | while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; | |
256 | ||
257 | /* Enable write/erase */ | |
258 | writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
259 | writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ; | |
260 | ||
261 | /* Wait for EEProm to not be busy */ | |
262 | writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
263 | while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; | |
264 | ||
265 | /* Put the value we want to write into EEDATA */ | |
266 | writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
267 | writew(ee_value, xl_mmio + MMIO_MACDATA) ; | |
268 | ||
269 | /* Tell EEProm to write eevalue into ee_addr */ | |
270 | writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
271 | writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ; | |
272 | ||
273 | /* Wait for EEProm to not be busy, to ensure write gets done */ | |
274 | writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
275 | while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; | |
276 | ||
277 | return ; | |
278 | } | |
69d65169 SH |
279 | |
280 | static const struct net_device_ops xl_netdev_ops = { | |
281 | .ndo_open = xl_open, | |
282 | .ndo_stop = xl_close, | |
283 | .ndo_start_xmit = xl_xmit, | |
284 | .ndo_change_mtu = xl_change_mtu, | |
285 | .ndo_set_multicast_list = xl_set_rx_mode, | |
286 | .ndo_set_mac_address = xl_set_mac_address, | |
287 | }; | |
1da177e4 | 288 | |
de70b4c8 AB |
289 | static int __devinit xl_probe(struct pci_dev *pdev, |
290 | const struct pci_device_id *ent) | |
1da177e4 LT |
291 | { |
292 | struct net_device *dev ; | |
293 | struct xl_private *xl_priv ; | |
294 | static int card_no = -1 ; | |
295 | int i ; | |
296 | ||
297 | card_no++ ; | |
298 | ||
299 | if (pci_enable_device(pdev)) { | |
300 | return -ENODEV ; | |
301 | } | |
302 | ||
303 | pci_set_master(pdev); | |
304 | ||
305 | if ((i = pci_request_regions(pdev,"3c359"))) { | |
306 | return i ; | |
307 | } ; | |
308 | ||
309 | /* | |
b74ca3a8 WC |
310 | * Allowing init_trdev to allocate the private data will align |
311 | * xl_private on a 32 bytes boundary which we need for the rx/tx | |
312 | * descriptors | |
1da177e4 LT |
313 | */ |
314 | ||
315 | dev = alloc_trdev(sizeof(struct xl_private)) ; | |
316 | if (!dev) { | |
317 | pci_release_regions(pdev) ; | |
318 | return -ENOMEM ; | |
319 | } | |
eda10531 | 320 | xl_priv = netdev_priv(dev); |
1da177e4 LT |
321 | |
322 | #if XL_DEBUG | |
323 | printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n", | |
eda10531 | 324 | pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start); |
1da177e4 LT |
325 | #endif |
326 | ||
327 | dev->irq=pdev->irq; | |
328 | dev->base_addr=pci_resource_start(pdev,0) ; | |
329 | xl_priv->xl_card_name = pci_name(pdev); | |
330 | xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE); | |
331 | xl_priv->pdev = pdev ; | |
332 | ||
333 | if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) ) | |
334 | xl_priv->pkt_buf_sz = PKT_BUF_SZ ; | |
335 | else | |
336 | xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ; | |
337 | ||
338 | dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ; | |
339 | xl_priv->xl_ring_speed = ringspeed[card_no] ; | |
340 | xl_priv->xl_message_level = message_level[card_no] ; | |
341 | xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ; | |
342 | xl_priv->xl_copy_all_options = 0 ; | |
343 | ||
344 | if((i = xl_init(dev))) { | |
345 | iounmap(xl_priv->xl_mmio) ; | |
346 | free_netdev(dev) ; | |
347 | pci_release_regions(pdev) ; | |
348 | return i ; | |
349 | } | |
350 | ||
69d65169 | 351 | dev->netdev_ops = &xl_netdev_ops; |
1da177e4 LT |
352 | SET_NETDEV_DEV(dev, &pdev->dev); |
353 | ||
354 | pci_set_drvdata(pdev,dev) ; | |
355 | if ((i = register_netdev(dev))) { | |
356 | printk(KERN_ERR "3C359, register netdev failed\n") ; | |
357 | pci_set_drvdata(pdev,NULL) ; | |
358 | iounmap(xl_priv->xl_mmio) ; | |
359 | free_netdev(dev) ; | |
360 | pci_release_regions(pdev) ; | |
361 | return i ; | |
362 | } | |
363 | ||
364 | printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ; | |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
4b6ece97 JSR |
369 | static int xl_init_firmware(struct xl_private *xl_priv) |
370 | { | |
371 | int err; | |
372 | ||
373 | err = request_firmware(&xl_priv->fw, FW_NAME, &xl_priv->pdev->dev); | |
374 | if (err) { | |
375 | printk(KERN_ERR "Failed to load firmware \"%s\"\n", FW_NAME); | |
376 | return err; | |
377 | } | |
378 | ||
379 | if (xl_priv->fw->size < 16) { | |
380 | printk(KERN_ERR "Bogus length %zu in \"%s\"\n", | |
381 | xl_priv->fw->size, FW_NAME); | |
382 | release_firmware(xl_priv->fw); | |
383 | err = -EINVAL; | |
384 | } | |
385 | ||
386 | return err; | |
387 | } | |
1da177e4 | 388 | |
9b5587cd | 389 | static int __devinit xl_init(struct net_device *dev) |
1da177e4 | 390 | { |
eda10531 | 391 | struct xl_private *xl_priv = netdev_priv(dev); |
4b6ece97 | 392 | int err; |
1da177e4 | 393 | |
014e4668 | 394 | printk(KERN_INFO "%s\n", version); |
1da177e4 LT |
395 | printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n", |
396 | xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq); | |
397 | ||
398 | spin_lock_init(&xl_priv->xl_lock) ; | |
399 | ||
4b6ece97 JSR |
400 | err = xl_init_firmware(xl_priv); |
401 | if (err == 0) | |
402 | err = xl_hw_reset(dev); | |
1da177e4 | 403 | |
4b6ece97 | 404 | return err; |
1da177e4 LT |
405 | } |
406 | ||
407 | ||
408 | /* | |
409 | * Hardware reset. This needs to be a separate entity as we need to reset the card | |
410 | * when we change the EEProm settings. | |
411 | */ | |
412 | ||
413 | static int xl_hw_reset(struct net_device *dev) | |
4b6ece97 | 414 | { |
eda10531 | 415 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
416 | u8 __iomem *xl_mmio = xl_priv->xl_mmio ; |
417 | unsigned long t ; | |
418 | u16 i ; | |
419 | u16 result_16 ; | |
420 | u8 result_8 ; | |
421 | u16 start ; | |
422 | int j ; | |
423 | ||
4b6ece97 JSR |
424 | if (xl_priv->fw == NULL) |
425 | return -EINVAL; | |
426 | ||
1da177e4 LT |
427 | /* |
428 | * Reset the card. If the card has got the microcode on board, we have | |
429 | * missed the initialization interrupt, so we must always do this. | |
430 | */ | |
431 | ||
432 | writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ; | |
433 | ||
434 | /* | |
435 | * Must wait for cmdInProgress bit (12) to clear before continuing with | |
436 | * card configuration. | |
437 | */ | |
438 | ||
439 | t=jiffies; | |
440 | while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { | |
441 | schedule(); | |
b7aa6909 | 442 | if (time_after(jiffies, t + 40 * HZ)) { |
1da177e4 LT |
443 | printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name); |
444 | return -ENODEV; | |
445 | } | |
446 | } | |
447 | ||
448 | /* | |
449 | * Enable pmbar by setting bit in CPAttention | |
450 | */ | |
451 | ||
452 | writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
453 | result_8 = readb(xl_mmio + MMIO_MACDATA) ; | |
454 | result_8 = result_8 | CPA_PMBARVIS ; | |
455 | writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
456 | writeb(result_8, xl_mmio + MMIO_MACDATA) ; | |
457 | ||
458 | /* | |
459 | * Read cpHold bit in pmbar, if cleared we have got Flashrom on board. | |
460 | * If not, we need to upload the microcode to the card | |
461 | */ | |
462 | ||
463 | writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD); | |
464 | ||
465 | #if XL_DEBUG | |
014e4668 | 466 | printk(KERN_INFO "Read from PMBAR = %04x\n", readw(xl_mmio + MMIO_MACDATA)); |
1da177e4 LT |
467 | #endif |
468 | ||
469 | if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) { | |
470 | ||
471 | /* Set PmBar, privateMemoryBase bits (8:2) to 0 */ | |
472 | ||
473 | writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD); | |
474 | result_16 = readw(xl_mmio + MMIO_MACDATA) ; | |
475 | result_16 = result_16 & ~((0x7F) << 2) ; | |
476 | writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
477 | writew(result_16,xl_mmio + MMIO_MACDATA) ; | |
478 | ||
479 | /* Set CPAttention, memWrEn bit */ | |
480 | ||
481 | writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
482 | result_8 = readb(xl_mmio + MMIO_MACDATA) ; | |
483 | result_8 = result_8 | CPA_MEMWREN ; | |
484 | writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
485 | writeb(result_8, xl_mmio + MMIO_MACDATA) ; | |
486 | ||
487 | /* | |
488 | * Now to write the microcode into the shared ram | |
4b6ece97 JSR |
489 | * The microcode must finish at position 0xFFFF, |
490 | * so we must subtract to get the start position for the code | |
491 | * | |
492 | * Looks strange but ensures compiler only uses | |
493 | * 16 bit unsigned int | |
1da177e4 | 494 | */ |
4b6ece97 | 495 | start = (0xFFFF - (xl_priv->fw->size) + 1) ; |
1da177e4 | 496 | |
1da177e4 | 497 | printk(KERN_INFO "3C359: Uploading Microcode: "); |
4b6ece97 JSR |
498 | |
499 | for (i = start, j = 0; j < xl_priv->fw->size; i++, j++) { | |
500 | writel(MEM_BYTE_WRITE | 0XD0000 | i, | |
501 | xl_mmio + MMIO_MAC_ACCESS_CMD); | |
502 | writeb(xl_priv->fw->data[j], xl_mmio + MMIO_MACDATA); | |
1da177e4 LT |
503 | if (j % 1024 == 0) |
504 | printk("."); | |
505 | } | |
506 | printk("\n") ; | |
507 | ||
4b6ece97 JSR |
508 | for (i = 0; i < 16; i++) { |
509 | writel((MEM_BYTE_WRITE | 0xDFFF0) + i, | |
510 | xl_mmio + MMIO_MAC_ACCESS_CMD); | |
511 | writeb(xl_priv->fw->data[xl_priv->fw->size - 16 + i], | |
512 | xl_mmio + MMIO_MACDATA); | |
1da177e4 LT |
513 | } |
514 | ||
515 | /* | |
516 | * Have to write the start address of the upload to FFF4, but | |
517 | * the address must be >> 4. You do not want to know how long | |
518 | * it took me to discover this. | |
519 | */ | |
520 | ||
521 | writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
522 | writew(start >> 4, xl_mmio + MMIO_MACDATA); | |
523 | ||
524 | /* Clear the CPAttention, memWrEn Bit */ | |
525 | ||
526 | writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
527 | result_8 = readb(xl_mmio + MMIO_MACDATA) ; | |
528 | result_8 = result_8 & ~CPA_MEMWREN ; | |
529 | writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
530 | writeb(result_8, xl_mmio + MMIO_MACDATA) ; | |
531 | ||
532 | /* Clear the cpHold bit in pmbar */ | |
533 | ||
534 | writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD); | |
535 | result_16 = readw(xl_mmio + MMIO_MACDATA) ; | |
536 | result_16 = result_16 & ~PMB_CPHOLD ; | |
537 | writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
538 | writew(result_16,xl_mmio + MMIO_MACDATA) ; | |
539 | ||
540 | ||
541 | } /* If microcode upload required */ | |
542 | ||
543 | /* | |
544 | * The card should now go though a self test procedure and get itself ready | |
545 | * to be opened, we must wait for an srb response with the initialization | |
546 | * information. | |
547 | */ | |
548 | ||
549 | #if XL_DEBUG | |
550 | printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name); | |
551 | #endif | |
552 | ||
553 | writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ; | |
554 | ||
555 | t=jiffies; | |
556 | while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) { | |
557 | schedule(); | |
b7aa6909 | 558 | if (time_after(jiffies, t + 15 * HZ)) { |
1da177e4 LT |
559 | printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n"); |
560 | return -ENODEV; | |
561 | } | |
562 | } | |
563 | ||
564 | /* | |
565 | * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh, | |
566 | * DnPriReqThresh, read the tech docs if you want to know what | |
567 | * values they need to be. | |
568 | */ | |
569 | ||
570 | writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
571 | writew(0xD000, xl_mmio + MMIO_MACDATA) ; | |
572 | ||
573 | writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
574 | writew(0X0020, xl_mmio + MMIO_MACDATA) ; | |
575 | ||
576 | writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ; | |
577 | ||
578 | writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ; | |
579 | writeb(0x04, xl_mmio + DNPRIREQTHRESH) ; | |
580 | ||
581 | /* | |
582 | * Read WRBR to provide the location of the srb block, have to use byte reads not word reads. | |
583 | * Tech docs have this wrong !!!! | |
584 | */ | |
585 | ||
586 | writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
587 | xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ; | |
588 | writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
589 | xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ; | |
590 | ||
591 | #if XL_DEBUG | |
592 | writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
593 | if ( readw(xl_mmio + MMIO_MACDATA) & 2) { | |
014e4668 | 594 | printk(KERN_INFO "Default ring speed 4 mbps\n"); |
1da177e4 | 595 | } else { |
014e4668 | 596 | printk(KERN_INFO "Default ring speed 16 mbps\n"); |
1da177e4 LT |
597 | } |
598 | printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb); | |
599 | #endif | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | static int xl_open(struct net_device *dev) | |
605 | { | |
eda10531 | 606 | struct xl_private *xl_priv=netdev_priv(dev); |
1da177e4 LT |
607 | u8 __iomem *xl_mmio = xl_priv->xl_mmio ; |
608 | u8 i ; | |
9914cad5 | 609 | __le16 hwaddr[3] ; /* Should be u8[6] but we get word return values */ |
1da177e4 LT |
610 | int open_err ; |
611 | ||
612 | u16 switchsettings, switchsettings_eeprom ; | |
613 | ||
dddcb445 | 614 | if (request_irq(dev->irq, xl_interrupt, IRQF_SHARED , "3c359", dev)) |
1da177e4 | 615 | return -EAGAIN; |
1da177e4 LT |
616 | |
617 | /* | |
9914cad5 | 618 | * Read the information from the EEPROM that we need. |
1da177e4 LT |
619 | */ |
620 | ||
9914cad5 AV |
621 | hwaddr[0] = cpu_to_le16(xl_ee_read(dev,0x10)); |
622 | hwaddr[1] = cpu_to_le16(xl_ee_read(dev,0x11)); | |
623 | hwaddr[2] = cpu_to_le16(xl_ee_read(dev,0x12)); | |
1da177e4 LT |
624 | |
625 | /* Ring speed */ | |
626 | ||
627 | switchsettings_eeprom = xl_ee_read(dev,0x08) ; | |
628 | switchsettings = switchsettings_eeprom ; | |
629 | ||
630 | if (xl_priv->xl_ring_speed != 0) { | |
631 | if (xl_priv->xl_ring_speed == 4) | |
632 | switchsettings = switchsettings | 0x02 ; | |
633 | else | |
634 | switchsettings = switchsettings & ~0x02 ; | |
635 | } | |
636 | ||
637 | /* Only write EEProm if there has been a change */ | |
638 | if (switchsettings != switchsettings_eeprom) { | |
639 | xl_ee_write(dev,0x08,switchsettings) ; | |
640 | /* Hardware reset after changing EEProm */ | |
641 | xl_hw_reset(dev) ; | |
642 | } | |
643 | ||
644 | memcpy(dev->dev_addr,hwaddr,dev->addr_len) ; | |
645 | ||
646 | open_err = xl_open_hw(dev) ; | |
647 | ||
648 | /* | |
649 | * This really needs to be cleaned up with better error reporting. | |
650 | */ | |
651 | ||
652 | if (open_err != 0) { /* Something went wrong with the open command */ | |
653 | if (open_err & 0x07) { /* Wrong speed, retry at different speed */ | |
014e4668 | 654 | printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed\n", dev->name); |
1da177e4 LT |
655 | switchsettings = switchsettings ^ 2 ; |
656 | xl_ee_write(dev,0x08,switchsettings) ; | |
657 | xl_hw_reset(dev) ; | |
658 | open_err = xl_open_hw(dev) ; | |
659 | if (open_err != 0) { | |
660 | printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name); | |
661 | free_irq(dev->irq,dev) ; | |
662 | return -ENODEV ; | |
663 | } | |
664 | } else { | |
665 | printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ; | |
666 | free_irq(dev->irq,dev) ; | |
667 | return -ENODEV ; | |
668 | } | |
669 | } | |
670 | ||
671 | /* | |
672 | * Now to set up the Rx and Tx buffer structures | |
673 | */ | |
674 | /* These MUST be on 8 byte boundaries */ | |
c821d55c | 675 | xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL); |
1da177e4 | 676 | if (xl_priv->xl_tx_ring == NULL) { |
138a5cdf | 677 | printk(KERN_WARNING "%s: Not enough memory to allocate tx buffers.\n", |
1da177e4 LT |
678 | dev->name); |
679 | free_irq(dev->irq,dev); | |
680 | return -ENOMEM; | |
681 | } | |
c821d55c | 682 | xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL); |
d0cc10ab | 683 | if (xl_priv->xl_rx_ring == NULL) { |
1da177e4 LT |
684 | printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n", |
685 | dev->name); | |
686 | free_irq(dev->irq,dev); | |
687 | kfree(xl_priv->xl_tx_ring); | |
688 | return -ENOMEM; | |
689 | } | |
1da177e4 LT |
690 | |
691 | /* Setup Rx Ring */ | |
692 | for (i=0 ; i < XL_RX_RING_SIZE ; i++) { | |
693 | struct sk_buff *skb ; | |
694 | ||
695 | skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ; | |
696 | if (skb==NULL) | |
697 | break ; | |
698 | ||
699 | skb->dev = dev ; | |
9914cad5 AV |
700 | xl_priv->xl_rx_ring[i].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE)); |
701 | xl_priv->xl_rx_ring[i].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG; | |
1da177e4 LT |
702 | xl_priv->rx_ring_skb[i] = skb ; |
703 | } | |
704 | ||
705 | if (i==0) { | |
014e4668 | 706 | printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled\n",dev->name); |
1da177e4 | 707 | free_irq(dev->irq,dev) ; |
5c94afd7 JP |
708 | kfree(xl_priv->xl_tx_ring); |
709 | kfree(xl_priv->xl_rx_ring); | |
1da177e4 LT |
710 | return -EIO ; |
711 | } | |
712 | ||
713 | xl_priv->rx_ring_no = i ; | |
714 | xl_priv->rx_ring_tail = 0 ; | |
715 | xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ; | |
716 | for (i=0;i<(xl_priv->rx_ring_no-1);i++) { | |
9914cad5 | 717 | xl_priv->xl_rx_ring[i].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1))); |
1da177e4 LT |
718 | } |
719 | xl_priv->xl_rx_ring[i].upnextptr = 0 ; | |
720 | ||
721 | writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ; | |
722 | ||
723 | /* Setup Tx Ring */ | |
724 | ||
725 | xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ; | |
726 | ||
727 | xl_priv->tx_ring_head = 1 ; | |
728 | xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */ | |
729 | xl_priv->free_ring_entries = XL_TX_RING_SIZE ; | |
730 | ||
731 | /* | |
732 | * Setup the first dummy DPD entry for polling to start working. | |
733 | */ | |
734 | ||
9914cad5 | 735 | xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY; |
1da177e4 LT |
736 | xl_priv->xl_tx_ring[0].buffer = 0 ; |
737 | xl_priv->xl_tx_ring[0].buffer_length = 0 ; | |
738 | xl_priv->xl_tx_ring[0].dnnextptr = 0 ; | |
739 | ||
740 | writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ; | |
741 | writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ; | |
742 | writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ; | |
743 | writel(DNENABLE, xl_mmio + MMIO_COMMAND) ; | |
744 | writeb(0x40, xl_mmio + MMIO_DNPOLL) ; | |
745 | ||
746 | /* | |
747 | * Enable interrupts on the card | |
748 | */ | |
749 | ||
750 | writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; | |
751 | writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; | |
752 | ||
753 | netif_start_queue(dev) ; | |
754 | return 0; | |
755 | ||
756 | } | |
757 | ||
758 | static int xl_open_hw(struct net_device *dev) | |
759 | { | |
eda10531 | 760 | struct xl_private *xl_priv=netdev_priv(dev); |
1da177e4 LT |
761 | u8 __iomem *xl_mmio = xl_priv->xl_mmio ; |
762 | u16 vsoff ; | |
763 | char ver_str[33]; | |
764 | int open_err ; | |
765 | int i ; | |
766 | unsigned long t ; | |
767 | ||
768 | /* | |
769 | * Okay, let's build up the Open.NIC srb command | |
770 | * | |
771 | */ | |
772 | ||
773 | writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
774 | writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ; | |
775 | ||
776 | /* | |
777 | * Use this as a test byte, if it comes back with the same value, the command didn't work | |
778 | */ | |
779 | ||
780 | writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
781 | writeb(0xff,xl_mmio + MMIO_MACDATA) ; | |
782 | ||
783 | /* Open options */ | |
784 | writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
785 | writeb(0x00, xl_mmio + MMIO_MACDATA) ; | |
786 | writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
787 | writeb(0x00, xl_mmio + MMIO_MACDATA) ; | |
788 | ||
789 | /* | |
790 | * Node address, be careful here, the docs say you can just put zeros here and it will use | |
791 | * the hardware address, it doesn't, you must include the node address in the open command. | |
792 | */ | |
793 | ||
794 | if (xl_priv->xl_laa[0]) { /* If using a LAA address */ | |
795 | for (i=10;i<16;i++) { | |
796 | writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
9a7387c2 | 797 | writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ; |
1da177e4 LT |
798 | } |
799 | memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ; | |
800 | } else { /* Regular hardware address */ | |
801 | for (i=10;i<16;i++) { | |
802 | writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
803 | writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ; | |
804 | } | |
805 | } | |
806 | ||
807 | /* Default everything else to 0 */ | |
808 | for (i = 16; i < 34; i++) { | |
809 | writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
810 | writeb(0x00,xl_mmio + MMIO_MACDATA) ; | |
811 | } | |
812 | ||
813 | /* | |
814 | * Set the csrb bit in the MISR register | |
815 | */ | |
816 | ||
817 | xl_wait_misr_flags(dev) ; | |
818 | writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
819 | writeb(0xFF, xl_mmio + MMIO_MACDATA) ; | |
820 | writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
821 | writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ; | |
822 | ||
823 | /* | |
824 | * Now wait for the command to run | |
825 | */ | |
826 | ||
827 | t=jiffies; | |
828 | while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) { | |
829 | schedule(); | |
b7aa6909 | 830 | if (time_after(jiffies, t + 40 * HZ)) { |
1da177e4 LT |
831 | printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n"); |
832 | break ; | |
833 | } | |
834 | } | |
835 | ||
836 | /* | |
837 | * Let's interpret the open response | |
838 | */ | |
839 | ||
840 | writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
841 | if (readb(xl_mmio + MMIO_MACDATA)!=0) { | |
842 | open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ; | |
843 | writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
844 | open_err |= readb(xl_mmio + MMIO_MACDATA) ; | |
845 | return open_err ; | |
846 | } else { | |
847 | writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
9914cad5 | 848 | xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ; |
1da177e4 LT |
849 | printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ; |
850 | printk("ASB: %04x",xl_priv->asb ) ; | |
851 | writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
9914cad5 | 852 | printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ; |
1da177e4 LT |
853 | |
854 | writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
9914cad5 | 855 | xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ; |
014e4668 | 856 | printk(", ARB: %04x\n",xl_priv->arb ); |
1da177e4 | 857 | writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ; |
9914cad5 | 858 | vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ; |
1da177e4 LT |
859 | |
860 | /* | |
861 | * Interesting, sending the individual characters directly to printk was causing klogd to use | |
862 | * use 100% of processor time, so we build up the string and print that instead. | |
863 | */ | |
864 | ||
865 | for (i=0;i<0x20;i++) { | |
866 | writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
867 | ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ; | |
868 | } | |
869 | ver_str[i] = '\0' ; | |
014e4668 | 870 | printk(KERN_INFO "%s: Microcode version String: %s\n",dev->name,ver_str); |
1da177e4 LT |
871 | } |
872 | ||
873 | /* | |
874 | * Issue the AckInterrupt | |
875 | */ | |
876 | writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; | |
877 | ||
878 | return 0 ; | |
879 | } | |
880 | ||
881 | /* | |
882 | * There are two ways of implementing rx on the 359 NIC, either | |
883 | * interrupt driven or polling. We are going to uses interrupts, | |
884 | * it is the easier way of doing things. | |
885 | * | |
886 | * The Rx works with a ring of Rx descriptors. At initialise time the ring | |
887 | * entries point to the next entry except for the last entry in the ring | |
888 | * which points to 0. The card is programmed with the location of the first | |
889 | * available descriptor and keeps reading the next_ptr until next_ptr is set | |
890 | * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr | |
891 | * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers | |
892 | * and then point the end of the ring to our current position and point our current | |
893 | * position to 0, therefore making the current position the last position on the ring. | |
894 | * The last position on the ring therefore loops continually loops around the rx ring. | |
895 | * | |
896 | * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head | |
897 | * expands as the card adds new packets and we go around eating the tail processing the | |
898 | * packets.) | |
899 | * | |
900 | * Undoubtably it could be streamlined and improved upon, but at the moment it works | |
901 | * and the fast path through the routine is fine. | |
902 | * | |
903 | * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times | |
904 | * in xl_rx so would increase the size of the function significantly. | |
905 | */ | |
906 | ||
907 | static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */ | |
908 | { | |
eda10531 | 909 | struct xl_private *xl_priv=netdev_priv(dev); |
9914cad5 AV |
910 | int n = xl_priv->rx_ring_tail; |
911 | int prev_ring_loc; | |
912 | ||
913 | prev_ring_loc = (n + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1); | |
914 | xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * n)); | |
915 | xl_priv->xl_rx_ring[n].framestatus = 0; | |
916 | xl_priv->xl_rx_ring[n].upnextptr = 0; | |
917 | xl_priv->rx_ring_tail++; | |
918 | xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1); | |
1da177e4 LT |
919 | } |
920 | ||
921 | static void xl_rx(struct net_device *dev) | |
922 | { | |
eda10531 | 923 | struct xl_private *xl_priv=netdev_priv(dev); |
1da177e4 LT |
924 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
925 | struct sk_buff *skb, *skb2 ; | |
926 | int frame_length = 0, copy_len = 0 ; | |
927 | int temp_ring_loc ; | |
928 | ||
929 | /* | |
930 | * Receive the next frame, loop around the ring until all frames | |
931 | * have been received. | |
932 | */ | |
933 | ||
934 | while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */ | |
935 | ||
936 | if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */ | |
937 | ||
938 | /* | |
939 | * This is a pain, you need to go through all the descriptors until the last one | |
940 | * for this frame to find the framelength | |
941 | */ | |
942 | ||
943 | temp_ring_loc = xl_priv->rx_ring_tail ; | |
944 | ||
945 | while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) { | |
946 | temp_ring_loc++ ; | |
947 | temp_ring_loc &= (XL_RX_RING_SIZE-1) ; | |
948 | } | |
949 | ||
9914cad5 | 950 | frame_length = le32_to_cpu(xl_priv->xl_rx_ring[temp_ring_loc].framestatus) & 0x7FFF; |
1da177e4 LT |
951 | |
952 | skb = dev_alloc_skb(frame_length) ; | |
953 | ||
954 | if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */ | |
955 | printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ; | |
956 | while (xl_priv->rx_ring_tail != temp_ring_loc) | |
957 | adv_rx_ring(dev) ; | |
958 | ||
959 | adv_rx_ring(dev) ; /* One more time just for luck :) */ | |
94f9d298 | 960 | dev->stats.rx_dropped++ ; |
1da177e4 LT |
961 | |
962 | writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; | |
963 | return ; | |
964 | } | |
965 | ||
1da177e4 | 966 | while (xl_priv->rx_ring_tail != temp_ring_loc) { |
9914cad5 | 967 | copy_len = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen) & 0x7FFF; |
1da177e4 | 968 | frame_length -= copy_len ; |
9914cad5 | 969 | pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); |
d626f62b ACM |
970 | skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail], |
971 | skb_put(skb, copy_len), | |
972 | copy_len); | |
9914cad5 | 973 | pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); |
1da177e4 LT |
974 | adv_rx_ring(dev) ; |
975 | } | |
976 | ||
977 | /* Now we have found the last fragment */ | |
9914cad5 | 978 | pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); |
d626f62b ACM |
979 | skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail], |
980 | skb_put(skb,copy_len), frame_length); | |
1da177e4 | 981 | /* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */ |
9914cad5 | 982 | pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); |
1da177e4 LT |
983 | adv_rx_ring(dev) ; |
984 | skb->protocol = tr_type_trans(skb,dev) ; | |
985 | netif_rx(skb) ; | |
986 | ||
987 | } else { /* Single Descriptor Used, simply swap buffers over, fast path */ | |
988 | ||
9914cad5 | 989 | frame_length = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus) & 0x7FFF; |
1da177e4 LT |
990 | |
991 | skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ; | |
992 | ||
993 | if (skb==NULL) { /* Still need to fix the rx ring */ | |
014e4668 | 994 | printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer\n",dev->name); |
1da177e4 | 995 | adv_rx_ring(dev) ; |
94f9d298 | 996 | dev->stats.rx_dropped++ ; |
1da177e4 LT |
997 | writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; |
998 | return ; | |
999 | } | |
1000 | ||
1da177e4 | 1001 | skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ; |
9914cad5 | 1002 | pci_unmap_single(xl_priv->pdev, le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ; |
1da177e4 LT |
1003 | skb_put(skb2, frame_length) ; |
1004 | skb2->protocol = tr_type_trans(skb2,dev) ; | |
1005 | ||
1006 | xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ; | |
9914cad5 AV |
1007 | xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE)); |
1008 | xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG; | |
1da177e4 | 1009 | adv_rx_ring(dev) ; |
94f9d298 PZ |
1010 | dev->stats.rx_packets++ ; |
1011 | dev->stats.rx_bytes += frame_length ; | |
1da177e4 LT |
1012 | |
1013 | netif_rx(skb2) ; | |
1014 | } /* if multiple buffers */ | |
1da177e4 LT |
1015 | } /* while packet to do */ |
1016 | ||
1017 | /* Clear the updComplete interrupt */ | |
1018 | writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; | |
1019 | return ; | |
1020 | } | |
1021 | ||
1022 | /* | |
1023 | * This is ruthless, it doesn't care what state the card is in it will | |
1024 | * completely reset the adapter. | |
1025 | */ | |
1026 | ||
1027 | static void xl_reset(struct net_device *dev) | |
1028 | { | |
eda10531 | 1029 | struct xl_private *xl_priv=netdev_priv(dev); |
1da177e4 LT |
1030 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1031 | unsigned long t; | |
1032 | ||
1033 | writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ; | |
1034 | ||
1035 | /* | |
1036 | * Must wait for cmdInProgress bit (12) to clear before continuing with | |
1037 | * card configuration. | |
1038 | */ | |
1039 | ||
1040 | t=jiffies; | |
1041 | while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { | |
b7aa6909 | 1042 | if (time_after(jiffies, t + 40 * HZ)) { |
1da177e4 LT |
1043 | printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n"); |
1044 | break ; | |
1045 | } | |
1046 | } | |
1047 | ||
1048 | } | |
1049 | ||
1050 | static void xl_freemem(struct net_device *dev) | |
1051 | { | |
eda10531 | 1052 | struct xl_private *xl_priv=netdev_priv(dev); |
1da177e4 LT |
1053 | int i ; |
1054 | ||
1055 | for (i=0;i<XL_RX_RING_SIZE;i++) { | |
1056 | dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ; | |
9914cad5 | 1057 | pci_unmap_single(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1058 | xl_priv->rx_ring_tail++ ; |
1059 | xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1; | |
1060 | } | |
1061 | ||
1062 | /* unmap ring */ | |
1063 | pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ; | |
1064 | ||
1065 | pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ; | |
1066 | ||
1067 | kfree(xl_priv->xl_rx_ring) ; | |
1068 | kfree(xl_priv->xl_tx_ring) ; | |
1069 | ||
1070 | return ; | |
1071 | } | |
1072 | ||
7d12e780 | 1073 | static irqreturn_t xl_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1074 | { |
1075 | struct net_device *dev = (struct net_device *)dev_id; | |
eda10531 | 1076 | struct xl_private *xl_priv =netdev_priv(dev); |
1da177e4 LT |
1077 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1078 | u16 intstatus, macstatus ; | |
1079 | ||
1da177e4 LT |
1080 | intstatus = readw(xl_mmio + MMIO_INTSTATUS) ; |
1081 | ||
1082 | if (!(intstatus & 1)) /* We didn't generate the interrupt */ | |
1083 | return IRQ_NONE; | |
1084 | ||
1085 | spin_lock(&xl_priv->xl_lock) ; | |
1086 | ||
1087 | /* | |
1088 | * Process the interrupt | |
1089 | */ | |
1090 | /* | |
1091 | * Something fishy going on here, we shouldn't get 0001 ints, not fatal though. | |
1092 | */ | |
1093 | if (intstatus == 0x0001) { | |
1094 | writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; | |
014e4668 | 1095 | printk(KERN_INFO "%s: 00001 int received\n",dev->name); |
1da177e4 LT |
1096 | } else { |
1097 | if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) { | |
1098 | ||
1099 | /* | |
1100 | * Host Error. | |
1101 | * It may be possible to recover from this, but usually it means something | |
1102 | * is seriously fubar, so we just close the adapter. | |
1103 | */ | |
1104 | ||
1105 | if (intstatus & HOSTERRINT) { | |
014e4668 | 1106 | printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x\n",dev->name,intstatus); |
1da177e4 | 1107 | writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ; |
014e4668 | 1108 | printk(KERN_WARNING "%s: Resetting hardware:\n", dev->name); |
1da177e4 LT |
1109 | netif_stop_queue(dev) ; |
1110 | xl_freemem(dev) ; | |
1111 | free_irq(dev->irq,dev); | |
1112 | xl_reset(dev) ; | |
1113 | writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; | |
1114 | spin_unlock(&xl_priv->xl_lock) ; | |
1115 | return IRQ_HANDLED; | |
1116 | } /* Host Error */ | |
1117 | ||
1118 | if (intstatus & SRBRINT ) { /* Srbc interrupt */ | |
1119 | writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; | |
1120 | if (xl_priv->srb_queued) | |
1121 | xl_srb_bh(dev) ; | |
1122 | } /* SRBR Interrupt */ | |
1123 | ||
1124 | if (intstatus & TXUNDERRUN) { /* Issue DnReset command */ | |
1125 | writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1126 | while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */ | |
1127 | /* !!! FIX-ME !!!! | |
1128 | Must put a timeout check here ! */ | |
1129 | /* Empty Loop */ | |
1130 | } | |
014e4668 | 1131 | printk(KERN_WARNING "%s: TX Underrun received\n",dev->name); |
1da177e4 LT |
1132 | writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; |
1133 | } /* TxUnderRun */ | |
1134 | ||
1135 | if (intstatus & ARBCINT ) { /* Arbc interrupt */ | |
1136 | xl_arb_cmd(dev) ; | |
1137 | } /* Arbc */ | |
1138 | ||
1139 | if (intstatus & ASBFINT) { | |
1140 | if (xl_priv->asb_queued == 1) { | |
1141 | xl_asb_cmd(dev) ; | |
1142 | } else if (xl_priv->asb_queued == 2) { | |
1143 | xl_asb_bh(dev) ; | |
1144 | } else { | |
1145 | writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ; | |
1146 | } | |
1147 | } /* Asbf */ | |
1148 | ||
1149 | if (intstatus & UPCOMPINT ) /* UpComplete */ | |
1150 | xl_rx(dev) ; | |
1151 | ||
1152 | if (intstatus & DNCOMPINT ) /* DnComplete */ | |
1153 | xl_dn_comp(dev) ; | |
1154 | ||
1155 | if (intstatus & HARDERRINT ) { /* Hardware error */ | |
1156 | writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1157 | macstatus = readw(xl_mmio + MMIO_MACDATA) ; | |
1158 | printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name); | |
1159 | if (macstatus & (1<<14)) | |
014e4668 | 1160 | printk(KERN_WARNING "tchk error: Unrecoverable error\n"); |
1da177e4 | 1161 | if (macstatus & (1<<3)) |
014e4668 | 1162 | printk(KERN_WARNING "eint error: Internal watchdog timer expired\n"); |
1da177e4 | 1163 | if (macstatus & (1<<2)) |
014e4668 | 1164 | printk(KERN_WARNING "aint error: Host tried to perform invalid operation\n"); |
1da177e4 | 1165 | printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ; |
014e4668 | 1166 | printk(KERN_WARNING "%s: Resetting hardware:\n", dev->name); |
1da177e4 LT |
1167 | netif_stop_queue(dev) ; |
1168 | xl_freemem(dev) ; | |
1169 | free_irq(dev->irq,dev); | |
1170 | unregister_netdev(dev) ; | |
1171 | free_netdev(dev) ; | |
1172 | xl_reset(dev) ; | |
1173 | writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; | |
1174 | spin_unlock(&xl_priv->xl_lock) ; | |
1175 | return IRQ_HANDLED; | |
1176 | } | |
1177 | } else { | |
014e4668 | 1178 | printk(KERN_WARNING "%s: Received Unknown interrupt : %04x\n", dev->name, intstatus); |
1da177e4 LT |
1179 | writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; |
1180 | } | |
1181 | } | |
1182 | ||
1183 | /* Turn interrupts back on */ | |
1184 | ||
1185 | writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; | |
1186 | writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; | |
1187 | ||
1188 | spin_unlock(&xl_priv->xl_lock) ; | |
1189 | return IRQ_HANDLED; | |
1190 | } | |
1191 | ||
1192 | /* | |
1193 | * Tx - Polling configuration | |
1194 | */ | |
1195 | ||
61a84108 | 1196 | static netdev_tx_t xl_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 1197 | { |
eda10531 | 1198 | struct xl_private *xl_priv=netdev_priv(dev); |
1da177e4 LT |
1199 | struct xl_tx_desc *txd ; |
1200 | int tx_head, tx_tail, tx_prev ; | |
1201 | unsigned long flags ; | |
1202 | ||
1203 | spin_lock_irqsave(&xl_priv->xl_lock,flags) ; | |
1204 | ||
1205 | netif_stop_queue(dev) ; | |
1206 | ||
1207 | if (xl_priv->free_ring_entries > 1 ) { | |
1208 | /* | |
1209 | * Set up the descriptor for the packet | |
1210 | */ | |
1211 | tx_head = xl_priv->tx_ring_head ; | |
1212 | tx_tail = xl_priv->tx_ring_tail ; | |
1213 | ||
1214 | txd = &(xl_priv->xl_tx_ring[tx_head]) ; | |
1215 | txd->dnnextptr = 0 ; | |
9914cad5 AV |
1216 | txd->framestartheader = cpu_to_le32(skb->len) | TXDNINDICATE; |
1217 | txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE)); | |
1218 | txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST; | |
1da177e4 | 1219 | xl_priv->tx_ring_skb[tx_head] = skb ; |
94f9d298 PZ |
1220 | dev->stats.tx_packets++ ; |
1221 | dev->stats.tx_bytes += skb->len ; | |
1da177e4 LT |
1222 | |
1223 | /* | |
1224 | * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1 | |
1225 | * to ensure no negative numbers in unsigned locations. | |
1226 | */ | |
1227 | ||
1228 | tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ; | |
1229 | ||
1230 | xl_priv->tx_ring_head++ ; | |
1231 | xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ; | |
1232 | xl_priv->free_ring_entries-- ; | |
1233 | ||
9914cad5 | 1234 | xl_priv->xl_tx_ring[tx_prev].dnnextptr = cpu_to_le32(xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head)); |
1da177e4 LT |
1235 | |
1236 | /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */ | |
1237 | /* readl(xl_mmio + MMIO_DNLISTPTR) ; */ | |
1238 | ||
1239 | netif_wake_queue(dev) ; | |
1240 | ||
1241 | spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ; | |
1242 | ||
6ed10654 | 1243 | return NETDEV_TX_OK; |
1da177e4 LT |
1244 | } else { |
1245 | spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ; | |
5b548140 | 1246 | return NETDEV_TX_BUSY; |
1da177e4 LT |
1247 | } |
1248 | ||
1249 | } | |
1250 | ||
1251 | /* | |
1252 | * The NIC has told us that a packet has been downloaded onto the card, we must | |
1253 | * find out which packet it has done, clear the skb and information for the packet | |
1254 | * then advance around the ring for all tranmitted packets | |
1255 | */ | |
1256 | ||
1257 | static void xl_dn_comp(struct net_device *dev) | |
1258 | { | |
eda10531 | 1259 | struct xl_private *xl_priv=netdev_priv(dev); |
1da177e4 LT |
1260 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1261 | struct xl_tx_desc *txd ; | |
1262 | ||
1263 | ||
1264 | if (xl_priv->tx_ring_tail == 255) {/* First time */ | |
1265 | xl_priv->xl_tx_ring[0].framestartheader = 0 ; | |
1266 | xl_priv->xl_tx_ring[0].dnnextptr = 0 ; | |
1267 | xl_priv->tx_ring_tail = 1 ; | |
1268 | } | |
1269 | ||
1270 | while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) { | |
1271 | txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ; | |
9914cad5 | 1272 | pci_unmap_single(xl_priv->pdev, le32_to_cpu(txd->buffer), xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE); |
1da177e4 | 1273 | txd->framestartheader = 0 ; |
9914cad5 | 1274 | txd->buffer = cpu_to_le32(0xdeadbeef); |
1da177e4 LT |
1275 | txd->buffer_length = 0 ; |
1276 | dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ; | |
1277 | xl_priv->tx_ring_tail++ ; | |
1278 | xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ; | |
1279 | xl_priv->free_ring_entries++ ; | |
1280 | } | |
1281 | ||
1282 | netif_wake_queue(dev) ; | |
1283 | ||
1284 | writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; | |
1285 | } | |
1286 | ||
1287 | /* | |
1288 | * Close the adapter properly. | |
1289 | * This srb reply cannot be handled from interrupt context as we have | |
1290 | * to free the interrupt from the driver. | |
1291 | */ | |
1292 | ||
1293 | static int xl_close(struct net_device *dev) | |
1294 | { | |
eda10531 | 1295 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
1296 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1297 | unsigned long t ; | |
1298 | ||
1299 | netif_stop_queue(dev) ; | |
1300 | ||
1301 | /* | |
1302 | * Close the adapter, need to stall the rx and tx queues. | |
1303 | */ | |
1304 | ||
1305 | writew(DNSTALL, xl_mmio + MMIO_COMMAND) ; | |
1306 | t=jiffies; | |
1307 | while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { | |
1308 | schedule(); | |
b7aa6909 | 1309 | if (time_after(jiffies, t + 10 * HZ)) { |
1da177e4 LT |
1310 | printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name); |
1311 | break ; | |
1312 | } | |
1313 | } | |
1314 | writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ; | |
1315 | t=jiffies; | |
1316 | while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { | |
1317 | schedule(); | |
b7aa6909 | 1318 | if (time_after(jiffies, t + 10 * HZ)) { |
1da177e4 LT |
1319 | printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name); |
1320 | break ; | |
1321 | } | |
1322 | } | |
1323 | writew(UPSTALL, xl_mmio + MMIO_COMMAND) ; | |
1324 | t=jiffies; | |
1325 | while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { | |
1326 | schedule(); | |
b7aa6909 | 1327 | if (time_after(jiffies, t + 10 * HZ)) { |
1da177e4 LT |
1328 | printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name); |
1329 | break ; | |
1330 | } | |
1331 | } | |
1332 | ||
1333 | /* Turn off interrupts, we will still get the indication though | |
1334 | * so we can trap it | |
1335 | */ | |
1336 | ||
1337 | writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ; | |
1338 | ||
1339 | xl_srb_cmd(dev,CLOSE_NIC) ; | |
1340 | ||
1341 | t=jiffies; | |
1342 | while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) { | |
1343 | schedule(); | |
b7aa6909 | 1344 | if (time_after(jiffies, t + 10 * HZ)) { |
1da177e4 LT |
1345 | printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name); |
1346 | break ; | |
1347 | } | |
1348 | } | |
1349 | /* Read the srb response from the adapter */ | |
1350 | ||
1351 | writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD); | |
1352 | if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) { | |
014e4668 | 1353 | printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response\n",dev->name); |
1da177e4 LT |
1354 | } else { |
1355 | writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1356 | if (readb(xl_mmio + MMIO_MACDATA)==0) { | |
014e4668 | 1357 | printk(KERN_INFO "%s: Adapter has been closed\n",dev->name); |
1da177e4 LT |
1358 | writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; |
1359 | ||
1360 | xl_freemem(dev) ; | |
1361 | free_irq(dev->irq,dev) ; | |
1362 | } else { | |
1363 | printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ; | |
1364 | } | |
1365 | } | |
1366 | ||
1367 | /* Reset the upload and download logic */ | |
1368 | ||
1369 | writew(UPRESET, xl_mmio + MMIO_COMMAND) ; | |
1370 | t=jiffies; | |
1371 | while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { | |
1372 | schedule(); | |
b7aa6909 | 1373 | if (time_after(jiffies, t + 10 * HZ)) { |
1da177e4 LT |
1374 | printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name); |
1375 | break ; | |
1376 | } | |
1377 | } | |
1378 | writew(DNRESET, xl_mmio + MMIO_COMMAND) ; | |
1379 | t=jiffies; | |
1380 | while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { | |
1381 | schedule(); | |
b7aa6909 | 1382 | if (time_after(jiffies, t + 10 * HZ)) { |
1da177e4 LT |
1383 | printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name); |
1384 | break ; | |
1385 | } | |
1386 | } | |
1387 | xl_hw_reset(dev) ; | |
1388 | return 0 ; | |
1389 | } | |
1390 | ||
1391 | static void xl_set_rx_mode(struct net_device *dev) | |
1392 | { | |
eda10531 | 1393 | struct xl_private *xl_priv = netdev_priv(dev); |
22bedad3 | 1394 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1395 | unsigned char dev_mc_address[4] ; |
1396 | u16 options ; | |
1da177e4 LT |
1397 | |
1398 | if (dev->flags & IFF_PROMISC) | |
1399 | options = 0x0004 ; | |
1400 | else | |
1401 | options = 0x0000 ; | |
1402 | ||
1403 | if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */ | |
1404 | xl_priv->xl_copy_all_options = options ; | |
1405 | xl_srb_cmd(dev, SET_RECEIVE_MODE) ; | |
1406 | return ; | |
1407 | } | |
1408 | ||
1409 | dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ; | |
1410 | ||
22bedad3 JP |
1411 | netdev_for_each_mc_addr(ha, dev) { |
1412 | dev_mc_address[0] |= ha->addr[2]; | |
1413 | dev_mc_address[1] |= ha->addr[3]; | |
1414 | dev_mc_address[2] |= ha->addr[4]; | |
1415 | dev_mc_address[3] |= ha->addr[5]; | |
1da177e4 LT |
1416 | } |
1417 | ||
1418 | if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */ | |
1419 | memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ; | |
1420 | xl_srb_cmd(dev, SET_FUNC_ADDRESS) ; | |
1421 | } | |
1422 | return ; | |
1423 | } | |
1424 | ||
1425 | ||
1426 | /* | |
1427 | * We issued an srb command and now we must read | |
1428 | * the response from the completed command. | |
1429 | */ | |
1430 | ||
1431 | static void xl_srb_bh(struct net_device *dev) | |
1432 | { | |
eda10531 | 1433 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
1434 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1435 | u8 srb_cmd, ret_code ; | |
1436 | int i ; | |
1437 | ||
1438 | writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1439 | srb_cmd = readb(xl_mmio + MMIO_MACDATA) ; | |
1440 | writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1441 | ret_code = readb(xl_mmio + MMIO_MACDATA) ; | |
1442 | ||
1443 | /* Ret_code is standard across all commands */ | |
1444 | ||
1445 | switch (ret_code) { | |
1446 | case 1: | |
1447 | printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ; | |
1448 | break ; | |
1449 | case 4: | |
014e4668 | 1450 | printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command\n",dev->name,srb_cmd); |
1da177e4 LT |
1451 | break ; |
1452 | ||
1453 | case 6: | |
014e4668 | 1454 | printk(KERN_INFO "%s: Command: %d - Options Invalid for command\n",dev->name,srb_cmd); |
1da177e4 LT |
1455 | break ; |
1456 | ||
1457 | case 0: /* Successful command execution */ | |
1458 | switch (srb_cmd) { | |
1459 | case READ_LOG: /* Returns 14 bytes of data from the NIC */ | |
1460 | if(xl_priv->xl_message_level) | |
1461 | printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ; | |
1462 | /* | |
1463 | * We still have to read the log even if message_level = 0 and we don't want | |
1464 | * to see it | |
1465 | */ | |
1466 | for (i=0;i<14;i++) { | |
1467 | writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1468 | if(xl_priv->xl_message_level) | |
1469 | printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ; | |
1470 | } | |
1471 | printk("\n") ; | |
1472 | break ; | |
1473 | case SET_FUNC_ADDRESS: | |
1474 | if(xl_priv->xl_message_level) | |
014e4668 | 1475 | printk(KERN_INFO "%s: Functional Address Set\n",dev->name); |
1da177e4 LT |
1476 | break ; |
1477 | case CLOSE_NIC: | |
1478 | if(xl_priv->xl_message_level) | |
014e4668 | 1479 | printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler\n",dev->name); |
1da177e4 LT |
1480 | break ; |
1481 | case SET_MULTICAST_MODE: | |
1482 | if(xl_priv->xl_message_level) | |
1483 | printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ; | |
1484 | break ; | |
1485 | case SET_RECEIVE_MODE: | |
1486 | if(xl_priv->xl_message_level) { | |
1487 | if (xl_priv->xl_copy_all_options == 0x0004) | |
014e4668 | 1488 | printk(KERN_INFO "%s: Entering promiscuous mode\n", dev->name); |
1da177e4 | 1489 | else |
014e4668 | 1490 | printk(KERN_INFO "%s: Entering normal receive mode\n",dev->name); |
1da177e4 LT |
1491 | } |
1492 | break ; | |
1493 | ||
1494 | } /* switch */ | |
1495 | break ; | |
1496 | } /* switch */ | |
1497 | return ; | |
1498 | } | |
1499 | ||
1da177e4 LT |
1500 | static int xl_set_mac_address (struct net_device *dev, void *addr) |
1501 | { | |
1502 | struct sockaddr *saddr = addr ; | |
eda10531 | 1503 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
1504 | |
1505 | if (netif_running(dev)) { | |
1506 | printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ; | |
1507 | return -EIO ; | |
1508 | } | |
1509 | ||
1510 | memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ; | |
1511 | ||
1512 | if (xl_priv->xl_message_level) { | |
1513 | printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0], | |
1514 | xl_priv->xl_laa[1], xl_priv->xl_laa[2], | |
1515 | xl_priv->xl_laa[3], xl_priv->xl_laa[4], | |
1516 | xl_priv->xl_laa[5]); | |
1517 | } | |
1518 | ||
1519 | return 0 ; | |
1520 | } | |
1521 | ||
1522 | static void xl_arb_cmd(struct net_device *dev) | |
1523 | { | |
eda10531 | 1524 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
1525 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1526 | u8 arb_cmd ; | |
1527 | u16 lan_status, lan_status_diff ; | |
1528 | ||
1529 | writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1530 | arb_cmd = readb(xl_mmio + MMIO_MACDATA) ; | |
1531 | ||
1532 | if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */ | |
1533 | writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1534 | ||
9914cad5 | 1535 | printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ; |
1da177e4 | 1536 | |
9914cad5 | 1537 | lan_status = swab16(readw(xl_mmio + MMIO_MACDATA)); |
1da177e4 LT |
1538 | |
1539 | /* Acknowledge interrupt, this tells nic we are done with the arb */ | |
1540 | writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; | |
1541 | ||
1542 | lan_status_diff = xl_priv->xl_lan_status ^ lan_status ; | |
1543 | ||
1544 | if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) { | |
1545 | if (lan_status_diff & LSC_LWF) | |
1546 | printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name); | |
1547 | if (lan_status_diff & LSC_ARW) | |
1548 | printk(KERN_WARNING "%s: Auto removal error\n",dev->name); | |
1549 | if (lan_status_diff & LSC_FPE) | |
1550 | printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name); | |
1551 | if (lan_status_diff & LSC_RR) | |
1552 | printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name); | |
1553 | ||
1554 | /* Adapter has been closed by the hardware */ | |
1555 | ||
1556 | netif_stop_queue(dev); | |
1557 | xl_freemem(dev) ; | |
1558 | free_irq(dev->irq,dev); | |
1559 | ||
014e4668 | 1560 | printk(KERN_WARNING "%s: Adapter has been closed\n", dev->name); |
1da177e4 LT |
1561 | } /* If serious error */ |
1562 | ||
1563 | if (xl_priv->xl_message_level) { | |
1564 | if (lan_status_diff & LSC_SIG_LOSS) | |
014e4668 | 1565 | printk(KERN_WARNING "%s: No receive signal detected\n", dev->name); |
1da177e4 | 1566 | if (lan_status_diff & LSC_HARD_ERR) |
014e4668 | 1567 | printk(KERN_INFO "%s: Beaconing\n",dev->name); |
1da177e4 | 1568 | if (lan_status_diff & LSC_SOFT_ERR) |
014e4668 | 1569 | printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame\n",dev->name); |
1da177e4 LT |
1570 | if (lan_status_diff & LSC_TRAN_BCN) |
1571 | printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name); | |
1572 | if (lan_status_diff & LSC_SS) | |
014e4668 | 1573 | printk(KERN_INFO "%s: Single Station on the ring\n", dev->name); |
1da177e4 LT |
1574 | if (lan_status_diff & LSC_RING_REC) |
1575 | printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name); | |
1576 | if (lan_status_diff & LSC_FDX_MODE) | |
1577 | printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name); | |
1578 | } | |
1579 | ||
1580 | if (lan_status_diff & LSC_CO) { | |
1581 | if (xl_priv->xl_message_level) | |
014e4668 | 1582 | printk(KERN_INFO "%s: Counter Overflow\n", dev->name); |
1da177e4 LT |
1583 | /* Issue READ.LOG command */ |
1584 | xl_srb_cmd(dev, READ_LOG) ; | |
1585 | } | |
1586 | ||
1587 | /* There is no command in the tech docs to issue the read_sr_counters */ | |
1588 | if (lan_status_diff & LSC_SR_CO) { | |
1589 | if (xl_priv->xl_message_level) | |
1590 | printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name); | |
1591 | } | |
1592 | ||
1593 | xl_priv->xl_lan_status = lan_status ; | |
1594 | ||
1595 | } /* Lan.change.status */ | |
1596 | else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */ | |
1597 | #if XL_DEBUG | |
014e4668 | 1598 | printk(KERN_INFO "Received.Data\n"); |
1da177e4 LT |
1599 | #endif |
1600 | writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
9914cad5 | 1601 | xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ; |
1da177e4 LT |
1602 | |
1603 | /* Now we are going to be really basic here and not do anything | |
1604 | * with the data at all. The tech docs do not give me enough | |
1605 | * information to calculate the buffers properly so we're | |
1606 | * just going to tell the nic that we've dealt with the frame | |
1607 | * anyway. | |
1608 | */ | |
1609 | ||
1da177e4 LT |
1610 | /* Acknowledge interrupt, this tells nic we are done with the arb */ |
1611 | writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; | |
1612 | ||
1613 | /* Is the ASB free ? */ | |
1614 | ||
1615 | xl_priv->asb_queued = 0 ; | |
1616 | writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1617 | if (readb(xl_mmio + MMIO_MACDATA) != 0xff) { | |
1618 | xl_priv->asb_queued = 1 ; | |
1619 | ||
1620 | xl_wait_misr_flags(dev) ; | |
1621 | ||
1622 | writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD); | |
1623 | writeb(0xff, xl_mmio + MMIO_MACDATA) ; | |
1624 | writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1625 | writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ; | |
1626 | return ; | |
1627 | /* Drop out and wait for the bottom half to be run */ | |
1628 | } | |
1629 | ||
1630 | xl_asb_cmd(dev) ; | |
1631 | ||
1632 | } else { | |
014e4668 | 1633 | printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x\n",dev->name,arb_cmd); |
1da177e4 LT |
1634 | } |
1635 | ||
1636 | /* Acknowledge the arb interrupt */ | |
1637 | ||
1638 | writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; | |
1639 | ||
1640 | return ; | |
1641 | } | |
1642 | ||
1643 | ||
1644 | /* | |
1645 | * There is only one asb command, but we can get called from different | |
1646 | * places. | |
1647 | */ | |
1648 | ||
1649 | static void xl_asb_cmd(struct net_device *dev) | |
1650 | { | |
eda10531 | 1651 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
1652 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1653 | ||
1654 | if (xl_priv->asb_queued == 1) | |
1655 | writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ; | |
1656 | ||
1657 | writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1658 | writeb(0x81, xl_mmio + MMIO_MACDATA) ; | |
1659 | ||
1660 | writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
9914cad5 | 1661 | writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ; |
1da177e4 LT |
1662 | |
1663 | xl_wait_misr_flags(dev) ; | |
1664 | ||
1665 | writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD); | |
1666 | writeb(0xff, xl_mmio + MMIO_MACDATA) ; | |
1667 | ||
1668 | writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1669 | writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ; | |
1670 | ||
1671 | xl_priv->asb_queued = 2 ; | |
1672 | ||
1673 | return ; | |
1674 | } | |
1675 | ||
1676 | /* | |
1677 | * This will only get called if there was an error | |
1678 | * from the asb cmd. | |
1679 | */ | |
1680 | static void xl_asb_bh(struct net_device *dev) | |
1681 | { | |
eda10531 | 1682 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
1683 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1684 | u8 ret_code ; | |
1685 | ||
1686 | writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1687 | ret_code = readb(xl_mmio + MMIO_MACDATA) ; | |
1688 | switch (ret_code) { | |
1689 | case 0x01: | |
014e4668 | 1690 | printk(KERN_INFO "%s: ASB Command, unrecognized command code\n",dev->name); |
1da177e4 LT |
1691 | break ; |
1692 | case 0x26: | |
014e4668 | 1693 | printk(KERN_INFO "%s: ASB Command, unexpected receive buffer\n", dev->name); |
1da177e4 LT |
1694 | break ; |
1695 | case 0x40: | |
014e4668 | 1696 | printk(KERN_INFO "%s: ASB Command, Invalid Station ID\n", dev->name); |
1da177e4 LT |
1697 | break ; |
1698 | } | |
1699 | xl_priv->asb_queued = 0 ; | |
1700 | writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ; | |
1701 | return ; | |
1702 | } | |
1703 | ||
1704 | /* | |
1705 | * Issue srb commands to the nic | |
1706 | */ | |
1707 | ||
1708 | static void xl_srb_cmd(struct net_device *dev, int srb_cmd) | |
1709 | { | |
eda10531 | 1710 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
1711 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1712 | ||
1713 | switch (srb_cmd) { | |
1714 | case READ_LOG: | |
1715 | writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1716 | writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ; | |
1717 | break; | |
1718 | ||
1719 | case CLOSE_NIC: | |
1720 | writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1721 | writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ; | |
1722 | break ; | |
1723 | ||
1724 | case SET_RECEIVE_MODE: | |
1725 | writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1726 | writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ; | |
1727 | writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1728 | writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ; | |
1729 | break ; | |
1730 | ||
1731 | case SET_FUNC_ADDRESS: | |
1732 | writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1733 | writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ; | |
1734 | writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1735 | writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ; | |
1736 | writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1737 | writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ; | |
1738 | writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1739 | writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ; | |
1740 | writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1741 | writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ; | |
1742 | break ; | |
1743 | } /* switch */ | |
1744 | ||
1745 | ||
1746 | xl_wait_misr_flags(dev) ; | |
1747 | ||
1748 | /* Write 0xff to the CSRB flag */ | |
1749 | writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1750 | writeb(0xFF, xl_mmio + MMIO_MACDATA) ; | |
1751 | /* Set csrb bit in MISR register to process command */ | |
1752 | writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1753 | writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ; | |
1754 | xl_priv->srb_queued = 1 ; | |
1755 | ||
1756 | return ; | |
1757 | } | |
1758 | ||
1759 | /* | |
1760 | * This is nasty, to use the MISR command you have to wait for 6 memory locations | |
1761 | * to be zero. This is the way the driver does on other OS'es so we should be ok with | |
1762 | * the empty loop. | |
1763 | */ | |
1764 | ||
1765 | static void xl_wait_misr_flags(struct net_device *dev) | |
1766 | { | |
eda10531 | 1767 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
1768 | u8 __iomem * xl_mmio = xl_priv->xl_mmio ; |
1769 | ||
1770 | int i ; | |
1771 | ||
1772 | writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1773 | if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */ | |
1774 | for (i=0; i<6; i++) { | |
1775 | writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1776 | while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */ | |
1777 | } | |
1778 | } | |
1779 | ||
1780 | writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ; | |
1781 | writeb(0x80, xl_mmio + MMIO_MACDATA) ; | |
1782 | ||
1783 | return ; | |
1784 | } | |
1785 | ||
1786 | /* | |
1787 | * Change mtu size, this should work the same as olympic | |
1788 | */ | |
1789 | ||
1790 | static int xl_change_mtu(struct net_device *dev, int mtu) | |
1791 | { | |
eda10531 | 1792 | struct xl_private *xl_priv = netdev_priv(dev); |
1da177e4 LT |
1793 | u16 max_mtu ; |
1794 | ||
1795 | if (xl_priv->xl_ring_speed == 4) | |
1796 | max_mtu = 4500 ; | |
1797 | else | |
1798 | max_mtu = 18000 ; | |
1799 | ||
1800 | if (mtu > max_mtu) | |
1801 | return -EINVAL ; | |
1802 | if (mtu < 100) | |
1803 | return -EINVAL ; | |
1804 | ||
1805 | dev->mtu = mtu ; | |
1806 | xl_priv->pkt_buf_sz = mtu + TR_HLEN ; | |
1807 | ||
1808 | return 0 ; | |
1809 | } | |
1810 | ||
1811 | static void __devexit xl_remove_one (struct pci_dev *pdev) | |
1812 | { | |
1813 | struct net_device *dev = pci_get_drvdata(pdev); | |
eda10531 | 1814 | struct xl_private *xl_priv=netdev_priv(dev); |
1da177e4 | 1815 | |
4b6ece97 | 1816 | release_firmware(xl_priv->fw); |
1da177e4 LT |
1817 | unregister_netdev(dev); |
1818 | iounmap(xl_priv->xl_mmio) ; | |
1819 | pci_release_regions(pdev) ; | |
1820 | pci_set_drvdata(pdev,NULL) ; | |
1821 | free_netdev(dev); | |
1822 | return ; | |
1823 | } | |
1824 | ||
1825 | static struct pci_driver xl_3c359_driver = { | |
1826 | .name = "3c359", | |
1827 | .id_table = xl_pci_tbl, | |
1828 | .probe = xl_probe, | |
1829 | .remove = __devexit_p(xl_remove_one), | |
1830 | }; | |
1831 | ||
1832 | static int __init xl_pci_init (void) | |
1833 | { | |
29917620 | 1834 | return pci_register_driver(&xl_3c359_driver); |
1da177e4 LT |
1835 | } |
1836 | ||
1837 | ||
1838 | static void __exit xl_pci_cleanup (void) | |
1839 | { | |
1840 | pci_unregister_driver (&xl_3c359_driver); | |
1841 | } | |
1842 | ||
1843 | module_init(xl_pci_init); | |
1844 | module_exit(xl_pci_cleanup); | |
1845 | ||
1846 | MODULE_LICENSE("GPL") ; |