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1da177e4 LT |
1 | /* |
2 | * madgemc.c: Driver for the Madge Smart 16/4 MC16 MCA token ring card. | |
3 | * | |
4 | * Written 2000 by Adam Fritzler | |
5 | * | |
6 | * This software may be used and distributed according to the terms | |
7 | * of the GNU General Public License, incorporated herein by reference. | |
8 | * | |
9 | * This driver module supports the following cards: | |
10 | * - Madge Smart 16/4 Ringnode MC16 | |
11 | * - Madge Smart 16/4 Ringnode MC32 (??) | |
12 | * | |
13 | * Maintainer(s): | |
726a6459 | 14 | * AF Adam Fritzler |
1da177e4 LT |
15 | * |
16 | * Modification History: | |
17 | * 16-Jan-00 AF Created | |
18 | * | |
19 | */ | |
20 | static const char version[] = "madgemc.c: v0.91 23/01/2000 by Adam Fritzler\n"; | |
21 | ||
22 | #include <linux/module.h> | |
84c3ea01 | 23 | #include <linux/mca.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
1da177e4 LT |
25 | #include <linux/kernel.h> |
26 | #include <linux/errno.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/netdevice.h> | |
29 | #include <linux/trdevice.h> | |
30 | ||
31 | #include <asm/system.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/irq.h> | |
34 | ||
35 | #include "tms380tr.h" | |
36 | #include "madgemc.h" /* Madge-specific constants */ | |
37 | ||
38 | #define MADGEMC_IO_EXTENT 32 | |
39 | #define MADGEMC_SIF_OFFSET 0x08 | |
40 | ||
84c3ea01 | 41 | struct card_info { |
1da177e4 LT |
42 | /* |
43 | * These are read from the BIA ROM. | |
44 | */ | |
45 | unsigned int manid; | |
46 | unsigned int cardtype; | |
47 | unsigned int cardrev; | |
48 | unsigned int ramsize; | |
49 | ||
50 | /* | |
51 | * These are read from the MCA POS registers. | |
52 | */ | |
53 | unsigned int burstmode:2; | |
54 | unsigned int fairness:1; /* 0 = Fair, 1 = Unfair */ | |
55 | unsigned int arblevel:4; | |
56 | unsigned int ringspeed:2; /* 0 = 4mb, 1 = 16, 2 = Auto/none */ | |
57 | unsigned int cabletype:1; /* 0 = RJ45, 1 = DB9 */ | |
1da177e4 | 58 | }; |
1da177e4 LT |
59 | |
60 | static int madgemc_open(struct net_device *dev); | |
61 | static int madgemc_close(struct net_device *dev); | |
62 | static int madgemc_chipset_init(struct net_device *dev); | |
84c3ea01 | 63 | static void madgemc_read_rom(struct net_device *dev, struct card_info *card); |
1da177e4 LT |
64 | static unsigned short madgemc_setnselout_pins(struct net_device *dev); |
65 | static void madgemc_setcabletype(struct net_device *dev, int type); | |
66 | ||
67 | static int madgemc_mcaproc(char *buf, int slot, void *d); | |
68 | ||
69 | static void madgemc_setregpage(struct net_device *dev, int page); | |
70 | static void madgemc_setsifsel(struct net_device *dev, int val); | |
71 | static void madgemc_setint(struct net_device *dev, int val); | |
72 | ||
7d12e780 | 73 | static irqreturn_t madgemc_interrupt(int irq, void *dev_id); |
1da177e4 LT |
74 | |
75 | /* | |
25985edc | 76 | * These work around paging, however they don't guarantee you're on the |
1da177e4 LT |
77 | * right page. |
78 | */ | |
79 | #define SIFREADB(reg) (inb(dev->base_addr + ((reg<0x8)?reg:reg-0x8))) | |
80 | #define SIFWRITEB(val, reg) (outb(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8))) | |
81 | #define SIFREADW(reg) (inw(dev->base_addr + ((reg<0x8)?reg:reg-0x8))) | |
82 | #define SIFWRITEW(val, reg) (outw(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8))) | |
83 | ||
84 | /* | |
85 | * Read a byte-length value from the register. | |
86 | */ | |
87 | static unsigned short madgemc_sifreadb(struct net_device *dev, unsigned short reg) | |
88 | { | |
89 | unsigned short ret; | |
90 | if (reg<0x8) | |
91 | ret = SIFREADB(reg); | |
92 | else { | |
93 | madgemc_setregpage(dev, 1); | |
94 | ret = SIFREADB(reg); | |
95 | madgemc_setregpage(dev, 0); | |
96 | } | |
97 | return ret; | |
98 | } | |
99 | ||
100 | /* | |
101 | * Write a byte-length value to a register. | |
102 | */ | |
103 | static void madgemc_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg) | |
104 | { | |
105 | if (reg<0x8) | |
106 | SIFWRITEB(val, reg); | |
107 | else { | |
108 | madgemc_setregpage(dev, 1); | |
109 | SIFWRITEB(val, reg); | |
110 | madgemc_setregpage(dev, 0); | |
111 | } | |
1da177e4 LT |
112 | } |
113 | ||
114 | /* | |
115 | * Read a word-length value from a register | |
116 | */ | |
117 | static unsigned short madgemc_sifreadw(struct net_device *dev, unsigned short reg) | |
118 | { | |
119 | unsigned short ret; | |
120 | if (reg<0x8) | |
121 | ret = SIFREADW(reg); | |
122 | else { | |
123 | madgemc_setregpage(dev, 1); | |
124 | ret = SIFREADW(reg); | |
125 | madgemc_setregpage(dev, 0); | |
126 | } | |
127 | return ret; | |
128 | } | |
129 | ||
130 | /* | |
131 | * Write a word-length value to a register. | |
132 | */ | |
133 | static void madgemc_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg) | |
134 | { | |
135 | if (reg<0x8) | |
136 | SIFWRITEW(val, reg); | |
137 | else { | |
138 | madgemc_setregpage(dev, 1); | |
139 | SIFWRITEW(val, reg); | |
140 | madgemc_setregpage(dev, 0); | |
141 | } | |
1da177e4 LT |
142 | } |
143 | ||
79f8ae3a | 144 | static struct net_device_ops madgemc_netdev_ops __read_mostly; |
1da177e4 | 145 | |
84c3ea01 | 146 | static int __devinit madgemc_probe(struct device *device) |
1da177e4 LT |
147 | { |
148 | static int versionprinted; | |
149 | struct net_device *dev; | |
150 | struct net_local *tp; | |
84c3ea01 JF |
151 | struct card_info *card; |
152 | struct mca_device *mdev = to_mca_device(device); | |
0795af57 | 153 | int ret = 0; |
84c3ea01 JF |
154 | |
155 | if (versionprinted++ == 0) | |
156 | printk("%s", version); | |
157 | ||
158 | if(mca_device_claimed(mdev)) | |
159 | return -EBUSY; | |
160 | mca_device_set_claim(mdev, 1); | |
161 | ||
162 | dev = alloc_trdev(sizeof(struct net_local)); | |
163 | if (!dev) { | |
164 | printk("madgemc: unable to allocate dev space\n"); | |
165 | mca_device_set_claim(mdev, 0); | |
166 | ret = -ENOMEM; | |
167 | goto getout; | |
168 | } | |
1da177e4 | 169 | |
79f8ae3a | 170 | dev->netdev_ops = &madgemc_netdev_ops; |
1da177e4 | 171 | |
84c3ea01 JF |
172 | card = kmalloc(sizeof(struct card_info), GFP_KERNEL); |
173 | if (card==NULL) { | |
84c3ea01 JF |
174 | ret = -ENOMEM; |
175 | goto getout1; | |
176 | } | |
177 | ||
178 | /* | |
179 | * Parse configuration information. This all comes | |
180 | * directly from the publicly available @002d.ADF. | |
181 | * Get it from Madge or your local ADF library. | |
182 | */ | |
183 | ||
184 | /* | |
185 | * Base address | |
186 | */ | |
187 | dev->base_addr = 0x0a20 + | |
188 | ((mdev->pos[2] & MC16_POS2_ADDR2)?0x0400:0) + | |
189 | ((mdev->pos[0] & MC16_POS0_ADDR1)?0x1000:0) + | |
190 | ((mdev->pos[3] & MC16_POS3_ADDR3)?0x2000:0); | |
191 | ||
192 | /* | |
193 | * Interrupt line | |
194 | */ | |
195 | switch(mdev->pos[0] >> 6) { /* upper two bits */ | |
1da177e4 LT |
196 | case 0x1: dev->irq = 3; break; |
197 | case 0x2: dev->irq = 9; break; /* IRQ 2 = IRQ 9 */ | |
198 | case 0x3: dev->irq = 10; break; | |
199 | default: dev->irq = 0; break; | |
84c3ea01 | 200 | } |
1da177e4 | 201 | |
84c3ea01 JF |
202 | if (dev->irq == 0) { |
203 | printk("%s: invalid IRQ\n", dev->name); | |
204 | ret = -EBUSY; | |
205 | goto getout2; | |
206 | } | |
1da177e4 | 207 | |
84c3ea01 JF |
208 | if (!request_region(dev->base_addr, MADGEMC_IO_EXTENT, |
209 | "madgemc")) { | |
210 | printk(KERN_INFO "madgemc: unable to setup Smart MC in slot %d because of I/O base conflict at 0x%04lx\n", mdev->slot, dev->base_addr); | |
1da177e4 | 211 | dev->base_addr += MADGEMC_SIF_OFFSET; |
84c3ea01 JF |
212 | ret = -EBUSY; |
213 | goto getout2; | |
214 | } | |
215 | dev->base_addr += MADGEMC_SIF_OFFSET; | |
216 | ||
217 | /* | |
218 | * Arbitration Level | |
219 | */ | |
220 | card->arblevel = ((mdev->pos[0] >> 1) & 0x7) + 8; | |
221 | ||
222 | /* | |
223 | * Burst mode and Fairness | |
224 | */ | |
225 | card->burstmode = ((mdev->pos[2] >> 6) & 0x3); | |
226 | card->fairness = ((mdev->pos[2] >> 4) & 0x1); | |
227 | ||
228 | /* | |
229 | * Ring Speed | |
230 | */ | |
231 | if ((mdev->pos[1] >> 2)&0x1) | |
232 | card->ringspeed = 2; /* not selected */ | |
233 | else if ((mdev->pos[2] >> 5) & 0x1) | |
234 | card->ringspeed = 1; /* 16Mb */ | |
235 | else | |
236 | card->ringspeed = 0; /* 4Mb */ | |
237 | ||
238 | /* | |
239 | * Cable type | |
240 | */ | |
241 | if ((mdev->pos[1] >> 6)&0x1) | |
242 | card->cabletype = 1; /* STP/DB9 */ | |
243 | else | |
244 | card->cabletype = 0; /* UTP/RJ-45 */ | |
245 | ||
246 | ||
247 | /* | |
248 | * ROM Info. This requires us to actually twiddle | |
249 | * bits on the card, so we must ensure above that | |
250 | * the base address is free of conflict (request_region above). | |
251 | */ | |
252 | madgemc_read_rom(dev, card); | |
1da177e4 | 253 | |
84c3ea01 JF |
254 | if (card->manid != 0x4d) { /* something went wrong */ |
255 | printk(KERN_INFO "%s: Madge MC ROM read failed (unknown manufacturer ID %02x)\n", dev->name, card->manid); | |
256 | goto getout3; | |
257 | } | |
1da177e4 | 258 | |
84c3ea01 JF |
259 | if ((card->cardtype != 0x08) && (card->cardtype != 0x0d)) { |
260 | printk(KERN_INFO "%s: Madge MC ROM read failed (unknown card ID %02x)\n", dev->name, card->cardtype); | |
261 | ret = -EIO; | |
262 | goto getout3; | |
263 | } | |
1da177e4 | 264 | |
84c3ea01 JF |
265 | /* All cards except Rev 0 and 1 MC16's have 256kb of RAM */ |
266 | if ((card->cardtype == 0x08) && (card->cardrev <= 0x01)) | |
267 | card->ramsize = 128; | |
268 | else | |
269 | card->ramsize = 256; | |
270 | ||
271 | printk("%s: %s Rev %d at 0x%04lx IRQ %d\n", | |
272 | dev->name, | |
273 | (card->cardtype == 0x08)?MADGEMC16_CARDNAME: | |
274 | MADGEMC32_CARDNAME, card->cardrev, | |
275 | dev->base_addr, dev->irq); | |
276 | ||
277 | if (card->cardtype == 0x0d) | |
278 | printk("%s: Warning: MC32 support is experimental and highly untested\n", dev->name); | |
279 | ||
280 | if (card->ringspeed==2) { /* Unknown */ | |
281 | printk("%s: Warning: Ring speed not set in POS -- Please run the reference disk and set it!\n", dev->name); | |
282 | card->ringspeed = 1; /* default to 16mb */ | |
283 | } | |
1da177e4 | 284 | |
84c3ea01 | 285 | printk("%s: RAM Size: %dKB\n", dev->name, card->ramsize); |
1da177e4 | 286 | |
84c3ea01 JF |
287 | printk("%s: Ring Speed: %dMb/sec on %s\n", dev->name, |
288 | (card->ringspeed)?16:4, | |
289 | card->cabletype?"STP/DB9":"UTP/RJ-45"); | |
290 | printk("%s: Arbitration Level: %d\n", dev->name, | |
291 | card->arblevel); | |
1da177e4 | 292 | |
84c3ea01 JF |
293 | printk("%s: Burst Mode: ", dev->name); |
294 | switch(card->burstmode) { | |
1da177e4 LT |
295 | case 0: printk("Cycle steal"); break; |
296 | case 1: printk("Limited burst"); break; | |
297 | case 2: printk("Delayed release"); break; | |
298 | case 3: printk("Immediate release"); break; | |
84c3ea01 JF |
299 | } |
300 | printk(" (%s)\n", (card->fairness)?"Unfair":"Fair"); | |
1da177e4 | 301 | |
1da177e4 | 302 | |
84c3ea01 JF |
303 | /* |
304 | * Enable SIF before we assign the interrupt handler, | |
305 | * just in case we get spurious interrupts that need | |
306 | * handling. | |
307 | */ | |
308 | outb(0, dev->base_addr + MC_CONTROL_REG0); /* sanity */ | |
309 | madgemc_setsifsel(dev, 1); | |
1fb9df5d | 310 | if (request_irq(dev->irq, madgemc_interrupt, IRQF_SHARED, |
84c3ea01 JF |
311 | "madgemc", dev)) { |
312 | ret = -EBUSY; | |
313 | goto getout3; | |
1da177e4 LT |
314 | } |
315 | ||
84c3ea01 JF |
316 | madgemc_chipset_init(dev); /* enables interrupts! */ |
317 | madgemc_setcabletype(dev, card->cabletype); | |
318 | ||
319 | /* Setup MCA structures */ | |
320 | mca_device_set_name(mdev, (card->cardtype == 0x08)?MADGEMC16_CARDNAME:MADGEMC32_CARDNAME); | |
321 | mca_set_adapter_procfn(mdev->slot, madgemc_mcaproc, dev); | |
322 | ||
e174961c JB |
323 | printk("%s: Ring Station Address: %pM\n", |
324 | dev->name, dev->dev_addr); | |
84c3ea01 JF |
325 | |
326 | if (tmsdev_init(dev, device)) { | |
327 | printk("%s: unable to get memory for dev->priv.\n", | |
328 | dev->name); | |
329 | ret = -ENOMEM; | |
330 | goto getout4; | |
331 | } | |
332 | tp = netdev_priv(dev); | |
333 | ||
334 | /* | |
335 | * The MC16 is physically a 32bit card. However, Madge | |
336 | * insists on calling it 16bit, so I'll assume here that | |
337 | * they know what they're talking about. Cut off DMA | |
338 | * at 16mb. | |
339 | */ | |
340 | tp->setnselout = madgemc_setnselout_pins; | |
341 | tp->sifwriteb = madgemc_sifwriteb; | |
342 | tp->sifreadb = madgemc_sifreadb; | |
343 | tp->sifwritew = madgemc_sifwritew; | |
344 | tp->sifreadw = madgemc_sifreadw; | |
345 | tp->DataRate = (card->ringspeed)?SPEED_16:SPEED_4; | |
346 | ||
347 | memcpy(tp->ProductID, "Madge MCA 16/4 ", PROD_ID_SIZE + 1); | |
348 | ||
84c3ea01 JF |
349 | tp->tmspriv = card; |
350 | dev_set_drvdata(device, dev); | |
351 | ||
352 | if (register_netdev(dev) == 0) | |
1da177e4 | 353 | return 0; |
84c3ea01 JF |
354 | |
355 | dev_set_drvdata(device, NULL); | |
356 | ret = -ENOMEM; | |
357 | getout4: | |
358 | free_irq(dev->irq, dev); | |
359 | getout3: | |
360 | release_region(dev->base_addr-MADGEMC_SIF_OFFSET, | |
361 | MADGEMC_IO_EXTENT); | |
362 | getout2: | |
363 | kfree(card); | |
364 | getout1: | |
365 | free_netdev(dev); | |
366 | getout: | |
367 | mca_device_set_claim(mdev, 0); | |
368 | return ret; | |
1da177e4 LT |
369 | } |
370 | ||
371 | /* | |
372 | * Handle interrupts generated by the card | |
373 | * | |
374 | * The MicroChannel Madge cards need slightly more handling | |
375 | * after an interrupt than other TMS380 cards do. | |
376 | * | |
377 | * First we must make sure it was this card that generated the | |
378 | * interrupt (since interrupt sharing is allowed). Then, | |
379 | * because we're using level-triggered interrupts (as is | |
380 | * standard on MCA), we must toggle the interrupt line | |
381 | * on the card in order to claim and acknowledge the interrupt. | |
382 | * Once that is done, the interrupt should be handlable in | |
383 | * the normal tms380tr_interrupt() routine. | |
384 | * | |
385 | * There's two ways we can check to see if the interrupt is ours, | |
386 | * both with their own disadvantages... | |
387 | * | |
388 | * 1) Read in the SIFSTS register from the TMS controller. This | |
25985edc | 389 | * is guaranteed to be accurate, however, there's a fairly |
1da177e4 LT |
390 | * large performance penalty for doing so: the Madge chips |
391 | * must request the register from the Eagle, the Eagle must | |
392 | * read them from its internal bus, and then take the route | |
393 | * back out again, for a 16bit read. | |
394 | * | |
395 | * 2) Use the MC_CONTROL_REG0_SINTR bit from the Madge ASICs. | |
396 | * The major disadvantage here is that the accuracy of the | |
397 | * bit is in question. However, it cuts out the extra read | |
398 | * cycles it takes to read the Eagle's SIF, as its only an | |
399 | * 8bit read, and theoretically the Madge bit is directly | |
400 | * connected to the interrupt latch coming out of the Eagle | |
401 | * hardware (that statement is not verified). | |
402 | * | |
403 | * I can't determine which of these methods has the best win. For now, | |
404 | * we make a compromise. Use the Madge way for the first interrupt, | |
405 | * which should be the fast-path, and then once we hit the first | |
406 | * interrupt, keep on trying using the SIF method until we've | |
407 | * exhausted all contiguous interrupts. | |
408 | * | |
409 | */ | |
7d12e780 | 410 | static irqreturn_t madgemc_interrupt(int irq, void *dev_id) |
1da177e4 LT |
411 | { |
412 | int pending,reg1; | |
413 | struct net_device *dev; | |
414 | ||
415 | if (!dev_id) { | |
416 | printk("madgemc_interrupt: was not passed a dev_id!\n"); | |
417 | return IRQ_NONE; | |
418 | } | |
419 | ||
43d620c8 | 420 | dev = dev_id; |
1da177e4 LT |
421 | |
422 | /* Make sure its really us. -- the Madge way */ | |
423 | pending = inb(dev->base_addr + MC_CONTROL_REG0); | |
424 | if (!(pending & MC_CONTROL_REG0_SINTR)) | |
425 | return IRQ_NONE; /* not our interrupt */ | |
426 | ||
427 | /* | |
428 | * Since we're level-triggered, we may miss the rising edge | |
429 | * of the next interrupt while we're off handling this one, | |
430 | * so keep checking until the SIF verifies that it has nothing | |
431 | * left for us to do. | |
432 | */ | |
433 | pending = STS_SYSTEM_IRQ; | |
434 | do { | |
435 | if (pending & STS_SYSTEM_IRQ) { | |
436 | ||
437 | /* Toggle the interrupt to reset the latch on card */ | |
438 | reg1 = inb(dev->base_addr + MC_CONTROL_REG1); | |
439 | outb(reg1 ^ MC_CONTROL_REG1_SINTEN, | |
440 | dev->base_addr + MC_CONTROL_REG1); | |
441 | outb(reg1, dev->base_addr + MC_CONTROL_REG1); | |
442 | ||
443 | /* Continue handling as normal */ | |
7d12e780 | 444 | tms380tr_interrupt(irq, dev_id); |
1da177e4 LT |
445 | |
446 | pending = SIFREADW(SIFSTS); /* restart - the SIF way */ | |
447 | ||
448 | } else | |
449 | return IRQ_HANDLED; | |
450 | } while (1); | |
451 | ||
452 | return IRQ_HANDLED; /* not reachable */ | |
453 | } | |
454 | ||
455 | /* | |
25985edc | 456 | * Set the card to the preferred ring speed. |
1da177e4 LT |
457 | * |
458 | * Unlike newer cards, the MC16/32 have their speed selection | |
459 | * circuit connected to the Madge ASICs and not to the TMS380 | |
460 | * NSELOUT pins. Set the ASIC bits correctly here, and return | |
461 | * zero to leave the TMS NSELOUT bits unaffected. | |
462 | * | |
463 | */ | |
27cd6ae5 | 464 | static unsigned short madgemc_setnselout_pins(struct net_device *dev) |
1da177e4 LT |
465 | { |
466 | unsigned char reg1; | |
467 | struct net_local *tp = netdev_priv(dev); | |
468 | ||
469 | reg1 = inb(dev->base_addr + MC_CONTROL_REG1); | |
470 | ||
471 | if(tp->DataRate == SPEED_16) | |
472 | reg1 |= MC_CONTROL_REG1_SPEED_SEL; /* add for 16mb */ | |
473 | else if (reg1 & MC_CONTROL_REG1_SPEED_SEL) | |
474 | reg1 ^= MC_CONTROL_REG1_SPEED_SEL; /* remove for 4mb */ | |
475 | outb(reg1, dev->base_addr + MC_CONTROL_REG1); | |
476 | ||
477 | return 0; /* no change */ | |
478 | } | |
479 | ||
480 | /* | |
481 | * Set the register page. This equates to the SRSX line | |
482 | * on the TMS380Cx6. | |
483 | * | |
484 | * Register selection is normally done via three contiguous | |
485 | * bits. However, some boards (such as the MC16/32) use only | |
486 | * two bits, plus a separate bit in the glue chip. This | |
487 | * sets the SRSX bit (the top bit). See page 4-17 in the | |
488 | * Yellow Book for which registers are affected. | |
489 | * | |
490 | */ | |
491 | static void madgemc_setregpage(struct net_device *dev, int page) | |
492 | { | |
493 | static int reg1; | |
494 | ||
495 | reg1 = inb(dev->base_addr + MC_CONTROL_REG1); | |
496 | if ((page == 0) && (reg1 & MC_CONTROL_REG1_SRSX)) { | |
497 | outb(reg1 ^ MC_CONTROL_REG1_SRSX, | |
498 | dev->base_addr + MC_CONTROL_REG1); | |
499 | } | |
500 | else if (page == 1) { | |
501 | outb(reg1 | MC_CONTROL_REG1_SRSX, | |
502 | dev->base_addr + MC_CONTROL_REG1); | |
503 | } | |
504 | reg1 = inb(dev->base_addr + MC_CONTROL_REG1); | |
1da177e4 LT |
505 | } |
506 | ||
507 | /* | |
508 | * The SIF registers are not mapped into register space by default | |
509 | * Set this to 1 to map them, 0 to map the BIA ROM. | |
510 | * | |
511 | */ | |
512 | static void madgemc_setsifsel(struct net_device *dev, int val) | |
513 | { | |
514 | unsigned int reg0; | |
515 | ||
516 | reg0 = inb(dev->base_addr + MC_CONTROL_REG0); | |
517 | if ((val == 0) && (reg0 & MC_CONTROL_REG0_SIFSEL)) { | |
518 | outb(reg0 ^ MC_CONTROL_REG0_SIFSEL, | |
519 | dev->base_addr + MC_CONTROL_REG0); | |
520 | } else if (val == 1) { | |
521 | outb(reg0 | MC_CONTROL_REG0_SIFSEL, | |
522 | dev->base_addr + MC_CONTROL_REG0); | |
523 | } | |
524 | reg0 = inb(dev->base_addr + MC_CONTROL_REG0); | |
1da177e4 LT |
525 | } |
526 | ||
527 | /* | |
528 | * Enable SIF interrupts | |
529 | * | |
530 | * This does not enable interrupts in the SIF, but rather | |
531 | * enables SIF interrupts to be passed onto the host. | |
532 | * | |
533 | */ | |
534 | static void madgemc_setint(struct net_device *dev, int val) | |
535 | { | |
536 | unsigned int reg1; | |
537 | ||
538 | reg1 = inb(dev->base_addr + MC_CONTROL_REG1); | |
539 | if ((val == 0) && (reg1 & MC_CONTROL_REG1_SINTEN)) { | |
540 | outb(reg1 ^ MC_CONTROL_REG1_SINTEN, | |
541 | dev->base_addr + MC_CONTROL_REG1); | |
542 | } else if (val == 1) { | |
543 | outb(reg1 | MC_CONTROL_REG1_SINTEN, | |
544 | dev->base_addr + MC_CONTROL_REG1); | |
545 | } | |
1da177e4 LT |
546 | } |
547 | ||
548 | /* | |
549 | * Cable type is set via control register 7. Bit zero high | |
550 | * for UTP, low for STP. | |
551 | */ | |
552 | static void madgemc_setcabletype(struct net_device *dev, int type) | |
553 | { | |
554 | outb((type==0)?MC_CONTROL_REG7_CABLEUTP:MC_CONTROL_REG7_CABLESTP, | |
555 | dev->base_addr + MC_CONTROL_REG7); | |
556 | } | |
557 | ||
558 | /* | |
559 | * Enable the functions of the Madge chipset needed for | |
560 | * full working order. | |
561 | */ | |
562 | static int madgemc_chipset_init(struct net_device *dev) | |
563 | { | |
564 | outb(0, dev->base_addr + MC_CONTROL_REG1); /* pull SRESET low */ | |
565 | tms380tr_wait(100); /* wait for card to reset */ | |
566 | ||
567 | /* bring back into normal operating mode */ | |
568 | outb(MC_CONTROL_REG1_NSRESET, dev->base_addr + MC_CONTROL_REG1); | |
569 | ||
570 | /* map SIF registers */ | |
571 | madgemc_setsifsel(dev, 1); | |
572 | ||
573 | /* enable SIF interrupts */ | |
574 | madgemc_setint(dev, 1); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | /* | |
580 | * Disable the board, and put back into power-up state. | |
581 | */ | |
de70b4c8 | 582 | static void madgemc_chipset_close(struct net_device *dev) |
1da177e4 LT |
583 | { |
584 | /* disable interrupts */ | |
585 | madgemc_setint(dev, 0); | |
586 | /* unmap SIF registers */ | |
587 | madgemc_setsifsel(dev, 0); | |
1da177e4 LT |
588 | } |
589 | ||
590 | /* | |
591 | * Read the card type (MC16 or MC32) from the card. | |
592 | * | |
593 | * The configuration registers are stored in two separate | |
594 | * pages. Pages are flipped by clearing bit 3 of CONTROL_REG0 (PAGE) | |
595 | * for page zero, or setting bit 3 for page one. | |
596 | * | |
597 | * Page zero contains the following data: | |
598 | * Byte 0: Manufacturer ID (0x4D -- ASCII "M") | |
599 | * Byte 1: Card type: | |
600 | * 0x08 for MC16 | |
601 | * 0x0D for MC32 | |
602 | * Byte 2: Card revision | |
603 | * Byte 3: Mirror of POS config register 0 | |
604 | * Byte 4: Mirror of POS 1 | |
605 | * Byte 5: Mirror of POS 2 | |
606 | * | |
607 | * Page one contains the following data: | |
608 | * Byte 0: Unused | |
609 | * Byte 1-6: BIA, MSB to LSB. | |
610 | * | |
611 | * Note that to read the BIA, we must unmap the SIF registers | |
612 | * by clearing bit 2 of CONTROL_REG0 (SIFSEL), as the data | |
613 | * will reside in the same logical location. For this reason, | |
614 | * _never_ read the BIA while the Eagle processor is running! | |
615 | * The SIF will be completely inaccessible until the BIA operation | |
616 | * is complete. | |
617 | * | |
618 | */ | |
84c3ea01 | 619 | static void madgemc_read_rom(struct net_device *dev, struct card_info *card) |
1da177e4 LT |
620 | { |
621 | unsigned long ioaddr; | |
622 | unsigned char reg0, reg1, tmpreg0, i; | |
623 | ||
84c3ea01 | 624 | ioaddr = dev->base_addr; |
1da177e4 LT |
625 | |
626 | reg0 = inb(ioaddr + MC_CONTROL_REG0); | |
627 | reg1 = inb(ioaddr + MC_CONTROL_REG1); | |
628 | ||
629 | /* Switch to page zero and unmap SIF */ | |
630 | tmpreg0 = reg0 & ~(MC_CONTROL_REG0_PAGE + MC_CONTROL_REG0_SIFSEL); | |
631 | outb(tmpreg0, ioaddr + MC_CONTROL_REG0); | |
632 | ||
633 | card->manid = inb(ioaddr + MC_ROM_MANUFACTURERID); | |
634 | card->cardtype = inb(ioaddr + MC_ROM_ADAPTERID); | |
635 | card->cardrev = inb(ioaddr + MC_ROM_REVISION); | |
636 | ||
637 | /* Switch to rom page one */ | |
638 | outb(tmpreg0 | MC_CONTROL_REG0_PAGE, ioaddr + MC_CONTROL_REG0); | |
639 | ||
640 | /* Read BIA */ | |
84c3ea01 | 641 | dev->addr_len = 6; |
1da177e4 | 642 | for (i = 0; i < 6; i++) |
84c3ea01 | 643 | dev->dev_addr[i] = inb(ioaddr + MC_ROM_BIA_START + i); |
1da177e4 LT |
644 | |
645 | /* Restore original register values */ | |
646 | outb(reg0, ioaddr + MC_CONTROL_REG0); | |
647 | outb(reg1, ioaddr + MC_CONTROL_REG1); | |
1da177e4 LT |
648 | } |
649 | ||
650 | static int madgemc_open(struct net_device *dev) | |
651 | { | |
652 | /* | |
653 | * Go ahead and reinitialize the chipset again, just to | |
654 | * make sure we didn't get left in a bad state. | |
655 | */ | |
656 | madgemc_chipset_init(dev); | |
657 | tms380tr_open(dev); | |
658 | return 0; | |
659 | } | |
660 | ||
661 | static int madgemc_close(struct net_device *dev) | |
662 | { | |
663 | tms380tr_close(dev); | |
664 | madgemc_chipset_close(dev); | |
665 | return 0; | |
666 | } | |
667 | ||
668 | /* | |
669 | * Give some details available from /proc/mca/slotX | |
670 | */ | |
671 | static int madgemc_mcaproc(char *buf, int slot, void *d) | |
672 | { | |
673 | struct net_device *dev = (struct net_device *)d; | |
eda10531 | 674 | struct net_local *tp = netdev_priv(dev); |
84c3ea01 | 675 | struct card_info *curcard = tp->tmspriv; |
1da177e4 LT |
676 | int len = 0; |
677 | ||
1da177e4 LT |
678 | len += sprintf(buf+len, "-------\n"); |
679 | if (curcard) { | |
1da177e4 LT |
680 | len += sprintf(buf+len, "Card Revision: %d\n", curcard->cardrev); |
681 | len += sprintf(buf+len, "RAM Size: %dkb\n", curcard->ramsize); | |
682 | len += sprintf(buf+len, "Cable type: %s\n", (curcard->cabletype)?"STP/DB9":"UTP/RJ-45"); | |
683 | len += sprintf(buf+len, "Configured ring speed: %dMb/sec\n", (curcard->ringspeed)?16:4); | |
684 | len += sprintf(buf+len, "Running ring speed: %dMb/sec\n", (tp->DataRate==SPEED_16)?16:4); | |
685 | len += sprintf(buf+len, "Device: %s\n", dev->name); | |
686 | len += sprintf(buf+len, "IO Port: 0x%04lx\n", dev->base_addr); | |
687 | len += sprintf(buf+len, "IRQ: %d\n", dev->irq); | |
688 | len += sprintf(buf+len, "Arbitration Level: %d\n", curcard->arblevel); | |
689 | len += sprintf(buf+len, "Burst Mode: "); | |
690 | switch(curcard->burstmode) { | |
691 | case 0: len += sprintf(buf+len, "Cycle steal"); break; | |
692 | case 1: len += sprintf(buf+len, "Limited burst"); break; | |
693 | case 2: len += sprintf(buf+len, "Delayed release"); break; | |
694 | case 3: len += sprintf(buf+len, "Immediate release"); break; | |
695 | } | |
696 | len += sprintf(buf+len, " (%s)\n", (curcard->fairness)?"Unfair":"Fair"); | |
697 | ||
e174961c JB |
698 | len += sprintf(buf+len, "Ring Station Address: %pM\n", |
699 | dev->dev_addr); | |
1da177e4 LT |
700 | } else |
701 | len += sprintf(buf+len, "Card not configured\n"); | |
702 | ||
703 | return len; | |
704 | } | |
705 | ||
84c3ea01 | 706 | static int __devexit madgemc_remove(struct device *device) |
1da177e4 | 707 | { |
84c3ea01 JF |
708 | struct net_device *dev = dev_get_drvdata(device); |
709 | struct net_local *tp; | |
710 | struct card_info *card; | |
711 | ||
5d9428de | 712 | BUG_ON(!dev); |
84c3ea01 | 713 | |
eda10531 | 714 | tp = netdev_priv(dev); |
84c3ea01 JF |
715 | card = tp->tmspriv; |
716 | kfree(card); | |
717 | tp->tmspriv = NULL; | |
718 | ||
719 | unregister_netdev(dev); | |
720 | release_region(dev->base_addr-MADGEMC_SIF_OFFSET, MADGEMC_IO_EXTENT); | |
721 | free_irq(dev->irq, dev); | |
722 | tmsdev_term(dev); | |
723 | free_netdev(dev); | |
724 | dev_set_drvdata(device, NULL); | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
948252cb | 729 | static short madgemc_adapter_ids[] __initdata = { |
84c3ea01 JF |
730 | 0x002d, |
731 | 0x0000 | |
732 | }; | |
733 | ||
734 | static struct mca_driver madgemc_driver = { | |
735 | .id_table = madgemc_adapter_ids, | |
736 | .driver = { | |
737 | .name = "madgemc", | |
738 | .bus = &mca_bus_type, | |
739 | .probe = madgemc_probe, | |
740 | .remove = __devexit_p(madgemc_remove), | |
741 | }, | |
742 | }; | |
743 | ||
744 | static int __init madgemc_init (void) | |
745 | { | |
79f8ae3a SH |
746 | madgemc_netdev_ops = tms380tr_netdev_ops; |
747 | madgemc_netdev_ops.ndo_open = madgemc_open; | |
748 | madgemc_netdev_ops.ndo_stop = madgemc_close; | |
749 | ||
84c3ea01 JF |
750 | return mca_register_driver (&madgemc_driver); |
751 | } | |
752 | ||
753 | static void __exit madgemc_exit (void) | |
754 | { | |
755 | mca_unregister_driver (&madgemc_driver); | |
1da177e4 LT |
756 | } |
757 | ||
84c3ea01 | 758 | module_init(madgemc_init); |
1da177e4 LT |
759 | module_exit(madgemc_exit); |
760 | ||
761 | MODULE_LICENSE("GPL"); | |
762 |