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[mirror_ubuntu-artful-kernel.git] / drivers / net / tulip / tulip_core.c
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1da177e4
LT		 1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */
2
3/*
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
1da177e4
LT		 17
18#define DRV_NAME "tulip"
19#ifdef CONFIG_TULIP_NAPI
d5b20697 20#define DRV_VERSION "1.1.14-NAPI" /* Keep at least for test */
1da177e4 21#else
d5b20697 22#define DRV_VERSION "1.1.14"
1da177e4
LT		 23#endif
24#define DRV_RELDATE "May 11, 2002"
25
26
27#include <linux/module.h>
28#include <linux/pci.h>
29#include "tulip.h"
30#include <linux/init.h>
31#include <linux/etherdevice.h>
32#include <linux/delay.h>
33#include <linux/mii.h>
34#include <linux/ethtool.h>
35#include <linux/crc32.h>
36#include <asm/unaligned.h>
37#include <asm/uaccess.h>
38
39#ifdef __sparc__
40#include <asm/pbm.h>
41#endif
42
43static char version[] __devinitdata =
44 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
45
46
47/* A few user-configurable values. */
48
49/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
50static unsigned int max_interrupt_work = 25;
51
52#define MAX_UNITS 8
53/* Used to pass the full-duplex flag, etc. */
54static int full_duplex[MAX_UNITS];
55static int options[MAX_UNITS];
56static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
57
58/* The possible media types that can be set in options[] are: */
59const char * const medianame[32] = {
60 "10baseT", "10base2", "AUI", "100baseTx",
61 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
62 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
63 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
64 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
65 "","","","", "","","","", "","","","Transceiver reset",
66};
67
68/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
69#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
70 || defined(__sparc_) || defined(__ia64__) \
71 || defined(__sh__) || defined(__mips__)
72static int rx_copybreak = 1518;
73#else
74static int rx_copybreak = 100;
75#endif
76
77/*
78 Set the bus performance register.
79 Typical: Set 16 longword cache alignment, no burst limit.
80 Cache alignment bits 15:14 Burst length 13:8
81 0000 No alignment 0x00000000 unlimited 0800 8 longwords
82 4000 8 longwords 0100 1 longword 1000 16 longwords
83 8000 16 longwords 0200 2 longwords 2000 32 longwords
84 C000 32 longwords 0400 4 longwords
85 Warning: many older 486 systems are broken and require setting 0x00A04800
86 8 longword cache alignment, 8 longword burst.
87 ToDo: Non-Intel setting could be better.
88*/
89
90#if defined(__alpha__) || defined(__ia64__)
91static int csr0 = 0x01A00000 | 0xE000;
92#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
93static int csr0 = 0x01A00000 | 0x8000;
94#elif defined(__sparc__) || defined(__hppa__)
95/* The UltraSparc PCI controllers will disconnect at every 64-byte
96 * crossing anyways so it makes no sense to tell Tulip to burst
97 * any more than that.
98 */
99static int csr0 = 0x01A00000 | 0x9000;
100#elif defined(__arm__) || defined(__sh__)
101static int csr0 = 0x01A00000 | 0x4800;
102#elif defined(__mips__)
103static int csr0 = 0x00200000 | 0x4000;
104#else
105#warning Processor architecture undefined!
106static int csr0 = 0x00A00000 | 0x4800;
107#endif
108
109/* Operational parameters that usually are not changed. */
110/* Time in jiffies before concluding the transmitter is hung. */
111#define TX_TIMEOUT (4*HZ)
112
113
114MODULE_AUTHOR("The Linux Kernel Team");
115MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
116MODULE_LICENSE("GPL");
117MODULE_VERSION(DRV_VERSION);
118module_param(tulip_debug, int, 0);
119module_param(max_interrupt_work, int, 0);
120module_param(rx_copybreak, int, 0);
121module_param(csr0, int, 0);
122module_param_array(options, int, NULL, 0);
123module_param_array(full_duplex, int, NULL, 0);
124
125#define PFX DRV_NAME ": "
126
127#ifdef TULIP_DEBUG
128int tulip_debug = TULIP_DEBUG;
129#else
130int tulip_debug = 1;
131#endif
132
133
134
135/*
136 * This table use during operation for capabilities and media timer.
137 *
138 * It is indexed via the values in 'enum chips'
139 */
140
141struct tulip_chip_table tulip_tbl[] = {
142 { }, /* placeholder for array, slot unused currently */
143 { }, /* placeholder for array, slot unused currently */
144
145 /* DC21140 */
146 { "Digital DS21140 Tulip", 128, 0x0001ebef,
147 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer },
148
149 /* DC21142, DC21143 */
150 { "Digital DS21143 Tulip", 128, 0x0801fbff,
151 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
152 | HAS_INTR_MITIGATION | HAS_PCI_MWI, t21142_timer },
153
154 /* LC82C168 */
155 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
156 HAS_MII | HAS_PNICNWAY, pnic_timer },
157
158 /* MX98713 */
159 { "Macronix 98713 PMAC", 128, 0x0001ebef,
160 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
161
162 /* MX98715 */
163 { "Macronix 98715 PMAC", 256, 0x0001ebef,
164 HAS_MEDIA_TABLE, mxic_timer },
165
166 /* MX98725 */
167 { "Macronix 98725 PMAC", 256, 0x0001ebef,
168 HAS_MEDIA_TABLE, mxic_timer },
169
170 /* AX88140 */
171 { "ASIX AX88140", 128, 0x0001fbff,
172 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
173 | IS_ASIX, tulip_timer },
174
175 /* PNIC2 */
176 { "Lite-On PNIC-II", 256, 0x0801fbff,
177 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer },
178
179 /* COMET */
180 { "ADMtek Comet", 256, 0x0001abef,
181 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer },
182
183 /* COMPEX9881 */
184 { "Compex 9881 PMAC", 128, 0x0001ebef,
185 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
186
187 /* I21145 */
188 { "Intel DS21145 Tulip", 128, 0x0801fbff,
189 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
190 | HAS_NWAY | HAS_PCI_MWI, t21142_timer },
191
192 /* DM910X */
193 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
194 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
195 tulip_timer },
196
197 /* RS7112 */
198 { "Conexant LANfinity", 256, 0x0001ebef,
199 HAS_MII | HAS_ACPI, tulip_timer },
200
1da177e4
LT		 201};
202
203
204static struct pci_device_id tulip_pci_tbl[] = {
205 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
206 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
207 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
208 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
209 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
210/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
211 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
212 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
213 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
214 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
215 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
216 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
217 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
218 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
219 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
220 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
221 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
224 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
225 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
226 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
227 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
229 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
232 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
233 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
234 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
235 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
236 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
237 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4 238 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
9b25978e 239 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
1a449358 240 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4
LT		 241 { } /* terminate list */
242};
243MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
244
245
246/* A full-duplex map for media types. */
247const char tulip_media_cap[32] =
248{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
249
250static void tulip_tx_timeout(struct net_device *dev);
251static void tulip_init_ring(struct net_device *dev);
252static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev);
253static int tulip_open(struct net_device *dev);
254static int tulip_close(struct net_device *dev);
255static void tulip_up(struct net_device *dev);
256static void tulip_down(struct net_device *dev);
257static struct net_device_stats *tulip_get_stats(struct net_device *dev);
258static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
259static void set_rx_mode(struct net_device *dev);
260#ifdef CONFIG_NET_POLL_CONTROLLER
261static void poll_tulip(struct net_device *dev);
262#endif
263
264static void tulip_set_power_state (struct tulip_private *tp,
265 int sleep, int snooze)
266{
267 if (tp->flags & HAS_ACPI) {
268 u32 tmp, newtmp;
269 pci_read_config_dword (tp->pdev, CFDD, &tmp);
270 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
271 if (sleep)
272 newtmp |= CFDD_Sleep;
273 else if (snooze)
274 newtmp |= CFDD_Snooze;
275 if (tmp != newtmp)
276 pci_write_config_dword (tp->pdev, CFDD, newtmp);
277 }
278
279}
280
281
282static void tulip_up(struct net_device *dev)
283{
284 struct tulip_private *tp = netdev_priv(dev);
285 void __iomem *ioaddr = tp->base_addr;
286 int next_tick = 3*HZ;
287 int i;
288
289 /* Wake the chip from sleep/snooze mode. */
290 tulip_set_power_state (tp, 0, 0);
291
292 /* On some chip revs we must set the MII/SYM port before the reset!? */
293 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
294 iowrite32(0x00040000, ioaddr + CSR6);
295
296 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
297 iowrite32(0x00000001, ioaddr + CSR0);
298 udelay(100);
299
300 /* Deassert reset.
301 Wait the specified 50 PCI cycles after a reset by initializing
302 Tx and Rx queues and the address filter list. */
303 iowrite32(tp->csr0, ioaddr + CSR0);
304 udelay(100);
305
306 if (tulip_debug > 1)
307 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
308
309 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
310 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
311 tp->cur_rx = tp->cur_tx = 0;
312 tp->dirty_rx = tp->dirty_tx = 0;
313
314 if (tp->flags & MC_HASH_ONLY) {
315 u32 addr_low = le32_to_cpu(get_unaligned((u32 *)dev->dev_addr));
316 u32 addr_high = le16_to_cpu(get_unaligned((u16 *)(dev->dev_addr+4)));
317 if (tp->chip_id == AX88140) {
318 iowrite32(0, ioaddr + CSR13);
319 iowrite32(addr_low, ioaddr + CSR14);
320 iowrite32(1, ioaddr + CSR13);
321 iowrite32(addr_high, ioaddr + CSR14);
322 } else if (tp->flags & COMET_MAC_ADDR) {
323 iowrite32(addr_low, ioaddr + 0xA4);
324 iowrite32(addr_high, ioaddr + 0xA8);
325 iowrite32(0, ioaddr + 0xAC);
326 iowrite32(0, ioaddr + 0xB0);
327 }
328 } else {
329 /* This is set_rx_mode(), but without starting the transmitter. */
330 u16 *eaddrs = (u16 *)dev->dev_addr;
331 u16 *setup_frm = &tp->setup_frame[15*6];
332 dma_addr_t mapping;
333
334 /* 21140 bug: you must add the broadcast address. */
335 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
336 /* Fill the final entry of the table with our physical address. */
337 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
338 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
339 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
340
341 mapping = pci_map_single(tp->pdev, tp->setup_frame,
342 sizeof(tp->setup_frame),
343 PCI_DMA_TODEVICE);
344 tp->tx_buffers[tp->cur_tx].skb = NULL;
345 tp->tx_buffers[tp->cur_tx].mapping = mapping;
346
347 /* Put the setup frame on the Tx list. */
348 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
349 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
350 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
351
352 tp->cur_tx++;
353 }
354
355 tp->saved_if_port = dev->if_port;
356 if (dev->if_port == 0)
357 dev->if_port = tp->default_port;
358
359 /* Allow selecting a default media. */
360 i = 0;
361 if (tp->mtable == NULL)
362 goto media_picked;
363 if (dev->if_port) {
364 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
365 (dev->if_port == 12 ? 0 : dev->if_port);
366 for (i = 0; i < tp->mtable->leafcount; i++)
367 if (tp->mtable->mleaf[i].media == looking_for) {
368 printk(KERN_INFO "%s: Using user-specified media %s.\n",
369 dev->name, medianame[dev->if_port]);
370 goto media_picked;
371 }
372 }
373 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
374 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
375 for (i = 0; i < tp->mtable->leafcount; i++)
376 if (tp->mtable->mleaf[i].media == looking_for) {
377 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
378 dev->name, medianame[looking_for]);
379 goto media_picked;
380 }
381 }
382 /* Start sensing first non-full-duplex media. */
383 for (i = tp->mtable->leafcount - 1;
384 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
385 ;
386media_picked:
387
388 tp->csr6 = 0;
389 tp->cur_index = i;
390 tp->nwayset = 0;
391
392 if (dev->if_port) {
393 if (tp->chip_id == DC21143 &&
394 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
395 /* We must reset the media CSRs when we force-select MII mode. */
396 iowrite32(0x0000, ioaddr + CSR13);
397 iowrite32(0x0000, ioaddr + CSR14);
398 iowrite32(0x0008, ioaddr + CSR15);
399 }
400 tulip_select_media(dev, 1);
401 } else if (tp->chip_id == DC21142) {
402 if (tp->mii_cnt) {
403 tulip_select_media(dev, 1);
404 if (tulip_debug > 1)
405 printk(KERN_INFO "%s: Using MII transceiver %d, status "
406 "%4.4x.\n",
407 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
408 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
409 tp->csr6 = csr6_mask_hdcap;
410 dev->if_port = 11;
411 iowrite32(0x0000, ioaddr + CSR13);
412 iowrite32(0x0000, ioaddr + CSR14);
413 } else
414 t21142_start_nway(dev);
415 } else if (tp->chip_id == PNIC2) {
416 /* for initial startup advertise 10/100 Full and Half */
417 tp->sym_advertise = 0x01E0;
418 /* enable autonegotiate end interrupt */
419 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
420 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
421 pnic2_start_nway(dev);
422 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
423 if (tp->mii_cnt) {
424 dev->if_port = 11;
425 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
426 iowrite32(0x0001, ioaddr + CSR15);
427 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
428 pnic_do_nway(dev);
429 else {
430 /* Start with 10mbps to do autonegotiation. */
431 iowrite32(0x32, ioaddr + CSR12);
432 tp->csr6 = 0x00420000;
433 iowrite32(0x0001B078, ioaddr + 0xB8);
434 iowrite32(0x0201B078, ioaddr + 0xB8);
435 next_tick = 1*HZ;
436 }
437 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
438 && ! tp->medialock) {
439 dev->if_port = 0;
440 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
441 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
442 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
443 /* Provided by BOLO, Macronix - 12/10/1998. */
444 dev->if_port = 0;
445 tp->csr6 = 0x01a80200;
446 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
447 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
448 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
449 /* Enable automatic Tx underrun recovery. */
450 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
451 dev->if_port = tp->mii_cnt ? 11 : 0;
452 tp->csr6 = 0x00040000;
453 } else if (tp->chip_id == AX88140) {
454 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
455 } else
456 tulip_select_media(dev, 1);
457
458 /* Start the chip's Tx to process setup frame. */
459 tulip_stop_rxtx(tp);
460 barrier();
461 udelay(5);
462 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
463
464 /* Enable interrupts by setting the interrupt mask. */
465 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
466 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
467 tulip_start_rxtx(tp);
468 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
469
470 if (tulip_debug > 2) {
471 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
472 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
473 ioread32(ioaddr + CSR6));
474 }
475
476 /* Set the timer to switch to check for link beat and perhaps switch
477 to an alternate media type. */
478 tp->timer.expires = RUN_AT(next_tick);
479 add_timer(&tp->timer);
480#ifdef CONFIG_TULIP_NAPI
481 init_timer(&tp->oom_timer);
482 tp->oom_timer.data = (unsigned long)dev;
483 tp->oom_timer.function = oom_timer;
484#endif
485}
486
487static int
488tulip_open(struct net_device *dev)
489{
490 int retval;
491
1fb9df5d 492 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev)))
1da177e4
LT		 493 return retval;
494
495 tulip_init_ring (dev);
496
497 tulip_up (dev);
498
499 netif_start_queue (dev);
500
501 return 0;
502}
503
504
505static void tulip_tx_timeout(struct net_device *dev)
506{
507 struct tulip_private *tp = netdev_priv(dev);
508 void __iomem *ioaddr = tp->base_addr;
509 unsigned long flags;
510
511 spin_lock_irqsave (&tp->lock, flags);
512
513 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
514 /* Do nothing -- the media monitor should handle this. */
515 if (tulip_debug > 1)
516 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
517 dev->name);
518 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
519 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
ea8f400c 520 || tp->chip_id == DM910X) {
1da177e4
LT		 521 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
522 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
523 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
524 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
525 if ( ! tp->medialock && tp->mtable) {
526 do
527 --tp->cur_index;
528 while (tp->cur_index >= 0
529 && (tulip_media_cap[tp->mtable->mleaf[tp->cur_index].media]
530 & MediaIsFD));
531 if (--tp->cur_index < 0) {
532 /* We start again, but should instead look for default. */
533 tp->cur_index = tp->mtable->leafcount - 1;
534 }
535 tulip_select_media(dev, 0);
536 printk(KERN_WARNING "%s: transmit timed out, switching to %s "
537 "media.\n", dev->name, medianame[dev->if_port]);
538 }
539 } else if (tp->chip_id == PNIC2) {
540 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
541 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
542 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
543 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
544 } else {
545 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
546 "%8.8x, resetting...\n",
547 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
548 dev->if_port = 0;
549 }
550
551#if defined(way_too_many_messages)
552 if (tulip_debug > 3) {
553 int i;
554 for (i = 0; i < RX_RING_SIZE; i++) {
555 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
556 int j;
557 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
558 "%2.2x %2.2x %2.2x.\n",
559 i, (unsigned int)tp->rx_ring[i].status,
560 (unsigned int)tp->rx_ring[i].length,
561 (unsigned int)tp->rx_ring[i].buffer1,
562 (unsigned int)tp->rx_ring[i].buffer2,
563 buf[0], buf[1], buf[2]);
564 for (j = 0; buf[j] != 0xee && j < 1600; j++)
565 if (j < 100) printk(" %2.2x", buf[j]);
566 printk(" j=%d.\n", j);
567 }
568 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
569 for (i = 0; i < RX_RING_SIZE; i++)
570 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
571 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
572 for (i = 0; i < TX_RING_SIZE; i++)
573 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
574 printk("\n");
575 }
576#endif
577
578 /* Stop and restart the chip's Tx processes . */
579
580 tulip_restart_rxtx(tp);
581 /* Trigger an immediate transmit demand. */
582 iowrite32(0, ioaddr + CSR1);
583
584 tp->stats.tx_errors++;
585
586 spin_unlock_irqrestore (&tp->lock, flags);
587 dev->trans_start = jiffies;
588 netif_wake_queue (dev);
589}
590
591
592/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
593static void tulip_init_ring(struct net_device *dev)
594{
595 struct tulip_private *tp = netdev_priv(dev);
596 int i;
597
598 tp->susp_rx = 0;
599 tp->ttimer = 0;
600 tp->nir = 0;
601
602 for (i = 0; i < RX_RING_SIZE; i++) {
603 tp->rx_ring[i].status = 0x00000000;
604 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
605 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
606 tp->rx_buffers[i].skb = NULL;
607 tp->rx_buffers[i].mapping = 0;
608 }
609 /* Mark the last entry as wrapping the ring. */
610 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
611 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
612
613 for (i = 0; i < RX_RING_SIZE; i++) {
614 dma_addr_t mapping;
615
616 /* Note the receive buffer must be longword aligned.
617 dev_alloc_skb() provides 16 byte alignment. But do *not*
618 use skb_reserve() to align the IP header! */
619 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
620 tp->rx_buffers[i].skb = skb;
621 if (skb == NULL)
622 break;
689be439 623 mapping = pci_map_single(tp->pdev, skb->data,
1da177e4
LT		 624 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
625 tp->rx_buffers[i].mapping = mapping;
626 skb->dev = dev; /* Mark as being used by this device. */
627 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
628 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
629 }
630 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
631
632 /* The Tx buffer descriptor is filled in as needed, but we
633 do need to clear the ownership bit. */
634 for (i = 0; i < TX_RING_SIZE; i++) {
635 tp->tx_buffers[i].skb = NULL;
636 tp->tx_buffers[i].mapping = 0;
637 tp->tx_ring[i].status = 0x00000000;
638 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
639 }
640 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
641}
642
643static int
644tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
645{
646 struct tulip_private *tp = netdev_priv(dev);
647 int entry;
648 u32 flag;
649 dma_addr_t mapping;
650
651 spin_lock_irq(&tp->lock);
652
653 /* Calculate the next Tx descriptor entry. */
654 entry = tp->cur_tx % TX_RING_SIZE;
655
656 tp->tx_buffers[entry].skb = skb;
657 mapping = pci_map_single(tp->pdev, skb->data,
658 skb->len, PCI_DMA_TODEVICE);
659 tp->tx_buffers[entry].mapping = mapping;
660 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
661
662 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
663 flag = 0x60000000; /* No interrupt */
664 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
665 flag = 0xe0000000; /* Tx-done intr. */
666 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
667 flag = 0x60000000; /* No Tx-done intr. */
668 } else { /* Leave room for set_rx_mode() to fill entries. */
669 flag = 0xe0000000; /* Tx-done intr. */
670 netif_stop_queue(dev);
671 }
672 if (entry == TX_RING_SIZE-1)
673 flag = 0xe0000000 | DESC_RING_WRAP;
674
675 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
676 /* if we were using Transmit Automatic Polling, we would need a
677 * wmb() here. */
678 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
679 wmb();
680
681 tp->cur_tx++;
682
683 /* Trigger an immediate transmit demand. */
684 iowrite32(0, tp->base_addr + CSR1);
685
686 spin_unlock_irq(&tp->lock);
687
688 dev->trans_start = jiffies;
689
690 return 0;
691}
692
693static void tulip_clean_tx_ring(struct tulip_private *tp)
694{
695 unsigned int dirty_tx;
696
697 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
698 dirty_tx++) {
699 int entry = dirty_tx % TX_RING_SIZE;
700 int status = le32_to_cpu(tp->tx_ring[entry].status);
701
702 if (status < 0) {
703 tp->stats.tx_errors++; /* It wasn't Txed */
704 tp->tx_ring[entry].status = 0;
705 }
706
707 /* Check for Tx filter setup frames. */
708 if (tp->tx_buffers[entry].skb == NULL) {
709 /* test because dummy frames not mapped */
710 if (tp->tx_buffers[entry].mapping)
711 pci_unmap_single(tp->pdev,
712 tp->tx_buffers[entry].mapping,
713 sizeof(tp->setup_frame),
714 PCI_DMA_TODEVICE);
715 continue;
716 }
717
718 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
719 tp->tx_buffers[entry].skb->len,
720 PCI_DMA_TODEVICE);
721
722 /* Free the original skb. */
723 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
724 tp->tx_buffers[entry].skb = NULL;
725 tp->tx_buffers[entry].mapping = 0;
726 }
727}
728
729static void tulip_down (struct net_device *dev)
730{
731 struct tulip_private *tp = netdev_priv(dev);
732 void __iomem *ioaddr = tp->base_addr;
733 unsigned long flags;
734
735 del_timer_sync (&tp->timer);
736#ifdef CONFIG_TULIP_NAPI
737 del_timer_sync (&tp->oom_timer);
738#endif
739 spin_lock_irqsave (&tp->lock, flags);
740
741 /* Disable interrupts by clearing the interrupt mask. */
742 iowrite32 (0x00000000, ioaddr + CSR7);
743
744 /* Stop the Tx and Rx processes. */
745 tulip_stop_rxtx(tp);
746
747 /* prepare receive buffers */
748 tulip_refill_rx(dev);
749
750 /* release any unconsumed transmit buffers */
751 tulip_clean_tx_ring(tp);
752
753 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
754 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
755
756 spin_unlock_irqrestore (&tp->lock, flags);
757
758 init_timer(&tp->timer);
759 tp->timer.data = (unsigned long)dev;
760 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
761
762 dev->if_port = tp->saved_if_port;
763
764 /* Leave the driver in snooze, not sleep, mode. */
765 tulip_set_power_state (tp, 0, 1);
766}
767
768
769static int tulip_close (struct net_device *dev)
770{
771 struct tulip_private *tp = netdev_priv(dev);
772 void __iomem *ioaddr = tp->base_addr;
773 int i;
774
775 netif_stop_queue (dev);
776
777 tulip_down (dev);
778
779 if (tulip_debug > 1)
780 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
781 dev->name, ioread32 (ioaddr + CSR5));
782
783 free_irq (dev->irq, dev);
784
785 /* Free all the skbuffs in the Rx queue. */
786 for (i = 0; i < RX_RING_SIZE; i++) {
787 struct sk_buff *skb = tp->rx_buffers[i].skb;
788 dma_addr_t mapping = tp->rx_buffers[i].mapping;
789
790 tp->rx_buffers[i].skb = NULL;
791 tp->rx_buffers[i].mapping = 0;
792
793 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
794 tp->rx_ring[i].length = 0;
795 tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */
796 if (skb) {
797 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
798 PCI_DMA_FROMDEVICE);
799 dev_kfree_skb (skb);
800 }
801 }
802 for (i = 0; i < TX_RING_SIZE; i++) {
803 struct sk_buff *skb = tp->tx_buffers[i].skb;
804
805 if (skb != NULL) {
806 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
807 skb->len, PCI_DMA_TODEVICE);
808 dev_kfree_skb (skb);
809 }
810 tp->tx_buffers[i].skb = NULL;
811 tp->tx_buffers[i].mapping = 0;
812 }
813
814 return 0;
815}
816
817static struct net_device_stats *tulip_get_stats(struct net_device *dev)
818{
819 struct tulip_private *tp = netdev_priv(dev);
820 void __iomem *ioaddr = tp->base_addr;
821
822 if (netif_running(dev)) {
823 unsigned long flags;
824
825 spin_lock_irqsave (&tp->lock, flags);
826
827 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
828
829 spin_unlock_irqrestore(&tp->lock, flags);
830 }
831
832 return &tp->stats;
833}
834
835
836static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
837{
838 struct tulip_private *np = netdev_priv(dev);
839 strcpy(info->driver, DRV_NAME);
840 strcpy(info->version, DRV_VERSION);
841 strcpy(info->bus_info, pci_name(np->pdev));
842}
843
844static struct ethtool_ops ops = {
845 .get_drvinfo = tulip_get_drvinfo
846};
847
848/* Provide ioctl() calls to examine the MII xcvr state. */
849static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
850{
851 struct tulip_private *tp = netdev_priv(dev);
852 void __iomem *ioaddr = tp->base_addr;
853 struct mii_ioctl_data *data = if_mii(rq);
854 const unsigned int phy_idx = 0;
855 int phy = tp->phys[phy_idx] & 0x1f;
856 unsigned int regnum = data->reg_num;
857
858 switch (cmd) {
859 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
860 if (tp->mii_cnt)
861 data->phy_id = phy;
862 else if (tp->flags & HAS_NWAY)
863 data->phy_id = 32;
864 else if (tp->chip_id == COMET)
865 data->phy_id = 1;
866 else
867 return -ENODEV;
868
869 case SIOCGMIIREG: /* Read MII PHY register. */
870 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
871 int csr12 = ioread32 (ioaddr + CSR12);
872 int csr14 = ioread32 (ioaddr + CSR14);
873 switch (regnum) {
874 case 0:
875 if (((csr14<<5) & 0x1000) ||
876 (dev->if_port == 5 && tp->nwayset))
877 data->val_out = 0x1000;
878 else
879 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
880 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
881 break;
882 case 1:
883 data->val_out =
884 0x1848 +
885 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
886 ((csr12&0x06) == 6 ? 0 : 4);
887 data->val_out |= 0x6048;
888 break;
889 case 4:
890 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
891 data->val_out =
892 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
893 ((csr14 >> 1) & 0x20) + 1;
894 data->val_out |= ((csr14 >> 9) & 0x03C0);
895 break;
896 case 5: data->val_out = tp->lpar; break;
897 default: data->val_out = 0; break;
898 }
899 } else {
900 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
901 }
902 return 0;
903
904 case SIOCSMIIREG: /* Write MII PHY register. */
905 if (!capable (CAP_NET_ADMIN))
906 return -EPERM;
907 if (regnum & ~0x1f)
908 return -EINVAL;
909 if (data->phy_id == phy) {
910 u16 value = data->val_in;
911 switch (regnum) {
912 case 0: /* Check for autonegotiation on or reset. */
913 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
914 if (tp->full_duplex_lock)
915 tp->full_duplex = (value & 0x0100) ? 1 : 0;
916 break;
917 case 4:
918 tp->advertising[phy_idx] =
919 tp->mii_advertise = data->val_in;
920 break;
921 }
922 }
923 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
924 u16 value = data->val_in;
925 if (regnum == 0) {
926 if ((value & 0x1200) == 0x1200) {
927 if (tp->chip_id == PNIC2) {
928 pnic2_start_nway (dev);
929 } else {
930 t21142_start_nway (dev);
931 }
932 }
933 } else if (regnum == 4)
934 tp->sym_advertise = value;
935 } else {
936 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
937 }
938 return 0;
939 default:
940 return -EOPNOTSUPP;
941 }
942
943 return -EOPNOTSUPP;
944}
945
946
947/* Set or clear the multicast filter for this adaptor.
948 Note that we only use exclusion around actually queueing the
949 new frame, not around filling tp->setup_frame. This is non-deterministic
950 when re-entered but still correct. */
951
952#undef set_bit_le
953#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
954
955static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
956{
957 struct tulip_private *tp = netdev_priv(dev);
958 u16 hash_table[32];
959 struct dev_mc_list *mclist;
960 int i;
961 u16 *eaddrs;
962
963 memset(hash_table, 0, sizeof(hash_table));
964 set_bit_le(255, hash_table); /* Broadcast entry */
965 /* This should work on big-endian machines as well. */
966 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
967 i++, mclist = mclist->next) {
968 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
969
970 set_bit_le(index, hash_table);
971
972 }
973 for (i = 0; i < 32; i++) {
974 *setup_frm++ = hash_table[i];
975 *setup_frm++ = hash_table[i];
976 }
977 setup_frm = &tp->setup_frame[13*6];
978
979 /* Fill the final entry with our physical address. */
980 eaddrs = (u16 *)dev->dev_addr;
981 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
982 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
983 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
984}
985
986static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
987{
988 struct tulip_private *tp = netdev_priv(dev);
989 struct dev_mc_list *mclist;
990 int i;
991 u16 *eaddrs;
992
993 /* We have <= 14 addresses so we can use the wonderful
994 16 address perfect filtering of the Tulip. */
995 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
996 i++, mclist = mclist->next) {
997 eaddrs = (u16 *)mclist->dmi_addr;
998 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
999 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1000 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1001 }
1002 /* Fill the unused entries with the broadcast address. */
1003 memset(setup_frm, 0xff, (15-i)*12);
1004 setup_frm = &tp->setup_frame[15*6];
1005
1006 /* Fill the final entry with our physical address. */
1007 eaddrs = (u16 *)dev->dev_addr;
1008 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1009 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1010 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1011}
1012
1013
1014static void set_rx_mode(struct net_device *dev)
1015{
1016 struct tulip_private *tp = netdev_priv(dev);
1017 void __iomem *ioaddr = tp->base_addr;
1018 int csr6;
1019
1020 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1021
1022 tp->csr6 &= ~0x00D5;
1023 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1024 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1025 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1da177e4
LT		 1026 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1027 /* Too many to filter well -- accept all multicasts. */
1028 tp->csr6 |= AcceptAllMulticast;
1029 csr6 |= AcceptAllMulticast;
1030 } else if (tp->flags & MC_HASH_ONLY) {
1031 /* Some work-alikes have only a 64-entry hash filter table. */
1032 /* Should verify correctness on big-endian/__powerpc__ */
1033 struct dev_mc_list *mclist;
1034 int i;
1035 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1036 tp->csr6 |= AcceptAllMulticast;
1037 csr6 |= AcceptAllMulticast;
1038 } else {
1039 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1040 int filterbit;
1041 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1042 i++, mclist = mclist->next) {
1043 if (tp->flags & COMET_MAC_ADDR)
1044 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1045 else
1046 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1047 filterbit &= 0x3f;
1048 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1049 if (tulip_debug > 2) {
1050 printk(KERN_INFO "%s: Added filter for %2.2x:%2.2x:%2.2x:"
1051 "%2.2x:%2.2x:%2.2x %8.8x bit %d.\n", dev->name,
1052 mclist->dmi_addr[0], mclist->dmi_addr[1],
1053 mclist->dmi_addr[2], mclist->dmi_addr[3],
1054 mclist->dmi_addr[4], mclist->dmi_addr[5],
1055 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1056 }
1057 }
1058 if (mc_filter[0] == tp->mc_filter[0] &&
1059 mc_filter[1] == tp->mc_filter[1])
1060 ; /* No change. */
1061 else if (tp->flags & IS_ASIX) {
1062 iowrite32(2, ioaddr + CSR13);
1063 iowrite32(mc_filter[0], ioaddr + CSR14);
1064 iowrite32(3, ioaddr + CSR13);
1065 iowrite32(mc_filter[1], ioaddr + CSR14);
1066 } else if (tp->flags & COMET_MAC_ADDR) {
1067 iowrite32(mc_filter[0], ioaddr + 0xAC);
1068 iowrite32(mc_filter[1], ioaddr + 0xB0);
1069 }
1070 tp->mc_filter[0] = mc_filter[0];
1071 tp->mc_filter[1] = mc_filter[1];
1072 }
1073 } else {
1074 unsigned long flags;
1075 u32 tx_flags = 0x08000000 | 192;
1076
1077 /* Note that only the low-address shortword of setup_frame is valid!
1078 The values are doubled for big-endian architectures. */
1079 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1080 build_setup_frame_hash(tp->setup_frame, dev);
1081 tx_flags = 0x08400000 | 192;
1082 } else {
1083 build_setup_frame_perfect(tp->setup_frame, dev);
1084 }
1085
1086 spin_lock_irqsave(&tp->lock, flags);
1087
1088 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1089 /* Same setup recently queued, we need not add it. */
1090 } else {
1091 unsigned int entry;
1092 int dummy = -1;
1093
1094 /* Now add this frame to the Tx list. */
1095
1096 entry = tp->cur_tx++ % TX_RING_SIZE;
1097
1098 if (entry != 0) {
ea8f400c
PC		 1099 /* Avoid a chip errata by prefixing a dummy entry. */
1100 tp->tx_buffers[entry].skb = NULL;
1101 tp->tx_buffers[entry].mapping = 0;
1102 tp->tx_ring[entry].length =
1103 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1104 tp->tx_ring[entry].buffer1 = 0;
1105 /* Must set DescOwned later to avoid race with chip */
1106 dummy = entry;
1107 entry = tp->cur_tx++ % TX_RING_SIZE;
1108
1da177e4
LT		 1109 }
1110
1111 tp->tx_buffers[entry].skb = NULL;
1112 tp->tx_buffers[entry].mapping =
1113 pci_map_single(tp->pdev, tp->setup_frame,
1114 sizeof(tp->setup_frame),
1115 PCI_DMA_TODEVICE);
1116 /* Put the setup frame on the Tx list. */
1117 if (entry == TX_RING_SIZE-1)
1118 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1119 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1120 tp->tx_ring[entry].buffer1 =
1121 cpu_to_le32(tp->tx_buffers[entry].mapping);
1122 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1123 if (dummy >= 0)
1124 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1125 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1126 netif_stop_queue(dev);
1127
1128 /* Trigger an immediate transmit demand. */
1129 iowrite32(0, ioaddr + CSR1);
1130 }
1131
1132 spin_unlock_irqrestore(&tp->lock, flags);
1133 }
1134
1135 iowrite32(csr6, ioaddr + CSR6);
1136}
1137
1138#ifdef CONFIG_TULIP_MWI
1139static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1140 struct net_device *dev)
1141{
1142 struct tulip_private *tp = netdev_priv(dev);
1143 u8 cache;
1144 u16 pci_command;
1145 u32 csr0;
1146
1147 if (tulip_debug > 3)
1148 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1149
1150 tp->csr0 = csr0 = 0;
1151
1152 /* if we have any cache line size at all, we can do MRM */
1153 csr0 |= MRM;
1154
1155 /* ...and barring hardware bugs, MWI */
1156 if (!(tp->chip_id == DC21143 && tp->revision == 65))
1157 csr0 |= MWI;
1158
1159 /* set or disable MWI in the standard PCI command bit.
1160 * Check for the case where mwi is desired but not available
1161 */
1162 if (csr0 & MWI) pci_set_mwi(pdev);
1163 else pci_clear_mwi(pdev);
1164
1165 /* read result from hardware (in case bit refused to enable) */
1166 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1167 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1168 csr0 &= ~MWI;
1169
1170 /* if cache line size hardwired to zero, no MWI */
1171 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1172 if ((csr0 & MWI) && (cache == 0)) {
1173 csr0 &= ~MWI;
1174 pci_clear_mwi(pdev);
1175 }
1176
1177 /* assign per-cacheline-size cache alignment and
1178 * burst length values
1179 */
1180 switch (cache) {
1181 case 8:
1182 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1183 break;
1184 case 16:
1185 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1186 break;
1187 case 32:
1188 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1189 break;
1190 default:
1191 cache = 0;
1192 break;
1193 }
1194
1195 /* if we have a good cache line size, we by now have a good
1196 * csr0, so save it and exit
1197 */
1198 if (cache)
1199 goto out;
1200
1201 /* we don't have a good csr0 or cache line size, disable MWI */
1202 if (csr0 & MWI) {
1203 pci_clear_mwi(pdev);
1204 csr0 &= ~MWI;
1205 }
1206
1207 /* sane defaults for burst length and cache alignment
1208 * originally from de4x5 driver
1209 */
1210 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1211
1212out:
1213 tp->csr0 = csr0;
1214 if (tulip_debug > 2)
1215 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1216 pci_name(pdev), cache, csr0);
1217}
1218#endif
1219
1220/*
1221 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1222 * is the DM910X and the on chip ULi devices
1223 */
f3b197ac 1224
1da177e4
LT		 1225static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1226{
1227 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1228 return 1;
1da177e4
LT		 1229 return 0;
1230}
1231
1232static int __devinit tulip_init_one (struct pci_dev *pdev,
1233 const struct pci_device_id *ent)
1234{
1235 struct tulip_private *tp;
1236 /* See note below on the multiport cards. */
1237 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1238 static struct pci_device_id early_486_chipsets[] = {
1239 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1240 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1241 { },
1242 };
1243 static int last_irq;
1244 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1245 u8 chip_rev;
1246 int i, irq;
1247 unsigned short sum;
1248 unsigned char *ee_data;
1249 struct net_device *dev;
1250 void __iomem *ioaddr;
1251 static int board_idx = -1;
1252 int chip_idx = ent->driver_data;
1253 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1254 unsigned int eeprom_missing = 0;
1255 unsigned int force_csr0 = 0;
1256
1257#ifndef MODULE
1258 static int did_version; /* Already printed version info. */
1259 if (tulip_debug > 0 && did_version++ == 0)
1260 printk (KERN_INFO "%s", version);
1261#endif
1262
1263 board_idx++;
1264
1265 /*
1266 * Lan media wire a tulip chip to a wan interface. Needs a very
1267 * different driver (lmc driver)
1268 */
1269
1270 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1271 printk (KERN_ERR PFX "skipping LMC card.\n");
1272 return -ENODEV;
1273 }
1274
1275 /*
1276 * Early DM9100's need software CRC and the DMFE driver
1277 */
1278
1279 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1280 {
1281 u32 dev_rev;
1282 /* Read Chip revision */
1283 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
1284 if(dev_rev < 0x02000030)
1285 {
1286 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1287 return -ENODEV;
1288 }
1289 }
1290
1291 /*
1292 * Looks for early PCI chipsets where people report hangs
1293 * without the workarounds being on.
1294 */
1295
1296 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
f3b197ac 1297 aligned. Aries might need this too. The Saturn errata are not
1da177e4
LT		 1298 pretty reading but thankfully it's an old 486 chipset.
1299
1300 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1301 Saturn.
1302 */
1303
1304 if (pci_dev_present(early_486_chipsets)) {
1305 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1306 force_csr0 = 1;
1307 }
1308
1309 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1310 if (chip_idx == AX88140) {
1311 if ((csr0 & 0x3f00) == 0)
1312 csr0 |= 0x2000;
1313 }
1314
1315 /* PNIC doesn't have MWI/MRL/MRM... */
1316 if (chip_idx == LC82C168)
1317 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1318
1319 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1320 if (tulip_uli_dm_quirk(pdev)) {
1321 csr0 &= ~0x01f100ff;
1322#if defined(__sparc__)
1323 csr0 = (csr0 & ~0xff00) | 0xe000;
1324#endif
1325 }
1326 /*
1327 * And back to business
1328 */
1329
1330 i = pci_enable_device(pdev);
1331 if (i) {
1332 printk (KERN_ERR PFX
1333 "Cannot enable tulip board #%d, aborting\n",
1334 board_idx);
1335 return i;
1336 }
1337
1338 irq = pdev->irq;
1339
1340 /* alloc_etherdev ensures aligned and zeroed private structures */
1341 dev = alloc_etherdev (sizeof (*tp));
1342 if (!dev) {
1343 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1344 return -ENOMEM;
1345 }
1346
1347 SET_MODULE_OWNER(dev);
1348 SET_NETDEV_DEV(dev, &pdev->dev);
1349 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
7c7459d1 1350 printk (KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, "
1da177e4 1351 "aborting\n", pci_name(pdev),
7c7459d1
GKH		 1352 (unsigned long long)pci_resource_len (pdev, 0),
1353 (unsigned long long)pci_resource_start (pdev, 0));
1da177e4
LT		 1354 goto err_out_free_netdev;
1355 }
1356
1357 /* grab all resources from both PIO and MMIO regions, as we
1358 * don't want anyone else messing around with our hardware */
1359 if (pci_request_regions (pdev, "tulip"))
1360 goto err_out_free_netdev;
1361
1362#ifndef USE_IO_OPS
1363 ioaddr = pci_iomap(pdev, 1, tulip_tbl[chip_idx].io_size);
1364#else
1365 ioaddr = pci_iomap(pdev, 0, tulip_tbl[chip_idx].io_size);
1366#endif
1367 if (!ioaddr)
1368 goto err_out_free_res;
1369
1370 pci_read_config_byte (pdev, PCI_REVISION_ID, &chip_rev);
1371
1372 /*
1373 * initialize private data structure 'tp'
1374 * it is zeroed and aligned in alloc_etherdev
1375 */
1376 tp = netdev_priv(dev);
1377
1378 tp->rx_ring = pci_alloc_consistent(pdev,
1379 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1380 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1381 &tp->rx_ring_dma);
1382 if (!tp->rx_ring)
1383 goto err_out_mtable;
1384 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1385 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1386
1387 tp->chip_id = chip_idx;
1388 tp->flags = tulip_tbl[chip_idx].flags;
1389 tp->pdev = pdev;
1390 tp->base_addr = ioaddr;
1391 tp->revision = chip_rev;
1392 tp->csr0 = csr0;
1393 spin_lock_init(&tp->lock);
1394 spin_lock_init(&tp->mii_lock);
1395 init_timer(&tp->timer);
1396 tp->timer.data = (unsigned long)dev;
1397 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1398
1399 dev->base_addr = (unsigned long)ioaddr;
1400
1401#ifdef CONFIG_TULIP_MWI
1402 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1403 tulip_mwi_config (pdev, dev);
1404#else
1405 /* MWI is broken for DC21143 rev 65... */
1406 if (chip_idx == DC21143 && chip_rev == 65)
1407 tp->csr0 &= ~MWI;
1408#endif
1409
1410 /* Stop the chip's Tx and Rx processes. */
1411 tulip_stop_rxtx(tp);
1412
1413 pci_set_master(pdev);
1414
1415#ifdef CONFIG_GSC
1416 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1417 switch (pdev->subsystem_device) {
1418 default:
1419 break;
1420 case 0x1061:
1421 case 0x1062:
1422 case 0x1063:
1423 case 0x1098:
1424 case 0x1099:
1425 case 0x10EE:
1426 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1427 chip_name = "GSC DS21140 Tulip";
1428 }
1429 }
1430#endif
1431
1432 /* Clear the missed-packet counter. */
1433 ioread32(ioaddr + CSR8);
1434
1435 /* The station address ROM is read byte serially. The register must
1436 be polled, waiting for the value to be read bit serially from the
1437 EEPROM.
1438 */
1439 ee_data = tp->eeprom;
1440 sum = 0;
1441 if (chip_idx == LC82C168) {
1442 for (i = 0; i < 3; i++) {
1443 int value, boguscnt = 100000;
1444 iowrite32(0x600 | i, ioaddr + 0x98);
1445 do
1446 value = ioread32(ioaddr + CSR9);
1447 while (value < 0 && --boguscnt > 0);
1448 put_unaligned(le16_to_cpu(value), ((u16*)dev->dev_addr) + i);
1449 sum += value & 0xffff;
1450 }
1451 } else if (chip_idx == COMET) {
1452 /* No need to read the EEPROM. */
1453 put_unaligned(cpu_to_le32(ioread32(ioaddr + 0xA4)), (u32 *)dev->dev_addr);
1454 put_unaligned(cpu_to_le16(ioread32(ioaddr + 0xA8)), (u16 *)(dev->dev_addr + 4));
1455 for (i = 0; i < 6; i ++)
1456 sum += dev->dev_addr[i];
1457 } else {
1458 /* A serial EEPROM interface, we read now and sort it out later. */
1459 int sa_offset = 0;
1460 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1461
1462 for (i = 0; i < sizeof(tp->eeprom); i+=2) {
1463 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1464 ee_data[i] = data & 0xff;
1465 ee_data[i + 1] = data >> 8;
1466 }
1467
1468 /* DEC now has a specification (see Notes) but early board makers
1469 just put the address in the first EEPROM locations. */
1470 /* This does memcmp(ee_data, ee_data+16, 8) */
1471 for (i = 0; i < 8; i ++)
1472 if (ee_data[i] != ee_data[16+i])
1473 sa_offset = 20;
1474 if (chip_idx == CONEXANT) {
1475 /* Check that the tuple type and length is correct. */
1476 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1477 sa_offset = 0x19A;
1478 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1479 ee_data[2] == 0) {
1480 sa_offset = 2; /* Grrr, damn Matrox boards. */
1481 multiport_cnt = 4;
1482 }
1da177e4
LT		 1483#ifdef CONFIG_DDB5477
1484 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
1485 /* DDB5477 MAC address in first EEPROM locations. */
1486 sa_offset = 0;
1487 /* No media table either */
1488 tp->flags &= ~HAS_MEDIA_TABLE;
1489 }
1490#endif
1491#ifdef CONFIG_MIPS_COBALT
f3b197ac 1492 if ((pdev->bus->number == 0) &&
1da177e4
LT		 1493 ((PCI_SLOT(pdev->devfn) == 7) ||
1494 (PCI_SLOT(pdev->devfn) == 12))) {
1495 /* Cobalt MAC address in first EEPROM locations. */
1496 sa_offset = 0;
12755c16
RB		 1497 /* Ensure our media table fixup get's applied */
1498 memcpy(ee_data + 16, ee_data, 8);
1da177e4
LT		 1499 }
1500#endif
1501#ifdef CONFIG_GSC
1502 /* Check to see if we have a broken srom */
1503 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1504 /* pci_vendor_id and subsystem_id are swapped */
1505 ee_data[0] = ee_data[2];
1506 ee_data[1] = ee_data[3];
1507 ee_data[2] = 0x61;
1508 ee_data[3] = 0x10;
1509
1510 /* HSC-PCI boards need to be byte-swaped and shifted
1511 * up 1 word. This shift needs to happen at the end
1512 * of the MAC first because of the 2 byte overlap.
1513 */
1514 for (i = 4; i >= 0; i -= 2) {
1515 ee_data[17 + i + 3] = ee_data[17 + i];
1516 ee_data[16 + i + 5] = ee_data[16 + i];
1517 }
1518 }
1519#endif
1520
1521 for (i = 0; i < 6; i ++) {
1522 dev->dev_addr[i] = ee_data[i + sa_offset];
1523 sum += ee_data[i + sa_offset];
1524 }
1525 }
1526 /* Lite-On boards have the address byte-swapped. */
1527 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1528 && dev->dev_addr[1] == 0x00)
1529 for (i = 0; i < 6; i+=2) {
1530 char tmp = dev->dev_addr[i];
1531 dev->dev_addr[i] = dev->dev_addr[i+1];
1532 dev->dev_addr[i+1] = tmp;
1533 }
1534 /* On the Zynx 315 Etherarray and other multiport boards only the
1535 first Tulip has an EEPROM.
1536 On Sparc systems the mac address is held in the OBP property
1537 "local-mac-address".
1538 The addresses of the subsequent ports are derived from the first.
1539 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1540 that here as well. */
1541 if (sum == 0 || sum == 6*0xff) {
1542#if defined(__sparc__)
1543 struct pcidev_cookie *pcp = pdev->sysdata;
1544#endif
1545 eeprom_missing = 1;
1546 for (i = 0; i < 5; i++)
1547 dev->dev_addr[i] = last_phys_addr[i];
1548 dev->dev_addr[i] = last_phys_addr[i] + 1;
1549#if defined(__sparc__)
de8d28b1
DM		 1550 if (pcp) {
1551 unsigned char *addr;
1552 int len;
1553
1554 addr = of_get_property(pcp->prom_node,
1555 "local-mac-address", &len);
1556 if (addr && len == 6)
1557 memcpy(dev->dev_addr, addr, 6);
1da177e4
LT		 1558 }
1559#endif
b9c4c609 1560#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1da177e4
LT		 1561 if (last_irq)
1562 irq = last_irq;
1563#endif
1564 }
1565
1566 for (i = 0; i < 6; i++)
1567 last_phys_addr[i] = dev->dev_addr[i];
1568 last_irq = irq;
1569 dev->irq = irq;
1570
1571 /* The lower four bits are the media type. */
1572 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1573 if (options[board_idx] & MEDIA_MASK)
1574 tp->default_port = options[board_idx] & MEDIA_MASK;
1575 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1576 tp->full_duplex = 1;
1577 if (mtu[board_idx] > 0)
1578 dev->mtu = mtu[board_idx];
1579 }
1580 if (dev->mem_start & MEDIA_MASK)
1581 tp->default_port = dev->mem_start & MEDIA_MASK;
1582 if (tp->default_port) {
1583 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1584 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1585 tp->medialock = 1;
1586 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1587 tp->full_duplex = 1;
1588 }
1589 if (tp->full_duplex)
1590 tp->full_duplex_lock = 1;
1591
1592 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1593 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1594 tp->mii_advertise = media2advert[tp->default_port - 9];
1595 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1596 }
1597
1598 if (tp->flags & HAS_MEDIA_TABLE) {
1599 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1600 tulip_parse_eeprom(dev);
1601 strcpy(dev->name, "eth%d"); /* un-hack */
1602 }
1603
1604 if ((tp->flags & ALWAYS_CHECK_MII) ||
1605 (tp->mtable && tp->mtable->has_mii) ||
1606 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1607 if (tp->mtable && tp->mtable->has_mii) {
1608 for (i = 0; i < tp->mtable->leafcount; i++)
1609 if (tp->mtable->mleaf[i].media == 11) {
1610 tp->cur_index = i;
1611 tp->saved_if_port = dev->if_port;
1612 tulip_select_media(dev, 2);
1613 dev->if_port = tp->saved_if_port;
1614 break;
1615 }
1616 }
1617
1618 /* Find the connected MII xcvrs.
1619 Doing this in open() would allow detecting external xcvrs
1620 later, but takes much time. */
1621 tulip_find_mii (dev, board_idx);
1622 }
1623
1624 /* The Tulip-specific entries in the device structure. */
1625 dev->open = tulip_open;
1626 dev->hard_start_xmit = tulip_start_xmit;
1627 dev->tx_timeout = tulip_tx_timeout;
1628 dev->watchdog_timeo = TX_TIMEOUT;
1629#ifdef CONFIG_TULIP_NAPI
1630 dev->poll = tulip_poll;
1631 dev->weight = 16;
1632#endif
1633 dev->stop = tulip_close;
1634 dev->get_stats = tulip_get_stats;
1635 dev->do_ioctl = private_ioctl;
1636 dev->set_multicast_list = set_rx_mode;
1637#ifdef CONFIG_NET_POLL_CONTROLLER
1638 dev->poll_controller = &poll_tulip;
1639#endif
1640 SET_ETHTOOL_OPS(dev, &ops);
1641
1642 if (register_netdev(dev))
1643 goto err_out_free_ring;
1644
1645 printk(KERN_INFO "%s: %s rev %d at %p,",
1646 dev->name, chip_name, chip_rev, ioaddr);
1647 pci_set_drvdata(pdev, dev);
1648
1649 if (eeprom_missing)
1650 printk(" EEPROM not present,");
1651 for (i = 0; i < 6; i++)
1652 printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
1653 printk(", IRQ %d.\n", irq);
1654
1655 if (tp->chip_id == PNIC2)
1656 tp->link_change = pnic2_lnk_change;
1657 else if (tp->flags & HAS_NWAY)
1658 tp->link_change = t21142_lnk_change;
1659 else if (tp->flags & HAS_PNICNWAY)
1660 tp->link_change = pnic_lnk_change;
1661
1662 /* Reset the xcvr interface and turn on heartbeat. */
1663 switch (chip_idx) {
1664 case DC21140:
1665 case DM910X:
1da177e4
LT		 1666 default:
1667 if (tp->mtable)
1668 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1669 break;
1670 case DC21142:
1671 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1672 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1673 iowrite32(0x0000, ioaddr + CSR13);
1674 iowrite32(0x0000, ioaddr + CSR14);
1675 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1676 } else
1677 t21142_start_nway(dev);
1678 break;
1679 case PNIC2:
1680 /* just do a reset for sanity sake */
1681 iowrite32(0x0000, ioaddr + CSR13);
1682 iowrite32(0x0000, ioaddr + CSR14);
1683 break;
1684 case LC82C168:
1685 if ( ! tp->mii_cnt) {
1686 tp->nway = 1;
1687 tp->nwayset = 0;
1688 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1689 iowrite32(0x30, ioaddr + CSR12);
1690 iowrite32(0x0001F078, ioaddr + CSR6);
1691 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1692 }
1693 break;
1694 case MX98713:
1695 case COMPEX9881:
1696 iowrite32(0x00000000, ioaddr + CSR6);
1697 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1698 iowrite32(0x00000001, ioaddr + CSR13);
1699 break;
1700 case MX98715:
1701 case MX98725:
1702 iowrite32(0x01a80000, ioaddr + CSR6);
1703 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1704 iowrite32(0x00001000, ioaddr + CSR12);
1705 break;
1706 case COMET:
1707 /* No initialization necessary. */
1708 break;
1709 }
1710
1711 /* put the chip in snooze mode until opened */
1712 tulip_set_power_state (tp, 0, 1);
1713
1714 return 0;
1715
1716err_out_free_ring:
1717 pci_free_consistent (pdev,
1718 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1719 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1720 tp->rx_ring, tp->rx_ring_dma);
1721
1722err_out_mtable:
b4558ea9 1723 kfree (tp->mtable);
1da177e4
LT		 1724 pci_iounmap(pdev, ioaddr);
1725
1726err_out_free_res:
1727 pci_release_regions (pdev);
1728
1729err_out_free_netdev:
1730 free_netdev (dev);
1731 return -ENODEV;
1732}
1733
1734
1735#ifdef CONFIG_PM
1736
1737static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1738{
1739 struct net_device *dev = pci_get_drvdata(pdev);
1740
1fe2cb32
AB		 1741 if (!dev)
1742 return -EINVAL;
1743
1744 if (netif_running(dev))
1745 tulip_down(dev);
1746
1747 netif_device_detach(dev);
1748 free_irq(dev->irq, dev);
1749
1750 pci_save_state(pdev);
1751 pci_disable_device(pdev);
1752 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1753
1da177e4
LT		 1754 return 0;
1755}
1756
1757
1758static int tulip_resume(struct pci_dev *pdev)
1759{
1760 struct net_device *dev = pci_get_drvdata(pdev);
1fe2cb32 1761 int retval;
1da177e4 1762
1fe2cb32
AB		 1763 if (!dev)
1764 return -EINVAL;
1765
1766 pci_set_power_state(pdev, PCI_D0);
1767 pci_restore_state(pdev);
1768
1769 pci_enable_device(pdev);
1770
1fb9df5d 1771 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1fe2cb32
AB		 1772 printk (KERN_ERR "tulip: request_irq failed in resume\n");
1773 return retval;
1da177e4 1774 }
1fe2cb32
AB		 1775
1776 netif_device_attach(dev);
1777
1778 if (netif_running(dev))
1779 tulip_up(dev);
1780
1da177e4
LT		 1781 return 0;
1782}
1783
1784#endif /* CONFIG_PM */
1785
1786
1787static void __devexit tulip_remove_one (struct pci_dev *pdev)
1788{
1789 struct net_device *dev = pci_get_drvdata (pdev);
1790 struct tulip_private *tp;
1791
1792 if (!dev)
1793 return;
1794
1795 tp = netdev_priv(dev);
1796 unregister_netdev(dev);
1797 pci_free_consistent (pdev,
1798 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1799 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1800 tp->rx_ring, tp->rx_ring_dma);
b4558ea9 1801 kfree (tp->mtable);
1da177e4
LT		 1802 pci_iounmap(pdev, tp->base_addr);
1803 free_netdev (dev);
1804 pci_release_regions (pdev);
1805 pci_set_drvdata (pdev, NULL);
1806
1807 /* pci_power_off (pdev, -1); */
1808}
1809
1810#ifdef CONFIG_NET_POLL_CONTROLLER
1811/*
1812 * Polling 'interrupt' - used by things like netconsole to send skbs
1813 * without having to re-enable interrupts. It's not called while
1814 * the interrupt routine is executing.
1815 */
1816
1817static void poll_tulip (struct net_device *dev)
1818{
1819 /* disable_irq here is not very nice, but with the lockless
1820 interrupt handler we have no other choice. */
1821 disable_irq(dev->irq);
1822 tulip_interrupt (dev->irq, dev, NULL);
1823 enable_irq(dev->irq);
1824}
1825#endif
1826
1827static struct pci_driver tulip_driver = {
1828 .name = DRV_NAME,
1829 .id_table = tulip_pci_tbl,
1830 .probe = tulip_init_one,
1831 .remove = __devexit_p(tulip_remove_one),
1832#ifdef CONFIG_PM
1833 .suspend = tulip_suspend,
1834 .resume = tulip_resume,
1835#endif /* CONFIG_PM */
1836};
1837
1838
1839static int __init tulip_init (void)
1840{
1841#ifdef MODULE
1842 printk (KERN_INFO "%s", version);
1843#endif
1844
1845 /* copy module parms into globals */
1846 tulip_rx_copybreak = rx_copybreak;
1847 tulip_max_interrupt_work = max_interrupt_work;
1848
1849 /* probe for and init boards */
1850 return pci_module_init (&tulip_driver);
1851}
1852
1853
1854static void __exit tulip_cleanup (void)
1855{
1856 pci_unregister_driver (&tulip_driver);
1857}
1858
1859
1860module_init(tulip_init);
1861module_exit(tulip_cleanup);
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