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net: fix network drivers ndo_start_xmit() return values (part 8)
[mirror_ubuntu-bionic-kernel.git] / drivers / net / tulip / uli526x.c
CommitLineData
4689ced9
PC		 1/*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
f3b197ac 12
4689ced9
PC		 13*/
14
15#define DRV_NAME "uli526x"
16#define DRV_VERSION "0.9.3"
17#define DRV_RELDATE "2005-7-29"
18
19#include <linux/module.h>
20
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/timer.h>
4689ced9
PC		 24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/slab.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/skbuff.h>
34#include <linux/delay.h>
35#include <linux/spinlock.h>
6cafa99f 36#include <linux/dma-mapping.h>
1977f032 37#include <linux/bitops.h>
4689ced9
PC		 38
39#include <asm/processor.h>
4689ced9
PC		 40#include <asm/io.h>
41#include <asm/dma.h>
42#include <asm/uaccess.h>
43
44
45/* Board/System/Debug information/definition ---------------- */
46#define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47#define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
48
49#define ULI526X_IO_SIZE 0x100
50#define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51#define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55#define TX_BUF_ALLOC 0x600
56#define RX_ALLOC_SIZE 0x620
57#define ULI526X_RESET 1
58#define CR0_DEFAULT 0
945a7876 59#define CR6_DEFAULT 0x22200000
4689ced9
PC		 60#define CR7_DEFAULT 0x180c1
61#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63#define MAX_PACKET_SIZE 1514
64#define ULI5261_MAX_MULTICAST 14
65#define RX_COPY_SIZE 100
66#define MAX_CHECK_PACKET 0x8000
67
68#define ULI526X_10MHF 0
69#define ULI526X_100MHF 1
70#define ULI526X_10MFD 4
71#define ULI526X_100MFD 5
72#define ULI526X_AUTO 8
73
74#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
80
81#define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82#define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83#define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
84
85#define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
86
87#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
88
89
90/* CR9 definition: SROM/MII */
91#define CR9_SROM_READ 0x4800
92#define CR9_SRCS 0x1
93#define CR9_SRCLK 0x2
94#define CR9_CRDOUT 0x8
95#define SROM_DATA_0 0x0
96#define SROM_DATA_1 0x4
97#define PHY_DATA_1 0x20000
98#define PHY_DATA_0 0x00000
99#define MDCLKH 0x10000
100
101#define PHY_POWER_DOWN 0x800
102
103#define SROM_V41_CODE 0x14
104
945a7876
PC		 105#define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
107 udelay(5); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
109 udelay(5); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
111 udelay(5);
4689ced9
PC		 112
113/* Structure/enum declaration ------------------------------- */
114struct tx_desc {
c559a5bc 115 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
4689ced9
PC		 116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118} __attribute__(( aligned(32) ));
119
120struct rx_desc {
c559a5bc 121 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
4689ced9
PC		 122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124} __attribute__(( aligned(32) ));
125
126struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
945a7876 128 struct net_device *next_dev; /* next device */
4689ced9
PC		 129 struct pci_dev *pdev; /* PCI device */
130 spinlock_t lock;
131
132 long ioaddr; /* I/O base address */
133 u32 cr0_data;
134 u32 cr5_data;
135 u32 cr6_data;
136 u32 cr7_data;
137 u32 cr15_data;
138
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
145
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
159
160 u16 dbug_cnt;
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
163
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
166 u8 phy_addr;
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
170
4689ced9
PC		 171 /* Driver defined statistic counter */
172 unsigned long tx_fifo_underrun;
173 unsigned long tx_loss_carrier;
174 unsigned long tx_no_carrier;
175 unsigned long tx_late_collision;
176 unsigned long tx_excessive_collision;
177 unsigned long tx_jabber_timeout;
178 unsigned long reset_count;
179 unsigned long reset_cr8;
180 unsigned long reset_fatal;
181 unsigned long reset_TXtimeout;
182
183 /* NIC SROM data */
184 unsigned char srom[128];
f3b197ac 185 u8 init;
4689ced9
PC		 186};
187
188enum uli526x_offsets {
189 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
190 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
191 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
192 DCR15 = 0x78
193};
194
195enum uli526x_CR6_bits {
196 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
197 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
198 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
199};
200
201/* Global variable declaration ----------------------------- */
202static int __devinitdata printed_version;
03f54b3d 203static const char version[] __devinitconst =
4689ced9
PC		 204 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
205 DRV_VERSION " (" DRV_RELDATE ")\n";
206
207static int uli526x_debug;
208static unsigned char uli526x_media_mode = ULI526X_AUTO;
209static u32 uli526x_cr6_user_set;
210
211/* For module input parameter */
212static int debug;
213static u32 cr6set;
99bb2579 214static int mode = 8;
4689ced9
PC		 215
216/* function declaration ------------------------------------- */
945a7876
PC		 217static int uli526x_open(struct net_device *);
218static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
219static int uli526x_stop(struct net_device *);
945a7876 220static void uli526x_set_filter_mode(struct net_device *);
7282d491 221static const struct ethtool_ops netdev_ethtool_ops;
945a7876 222static u16 read_srom_word(long, int);
7d12e780 223static irqreturn_t uli526x_interrupt(int, void *);
7fa0cba3
AV		 224#ifdef CONFIG_NET_POLL_CONTROLLER
225static void uli526x_poll(struct net_device *dev);
226#endif
4689ced9
PC		 227static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
228static void allocate_rx_buffer(struct uli526x_board_info *);
229static void update_cr6(u32, unsigned long);
945a7876 230static void send_filter_frame(struct net_device *, int);
4689ced9
PC		 231static u16 phy_read(unsigned long, u8, u8, u32);
232static u16 phy_readby_cr10(unsigned long, u8, u8);
233static void phy_write(unsigned long, u8, u8, u16, u32);
234static void phy_writeby_cr10(unsigned long, u8, u8, u16);
235static void phy_write_1bit(unsigned long, u32, u32);
236static u16 phy_read_1bit(unsigned long, u32);
237static u8 uli526x_sense_speed(struct uli526x_board_info *);
238static void uli526x_process_mode(struct uli526x_board_info *);
239static void uli526x_timer(unsigned long);
945a7876
PC		 240static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
241static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
4689ced9 242static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
945a7876 243static void uli526x_dynamic_reset(struct net_device *);
4689ced9 244static void uli526x_free_rxbuffer(struct uli526x_board_info *);
945a7876 245static void uli526x_init(struct net_device *);
4689ced9
PC		 246static void uli526x_set_phyxcer(struct uli526x_board_info *);
247
945a7876 248/* ULI526X network board routine ---------------------------- */
4689ced9 249
dfefe02b
SH		 250static const struct net_device_ops netdev_ops = {
251 .ndo_open = uli526x_open,
252 .ndo_stop = uli526x_stop,
253 .ndo_start_xmit = uli526x_start_xmit,
254 .ndo_set_multicast_list = uli526x_set_filter_mode,
255 .ndo_change_mtu = eth_change_mtu,
256 .ndo_set_mac_address = eth_mac_addr,
257 .ndo_validate_addr = eth_validate_addr,
258#ifdef CONFIG_NET_POLL_CONTROLLER
259 .ndo_poll_controller = uli526x_poll,
260#endif
261};
262
4689ced9 263/*
945a7876 264 * Search ULI526X board, allocate space and register it
4689ced9
PC		 265 */
266
267static int __devinit uli526x_init_one (struct pci_dev *pdev,
268 const struct pci_device_id *ent)
269{
270 struct uli526x_board_info *db; /* board information structure */
271 struct net_device *dev;
272 int i, err;
f3b197ac 273
4689ced9
PC		 274 ULI526X_DBUG(0, "uli526x_init_one()", 0);
275
276 if (!printed_version++)
277 printk(version);
278
279 /* Init network device */
280 dev = alloc_etherdev(sizeof(*db));
281 if (dev == NULL)
282 return -ENOMEM;
4689ced9
PC		 283 SET_NETDEV_DEV(dev, &pdev->dev);
284
284901a9 285 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
4689ced9
PC		 286 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
287 err = -ENODEV;
288 goto err_out_free;
289 }
290
291 /* Enable Master/IO access, Disable memory access */
292 err = pci_enable_device(pdev);
293 if (err)
294 goto err_out_free;
295
296 if (!pci_resource_start(pdev, 0)) {
297 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
298 err = -ENODEV;
299 goto err_out_disable;
300 }
301
302 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
303 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
304 err = -ENODEV;
305 goto err_out_disable;
306 }
307
308 if (pci_request_regions(pdev, DRV_NAME)) {
309 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
310 err = -ENODEV;
311 goto err_out_disable;
312 }
313
4689ced9
PC		 314 /* Init system & device */
315 db = netdev_priv(dev);
316
317 /* Allocate Tx/Rx descriptor memory */
318 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
945a7876
PC		 319 if(db->desc_pool_ptr == NULL)
320 {
321 err = -ENOMEM;
322 goto err_out_nomem;
323 }
4689ced9 324 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
945a7876
PC		 325 if(db->buf_pool_ptr == NULL)
326 {
327 err = -ENOMEM;
328 goto err_out_nomem;
329 }
f3b197ac 330
4689ced9
PC		 331 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
332 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
333 db->buf_pool_start = db->buf_pool_ptr;
334 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
335
336 db->chip_id = ent->driver_data;
337 db->ioaddr = pci_resource_start(pdev, 0);
f3b197ac 338
4689ced9
PC		 339 db->pdev = pdev;
340 db->init = 1;
f3b197ac 341
4689ced9
PC		 342 dev->base_addr = db->ioaddr;
343 dev->irq = pdev->irq;
344 pci_set_drvdata(pdev, dev);
f3b197ac 345
4689ced9 346 /* Register some necessary functions */
dfefe02b 347 dev->netdev_ops = &netdev_ops;
4689ced9 348 dev->ethtool_ops = &netdev_ethtool_ops;
dfefe02b 349
4689ced9
PC		 350 spin_lock_init(&db->lock);
351
f3b197ac 352
4689ced9
PC		 353 /* read 64 word srom data */
354 for (i = 0; i < 64; i++)
c559a5bc 355 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
4689ced9
PC		 356
357 /* Set Node address */
945a7876 358 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
4689ced9
PC		 359 {
360 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
361 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
362 outl(0, db->ioaddr + DCR14); //Clear reset port
363 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
364 outl(0, db->ioaddr + DCR14); //Clear reset port
365 outl(0, db->ioaddr + DCR13); //Clear CR13
366 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
367 //Read MAC address from CR14
368 for (i = 0; i < 6; i++)
369 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
370 //Read end
371 outl(0, db->ioaddr + DCR13); //Clear CR13
372 outl(0, db->ioaddr + DCR0); //Clear CR0
373 udelay(10);
374 }
375 else /*Exist SROM*/
376 {
377 for (i = 0; i < 6; i++)
378 dev->dev_addr[i] = db->srom[20 + i];
379 }
380 err = register_netdev (dev);
381 if (err)
382 goto err_out_res;
383
e174961c 384 printk(KERN_INFO "%s: ULi M%04lx at pci%s, %pM, irq %d.\n",
0795af57 385 dev->name,ent->driver_data >> 16,pci_name(pdev),
e174961c 386 dev->dev_addr, dev->irq);
4689ced9
PC		 387
388 pci_set_master(pdev);
389
390 return 0;
391
392err_out_res:
393 pci_release_regions(pdev);
945a7876
PC		 394err_out_nomem:
395 if(db->desc_pool_ptr)
396 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
397 db->desc_pool_ptr, db->desc_pool_dma_ptr);
f3b197ac 398
945a7876
PC		 399 if(db->buf_pool_ptr != NULL)
400 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
401 db->buf_pool_ptr, db->buf_pool_dma_ptr);
4689ced9
PC		 402err_out_disable:
403 pci_disable_device(pdev);
404err_out_free:
405 pci_set_drvdata(pdev, NULL);
406 free_netdev(dev);
407
408 return err;
409}
410
411
412static void __devexit uli526x_remove_one (struct pci_dev *pdev)
413{
414 struct net_device *dev = pci_get_drvdata(pdev);
415 struct uli526x_board_info *db = netdev_priv(dev);
416
417 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
418
945a7876
PC		 419 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
420 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
421 db->desc_pool_dma_ptr);
422 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
423 db->buf_pool_ptr, db->buf_pool_dma_ptr);
424 unregister_netdev(dev);
425 pci_release_regions(pdev);
426 free_netdev(dev); /* free board information */
427 pci_set_drvdata(pdev, NULL);
428 pci_disable_device(pdev);
4689ced9
PC		 429 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
430}
431
432
433/*
434 * Open the interface.
945a7876 435 * The interface is opened whenever "ifconfig" activates it.
4689ced9
PC		 436 */
437
945a7876 438static int uli526x_open(struct net_device *dev)
4689ced9
PC		 439{
440 int ret;
441 struct uli526x_board_info *db = netdev_priv(dev);
f3b197ac 442
4689ced9
PC		 443 ULI526X_DBUG(0, "uli526x_open", 0);
444
4689ced9
PC		 445 /* system variable init */
446 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
4689ced9
PC		 447 db->tx_packet_cnt = 0;
448 db->rx_avail_cnt = 0;
449 db->link_failed = 1;
450 netif_carrier_off(dev);
451 db->wait_reset = 0;
452
453 db->NIC_capability = 0xf; /* All capability*/
454 db->PHY_reg4 = 0x1e0;
455
456 /* CR6 operation mode decision */
457 db->cr6_data |= ULI526X_TXTH_256;
458 db->cr0_data = CR0_DEFAULT;
f3b197ac 459
945a7876 460 /* Initialize ULI526X board */
4689ced9
PC		 461 uli526x_init(dev);
462
afd8e399
AV		 463 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
464 if (ret)
465 return ret;
466
4689ced9
PC		 467 /* Active System Interface */
468 netif_wake_queue(dev);
469
470 /* set and active a timer process */
471 init_timer(&db->timer);
472 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
473 db->timer.data = (unsigned long)dev;
474 db->timer.function = &uli526x_timer;
475 add_timer(&db->timer);
476
477 return 0;
478}
479
480
945a7876 481/* Initialize ULI526X board
4689ced9 482 * Reset ULI526X board
945a7876 483 * Initialize TX/Rx descriptor chain structure
4689ced9
PC		 484 * Send the set-up frame
485 * Enable Tx/Rx machine
486 */
487
945a7876 488static void uli526x_init(struct net_device *dev)
4689ced9
PC		 489{
490 struct uli526x_board_info *db = netdev_priv(dev);
491 unsigned long ioaddr = db->ioaddr;
492 u8 phy_tmp;
7a7d23da 493 u8 timeout;
4689ced9
PC		 494 u16 phy_value;
495 u16 phy_reg_reset;
496
7a7d23da 497
4689ced9
PC		 498 ULI526X_DBUG(0, "uli526x_init()", 0);
499
500 /* Reset M526x MAC controller */
501 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
502 udelay(100);
503 outl(db->cr0_data, ioaddr + DCR0);
504 udelay(5);
505
506 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
507 db->phy_addr = 1;
508 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
509 {
510 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
511 if(phy_value != 0xffff&&phy_value!=0)
512 {
513 db->phy_addr = phy_tmp;
514 break;
515 }
516 }
517 if(phy_tmp == 32)
518 printk(KERN_WARNING "Can not find the phy address!!!");
519 /* Parser SROM and media mode */
520 db->media_mode = uli526x_media_mode;
521
7a7d23da 522 /* phyxcer capability setting */
4689ced9
PC		 523 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
524 phy_reg_reset = (phy_reg_reset | 0x8000);
525 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
7a7d23da
GG		 526
527 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
528 * functions") or phy data sheet for details on phy reset
529 */
4689ced9 530 udelay(500);
7a7d23da
GG		 531 timeout = 10;
532 while (timeout-- &&
533 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
534 udelay(100);
4689ced9
PC		 535
536 /* Process Phyxcer Media Mode */
537 uli526x_set_phyxcer(db);
538
539 /* Media Mode Process */
540 if ( !(db->media_mode & ULI526X_AUTO) )
541 db->op_mode = db->media_mode; /* Force Mode */
542
945a7876 543 /* Initialize Transmit/Receive decriptor and CR3/4 */
4689ced9
PC		 544 uli526x_descriptor_init(db, ioaddr);
545
546 /* Init CR6 to program M526X operation */
547 update_cr6(db->cr6_data, ioaddr);
548
549 /* Send setup frame */
550 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
551
552 /* Init CR7, interrupt active bit */
553 db->cr7_data = CR7_DEFAULT;
554 outl(db->cr7_data, ioaddr + DCR7);
555
556 /* Init CR15, Tx jabber and Rx watchdog timer */
557 outl(db->cr15_data, ioaddr + DCR15);
558
559 /* Enable ULI526X Tx/Rx function */
560 db->cr6_data |= CR6_RXSC | CR6_TXSC;
561 update_cr6(db->cr6_data, ioaddr);
562}
563
564
565/*
566 * Hardware start transmission.
567 * Send a packet to media from the upper layer.
568 */
569
945a7876 570static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
4689ced9
PC		 571{
572 struct uli526x_board_info *db = netdev_priv(dev);
573 struct tx_desc *txptr;
574 unsigned long flags;
575
576 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
577
578 /* Resource flag check */
579 netif_stop_queue(dev);
580
581 /* Too large packet check */
582 if (skb->len > MAX_PACKET_SIZE) {
583 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
584 dev_kfree_skb(skb);
585 return 0;
586 }
587
588 spin_lock_irqsave(&db->lock, flags);
589
590 /* No Tx resource check, it never happen nromally */
591 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
592 spin_unlock_irqrestore(&db->lock, flags);
593 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
594 return 1;
595 }
596
597 /* Disable NIC interrupt */
598 outl(0, dev->base_addr + DCR7);
599
600 /* transmit this packet */
601 txptr = db->tx_insert_ptr;
d626f62b 602 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
4689ced9
PC		 603 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
604
605 /* Point to next transmit free descriptor */
606 db->tx_insert_ptr = txptr->next_tx_desc;
607
608 /* Transmit Packet Process */
609 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
610 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
611 db->tx_packet_cnt++; /* Ready to send */
612 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
613 dev->trans_start = jiffies; /* saved time stamp */
614 }
615
616 /* Tx resource check */
617 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
618 netif_wake_queue(dev);
619
620 /* Restore CR7 to enable interrupt */
621 spin_unlock_irqrestore(&db->lock, flags);
622 outl(db->cr7_data, dev->base_addr + DCR7);
f3b197ac 623
4689ced9
PC		 624 /* free this SKB */
625 dev_kfree_skb(skb);
626
627 return 0;
628}
629
630
631/*
632 * Stop the interface.
633 * The interface is stopped when it is brought.
634 */
635
945a7876 636static int uli526x_stop(struct net_device *dev)
4689ced9
PC		 637{
638 struct uli526x_board_info *db = netdev_priv(dev);
639 unsigned long ioaddr = dev->base_addr;
640
641 ULI526X_DBUG(0, "uli526x_stop", 0);
642
643 /* disable system */
644 netif_stop_queue(dev);
645
646 /* deleted timer */
647 del_timer_sync(&db->timer);
648
649 /* Reset & stop ULI526X board */
650 outl(ULI526X_RESET, ioaddr + DCR0);
651 udelay(5);
652 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
653
654 /* free interrupt */
655 free_irq(dev->irq, dev);
656
657 /* free allocated rx buffer */
658 uli526x_free_rxbuffer(db);
659
660#if 0
661 /* show statistic counter */
662 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
663 db->tx_fifo_underrun, db->tx_excessive_collision,
664 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
665 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
666 db->reset_fatal, db->reset_TXtimeout);
667#endif
668
669 return 0;
670}
671
672
673/*
674 * M5261/M5263 insterrupt handler
675 * receive the packet to upper layer, free the transmitted packet
676 */
677
7d12e780 678static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
4689ced9 679{
945a7876 680 struct net_device *dev = dev_id;
4689ced9
PC		 681 struct uli526x_board_info *db = netdev_priv(dev);
682 unsigned long ioaddr = dev->base_addr;
683 unsigned long flags;
684
4689ced9
PC		 685 spin_lock_irqsave(&db->lock, flags);
686 outl(0, ioaddr + DCR7);
687
688 /* Got ULI526X status */
689 db->cr5_data = inl(ioaddr + DCR5);
690 outl(db->cr5_data, ioaddr + DCR5);
691 if ( !(db->cr5_data & 0x180c1) ) {
7fa0cba3 692 /* Restore CR7 to enable interrupt mask */
4689ced9 693 outl(db->cr7_data, ioaddr + DCR7);
7fa0cba3 694 spin_unlock_irqrestore(&db->lock, flags);
4689ced9
PC		 695 return IRQ_HANDLED;
696 }
697
4689ced9
PC		 698 /* Check system status */
699 if (db->cr5_data & 0x2000) {
700 /* system bus error happen */
701 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
702 db->reset_fatal++;
703 db->wait_reset = 1; /* Need to RESET */
704 spin_unlock_irqrestore(&db->lock, flags);
705 return IRQ_HANDLED;
706 }
707
708 /* Received the coming packet */
709 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
710 uli526x_rx_packet(dev, db);
711
712 /* reallocate rx descriptor buffer */
713 if (db->rx_avail_cnt<RX_DESC_CNT)
714 allocate_rx_buffer(db);
715
716 /* Free the transmitted descriptor */
717 if ( db->cr5_data & 0x01)
718 uli526x_free_tx_pkt(dev, db);
719
720 /* Restore CR7 to enable interrupt mask */
721 outl(db->cr7_data, ioaddr + DCR7);
722
723 spin_unlock_irqrestore(&db->lock, flags);
724 return IRQ_HANDLED;
725}
726
7fa0cba3
AV		 727#ifdef CONFIG_NET_POLL_CONTROLLER
728static void uli526x_poll(struct net_device *dev)
729{
730 /* ISR grabs the irqsave lock, so this should be safe */
731 uli526x_interrupt(dev->irq, dev);
732}
733#endif
4689ced9
PC		 734
735/*
736 * Free TX resource after TX complete
737 */
738
dfefe02b
SH		 739static void uli526x_free_tx_pkt(struct net_device *dev,
740 struct uli526x_board_info * db)
4689ced9
PC		 741{
742 struct tx_desc *txptr;
4689ced9
PC		 743 u32 tdes0;
744
745 txptr = db->tx_remove_ptr;
746 while(db->tx_packet_cnt) {
747 tdes0 = le32_to_cpu(txptr->tdes0);
748 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
749 if (tdes0 & 0x80000000)
750 break;
751
752 /* A packet sent completed */
753 db->tx_packet_cnt--;
dfefe02b 754 dev->stats.tx_packets++;
4689ced9
PC		 755
756 /* Transmit statistic counter */
757 if ( tdes0 != 0x7fffffff ) {
758 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
dfefe02b
SH		 759 dev->stats.collisions += (tdes0 >> 3) & 0xf;
760 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
4689ced9 761 if (tdes0 & TDES0_ERR_MASK) {
dfefe02b 762 dev->stats.tx_errors++;
4689ced9
PC		 763 if (tdes0 & 0x0002) { /* UnderRun */
764 db->tx_fifo_underrun++;
765 if ( !(db->cr6_data & CR6_SFT) ) {
766 db->cr6_data = db->cr6_data | CR6_SFT;
767 update_cr6(db->cr6_data, db->ioaddr);
768 }
769 }
770 if (tdes0 & 0x0100)
771 db->tx_excessive_collision++;
772 if (tdes0 & 0x0200)
773 db->tx_late_collision++;
774 if (tdes0 & 0x0400)
775 db->tx_no_carrier++;
776 if (tdes0 & 0x0800)
777 db->tx_loss_carrier++;
778 if (tdes0 & 0x4000)
779 db->tx_jabber_timeout++;
780 }
781 }
782
783 txptr = txptr->next_tx_desc;
784 }/* End of while */
785
786 /* Update TX remove pointer to next */
787 db->tx_remove_ptr = txptr;
788
789 /* Resource available check */
790 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
791 netif_wake_queue(dev); /* Active upper layer, send again */
792}
793
794
795/*
796 * Receive the come packet and pass to upper layer
797 */
798
945a7876 799static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 800{
801 struct rx_desc *rxptr;
802 struct sk_buff *skb;
803 int rxlen;
804 u32 rdes0;
f3b197ac 805
4689ced9
PC		 806 rxptr = db->rx_ready_ptr;
807
808 while(db->rx_avail_cnt) {
809 rdes0 = le32_to_cpu(rxptr->rdes0);
810 if (rdes0 & 0x80000000) /* packet owner check */
811 {
812 break;
813 }
814
815 db->rx_avail_cnt--;
816 db->interval_rx_cnt++;
817
818 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
819 if ( (rdes0 & 0x300) != 0x300) {
820 /* A packet without First/Last flag */
821 /* reuse this SKB */
822 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
823 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
824 } else {
825 /* A packet with First/Last flag */
826 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
827
828 /* error summary bit check */
829 if (rdes0 & 0x8000) {
830 /* This is a error packet */
831 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
dfefe02b 832 dev->stats.rx_errors++;
4689ced9 833 if (rdes0 & 1)
dfefe02b 834 dev->stats.rx_fifo_errors++;
4689ced9 835 if (rdes0 & 2)
dfefe02b 836 dev->stats.rx_crc_errors++;
4689ced9 837 if (rdes0 & 0x80)
dfefe02b 838 dev->stats.rx_length_errors++;
4689ced9
PC		 839 }
840
841 if ( !(rdes0 & 0x8000) ||
842 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
843 skb = rxptr->rx_skb_ptr;
f3b197ac 844
4689ced9
PC		 845 /* Good packet, send to upper layer */
846 /* Shorst packet used new SKB */
847 if ( (rxlen < RX_COPY_SIZE) &&
848 ( (skb = dev_alloc_skb(rxlen + 2) )
849 != NULL) ) {
850 /* size less than COPY_SIZE, allocate a rxlen SKB */
4689ced9 851 skb_reserve(skb, 2); /* 16byte align */
27a884dc
ACM		 852 memcpy(skb_put(skb, rxlen),
853 skb_tail_pointer(rxptr->rx_skb_ptr),
854 rxlen);
4689ced9 855 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 856 } else
4689ced9 857 skb_put(skb, rxlen);
4c13eb66 858
4689ced9
PC		 859 skb->protocol = eth_type_trans(skb, dev);
860 netif_rx(skb);
dfefe02b
SH		 861 dev->stats.rx_packets++;
862 dev->stats.rx_bytes += rxlen;
f3b197ac 863
4689ced9
PC		 864 } else {
865 /* Reuse SKB buffer when the packet is error */
866 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
867 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
868 }
869 }
870
871 rxptr = rxptr->next_rx_desc;
872 }
873
874 db->rx_ready_ptr = rxptr;
875}
876
877
4689ced9
PC		 878/*
879 * Set ULI526X multicast address
880 */
881
945a7876 882static void uli526x_set_filter_mode(struct net_device * dev)
4689ced9 883{
8f15ea42 884 struct uli526x_board_info *db = netdev_priv(dev);
4689ced9
PC		 885 unsigned long flags;
886
887 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
888 spin_lock_irqsave(&db->lock, flags);
889
890 if (dev->flags & IFF_PROMISC) {
891 ULI526X_DBUG(0, "Enable PROM Mode", 0);
892 db->cr6_data |= CR6_PM | CR6_PBF;
893 update_cr6(db->cr6_data, db->ioaddr);
894 spin_unlock_irqrestore(&db->lock, flags);
895 return;
896 }
897
898 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
899 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
900 db->cr6_data &= ~(CR6_PM | CR6_PBF);
901 db->cr6_data |= CR6_PAM;
902 spin_unlock_irqrestore(&db->lock, flags);
903 return;
904 }
905
906 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
907 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
908 spin_unlock_irqrestore(&db->lock, flags);
909}
910
911static void
912ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
913{
945a7876
PC		 914 ecmd->supported = (SUPPORTED_10baseT_Half |
915 SUPPORTED_10baseT_Full |
916 SUPPORTED_100baseT_Half |
917 SUPPORTED_100baseT_Full |
918 SUPPORTED_Autoneg |
919 SUPPORTED_MII);
f3b197ac 920
945a7876
PC		 921 ecmd->advertising = (ADVERTISED_10baseT_Half |
922 ADVERTISED_10baseT_Full |
923 ADVERTISED_100baseT_Half |
924 ADVERTISED_100baseT_Full |
925 ADVERTISED_Autoneg |
926 ADVERTISED_MII);
4689ced9
PC		 927
928
945a7876
PC		 929 ecmd->port = PORT_MII;
930 ecmd->phy_address = db->phy_addr;
4689ced9 931
945a7876 932 ecmd->transceiver = XCVR_EXTERNAL;
f3b197ac 933
4689ced9
PC		 934 ecmd->speed = 10;
935 ecmd->duplex = DUPLEX_HALF;
f3b197ac 936
4689ced9
PC		 937 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
938 {
f3b197ac 939 ecmd->speed = 100;
4689ced9
PC		 940 }
941 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
942 {
943 ecmd->duplex = DUPLEX_FULL;
944 }
945 if(db->link_failed)
946 {
947 ecmd->speed = -1;
f3b197ac 948 ecmd->duplex = -1;
4689ced9 949 }
f3b197ac 950
4689ced9 951 if (db->media_mode & ULI526X_AUTO)
f3b197ac 952 {
4689ced9
PC		 953 ecmd->autoneg = AUTONEG_ENABLE;
954 }
4689ced9
PC		 955}
956
957static void netdev_get_drvinfo(struct net_device *dev,
958 struct ethtool_drvinfo *info)
959{
960 struct uli526x_board_info *np = netdev_priv(dev);
961
962 strcpy(info->driver, DRV_NAME);
963 strcpy(info->version, DRV_VERSION);
964 if (np->pdev)
965 strcpy(info->bus_info, pci_name(np->pdev));
966 else
967 sprintf(info->bus_info, "EISA 0x%lx %d",
968 dev->base_addr, dev->irq);
969}
970
971static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
972 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 973
4689ced9 974 ULi_ethtool_gset(np, cmd);
f3b197ac 975
4689ced9
PC		 976 return 0;
977}
978
979static u32 netdev_get_link(struct net_device *dev) {
980 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 981
4689ced9
PC		 982 if(np->link_failed)
983 return 0;
984 else
985 return 1;
986}
987
988static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
989{
990 wol->supported = WAKE_PHY | WAKE_MAGIC;
991 wol->wolopts = 0;
992}
993
7282d491 994static const struct ethtool_ops netdev_ethtool_ops = {
4689ced9
PC		 995 .get_drvinfo = netdev_get_drvinfo,
996 .get_settings = netdev_get_settings,
997 .get_link = netdev_get_link,
998 .get_wol = uli526x_get_wol,
999};
1000
1001/*
1002 * A periodic timer routine
1003 * Dynamic media sense, allocate Rx buffer...
1004 */
1005
1006static void uli526x_timer(unsigned long data)
1007{
1008 u32 tmp_cr8;
1009 unsigned char tmp_cr12=0;
945a7876 1010 struct net_device *dev = (struct net_device *) data;
4689ced9
PC		 1011 struct uli526x_board_info *db = netdev_priv(dev);
1012 unsigned long flags;
1013 u8 TmpSpeed=10;
f3b197ac 1014
4689ced9
PC		 1015 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1016 spin_lock_irqsave(&db->lock, flags);
1017
f3b197ac 1018
4689ced9
PC		 1019 /* Dynamic reset ULI526X : system error or transmit time-out */
1020 tmp_cr8 = inl(db->ioaddr + DCR8);
1021 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1022 db->reset_cr8++;
1023 db->wait_reset = 1;
1024 }
1025 db->interval_rx_cnt = 0;
1026
1027 /* TX polling kick monitor */
1028 if ( db->tx_packet_cnt &&
1029 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
f3b197ac 1030 outl(0x1, dev->base_addr + DCR1); // Tx polling again
4689ced9 1031
f3b197ac 1032 // TX Timeout
4689ced9
PC		 1033 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1034 db->reset_TXtimeout++;
1035 db->wait_reset = 1;
1036 printk( "%s: Tx timeout - resetting\n",
1037 dev->name);
1038 }
1039 }
1040
1041 if (db->wait_reset) {
1042 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1043 db->reset_count++;
1044 uli526x_dynamic_reset(dev);
1045 db->timer.expires = ULI526X_TIMER_WUT;
1046 add_timer(&db->timer);
1047 spin_unlock_irqrestore(&db->lock, flags);
1048 return;
1049 }
1050
1051 /* Link status check, Dynamic media type change */
1052 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1053 tmp_cr12 = 3;
1054
1055 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1056 /* Link Failed */
1057 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1058 netif_carrier_off(dev);
1059 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1060 db->link_failed = 1;
1061
1062 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1063 /* AUTO don't need */
1064 if ( !(db->media_mode & 0x8) )
1065 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1066
1067 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1068 if (db->media_mode & ULI526X_AUTO) {
1069 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1070 update_cr6(db->cr6_data, db->ioaddr);
1071 }
1072 } else
1073 if ((tmp_cr12 & 0x3) && db->link_failed) {
1074 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1075 db->link_failed = 0;
1076
1077 /* Auto Sense Speed */
1078 if ( (db->media_mode & ULI526X_AUTO) &&
1079 uli526x_sense_speed(db) )
1080 db->link_failed = 1;
1081 uli526x_process_mode(db);
f3b197ac 1082
4689ced9
PC		 1083 if(db->link_failed==0)
1084 {
1085 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1086 {
1087 TmpSpeed = 100;
1088 }
1089 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1090 {
1091 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1092 }
1093 else
1094 {
1095 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1096 }
1097 netif_carrier_on(dev);
1098 }
1099 /* SHOW_MEDIA_TYPE(db->op_mode); */
1100 }
1101 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1102 {
1103 if(db->init==1)
1104 {
1105 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1106 netif_carrier_off(dev);
1107 }
1108 }
1109 db->init=0;
1110
1111 /* Timer active again */
1112 db->timer.expires = ULI526X_TIMER_WUT;
1113 add_timer(&db->timer);
1114 spin_unlock_irqrestore(&db->lock, flags);
1115}
1116
1117
1118/*
4689ced9
PC		 1119 * Stop ULI526X board
1120 * Free Tx/Rx allocated memory
b6aec32a 1121 * Init system variable
4689ced9
PC		 1122 */
1123
b6aec32a 1124static void uli526x_reset_prepare(struct net_device *dev)
4689ced9
PC		 1125{
1126 struct uli526x_board_info *db = netdev_priv(dev);
1127
4689ced9
PC		 1128 /* Sopt MAC controller */
1129 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1130 update_cr6(db->cr6_data, dev->base_addr);
1131 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1132 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1133
1134 /* Disable upper layer interface */
1135 netif_stop_queue(dev);
1136
1137 /* Free Rx Allocate buffer */
1138 uli526x_free_rxbuffer(db);
1139
1140 /* system variable init */
1141 db->tx_packet_cnt = 0;
1142 db->rx_avail_cnt = 0;
1143 db->link_failed = 1;
1144 db->init=1;
1145 db->wait_reset = 0;
b6aec32a
RW		 1146}
1147
1148
1149/*
1150 * Dynamic reset the ULI526X board
1151 * Stop ULI526X board
1152 * Free Tx/Rx allocated memory
1153 * Reset ULI526X board
1154 * Re-initialize ULI526X board
1155 */
1156
1157static void uli526x_dynamic_reset(struct net_device *dev)
1158{
1159 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1160
1161 uli526x_reset_prepare(dev);
4689ced9 1162
945a7876 1163 /* Re-initialize ULI526X board */
4689ced9
PC		 1164 uli526x_init(dev);
1165
1166 /* Restart upper layer interface */
1167 netif_wake_queue(dev);
1168}
1169
1170
b6aec32a
RW		 1171#ifdef CONFIG_PM
1172
1173/*
1174 * Suspend the interface.
1175 */
1176
1177static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1178{
1179 struct net_device *dev = pci_get_drvdata(pdev);
1180 pci_power_t power_state;
1181 int err;
1182
1183 ULI526X_DBUG(0, "uli526x_suspend", 0);
1184
1185 if (!netdev_priv(dev))
1186 return 0;
1187
1188 pci_save_state(pdev);
1189
1190 if (!netif_running(dev))
1191 return 0;
1192
1193 netif_device_detach(dev);
1194 uli526x_reset_prepare(dev);
1195
1196 power_state = pci_choose_state(pdev, state);
1197 pci_enable_wake(pdev, power_state, 0);
1198 err = pci_set_power_state(pdev, power_state);
1199 if (err) {
1200 netif_device_attach(dev);
1201 /* Re-initialize ULI526X board */
1202 uli526x_init(dev);
1203 /* Restart upper layer interface */
1204 netif_wake_queue(dev);
1205 }
1206
1207 return err;
1208}
1209
1210/*
1211 * Resume the interface.
1212 */
1213
1214static int uli526x_resume(struct pci_dev *pdev)
1215{
1216 struct net_device *dev = pci_get_drvdata(pdev);
1217 int err;
1218
1219 ULI526X_DBUG(0, "uli526x_resume", 0);
1220
1221 if (!netdev_priv(dev))
1222 return 0;
1223
1224 pci_restore_state(pdev);
1225
1226 if (!netif_running(dev))
1227 return 0;
1228
1229 err = pci_set_power_state(pdev, PCI_D0);
1230 if (err) {
1231 printk(KERN_WARNING "%s: Could not put device into D0\n",
1232 dev->name);
1233 return err;
1234 }
1235
1236 netif_device_attach(dev);
1237 /* Re-initialize ULI526X board */
1238 uli526x_init(dev);
1239 /* Restart upper layer interface */
1240 netif_wake_queue(dev);
1241
1242 return 0;
1243}
1244
1245#else /* !CONFIG_PM */
1246
1247#define uli526x_suspend NULL
1248#define uli526x_resume NULL
1249
1250#endif /* !CONFIG_PM */
1251
1252
4689ced9
PC		 1253/*
1254 * free all allocated rx buffer
1255 */
1256
1257static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1258{
1259 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1260
1261 /* free allocated rx buffer */
1262 while (db->rx_avail_cnt) {
1263 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1264 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1265 db->rx_avail_cnt--;
1266 }
1267}
1268
1269
1270/*
1271 * Reuse the SK buffer
1272 */
1273
1274static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1275{
1276 struct rx_desc *rxptr = db->rx_insert_ptr;
1277
1278 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1279 rxptr->rx_skb_ptr = skb;
27a884dc
ACM		 1280 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1281 skb_tail_pointer(skb),
1282 RX_ALLOC_SIZE,
1283 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1284 wmb();
1285 rxptr->rdes0 = cpu_to_le32(0x80000000);
1286 db->rx_avail_cnt++;
1287 db->rx_insert_ptr = rxptr->next_rx_desc;
1288 } else
1289 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1290}
1291
1292
1293/*
1294 * Initialize transmit/Receive descriptor
1295 * Using Chain structure, and allocate Tx/Rx buffer
1296 */
1297
1298static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1299{
1300 struct tx_desc *tmp_tx;
1301 struct rx_desc *tmp_rx;
1302 unsigned char *tmp_buf;
1303 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1304 dma_addr_t tmp_buf_dma;
1305 int i;
1306
1307 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1308
1309 /* tx descriptor start pointer */
1310 db->tx_insert_ptr = db->first_tx_desc;
1311 db->tx_remove_ptr = db->first_tx_desc;
1312 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1313
1314 /* rx descriptor start pointer */
1315 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1316 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1317 db->rx_insert_ptr = db->first_rx_desc;
1318 db->rx_ready_ptr = db->first_rx_desc;
1319 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1320
1321 /* Init Transmit chain */
1322 tmp_buf = db->buf_pool_start;
1323 tmp_buf_dma = db->buf_pool_dma_start;
1324 tmp_tx_dma = db->first_tx_desc_dma;
1325 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1326 tmp_tx->tx_buf_ptr = tmp_buf;
1327 tmp_tx->tdes0 = cpu_to_le32(0);
1328 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1329 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1330 tmp_tx_dma += sizeof(struct tx_desc);
1331 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1332 tmp_tx->next_tx_desc = tmp_tx + 1;
1333 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1334 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1335 }
1336 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1337 tmp_tx->next_tx_desc = db->first_tx_desc;
1338
1339 /* Init Receive descriptor chain */
1340 tmp_rx_dma=db->first_rx_desc_dma;
1341 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1342 tmp_rx->rdes0 = cpu_to_le32(0);
1343 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1344 tmp_rx_dma += sizeof(struct rx_desc);
1345 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1346 tmp_rx->next_rx_desc = tmp_rx + 1;
1347 }
1348 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1349 tmp_rx->next_rx_desc = db->first_rx_desc;
1350
1351 /* pre-allocate Rx buffer */
1352 allocate_rx_buffer(db);
1353}
1354
1355
1356/*
1357 * Update CR6 value
945a7876 1358 * Firstly stop ULI526X, then written value and start
4689ced9
PC		 1359 */
1360
1361static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1362{
1363
1364 outl(cr6_data, ioaddr + DCR6);
1365 udelay(5);
1366}
1367
1368
1369/*
1370 * Send a setup frame for M5261/M5263
945a7876 1371 * This setup frame initialize ULI526X address filter mode
4689ced9
PC		 1372 */
1373
e284e5c6
AV		 1374#ifdef __BIG_ENDIAN
1375#define FLT_SHIFT 16
1376#else
1377#define FLT_SHIFT 0
1378#endif
1379
945a7876 1380static void send_filter_frame(struct net_device *dev, int mc_cnt)
4689ced9
PC		 1381{
1382 struct uli526x_board_info *db = netdev_priv(dev);
1383 struct dev_mc_list *mcptr;
1384 struct tx_desc *txptr;
1385 u16 * addrptr;
1386 u32 * suptr;
1387 int i;
1388
1389 ULI526X_DBUG(0, "send_filter_frame()", 0);
1390
1391 txptr = db->tx_insert_ptr;
1392 suptr = (u32 *) txptr->tx_buf_ptr;
1393
1394 /* Node address */
1395 addrptr = (u16 *) dev->dev_addr;
e284e5c6
AV		 1396 *suptr++ = addrptr[0] << FLT_SHIFT;
1397 *suptr++ = addrptr[1] << FLT_SHIFT;
1398 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1399
1400 /* broadcast address */
e284e5c6
AV		 1401 *suptr++ = 0xffff << FLT_SHIFT;
1402 *suptr++ = 0xffff << FLT_SHIFT;
1403 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1404
1405 /* fit the multicast address */
1406 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1407 addrptr = (u16 *) mcptr->dmi_addr;
e284e5c6
AV		 1408 *suptr++ = addrptr[0] << FLT_SHIFT;
1409 *suptr++ = addrptr[1] << FLT_SHIFT;
1410 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1411 }
1412
1413 for (; i<14; i++) {
e284e5c6
AV		 1414 *suptr++ = 0xffff << FLT_SHIFT;
1415 *suptr++ = 0xffff << FLT_SHIFT;
1416 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1417 }
1418
1419 /* prepare the setup frame */
1420 db->tx_insert_ptr = txptr->next_tx_desc;
1421 txptr->tdes1 = cpu_to_le32(0x890000c0);
1422
1423 /* Resource Check and Send the setup packet */
1424 if (db->tx_packet_cnt < TX_DESC_CNT) {
1425 /* Resource Empty */
1426 db->tx_packet_cnt++;
1427 txptr->tdes0 = cpu_to_le32(0x80000000);
1428 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1429 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1430 update_cr6(db->cr6_data, dev->base_addr);
1431 dev->trans_start = jiffies;
1432 } else
1433 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1434}
1435
1436
1437/*
1438 * Allocate rx buffer,
1439 * As possible as allocate maxiumn Rx buffer
1440 */
1441
1442static void allocate_rx_buffer(struct uli526x_board_info *db)
1443{
1444 struct rx_desc *rxptr;
1445 struct sk_buff *skb;
1446
1447 rxptr = db->rx_insert_ptr;
1448
1449 while(db->rx_avail_cnt < RX_DESC_CNT) {
1450 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1451 break;
1452 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
27a884dc
ACM		 1453 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1454 skb_tail_pointer(skb),
1455 RX_ALLOC_SIZE,
1456 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1457 wmb();
1458 rxptr->rdes0 = cpu_to_le32(0x80000000);
1459 rxptr = rxptr->next_rx_desc;
1460 db->rx_avail_cnt++;
1461 }
1462
1463 db->rx_insert_ptr = rxptr;
1464}
1465
1466
1467/*
1468 * Read one word data from the serial ROM
1469 */
1470
1471static u16 read_srom_word(long ioaddr, int offset)
1472{
1473 int i;
1474 u16 srom_data = 0;
1475 long cr9_ioaddr = ioaddr + DCR9;
1476
1477 outl(CR9_SROM_READ, cr9_ioaddr);
1478 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1479
1480 /* Send the Read Command 110b */
1481 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1482 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1483 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1484
1485 /* Send the offset */
1486 for (i = 5; i >= 0; i--) {
1487 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1488 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1489 }
1490
1491 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1492
1493 for (i = 16; i > 0; i--) {
1494 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1495 udelay(5);
1496 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1497 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1498 udelay(5);
1499 }
1500
1501 outl(CR9_SROM_READ, cr9_ioaddr);
1502 return srom_data;
1503}
1504
1505
1506/*
1507 * Auto sense the media mode
1508 */
1509
1510static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1511{
1512 u8 ErrFlag = 0;
1513 u16 phy_mode;
1514
1515 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1516 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1517
1518 if ( (phy_mode & 0x24) == 0x24 ) {
f3b197ac 1519
4689ced9
PC		 1520 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1521 if(phy_mode&0x8000)
1522 phy_mode = 0x8000;
1523 else if(phy_mode&0x4000)
1524 phy_mode = 0x4000;
1525 else if(phy_mode&0x2000)
1526 phy_mode = 0x2000;
1527 else
1528 phy_mode = 0x1000;
f3b197ac 1529
4689ced9
PC		 1530 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1531 switch (phy_mode) {
1532 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1533 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1534 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1535 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1536 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1537 }
1538 } else {
1539 db->op_mode = ULI526X_10MHF;
1540 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1541 ErrFlag = 1;
1542 }
1543
1544 return ErrFlag;
1545}
1546
1547
1548/*
1549 * Set 10/100 phyxcer capability
1550 * AUTO mode : phyxcer register4 is NIC capability
1551 * Force mode: phyxcer register4 is the force media
1552 */
1553
1554static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1555{
1556 u16 phy_reg;
f3b197ac 1557
4689ced9
PC		 1558 /* Phyxcer capability setting */
1559 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1560
1561 if (db->media_mode & ULI526X_AUTO) {
1562 /* AUTO Mode */
1563 phy_reg |= db->PHY_reg4;
1564 } else {
1565 /* Force Mode */
1566 switch(db->media_mode) {
1567 case ULI526X_10MHF: phy_reg |= 0x20; break;
1568 case ULI526X_10MFD: phy_reg |= 0x40; break;
1569 case ULI526X_100MHF: phy_reg |= 0x80; break;
1570 case ULI526X_100MFD: phy_reg |= 0x100; break;
1571 }
f3b197ac 1572
4689ced9
PC		 1573 }
1574
1575 /* Write new capability to Phyxcer Reg4 */
1576 if ( !(phy_reg & 0x01e0)) {
1577 phy_reg|=db->PHY_reg4;
1578 db->media_mode|=ULI526X_AUTO;
1579 }
1580 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1581
1582 /* Restart Auto-Negotiation */
1583 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1584 udelay(50);
1585}
1586
1587
1588/*
1589 * Process op-mode
1590 AUTO mode : PHY controller in Auto-negotiation Mode
1591 * Force mode: PHY controller in force mode with HUB
1592 * N-way force capability with SWITCH
1593 */
1594
1595static void uli526x_process_mode(struct uli526x_board_info *db)
1596{
1597 u16 phy_reg;
1598
1599 /* Full Duplex Mode Check */
1600 if (db->op_mode & 0x4)
1601 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1602 else
1603 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1604
1605 update_cr6(db->cr6_data, db->ioaddr);
1606
1607 /* 10/100M phyxcer force mode need */
1608 if ( !(db->media_mode & 0x8)) {
1609 /* Forece Mode */
1610 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1611 if ( !(phy_reg & 0x1) ) {
1612 /* parter without N-Way capability */
1613 phy_reg = 0x0;
1614 switch(db->op_mode) {
1615 case ULI526X_10MHF: phy_reg = 0x0; break;
1616 case ULI526X_10MFD: phy_reg = 0x100; break;
1617 case ULI526X_100MHF: phy_reg = 0x2000; break;
1618 case ULI526X_100MFD: phy_reg = 0x2100; break;
1619 }
1620 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
4689ced9
PC		 1621 }
1622 }
1623}
1624
1625
1626/*
1627 * Write a word to Phy register
1628 */
1629
1630static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1631{
1632 u16 i;
1633 unsigned long ioaddr;
1634
1635 if(chip_id == PCI_ULI5263_ID)
1636 {
1637 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1638 return;
1639 }
1640 /* M5261/M5263 Chip */
1641 ioaddr = iobase + DCR9;
1642
1643 /* Send 33 synchronization clock to Phy controller */
1644 for (i = 0; i < 35; i++)
1645 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1646
1647 /* Send start command(01) to Phy */
1648 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1649 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1650
1651 /* Send write command(01) to Phy */
1652 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1653 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1654
1655 /* Send Phy address */
1656 for (i = 0x10; i > 0; i = i >> 1)
1657 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1658
1659 /* Send register address */
1660 for (i = 0x10; i > 0; i = i >> 1)
1661 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1662
1663 /* written trasnition */
1664 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1665 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1666
1667 /* Write a word data to PHY controller */
1668 for ( i = 0x8000; i > 0; i >>= 1)
1669 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
f3b197ac 1670
4689ced9
PC		 1671}
1672
1673
1674/*
1675 * Read a word data from phy register
1676 */
1677
1678static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1679{
1680 int i;
1681 u16 phy_data;
1682 unsigned long ioaddr;
1683
1684 if(chip_id == PCI_ULI5263_ID)
1685 return phy_readby_cr10(iobase, phy_addr, offset);
1686 /* M5261/M5263 Chip */
1687 ioaddr = iobase + DCR9;
f3b197ac 1688
4689ced9
PC		 1689 /* Send 33 synchronization clock to Phy controller */
1690 for (i = 0; i < 35; i++)
1691 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1692
1693 /* Send start command(01) to Phy */
1694 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1695 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1696
1697 /* Send read command(10) to Phy */
1698 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1699 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1700
1701 /* Send Phy address */
1702 for (i = 0x10; i > 0; i = i >> 1)
1703 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1704
1705 /* Send register address */
1706 for (i = 0x10; i > 0; i = i >> 1)
1707 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1708
1709 /* Skip transition state */
1710 phy_read_1bit(ioaddr, chip_id);
1711
1712 /* read 16bit data */
1713 for (phy_data = 0, i = 0; i < 16; i++) {
1714 phy_data <<= 1;
1715 phy_data |= phy_read_1bit(ioaddr, chip_id);
1716 }
1717
1718 return phy_data;
1719}
1720
1721static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1722{
1723 unsigned long ioaddr,cr10_value;
f3b197ac 1724
4689ced9
PC		 1725 ioaddr = iobase + DCR10;
1726 cr10_value = phy_addr;
1727 cr10_value = (cr10_value<<5) + offset;
1728 cr10_value = (cr10_value<<16) + 0x08000000;
1729 outl(cr10_value,ioaddr);
1730 udelay(1);
1731 while(1)
1732 {
1733 cr10_value = inl(ioaddr);
1734 if(cr10_value&0x10000000)
1735 break;
1736 }
1737 return (cr10_value&0x0ffff);
1738}
1739
1740static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1741{
1742 unsigned long ioaddr,cr10_value;
f3b197ac 1743
4689ced9
PC		 1744 ioaddr = iobase + DCR10;
1745 cr10_value = phy_addr;
1746 cr10_value = (cr10_value<<5) + offset;
1747 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1748 outl(cr10_value,ioaddr);
1749 udelay(1);
1750}
1751/*
1752 * Write one bit data to Phy Controller
1753 */
1754
1755static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1756{
1757 outl(phy_data , ioaddr); /* MII Clock Low */
1758 udelay(1);
1759 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1760 udelay(1);
1761 outl(phy_data , ioaddr); /* MII Clock Low */
1762 udelay(1);
1763}
1764
1765
1766/*
1767 * Read one bit phy data from PHY controller
1768 */
1769
1770static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1771{
1772 u16 phy_data;
f3b197ac 1773
4689ced9
PC		 1774 outl(0x50000 , ioaddr);
1775 udelay(1);
1776 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1777 outl(0x40000 , ioaddr);
1778 udelay(1);
1779
1780 return phy_data;
1781}
1782
1783
1784static struct pci_device_id uli526x_pci_tbl[] = {
1785 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1786 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1787 { 0, }
1788};
1789MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1790
1791
1792static struct pci_driver uli526x_driver = {
1793 .name = "uli526x",
1794 .id_table = uli526x_pci_tbl,
1795 .probe = uli526x_init_one,
1796 .remove = __devexit_p(uli526x_remove_one),
b6aec32a
RW		 1797 .suspend = uli526x_suspend,
1798 .resume = uli526x_resume,
4689ced9
PC		 1799};
1800
1801MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1802MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1803MODULE_LICENSE("GPL");
1804
c213460f
ES		 1805module_param(debug, int, 0644);
1806module_param(mode, int, 0);
1807module_param(cr6set, int, 0);
4689ced9
PC		 1808MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1809MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1810
1811/* Description:
1812 * when user used insmod to add module, system invoked init_module()
945a7876 1813 * to register the services.
4689ced9
PC		 1814 */
1815
1816static int __init uli526x_init_module(void)
1817{
4689ced9
PC		 1818
1819 printk(version);
1820 printed_version = 1;
1821
1822 ULI526X_DBUG(0, "init_module() ", debug);
1823
1824 if (debug)
1825 uli526x_debug = debug; /* set debug flag */
1826 if (cr6set)
1827 uli526x_cr6_user_set = cr6set;
1828
e1c3e501 1829 switch (mode) {
4689ced9
PC		 1830 case ULI526X_10MHF:
1831 case ULI526X_100MHF:
1832 case ULI526X_10MFD:
1833 case ULI526X_100MFD:
1834 uli526x_media_mode = mode;
1835 break;
e1c3e501
HK		 1836 default:
1837 uli526x_media_mode = ULI526X_AUTO;
4689ced9
PC		 1838 break;
1839 }
1840
e1c3e501 1841 return pci_register_driver(&uli526x_driver);
4689ced9
PC		 1842}
1843
1844
1845/*
1846 * Description:
1847 * when user used rmmod to delete module, system invoked clean_module()
1848 * to un-register all registered services.
1849 */
1850
1851static void __exit uli526x_cleanup_module(void)
1852{
1853 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1854 pci_unregister_driver(&uli526x_driver);
1855}
1856
1857module_init(uli526x_init_module);
1858module_exit(uli526x_cleanup_module);
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