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ucc_geth: Fix a bunch of sparse warnings
[mirror_ubuntu-bionic-kernel.git] / drivers / net / tulip / uli526x.c
CommitLineData
4689ced9
PC		 1/*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
f3b197ac 12
4689ced9
PC		 13*/
14
15#define DRV_NAME "uli526x"
16#define DRV_VERSION "0.9.3"
17#define DRV_RELDATE "2005-7-29"
18
19#include <linux/module.h>
20
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/timer.h>
4689ced9
PC		 24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/slab.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/skbuff.h>
34#include <linux/delay.h>
35#include <linux/spinlock.h>
6cafa99f 36#include <linux/dma-mapping.h>
1977f032 37#include <linux/bitops.h>
4689ced9
PC		 38
39#include <asm/processor.h>
4689ced9
PC		 40#include <asm/io.h>
41#include <asm/dma.h>
42#include <asm/uaccess.h>
43
44
45/* Board/System/Debug information/definition ---------------- */
46#define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47#define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
48
49#define ULI526X_IO_SIZE 0x100
50#define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51#define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55#define TX_BUF_ALLOC 0x600
56#define RX_ALLOC_SIZE 0x620
57#define ULI526X_RESET 1
58#define CR0_DEFAULT 0
945a7876 59#define CR6_DEFAULT 0x22200000
4689ced9
PC		 60#define CR7_DEFAULT 0x180c1
61#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63#define MAX_PACKET_SIZE 1514
64#define ULI5261_MAX_MULTICAST 14
65#define RX_COPY_SIZE 100
66#define MAX_CHECK_PACKET 0x8000
67
68#define ULI526X_10MHF 0
69#define ULI526X_100MHF 1
70#define ULI526X_10MFD 4
71#define ULI526X_100MFD 5
72#define ULI526X_AUTO 8
73
74#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
80
81#define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82#define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83#define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
84
85#define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
86
87#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
88
89
90/* CR9 definition: SROM/MII */
91#define CR9_SROM_READ 0x4800
92#define CR9_SRCS 0x1
93#define CR9_SRCLK 0x2
94#define CR9_CRDOUT 0x8
95#define SROM_DATA_0 0x0
96#define SROM_DATA_1 0x4
97#define PHY_DATA_1 0x20000
98#define PHY_DATA_0 0x00000
99#define MDCLKH 0x10000
100
101#define PHY_POWER_DOWN 0x800
102
103#define SROM_V41_CODE 0x14
104
945a7876
PC		 105#define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
107 udelay(5); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
109 udelay(5); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
111 udelay(5);
4689ced9
PC		 112
113/* Structure/enum declaration ------------------------------- */
114struct tx_desc {
c559a5bc 115 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
4689ced9
PC		 116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118} __attribute__(( aligned(32) ));
119
120struct rx_desc {
c559a5bc 121 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
4689ced9
PC		 122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124} __attribute__(( aligned(32) ));
125
126struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
945a7876 128 struct net_device *next_dev; /* next device */
4689ced9
PC		 129 struct pci_dev *pdev; /* PCI device */
130 spinlock_t lock;
131
132 long ioaddr; /* I/O base address */
133 u32 cr0_data;
134 u32 cr5_data;
135 u32 cr6_data;
136 u32 cr7_data;
137 u32 cr15_data;
138
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
145
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
159
160 u16 dbug_cnt;
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
163
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
166 u8 phy_addr;
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
170
171 /* System defined statistic counter */
172 struct net_device_stats stats;
173
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun;
176 unsigned long tx_loss_carrier;
177 unsigned long tx_no_carrier;
178 unsigned long tx_late_collision;
179 unsigned long tx_excessive_collision;
180 unsigned long tx_jabber_timeout;
181 unsigned long reset_count;
182 unsigned long reset_cr8;
183 unsigned long reset_fatal;
184 unsigned long reset_TXtimeout;
185
186 /* NIC SROM data */
187 unsigned char srom[128];
f3b197ac 188 u8 init;
4689ced9
PC		 189};
190
191enum uli526x_offsets {
192 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
193 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
194 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
195 DCR15 = 0x78
196};
197
198enum uli526x_CR6_bits {
199 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
200 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
201 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
202};
203
204/* Global variable declaration ----------------------------- */
205static int __devinitdata printed_version;
206static char version[] __devinitdata =
207 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
208 DRV_VERSION " (" DRV_RELDATE ")\n";
209
210static int uli526x_debug;
211static unsigned char uli526x_media_mode = ULI526X_AUTO;
212static u32 uli526x_cr6_user_set;
213
214/* For module input parameter */
215static int debug;
216static u32 cr6set;
99bb2579 217static int mode = 8;
4689ced9
PC		 218
219/* function declaration ------------------------------------- */
945a7876
PC		 220static int uli526x_open(struct net_device *);
221static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
222static int uli526x_stop(struct net_device *);
223static struct net_device_stats * uli526x_get_stats(struct net_device *);
224static void uli526x_set_filter_mode(struct net_device *);
7282d491 225static const struct ethtool_ops netdev_ethtool_ops;
945a7876 226static u16 read_srom_word(long, int);
7d12e780 227static irqreturn_t uli526x_interrupt(int, void *);
4689ced9
PC		 228static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
229static void allocate_rx_buffer(struct uli526x_board_info *);
230static void update_cr6(u32, unsigned long);
945a7876 231static void send_filter_frame(struct net_device *, int);
4689ced9
PC		 232static u16 phy_read(unsigned long, u8, u8, u32);
233static u16 phy_readby_cr10(unsigned long, u8, u8);
234static void phy_write(unsigned long, u8, u8, u16, u32);
235static void phy_writeby_cr10(unsigned long, u8, u8, u16);
236static void phy_write_1bit(unsigned long, u32, u32);
237static u16 phy_read_1bit(unsigned long, u32);
238static u8 uli526x_sense_speed(struct uli526x_board_info *);
239static void uli526x_process_mode(struct uli526x_board_info *);
240static void uli526x_timer(unsigned long);
945a7876
PC		 241static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
242static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
4689ced9 243static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
945a7876 244static void uli526x_dynamic_reset(struct net_device *);
4689ced9 245static void uli526x_free_rxbuffer(struct uli526x_board_info *);
945a7876 246static void uli526x_init(struct net_device *);
4689ced9
PC		 247static void uli526x_set_phyxcer(struct uli526x_board_info *);
248
945a7876 249/* ULI526X network board routine ---------------------------- */
4689ced9
PC		 250
251/*
945a7876 252 * Search ULI526X board, allocate space and register it
4689ced9
PC		 253 */
254
255static int __devinit uli526x_init_one (struct pci_dev *pdev,
256 const struct pci_device_id *ent)
257{
258 struct uli526x_board_info *db; /* board information structure */
259 struct net_device *dev;
260 int i, err;
0795af57 261 DECLARE_MAC_BUF(mac);
f3b197ac 262
4689ced9
PC		 263 ULI526X_DBUG(0, "uli526x_init_one()", 0);
264
265 if (!printed_version++)
266 printk(version);
267
268 /* Init network device */
269 dev = alloc_etherdev(sizeof(*db));
270 if (dev == NULL)
271 return -ENOMEM;
4689ced9
PC		 272 SET_NETDEV_DEV(dev, &pdev->dev);
273
945a7876 274 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
4689ced9
PC		 275 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
276 err = -ENODEV;
277 goto err_out_free;
278 }
279
280 /* Enable Master/IO access, Disable memory access */
281 err = pci_enable_device(pdev);
282 if (err)
283 goto err_out_free;
284
285 if (!pci_resource_start(pdev, 0)) {
286 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
287 err = -ENODEV;
288 goto err_out_disable;
289 }
290
291 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
292 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
293 err = -ENODEV;
294 goto err_out_disable;
295 }
296
297 if (pci_request_regions(pdev, DRV_NAME)) {
298 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
299 err = -ENODEV;
300 goto err_out_disable;
301 }
302
4689ced9
PC		 303 /* Init system & device */
304 db = netdev_priv(dev);
305
306 /* Allocate Tx/Rx descriptor memory */
307 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
945a7876
PC		 308 if(db->desc_pool_ptr == NULL)
309 {
310 err = -ENOMEM;
311 goto err_out_nomem;
312 }
4689ced9 313 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
945a7876
PC		 314 if(db->buf_pool_ptr == NULL)
315 {
316 err = -ENOMEM;
317 goto err_out_nomem;
318 }
f3b197ac 319
4689ced9
PC		 320 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
321 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
322 db->buf_pool_start = db->buf_pool_ptr;
323 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
324
325 db->chip_id = ent->driver_data;
326 db->ioaddr = pci_resource_start(pdev, 0);
f3b197ac 327
4689ced9
PC		 328 db->pdev = pdev;
329 db->init = 1;
f3b197ac 330
4689ced9
PC		 331 dev->base_addr = db->ioaddr;
332 dev->irq = pdev->irq;
333 pci_set_drvdata(pdev, dev);
f3b197ac 334
4689ced9
PC		 335 /* Register some necessary functions */
336 dev->open = &uli526x_open;
337 dev->hard_start_xmit = &uli526x_start_xmit;
338 dev->stop = &uli526x_stop;
339 dev->get_stats = &uli526x_get_stats;
340 dev->set_multicast_list = &uli526x_set_filter_mode;
341 dev->ethtool_ops = &netdev_ethtool_ops;
342 spin_lock_init(&db->lock);
343
f3b197ac 344
4689ced9
PC		 345 /* read 64 word srom data */
346 for (i = 0; i < 64; i++)
c559a5bc 347 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
4689ced9
PC		 348
349 /* Set Node address */
945a7876 350 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
4689ced9
PC		 351 {
352 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
353 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
354 outl(0, db->ioaddr + DCR14); //Clear reset port
355 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
356 outl(0, db->ioaddr + DCR14); //Clear reset port
357 outl(0, db->ioaddr + DCR13); //Clear CR13
358 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
359 //Read MAC address from CR14
360 for (i = 0; i < 6; i++)
361 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
362 //Read end
363 outl(0, db->ioaddr + DCR13); //Clear CR13
364 outl(0, db->ioaddr + DCR0); //Clear CR0
365 udelay(10);
366 }
367 else /*Exist SROM*/
368 {
369 for (i = 0; i < 6; i++)
370 dev->dev_addr[i] = db->srom[20 + i];
371 }
372 err = register_netdev (dev);
373 if (err)
374 goto err_out_res;
375
0795af57
JP		 376 printk(KERN_INFO "%s: ULi M%04lx at pci%s, %s, irq %d.\n",
377 dev->name,ent->driver_data >> 16,pci_name(pdev),
378 print_mac(mac, dev->dev_addr), dev->irq);
4689ced9
PC		 379
380 pci_set_master(pdev);
381
382 return 0;
383
384err_out_res:
385 pci_release_regions(pdev);
945a7876
PC		 386err_out_nomem:
387 if(db->desc_pool_ptr)
388 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
389 db->desc_pool_ptr, db->desc_pool_dma_ptr);
f3b197ac 390
945a7876
PC		 391 if(db->buf_pool_ptr != NULL)
392 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
393 db->buf_pool_ptr, db->buf_pool_dma_ptr);
4689ced9
PC		 394err_out_disable:
395 pci_disable_device(pdev);
396err_out_free:
397 pci_set_drvdata(pdev, NULL);
398 free_netdev(dev);
399
400 return err;
401}
402
403
404static void __devexit uli526x_remove_one (struct pci_dev *pdev)
405{
406 struct net_device *dev = pci_get_drvdata(pdev);
407 struct uli526x_board_info *db = netdev_priv(dev);
408
409 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
410
945a7876
PC		 411 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
412 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
413 db->desc_pool_dma_ptr);
414 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
415 db->buf_pool_ptr, db->buf_pool_dma_ptr);
416 unregister_netdev(dev);
417 pci_release_regions(pdev);
418 free_netdev(dev); /* free board information */
419 pci_set_drvdata(pdev, NULL);
420 pci_disable_device(pdev);
4689ced9
PC		 421 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
422}
423
424
425/*
426 * Open the interface.
945a7876 427 * The interface is opened whenever "ifconfig" activates it.
4689ced9
PC		 428 */
429
945a7876 430static int uli526x_open(struct net_device *dev)
4689ced9
PC		 431{
432 int ret;
433 struct uli526x_board_info *db = netdev_priv(dev);
f3b197ac 434
4689ced9
PC		 435 ULI526X_DBUG(0, "uli526x_open", 0);
436
1fb9df5d 437 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
4689ced9
PC		 438 if (ret)
439 return ret;
440
441 /* system variable init */
442 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
4689ced9
PC		 443 db->tx_packet_cnt = 0;
444 db->rx_avail_cnt = 0;
445 db->link_failed = 1;
446 netif_carrier_off(dev);
447 db->wait_reset = 0;
448
449 db->NIC_capability = 0xf; /* All capability*/
450 db->PHY_reg4 = 0x1e0;
451
452 /* CR6 operation mode decision */
453 db->cr6_data |= ULI526X_TXTH_256;
454 db->cr0_data = CR0_DEFAULT;
f3b197ac 455
945a7876 456 /* Initialize ULI526X board */
4689ced9
PC		 457 uli526x_init(dev);
458
459 /* Active System Interface */
460 netif_wake_queue(dev);
461
462 /* set and active a timer process */
463 init_timer(&db->timer);
464 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
465 db->timer.data = (unsigned long)dev;
466 db->timer.function = &uli526x_timer;
467 add_timer(&db->timer);
468
469 return 0;
470}
471
472
945a7876 473/* Initialize ULI526X board
4689ced9 474 * Reset ULI526X board
945a7876 475 * Initialize TX/Rx descriptor chain structure
4689ced9
PC		 476 * Send the set-up frame
477 * Enable Tx/Rx machine
478 */
479
945a7876 480static void uli526x_init(struct net_device *dev)
4689ced9
PC		 481{
482 struct uli526x_board_info *db = netdev_priv(dev);
483 unsigned long ioaddr = db->ioaddr;
484 u8 phy_tmp;
7a7d23da 485 u8 timeout;
4689ced9
PC		 486 u16 phy_value;
487 u16 phy_reg_reset;
488
7a7d23da 489
4689ced9
PC		 490 ULI526X_DBUG(0, "uli526x_init()", 0);
491
492 /* Reset M526x MAC controller */
493 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
494 udelay(100);
495 outl(db->cr0_data, ioaddr + DCR0);
496 udelay(5);
497
498 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
499 db->phy_addr = 1;
500 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
501 {
502 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
503 if(phy_value != 0xffff&&phy_value!=0)
504 {
505 db->phy_addr = phy_tmp;
506 break;
507 }
508 }
509 if(phy_tmp == 32)
510 printk(KERN_WARNING "Can not find the phy address!!!");
511 /* Parser SROM and media mode */
512 db->media_mode = uli526x_media_mode;
513
7a7d23da 514 /* phyxcer capability setting */
4689ced9
PC		 515 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
516 phy_reg_reset = (phy_reg_reset | 0x8000);
517 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
7a7d23da
GG		 518
519 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
520 * functions") or phy data sheet for details on phy reset
521 */
4689ced9 522 udelay(500);
7a7d23da
GG		 523 timeout = 10;
524 while (timeout-- &&
525 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
526 udelay(100);
4689ced9
PC		 527
528 /* Process Phyxcer Media Mode */
529 uli526x_set_phyxcer(db);
530
531 /* Media Mode Process */
532 if ( !(db->media_mode & ULI526X_AUTO) )
533 db->op_mode = db->media_mode; /* Force Mode */
534
945a7876 535 /* Initialize Transmit/Receive decriptor and CR3/4 */
4689ced9
PC		 536 uli526x_descriptor_init(db, ioaddr);
537
538 /* Init CR6 to program M526X operation */
539 update_cr6(db->cr6_data, ioaddr);
540
541 /* Send setup frame */
542 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
543
544 /* Init CR7, interrupt active bit */
545 db->cr7_data = CR7_DEFAULT;
546 outl(db->cr7_data, ioaddr + DCR7);
547
548 /* Init CR15, Tx jabber and Rx watchdog timer */
549 outl(db->cr15_data, ioaddr + DCR15);
550
551 /* Enable ULI526X Tx/Rx function */
552 db->cr6_data |= CR6_RXSC | CR6_TXSC;
553 update_cr6(db->cr6_data, ioaddr);
554}
555
556
557/*
558 * Hardware start transmission.
559 * Send a packet to media from the upper layer.
560 */
561
945a7876 562static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
4689ced9
PC		 563{
564 struct uli526x_board_info *db = netdev_priv(dev);
565 struct tx_desc *txptr;
566 unsigned long flags;
567
568 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
569
570 /* Resource flag check */
571 netif_stop_queue(dev);
572
573 /* Too large packet check */
574 if (skb->len > MAX_PACKET_SIZE) {
575 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
576 dev_kfree_skb(skb);
577 return 0;
578 }
579
580 spin_lock_irqsave(&db->lock, flags);
581
582 /* No Tx resource check, it never happen nromally */
583 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
584 spin_unlock_irqrestore(&db->lock, flags);
585 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
586 return 1;
587 }
588
589 /* Disable NIC interrupt */
590 outl(0, dev->base_addr + DCR7);
591
592 /* transmit this packet */
593 txptr = db->tx_insert_ptr;
d626f62b 594 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
4689ced9
PC		 595 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
596
597 /* Point to next transmit free descriptor */
598 db->tx_insert_ptr = txptr->next_tx_desc;
599
600 /* Transmit Packet Process */
601 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
602 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
603 db->tx_packet_cnt++; /* Ready to send */
604 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
605 dev->trans_start = jiffies; /* saved time stamp */
606 }
607
608 /* Tx resource check */
609 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
610 netif_wake_queue(dev);
611
612 /* Restore CR7 to enable interrupt */
613 spin_unlock_irqrestore(&db->lock, flags);
614 outl(db->cr7_data, dev->base_addr + DCR7);
f3b197ac 615
4689ced9
PC		 616 /* free this SKB */
617 dev_kfree_skb(skb);
618
619 return 0;
620}
621
622
623/*
624 * Stop the interface.
625 * The interface is stopped when it is brought.
626 */
627
945a7876 628static int uli526x_stop(struct net_device *dev)
4689ced9
PC		 629{
630 struct uli526x_board_info *db = netdev_priv(dev);
631 unsigned long ioaddr = dev->base_addr;
632
633 ULI526X_DBUG(0, "uli526x_stop", 0);
634
635 /* disable system */
636 netif_stop_queue(dev);
637
638 /* deleted timer */
639 del_timer_sync(&db->timer);
640
641 /* Reset & stop ULI526X board */
642 outl(ULI526X_RESET, ioaddr + DCR0);
643 udelay(5);
644 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
645
646 /* free interrupt */
647 free_irq(dev->irq, dev);
648
649 /* free allocated rx buffer */
650 uli526x_free_rxbuffer(db);
651
652#if 0
653 /* show statistic counter */
654 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
655 db->tx_fifo_underrun, db->tx_excessive_collision,
656 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
657 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
658 db->reset_fatal, db->reset_TXtimeout);
659#endif
660
661 return 0;
662}
663
664
665/*
666 * M5261/M5263 insterrupt handler
667 * receive the packet to upper layer, free the transmitted packet
668 */
669
7d12e780 670static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
4689ced9 671{
945a7876 672 struct net_device *dev = dev_id;
4689ced9
PC		 673 struct uli526x_board_info *db = netdev_priv(dev);
674 unsigned long ioaddr = dev->base_addr;
675 unsigned long flags;
676
4689ced9
PC		 677 spin_lock_irqsave(&db->lock, flags);
678 outl(0, ioaddr + DCR7);
679
680 /* Got ULI526X status */
681 db->cr5_data = inl(ioaddr + DCR5);
682 outl(db->cr5_data, ioaddr + DCR5);
683 if ( !(db->cr5_data & 0x180c1) ) {
684 spin_unlock_irqrestore(&db->lock, flags);
685 outl(db->cr7_data, ioaddr + DCR7);
686 return IRQ_HANDLED;
687 }
688
4689ced9
PC		 689 /* Check system status */
690 if (db->cr5_data & 0x2000) {
691 /* system bus error happen */
692 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
693 db->reset_fatal++;
694 db->wait_reset = 1; /* Need to RESET */
695 spin_unlock_irqrestore(&db->lock, flags);
696 return IRQ_HANDLED;
697 }
698
699 /* Received the coming packet */
700 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
701 uli526x_rx_packet(dev, db);
702
703 /* reallocate rx descriptor buffer */
704 if (db->rx_avail_cnt<RX_DESC_CNT)
705 allocate_rx_buffer(db);
706
707 /* Free the transmitted descriptor */
708 if ( db->cr5_data & 0x01)
709 uli526x_free_tx_pkt(dev, db);
710
711 /* Restore CR7 to enable interrupt mask */
712 outl(db->cr7_data, ioaddr + DCR7);
713
714 spin_unlock_irqrestore(&db->lock, flags);
715 return IRQ_HANDLED;
716}
717
718
719/*
720 * Free TX resource after TX complete
721 */
722
945a7876 723static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 724{
725 struct tx_desc *txptr;
4689ced9
PC		 726 u32 tdes0;
727
728 txptr = db->tx_remove_ptr;
729 while(db->tx_packet_cnt) {
730 tdes0 = le32_to_cpu(txptr->tdes0);
731 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
732 if (tdes0 & 0x80000000)
733 break;
734
735 /* A packet sent completed */
736 db->tx_packet_cnt--;
737 db->stats.tx_packets++;
738
739 /* Transmit statistic counter */
740 if ( tdes0 != 0x7fffffff ) {
741 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
742 db->stats.collisions += (tdes0 >> 3) & 0xf;
743 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
744 if (tdes0 & TDES0_ERR_MASK) {
745 db->stats.tx_errors++;
746 if (tdes0 & 0x0002) { /* UnderRun */
747 db->tx_fifo_underrun++;
748 if ( !(db->cr6_data & CR6_SFT) ) {
749 db->cr6_data = db->cr6_data | CR6_SFT;
750 update_cr6(db->cr6_data, db->ioaddr);
751 }
752 }
753 if (tdes0 & 0x0100)
754 db->tx_excessive_collision++;
755 if (tdes0 & 0x0200)
756 db->tx_late_collision++;
757 if (tdes0 & 0x0400)
758 db->tx_no_carrier++;
759 if (tdes0 & 0x0800)
760 db->tx_loss_carrier++;
761 if (tdes0 & 0x4000)
762 db->tx_jabber_timeout++;
763 }
764 }
765
766 txptr = txptr->next_tx_desc;
767 }/* End of while */
768
769 /* Update TX remove pointer to next */
770 db->tx_remove_ptr = txptr;
771
772 /* Resource available check */
773 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
774 netif_wake_queue(dev); /* Active upper layer, send again */
775}
776
777
778/*
779 * Receive the come packet and pass to upper layer
780 */
781
945a7876 782static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 783{
784 struct rx_desc *rxptr;
785 struct sk_buff *skb;
786 int rxlen;
787 u32 rdes0;
f3b197ac 788
4689ced9
PC		 789 rxptr = db->rx_ready_ptr;
790
791 while(db->rx_avail_cnt) {
792 rdes0 = le32_to_cpu(rxptr->rdes0);
793 if (rdes0 & 0x80000000) /* packet owner check */
794 {
795 break;
796 }
797
798 db->rx_avail_cnt--;
799 db->interval_rx_cnt++;
800
801 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
802 if ( (rdes0 & 0x300) != 0x300) {
803 /* A packet without First/Last flag */
804 /* reuse this SKB */
805 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
806 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
807 } else {
808 /* A packet with First/Last flag */
809 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
810
811 /* error summary bit check */
812 if (rdes0 & 0x8000) {
813 /* This is a error packet */
814 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
815 db->stats.rx_errors++;
816 if (rdes0 & 1)
817 db->stats.rx_fifo_errors++;
818 if (rdes0 & 2)
819 db->stats.rx_crc_errors++;
820 if (rdes0 & 0x80)
821 db->stats.rx_length_errors++;
822 }
823
824 if ( !(rdes0 & 0x8000) ||
825 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
826 skb = rxptr->rx_skb_ptr;
f3b197ac 827
4689ced9
PC		 828 /* Good packet, send to upper layer */
829 /* Shorst packet used new SKB */
830 if ( (rxlen < RX_COPY_SIZE) &&
831 ( (skb = dev_alloc_skb(rxlen + 2) )
832 != NULL) ) {
833 /* size less than COPY_SIZE, allocate a rxlen SKB */
4689ced9 834 skb_reserve(skb, 2); /* 16byte align */
27a884dc
ACM		 835 memcpy(skb_put(skb, rxlen),
836 skb_tail_pointer(rxptr->rx_skb_ptr),
837 rxlen);
4689ced9 838 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 839 } else
4689ced9 840 skb_put(skb, rxlen);
4c13eb66 841
4689ced9
PC		 842 skb->protocol = eth_type_trans(skb, dev);
843 netif_rx(skb);
844 dev->last_rx = jiffies;
845 db->stats.rx_packets++;
846 db->stats.rx_bytes += rxlen;
f3b197ac 847
4689ced9
PC		 848 } else {
849 /* Reuse SKB buffer when the packet is error */
850 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
851 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
852 }
853 }
854
855 rxptr = rxptr->next_rx_desc;
856 }
857
858 db->rx_ready_ptr = rxptr;
859}
860
861
862/*
863 * Get statistics from driver.
864 */
865
945a7876 866static struct net_device_stats * uli526x_get_stats(struct net_device *dev)
4689ced9
PC		 867{
868 struct uli526x_board_info *db = netdev_priv(dev);
869
870 ULI526X_DBUG(0, "uli526x_get_stats", 0);
871 return &db->stats;
872}
873
874
875/*
876 * Set ULI526X multicast address
877 */
878
945a7876 879static void uli526x_set_filter_mode(struct net_device * dev)
4689ced9
PC		 880{
881 struct uli526x_board_info *db = dev->priv;
882 unsigned long flags;
883
884 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
885 spin_lock_irqsave(&db->lock, flags);
886
887 if (dev->flags & IFF_PROMISC) {
888 ULI526X_DBUG(0, "Enable PROM Mode", 0);
889 db->cr6_data |= CR6_PM | CR6_PBF;
890 update_cr6(db->cr6_data, db->ioaddr);
891 spin_unlock_irqrestore(&db->lock, flags);
892 return;
893 }
894
895 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
896 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
897 db->cr6_data &= ~(CR6_PM | CR6_PBF);
898 db->cr6_data |= CR6_PAM;
899 spin_unlock_irqrestore(&db->lock, flags);
900 return;
901 }
902
903 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
904 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
905 spin_unlock_irqrestore(&db->lock, flags);
906}
907
908static void
909ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
910{
945a7876
PC		 911 ecmd->supported = (SUPPORTED_10baseT_Half |
912 SUPPORTED_10baseT_Full |
913 SUPPORTED_100baseT_Half |
914 SUPPORTED_100baseT_Full |
915 SUPPORTED_Autoneg |
916 SUPPORTED_MII);
f3b197ac 917
945a7876
PC		 918 ecmd->advertising = (ADVERTISED_10baseT_Half |
919 ADVERTISED_10baseT_Full |
920 ADVERTISED_100baseT_Half |
921 ADVERTISED_100baseT_Full |
922 ADVERTISED_Autoneg |
923 ADVERTISED_MII);
4689ced9
PC		 924
925
945a7876
PC		 926 ecmd->port = PORT_MII;
927 ecmd->phy_address = db->phy_addr;
4689ced9 928
945a7876 929 ecmd->transceiver = XCVR_EXTERNAL;
f3b197ac 930
4689ced9
PC		 931 ecmd->speed = 10;
932 ecmd->duplex = DUPLEX_HALF;
f3b197ac 933
4689ced9
PC		 934 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
935 {
f3b197ac 936 ecmd->speed = 100;
4689ced9
PC		 937 }
938 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
939 {
940 ecmd->duplex = DUPLEX_FULL;
941 }
942 if(db->link_failed)
943 {
944 ecmd->speed = -1;
f3b197ac 945 ecmd->duplex = -1;
4689ced9 946 }
f3b197ac 947
4689ced9 948 if (db->media_mode & ULI526X_AUTO)
f3b197ac 949 {
4689ced9
PC		 950 ecmd->autoneg = AUTONEG_ENABLE;
951 }
4689ced9
PC		 952}
953
954static void netdev_get_drvinfo(struct net_device *dev,
955 struct ethtool_drvinfo *info)
956{
957 struct uli526x_board_info *np = netdev_priv(dev);
958
959 strcpy(info->driver, DRV_NAME);
960 strcpy(info->version, DRV_VERSION);
961 if (np->pdev)
962 strcpy(info->bus_info, pci_name(np->pdev));
963 else
964 sprintf(info->bus_info, "EISA 0x%lx %d",
965 dev->base_addr, dev->irq);
966}
967
968static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
969 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 970
4689ced9 971 ULi_ethtool_gset(np, cmd);
f3b197ac 972
4689ced9
PC		 973 return 0;
974}
975
976static u32 netdev_get_link(struct net_device *dev) {
977 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 978
4689ced9
PC		 979 if(np->link_failed)
980 return 0;
981 else
982 return 1;
983}
984
985static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
986{
987 wol->supported = WAKE_PHY | WAKE_MAGIC;
988 wol->wolopts = 0;
989}
990
7282d491 991static const struct ethtool_ops netdev_ethtool_ops = {
4689ced9
PC		 992 .get_drvinfo = netdev_get_drvinfo,
993 .get_settings = netdev_get_settings,
994 .get_link = netdev_get_link,
995 .get_wol = uli526x_get_wol,
996};
997
998/*
999 * A periodic timer routine
1000 * Dynamic media sense, allocate Rx buffer...
1001 */
1002
1003static void uli526x_timer(unsigned long data)
1004{
1005 u32 tmp_cr8;
1006 unsigned char tmp_cr12=0;
945a7876 1007 struct net_device *dev = (struct net_device *) data;
4689ced9
PC		 1008 struct uli526x_board_info *db = netdev_priv(dev);
1009 unsigned long flags;
1010 u8 TmpSpeed=10;
f3b197ac 1011
4689ced9
PC		 1012 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1013 spin_lock_irqsave(&db->lock, flags);
1014
f3b197ac 1015
4689ced9
PC		 1016 /* Dynamic reset ULI526X : system error or transmit time-out */
1017 tmp_cr8 = inl(db->ioaddr + DCR8);
1018 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1019 db->reset_cr8++;
1020 db->wait_reset = 1;
1021 }
1022 db->interval_rx_cnt = 0;
1023
1024 /* TX polling kick monitor */
1025 if ( db->tx_packet_cnt &&
1026 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
f3b197ac 1027 outl(0x1, dev->base_addr + DCR1); // Tx polling again
4689ced9 1028
f3b197ac 1029 // TX Timeout
4689ced9
PC		 1030 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1031 db->reset_TXtimeout++;
1032 db->wait_reset = 1;
1033 printk( "%s: Tx timeout - resetting\n",
1034 dev->name);
1035 }
1036 }
1037
1038 if (db->wait_reset) {
1039 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1040 db->reset_count++;
1041 uli526x_dynamic_reset(dev);
1042 db->timer.expires = ULI526X_TIMER_WUT;
1043 add_timer(&db->timer);
1044 spin_unlock_irqrestore(&db->lock, flags);
1045 return;
1046 }
1047
1048 /* Link status check, Dynamic media type change */
1049 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1050 tmp_cr12 = 3;
1051
1052 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1053 /* Link Failed */
1054 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1055 netif_carrier_off(dev);
1056 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1057 db->link_failed = 1;
1058
1059 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1060 /* AUTO don't need */
1061 if ( !(db->media_mode & 0x8) )
1062 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1063
1064 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1065 if (db->media_mode & ULI526X_AUTO) {
1066 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1067 update_cr6(db->cr6_data, db->ioaddr);
1068 }
1069 } else
1070 if ((tmp_cr12 & 0x3) && db->link_failed) {
1071 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1072 db->link_failed = 0;
1073
1074 /* Auto Sense Speed */
1075 if ( (db->media_mode & ULI526X_AUTO) &&
1076 uli526x_sense_speed(db) )
1077 db->link_failed = 1;
1078 uli526x_process_mode(db);
f3b197ac 1079
4689ced9
PC		 1080 if(db->link_failed==0)
1081 {
1082 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1083 {
1084 TmpSpeed = 100;
1085 }
1086 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1087 {
1088 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1089 }
1090 else
1091 {
1092 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1093 }
1094 netif_carrier_on(dev);
1095 }
1096 /* SHOW_MEDIA_TYPE(db->op_mode); */
1097 }
1098 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1099 {
1100 if(db->init==1)
1101 {
1102 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1103 netif_carrier_off(dev);
1104 }
1105 }
1106 db->init=0;
1107
1108 /* Timer active again */
1109 db->timer.expires = ULI526X_TIMER_WUT;
1110 add_timer(&db->timer);
1111 spin_unlock_irqrestore(&db->lock, flags);
1112}
1113
1114
1115/*
4689ced9
PC		 1116 * Stop ULI526X board
1117 * Free Tx/Rx allocated memory
b6aec32a 1118 * Init system variable
4689ced9
PC		 1119 */
1120
b6aec32a 1121static void uli526x_reset_prepare(struct net_device *dev)
4689ced9
PC		 1122{
1123 struct uli526x_board_info *db = netdev_priv(dev);
1124
4689ced9
PC		 1125 /* Sopt MAC controller */
1126 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1127 update_cr6(db->cr6_data, dev->base_addr);
1128 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1129 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1130
1131 /* Disable upper layer interface */
1132 netif_stop_queue(dev);
1133
1134 /* Free Rx Allocate buffer */
1135 uli526x_free_rxbuffer(db);
1136
1137 /* system variable init */
1138 db->tx_packet_cnt = 0;
1139 db->rx_avail_cnt = 0;
1140 db->link_failed = 1;
1141 db->init=1;
1142 db->wait_reset = 0;
b6aec32a
RW		 1143}
1144
1145
1146/*
1147 * Dynamic reset the ULI526X board
1148 * Stop ULI526X board
1149 * Free Tx/Rx allocated memory
1150 * Reset ULI526X board
1151 * Re-initialize ULI526X board
1152 */
1153
1154static void uli526x_dynamic_reset(struct net_device *dev)
1155{
1156 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1157
1158 uli526x_reset_prepare(dev);
4689ced9 1159
945a7876 1160 /* Re-initialize ULI526X board */
4689ced9
PC		 1161 uli526x_init(dev);
1162
1163 /* Restart upper layer interface */
1164 netif_wake_queue(dev);
1165}
1166
1167
b6aec32a
RW		 1168#ifdef CONFIG_PM
1169
1170/*
1171 * Suspend the interface.
1172 */
1173
1174static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1175{
1176 struct net_device *dev = pci_get_drvdata(pdev);
1177 pci_power_t power_state;
1178 int err;
1179
1180 ULI526X_DBUG(0, "uli526x_suspend", 0);
1181
1182 if (!netdev_priv(dev))
1183 return 0;
1184
1185 pci_save_state(pdev);
1186
1187 if (!netif_running(dev))
1188 return 0;
1189
1190 netif_device_detach(dev);
1191 uli526x_reset_prepare(dev);
1192
1193 power_state = pci_choose_state(pdev, state);
1194 pci_enable_wake(pdev, power_state, 0);
1195 err = pci_set_power_state(pdev, power_state);
1196 if (err) {
1197 netif_device_attach(dev);
1198 /* Re-initialize ULI526X board */
1199 uli526x_init(dev);
1200 /* Restart upper layer interface */
1201 netif_wake_queue(dev);
1202 }
1203
1204 return err;
1205}
1206
1207/*
1208 * Resume the interface.
1209 */
1210
1211static int uli526x_resume(struct pci_dev *pdev)
1212{
1213 struct net_device *dev = pci_get_drvdata(pdev);
1214 int err;
1215
1216 ULI526X_DBUG(0, "uli526x_resume", 0);
1217
1218 if (!netdev_priv(dev))
1219 return 0;
1220
1221 pci_restore_state(pdev);
1222
1223 if (!netif_running(dev))
1224 return 0;
1225
1226 err = pci_set_power_state(pdev, PCI_D0);
1227 if (err) {
1228 printk(KERN_WARNING "%s: Could not put device into D0\n",
1229 dev->name);
1230 return err;
1231 }
1232
1233 netif_device_attach(dev);
1234 /* Re-initialize ULI526X board */
1235 uli526x_init(dev);
1236 /* Restart upper layer interface */
1237 netif_wake_queue(dev);
1238
1239 return 0;
1240}
1241
1242#else /* !CONFIG_PM */
1243
1244#define uli526x_suspend NULL
1245#define uli526x_resume NULL
1246
1247#endif /* !CONFIG_PM */
1248
1249
4689ced9
PC		 1250/*
1251 * free all allocated rx buffer
1252 */
1253
1254static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1255{
1256 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1257
1258 /* free allocated rx buffer */
1259 while (db->rx_avail_cnt) {
1260 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1261 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1262 db->rx_avail_cnt--;
1263 }
1264}
1265
1266
1267/*
1268 * Reuse the SK buffer
1269 */
1270
1271static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1272{
1273 struct rx_desc *rxptr = db->rx_insert_ptr;
1274
1275 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1276 rxptr->rx_skb_ptr = skb;
27a884dc
ACM		 1277 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1278 skb_tail_pointer(skb),
1279 RX_ALLOC_SIZE,
1280 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1281 wmb();
1282 rxptr->rdes0 = cpu_to_le32(0x80000000);
1283 db->rx_avail_cnt++;
1284 db->rx_insert_ptr = rxptr->next_rx_desc;
1285 } else
1286 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1287}
1288
1289
1290/*
1291 * Initialize transmit/Receive descriptor
1292 * Using Chain structure, and allocate Tx/Rx buffer
1293 */
1294
1295static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1296{
1297 struct tx_desc *tmp_tx;
1298 struct rx_desc *tmp_rx;
1299 unsigned char *tmp_buf;
1300 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1301 dma_addr_t tmp_buf_dma;
1302 int i;
1303
1304 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1305
1306 /* tx descriptor start pointer */
1307 db->tx_insert_ptr = db->first_tx_desc;
1308 db->tx_remove_ptr = db->first_tx_desc;
1309 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1310
1311 /* rx descriptor start pointer */
1312 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1313 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1314 db->rx_insert_ptr = db->first_rx_desc;
1315 db->rx_ready_ptr = db->first_rx_desc;
1316 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1317
1318 /* Init Transmit chain */
1319 tmp_buf = db->buf_pool_start;
1320 tmp_buf_dma = db->buf_pool_dma_start;
1321 tmp_tx_dma = db->first_tx_desc_dma;
1322 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1323 tmp_tx->tx_buf_ptr = tmp_buf;
1324 tmp_tx->tdes0 = cpu_to_le32(0);
1325 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1326 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1327 tmp_tx_dma += sizeof(struct tx_desc);
1328 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1329 tmp_tx->next_tx_desc = tmp_tx + 1;
1330 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1331 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1332 }
1333 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1334 tmp_tx->next_tx_desc = db->first_tx_desc;
1335
1336 /* Init Receive descriptor chain */
1337 tmp_rx_dma=db->first_rx_desc_dma;
1338 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1339 tmp_rx->rdes0 = cpu_to_le32(0);
1340 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1341 tmp_rx_dma += sizeof(struct rx_desc);
1342 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1343 tmp_rx->next_rx_desc = tmp_rx + 1;
1344 }
1345 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1346 tmp_rx->next_rx_desc = db->first_rx_desc;
1347
1348 /* pre-allocate Rx buffer */
1349 allocate_rx_buffer(db);
1350}
1351
1352
1353/*
1354 * Update CR6 value
945a7876 1355 * Firstly stop ULI526X, then written value and start
4689ced9
PC		 1356 */
1357
1358static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1359{
1360
1361 outl(cr6_data, ioaddr + DCR6);
1362 udelay(5);
1363}
1364
1365
1366/*
1367 * Send a setup frame for M5261/M5263
945a7876 1368 * This setup frame initialize ULI526X address filter mode
4689ced9
PC		 1369 */
1370
945a7876 1371static void send_filter_frame(struct net_device *dev, int mc_cnt)
4689ced9
PC		 1372{
1373 struct uli526x_board_info *db = netdev_priv(dev);
1374 struct dev_mc_list *mcptr;
1375 struct tx_desc *txptr;
1376 u16 * addrptr;
1377 u32 * suptr;
1378 int i;
1379
1380 ULI526X_DBUG(0, "send_filter_frame()", 0);
1381
1382 txptr = db->tx_insert_ptr;
1383 suptr = (u32 *) txptr->tx_buf_ptr;
1384
1385 /* Node address */
1386 addrptr = (u16 *) dev->dev_addr;
1387 *suptr++ = addrptr[0];
1388 *suptr++ = addrptr[1];
1389 *suptr++ = addrptr[2];
1390
1391 /* broadcast address */
1392 *suptr++ = 0xffff;
1393 *suptr++ = 0xffff;
1394 *suptr++ = 0xffff;
1395
1396 /* fit the multicast address */
1397 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1398 addrptr = (u16 *) mcptr->dmi_addr;
1399 *suptr++ = addrptr[0];
1400 *suptr++ = addrptr[1];
1401 *suptr++ = addrptr[2];
1402 }
1403
1404 for (; i<14; i++) {
1405 *suptr++ = 0xffff;
1406 *suptr++ = 0xffff;
1407 *suptr++ = 0xffff;
1408 }
1409
1410 /* prepare the setup frame */
1411 db->tx_insert_ptr = txptr->next_tx_desc;
1412 txptr->tdes1 = cpu_to_le32(0x890000c0);
1413
1414 /* Resource Check and Send the setup packet */
1415 if (db->tx_packet_cnt < TX_DESC_CNT) {
1416 /* Resource Empty */
1417 db->tx_packet_cnt++;
1418 txptr->tdes0 = cpu_to_le32(0x80000000);
1419 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1420 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1421 update_cr6(db->cr6_data, dev->base_addr);
1422 dev->trans_start = jiffies;
1423 } else
1424 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1425}
1426
1427
1428/*
1429 * Allocate rx buffer,
1430 * As possible as allocate maxiumn Rx buffer
1431 */
1432
1433static void allocate_rx_buffer(struct uli526x_board_info *db)
1434{
1435 struct rx_desc *rxptr;
1436 struct sk_buff *skb;
1437
1438 rxptr = db->rx_insert_ptr;
1439
1440 while(db->rx_avail_cnt < RX_DESC_CNT) {
1441 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1442 break;
1443 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
27a884dc
ACM		 1444 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1445 skb_tail_pointer(skb),
1446 RX_ALLOC_SIZE,
1447 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1448 wmb();
1449 rxptr->rdes0 = cpu_to_le32(0x80000000);
1450 rxptr = rxptr->next_rx_desc;
1451 db->rx_avail_cnt++;
1452 }
1453
1454 db->rx_insert_ptr = rxptr;
1455}
1456
1457
1458/*
1459 * Read one word data from the serial ROM
1460 */
1461
1462static u16 read_srom_word(long ioaddr, int offset)
1463{
1464 int i;
1465 u16 srom_data = 0;
1466 long cr9_ioaddr = ioaddr + DCR9;
1467
1468 outl(CR9_SROM_READ, cr9_ioaddr);
1469 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1470
1471 /* Send the Read Command 110b */
1472 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1473 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1474 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1475
1476 /* Send the offset */
1477 for (i = 5; i >= 0; i--) {
1478 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1479 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1480 }
1481
1482 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1483
1484 for (i = 16; i > 0; i--) {
1485 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1486 udelay(5);
1487 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1488 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1489 udelay(5);
1490 }
1491
1492 outl(CR9_SROM_READ, cr9_ioaddr);
1493 return srom_data;
1494}
1495
1496
1497/*
1498 * Auto sense the media mode
1499 */
1500
1501static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1502{
1503 u8 ErrFlag = 0;
1504 u16 phy_mode;
1505
1506 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1507 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1508
1509 if ( (phy_mode & 0x24) == 0x24 ) {
f3b197ac 1510
4689ced9
PC		 1511 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1512 if(phy_mode&0x8000)
1513 phy_mode = 0x8000;
1514 else if(phy_mode&0x4000)
1515 phy_mode = 0x4000;
1516 else if(phy_mode&0x2000)
1517 phy_mode = 0x2000;
1518 else
1519 phy_mode = 0x1000;
f3b197ac 1520
4689ced9
PC		 1521 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1522 switch (phy_mode) {
1523 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1524 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1525 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1526 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1527 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1528 }
1529 } else {
1530 db->op_mode = ULI526X_10MHF;
1531 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1532 ErrFlag = 1;
1533 }
1534
1535 return ErrFlag;
1536}
1537
1538
1539/*
1540 * Set 10/100 phyxcer capability
1541 * AUTO mode : phyxcer register4 is NIC capability
1542 * Force mode: phyxcer register4 is the force media
1543 */
1544
1545static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1546{
1547 u16 phy_reg;
f3b197ac 1548
4689ced9
PC		 1549 /* Phyxcer capability setting */
1550 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1551
1552 if (db->media_mode & ULI526X_AUTO) {
1553 /* AUTO Mode */
1554 phy_reg |= db->PHY_reg4;
1555 } else {
1556 /* Force Mode */
1557 switch(db->media_mode) {
1558 case ULI526X_10MHF: phy_reg |= 0x20; break;
1559 case ULI526X_10MFD: phy_reg |= 0x40; break;
1560 case ULI526X_100MHF: phy_reg |= 0x80; break;
1561 case ULI526X_100MFD: phy_reg |= 0x100; break;
1562 }
f3b197ac 1563
4689ced9
PC		 1564 }
1565
1566 /* Write new capability to Phyxcer Reg4 */
1567 if ( !(phy_reg & 0x01e0)) {
1568 phy_reg|=db->PHY_reg4;
1569 db->media_mode|=ULI526X_AUTO;
1570 }
1571 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1572
1573 /* Restart Auto-Negotiation */
1574 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1575 udelay(50);
1576}
1577
1578
1579/*
1580 * Process op-mode
1581 AUTO mode : PHY controller in Auto-negotiation Mode
1582 * Force mode: PHY controller in force mode with HUB
1583 * N-way force capability with SWITCH
1584 */
1585
1586static void uli526x_process_mode(struct uli526x_board_info *db)
1587{
1588 u16 phy_reg;
1589
1590 /* Full Duplex Mode Check */
1591 if (db->op_mode & 0x4)
1592 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1593 else
1594 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1595
1596 update_cr6(db->cr6_data, db->ioaddr);
1597
1598 /* 10/100M phyxcer force mode need */
1599 if ( !(db->media_mode & 0x8)) {
1600 /* Forece Mode */
1601 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1602 if ( !(phy_reg & 0x1) ) {
1603 /* parter without N-Way capability */
1604 phy_reg = 0x0;
1605 switch(db->op_mode) {
1606 case ULI526X_10MHF: phy_reg = 0x0; break;
1607 case ULI526X_10MFD: phy_reg = 0x100; break;
1608 case ULI526X_100MHF: phy_reg = 0x2000; break;
1609 case ULI526X_100MFD: phy_reg = 0x2100; break;
1610 }
1611 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
4689ced9
PC		 1612 }
1613 }
1614}
1615
1616
1617/*
1618 * Write a word to Phy register
1619 */
1620
1621static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1622{
1623 u16 i;
1624 unsigned long ioaddr;
1625
1626 if(chip_id == PCI_ULI5263_ID)
1627 {
1628 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1629 return;
1630 }
1631 /* M5261/M5263 Chip */
1632 ioaddr = iobase + DCR9;
1633
1634 /* Send 33 synchronization clock to Phy controller */
1635 for (i = 0; i < 35; i++)
1636 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1637
1638 /* Send start command(01) to Phy */
1639 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1640 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1641
1642 /* Send write command(01) to Phy */
1643 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1644 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1645
1646 /* Send Phy address */
1647 for (i = 0x10; i > 0; i = i >> 1)
1648 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1649
1650 /* Send register address */
1651 for (i = 0x10; i > 0; i = i >> 1)
1652 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1653
1654 /* written trasnition */
1655 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1656 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1657
1658 /* Write a word data to PHY controller */
1659 for ( i = 0x8000; i > 0; i >>= 1)
1660 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
f3b197ac 1661
4689ced9
PC		 1662}
1663
1664
1665/*
1666 * Read a word data from phy register
1667 */
1668
1669static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1670{
1671 int i;
1672 u16 phy_data;
1673 unsigned long ioaddr;
1674
1675 if(chip_id == PCI_ULI5263_ID)
1676 return phy_readby_cr10(iobase, phy_addr, offset);
1677 /* M5261/M5263 Chip */
1678 ioaddr = iobase + DCR9;
f3b197ac 1679
4689ced9
PC		 1680 /* Send 33 synchronization clock to Phy controller */
1681 for (i = 0; i < 35; i++)
1682 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1683
1684 /* Send start command(01) to Phy */
1685 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1686 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1687
1688 /* Send read command(10) to Phy */
1689 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1690 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1691
1692 /* Send Phy address */
1693 for (i = 0x10; i > 0; i = i >> 1)
1694 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1695
1696 /* Send register address */
1697 for (i = 0x10; i > 0; i = i >> 1)
1698 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1699
1700 /* Skip transition state */
1701 phy_read_1bit(ioaddr, chip_id);
1702
1703 /* read 16bit data */
1704 for (phy_data = 0, i = 0; i < 16; i++) {
1705 phy_data <<= 1;
1706 phy_data |= phy_read_1bit(ioaddr, chip_id);
1707 }
1708
1709 return phy_data;
1710}
1711
1712static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1713{
1714 unsigned long ioaddr,cr10_value;
f3b197ac 1715
4689ced9
PC		 1716 ioaddr = iobase + DCR10;
1717 cr10_value = phy_addr;
1718 cr10_value = (cr10_value<<5) + offset;
1719 cr10_value = (cr10_value<<16) + 0x08000000;
1720 outl(cr10_value,ioaddr);
1721 udelay(1);
1722 while(1)
1723 {
1724 cr10_value = inl(ioaddr);
1725 if(cr10_value&0x10000000)
1726 break;
1727 }
1728 return (cr10_value&0x0ffff);
1729}
1730
1731static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1732{
1733 unsigned long ioaddr,cr10_value;
f3b197ac 1734
4689ced9
PC		 1735 ioaddr = iobase + DCR10;
1736 cr10_value = phy_addr;
1737 cr10_value = (cr10_value<<5) + offset;
1738 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1739 outl(cr10_value,ioaddr);
1740 udelay(1);
1741}
1742/*
1743 * Write one bit data to Phy Controller
1744 */
1745
1746static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1747{
1748 outl(phy_data , ioaddr); /* MII Clock Low */
1749 udelay(1);
1750 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1751 udelay(1);
1752 outl(phy_data , ioaddr); /* MII Clock Low */
1753 udelay(1);
1754}
1755
1756
1757/*
1758 * Read one bit phy data from PHY controller
1759 */
1760
1761static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1762{
1763 u16 phy_data;
f3b197ac 1764
4689ced9
PC		 1765 outl(0x50000 , ioaddr);
1766 udelay(1);
1767 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1768 outl(0x40000 , ioaddr);
1769 udelay(1);
1770
1771 return phy_data;
1772}
1773
1774
1775static struct pci_device_id uli526x_pci_tbl[] = {
1776 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1777 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1778 { 0, }
1779};
1780MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1781
1782
1783static struct pci_driver uli526x_driver = {
1784 .name = "uli526x",
1785 .id_table = uli526x_pci_tbl,
1786 .probe = uli526x_init_one,
1787 .remove = __devexit_p(uli526x_remove_one),
b6aec32a
RW		 1788 .suspend = uli526x_suspend,
1789 .resume = uli526x_resume,
4689ced9
PC		 1790};
1791
1792MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1793MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1794MODULE_LICENSE("GPL");
1795
c213460f
ES		 1796module_param(debug, int, 0644);
1797module_param(mode, int, 0);
1798module_param(cr6set, int, 0);
4689ced9
PC		 1799MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1800MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1801
1802/* Description:
1803 * when user used insmod to add module, system invoked init_module()
945a7876 1804 * to register the services.
4689ced9
PC		 1805 */
1806
1807static int __init uli526x_init_module(void)
1808{
4689ced9
PC		 1809
1810 printk(version);
1811 printed_version = 1;
1812
1813 ULI526X_DBUG(0, "init_module() ", debug);
1814
1815 if (debug)
1816 uli526x_debug = debug; /* set debug flag */
1817 if (cr6set)
1818 uli526x_cr6_user_set = cr6set;
1819
e1c3e501 1820 switch (mode) {
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PC		 1821 case ULI526X_10MHF:
1822 case ULI526X_100MHF:
1823 case ULI526X_10MFD:
1824 case ULI526X_100MFD:
1825 uli526x_media_mode = mode;
1826 break;
e1c3e501
HK		 1827 default:
1828 uli526x_media_mode = ULI526X_AUTO;
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PC		 1829 break;
1830 }
1831
e1c3e501 1832 return pci_register_driver(&uli526x_driver);
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PC		 1833}
1834
1835
1836/*
1837 * Description:
1838 * when user used rmmod to delete module, system invoked clean_module()
1839 * to un-register all registered services.
1840 */
1841
1842static void __exit uli526x_cleanup_module(void)
1843{
1844 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1845 pci_unregister_driver(&uli526x_driver);
1846}
1847
1848module_init(uli526x_init_module);
1849module_exit(uli526x_cleanup_module);
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