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Commit | Line | Data |
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4689ced9 PC |
1 | /* |
2 | This program is free software; you can redistribute it and/or | |
3 | modify it under the terms of the GNU General Public License | |
4 | as published by the Free Software Foundation; either version 2 | |
5 | of the License, or (at your option) any later version. | |
6 | ||
7 | This program is distributed in the hope that it will be useful, | |
8 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | GNU General Public License for more details. | |
11 | ||
f3b197ac | 12 | |
4689ced9 PC |
13 | */ |
14 | ||
e02fb7aa JP |
15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
16 | ||
4689ced9 PC |
17 | #define DRV_NAME "uli526x" |
18 | #define DRV_VERSION "0.9.3" | |
19 | #define DRV_RELDATE "2005-7-29" | |
20 | ||
21 | #include <linux/module.h> | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/timer.h> | |
4689ced9 PC |
26 | #include <linux/errno.h> |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/ethtool.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/spinlock.h> | |
6cafa99f | 38 | #include <linux/dma-mapping.h> |
1977f032 | 39 | #include <linux/bitops.h> |
4689ced9 PC |
40 | |
41 | #include <asm/processor.h> | |
4689ced9 PC |
42 | #include <asm/io.h> |
43 | #include <asm/dma.h> | |
44 | #include <asm/uaccess.h> | |
45 | ||
46 | ||
47 | /* Board/System/Debug information/definition ---------------- */ | |
48 | #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/ | |
49 | #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/ | |
50 | ||
51 | #define ULI526X_IO_SIZE 0x100 | |
52 | #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */ | |
53 | #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */ | |
54 | #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ | |
55 | #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ | |
56 | #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) | |
57 | #define TX_BUF_ALLOC 0x600 | |
58 | #define RX_ALLOC_SIZE 0x620 | |
59 | #define ULI526X_RESET 1 | |
60 | #define CR0_DEFAULT 0 | |
945a7876 | 61 | #define CR6_DEFAULT 0x22200000 |
4689ced9 PC |
62 | #define CR7_DEFAULT 0x180c1 |
63 | #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ | |
64 | #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ | |
65 | #define MAX_PACKET_SIZE 1514 | |
66 | #define ULI5261_MAX_MULTICAST 14 | |
67 | #define RX_COPY_SIZE 100 | |
68 | #define MAX_CHECK_PACKET 0x8000 | |
69 | ||
70 | #define ULI526X_10MHF 0 | |
71 | #define ULI526X_100MHF 1 | |
72 | #define ULI526X_10MFD 4 | |
73 | #define ULI526X_100MFD 5 | |
74 | #define ULI526X_AUTO 8 | |
75 | ||
76 | #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */ | |
77 | #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */ | |
78 | #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */ | |
79 | #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */ | |
80 | #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */ | |
81 | #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */ | |
82 | ||
83 | #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */ | |
84 | #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */ | |
85 | #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */ | |
86 | ||
e02fb7aa JP |
87 | #define ULI526X_DBUG(dbug_now, msg, value) \ |
88 | do { \ | |
89 | if (uli526x_debug || (dbug_now)) \ | |
90 | pr_err("%s %lx\n", (msg), (long) (value)); \ | |
91 | } while (0) | |
4689ced9 | 92 | |
e02fb7aa JP |
93 | #define SHOW_MEDIA_TYPE(mode) \ |
94 | pr_err("Change Speed to %sMhz %s duplex\n", \ | |
95 | mode & 1 ? "100" : "10", \ | |
96 | mode & 4 ? "full" : "half"); | |
4689ced9 PC |
97 | |
98 | ||
99 | /* CR9 definition: SROM/MII */ | |
100 | #define CR9_SROM_READ 0x4800 | |
101 | #define CR9_SRCS 0x1 | |
102 | #define CR9_SRCLK 0x2 | |
103 | #define CR9_CRDOUT 0x8 | |
104 | #define SROM_DATA_0 0x0 | |
105 | #define SROM_DATA_1 0x4 | |
106 | #define PHY_DATA_1 0x20000 | |
107 | #define PHY_DATA_0 0x00000 | |
108 | #define MDCLKH 0x10000 | |
109 | ||
110 | #define PHY_POWER_DOWN 0x800 | |
111 | ||
112 | #define SROM_V41_CODE 0x14 | |
113 | ||
945a7876 PC |
114 | #define SROM_CLK_WRITE(data, ioaddr) \ |
115 | outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \ | |
116 | udelay(5); \ | |
117 | outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \ | |
118 | udelay(5); \ | |
119 | outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \ | |
120 | udelay(5); | |
4689ced9 PC |
121 | |
122 | /* Structure/enum declaration ------------------------------- */ | |
123 | struct tx_desc { | |
c559a5bc | 124 | __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ |
4689ced9 PC |
125 | char *tx_buf_ptr; /* Data for us */ |
126 | struct tx_desc *next_tx_desc; | |
127 | } __attribute__(( aligned(32) )); | |
128 | ||
129 | struct rx_desc { | |
c559a5bc | 130 | __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ |
4689ced9 PC |
131 | struct sk_buff *rx_skb_ptr; /* Data for us */ |
132 | struct rx_desc *next_rx_desc; | |
133 | } __attribute__(( aligned(32) )); | |
134 | ||
135 | struct uli526x_board_info { | |
136 | u32 chip_id; /* Chip vendor/Device ID */ | |
945a7876 | 137 | struct net_device *next_dev; /* next device */ |
4689ced9 PC |
138 | struct pci_dev *pdev; /* PCI device */ |
139 | spinlock_t lock; | |
140 | ||
141 | long ioaddr; /* I/O base address */ | |
142 | u32 cr0_data; | |
143 | u32 cr5_data; | |
144 | u32 cr6_data; | |
145 | u32 cr7_data; | |
146 | u32 cr15_data; | |
147 | ||
148 | /* pointer for memory physical address */ | |
149 | dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */ | |
150 | dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */ | |
151 | dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */ | |
152 | dma_addr_t first_tx_desc_dma; | |
153 | dma_addr_t first_rx_desc_dma; | |
154 | ||
155 | /* descriptor pointer */ | |
156 | unsigned char *buf_pool_ptr; /* Tx buffer pool memory */ | |
157 | unsigned char *buf_pool_start; /* Tx buffer pool align dword */ | |
158 | unsigned char *desc_pool_ptr; /* descriptor pool memory */ | |
159 | struct tx_desc *first_tx_desc; | |
160 | struct tx_desc *tx_insert_ptr; | |
161 | struct tx_desc *tx_remove_ptr; | |
162 | struct rx_desc *first_rx_desc; | |
163 | struct rx_desc *rx_insert_ptr; | |
164 | struct rx_desc *rx_ready_ptr; /* packet come pointer */ | |
165 | unsigned long tx_packet_cnt; /* transmitted packet count */ | |
166 | unsigned long rx_avail_cnt; /* available rx descriptor count */ | |
167 | unsigned long interval_rx_cnt; /* rx packet count a callback time */ | |
168 | ||
169 | u16 dbug_cnt; | |
170 | u16 NIC_capability; /* NIC media capability */ | |
171 | u16 PHY_reg4; /* Saved Phyxcer register 4 value */ | |
172 | ||
173 | u8 media_mode; /* user specify media mode */ | |
174 | u8 op_mode; /* real work media mode */ | |
175 | u8 phy_addr; | |
176 | u8 link_failed; /* Ever link failed */ | |
177 | u8 wait_reset; /* Hardware failed, need to reset */ | |
178 | struct timer_list timer; | |
179 | ||
4689ced9 PC |
180 | /* Driver defined statistic counter */ |
181 | unsigned long tx_fifo_underrun; | |
182 | unsigned long tx_loss_carrier; | |
183 | unsigned long tx_no_carrier; | |
184 | unsigned long tx_late_collision; | |
185 | unsigned long tx_excessive_collision; | |
186 | unsigned long tx_jabber_timeout; | |
187 | unsigned long reset_count; | |
188 | unsigned long reset_cr8; | |
189 | unsigned long reset_fatal; | |
190 | unsigned long reset_TXtimeout; | |
191 | ||
192 | /* NIC SROM data */ | |
193 | unsigned char srom[128]; | |
f3b197ac | 194 | u8 init; |
4689ced9 PC |
195 | }; |
196 | ||
197 | enum uli526x_offsets { | |
198 | DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, | |
199 | DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, | |
200 | DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, | |
201 | DCR15 = 0x78 | |
202 | }; | |
203 | ||
204 | enum uli526x_CR6_bits { | |
205 | CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, | |
206 | CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, | |
207 | CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 | |
208 | }; | |
209 | ||
210 | /* Global variable declaration ----------------------------- */ | |
211 | static int __devinitdata printed_version; | |
03f54b3d | 212 | static const char version[] __devinitconst = |
4689ced9 PC |
213 | KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version " |
214 | DRV_VERSION " (" DRV_RELDATE ")\n"; | |
215 | ||
216 | static int uli526x_debug; | |
217 | static unsigned char uli526x_media_mode = ULI526X_AUTO; | |
218 | static u32 uli526x_cr6_user_set; | |
219 | ||
220 | /* For module input parameter */ | |
221 | static int debug; | |
222 | static u32 cr6set; | |
99bb2579 | 223 | static int mode = 8; |
4689ced9 PC |
224 | |
225 | /* function declaration ------------------------------------- */ | |
945a7876 | 226 | static int uli526x_open(struct net_device *); |
ad096463 SH |
227 | static netdev_tx_t uli526x_start_xmit(struct sk_buff *, |
228 | struct net_device *); | |
945a7876 | 229 | static int uli526x_stop(struct net_device *); |
945a7876 | 230 | static void uli526x_set_filter_mode(struct net_device *); |
7282d491 | 231 | static const struct ethtool_ops netdev_ethtool_ops; |
945a7876 | 232 | static u16 read_srom_word(long, int); |
7d12e780 | 233 | static irqreturn_t uli526x_interrupt(int, void *); |
7fa0cba3 AV |
234 | #ifdef CONFIG_NET_POLL_CONTROLLER |
235 | static void uli526x_poll(struct net_device *dev); | |
236 | #endif | |
4689ced9 PC |
237 | static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long); |
238 | static void allocate_rx_buffer(struct uli526x_board_info *); | |
239 | static void update_cr6(u32, unsigned long); | |
945a7876 | 240 | static void send_filter_frame(struct net_device *, int); |
4689ced9 PC |
241 | static u16 phy_read(unsigned long, u8, u8, u32); |
242 | static u16 phy_readby_cr10(unsigned long, u8, u8); | |
243 | static void phy_write(unsigned long, u8, u8, u16, u32); | |
244 | static void phy_writeby_cr10(unsigned long, u8, u8, u16); | |
245 | static void phy_write_1bit(unsigned long, u32, u32); | |
246 | static u16 phy_read_1bit(unsigned long, u32); | |
247 | static u8 uli526x_sense_speed(struct uli526x_board_info *); | |
248 | static void uli526x_process_mode(struct uli526x_board_info *); | |
249 | static void uli526x_timer(unsigned long); | |
945a7876 PC |
250 | static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *); |
251 | static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *); | |
4689ced9 | 252 | static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *); |
945a7876 | 253 | static void uli526x_dynamic_reset(struct net_device *); |
4689ced9 | 254 | static void uli526x_free_rxbuffer(struct uli526x_board_info *); |
945a7876 | 255 | static void uli526x_init(struct net_device *); |
4689ced9 PC |
256 | static void uli526x_set_phyxcer(struct uli526x_board_info *); |
257 | ||
945a7876 | 258 | /* ULI526X network board routine ---------------------------- */ |
4689ced9 | 259 | |
dfefe02b SH |
260 | static const struct net_device_ops netdev_ops = { |
261 | .ndo_open = uli526x_open, | |
262 | .ndo_stop = uli526x_stop, | |
263 | .ndo_start_xmit = uli526x_start_xmit, | |
264 | .ndo_set_multicast_list = uli526x_set_filter_mode, | |
265 | .ndo_change_mtu = eth_change_mtu, | |
266 | .ndo_set_mac_address = eth_mac_addr, | |
267 | .ndo_validate_addr = eth_validate_addr, | |
268 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
269 | .ndo_poll_controller = uli526x_poll, | |
270 | #endif | |
271 | }; | |
272 | ||
4689ced9 | 273 | /* |
945a7876 | 274 | * Search ULI526X board, allocate space and register it |
4689ced9 PC |
275 | */ |
276 | ||
277 | static int __devinit uli526x_init_one (struct pci_dev *pdev, | |
278 | const struct pci_device_id *ent) | |
279 | { | |
280 | struct uli526x_board_info *db; /* board information structure */ | |
281 | struct net_device *dev; | |
282 | int i, err; | |
f3b197ac | 283 | |
4689ced9 PC |
284 | ULI526X_DBUG(0, "uli526x_init_one()", 0); |
285 | ||
286 | if (!printed_version++) | |
287 | printk(version); | |
288 | ||
289 | /* Init network device */ | |
290 | dev = alloc_etherdev(sizeof(*db)); | |
291 | if (dev == NULL) | |
292 | return -ENOMEM; | |
4689ced9 PC |
293 | SET_NETDEV_DEV(dev, &pdev->dev); |
294 | ||
284901a9 | 295 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { |
e02fb7aa | 296 | pr_warning("32-bit PCI DMA not available\n"); |
4689ced9 PC |
297 | err = -ENODEV; |
298 | goto err_out_free; | |
299 | } | |
300 | ||
301 | /* Enable Master/IO access, Disable memory access */ | |
302 | err = pci_enable_device(pdev); | |
303 | if (err) | |
304 | goto err_out_free; | |
305 | ||
306 | if (!pci_resource_start(pdev, 0)) { | |
e02fb7aa | 307 | pr_err("I/O base is zero\n"); |
4689ced9 PC |
308 | err = -ENODEV; |
309 | goto err_out_disable; | |
310 | } | |
311 | ||
312 | if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) { | |
e02fb7aa | 313 | pr_err("Allocated I/O size too small\n"); |
4689ced9 PC |
314 | err = -ENODEV; |
315 | goto err_out_disable; | |
316 | } | |
317 | ||
318 | if (pci_request_regions(pdev, DRV_NAME)) { | |
e02fb7aa | 319 | pr_err("Failed to request PCI regions\n"); |
4689ced9 PC |
320 | err = -ENODEV; |
321 | goto err_out_disable; | |
322 | } | |
323 | ||
4689ced9 PC |
324 | /* Init system & device */ |
325 | db = netdev_priv(dev); | |
326 | ||
327 | /* Allocate Tx/Rx descriptor memory */ | |
328 | db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr); | |
945a7876 PC |
329 | if(db->desc_pool_ptr == NULL) |
330 | { | |
331 | err = -ENOMEM; | |
332 | goto err_out_nomem; | |
333 | } | |
4689ced9 | 334 | db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr); |
945a7876 PC |
335 | if(db->buf_pool_ptr == NULL) |
336 | { | |
337 | err = -ENOMEM; | |
338 | goto err_out_nomem; | |
339 | } | |
f3b197ac | 340 | |
4689ced9 PC |
341 | db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; |
342 | db->first_tx_desc_dma = db->desc_pool_dma_ptr; | |
343 | db->buf_pool_start = db->buf_pool_ptr; | |
344 | db->buf_pool_dma_start = db->buf_pool_dma_ptr; | |
345 | ||
346 | db->chip_id = ent->driver_data; | |
347 | db->ioaddr = pci_resource_start(pdev, 0); | |
f3b197ac | 348 | |
4689ced9 PC |
349 | db->pdev = pdev; |
350 | db->init = 1; | |
f3b197ac | 351 | |
4689ced9 PC |
352 | dev->base_addr = db->ioaddr; |
353 | dev->irq = pdev->irq; | |
354 | pci_set_drvdata(pdev, dev); | |
f3b197ac | 355 | |
4689ced9 | 356 | /* Register some necessary functions */ |
dfefe02b | 357 | dev->netdev_ops = &netdev_ops; |
4689ced9 | 358 | dev->ethtool_ops = &netdev_ethtool_ops; |
dfefe02b | 359 | |
4689ced9 PC |
360 | spin_lock_init(&db->lock); |
361 | ||
f3b197ac | 362 | |
4689ced9 PC |
363 | /* read 64 word srom data */ |
364 | for (i = 0; i < 64; i++) | |
c559a5bc | 365 | ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i)); |
4689ced9 PC |
366 | |
367 | /* Set Node address */ | |
945a7876 | 368 | if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */ |
4689ced9 PC |
369 | { |
370 | outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode | |
371 | outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port | |
372 | outl(0, db->ioaddr + DCR14); //Clear reset port | |
373 | outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer | |
374 | outl(0, db->ioaddr + DCR14); //Clear reset port | |
375 | outl(0, db->ioaddr + DCR13); //Clear CR13 | |
376 | outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port | |
377 | //Read MAC address from CR14 | |
378 | for (i = 0; i < 6; i++) | |
379 | dev->dev_addr[i] = inl(db->ioaddr + DCR14); | |
380 | //Read end | |
381 | outl(0, db->ioaddr + DCR13); //Clear CR13 | |
382 | outl(0, db->ioaddr + DCR0); //Clear CR0 | |
383 | udelay(10); | |
384 | } | |
385 | else /*Exist SROM*/ | |
386 | { | |
387 | for (i = 0; i < 6; i++) | |
388 | dev->dev_addr[i] = db->srom[20 + i]; | |
389 | } | |
390 | err = register_netdev (dev); | |
391 | if (err) | |
392 | goto err_out_res; | |
393 | ||
e02fb7aa JP |
394 | dev_info(&dev->dev, "ULi M%04lx at pci%s, %pM, irq %d\n", |
395 | ent->driver_data >> 16, pci_name(pdev), | |
396 | dev->dev_addr, dev->irq); | |
4689ced9 PC |
397 | |
398 | pci_set_master(pdev); | |
399 | ||
400 | return 0; | |
401 | ||
402 | err_out_res: | |
403 | pci_release_regions(pdev); | |
945a7876 PC |
404 | err_out_nomem: |
405 | if(db->desc_pool_ptr) | |
406 | pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, | |
407 | db->desc_pool_ptr, db->desc_pool_dma_ptr); | |
f3b197ac | 408 | |
945a7876 PC |
409 | if(db->buf_pool_ptr != NULL) |
410 | pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, | |
411 | db->buf_pool_ptr, db->buf_pool_dma_ptr); | |
4689ced9 PC |
412 | err_out_disable: |
413 | pci_disable_device(pdev); | |
414 | err_out_free: | |
415 | pci_set_drvdata(pdev, NULL); | |
416 | free_netdev(dev); | |
417 | ||
418 | return err; | |
419 | } | |
420 | ||
421 | ||
422 | static void __devexit uli526x_remove_one (struct pci_dev *pdev) | |
423 | { | |
424 | struct net_device *dev = pci_get_drvdata(pdev); | |
425 | struct uli526x_board_info *db = netdev_priv(dev); | |
426 | ||
427 | ULI526X_DBUG(0, "uli526x_remove_one()", 0); | |
428 | ||
945a7876 PC |
429 | pci_free_consistent(db->pdev, sizeof(struct tx_desc) * |
430 | DESC_ALL_CNT + 0x20, db->desc_pool_ptr, | |
431 | db->desc_pool_dma_ptr); | |
432 | pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, | |
433 | db->buf_pool_ptr, db->buf_pool_dma_ptr); | |
434 | unregister_netdev(dev); | |
435 | pci_release_regions(pdev); | |
436 | free_netdev(dev); /* free board information */ | |
437 | pci_set_drvdata(pdev, NULL); | |
438 | pci_disable_device(pdev); | |
4689ced9 PC |
439 | ULI526X_DBUG(0, "uli526x_remove_one() exit", 0); |
440 | } | |
441 | ||
442 | ||
443 | /* | |
444 | * Open the interface. | |
945a7876 | 445 | * The interface is opened whenever "ifconfig" activates it. |
4689ced9 PC |
446 | */ |
447 | ||
945a7876 | 448 | static int uli526x_open(struct net_device *dev) |
4689ced9 PC |
449 | { |
450 | int ret; | |
451 | struct uli526x_board_info *db = netdev_priv(dev); | |
f3b197ac | 452 | |
4689ced9 PC |
453 | ULI526X_DBUG(0, "uli526x_open", 0); |
454 | ||
4689ced9 PC |
455 | /* system variable init */ |
456 | db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set; | |
4689ced9 PC |
457 | db->tx_packet_cnt = 0; |
458 | db->rx_avail_cnt = 0; | |
459 | db->link_failed = 1; | |
460 | netif_carrier_off(dev); | |
461 | db->wait_reset = 0; | |
462 | ||
463 | db->NIC_capability = 0xf; /* All capability*/ | |
464 | db->PHY_reg4 = 0x1e0; | |
465 | ||
466 | /* CR6 operation mode decision */ | |
467 | db->cr6_data |= ULI526X_TXTH_256; | |
468 | db->cr0_data = CR0_DEFAULT; | |
f3b197ac | 469 | |
945a7876 | 470 | /* Initialize ULI526X board */ |
4689ced9 PC |
471 | uli526x_init(dev); |
472 | ||
a0607fd3 | 473 | ret = request_irq(dev->irq, uli526x_interrupt, IRQF_SHARED, dev->name, dev); |
afd8e399 AV |
474 | if (ret) |
475 | return ret; | |
476 | ||
4689ced9 PC |
477 | /* Active System Interface */ |
478 | netif_wake_queue(dev); | |
479 | ||
480 | /* set and active a timer process */ | |
481 | init_timer(&db->timer); | |
482 | db->timer.expires = ULI526X_TIMER_WUT + HZ * 2; | |
483 | db->timer.data = (unsigned long)dev; | |
484 | db->timer.function = &uli526x_timer; | |
485 | add_timer(&db->timer); | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | ||
945a7876 | 491 | /* Initialize ULI526X board |
4689ced9 | 492 | * Reset ULI526X board |
945a7876 | 493 | * Initialize TX/Rx descriptor chain structure |
4689ced9 PC |
494 | * Send the set-up frame |
495 | * Enable Tx/Rx machine | |
496 | */ | |
497 | ||
945a7876 | 498 | static void uli526x_init(struct net_device *dev) |
4689ced9 PC |
499 | { |
500 | struct uli526x_board_info *db = netdev_priv(dev); | |
501 | unsigned long ioaddr = db->ioaddr; | |
502 | u8 phy_tmp; | |
7a7d23da | 503 | u8 timeout; |
4689ced9 PC |
504 | u16 phy_value; |
505 | u16 phy_reg_reset; | |
506 | ||
7a7d23da | 507 | |
4689ced9 PC |
508 | ULI526X_DBUG(0, "uli526x_init()", 0); |
509 | ||
510 | /* Reset M526x MAC controller */ | |
511 | outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */ | |
512 | udelay(100); | |
513 | outl(db->cr0_data, ioaddr + DCR0); | |
514 | udelay(5); | |
515 | ||
516 | /* Phy addr : In some boards,M5261/M5263 phy address != 1 */ | |
517 | db->phy_addr = 1; | |
518 | for(phy_tmp=0;phy_tmp<32;phy_tmp++) | |
519 | { | |
520 | phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add | |
521 | if(phy_value != 0xffff&&phy_value!=0) | |
522 | { | |
523 | db->phy_addr = phy_tmp; | |
524 | break; | |
525 | } | |
526 | } | |
527 | if(phy_tmp == 32) | |
e02fb7aa | 528 | pr_warning("Can not find the phy address!!!"); |
4689ced9 PC |
529 | /* Parser SROM and media mode */ |
530 | db->media_mode = uli526x_media_mode; | |
531 | ||
7a7d23da | 532 | /* phyxcer capability setting */ |
4689ced9 PC |
533 | phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id); |
534 | phy_reg_reset = (phy_reg_reset | 0x8000); | |
535 | phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id); | |
7a7d23da GG |
536 | |
537 | /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management | |
538 | * functions") or phy data sheet for details on phy reset | |
539 | */ | |
4689ced9 | 540 | udelay(500); |
7a7d23da GG |
541 | timeout = 10; |
542 | while (timeout-- && | |
543 | phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000) | |
544 | udelay(100); | |
4689ced9 PC |
545 | |
546 | /* Process Phyxcer Media Mode */ | |
547 | uli526x_set_phyxcer(db); | |
548 | ||
549 | /* Media Mode Process */ | |
550 | if ( !(db->media_mode & ULI526X_AUTO) ) | |
551 | db->op_mode = db->media_mode; /* Force Mode */ | |
552 | ||
945a7876 | 553 | /* Initialize Transmit/Receive decriptor and CR3/4 */ |
4689ced9 PC |
554 | uli526x_descriptor_init(db, ioaddr); |
555 | ||
556 | /* Init CR6 to program M526X operation */ | |
557 | update_cr6(db->cr6_data, ioaddr); | |
558 | ||
559 | /* Send setup frame */ | |
560 | send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */ | |
561 | ||
562 | /* Init CR7, interrupt active bit */ | |
563 | db->cr7_data = CR7_DEFAULT; | |
564 | outl(db->cr7_data, ioaddr + DCR7); | |
565 | ||
566 | /* Init CR15, Tx jabber and Rx watchdog timer */ | |
567 | outl(db->cr15_data, ioaddr + DCR15); | |
568 | ||
569 | /* Enable ULI526X Tx/Rx function */ | |
570 | db->cr6_data |= CR6_RXSC | CR6_TXSC; | |
571 | update_cr6(db->cr6_data, ioaddr); | |
572 | } | |
573 | ||
574 | ||
575 | /* | |
576 | * Hardware start transmission. | |
577 | * Send a packet to media from the upper layer. | |
578 | */ | |
579 | ||
ad096463 SH |
580 | static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb, |
581 | struct net_device *dev) | |
4689ced9 PC |
582 | { |
583 | struct uli526x_board_info *db = netdev_priv(dev); | |
584 | struct tx_desc *txptr; | |
585 | unsigned long flags; | |
586 | ||
587 | ULI526X_DBUG(0, "uli526x_start_xmit", 0); | |
588 | ||
589 | /* Resource flag check */ | |
590 | netif_stop_queue(dev); | |
591 | ||
592 | /* Too large packet check */ | |
593 | if (skb->len > MAX_PACKET_SIZE) { | |
e02fb7aa | 594 | pr_err("big packet = %d\n", (u16)skb->len); |
4689ced9 | 595 | dev_kfree_skb(skb); |
6ed10654 | 596 | return NETDEV_TX_OK; |
4689ced9 PC |
597 | } |
598 | ||
599 | spin_lock_irqsave(&db->lock, flags); | |
600 | ||
601 | /* No Tx resource check, it never happen nromally */ | |
602 | if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) { | |
603 | spin_unlock_irqrestore(&db->lock, flags); | |
e02fb7aa | 604 | pr_err("No Tx resource %ld\n", db->tx_packet_cnt); |
5b548140 | 605 | return NETDEV_TX_BUSY; |
4689ced9 PC |
606 | } |
607 | ||
608 | /* Disable NIC interrupt */ | |
609 | outl(0, dev->base_addr + DCR7); | |
610 | ||
611 | /* transmit this packet */ | |
612 | txptr = db->tx_insert_ptr; | |
d626f62b | 613 | skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len); |
4689ced9 PC |
614 | txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len); |
615 | ||
616 | /* Point to next transmit free descriptor */ | |
617 | db->tx_insert_ptr = txptr->next_tx_desc; | |
618 | ||
619 | /* Transmit Packet Process */ | |
620 | if ( (db->tx_packet_cnt < TX_DESC_CNT) ) { | |
621 | txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ | |
622 | db->tx_packet_cnt++; /* Ready to send */ | |
623 | outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ | |
624 | dev->trans_start = jiffies; /* saved time stamp */ | |
625 | } | |
626 | ||
627 | /* Tx resource check */ | |
628 | if ( db->tx_packet_cnt < TX_FREE_DESC_CNT ) | |
629 | netif_wake_queue(dev); | |
630 | ||
631 | /* Restore CR7 to enable interrupt */ | |
632 | spin_unlock_irqrestore(&db->lock, flags); | |
633 | outl(db->cr7_data, dev->base_addr + DCR7); | |
f3b197ac | 634 | |
4689ced9 PC |
635 | /* free this SKB */ |
636 | dev_kfree_skb(skb); | |
637 | ||
6ed10654 | 638 | return NETDEV_TX_OK; |
4689ced9 PC |
639 | } |
640 | ||
641 | ||
642 | /* | |
643 | * Stop the interface. | |
644 | * The interface is stopped when it is brought. | |
645 | */ | |
646 | ||
945a7876 | 647 | static int uli526x_stop(struct net_device *dev) |
4689ced9 PC |
648 | { |
649 | struct uli526x_board_info *db = netdev_priv(dev); | |
650 | unsigned long ioaddr = dev->base_addr; | |
651 | ||
652 | ULI526X_DBUG(0, "uli526x_stop", 0); | |
653 | ||
654 | /* disable system */ | |
655 | netif_stop_queue(dev); | |
656 | ||
657 | /* deleted timer */ | |
658 | del_timer_sync(&db->timer); | |
659 | ||
660 | /* Reset & stop ULI526X board */ | |
661 | outl(ULI526X_RESET, ioaddr + DCR0); | |
662 | udelay(5); | |
663 | phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); | |
664 | ||
665 | /* free interrupt */ | |
666 | free_irq(dev->irq, dev); | |
667 | ||
668 | /* free allocated rx buffer */ | |
669 | uli526x_free_rxbuffer(db); | |
670 | ||
671 | #if 0 | |
672 | /* show statistic counter */ | |
673 | printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n", | |
674 | db->tx_fifo_underrun, db->tx_excessive_collision, | |
675 | db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier, | |
676 | db->tx_jabber_timeout, db->reset_count, db->reset_cr8, | |
677 | db->reset_fatal, db->reset_TXtimeout); | |
678 | #endif | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | ||
684 | /* | |
685 | * M5261/M5263 insterrupt handler | |
686 | * receive the packet to upper layer, free the transmitted packet | |
687 | */ | |
688 | ||
7d12e780 | 689 | static irqreturn_t uli526x_interrupt(int irq, void *dev_id) |
4689ced9 | 690 | { |
945a7876 | 691 | struct net_device *dev = dev_id; |
4689ced9 PC |
692 | struct uli526x_board_info *db = netdev_priv(dev); |
693 | unsigned long ioaddr = dev->base_addr; | |
694 | unsigned long flags; | |
695 | ||
4689ced9 PC |
696 | spin_lock_irqsave(&db->lock, flags); |
697 | outl(0, ioaddr + DCR7); | |
698 | ||
699 | /* Got ULI526X status */ | |
700 | db->cr5_data = inl(ioaddr + DCR5); | |
701 | outl(db->cr5_data, ioaddr + DCR5); | |
702 | if ( !(db->cr5_data & 0x180c1) ) { | |
7fa0cba3 | 703 | /* Restore CR7 to enable interrupt mask */ |
4689ced9 | 704 | outl(db->cr7_data, ioaddr + DCR7); |
7fa0cba3 | 705 | spin_unlock_irqrestore(&db->lock, flags); |
4689ced9 PC |
706 | return IRQ_HANDLED; |
707 | } | |
708 | ||
4689ced9 PC |
709 | /* Check system status */ |
710 | if (db->cr5_data & 0x2000) { | |
711 | /* system bus error happen */ | |
712 | ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data); | |
713 | db->reset_fatal++; | |
714 | db->wait_reset = 1; /* Need to RESET */ | |
715 | spin_unlock_irqrestore(&db->lock, flags); | |
716 | return IRQ_HANDLED; | |
717 | } | |
718 | ||
719 | /* Received the coming packet */ | |
720 | if ( (db->cr5_data & 0x40) && db->rx_avail_cnt ) | |
721 | uli526x_rx_packet(dev, db); | |
722 | ||
723 | /* reallocate rx descriptor buffer */ | |
724 | if (db->rx_avail_cnt<RX_DESC_CNT) | |
725 | allocate_rx_buffer(db); | |
726 | ||
727 | /* Free the transmitted descriptor */ | |
728 | if ( db->cr5_data & 0x01) | |
729 | uli526x_free_tx_pkt(dev, db); | |
730 | ||
731 | /* Restore CR7 to enable interrupt mask */ | |
732 | outl(db->cr7_data, ioaddr + DCR7); | |
733 | ||
734 | spin_unlock_irqrestore(&db->lock, flags); | |
735 | return IRQ_HANDLED; | |
736 | } | |
737 | ||
7fa0cba3 AV |
738 | #ifdef CONFIG_NET_POLL_CONTROLLER |
739 | static void uli526x_poll(struct net_device *dev) | |
740 | { | |
741 | /* ISR grabs the irqsave lock, so this should be safe */ | |
742 | uli526x_interrupt(dev->irq, dev); | |
743 | } | |
744 | #endif | |
4689ced9 PC |
745 | |
746 | /* | |
747 | * Free TX resource after TX complete | |
748 | */ | |
749 | ||
dfefe02b SH |
750 | static void uli526x_free_tx_pkt(struct net_device *dev, |
751 | struct uli526x_board_info * db) | |
4689ced9 PC |
752 | { |
753 | struct tx_desc *txptr; | |
4689ced9 PC |
754 | u32 tdes0; |
755 | ||
756 | txptr = db->tx_remove_ptr; | |
757 | while(db->tx_packet_cnt) { | |
758 | tdes0 = le32_to_cpu(txptr->tdes0); | |
759 | /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */ | |
760 | if (tdes0 & 0x80000000) | |
761 | break; | |
762 | ||
763 | /* A packet sent completed */ | |
764 | db->tx_packet_cnt--; | |
dfefe02b | 765 | dev->stats.tx_packets++; |
4689ced9 PC |
766 | |
767 | /* Transmit statistic counter */ | |
768 | if ( tdes0 != 0x7fffffff ) { | |
769 | /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */ | |
dfefe02b SH |
770 | dev->stats.collisions += (tdes0 >> 3) & 0xf; |
771 | dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff; | |
4689ced9 | 772 | if (tdes0 & TDES0_ERR_MASK) { |
dfefe02b | 773 | dev->stats.tx_errors++; |
4689ced9 PC |
774 | if (tdes0 & 0x0002) { /* UnderRun */ |
775 | db->tx_fifo_underrun++; | |
776 | if ( !(db->cr6_data & CR6_SFT) ) { | |
777 | db->cr6_data = db->cr6_data | CR6_SFT; | |
778 | update_cr6(db->cr6_data, db->ioaddr); | |
779 | } | |
780 | } | |
781 | if (tdes0 & 0x0100) | |
782 | db->tx_excessive_collision++; | |
783 | if (tdes0 & 0x0200) | |
784 | db->tx_late_collision++; | |
785 | if (tdes0 & 0x0400) | |
786 | db->tx_no_carrier++; | |
787 | if (tdes0 & 0x0800) | |
788 | db->tx_loss_carrier++; | |
789 | if (tdes0 & 0x4000) | |
790 | db->tx_jabber_timeout++; | |
791 | } | |
792 | } | |
793 | ||
794 | txptr = txptr->next_tx_desc; | |
795 | }/* End of while */ | |
796 | ||
797 | /* Update TX remove pointer to next */ | |
798 | db->tx_remove_ptr = txptr; | |
799 | ||
800 | /* Resource available check */ | |
801 | if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT ) | |
802 | netif_wake_queue(dev); /* Active upper layer, send again */ | |
803 | } | |
804 | ||
805 | ||
806 | /* | |
807 | * Receive the come packet and pass to upper layer | |
808 | */ | |
809 | ||
945a7876 | 810 | static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db) |
4689ced9 PC |
811 | { |
812 | struct rx_desc *rxptr; | |
813 | struct sk_buff *skb; | |
814 | int rxlen; | |
815 | u32 rdes0; | |
f3b197ac | 816 | |
4689ced9 PC |
817 | rxptr = db->rx_ready_ptr; |
818 | ||
819 | while(db->rx_avail_cnt) { | |
820 | rdes0 = le32_to_cpu(rxptr->rdes0); | |
821 | if (rdes0 & 0x80000000) /* packet owner check */ | |
822 | { | |
823 | break; | |
824 | } | |
825 | ||
826 | db->rx_avail_cnt--; | |
827 | db->interval_rx_cnt++; | |
828 | ||
829 | pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | |
830 | if ( (rdes0 & 0x300) != 0x300) { | |
831 | /* A packet without First/Last flag */ | |
832 | /* reuse this SKB */ | |
833 | ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); | |
834 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); | |
835 | } else { | |
836 | /* A packet with First/Last flag */ | |
837 | rxlen = ( (rdes0 >> 16) & 0x3fff) - 4; | |
838 | ||
839 | /* error summary bit check */ | |
840 | if (rdes0 & 0x8000) { | |
841 | /* This is a error packet */ | |
842 | //printk(DRV_NAME ": rdes0: %lx\n", rdes0); | |
dfefe02b | 843 | dev->stats.rx_errors++; |
4689ced9 | 844 | if (rdes0 & 1) |
dfefe02b | 845 | dev->stats.rx_fifo_errors++; |
4689ced9 | 846 | if (rdes0 & 2) |
dfefe02b | 847 | dev->stats.rx_crc_errors++; |
4689ced9 | 848 | if (rdes0 & 0x80) |
dfefe02b | 849 | dev->stats.rx_length_errors++; |
4689ced9 PC |
850 | } |
851 | ||
852 | if ( !(rdes0 & 0x8000) || | |
853 | ((db->cr6_data & CR6_PM) && (rxlen>6)) ) { | |
854 | skb = rxptr->rx_skb_ptr; | |
f3b197ac | 855 | |
4689ced9 PC |
856 | /* Good packet, send to upper layer */ |
857 | /* Shorst packet used new SKB */ | |
858 | if ( (rxlen < RX_COPY_SIZE) && | |
859 | ( (skb = dev_alloc_skb(rxlen + 2) ) | |
860 | != NULL) ) { | |
861 | /* size less than COPY_SIZE, allocate a rxlen SKB */ | |
4689ced9 | 862 | skb_reserve(skb, 2); /* 16byte align */ |
27a884dc ACM |
863 | memcpy(skb_put(skb, rxlen), |
864 | skb_tail_pointer(rxptr->rx_skb_ptr), | |
865 | rxlen); | |
4689ced9 | 866 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); |
4c13eb66 | 867 | } else |
4689ced9 | 868 | skb_put(skb, rxlen); |
4c13eb66 | 869 | |
4689ced9 PC |
870 | skb->protocol = eth_type_trans(skb, dev); |
871 | netif_rx(skb); | |
dfefe02b SH |
872 | dev->stats.rx_packets++; |
873 | dev->stats.rx_bytes += rxlen; | |
f3b197ac | 874 | |
4689ced9 PC |
875 | } else { |
876 | /* Reuse SKB buffer when the packet is error */ | |
877 | ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); | |
878 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); | |
879 | } | |
880 | } | |
881 | ||
882 | rxptr = rxptr->next_rx_desc; | |
883 | } | |
884 | ||
885 | db->rx_ready_ptr = rxptr; | |
886 | } | |
887 | ||
888 | ||
4689ced9 PC |
889 | /* |
890 | * Set ULI526X multicast address | |
891 | */ | |
892 | ||
945a7876 | 893 | static void uli526x_set_filter_mode(struct net_device * dev) |
4689ced9 | 894 | { |
8f15ea42 | 895 | struct uli526x_board_info *db = netdev_priv(dev); |
4689ced9 PC |
896 | unsigned long flags; |
897 | ||
898 | ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0); | |
899 | spin_lock_irqsave(&db->lock, flags); | |
900 | ||
901 | if (dev->flags & IFF_PROMISC) { | |
902 | ULI526X_DBUG(0, "Enable PROM Mode", 0); | |
903 | db->cr6_data |= CR6_PM | CR6_PBF; | |
904 | update_cr6(db->cr6_data, db->ioaddr); | |
905 | spin_unlock_irqrestore(&db->lock, flags); | |
906 | return; | |
907 | } | |
908 | ||
909 | if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) { | |
910 | ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count); | |
911 | db->cr6_data &= ~(CR6_PM | CR6_PBF); | |
912 | db->cr6_data |= CR6_PAM; | |
913 | spin_unlock_irqrestore(&db->lock, flags); | |
914 | return; | |
915 | } | |
916 | ||
917 | ULI526X_DBUG(0, "Set multicast address", dev->mc_count); | |
918 | send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */ | |
919 | spin_unlock_irqrestore(&db->lock, flags); | |
920 | } | |
921 | ||
922 | static void | |
923 | ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd) | |
924 | { | |
945a7876 PC |
925 | ecmd->supported = (SUPPORTED_10baseT_Half | |
926 | SUPPORTED_10baseT_Full | | |
927 | SUPPORTED_100baseT_Half | | |
928 | SUPPORTED_100baseT_Full | | |
929 | SUPPORTED_Autoneg | | |
930 | SUPPORTED_MII); | |
f3b197ac | 931 | |
945a7876 PC |
932 | ecmd->advertising = (ADVERTISED_10baseT_Half | |
933 | ADVERTISED_10baseT_Full | | |
934 | ADVERTISED_100baseT_Half | | |
935 | ADVERTISED_100baseT_Full | | |
936 | ADVERTISED_Autoneg | | |
937 | ADVERTISED_MII); | |
4689ced9 PC |
938 | |
939 | ||
945a7876 PC |
940 | ecmd->port = PORT_MII; |
941 | ecmd->phy_address = db->phy_addr; | |
4689ced9 | 942 | |
945a7876 | 943 | ecmd->transceiver = XCVR_EXTERNAL; |
f3b197ac | 944 | |
4689ced9 PC |
945 | ecmd->speed = 10; |
946 | ecmd->duplex = DUPLEX_HALF; | |
f3b197ac | 947 | |
4689ced9 PC |
948 | if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) |
949 | { | |
f3b197ac | 950 | ecmd->speed = 100; |
4689ced9 PC |
951 | } |
952 | if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) | |
953 | { | |
954 | ecmd->duplex = DUPLEX_FULL; | |
955 | } | |
956 | if(db->link_failed) | |
957 | { | |
958 | ecmd->speed = -1; | |
f3b197ac | 959 | ecmd->duplex = -1; |
4689ced9 | 960 | } |
f3b197ac | 961 | |
4689ced9 | 962 | if (db->media_mode & ULI526X_AUTO) |
f3b197ac | 963 | { |
4689ced9 PC |
964 | ecmd->autoneg = AUTONEG_ENABLE; |
965 | } | |
4689ced9 PC |
966 | } |
967 | ||
968 | static void netdev_get_drvinfo(struct net_device *dev, | |
969 | struct ethtool_drvinfo *info) | |
970 | { | |
971 | struct uli526x_board_info *np = netdev_priv(dev); | |
972 | ||
973 | strcpy(info->driver, DRV_NAME); | |
974 | strcpy(info->version, DRV_VERSION); | |
975 | if (np->pdev) | |
976 | strcpy(info->bus_info, pci_name(np->pdev)); | |
977 | else | |
978 | sprintf(info->bus_info, "EISA 0x%lx %d", | |
979 | dev->base_addr, dev->irq); | |
980 | } | |
981 | ||
982 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { | |
983 | struct uli526x_board_info *np = netdev_priv(dev); | |
f3b197ac | 984 | |
4689ced9 | 985 | ULi_ethtool_gset(np, cmd); |
f3b197ac | 986 | |
4689ced9 PC |
987 | return 0; |
988 | } | |
989 | ||
990 | static u32 netdev_get_link(struct net_device *dev) { | |
991 | struct uli526x_board_info *np = netdev_priv(dev); | |
f3b197ac | 992 | |
4689ced9 PC |
993 | if(np->link_failed) |
994 | return 0; | |
995 | else | |
996 | return 1; | |
997 | } | |
998 | ||
999 | static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1000 | { | |
1001 | wol->supported = WAKE_PHY | WAKE_MAGIC; | |
1002 | wol->wolopts = 0; | |
1003 | } | |
1004 | ||
7282d491 | 1005 | static const struct ethtool_ops netdev_ethtool_ops = { |
4689ced9 PC |
1006 | .get_drvinfo = netdev_get_drvinfo, |
1007 | .get_settings = netdev_get_settings, | |
1008 | .get_link = netdev_get_link, | |
1009 | .get_wol = uli526x_get_wol, | |
1010 | }; | |
1011 | ||
1012 | /* | |
1013 | * A periodic timer routine | |
1014 | * Dynamic media sense, allocate Rx buffer... | |
1015 | */ | |
1016 | ||
1017 | static void uli526x_timer(unsigned long data) | |
1018 | { | |
1019 | u32 tmp_cr8; | |
1020 | unsigned char tmp_cr12=0; | |
945a7876 | 1021 | struct net_device *dev = (struct net_device *) data; |
4689ced9 PC |
1022 | struct uli526x_board_info *db = netdev_priv(dev); |
1023 | unsigned long flags; | |
1024 | u8 TmpSpeed=10; | |
f3b197ac | 1025 | |
4689ced9 PC |
1026 | //ULI526X_DBUG(0, "uli526x_timer()", 0); |
1027 | spin_lock_irqsave(&db->lock, flags); | |
1028 | ||
f3b197ac | 1029 | |
4689ced9 PC |
1030 | /* Dynamic reset ULI526X : system error or transmit time-out */ |
1031 | tmp_cr8 = inl(db->ioaddr + DCR8); | |
1032 | if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { | |
1033 | db->reset_cr8++; | |
1034 | db->wait_reset = 1; | |
1035 | } | |
1036 | db->interval_rx_cnt = 0; | |
1037 | ||
1038 | /* TX polling kick monitor */ | |
1039 | if ( db->tx_packet_cnt && | |
1040 | time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) { | |
f3b197ac | 1041 | outl(0x1, dev->base_addr + DCR1); // Tx polling again |
4689ced9 | 1042 | |
f3b197ac | 1043 | // TX Timeout |
4689ced9 PC |
1044 | if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) { |
1045 | db->reset_TXtimeout++; | |
1046 | db->wait_reset = 1; | |
1047 | printk( "%s: Tx timeout - resetting\n", | |
1048 | dev->name); | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | if (db->wait_reset) { | |
1053 | ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt); | |
1054 | db->reset_count++; | |
1055 | uli526x_dynamic_reset(dev); | |
1056 | db->timer.expires = ULI526X_TIMER_WUT; | |
1057 | add_timer(&db->timer); | |
1058 | spin_unlock_irqrestore(&db->lock, flags); | |
1059 | return; | |
1060 | } | |
1061 | ||
1062 | /* Link status check, Dynamic media type change */ | |
1063 | if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0) | |
1064 | tmp_cr12 = 3; | |
1065 | ||
1066 | if ( !(tmp_cr12 & 0x3) && !db->link_failed ) { | |
1067 | /* Link Failed */ | |
1068 | ULI526X_DBUG(0, "Link Failed", tmp_cr12); | |
1069 | netif_carrier_off(dev); | |
e02fb7aa | 1070 | pr_info("%s NIC Link is Down\n",dev->name); |
4689ced9 PC |
1071 | db->link_failed = 1; |
1072 | ||
1073 | /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ | |
1074 | /* AUTO don't need */ | |
1075 | if ( !(db->media_mode & 0x8) ) | |
1076 | phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); | |
1077 | ||
1078 | /* AUTO mode, if INT phyxcer link failed, select EXT device */ | |
1079 | if (db->media_mode & ULI526X_AUTO) { | |
1080 | db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ | |
1081 | update_cr6(db->cr6_data, db->ioaddr); | |
1082 | } | |
1083 | } else | |
1084 | if ((tmp_cr12 & 0x3) && db->link_failed) { | |
1085 | ULI526X_DBUG(0, "Link link OK", tmp_cr12); | |
1086 | db->link_failed = 0; | |
1087 | ||
1088 | /* Auto Sense Speed */ | |
1089 | if ( (db->media_mode & ULI526X_AUTO) && | |
1090 | uli526x_sense_speed(db) ) | |
1091 | db->link_failed = 1; | |
1092 | uli526x_process_mode(db); | |
f3b197ac | 1093 | |
4689ced9 PC |
1094 | if(db->link_failed==0) |
1095 | { | |
1096 | if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) | |
1097 | { | |
1098 | TmpSpeed = 100; | |
1099 | } | |
1100 | if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) | |
1101 | { | |
e02fb7aa | 1102 | pr_info("%s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed); |
4689ced9 PC |
1103 | } |
1104 | else | |
1105 | { | |
e02fb7aa | 1106 | pr_info("%s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed); |
4689ced9 PC |
1107 | } |
1108 | netif_carrier_on(dev); | |
1109 | } | |
1110 | /* SHOW_MEDIA_TYPE(db->op_mode); */ | |
1111 | } | |
1112 | else if(!(tmp_cr12 & 0x3) && db->link_failed) | |
1113 | { | |
1114 | if(db->init==1) | |
1115 | { | |
e02fb7aa | 1116 | pr_info("%s NIC Link is Down\n",dev->name); |
4689ced9 PC |
1117 | netif_carrier_off(dev); |
1118 | } | |
1119 | } | |
1120 | db->init=0; | |
1121 | ||
1122 | /* Timer active again */ | |
1123 | db->timer.expires = ULI526X_TIMER_WUT; | |
1124 | add_timer(&db->timer); | |
1125 | spin_unlock_irqrestore(&db->lock, flags); | |
1126 | } | |
1127 | ||
1128 | ||
1129 | /* | |
4689ced9 PC |
1130 | * Stop ULI526X board |
1131 | * Free Tx/Rx allocated memory | |
b6aec32a | 1132 | * Init system variable |
4689ced9 PC |
1133 | */ |
1134 | ||
b6aec32a | 1135 | static void uli526x_reset_prepare(struct net_device *dev) |
4689ced9 PC |
1136 | { |
1137 | struct uli526x_board_info *db = netdev_priv(dev); | |
1138 | ||
4689ced9 PC |
1139 | /* Sopt MAC controller */ |
1140 | db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ | |
1141 | update_cr6(db->cr6_data, dev->base_addr); | |
1142 | outl(0, dev->base_addr + DCR7); /* Disable Interrupt */ | |
1143 | outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5); | |
1144 | ||
1145 | /* Disable upper layer interface */ | |
1146 | netif_stop_queue(dev); | |
1147 | ||
1148 | /* Free Rx Allocate buffer */ | |
1149 | uli526x_free_rxbuffer(db); | |
1150 | ||
1151 | /* system variable init */ | |
1152 | db->tx_packet_cnt = 0; | |
1153 | db->rx_avail_cnt = 0; | |
1154 | db->link_failed = 1; | |
1155 | db->init=1; | |
1156 | db->wait_reset = 0; | |
b6aec32a RW |
1157 | } |
1158 | ||
1159 | ||
1160 | /* | |
1161 | * Dynamic reset the ULI526X board | |
1162 | * Stop ULI526X board | |
1163 | * Free Tx/Rx allocated memory | |
1164 | * Reset ULI526X board | |
1165 | * Re-initialize ULI526X board | |
1166 | */ | |
1167 | ||
1168 | static void uli526x_dynamic_reset(struct net_device *dev) | |
1169 | { | |
1170 | ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0); | |
1171 | ||
1172 | uli526x_reset_prepare(dev); | |
4689ced9 | 1173 | |
945a7876 | 1174 | /* Re-initialize ULI526X board */ |
4689ced9 PC |
1175 | uli526x_init(dev); |
1176 | ||
1177 | /* Restart upper layer interface */ | |
1178 | netif_wake_queue(dev); | |
1179 | } | |
1180 | ||
1181 | ||
b6aec32a RW |
1182 | #ifdef CONFIG_PM |
1183 | ||
1184 | /* | |
1185 | * Suspend the interface. | |
1186 | */ | |
1187 | ||
1188 | static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state) | |
1189 | { | |
1190 | struct net_device *dev = pci_get_drvdata(pdev); | |
1191 | pci_power_t power_state; | |
1192 | int err; | |
1193 | ||
1194 | ULI526X_DBUG(0, "uli526x_suspend", 0); | |
1195 | ||
1196 | if (!netdev_priv(dev)) | |
1197 | return 0; | |
1198 | ||
1199 | pci_save_state(pdev); | |
1200 | ||
1201 | if (!netif_running(dev)) | |
1202 | return 0; | |
1203 | ||
1204 | netif_device_detach(dev); | |
1205 | uli526x_reset_prepare(dev); | |
1206 | ||
1207 | power_state = pci_choose_state(pdev, state); | |
1208 | pci_enable_wake(pdev, power_state, 0); | |
1209 | err = pci_set_power_state(pdev, power_state); | |
1210 | if (err) { | |
1211 | netif_device_attach(dev); | |
1212 | /* Re-initialize ULI526X board */ | |
1213 | uli526x_init(dev); | |
1214 | /* Restart upper layer interface */ | |
1215 | netif_wake_queue(dev); | |
1216 | } | |
1217 | ||
1218 | return err; | |
1219 | } | |
1220 | ||
1221 | /* | |
1222 | * Resume the interface. | |
1223 | */ | |
1224 | ||
1225 | static int uli526x_resume(struct pci_dev *pdev) | |
1226 | { | |
1227 | struct net_device *dev = pci_get_drvdata(pdev); | |
1228 | int err; | |
1229 | ||
1230 | ULI526X_DBUG(0, "uli526x_resume", 0); | |
1231 | ||
1232 | if (!netdev_priv(dev)) | |
1233 | return 0; | |
1234 | ||
1235 | pci_restore_state(pdev); | |
1236 | ||
1237 | if (!netif_running(dev)) | |
1238 | return 0; | |
1239 | ||
1240 | err = pci_set_power_state(pdev, PCI_D0); | |
1241 | if (err) { | |
e02fb7aa | 1242 | dev_warn(&dev->dev, "Could not put device into D0\n"); |
b6aec32a RW |
1243 | return err; |
1244 | } | |
1245 | ||
1246 | netif_device_attach(dev); | |
1247 | /* Re-initialize ULI526X board */ | |
1248 | uli526x_init(dev); | |
1249 | /* Restart upper layer interface */ | |
1250 | netif_wake_queue(dev); | |
1251 | ||
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | #else /* !CONFIG_PM */ | |
1256 | ||
1257 | #define uli526x_suspend NULL | |
1258 | #define uli526x_resume NULL | |
1259 | ||
1260 | #endif /* !CONFIG_PM */ | |
1261 | ||
1262 | ||
4689ced9 PC |
1263 | /* |
1264 | * free all allocated rx buffer | |
1265 | */ | |
1266 | ||
1267 | static void uli526x_free_rxbuffer(struct uli526x_board_info * db) | |
1268 | { | |
1269 | ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0); | |
1270 | ||
1271 | /* free allocated rx buffer */ | |
1272 | while (db->rx_avail_cnt) { | |
1273 | dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr); | |
1274 | db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc; | |
1275 | db->rx_avail_cnt--; | |
1276 | } | |
1277 | } | |
1278 | ||
1279 | ||
1280 | /* | |
1281 | * Reuse the SK buffer | |
1282 | */ | |
1283 | ||
1284 | static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb) | |
1285 | { | |
1286 | struct rx_desc *rxptr = db->rx_insert_ptr; | |
1287 | ||
1288 | if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { | |
1289 | rxptr->rx_skb_ptr = skb; | |
27a884dc ACM |
1290 | rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev, |
1291 | skb_tail_pointer(skb), | |
1292 | RX_ALLOC_SIZE, | |
1293 | PCI_DMA_FROMDEVICE)); | |
4689ced9 PC |
1294 | wmb(); |
1295 | rxptr->rdes0 = cpu_to_le32(0x80000000); | |
1296 | db->rx_avail_cnt++; | |
1297 | db->rx_insert_ptr = rxptr->next_rx_desc; | |
1298 | } else | |
1299 | ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt); | |
1300 | } | |
1301 | ||
1302 | ||
1303 | /* | |
1304 | * Initialize transmit/Receive descriptor | |
1305 | * Using Chain structure, and allocate Tx/Rx buffer | |
1306 | */ | |
1307 | ||
1308 | static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr) | |
1309 | { | |
1310 | struct tx_desc *tmp_tx; | |
1311 | struct rx_desc *tmp_rx; | |
1312 | unsigned char *tmp_buf; | |
1313 | dma_addr_t tmp_tx_dma, tmp_rx_dma; | |
1314 | dma_addr_t tmp_buf_dma; | |
1315 | int i; | |
1316 | ||
1317 | ULI526X_DBUG(0, "uli526x_descriptor_init()", 0); | |
1318 | ||
1319 | /* tx descriptor start pointer */ | |
1320 | db->tx_insert_ptr = db->first_tx_desc; | |
1321 | db->tx_remove_ptr = db->first_tx_desc; | |
1322 | outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ | |
1323 | ||
1324 | /* rx descriptor start pointer */ | |
1325 | db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT; | |
1326 | db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT; | |
1327 | db->rx_insert_ptr = db->first_rx_desc; | |
1328 | db->rx_ready_ptr = db->first_rx_desc; | |
1329 | outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ | |
1330 | ||
1331 | /* Init Transmit chain */ | |
1332 | tmp_buf = db->buf_pool_start; | |
1333 | tmp_buf_dma = db->buf_pool_dma_start; | |
1334 | tmp_tx_dma = db->first_tx_desc_dma; | |
1335 | for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) { | |
1336 | tmp_tx->tx_buf_ptr = tmp_buf; | |
1337 | tmp_tx->tdes0 = cpu_to_le32(0); | |
1338 | tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ | |
1339 | tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma); | |
1340 | tmp_tx_dma += sizeof(struct tx_desc); | |
1341 | tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma); | |
1342 | tmp_tx->next_tx_desc = tmp_tx + 1; | |
1343 | tmp_buf = tmp_buf + TX_BUF_ALLOC; | |
1344 | tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC; | |
1345 | } | |
1346 | (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); | |
1347 | tmp_tx->next_tx_desc = db->first_tx_desc; | |
1348 | ||
1349 | /* Init Receive descriptor chain */ | |
1350 | tmp_rx_dma=db->first_rx_desc_dma; | |
1351 | for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) { | |
1352 | tmp_rx->rdes0 = cpu_to_le32(0); | |
1353 | tmp_rx->rdes1 = cpu_to_le32(0x01000600); | |
1354 | tmp_rx_dma += sizeof(struct rx_desc); | |
1355 | tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma); | |
1356 | tmp_rx->next_rx_desc = tmp_rx + 1; | |
1357 | } | |
1358 | (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); | |
1359 | tmp_rx->next_rx_desc = db->first_rx_desc; | |
1360 | ||
1361 | /* pre-allocate Rx buffer */ | |
1362 | allocate_rx_buffer(db); | |
1363 | } | |
1364 | ||
1365 | ||
1366 | /* | |
1367 | * Update CR6 value | |
945a7876 | 1368 | * Firstly stop ULI526X, then written value and start |
4689ced9 PC |
1369 | */ |
1370 | ||
1371 | static void update_cr6(u32 cr6_data, unsigned long ioaddr) | |
1372 | { | |
1373 | ||
1374 | outl(cr6_data, ioaddr + DCR6); | |
1375 | udelay(5); | |
1376 | } | |
1377 | ||
1378 | ||
1379 | /* | |
1380 | * Send a setup frame for M5261/M5263 | |
945a7876 | 1381 | * This setup frame initialize ULI526X address filter mode |
4689ced9 PC |
1382 | */ |
1383 | ||
e284e5c6 AV |
1384 | #ifdef __BIG_ENDIAN |
1385 | #define FLT_SHIFT 16 | |
1386 | #else | |
1387 | #define FLT_SHIFT 0 | |
1388 | #endif | |
1389 | ||
945a7876 | 1390 | static void send_filter_frame(struct net_device *dev, int mc_cnt) |
4689ced9 PC |
1391 | { |
1392 | struct uli526x_board_info *db = netdev_priv(dev); | |
1393 | struct dev_mc_list *mcptr; | |
1394 | struct tx_desc *txptr; | |
1395 | u16 * addrptr; | |
1396 | u32 * suptr; | |
1397 | int i; | |
1398 | ||
1399 | ULI526X_DBUG(0, "send_filter_frame()", 0); | |
1400 | ||
1401 | txptr = db->tx_insert_ptr; | |
1402 | suptr = (u32 *) txptr->tx_buf_ptr; | |
1403 | ||
1404 | /* Node address */ | |
1405 | addrptr = (u16 *) dev->dev_addr; | |
e284e5c6 AV |
1406 | *suptr++ = addrptr[0] << FLT_SHIFT; |
1407 | *suptr++ = addrptr[1] << FLT_SHIFT; | |
1408 | *suptr++ = addrptr[2] << FLT_SHIFT; | |
4689ced9 PC |
1409 | |
1410 | /* broadcast address */ | |
e284e5c6 AV |
1411 | *suptr++ = 0xffff << FLT_SHIFT; |
1412 | *suptr++ = 0xffff << FLT_SHIFT; | |
1413 | *suptr++ = 0xffff << FLT_SHIFT; | |
4689ced9 PC |
1414 | |
1415 | /* fit the multicast address */ | |
1416 | for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
1417 | addrptr = (u16 *) mcptr->dmi_addr; | |
e284e5c6 AV |
1418 | *suptr++ = addrptr[0] << FLT_SHIFT; |
1419 | *suptr++ = addrptr[1] << FLT_SHIFT; | |
1420 | *suptr++ = addrptr[2] << FLT_SHIFT; | |
4689ced9 PC |
1421 | } |
1422 | ||
1423 | for (; i<14; i++) { | |
e284e5c6 AV |
1424 | *suptr++ = 0xffff << FLT_SHIFT; |
1425 | *suptr++ = 0xffff << FLT_SHIFT; | |
1426 | *suptr++ = 0xffff << FLT_SHIFT; | |
4689ced9 PC |
1427 | } |
1428 | ||
1429 | /* prepare the setup frame */ | |
1430 | db->tx_insert_ptr = txptr->next_tx_desc; | |
1431 | txptr->tdes1 = cpu_to_le32(0x890000c0); | |
1432 | ||
1433 | /* Resource Check and Send the setup packet */ | |
1434 | if (db->tx_packet_cnt < TX_DESC_CNT) { | |
1435 | /* Resource Empty */ | |
1436 | db->tx_packet_cnt++; | |
1437 | txptr->tdes0 = cpu_to_le32(0x80000000); | |
1438 | update_cr6(db->cr6_data | 0x2000, dev->base_addr); | |
1439 | outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ | |
1440 | update_cr6(db->cr6_data, dev->base_addr); | |
1441 | dev->trans_start = jiffies; | |
1442 | } else | |
e02fb7aa | 1443 | pr_err("No Tx resource - Send_filter_frame!\n"); |
4689ced9 PC |
1444 | } |
1445 | ||
1446 | ||
1447 | /* | |
1448 | * Allocate rx buffer, | |
1449 | * As possible as allocate maxiumn Rx buffer | |
1450 | */ | |
1451 | ||
1452 | static void allocate_rx_buffer(struct uli526x_board_info *db) | |
1453 | { | |
1454 | struct rx_desc *rxptr; | |
1455 | struct sk_buff *skb; | |
1456 | ||
1457 | rxptr = db->rx_insert_ptr; | |
1458 | ||
1459 | while(db->rx_avail_cnt < RX_DESC_CNT) { | |
1460 | if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL ) | |
1461 | break; | |
1462 | rxptr->rx_skb_ptr = skb; /* FIXME (?) */ | |
27a884dc ACM |
1463 | rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev, |
1464 | skb_tail_pointer(skb), | |
1465 | RX_ALLOC_SIZE, | |
1466 | PCI_DMA_FROMDEVICE)); | |
4689ced9 PC |
1467 | wmb(); |
1468 | rxptr->rdes0 = cpu_to_le32(0x80000000); | |
1469 | rxptr = rxptr->next_rx_desc; | |
1470 | db->rx_avail_cnt++; | |
1471 | } | |
1472 | ||
1473 | db->rx_insert_ptr = rxptr; | |
1474 | } | |
1475 | ||
1476 | ||
1477 | /* | |
1478 | * Read one word data from the serial ROM | |
1479 | */ | |
1480 | ||
1481 | static u16 read_srom_word(long ioaddr, int offset) | |
1482 | { | |
1483 | int i; | |
1484 | u16 srom_data = 0; | |
1485 | long cr9_ioaddr = ioaddr + DCR9; | |
1486 | ||
1487 | outl(CR9_SROM_READ, cr9_ioaddr); | |
1488 | outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); | |
1489 | ||
1490 | /* Send the Read Command 110b */ | |
1491 | SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); | |
1492 | SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); | |
1493 | SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr); | |
1494 | ||
1495 | /* Send the offset */ | |
1496 | for (i = 5; i >= 0; i--) { | |
1497 | srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; | |
1498 | SROM_CLK_WRITE(srom_data, cr9_ioaddr); | |
1499 | } | |
1500 | ||
1501 | outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); | |
1502 | ||
1503 | for (i = 16; i > 0; i--) { | |
1504 | outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); | |
1505 | udelay(5); | |
1506 | srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0); | |
1507 | outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); | |
1508 | udelay(5); | |
1509 | } | |
1510 | ||
1511 | outl(CR9_SROM_READ, cr9_ioaddr); | |
1512 | return srom_data; | |
1513 | } | |
1514 | ||
1515 | ||
1516 | /* | |
1517 | * Auto sense the media mode | |
1518 | */ | |
1519 | ||
1520 | static u8 uli526x_sense_speed(struct uli526x_board_info * db) | |
1521 | { | |
1522 | u8 ErrFlag = 0; | |
1523 | u16 phy_mode; | |
1524 | ||
1525 | phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); | |
1526 | phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); | |
1527 | ||
1528 | if ( (phy_mode & 0x24) == 0x24 ) { | |
f3b197ac | 1529 | |
4689ced9 PC |
1530 | phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7); |
1531 | if(phy_mode&0x8000) | |
1532 | phy_mode = 0x8000; | |
1533 | else if(phy_mode&0x4000) | |
1534 | phy_mode = 0x4000; | |
1535 | else if(phy_mode&0x2000) | |
1536 | phy_mode = 0x2000; | |
1537 | else | |
1538 | phy_mode = 0x1000; | |
f3b197ac | 1539 | |
4689ced9 PC |
1540 | /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */ |
1541 | switch (phy_mode) { | |
1542 | case 0x1000: db->op_mode = ULI526X_10MHF; break; | |
1543 | case 0x2000: db->op_mode = ULI526X_10MFD; break; | |
1544 | case 0x4000: db->op_mode = ULI526X_100MHF; break; | |
1545 | case 0x8000: db->op_mode = ULI526X_100MFD; break; | |
1546 | default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break; | |
1547 | } | |
1548 | } else { | |
1549 | db->op_mode = ULI526X_10MHF; | |
1550 | ULI526X_DBUG(0, "Link Failed :", phy_mode); | |
1551 | ErrFlag = 1; | |
1552 | } | |
1553 | ||
1554 | return ErrFlag; | |
1555 | } | |
1556 | ||
1557 | ||
1558 | /* | |
1559 | * Set 10/100 phyxcer capability | |
1560 | * AUTO mode : phyxcer register4 is NIC capability | |
1561 | * Force mode: phyxcer register4 is the force media | |
1562 | */ | |
1563 | ||
1564 | static void uli526x_set_phyxcer(struct uli526x_board_info *db) | |
1565 | { | |
1566 | u16 phy_reg; | |
f3b197ac | 1567 | |
4689ced9 PC |
1568 | /* Phyxcer capability setting */ |
1569 | phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; | |
1570 | ||
1571 | if (db->media_mode & ULI526X_AUTO) { | |
1572 | /* AUTO Mode */ | |
1573 | phy_reg |= db->PHY_reg4; | |
1574 | } else { | |
1575 | /* Force Mode */ | |
1576 | switch(db->media_mode) { | |
1577 | case ULI526X_10MHF: phy_reg |= 0x20; break; | |
1578 | case ULI526X_10MFD: phy_reg |= 0x40; break; | |
1579 | case ULI526X_100MHF: phy_reg |= 0x80; break; | |
1580 | case ULI526X_100MFD: phy_reg |= 0x100; break; | |
1581 | } | |
f3b197ac | 1582 | |
4689ced9 PC |
1583 | } |
1584 | ||
1585 | /* Write new capability to Phyxcer Reg4 */ | |
1586 | if ( !(phy_reg & 0x01e0)) { | |
1587 | phy_reg|=db->PHY_reg4; | |
1588 | db->media_mode|=ULI526X_AUTO; | |
1589 | } | |
1590 | phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); | |
1591 | ||
1592 | /* Restart Auto-Negotiation */ | |
1593 | phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); | |
1594 | udelay(50); | |
1595 | } | |
1596 | ||
1597 | ||
1598 | /* | |
1599 | * Process op-mode | |
1600 | AUTO mode : PHY controller in Auto-negotiation Mode | |
1601 | * Force mode: PHY controller in force mode with HUB | |
1602 | * N-way force capability with SWITCH | |
1603 | */ | |
1604 | ||
1605 | static void uli526x_process_mode(struct uli526x_board_info *db) | |
1606 | { | |
1607 | u16 phy_reg; | |
1608 | ||
1609 | /* Full Duplex Mode Check */ | |
1610 | if (db->op_mode & 0x4) | |
1611 | db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */ | |
1612 | else | |
1613 | db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */ | |
1614 | ||
1615 | update_cr6(db->cr6_data, db->ioaddr); | |
1616 | ||
1617 | /* 10/100M phyxcer force mode need */ | |
1618 | if ( !(db->media_mode & 0x8)) { | |
1619 | /* Forece Mode */ | |
1620 | phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id); | |
1621 | if ( !(phy_reg & 0x1) ) { | |
1622 | /* parter without N-Way capability */ | |
1623 | phy_reg = 0x0; | |
1624 | switch(db->op_mode) { | |
1625 | case ULI526X_10MHF: phy_reg = 0x0; break; | |
1626 | case ULI526X_10MFD: phy_reg = 0x100; break; | |
1627 | case ULI526X_100MHF: phy_reg = 0x2000; break; | |
1628 | case ULI526X_100MFD: phy_reg = 0x2100; break; | |
1629 | } | |
1630 | phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); | |
4689ced9 PC |
1631 | } |
1632 | } | |
1633 | } | |
1634 | ||
1635 | ||
1636 | /* | |
1637 | * Write a word to Phy register | |
1638 | */ | |
1639 | ||
1640 | static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id) | |
1641 | { | |
1642 | u16 i; | |
1643 | unsigned long ioaddr; | |
1644 | ||
1645 | if(chip_id == PCI_ULI5263_ID) | |
1646 | { | |
1647 | phy_writeby_cr10(iobase, phy_addr, offset, phy_data); | |
1648 | return; | |
1649 | } | |
1650 | /* M5261/M5263 Chip */ | |
1651 | ioaddr = iobase + DCR9; | |
1652 | ||
1653 | /* Send 33 synchronization clock to Phy controller */ | |
1654 | for (i = 0; i < 35; i++) | |
1655 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1656 | ||
1657 | /* Send start command(01) to Phy */ | |
1658 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1659 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1660 | ||
1661 | /* Send write command(01) to Phy */ | |
1662 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1663 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1664 | ||
1665 | /* Send Phy address */ | |
1666 | for (i = 0x10; i > 0; i = i >> 1) | |
1667 | phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
1668 | ||
1669 | /* Send register address */ | |
1670 | for (i = 0x10; i > 0; i = i >> 1) | |
1671 | phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
1672 | ||
1673 | /* written trasnition */ | |
1674 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1675 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1676 | ||
1677 | /* Write a word data to PHY controller */ | |
1678 | for ( i = 0x8000; i > 0; i >>= 1) | |
1679 | phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
f3b197ac | 1680 | |
4689ced9 PC |
1681 | } |
1682 | ||
1683 | ||
1684 | /* | |
1685 | * Read a word data from phy register | |
1686 | */ | |
1687 | ||
1688 | static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id) | |
1689 | { | |
1690 | int i; | |
1691 | u16 phy_data; | |
1692 | unsigned long ioaddr; | |
1693 | ||
1694 | if(chip_id == PCI_ULI5263_ID) | |
1695 | return phy_readby_cr10(iobase, phy_addr, offset); | |
1696 | /* M5261/M5263 Chip */ | |
1697 | ioaddr = iobase + DCR9; | |
f3b197ac | 1698 | |
4689ced9 PC |
1699 | /* Send 33 synchronization clock to Phy controller */ |
1700 | for (i = 0; i < 35; i++) | |
1701 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1702 | ||
1703 | /* Send start command(01) to Phy */ | |
1704 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1705 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1706 | ||
1707 | /* Send read command(10) to Phy */ | |
1708 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1709 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1710 | ||
1711 | /* Send Phy address */ | |
1712 | for (i = 0x10; i > 0; i = i >> 1) | |
1713 | phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
1714 | ||
1715 | /* Send register address */ | |
1716 | for (i = 0x10; i > 0; i = i >> 1) | |
1717 | phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
1718 | ||
1719 | /* Skip transition state */ | |
1720 | phy_read_1bit(ioaddr, chip_id); | |
1721 | ||
1722 | /* read 16bit data */ | |
1723 | for (phy_data = 0, i = 0; i < 16; i++) { | |
1724 | phy_data <<= 1; | |
1725 | phy_data |= phy_read_1bit(ioaddr, chip_id); | |
1726 | } | |
1727 | ||
1728 | return phy_data; | |
1729 | } | |
1730 | ||
1731 | static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset) | |
1732 | { | |
1733 | unsigned long ioaddr,cr10_value; | |
f3b197ac | 1734 | |
4689ced9 PC |
1735 | ioaddr = iobase + DCR10; |
1736 | cr10_value = phy_addr; | |
1737 | cr10_value = (cr10_value<<5) + offset; | |
1738 | cr10_value = (cr10_value<<16) + 0x08000000; | |
1739 | outl(cr10_value,ioaddr); | |
1740 | udelay(1); | |
1741 | while(1) | |
1742 | { | |
1743 | cr10_value = inl(ioaddr); | |
1744 | if(cr10_value&0x10000000) | |
1745 | break; | |
1746 | } | |
1747 | return (cr10_value&0x0ffff); | |
1748 | } | |
1749 | ||
1750 | static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data) | |
1751 | { | |
1752 | unsigned long ioaddr,cr10_value; | |
f3b197ac | 1753 | |
4689ced9 PC |
1754 | ioaddr = iobase + DCR10; |
1755 | cr10_value = phy_addr; | |
1756 | cr10_value = (cr10_value<<5) + offset; | |
1757 | cr10_value = (cr10_value<<16) + 0x04000000 + phy_data; | |
1758 | outl(cr10_value,ioaddr); | |
1759 | udelay(1); | |
1760 | } | |
1761 | /* | |
1762 | * Write one bit data to Phy Controller | |
1763 | */ | |
1764 | ||
1765 | static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id) | |
1766 | { | |
1767 | outl(phy_data , ioaddr); /* MII Clock Low */ | |
1768 | udelay(1); | |
1769 | outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ | |
1770 | udelay(1); | |
1771 | outl(phy_data , ioaddr); /* MII Clock Low */ | |
1772 | udelay(1); | |
1773 | } | |
1774 | ||
1775 | ||
1776 | /* | |
1777 | * Read one bit phy data from PHY controller | |
1778 | */ | |
1779 | ||
1780 | static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id) | |
1781 | { | |
1782 | u16 phy_data; | |
f3b197ac | 1783 | |
4689ced9 PC |
1784 | outl(0x50000 , ioaddr); |
1785 | udelay(1); | |
1786 | phy_data = ( inl(ioaddr) >> 19 ) & 0x1; | |
1787 | outl(0x40000 , ioaddr); | |
1788 | udelay(1); | |
1789 | ||
1790 | return phy_data; | |
1791 | } | |
1792 | ||
1793 | ||
a3aa1884 | 1794 | static DEFINE_PCI_DEVICE_TABLE(uli526x_pci_tbl) = { |
4689ced9 PC |
1795 | { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID }, |
1796 | { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID }, | |
1797 | { 0, } | |
1798 | }; | |
1799 | MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl); | |
1800 | ||
1801 | ||
1802 | static struct pci_driver uli526x_driver = { | |
1803 | .name = "uli526x", | |
1804 | .id_table = uli526x_pci_tbl, | |
1805 | .probe = uli526x_init_one, | |
1806 | .remove = __devexit_p(uli526x_remove_one), | |
b6aec32a RW |
1807 | .suspend = uli526x_suspend, |
1808 | .resume = uli526x_resume, | |
4689ced9 PC |
1809 | }; |
1810 | ||
1811 | MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw"); | |
1812 | MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver"); | |
1813 | MODULE_LICENSE("GPL"); | |
1814 | ||
c213460f ES |
1815 | module_param(debug, int, 0644); |
1816 | module_param(mode, int, 0); | |
1817 | module_param(cr6set, int, 0); | |
4689ced9 PC |
1818 | MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)"); |
1819 | MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA"); | |
1820 | ||
1821 | /* Description: | |
1822 | * when user used insmod to add module, system invoked init_module() | |
945a7876 | 1823 | * to register the services. |
4689ced9 PC |
1824 | */ |
1825 | ||
1826 | static int __init uli526x_init_module(void) | |
1827 | { | |
4689ced9 PC |
1828 | |
1829 | printk(version); | |
1830 | printed_version = 1; | |
1831 | ||
1832 | ULI526X_DBUG(0, "init_module() ", debug); | |
1833 | ||
1834 | if (debug) | |
1835 | uli526x_debug = debug; /* set debug flag */ | |
1836 | if (cr6set) | |
1837 | uli526x_cr6_user_set = cr6set; | |
1838 | ||
e1c3e501 | 1839 | switch (mode) { |
4689ced9 PC |
1840 | case ULI526X_10MHF: |
1841 | case ULI526X_100MHF: | |
1842 | case ULI526X_10MFD: | |
1843 | case ULI526X_100MFD: | |
1844 | uli526x_media_mode = mode; | |
1845 | break; | |
e1c3e501 HK |
1846 | default: |
1847 | uli526x_media_mode = ULI526X_AUTO; | |
4689ced9 PC |
1848 | break; |
1849 | } | |
1850 | ||
e1c3e501 | 1851 | return pci_register_driver(&uli526x_driver); |
4689ced9 PC |
1852 | } |
1853 | ||
1854 | ||
1855 | /* | |
1856 | * Description: | |
1857 | * when user used rmmod to delete module, system invoked clean_module() | |
1858 | * to un-register all registered services. | |
1859 | */ | |
1860 | ||
1861 | static void __exit uli526x_cleanup_module(void) | |
1862 | { | |
1863 | ULI526X_DBUG(0, "uli526x_clean_module() ", debug); | |
1864 | pci_unregister_driver(&uli526x_driver); | |
1865 | } | |
1866 | ||
1867 | module_init(uli526x_init_module); | |
1868 | module_exit(uli526x_cleanup_module); |