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Commit | Line | Data |
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4689ced9 PC |
1 | /* |
2 | This program is free software; you can redistribute it and/or | |
3 | modify it under the terms of the GNU General Public License | |
4 | as published by the Free Software Foundation; either version 2 | |
5 | of the License, or (at your option) any later version. | |
6 | ||
7 | This program is distributed in the hope that it will be useful, | |
8 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | GNU General Public License for more details. | |
11 | ||
f3b197ac | 12 | |
4689ced9 PC |
13 | */ |
14 | ||
e02fb7aa JP |
15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
16 | ||
4689ced9 PC |
17 | #define DRV_NAME "uli526x" |
18 | #define DRV_VERSION "0.9.3" | |
19 | #define DRV_RELDATE "2005-7-29" | |
20 | ||
21 | #include <linux/module.h> | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/timer.h> | |
4689ced9 PC |
26 | #include <linux/errno.h> |
27 | #include <linux/ioport.h> | |
4689ced9 PC |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/spinlock.h> | |
6cafa99f | 37 | #include <linux/dma-mapping.h> |
1977f032 | 38 | #include <linux/bitops.h> |
4689ced9 PC |
39 | |
40 | #include <asm/processor.h> | |
4689ced9 PC |
41 | #include <asm/io.h> |
42 | #include <asm/dma.h> | |
43 | #include <asm/uaccess.h> | |
44 | ||
45 | ||
46 | /* Board/System/Debug information/definition ---------------- */ | |
47 | #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/ | |
48 | #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/ | |
49 | ||
50 | #define ULI526X_IO_SIZE 0x100 | |
51 | #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */ | |
52 | #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */ | |
53 | #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ | |
54 | #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ | |
55 | #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) | |
56 | #define TX_BUF_ALLOC 0x600 | |
57 | #define RX_ALLOC_SIZE 0x620 | |
58 | #define ULI526X_RESET 1 | |
59 | #define CR0_DEFAULT 0 | |
945a7876 | 60 | #define CR6_DEFAULT 0x22200000 |
4689ced9 PC |
61 | #define CR7_DEFAULT 0x180c1 |
62 | #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ | |
63 | #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ | |
64 | #define MAX_PACKET_SIZE 1514 | |
65 | #define ULI5261_MAX_MULTICAST 14 | |
66 | #define RX_COPY_SIZE 100 | |
67 | #define MAX_CHECK_PACKET 0x8000 | |
68 | ||
69 | #define ULI526X_10MHF 0 | |
70 | #define ULI526X_100MHF 1 | |
71 | #define ULI526X_10MFD 4 | |
72 | #define ULI526X_100MFD 5 | |
73 | #define ULI526X_AUTO 8 | |
74 | ||
75 | #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */ | |
76 | #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */ | |
77 | #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */ | |
78 | #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */ | |
79 | #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */ | |
80 | #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */ | |
81 | ||
82 | #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */ | |
83 | #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */ | |
84 | #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */ | |
85 | ||
e02fb7aa JP |
86 | #define ULI526X_DBUG(dbug_now, msg, value) \ |
87 | do { \ | |
88 | if (uli526x_debug || (dbug_now)) \ | |
89 | pr_err("%s %lx\n", (msg), (long) (value)); \ | |
90 | } while (0) | |
4689ced9 | 91 | |
e02fb7aa JP |
92 | #define SHOW_MEDIA_TYPE(mode) \ |
93 | pr_err("Change Speed to %sMhz %s duplex\n", \ | |
94 | mode & 1 ? "100" : "10", \ | |
95 | mode & 4 ? "full" : "half"); | |
4689ced9 PC |
96 | |
97 | ||
98 | /* CR9 definition: SROM/MII */ | |
99 | #define CR9_SROM_READ 0x4800 | |
100 | #define CR9_SRCS 0x1 | |
101 | #define CR9_SRCLK 0x2 | |
102 | #define CR9_CRDOUT 0x8 | |
103 | #define SROM_DATA_0 0x0 | |
104 | #define SROM_DATA_1 0x4 | |
105 | #define PHY_DATA_1 0x20000 | |
106 | #define PHY_DATA_0 0x00000 | |
107 | #define MDCLKH 0x10000 | |
108 | ||
109 | #define PHY_POWER_DOWN 0x800 | |
110 | ||
111 | #define SROM_V41_CODE 0x14 | |
112 | ||
945a7876 PC |
113 | #define SROM_CLK_WRITE(data, ioaddr) \ |
114 | outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \ | |
115 | udelay(5); \ | |
116 | outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \ | |
117 | udelay(5); \ | |
118 | outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \ | |
119 | udelay(5); | |
4689ced9 PC |
120 | |
121 | /* Structure/enum declaration ------------------------------- */ | |
122 | struct tx_desc { | |
c559a5bc | 123 | __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ |
4689ced9 PC |
124 | char *tx_buf_ptr; /* Data for us */ |
125 | struct tx_desc *next_tx_desc; | |
126 | } __attribute__(( aligned(32) )); | |
127 | ||
128 | struct rx_desc { | |
c559a5bc | 129 | __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ |
4689ced9 PC |
130 | struct sk_buff *rx_skb_ptr; /* Data for us */ |
131 | struct rx_desc *next_rx_desc; | |
132 | } __attribute__(( aligned(32) )); | |
133 | ||
134 | struct uli526x_board_info { | |
135 | u32 chip_id; /* Chip vendor/Device ID */ | |
945a7876 | 136 | struct net_device *next_dev; /* next device */ |
4689ced9 PC |
137 | struct pci_dev *pdev; /* PCI device */ |
138 | spinlock_t lock; | |
139 | ||
140 | long ioaddr; /* I/O base address */ | |
141 | u32 cr0_data; | |
142 | u32 cr5_data; | |
143 | u32 cr6_data; | |
144 | u32 cr7_data; | |
145 | u32 cr15_data; | |
146 | ||
147 | /* pointer for memory physical address */ | |
148 | dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */ | |
149 | dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */ | |
150 | dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */ | |
151 | dma_addr_t first_tx_desc_dma; | |
152 | dma_addr_t first_rx_desc_dma; | |
153 | ||
154 | /* descriptor pointer */ | |
155 | unsigned char *buf_pool_ptr; /* Tx buffer pool memory */ | |
156 | unsigned char *buf_pool_start; /* Tx buffer pool align dword */ | |
157 | unsigned char *desc_pool_ptr; /* descriptor pool memory */ | |
158 | struct tx_desc *first_tx_desc; | |
159 | struct tx_desc *tx_insert_ptr; | |
160 | struct tx_desc *tx_remove_ptr; | |
161 | struct rx_desc *first_rx_desc; | |
162 | struct rx_desc *rx_insert_ptr; | |
163 | struct rx_desc *rx_ready_ptr; /* packet come pointer */ | |
164 | unsigned long tx_packet_cnt; /* transmitted packet count */ | |
165 | unsigned long rx_avail_cnt; /* available rx descriptor count */ | |
166 | unsigned long interval_rx_cnt; /* rx packet count a callback time */ | |
167 | ||
168 | u16 dbug_cnt; | |
169 | u16 NIC_capability; /* NIC media capability */ | |
170 | u16 PHY_reg4; /* Saved Phyxcer register 4 value */ | |
171 | ||
172 | u8 media_mode; /* user specify media mode */ | |
173 | u8 op_mode; /* real work media mode */ | |
174 | u8 phy_addr; | |
175 | u8 link_failed; /* Ever link failed */ | |
176 | u8 wait_reset; /* Hardware failed, need to reset */ | |
177 | struct timer_list timer; | |
178 | ||
4689ced9 PC |
179 | /* Driver defined statistic counter */ |
180 | unsigned long tx_fifo_underrun; | |
181 | unsigned long tx_loss_carrier; | |
182 | unsigned long tx_no_carrier; | |
183 | unsigned long tx_late_collision; | |
184 | unsigned long tx_excessive_collision; | |
185 | unsigned long tx_jabber_timeout; | |
186 | unsigned long reset_count; | |
187 | unsigned long reset_cr8; | |
188 | unsigned long reset_fatal; | |
189 | unsigned long reset_TXtimeout; | |
190 | ||
191 | /* NIC SROM data */ | |
192 | unsigned char srom[128]; | |
f3b197ac | 193 | u8 init; |
4689ced9 PC |
194 | }; |
195 | ||
196 | enum uli526x_offsets { | |
197 | DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, | |
198 | DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, | |
199 | DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, | |
200 | DCR15 = 0x78 | |
201 | }; | |
202 | ||
203 | enum uli526x_CR6_bits { | |
204 | CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, | |
205 | CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, | |
206 | CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 | |
207 | }; | |
208 | ||
209 | /* Global variable declaration ----------------------------- */ | |
210 | static int __devinitdata printed_version; | |
03f54b3d | 211 | static const char version[] __devinitconst = |
4689ced9 PC |
212 | KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version " |
213 | DRV_VERSION " (" DRV_RELDATE ")\n"; | |
214 | ||
215 | static int uli526x_debug; | |
216 | static unsigned char uli526x_media_mode = ULI526X_AUTO; | |
217 | static u32 uli526x_cr6_user_set; | |
218 | ||
219 | /* For module input parameter */ | |
220 | static int debug; | |
221 | static u32 cr6set; | |
99bb2579 | 222 | static int mode = 8; |
4689ced9 PC |
223 | |
224 | /* function declaration ------------------------------------- */ | |
945a7876 | 225 | static int uli526x_open(struct net_device *); |
ad096463 SH |
226 | static netdev_tx_t uli526x_start_xmit(struct sk_buff *, |
227 | struct net_device *); | |
945a7876 | 228 | static int uli526x_stop(struct net_device *); |
945a7876 | 229 | static void uli526x_set_filter_mode(struct net_device *); |
7282d491 | 230 | static const struct ethtool_ops netdev_ethtool_ops; |
945a7876 | 231 | static u16 read_srom_word(long, int); |
7d12e780 | 232 | static irqreturn_t uli526x_interrupt(int, void *); |
7fa0cba3 AV |
233 | #ifdef CONFIG_NET_POLL_CONTROLLER |
234 | static void uli526x_poll(struct net_device *dev); | |
235 | #endif | |
4689ced9 PC |
236 | static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long); |
237 | static void allocate_rx_buffer(struct uli526x_board_info *); | |
238 | static void update_cr6(u32, unsigned long); | |
945a7876 | 239 | static void send_filter_frame(struct net_device *, int); |
4689ced9 PC |
240 | static u16 phy_read(unsigned long, u8, u8, u32); |
241 | static u16 phy_readby_cr10(unsigned long, u8, u8); | |
242 | static void phy_write(unsigned long, u8, u8, u16, u32); | |
243 | static void phy_writeby_cr10(unsigned long, u8, u8, u16); | |
244 | static void phy_write_1bit(unsigned long, u32, u32); | |
245 | static u16 phy_read_1bit(unsigned long, u32); | |
246 | static u8 uli526x_sense_speed(struct uli526x_board_info *); | |
247 | static void uli526x_process_mode(struct uli526x_board_info *); | |
248 | static void uli526x_timer(unsigned long); | |
945a7876 PC |
249 | static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *); |
250 | static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *); | |
4689ced9 | 251 | static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *); |
945a7876 | 252 | static void uli526x_dynamic_reset(struct net_device *); |
4689ced9 | 253 | static void uli526x_free_rxbuffer(struct uli526x_board_info *); |
945a7876 | 254 | static void uli526x_init(struct net_device *); |
4689ced9 PC |
255 | static void uli526x_set_phyxcer(struct uli526x_board_info *); |
256 | ||
945a7876 | 257 | /* ULI526X network board routine ---------------------------- */ |
4689ced9 | 258 | |
dfefe02b SH |
259 | static const struct net_device_ops netdev_ops = { |
260 | .ndo_open = uli526x_open, | |
261 | .ndo_stop = uli526x_stop, | |
262 | .ndo_start_xmit = uli526x_start_xmit, | |
263 | .ndo_set_multicast_list = uli526x_set_filter_mode, | |
264 | .ndo_change_mtu = eth_change_mtu, | |
265 | .ndo_set_mac_address = eth_mac_addr, | |
266 | .ndo_validate_addr = eth_validate_addr, | |
267 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
268 | .ndo_poll_controller = uli526x_poll, | |
269 | #endif | |
270 | }; | |
271 | ||
4689ced9 | 272 | /* |
945a7876 | 273 | * Search ULI526X board, allocate space and register it |
4689ced9 PC |
274 | */ |
275 | ||
276 | static int __devinit uli526x_init_one (struct pci_dev *pdev, | |
277 | const struct pci_device_id *ent) | |
278 | { | |
279 | struct uli526x_board_info *db; /* board information structure */ | |
280 | struct net_device *dev; | |
281 | int i, err; | |
f3b197ac | 282 | |
4689ced9 PC |
283 | ULI526X_DBUG(0, "uli526x_init_one()", 0); |
284 | ||
285 | if (!printed_version++) | |
286 | printk(version); | |
287 | ||
288 | /* Init network device */ | |
289 | dev = alloc_etherdev(sizeof(*db)); | |
290 | if (dev == NULL) | |
291 | return -ENOMEM; | |
4689ced9 PC |
292 | SET_NETDEV_DEV(dev, &pdev->dev); |
293 | ||
284901a9 | 294 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { |
e02fb7aa | 295 | pr_warning("32-bit PCI DMA not available\n"); |
4689ced9 PC |
296 | err = -ENODEV; |
297 | goto err_out_free; | |
298 | } | |
299 | ||
300 | /* Enable Master/IO access, Disable memory access */ | |
301 | err = pci_enable_device(pdev); | |
302 | if (err) | |
303 | goto err_out_free; | |
304 | ||
305 | if (!pci_resource_start(pdev, 0)) { | |
e02fb7aa | 306 | pr_err("I/O base is zero\n"); |
4689ced9 PC |
307 | err = -ENODEV; |
308 | goto err_out_disable; | |
309 | } | |
310 | ||
311 | if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) { | |
e02fb7aa | 312 | pr_err("Allocated I/O size too small\n"); |
4689ced9 PC |
313 | err = -ENODEV; |
314 | goto err_out_disable; | |
315 | } | |
316 | ||
317 | if (pci_request_regions(pdev, DRV_NAME)) { | |
e02fb7aa | 318 | pr_err("Failed to request PCI regions\n"); |
4689ced9 PC |
319 | err = -ENODEV; |
320 | goto err_out_disable; | |
321 | } | |
322 | ||
4689ced9 PC |
323 | /* Init system & device */ |
324 | db = netdev_priv(dev); | |
325 | ||
326 | /* Allocate Tx/Rx descriptor memory */ | |
327 | db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr); | |
945a7876 PC |
328 | if(db->desc_pool_ptr == NULL) |
329 | { | |
330 | err = -ENOMEM; | |
331 | goto err_out_nomem; | |
332 | } | |
4689ced9 | 333 | db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr); |
945a7876 PC |
334 | if(db->buf_pool_ptr == NULL) |
335 | { | |
336 | err = -ENOMEM; | |
337 | goto err_out_nomem; | |
338 | } | |
f3b197ac | 339 | |
4689ced9 PC |
340 | db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; |
341 | db->first_tx_desc_dma = db->desc_pool_dma_ptr; | |
342 | db->buf_pool_start = db->buf_pool_ptr; | |
343 | db->buf_pool_dma_start = db->buf_pool_dma_ptr; | |
344 | ||
345 | db->chip_id = ent->driver_data; | |
346 | db->ioaddr = pci_resource_start(pdev, 0); | |
f3b197ac | 347 | |
4689ced9 PC |
348 | db->pdev = pdev; |
349 | db->init = 1; | |
f3b197ac | 350 | |
4689ced9 PC |
351 | dev->base_addr = db->ioaddr; |
352 | dev->irq = pdev->irq; | |
353 | pci_set_drvdata(pdev, dev); | |
f3b197ac | 354 | |
4689ced9 | 355 | /* Register some necessary functions */ |
dfefe02b | 356 | dev->netdev_ops = &netdev_ops; |
4689ced9 | 357 | dev->ethtool_ops = &netdev_ethtool_ops; |
dfefe02b | 358 | |
4689ced9 PC |
359 | spin_lock_init(&db->lock); |
360 | ||
f3b197ac | 361 | |
4689ced9 PC |
362 | /* read 64 word srom data */ |
363 | for (i = 0; i < 64; i++) | |
c559a5bc | 364 | ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i)); |
4689ced9 PC |
365 | |
366 | /* Set Node address */ | |
945a7876 | 367 | if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */ |
4689ced9 PC |
368 | { |
369 | outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode | |
370 | outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port | |
371 | outl(0, db->ioaddr + DCR14); //Clear reset port | |
372 | outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer | |
373 | outl(0, db->ioaddr + DCR14); //Clear reset port | |
374 | outl(0, db->ioaddr + DCR13); //Clear CR13 | |
375 | outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port | |
376 | //Read MAC address from CR14 | |
377 | for (i = 0; i < 6; i++) | |
378 | dev->dev_addr[i] = inl(db->ioaddr + DCR14); | |
379 | //Read end | |
380 | outl(0, db->ioaddr + DCR13); //Clear CR13 | |
381 | outl(0, db->ioaddr + DCR0); //Clear CR0 | |
382 | udelay(10); | |
383 | } | |
384 | else /*Exist SROM*/ | |
385 | { | |
386 | for (i = 0; i < 6; i++) | |
387 | dev->dev_addr[i] = db->srom[20 + i]; | |
388 | } | |
389 | err = register_netdev (dev); | |
390 | if (err) | |
391 | goto err_out_res; | |
392 | ||
e02fb7aa JP |
393 | dev_info(&dev->dev, "ULi M%04lx at pci%s, %pM, irq %d\n", |
394 | ent->driver_data >> 16, pci_name(pdev), | |
395 | dev->dev_addr, dev->irq); | |
4689ced9 PC |
396 | |
397 | pci_set_master(pdev); | |
398 | ||
399 | return 0; | |
400 | ||
401 | err_out_res: | |
402 | pci_release_regions(pdev); | |
945a7876 PC |
403 | err_out_nomem: |
404 | if(db->desc_pool_ptr) | |
405 | pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, | |
406 | db->desc_pool_ptr, db->desc_pool_dma_ptr); | |
f3b197ac | 407 | |
945a7876 PC |
408 | if(db->buf_pool_ptr != NULL) |
409 | pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, | |
410 | db->buf_pool_ptr, db->buf_pool_dma_ptr); | |
4689ced9 PC |
411 | err_out_disable: |
412 | pci_disable_device(pdev); | |
413 | err_out_free: | |
414 | pci_set_drvdata(pdev, NULL); | |
415 | free_netdev(dev); | |
416 | ||
417 | return err; | |
418 | } | |
419 | ||
420 | ||
421 | static void __devexit uli526x_remove_one (struct pci_dev *pdev) | |
422 | { | |
423 | struct net_device *dev = pci_get_drvdata(pdev); | |
424 | struct uli526x_board_info *db = netdev_priv(dev); | |
425 | ||
426 | ULI526X_DBUG(0, "uli526x_remove_one()", 0); | |
427 | ||
945a7876 PC |
428 | pci_free_consistent(db->pdev, sizeof(struct tx_desc) * |
429 | DESC_ALL_CNT + 0x20, db->desc_pool_ptr, | |
430 | db->desc_pool_dma_ptr); | |
431 | pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, | |
432 | db->buf_pool_ptr, db->buf_pool_dma_ptr); | |
433 | unregister_netdev(dev); | |
434 | pci_release_regions(pdev); | |
435 | free_netdev(dev); /* free board information */ | |
436 | pci_set_drvdata(pdev, NULL); | |
437 | pci_disable_device(pdev); | |
4689ced9 PC |
438 | ULI526X_DBUG(0, "uli526x_remove_one() exit", 0); |
439 | } | |
440 | ||
441 | ||
442 | /* | |
443 | * Open the interface. | |
945a7876 | 444 | * The interface is opened whenever "ifconfig" activates it. |
4689ced9 PC |
445 | */ |
446 | ||
945a7876 | 447 | static int uli526x_open(struct net_device *dev) |
4689ced9 PC |
448 | { |
449 | int ret; | |
450 | struct uli526x_board_info *db = netdev_priv(dev); | |
f3b197ac | 451 | |
4689ced9 PC |
452 | ULI526X_DBUG(0, "uli526x_open", 0); |
453 | ||
4689ced9 PC |
454 | /* system variable init */ |
455 | db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set; | |
4689ced9 PC |
456 | db->tx_packet_cnt = 0; |
457 | db->rx_avail_cnt = 0; | |
458 | db->link_failed = 1; | |
459 | netif_carrier_off(dev); | |
460 | db->wait_reset = 0; | |
461 | ||
462 | db->NIC_capability = 0xf; /* All capability*/ | |
463 | db->PHY_reg4 = 0x1e0; | |
464 | ||
465 | /* CR6 operation mode decision */ | |
466 | db->cr6_data |= ULI526X_TXTH_256; | |
467 | db->cr0_data = CR0_DEFAULT; | |
f3b197ac | 468 | |
945a7876 | 469 | /* Initialize ULI526X board */ |
4689ced9 PC |
470 | uli526x_init(dev); |
471 | ||
a0607fd3 | 472 | ret = request_irq(dev->irq, uli526x_interrupt, IRQF_SHARED, dev->name, dev); |
afd8e399 AV |
473 | if (ret) |
474 | return ret; | |
475 | ||
4689ced9 PC |
476 | /* Active System Interface */ |
477 | netif_wake_queue(dev); | |
478 | ||
479 | /* set and active a timer process */ | |
480 | init_timer(&db->timer); | |
481 | db->timer.expires = ULI526X_TIMER_WUT + HZ * 2; | |
482 | db->timer.data = (unsigned long)dev; | |
c061b18d | 483 | db->timer.function = uli526x_timer; |
4689ced9 PC |
484 | add_timer(&db->timer); |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | ||
945a7876 | 490 | /* Initialize ULI526X board |
4689ced9 | 491 | * Reset ULI526X board |
945a7876 | 492 | * Initialize TX/Rx descriptor chain structure |
4689ced9 PC |
493 | * Send the set-up frame |
494 | * Enable Tx/Rx machine | |
495 | */ | |
496 | ||
945a7876 | 497 | static void uli526x_init(struct net_device *dev) |
4689ced9 PC |
498 | { |
499 | struct uli526x_board_info *db = netdev_priv(dev); | |
500 | unsigned long ioaddr = db->ioaddr; | |
501 | u8 phy_tmp; | |
7a7d23da | 502 | u8 timeout; |
4689ced9 PC |
503 | u16 phy_value; |
504 | u16 phy_reg_reset; | |
505 | ||
7a7d23da | 506 | |
4689ced9 PC |
507 | ULI526X_DBUG(0, "uli526x_init()", 0); |
508 | ||
509 | /* Reset M526x MAC controller */ | |
510 | outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */ | |
511 | udelay(100); | |
512 | outl(db->cr0_data, ioaddr + DCR0); | |
513 | udelay(5); | |
514 | ||
515 | /* Phy addr : In some boards,M5261/M5263 phy address != 1 */ | |
516 | db->phy_addr = 1; | |
517 | for(phy_tmp=0;phy_tmp<32;phy_tmp++) | |
518 | { | |
519 | phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add | |
520 | if(phy_value != 0xffff&&phy_value!=0) | |
521 | { | |
522 | db->phy_addr = phy_tmp; | |
523 | break; | |
524 | } | |
525 | } | |
526 | if(phy_tmp == 32) | |
e02fb7aa | 527 | pr_warning("Can not find the phy address!!!"); |
4689ced9 PC |
528 | /* Parser SROM and media mode */ |
529 | db->media_mode = uli526x_media_mode; | |
530 | ||
7a7d23da | 531 | /* phyxcer capability setting */ |
4689ced9 PC |
532 | phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id); |
533 | phy_reg_reset = (phy_reg_reset | 0x8000); | |
534 | phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id); | |
7a7d23da GG |
535 | |
536 | /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management | |
537 | * functions") or phy data sheet for details on phy reset | |
538 | */ | |
4689ced9 | 539 | udelay(500); |
7a7d23da GG |
540 | timeout = 10; |
541 | while (timeout-- && | |
542 | phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000) | |
543 | udelay(100); | |
4689ced9 PC |
544 | |
545 | /* Process Phyxcer Media Mode */ | |
546 | uli526x_set_phyxcer(db); | |
547 | ||
548 | /* Media Mode Process */ | |
549 | if ( !(db->media_mode & ULI526X_AUTO) ) | |
550 | db->op_mode = db->media_mode; /* Force Mode */ | |
551 | ||
945a7876 | 552 | /* Initialize Transmit/Receive decriptor and CR3/4 */ |
4689ced9 PC |
553 | uli526x_descriptor_init(db, ioaddr); |
554 | ||
555 | /* Init CR6 to program M526X operation */ | |
556 | update_cr6(db->cr6_data, ioaddr); | |
557 | ||
558 | /* Send setup frame */ | |
4cd24eaf | 559 | send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */ |
4689ced9 PC |
560 | |
561 | /* Init CR7, interrupt active bit */ | |
562 | db->cr7_data = CR7_DEFAULT; | |
563 | outl(db->cr7_data, ioaddr + DCR7); | |
564 | ||
565 | /* Init CR15, Tx jabber and Rx watchdog timer */ | |
566 | outl(db->cr15_data, ioaddr + DCR15); | |
567 | ||
568 | /* Enable ULI526X Tx/Rx function */ | |
569 | db->cr6_data |= CR6_RXSC | CR6_TXSC; | |
570 | update_cr6(db->cr6_data, ioaddr); | |
571 | } | |
572 | ||
573 | ||
574 | /* | |
575 | * Hardware start transmission. | |
576 | * Send a packet to media from the upper layer. | |
577 | */ | |
578 | ||
ad096463 SH |
579 | static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb, |
580 | struct net_device *dev) | |
4689ced9 PC |
581 | { |
582 | struct uli526x_board_info *db = netdev_priv(dev); | |
583 | struct tx_desc *txptr; | |
584 | unsigned long flags; | |
585 | ||
586 | ULI526X_DBUG(0, "uli526x_start_xmit", 0); | |
587 | ||
588 | /* Resource flag check */ | |
589 | netif_stop_queue(dev); | |
590 | ||
591 | /* Too large packet check */ | |
592 | if (skb->len > MAX_PACKET_SIZE) { | |
e02fb7aa | 593 | pr_err("big packet = %d\n", (u16)skb->len); |
4689ced9 | 594 | dev_kfree_skb(skb); |
6ed10654 | 595 | return NETDEV_TX_OK; |
4689ced9 PC |
596 | } |
597 | ||
598 | spin_lock_irqsave(&db->lock, flags); | |
599 | ||
600 | /* No Tx resource check, it never happen nromally */ | |
601 | if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) { | |
602 | spin_unlock_irqrestore(&db->lock, flags); | |
e02fb7aa | 603 | pr_err("No Tx resource %ld\n", db->tx_packet_cnt); |
5b548140 | 604 | return NETDEV_TX_BUSY; |
4689ced9 PC |
605 | } |
606 | ||
607 | /* Disable NIC interrupt */ | |
608 | outl(0, dev->base_addr + DCR7); | |
609 | ||
610 | /* transmit this packet */ | |
611 | txptr = db->tx_insert_ptr; | |
d626f62b | 612 | skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len); |
4689ced9 PC |
613 | txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len); |
614 | ||
615 | /* Point to next transmit free descriptor */ | |
616 | db->tx_insert_ptr = txptr->next_tx_desc; | |
617 | ||
618 | /* Transmit Packet Process */ | |
619 | if ( (db->tx_packet_cnt < TX_DESC_CNT) ) { | |
620 | txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ | |
621 | db->tx_packet_cnt++; /* Ready to send */ | |
622 | outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ | |
623 | dev->trans_start = jiffies; /* saved time stamp */ | |
624 | } | |
625 | ||
626 | /* Tx resource check */ | |
627 | if ( db->tx_packet_cnt < TX_FREE_DESC_CNT ) | |
628 | netif_wake_queue(dev); | |
629 | ||
630 | /* Restore CR7 to enable interrupt */ | |
631 | spin_unlock_irqrestore(&db->lock, flags); | |
632 | outl(db->cr7_data, dev->base_addr + DCR7); | |
f3b197ac | 633 | |
4689ced9 PC |
634 | /* free this SKB */ |
635 | dev_kfree_skb(skb); | |
636 | ||
6ed10654 | 637 | return NETDEV_TX_OK; |
4689ced9 PC |
638 | } |
639 | ||
640 | ||
641 | /* | |
642 | * Stop the interface. | |
643 | * The interface is stopped when it is brought. | |
644 | */ | |
645 | ||
945a7876 | 646 | static int uli526x_stop(struct net_device *dev) |
4689ced9 PC |
647 | { |
648 | struct uli526x_board_info *db = netdev_priv(dev); | |
649 | unsigned long ioaddr = dev->base_addr; | |
650 | ||
651 | ULI526X_DBUG(0, "uli526x_stop", 0); | |
652 | ||
653 | /* disable system */ | |
654 | netif_stop_queue(dev); | |
655 | ||
656 | /* deleted timer */ | |
657 | del_timer_sync(&db->timer); | |
658 | ||
659 | /* Reset & stop ULI526X board */ | |
660 | outl(ULI526X_RESET, ioaddr + DCR0); | |
661 | udelay(5); | |
662 | phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); | |
663 | ||
664 | /* free interrupt */ | |
665 | free_irq(dev->irq, dev); | |
666 | ||
667 | /* free allocated rx buffer */ | |
668 | uli526x_free_rxbuffer(db); | |
669 | ||
670 | #if 0 | |
671 | /* show statistic counter */ | |
672 | printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n", | |
673 | db->tx_fifo_underrun, db->tx_excessive_collision, | |
674 | db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier, | |
675 | db->tx_jabber_timeout, db->reset_count, db->reset_cr8, | |
676 | db->reset_fatal, db->reset_TXtimeout); | |
677 | #endif | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
682 | ||
683 | /* | |
684 | * M5261/M5263 insterrupt handler | |
685 | * receive the packet to upper layer, free the transmitted packet | |
686 | */ | |
687 | ||
7d12e780 | 688 | static irqreturn_t uli526x_interrupt(int irq, void *dev_id) |
4689ced9 | 689 | { |
945a7876 | 690 | struct net_device *dev = dev_id; |
4689ced9 PC |
691 | struct uli526x_board_info *db = netdev_priv(dev); |
692 | unsigned long ioaddr = dev->base_addr; | |
693 | unsigned long flags; | |
694 | ||
4689ced9 PC |
695 | spin_lock_irqsave(&db->lock, flags); |
696 | outl(0, ioaddr + DCR7); | |
697 | ||
698 | /* Got ULI526X status */ | |
699 | db->cr5_data = inl(ioaddr + DCR5); | |
700 | outl(db->cr5_data, ioaddr + DCR5); | |
701 | if ( !(db->cr5_data & 0x180c1) ) { | |
7fa0cba3 | 702 | /* Restore CR7 to enable interrupt mask */ |
4689ced9 | 703 | outl(db->cr7_data, ioaddr + DCR7); |
7fa0cba3 | 704 | spin_unlock_irqrestore(&db->lock, flags); |
4689ced9 PC |
705 | return IRQ_HANDLED; |
706 | } | |
707 | ||
4689ced9 PC |
708 | /* Check system status */ |
709 | if (db->cr5_data & 0x2000) { | |
710 | /* system bus error happen */ | |
711 | ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data); | |
712 | db->reset_fatal++; | |
713 | db->wait_reset = 1; /* Need to RESET */ | |
714 | spin_unlock_irqrestore(&db->lock, flags); | |
715 | return IRQ_HANDLED; | |
716 | } | |
717 | ||
718 | /* Received the coming packet */ | |
719 | if ( (db->cr5_data & 0x40) && db->rx_avail_cnt ) | |
720 | uli526x_rx_packet(dev, db); | |
721 | ||
722 | /* reallocate rx descriptor buffer */ | |
723 | if (db->rx_avail_cnt<RX_DESC_CNT) | |
724 | allocate_rx_buffer(db); | |
725 | ||
726 | /* Free the transmitted descriptor */ | |
727 | if ( db->cr5_data & 0x01) | |
728 | uli526x_free_tx_pkt(dev, db); | |
729 | ||
730 | /* Restore CR7 to enable interrupt mask */ | |
731 | outl(db->cr7_data, ioaddr + DCR7); | |
732 | ||
733 | spin_unlock_irqrestore(&db->lock, flags); | |
734 | return IRQ_HANDLED; | |
735 | } | |
736 | ||
7fa0cba3 AV |
737 | #ifdef CONFIG_NET_POLL_CONTROLLER |
738 | static void uli526x_poll(struct net_device *dev) | |
739 | { | |
740 | /* ISR grabs the irqsave lock, so this should be safe */ | |
741 | uli526x_interrupt(dev->irq, dev); | |
742 | } | |
743 | #endif | |
4689ced9 PC |
744 | |
745 | /* | |
746 | * Free TX resource after TX complete | |
747 | */ | |
748 | ||
dfefe02b SH |
749 | static void uli526x_free_tx_pkt(struct net_device *dev, |
750 | struct uli526x_board_info * db) | |
4689ced9 PC |
751 | { |
752 | struct tx_desc *txptr; | |
4689ced9 PC |
753 | u32 tdes0; |
754 | ||
755 | txptr = db->tx_remove_ptr; | |
756 | while(db->tx_packet_cnt) { | |
757 | tdes0 = le32_to_cpu(txptr->tdes0); | |
758 | /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */ | |
759 | if (tdes0 & 0x80000000) | |
760 | break; | |
761 | ||
762 | /* A packet sent completed */ | |
763 | db->tx_packet_cnt--; | |
dfefe02b | 764 | dev->stats.tx_packets++; |
4689ced9 PC |
765 | |
766 | /* Transmit statistic counter */ | |
767 | if ( tdes0 != 0x7fffffff ) { | |
768 | /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */ | |
dfefe02b SH |
769 | dev->stats.collisions += (tdes0 >> 3) & 0xf; |
770 | dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff; | |
4689ced9 | 771 | if (tdes0 & TDES0_ERR_MASK) { |
dfefe02b | 772 | dev->stats.tx_errors++; |
4689ced9 PC |
773 | if (tdes0 & 0x0002) { /* UnderRun */ |
774 | db->tx_fifo_underrun++; | |
775 | if ( !(db->cr6_data & CR6_SFT) ) { | |
776 | db->cr6_data = db->cr6_data | CR6_SFT; | |
777 | update_cr6(db->cr6_data, db->ioaddr); | |
778 | } | |
779 | } | |
780 | if (tdes0 & 0x0100) | |
781 | db->tx_excessive_collision++; | |
782 | if (tdes0 & 0x0200) | |
783 | db->tx_late_collision++; | |
784 | if (tdes0 & 0x0400) | |
785 | db->tx_no_carrier++; | |
786 | if (tdes0 & 0x0800) | |
787 | db->tx_loss_carrier++; | |
788 | if (tdes0 & 0x4000) | |
789 | db->tx_jabber_timeout++; | |
790 | } | |
791 | } | |
792 | ||
793 | txptr = txptr->next_tx_desc; | |
794 | }/* End of while */ | |
795 | ||
796 | /* Update TX remove pointer to next */ | |
797 | db->tx_remove_ptr = txptr; | |
798 | ||
799 | /* Resource available check */ | |
800 | if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT ) | |
801 | netif_wake_queue(dev); /* Active upper layer, send again */ | |
802 | } | |
803 | ||
804 | ||
805 | /* | |
806 | * Receive the come packet and pass to upper layer | |
807 | */ | |
808 | ||
945a7876 | 809 | static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db) |
4689ced9 PC |
810 | { |
811 | struct rx_desc *rxptr; | |
812 | struct sk_buff *skb; | |
813 | int rxlen; | |
814 | u32 rdes0; | |
f3b197ac | 815 | |
4689ced9 PC |
816 | rxptr = db->rx_ready_ptr; |
817 | ||
818 | while(db->rx_avail_cnt) { | |
819 | rdes0 = le32_to_cpu(rxptr->rdes0); | |
820 | if (rdes0 & 0x80000000) /* packet owner check */ | |
821 | { | |
822 | break; | |
823 | } | |
824 | ||
825 | db->rx_avail_cnt--; | |
826 | db->interval_rx_cnt++; | |
827 | ||
828 | pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | |
829 | if ( (rdes0 & 0x300) != 0x300) { | |
830 | /* A packet without First/Last flag */ | |
831 | /* reuse this SKB */ | |
832 | ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); | |
833 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); | |
834 | } else { | |
835 | /* A packet with First/Last flag */ | |
836 | rxlen = ( (rdes0 >> 16) & 0x3fff) - 4; | |
837 | ||
838 | /* error summary bit check */ | |
839 | if (rdes0 & 0x8000) { | |
840 | /* This is a error packet */ | |
841 | //printk(DRV_NAME ": rdes0: %lx\n", rdes0); | |
dfefe02b | 842 | dev->stats.rx_errors++; |
4689ced9 | 843 | if (rdes0 & 1) |
dfefe02b | 844 | dev->stats.rx_fifo_errors++; |
4689ced9 | 845 | if (rdes0 & 2) |
dfefe02b | 846 | dev->stats.rx_crc_errors++; |
4689ced9 | 847 | if (rdes0 & 0x80) |
dfefe02b | 848 | dev->stats.rx_length_errors++; |
4689ced9 PC |
849 | } |
850 | ||
851 | if ( !(rdes0 & 0x8000) || | |
852 | ((db->cr6_data & CR6_PM) && (rxlen>6)) ) { | |
ac90a149 KM |
853 | struct sk_buff *new_skb = NULL; |
854 | ||
4689ced9 | 855 | skb = rxptr->rx_skb_ptr; |
f3b197ac | 856 | |
4689ced9 PC |
857 | /* Good packet, send to upper layer */ |
858 | /* Shorst packet used new SKB */ | |
ac90a149 | 859 | if ((rxlen < RX_COPY_SIZE) && |
7855f761 | 860 | (((new_skb = dev_alloc_skb(rxlen + 2)) != NULL))) { |
ac90a149 | 861 | skb = new_skb; |
4689ced9 | 862 | /* size less than COPY_SIZE, allocate a rxlen SKB */ |
4689ced9 | 863 | skb_reserve(skb, 2); /* 16byte align */ |
27a884dc ACM |
864 | memcpy(skb_put(skb, rxlen), |
865 | skb_tail_pointer(rxptr->rx_skb_ptr), | |
866 | rxlen); | |
4689ced9 | 867 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); |
4c13eb66 | 868 | } else |
4689ced9 | 869 | skb_put(skb, rxlen); |
4c13eb66 | 870 | |
4689ced9 PC |
871 | skb->protocol = eth_type_trans(skb, dev); |
872 | netif_rx(skb); | |
dfefe02b SH |
873 | dev->stats.rx_packets++; |
874 | dev->stats.rx_bytes += rxlen; | |
f3b197ac | 875 | |
4689ced9 PC |
876 | } else { |
877 | /* Reuse SKB buffer when the packet is error */ | |
878 | ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); | |
879 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); | |
880 | } | |
881 | } | |
882 | ||
883 | rxptr = rxptr->next_rx_desc; | |
884 | } | |
885 | ||
886 | db->rx_ready_ptr = rxptr; | |
887 | } | |
888 | ||
889 | ||
4689ced9 PC |
890 | /* |
891 | * Set ULI526X multicast address | |
892 | */ | |
893 | ||
945a7876 | 894 | static void uli526x_set_filter_mode(struct net_device * dev) |
4689ced9 | 895 | { |
8f15ea42 | 896 | struct uli526x_board_info *db = netdev_priv(dev); |
4689ced9 PC |
897 | unsigned long flags; |
898 | ||
899 | ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0); | |
900 | spin_lock_irqsave(&db->lock, flags); | |
901 | ||
902 | if (dev->flags & IFF_PROMISC) { | |
903 | ULI526X_DBUG(0, "Enable PROM Mode", 0); | |
904 | db->cr6_data |= CR6_PM | CR6_PBF; | |
905 | update_cr6(db->cr6_data, db->ioaddr); | |
906 | spin_unlock_irqrestore(&db->lock, flags); | |
907 | return; | |
908 | } | |
909 | ||
4cd24eaf JP |
910 | if (dev->flags & IFF_ALLMULTI || |
911 | netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) { | |
912 | ULI526X_DBUG(0, "Pass all multicast address", | |
913 | netdev_mc_count(dev)); | |
4689ced9 PC |
914 | db->cr6_data &= ~(CR6_PM | CR6_PBF); |
915 | db->cr6_data |= CR6_PAM; | |
916 | spin_unlock_irqrestore(&db->lock, flags); | |
917 | return; | |
918 | } | |
919 | ||
4cd24eaf JP |
920 | ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev)); |
921 | send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */ | |
4689ced9 PC |
922 | spin_unlock_irqrestore(&db->lock, flags); |
923 | } | |
924 | ||
925 | static void | |
926 | ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd) | |
927 | { | |
945a7876 PC |
928 | ecmd->supported = (SUPPORTED_10baseT_Half | |
929 | SUPPORTED_10baseT_Full | | |
930 | SUPPORTED_100baseT_Half | | |
931 | SUPPORTED_100baseT_Full | | |
932 | SUPPORTED_Autoneg | | |
933 | SUPPORTED_MII); | |
f3b197ac | 934 | |
945a7876 PC |
935 | ecmd->advertising = (ADVERTISED_10baseT_Half | |
936 | ADVERTISED_10baseT_Full | | |
937 | ADVERTISED_100baseT_Half | | |
938 | ADVERTISED_100baseT_Full | | |
939 | ADVERTISED_Autoneg | | |
940 | ADVERTISED_MII); | |
4689ced9 PC |
941 | |
942 | ||
945a7876 PC |
943 | ecmd->port = PORT_MII; |
944 | ecmd->phy_address = db->phy_addr; | |
4689ced9 | 945 | |
945a7876 | 946 | ecmd->transceiver = XCVR_EXTERNAL; |
f3b197ac | 947 | |
4689ced9 PC |
948 | ecmd->speed = 10; |
949 | ecmd->duplex = DUPLEX_HALF; | |
f3b197ac | 950 | |
4689ced9 PC |
951 | if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) |
952 | { | |
f3b197ac | 953 | ecmd->speed = 100; |
4689ced9 PC |
954 | } |
955 | if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) | |
956 | { | |
957 | ecmd->duplex = DUPLEX_FULL; | |
958 | } | |
959 | if(db->link_failed) | |
960 | { | |
961 | ecmd->speed = -1; | |
f3b197ac | 962 | ecmd->duplex = -1; |
4689ced9 | 963 | } |
f3b197ac | 964 | |
4689ced9 | 965 | if (db->media_mode & ULI526X_AUTO) |
f3b197ac | 966 | { |
4689ced9 PC |
967 | ecmd->autoneg = AUTONEG_ENABLE; |
968 | } | |
4689ced9 PC |
969 | } |
970 | ||
971 | static void netdev_get_drvinfo(struct net_device *dev, | |
972 | struct ethtool_drvinfo *info) | |
973 | { | |
974 | struct uli526x_board_info *np = netdev_priv(dev); | |
975 | ||
976 | strcpy(info->driver, DRV_NAME); | |
977 | strcpy(info->version, DRV_VERSION); | |
978 | if (np->pdev) | |
979 | strcpy(info->bus_info, pci_name(np->pdev)); | |
980 | else | |
981 | sprintf(info->bus_info, "EISA 0x%lx %d", | |
982 | dev->base_addr, dev->irq); | |
983 | } | |
984 | ||
985 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { | |
986 | struct uli526x_board_info *np = netdev_priv(dev); | |
f3b197ac | 987 | |
4689ced9 | 988 | ULi_ethtool_gset(np, cmd); |
f3b197ac | 989 | |
4689ced9 PC |
990 | return 0; |
991 | } | |
992 | ||
993 | static u32 netdev_get_link(struct net_device *dev) { | |
994 | struct uli526x_board_info *np = netdev_priv(dev); | |
f3b197ac | 995 | |
4689ced9 PC |
996 | if(np->link_failed) |
997 | return 0; | |
998 | else | |
999 | return 1; | |
1000 | } | |
1001 | ||
1002 | static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1003 | { | |
1004 | wol->supported = WAKE_PHY | WAKE_MAGIC; | |
1005 | wol->wolopts = 0; | |
1006 | } | |
1007 | ||
7282d491 | 1008 | static const struct ethtool_ops netdev_ethtool_ops = { |
4689ced9 PC |
1009 | .get_drvinfo = netdev_get_drvinfo, |
1010 | .get_settings = netdev_get_settings, | |
1011 | .get_link = netdev_get_link, | |
1012 | .get_wol = uli526x_get_wol, | |
1013 | }; | |
1014 | ||
1015 | /* | |
1016 | * A periodic timer routine | |
1017 | * Dynamic media sense, allocate Rx buffer... | |
1018 | */ | |
1019 | ||
1020 | static void uli526x_timer(unsigned long data) | |
1021 | { | |
1022 | u32 tmp_cr8; | |
1023 | unsigned char tmp_cr12=0; | |
945a7876 | 1024 | struct net_device *dev = (struct net_device *) data; |
4689ced9 PC |
1025 | struct uli526x_board_info *db = netdev_priv(dev); |
1026 | unsigned long flags; | |
1027 | u8 TmpSpeed=10; | |
f3b197ac | 1028 | |
4689ced9 PC |
1029 | //ULI526X_DBUG(0, "uli526x_timer()", 0); |
1030 | spin_lock_irqsave(&db->lock, flags); | |
1031 | ||
f3b197ac | 1032 | |
4689ced9 PC |
1033 | /* Dynamic reset ULI526X : system error or transmit time-out */ |
1034 | tmp_cr8 = inl(db->ioaddr + DCR8); | |
1035 | if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { | |
1036 | db->reset_cr8++; | |
1037 | db->wait_reset = 1; | |
1038 | } | |
1039 | db->interval_rx_cnt = 0; | |
1040 | ||
1041 | /* TX polling kick monitor */ | |
1042 | if ( db->tx_packet_cnt && | |
1ae5dc34 | 1043 | time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) { |
f3b197ac | 1044 | outl(0x1, dev->base_addr + DCR1); // Tx polling again |
4689ced9 | 1045 | |
f3b197ac | 1046 | // TX Timeout |
1ae5dc34 | 1047 | if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) { |
4689ced9 PC |
1048 | db->reset_TXtimeout++; |
1049 | db->wait_reset = 1; | |
1050 | printk( "%s: Tx timeout - resetting\n", | |
1051 | dev->name); | |
1052 | } | |
1053 | } | |
1054 | ||
1055 | if (db->wait_reset) { | |
1056 | ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt); | |
1057 | db->reset_count++; | |
1058 | uli526x_dynamic_reset(dev); | |
1059 | db->timer.expires = ULI526X_TIMER_WUT; | |
1060 | add_timer(&db->timer); | |
1061 | spin_unlock_irqrestore(&db->lock, flags); | |
1062 | return; | |
1063 | } | |
1064 | ||
1065 | /* Link status check, Dynamic media type change */ | |
1066 | if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0) | |
1067 | tmp_cr12 = 3; | |
1068 | ||
1069 | if ( !(tmp_cr12 & 0x3) && !db->link_failed ) { | |
1070 | /* Link Failed */ | |
1071 | ULI526X_DBUG(0, "Link Failed", tmp_cr12); | |
1072 | netif_carrier_off(dev); | |
e02fb7aa | 1073 | pr_info("%s NIC Link is Down\n",dev->name); |
4689ced9 PC |
1074 | db->link_failed = 1; |
1075 | ||
1076 | /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ | |
1077 | /* AUTO don't need */ | |
1078 | if ( !(db->media_mode & 0x8) ) | |
1079 | phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); | |
1080 | ||
1081 | /* AUTO mode, if INT phyxcer link failed, select EXT device */ | |
1082 | if (db->media_mode & ULI526X_AUTO) { | |
1083 | db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ | |
1084 | update_cr6(db->cr6_data, db->ioaddr); | |
1085 | } | |
1086 | } else | |
1087 | if ((tmp_cr12 & 0x3) && db->link_failed) { | |
1088 | ULI526X_DBUG(0, "Link link OK", tmp_cr12); | |
1089 | db->link_failed = 0; | |
1090 | ||
1091 | /* Auto Sense Speed */ | |
1092 | if ( (db->media_mode & ULI526X_AUTO) && | |
1093 | uli526x_sense_speed(db) ) | |
1094 | db->link_failed = 1; | |
1095 | uli526x_process_mode(db); | |
f3b197ac | 1096 | |
4689ced9 PC |
1097 | if(db->link_failed==0) |
1098 | { | |
1099 | if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) | |
1100 | { | |
1101 | TmpSpeed = 100; | |
1102 | } | |
1103 | if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) | |
1104 | { | |
e02fb7aa | 1105 | pr_info("%s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed); |
4689ced9 PC |
1106 | } |
1107 | else | |
1108 | { | |
e02fb7aa | 1109 | pr_info("%s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed); |
4689ced9 PC |
1110 | } |
1111 | netif_carrier_on(dev); | |
1112 | } | |
1113 | /* SHOW_MEDIA_TYPE(db->op_mode); */ | |
1114 | } | |
1115 | else if(!(tmp_cr12 & 0x3) && db->link_failed) | |
1116 | { | |
1117 | if(db->init==1) | |
1118 | { | |
e02fb7aa | 1119 | pr_info("%s NIC Link is Down\n",dev->name); |
4689ced9 PC |
1120 | netif_carrier_off(dev); |
1121 | } | |
1122 | } | |
1123 | db->init=0; | |
1124 | ||
1125 | /* Timer active again */ | |
1126 | db->timer.expires = ULI526X_TIMER_WUT; | |
1127 | add_timer(&db->timer); | |
1128 | spin_unlock_irqrestore(&db->lock, flags); | |
1129 | } | |
1130 | ||
1131 | ||
1132 | /* | |
4689ced9 PC |
1133 | * Stop ULI526X board |
1134 | * Free Tx/Rx allocated memory | |
b6aec32a | 1135 | * Init system variable |
4689ced9 PC |
1136 | */ |
1137 | ||
b6aec32a | 1138 | static void uli526x_reset_prepare(struct net_device *dev) |
4689ced9 PC |
1139 | { |
1140 | struct uli526x_board_info *db = netdev_priv(dev); | |
1141 | ||
4689ced9 PC |
1142 | /* Sopt MAC controller */ |
1143 | db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ | |
1144 | update_cr6(db->cr6_data, dev->base_addr); | |
1145 | outl(0, dev->base_addr + DCR7); /* Disable Interrupt */ | |
1146 | outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5); | |
1147 | ||
1148 | /* Disable upper layer interface */ | |
1149 | netif_stop_queue(dev); | |
1150 | ||
1151 | /* Free Rx Allocate buffer */ | |
1152 | uli526x_free_rxbuffer(db); | |
1153 | ||
1154 | /* system variable init */ | |
1155 | db->tx_packet_cnt = 0; | |
1156 | db->rx_avail_cnt = 0; | |
1157 | db->link_failed = 1; | |
1158 | db->init=1; | |
1159 | db->wait_reset = 0; | |
b6aec32a RW |
1160 | } |
1161 | ||
1162 | ||
1163 | /* | |
1164 | * Dynamic reset the ULI526X board | |
1165 | * Stop ULI526X board | |
1166 | * Free Tx/Rx allocated memory | |
1167 | * Reset ULI526X board | |
1168 | * Re-initialize ULI526X board | |
1169 | */ | |
1170 | ||
1171 | static void uli526x_dynamic_reset(struct net_device *dev) | |
1172 | { | |
1173 | ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0); | |
1174 | ||
1175 | uli526x_reset_prepare(dev); | |
4689ced9 | 1176 | |
945a7876 | 1177 | /* Re-initialize ULI526X board */ |
4689ced9 PC |
1178 | uli526x_init(dev); |
1179 | ||
1180 | /* Restart upper layer interface */ | |
1181 | netif_wake_queue(dev); | |
1182 | } | |
1183 | ||
1184 | ||
b6aec32a RW |
1185 | #ifdef CONFIG_PM |
1186 | ||
1187 | /* | |
1188 | * Suspend the interface. | |
1189 | */ | |
1190 | ||
1191 | static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state) | |
1192 | { | |
1193 | struct net_device *dev = pci_get_drvdata(pdev); | |
1194 | pci_power_t power_state; | |
1195 | int err; | |
1196 | ||
1197 | ULI526X_DBUG(0, "uli526x_suspend", 0); | |
1198 | ||
1199 | if (!netdev_priv(dev)) | |
1200 | return 0; | |
1201 | ||
1202 | pci_save_state(pdev); | |
1203 | ||
1204 | if (!netif_running(dev)) | |
1205 | return 0; | |
1206 | ||
1207 | netif_device_detach(dev); | |
1208 | uli526x_reset_prepare(dev); | |
1209 | ||
1210 | power_state = pci_choose_state(pdev, state); | |
1211 | pci_enable_wake(pdev, power_state, 0); | |
1212 | err = pci_set_power_state(pdev, power_state); | |
1213 | if (err) { | |
1214 | netif_device_attach(dev); | |
1215 | /* Re-initialize ULI526X board */ | |
1216 | uli526x_init(dev); | |
1217 | /* Restart upper layer interface */ | |
1218 | netif_wake_queue(dev); | |
1219 | } | |
1220 | ||
1221 | return err; | |
1222 | } | |
1223 | ||
1224 | /* | |
1225 | * Resume the interface. | |
1226 | */ | |
1227 | ||
1228 | static int uli526x_resume(struct pci_dev *pdev) | |
1229 | { | |
1230 | struct net_device *dev = pci_get_drvdata(pdev); | |
1231 | int err; | |
1232 | ||
1233 | ULI526X_DBUG(0, "uli526x_resume", 0); | |
1234 | ||
1235 | if (!netdev_priv(dev)) | |
1236 | return 0; | |
1237 | ||
1238 | pci_restore_state(pdev); | |
1239 | ||
1240 | if (!netif_running(dev)) | |
1241 | return 0; | |
1242 | ||
1243 | err = pci_set_power_state(pdev, PCI_D0); | |
1244 | if (err) { | |
e02fb7aa | 1245 | dev_warn(&dev->dev, "Could not put device into D0\n"); |
b6aec32a RW |
1246 | return err; |
1247 | } | |
1248 | ||
1249 | netif_device_attach(dev); | |
1250 | /* Re-initialize ULI526X board */ | |
1251 | uli526x_init(dev); | |
1252 | /* Restart upper layer interface */ | |
1253 | netif_wake_queue(dev); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
1258 | #else /* !CONFIG_PM */ | |
1259 | ||
1260 | #define uli526x_suspend NULL | |
1261 | #define uli526x_resume NULL | |
1262 | ||
1263 | #endif /* !CONFIG_PM */ | |
1264 | ||
1265 | ||
4689ced9 PC |
1266 | /* |
1267 | * free all allocated rx buffer | |
1268 | */ | |
1269 | ||
1270 | static void uli526x_free_rxbuffer(struct uli526x_board_info * db) | |
1271 | { | |
1272 | ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0); | |
1273 | ||
1274 | /* free allocated rx buffer */ | |
1275 | while (db->rx_avail_cnt) { | |
1276 | dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr); | |
1277 | db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc; | |
1278 | db->rx_avail_cnt--; | |
1279 | } | |
1280 | } | |
1281 | ||
1282 | ||
1283 | /* | |
1284 | * Reuse the SK buffer | |
1285 | */ | |
1286 | ||
1287 | static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb) | |
1288 | { | |
1289 | struct rx_desc *rxptr = db->rx_insert_ptr; | |
1290 | ||
1291 | if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { | |
1292 | rxptr->rx_skb_ptr = skb; | |
27a884dc ACM |
1293 | rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev, |
1294 | skb_tail_pointer(skb), | |
1295 | RX_ALLOC_SIZE, | |
1296 | PCI_DMA_FROMDEVICE)); | |
4689ced9 PC |
1297 | wmb(); |
1298 | rxptr->rdes0 = cpu_to_le32(0x80000000); | |
1299 | db->rx_avail_cnt++; | |
1300 | db->rx_insert_ptr = rxptr->next_rx_desc; | |
1301 | } else | |
1302 | ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt); | |
1303 | } | |
1304 | ||
1305 | ||
1306 | /* | |
1307 | * Initialize transmit/Receive descriptor | |
1308 | * Using Chain structure, and allocate Tx/Rx buffer | |
1309 | */ | |
1310 | ||
1311 | static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr) | |
1312 | { | |
1313 | struct tx_desc *tmp_tx; | |
1314 | struct rx_desc *tmp_rx; | |
1315 | unsigned char *tmp_buf; | |
1316 | dma_addr_t tmp_tx_dma, tmp_rx_dma; | |
1317 | dma_addr_t tmp_buf_dma; | |
1318 | int i; | |
1319 | ||
1320 | ULI526X_DBUG(0, "uli526x_descriptor_init()", 0); | |
1321 | ||
1322 | /* tx descriptor start pointer */ | |
1323 | db->tx_insert_ptr = db->first_tx_desc; | |
1324 | db->tx_remove_ptr = db->first_tx_desc; | |
1325 | outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ | |
1326 | ||
1327 | /* rx descriptor start pointer */ | |
1328 | db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT; | |
1329 | db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT; | |
1330 | db->rx_insert_ptr = db->first_rx_desc; | |
1331 | db->rx_ready_ptr = db->first_rx_desc; | |
1332 | outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ | |
1333 | ||
1334 | /* Init Transmit chain */ | |
1335 | tmp_buf = db->buf_pool_start; | |
1336 | tmp_buf_dma = db->buf_pool_dma_start; | |
1337 | tmp_tx_dma = db->first_tx_desc_dma; | |
1338 | for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) { | |
1339 | tmp_tx->tx_buf_ptr = tmp_buf; | |
1340 | tmp_tx->tdes0 = cpu_to_le32(0); | |
1341 | tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ | |
1342 | tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma); | |
1343 | tmp_tx_dma += sizeof(struct tx_desc); | |
1344 | tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma); | |
1345 | tmp_tx->next_tx_desc = tmp_tx + 1; | |
1346 | tmp_buf = tmp_buf + TX_BUF_ALLOC; | |
1347 | tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC; | |
1348 | } | |
1349 | (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); | |
1350 | tmp_tx->next_tx_desc = db->first_tx_desc; | |
1351 | ||
1352 | /* Init Receive descriptor chain */ | |
1353 | tmp_rx_dma=db->first_rx_desc_dma; | |
1354 | for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) { | |
1355 | tmp_rx->rdes0 = cpu_to_le32(0); | |
1356 | tmp_rx->rdes1 = cpu_to_le32(0x01000600); | |
1357 | tmp_rx_dma += sizeof(struct rx_desc); | |
1358 | tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma); | |
1359 | tmp_rx->next_rx_desc = tmp_rx + 1; | |
1360 | } | |
1361 | (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); | |
1362 | tmp_rx->next_rx_desc = db->first_rx_desc; | |
1363 | ||
1364 | /* pre-allocate Rx buffer */ | |
1365 | allocate_rx_buffer(db); | |
1366 | } | |
1367 | ||
1368 | ||
1369 | /* | |
1370 | * Update CR6 value | |
945a7876 | 1371 | * Firstly stop ULI526X, then written value and start |
4689ced9 PC |
1372 | */ |
1373 | ||
1374 | static void update_cr6(u32 cr6_data, unsigned long ioaddr) | |
1375 | { | |
1376 | ||
1377 | outl(cr6_data, ioaddr + DCR6); | |
1378 | udelay(5); | |
1379 | } | |
1380 | ||
1381 | ||
1382 | /* | |
1383 | * Send a setup frame for M5261/M5263 | |
945a7876 | 1384 | * This setup frame initialize ULI526X address filter mode |
4689ced9 PC |
1385 | */ |
1386 | ||
e284e5c6 AV |
1387 | #ifdef __BIG_ENDIAN |
1388 | #define FLT_SHIFT 16 | |
1389 | #else | |
1390 | #define FLT_SHIFT 0 | |
1391 | #endif | |
1392 | ||
945a7876 | 1393 | static void send_filter_frame(struct net_device *dev, int mc_cnt) |
4689ced9 PC |
1394 | { |
1395 | struct uli526x_board_info *db = netdev_priv(dev); | |
22bedad3 | 1396 | struct netdev_hw_addr *ha; |
4689ced9 PC |
1397 | struct tx_desc *txptr; |
1398 | u16 * addrptr; | |
1399 | u32 * suptr; | |
1400 | int i; | |
1401 | ||
1402 | ULI526X_DBUG(0, "send_filter_frame()", 0); | |
1403 | ||
1404 | txptr = db->tx_insert_ptr; | |
1405 | suptr = (u32 *) txptr->tx_buf_ptr; | |
1406 | ||
1407 | /* Node address */ | |
1408 | addrptr = (u16 *) dev->dev_addr; | |
e284e5c6 AV |
1409 | *suptr++ = addrptr[0] << FLT_SHIFT; |
1410 | *suptr++ = addrptr[1] << FLT_SHIFT; | |
1411 | *suptr++ = addrptr[2] << FLT_SHIFT; | |
4689ced9 PC |
1412 | |
1413 | /* broadcast address */ | |
e284e5c6 AV |
1414 | *suptr++ = 0xffff << FLT_SHIFT; |
1415 | *suptr++ = 0xffff << FLT_SHIFT; | |
1416 | *suptr++ = 0xffff << FLT_SHIFT; | |
4689ced9 PC |
1417 | |
1418 | /* fit the multicast address */ | |
22bedad3 JP |
1419 | netdev_for_each_mc_addr(ha, dev) { |
1420 | addrptr = (u16 *) ha->addr; | |
e284e5c6 AV |
1421 | *suptr++ = addrptr[0] << FLT_SHIFT; |
1422 | *suptr++ = addrptr[1] << FLT_SHIFT; | |
1423 | *suptr++ = addrptr[2] << FLT_SHIFT; | |
4689ced9 PC |
1424 | } |
1425 | ||
4302b67e | 1426 | for (i = netdev_mc_count(dev); i < 14; i++) { |
e284e5c6 AV |
1427 | *suptr++ = 0xffff << FLT_SHIFT; |
1428 | *suptr++ = 0xffff << FLT_SHIFT; | |
1429 | *suptr++ = 0xffff << FLT_SHIFT; | |
4689ced9 PC |
1430 | } |
1431 | ||
1432 | /* prepare the setup frame */ | |
1433 | db->tx_insert_ptr = txptr->next_tx_desc; | |
1434 | txptr->tdes1 = cpu_to_le32(0x890000c0); | |
1435 | ||
1436 | /* Resource Check and Send the setup packet */ | |
1437 | if (db->tx_packet_cnt < TX_DESC_CNT) { | |
1438 | /* Resource Empty */ | |
1439 | db->tx_packet_cnt++; | |
1440 | txptr->tdes0 = cpu_to_le32(0x80000000); | |
1441 | update_cr6(db->cr6_data | 0x2000, dev->base_addr); | |
1442 | outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ | |
1443 | update_cr6(db->cr6_data, dev->base_addr); | |
1444 | dev->trans_start = jiffies; | |
1445 | } else | |
e02fb7aa | 1446 | pr_err("No Tx resource - Send_filter_frame!\n"); |
4689ced9 PC |
1447 | } |
1448 | ||
1449 | ||
1450 | /* | |
1451 | * Allocate rx buffer, | |
1452 | * As possible as allocate maxiumn Rx buffer | |
1453 | */ | |
1454 | ||
1455 | static void allocate_rx_buffer(struct uli526x_board_info *db) | |
1456 | { | |
1457 | struct rx_desc *rxptr; | |
1458 | struct sk_buff *skb; | |
1459 | ||
1460 | rxptr = db->rx_insert_ptr; | |
1461 | ||
1462 | while(db->rx_avail_cnt < RX_DESC_CNT) { | |
1463 | if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL ) | |
1464 | break; | |
1465 | rxptr->rx_skb_ptr = skb; /* FIXME (?) */ | |
27a884dc ACM |
1466 | rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev, |
1467 | skb_tail_pointer(skb), | |
1468 | RX_ALLOC_SIZE, | |
1469 | PCI_DMA_FROMDEVICE)); | |
4689ced9 PC |
1470 | wmb(); |
1471 | rxptr->rdes0 = cpu_to_le32(0x80000000); | |
1472 | rxptr = rxptr->next_rx_desc; | |
1473 | db->rx_avail_cnt++; | |
1474 | } | |
1475 | ||
1476 | db->rx_insert_ptr = rxptr; | |
1477 | } | |
1478 | ||
1479 | ||
1480 | /* | |
1481 | * Read one word data from the serial ROM | |
1482 | */ | |
1483 | ||
1484 | static u16 read_srom_word(long ioaddr, int offset) | |
1485 | { | |
1486 | int i; | |
1487 | u16 srom_data = 0; | |
1488 | long cr9_ioaddr = ioaddr + DCR9; | |
1489 | ||
1490 | outl(CR9_SROM_READ, cr9_ioaddr); | |
1491 | outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); | |
1492 | ||
1493 | /* Send the Read Command 110b */ | |
1494 | SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); | |
1495 | SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); | |
1496 | SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr); | |
1497 | ||
1498 | /* Send the offset */ | |
1499 | for (i = 5; i >= 0; i--) { | |
1500 | srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; | |
1501 | SROM_CLK_WRITE(srom_data, cr9_ioaddr); | |
1502 | } | |
1503 | ||
1504 | outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); | |
1505 | ||
1506 | for (i = 16; i > 0; i--) { | |
1507 | outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); | |
1508 | udelay(5); | |
1509 | srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0); | |
1510 | outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); | |
1511 | udelay(5); | |
1512 | } | |
1513 | ||
1514 | outl(CR9_SROM_READ, cr9_ioaddr); | |
1515 | return srom_data; | |
1516 | } | |
1517 | ||
1518 | ||
1519 | /* | |
1520 | * Auto sense the media mode | |
1521 | */ | |
1522 | ||
1523 | static u8 uli526x_sense_speed(struct uli526x_board_info * db) | |
1524 | { | |
1525 | u8 ErrFlag = 0; | |
1526 | u16 phy_mode; | |
1527 | ||
1528 | phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); | |
1529 | phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); | |
1530 | ||
1531 | if ( (phy_mode & 0x24) == 0x24 ) { | |
f3b197ac | 1532 | |
4689ced9 PC |
1533 | phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7); |
1534 | if(phy_mode&0x8000) | |
1535 | phy_mode = 0x8000; | |
1536 | else if(phy_mode&0x4000) | |
1537 | phy_mode = 0x4000; | |
1538 | else if(phy_mode&0x2000) | |
1539 | phy_mode = 0x2000; | |
1540 | else | |
1541 | phy_mode = 0x1000; | |
f3b197ac | 1542 | |
4689ced9 PC |
1543 | /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */ |
1544 | switch (phy_mode) { | |
1545 | case 0x1000: db->op_mode = ULI526X_10MHF; break; | |
1546 | case 0x2000: db->op_mode = ULI526X_10MFD; break; | |
1547 | case 0x4000: db->op_mode = ULI526X_100MHF; break; | |
1548 | case 0x8000: db->op_mode = ULI526X_100MFD; break; | |
1549 | default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break; | |
1550 | } | |
1551 | } else { | |
1552 | db->op_mode = ULI526X_10MHF; | |
1553 | ULI526X_DBUG(0, "Link Failed :", phy_mode); | |
1554 | ErrFlag = 1; | |
1555 | } | |
1556 | ||
1557 | return ErrFlag; | |
1558 | } | |
1559 | ||
1560 | ||
1561 | /* | |
1562 | * Set 10/100 phyxcer capability | |
1563 | * AUTO mode : phyxcer register4 is NIC capability | |
1564 | * Force mode: phyxcer register4 is the force media | |
1565 | */ | |
1566 | ||
1567 | static void uli526x_set_phyxcer(struct uli526x_board_info *db) | |
1568 | { | |
1569 | u16 phy_reg; | |
f3b197ac | 1570 | |
4689ced9 PC |
1571 | /* Phyxcer capability setting */ |
1572 | phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; | |
1573 | ||
1574 | if (db->media_mode & ULI526X_AUTO) { | |
1575 | /* AUTO Mode */ | |
1576 | phy_reg |= db->PHY_reg4; | |
1577 | } else { | |
1578 | /* Force Mode */ | |
1579 | switch(db->media_mode) { | |
1580 | case ULI526X_10MHF: phy_reg |= 0x20; break; | |
1581 | case ULI526X_10MFD: phy_reg |= 0x40; break; | |
1582 | case ULI526X_100MHF: phy_reg |= 0x80; break; | |
1583 | case ULI526X_100MFD: phy_reg |= 0x100; break; | |
1584 | } | |
f3b197ac | 1585 | |
4689ced9 PC |
1586 | } |
1587 | ||
1588 | /* Write new capability to Phyxcer Reg4 */ | |
1589 | if ( !(phy_reg & 0x01e0)) { | |
1590 | phy_reg|=db->PHY_reg4; | |
1591 | db->media_mode|=ULI526X_AUTO; | |
1592 | } | |
1593 | phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); | |
1594 | ||
1595 | /* Restart Auto-Negotiation */ | |
1596 | phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); | |
1597 | udelay(50); | |
1598 | } | |
1599 | ||
1600 | ||
1601 | /* | |
1602 | * Process op-mode | |
1603 | AUTO mode : PHY controller in Auto-negotiation Mode | |
1604 | * Force mode: PHY controller in force mode with HUB | |
1605 | * N-way force capability with SWITCH | |
1606 | */ | |
1607 | ||
1608 | static void uli526x_process_mode(struct uli526x_board_info *db) | |
1609 | { | |
1610 | u16 phy_reg; | |
1611 | ||
1612 | /* Full Duplex Mode Check */ | |
1613 | if (db->op_mode & 0x4) | |
1614 | db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */ | |
1615 | else | |
1616 | db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */ | |
1617 | ||
1618 | update_cr6(db->cr6_data, db->ioaddr); | |
1619 | ||
1620 | /* 10/100M phyxcer force mode need */ | |
1621 | if ( !(db->media_mode & 0x8)) { | |
1622 | /* Forece Mode */ | |
1623 | phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id); | |
1624 | if ( !(phy_reg & 0x1) ) { | |
1625 | /* parter without N-Way capability */ | |
1626 | phy_reg = 0x0; | |
1627 | switch(db->op_mode) { | |
1628 | case ULI526X_10MHF: phy_reg = 0x0; break; | |
1629 | case ULI526X_10MFD: phy_reg = 0x100; break; | |
1630 | case ULI526X_100MHF: phy_reg = 0x2000; break; | |
1631 | case ULI526X_100MFD: phy_reg = 0x2100; break; | |
1632 | } | |
1633 | phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); | |
4689ced9 PC |
1634 | } |
1635 | } | |
1636 | } | |
1637 | ||
1638 | ||
1639 | /* | |
1640 | * Write a word to Phy register | |
1641 | */ | |
1642 | ||
1643 | static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id) | |
1644 | { | |
1645 | u16 i; | |
1646 | unsigned long ioaddr; | |
1647 | ||
1648 | if(chip_id == PCI_ULI5263_ID) | |
1649 | { | |
1650 | phy_writeby_cr10(iobase, phy_addr, offset, phy_data); | |
1651 | return; | |
1652 | } | |
1653 | /* M5261/M5263 Chip */ | |
1654 | ioaddr = iobase + DCR9; | |
1655 | ||
1656 | /* Send 33 synchronization clock to Phy controller */ | |
1657 | for (i = 0; i < 35; i++) | |
1658 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1659 | ||
1660 | /* Send start command(01) to Phy */ | |
1661 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1662 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1663 | ||
1664 | /* Send write command(01) to Phy */ | |
1665 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1666 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1667 | ||
1668 | /* Send Phy address */ | |
1669 | for (i = 0x10; i > 0; i = i >> 1) | |
1670 | phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
1671 | ||
1672 | /* Send register address */ | |
1673 | for (i = 0x10; i > 0; i = i >> 1) | |
1674 | phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
1675 | ||
1676 | /* written trasnition */ | |
1677 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1678 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1679 | ||
1680 | /* Write a word data to PHY controller */ | |
1681 | for ( i = 0x8000; i > 0; i >>= 1) | |
1682 | phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
f3b197ac | 1683 | |
4689ced9 PC |
1684 | } |
1685 | ||
1686 | ||
1687 | /* | |
1688 | * Read a word data from phy register | |
1689 | */ | |
1690 | ||
1691 | static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id) | |
1692 | { | |
1693 | int i; | |
1694 | u16 phy_data; | |
1695 | unsigned long ioaddr; | |
1696 | ||
1697 | if(chip_id == PCI_ULI5263_ID) | |
1698 | return phy_readby_cr10(iobase, phy_addr, offset); | |
1699 | /* M5261/M5263 Chip */ | |
1700 | ioaddr = iobase + DCR9; | |
f3b197ac | 1701 | |
4689ced9 PC |
1702 | /* Send 33 synchronization clock to Phy controller */ |
1703 | for (i = 0; i < 35; i++) | |
1704 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1705 | ||
1706 | /* Send start command(01) to Phy */ | |
1707 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1708 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1709 | ||
1710 | /* Send read command(10) to Phy */ | |
1711 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | |
1712 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | |
1713 | ||
1714 | /* Send Phy address */ | |
1715 | for (i = 0x10; i > 0; i = i >> 1) | |
1716 | phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
1717 | ||
1718 | /* Send register address */ | |
1719 | for (i = 0x10; i > 0; i = i >> 1) | |
1720 | phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | |
1721 | ||
1722 | /* Skip transition state */ | |
1723 | phy_read_1bit(ioaddr, chip_id); | |
1724 | ||
1725 | /* read 16bit data */ | |
1726 | for (phy_data = 0, i = 0; i < 16; i++) { | |
1727 | phy_data <<= 1; | |
1728 | phy_data |= phy_read_1bit(ioaddr, chip_id); | |
1729 | } | |
1730 | ||
1731 | return phy_data; | |
1732 | } | |
1733 | ||
1734 | static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset) | |
1735 | { | |
1736 | unsigned long ioaddr,cr10_value; | |
f3b197ac | 1737 | |
4689ced9 PC |
1738 | ioaddr = iobase + DCR10; |
1739 | cr10_value = phy_addr; | |
1740 | cr10_value = (cr10_value<<5) + offset; | |
1741 | cr10_value = (cr10_value<<16) + 0x08000000; | |
1742 | outl(cr10_value,ioaddr); | |
1743 | udelay(1); | |
1744 | while(1) | |
1745 | { | |
1746 | cr10_value = inl(ioaddr); | |
1747 | if(cr10_value&0x10000000) | |
1748 | break; | |
1749 | } | |
1750 | return (cr10_value&0x0ffff); | |
1751 | } | |
1752 | ||
1753 | static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data) | |
1754 | { | |
1755 | unsigned long ioaddr,cr10_value; | |
f3b197ac | 1756 | |
4689ced9 PC |
1757 | ioaddr = iobase + DCR10; |
1758 | cr10_value = phy_addr; | |
1759 | cr10_value = (cr10_value<<5) + offset; | |
1760 | cr10_value = (cr10_value<<16) + 0x04000000 + phy_data; | |
1761 | outl(cr10_value,ioaddr); | |
1762 | udelay(1); | |
1763 | } | |
1764 | /* | |
1765 | * Write one bit data to Phy Controller | |
1766 | */ | |
1767 | ||
1768 | static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id) | |
1769 | { | |
1770 | outl(phy_data , ioaddr); /* MII Clock Low */ | |
1771 | udelay(1); | |
1772 | outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ | |
1773 | udelay(1); | |
1774 | outl(phy_data , ioaddr); /* MII Clock Low */ | |
1775 | udelay(1); | |
1776 | } | |
1777 | ||
1778 | ||
1779 | /* | |
1780 | * Read one bit phy data from PHY controller | |
1781 | */ | |
1782 | ||
1783 | static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id) | |
1784 | { | |
1785 | u16 phy_data; | |
f3b197ac | 1786 | |
4689ced9 PC |
1787 | outl(0x50000 , ioaddr); |
1788 | udelay(1); | |
1789 | phy_data = ( inl(ioaddr) >> 19 ) & 0x1; | |
1790 | outl(0x40000 , ioaddr); | |
1791 | udelay(1); | |
1792 | ||
1793 | return phy_data; | |
1794 | } | |
1795 | ||
1796 | ||
a3aa1884 | 1797 | static DEFINE_PCI_DEVICE_TABLE(uli526x_pci_tbl) = { |
4689ced9 PC |
1798 | { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID }, |
1799 | { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID }, | |
1800 | { 0, } | |
1801 | }; | |
1802 | MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl); | |
1803 | ||
1804 | ||
1805 | static struct pci_driver uli526x_driver = { | |
1806 | .name = "uli526x", | |
1807 | .id_table = uli526x_pci_tbl, | |
1808 | .probe = uli526x_init_one, | |
1809 | .remove = __devexit_p(uli526x_remove_one), | |
b6aec32a RW |
1810 | .suspend = uli526x_suspend, |
1811 | .resume = uli526x_resume, | |
4689ced9 PC |
1812 | }; |
1813 | ||
1814 | MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw"); | |
1815 | MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver"); | |
1816 | MODULE_LICENSE("GPL"); | |
1817 | ||
c213460f ES |
1818 | module_param(debug, int, 0644); |
1819 | module_param(mode, int, 0); | |
1820 | module_param(cr6set, int, 0); | |
4689ced9 PC |
1821 | MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)"); |
1822 | MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA"); | |
1823 | ||
1824 | /* Description: | |
1825 | * when user used insmod to add module, system invoked init_module() | |
945a7876 | 1826 | * to register the services. |
4689ced9 PC |
1827 | */ |
1828 | ||
1829 | static int __init uli526x_init_module(void) | |
1830 | { | |
4689ced9 PC |
1831 | |
1832 | printk(version); | |
1833 | printed_version = 1; | |
1834 | ||
1835 | ULI526X_DBUG(0, "init_module() ", debug); | |
1836 | ||
1837 | if (debug) | |
1838 | uli526x_debug = debug; /* set debug flag */ | |
1839 | if (cr6set) | |
1840 | uli526x_cr6_user_set = cr6set; | |
1841 | ||
e1c3e501 | 1842 | switch (mode) { |
4689ced9 PC |
1843 | case ULI526X_10MHF: |
1844 | case ULI526X_100MHF: | |
1845 | case ULI526X_10MFD: | |
1846 | case ULI526X_100MFD: | |
1847 | uli526x_media_mode = mode; | |
1848 | break; | |
e1c3e501 HK |
1849 | default: |
1850 | uli526x_media_mode = ULI526X_AUTO; | |
4689ced9 PC |
1851 | break; |
1852 | } | |
1853 | ||
e1c3e501 | 1854 | return pci_register_driver(&uli526x_driver); |
4689ced9 PC |
1855 | } |
1856 | ||
1857 | ||
1858 | /* | |
1859 | * Description: | |
1860 | * when user used rmmod to delete module, system invoked clean_module() | |
1861 | * to un-register all registered services. | |
1862 | */ | |
1863 | ||
1864 | static void __exit uli526x_cleanup_module(void) | |
1865 | { | |
1866 | ULI526X_DBUG(0, "uli526x_clean_module() ", debug); | |
1867 | pci_unregister_driver(&uli526x_driver); | |
1868 | } | |
1869 | ||
1870 | module_init(uli526x_init_module); | |
1871 | module_exit(uli526x_cleanup_module); |