]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* winbond-840.c: A Linux PCI network adapter device driver. */ |
2 | /* | |
3 | Written 1998-2001 by Donald Becker. | |
4 | ||
5 | This software may be used and distributed according to the terms of | |
6 | the GNU General Public License (GPL), incorporated herein by reference. | |
7 | Drivers based on or derived from this code fall under the GPL and must | |
8 | retain the authorship, copyright and license notice. This file is not | |
9 | a complete program and may only be used when the entire operating | |
10 | system is licensed under the GPL. | |
11 | ||
12 | The author may be reached as becker@scyld.com, or C/O | |
13 | Scyld Computing Corporation | |
14 | 410 Severn Ave., Suite 210 | |
15 | Annapolis MD 21403 | |
16 | ||
17 | Support and updates available at | |
18 | http://www.scyld.com/network/drivers.html | |
19 | ||
20 | Do not remove the copyright information. | |
21 | Do not change the version information unless an improvement has been made. | |
22 | Merely removing my name, as Compex has done in the past, does not count | |
23 | as an improvement. | |
24 | ||
25 | Changelog: | |
26 | * ported to 2.4 | |
27 | ??? | |
28 | * spin lock update, memory barriers, new style dma mappings | |
29 | limit each tx buffer to < 1024 bytes | |
30 | remove DescIntr from Rx descriptors (that's an Tx flag) | |
31 | remove next pointer from Tx descriptors | |
32 | synchronize tx_q_bytes | |
33 | software reset in tx_timeout | |
34 | Copyright (C) 2000 Manfred Spraul | |
35 | * further cleanups | |
36 | power management. | |
37 | support for big endian descriptors | |
38 | Copyright (C) 2001 Manfred Spraul | |
39 | * ethtool support (jgarzik) | |
40 | * Replace some MII-related magic numbers with constants (jgarzik) | |
f3b197ac | 41 | |
1da177e4 LT |
42 | TODO: |
43 | * enable pci_power_off | |
44 | * Wake-On-LAN | |
45 | */ | |
f3b197ac | 46 | |
1da177e4 | 47 | #define DRV_NAME "winbond-840" |
d5b20697 AG |
48 | #define DRV_VERSION "1.01-e" |
49 | #define DRV_RELDATE "Sep-11-2006" | |
1da177e4 LT |
50 | |
51 | ||
52 | /* Automatically extracted configuration info: | |
53 | probe-func: winbond840_probe | |
54 | config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840 | |
55 | ||
56 | c-help-name: Winbond W89c840 PCI Ethernet support | |
57 | c-help-symbol: CONFIG_WINBOND_840 | |
58 | c-help: This driver is for the Winbond W89c840 chip. It also works with | |
59 | c-help: the TX9882 chip on the Compex RL100-ATX board. | |
f3b197ac | 60 | c-help: More specific information and updates are available from |
1da177e4 LT |
61 | c-help: http://www.scyld.com/network/drivers.html |
62 | */ | |
63 | ||
64 | /* The user-configurable values. | |
65 | These may be modified when a driver module is loaded.*/ | |
66 | ||
67 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
68 | static int max_interrupt_work = 20; | |
69 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
70 | The '840 uses a 64 element hash table based on the Ethernet CRC. */ | |
71 | static int multicast_filter_limit = 32; | |
72 | ||
73 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
74 | Setting to > 1518 effectively disables this feature. */ | |
75 | static int rx_copybreak; | |
76 | ||
77 | /* Used to pass the media type, etc. | |
78 | Both 'options[]' and 'full_duplex[]' should exist for driver | |
79 | interoperability. | |
80 | The media type is usually passed in 'options[]'. | |
81 | */ | |
82 | #define MAX_UNITS 8 /* More are supported, limit only on options */ | |
83 | static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
84 | static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
85 | ||
86 | /* Operational parameters that are set at compile time. */ | |
87 | ||
88 | /* Keep the ring sizes a power of two for compile efficiency. | |
89 | The compiler will convert <unsigned>'%'<2^N> into a bit mask. | |
90 | Making the Tx ring too large decreases the effectiveness of channel | |
91 | bonding and packet priority. | |
92 | There are no ill effects from too-large receive rings. */ | |
1da177e4 LT |
93 | #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ |
94 | #define TX_QUEUE_LEN_RESTART 5 | |
1da177e4 LT |
95 | |
96 | #define TX_BUFLIMIT (1024-128) | |
97 | ||
98 | /* The presumed FIFO size for working around the Tx-FIFO-overflow bug. | |
99 | To avoid overflowing we don't queue again until we have room for a | |
100 | full-size packet. | |
101 | */ | |
102 | #define TX_FIFO_SIZE (2048) | |
103 | #define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16) | |
104 | ||
105 | ||
106 | /* Operational parameters that usually are not changed. */ | |
107 | /* Time in jiffies before concluding the transmitter is hung. */ | |
108 | #define TX_TIMEOUT (2*HZ) | |
109 | ||
1da177e4 LT |
110 | /* Include files, designed to support most kernel versions 2.0.0 and later. */ |
111 | #include <linux/module.h> | |
112 | #include <linux/kernel.h> | |
113 | #include <linux/string.h> | |
114 | #include <linux/timer.h> | |
115 | #include <linux/errno.h> | |
116 | #include <linux/ioport.h> | |
1da177e4 LT |
117 | #include <linux/interrupt.h> |
118 | #include <linux/pci.h> | |
10a87fcf | 119 | #include <linux/dma-mapping.h> |
1da177e4 LT |
120 | #include <linux/netdevice.h> |
121 | #include <linux/etherdevice.h> | |
122 | #include <linux/skbuff.h> | |
123 | #include <linux/init.h> | |
124 | #include <linux/delay.h> | |
125 | #include <linux/ethtool.h> | |
126 | #include <linux/mii.h> | |
127 | #include <linux/rtnetlink.h> | |
128 | #include <linux/crc32.h> | |
129 | #include <linux/bitops.h> | |
130 | #include <asm/uaccess.h> | |
131 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
132 | #include <asm/io.h> | |
133 | #include <asm/irq.h> | |
134 | ||
42eab567 GG |
135 | #include "tulip.h" |
136 | ||
48dd59e3 JG |
137 | #undef PKT_BUF_SZ /* tulip.h also defines this */ |
138 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
139 | ||
1da177e4 | 140 | /* These identify the driver base version and may not be removed. */ |
03f54b3d SH |
141 | static const char version[] __initconst = |
142 | KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) " | |
143 | DRV_RELDATE " Donald Becker <becker@scyld.com>\n" | |
ad361c98 | 144 | " http://www.scyld.com/network/drivers.html\n"; |
1da177e4 LT |
145 | |
146 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
147 | MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | MODULE_VERSION(DRV_VERSION); | |
150 | ||
151 | module_param(max_interrupt_work, int, 0); | |
152 | module_param(debug, int, 0); | |
153 | module_param(rx_copybreak, int, 0); | |
154 | module_param(multicast_filter_limit, int, 0); | |
155 | module_param_array(options, int, NULL, 0); | |
156 | module_param_array(full_duplex, int, NULL, 0); | |
157 | MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt"); | |
158 | MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)"); | |
159 | MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames"); | |
160 | MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses"); | |
161 | MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex"); | |
162 | MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)"); | |
163 | ||
164 | /* | |
165 | Theory of Operation | |
166 | ||
167 | I. Board Compatibility | |
168 | ||
169 | This driver is for the Winbond w89c840 chip. | |
170 | ||
171 | II. Board-specific settings | |
172 | ||
173 | None. | |
174 | ||
175 | III. Driver operation | |
176 | ||
177 | This chip is very similar to the Digital 21*4* "Tulip" family. The first | |
178 | twelve registers and the descriptor format are nearly identical. Read a | |
179 | Tulip manual for operational details. | |
180 | ||
181 | A significant difference is that the multicast filter and station address are | |
182 | stored in registers rather than loaded through a pseudo-transmit packet. | |
183 | ||
184 | Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a | |
185 | full-sized packet we must use both data buffers in a descriptor. Thus the | |
186 | driver uses ring mode where descriptors are implicitly sequential in memory, | |
187 | rather than using the second descriptor address as a chain pointer to | |
188 | subsequent descriptors. | |
189 | ||
190 | IV. Notes | |
191 | ||
192 | If you are going to almost clone a Tulip, why not go all the way and avoid | |
193 | the need for a new driver? | |
194 | ||
195 | IVb. References | |
196 | ||
197 | http://www.scyld.com/expert/100mbps.html | |
198 | http://www.scyld.com/expert/NWay.html | |
199 | http://www.winbond.com.tw/ | |
200 | ||
201 | IVc. Errata | |
202 | ||
203 | A horrible bug exists in the transmit FIFO. Apparently the chip doesn't | |
204 | correctly detect a full FIFO, and queuing more than 2048 bytes may result in | |
205 | silent data corruption. | |
206 | ||
207 | Test with 'ping -s 10000' on a fast computer. | |
208 | ||
209 | */ | |
210 | ||
f3b197ac | 211 | |
1da177e4 LT |
212 | |
213 | /* | |
214 | PCI probe table. | |
215 | */ | |
1da177e4 | 216 | enum chip_capability_flags { |
1f1bd5fc JG |
217 | CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8, |
218 | }; | |
219 | ||
a3aa1884 | 220 | static DEFINE_PCI_DEVICE_TABLE(w840_pci_tbl) = { |
1da177e4 LT |
221 | { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 }, |
222 | { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, | |
223 | { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, | |
1f1bd5fc | 224 | { } |
1da177e4 LT |
225 | }; |
226 | MODULE_DEVICE_TABLE(pci, w840_pci_tbl); | |
227 | ||
c3d8e682 JG |
228 | enum { |
229 | netdev_res_size = 128, /* size of PCI BAR resource */ | |
230 | }; | |
231 | ||
1da177e4 LT |
232 | struct pci_id_info { |
233 | const char *name; | |
c3d8e682 | 234 | int drv_flags; /* Driver use, intended as capability flags. */ |
1da177e4 | 235 | }; |
c3d8e682 JG |
236 | |
237 | static const struct pci_id_info pci_id_tbl[] __devinitdata = { | |
238 | { /* Sometime a Level-One switch card. */ | |
239 | "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII}, | |
240 | { "Winbond W89c840", CanHaveMII | HasBrokenTx}, | |
241 | { "Compex RL100-ATX", CanHaveMII | HasBrokenTx}, | |
242 | { } /* terminate list. */ | |
1da177e4 LT |
243 | }; |
244 | ||
245 | /* This driver was written to use PCI memory space, however some x86 systems | |
42eab567 GG |
246 | work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config |
247 | */ | |
1da177e4 LT |
248 | |
249 | /* Offsets to the Command and Status Registers, "CSRs". | |
250 | While similar to the Tulip, these registers are longword aligned. | |
251 | Note: It's not useful to define symbolic names for every register bit in | |
252 | the device. The name can only partially document the semantics and make | |
253 | the driver longer and more difficult to read. | |
254 | */ | |
255 | enum w840_offsets { | |
256 | PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08, | |
257 | RxRingPtr=0x0C, TxRingPtr=0x10, | |
258 | IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C, | |
259 | RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C, | |
260 | CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */ | |
261 | MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40, | |
262 | CurTxDescAddr=0x4C, CurTxBufAddr=0x50, | |
263 | }; | |
264 | ||
1da177e4 LT |
265 | /* Bits in the NetworkConfig register. */ |
266 | enum rx_mode_bits { | |
42eab567 GG |
267 | AcceptErr=0x80, |
268 | RxAcceptBroadcast=0x20, AcceptMulticast=0x10, | |
269 | RxAcceptAllPhys=0x08, AcceptMyPhys=0x02, | |
1da177e4 LT |
270 | }; |
271 | ||
272 | enum mii_reg_bits { | |
273 | MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000, | |
274 | MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000, | |
275 | }; | |
276 | ||
277 | /* The Tulip Rx and Tx buffer descriptors. */ | |
278 | struct w840_rx_desc { | |
279 | s32 status; | |
280 | s32 length; | |
281 | u32 buffer1; | |
282 | u32 buffer2; | |
283 | }; | |
284 | ||
285 | struct w840_tx_desc { | |
286 | s32 status; | |
287 | s32 length; | |
288 | u32 buffer1, buffer2; | |
289 | }; | |
290 | ||
1da177e4 LT |
291 | #define MII_CNT 1 /* winbond only supports one MII */ |
292 | struct netdev_private { | |
293 | struct w840_rx_desc *rx_ring; | |
294 | dma_addr_t rx_addr[RX_RING_SIZE]; | |
295 | struct w840_tx_desc *tx_ring; | |
296 | dma_addr_t tx_addr[TX_RING_SIZE]; | |
297 | dma_addr_t ring_dma_addr; | |
298 | /* The addresses of receive-in-place skbuffs. */ | |
299 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; | |
300 | /* The saved address of a sent-in-place packet/buffer, for later free(). */ | |
301 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
302 | struct net_device_stats stats; | |
303 | struct timer_list timer; /* Media monitoring timer. */ | |
304 | /* Frequently used values: keep some adjacent for cache effect. */ | |
305 | spinlock_t lock; | |
306 | int chip_id, drv_flags; | |
307 | struct pci_dev *pci_dev; | |
308 | int csr6; | |
309 | struct w840_rx_desc *rx_head_desc; | |
310 | unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
311 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
312 | unsigned int cur_tx, dirty_tx; | |
313 | unsigned int tx_q_bytes; | |
314 | unsigned int tx_full; /* The Tx queue is full. */ | |
315 | /* MII transceiver section. */ | |
316 | int mii_cnt; /* MII device addresses. */ | |
317 | unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */ | |
318 | u32 mii; | |
319 | struct mii_if_info mii_if; | |
320 | void __iomem *base_addr; | |
321 | }; | |
322 | ||
323 | static int eeprom_read(void __iomem *ioaddr, int location); | |
324 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
325 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value); | |
326 | static int netdev_open(struct net_device *dev); | |
327 | static int update_link(struct net_device *dev); | |
328 | static void netdev_timer(unsigned long data); | |
329 | static void init_rxtx_rings(struct net_device *dev); | |
330 | static void free_rxtx_rings(struct netdev_private *np); | |
331 | static void init_registers(struct net_device *dev); | |
332 | static void tx_timeout(struct net_device *dev); | |
333 | static int alloc_ringdesc(struct net_device *dev); | |
334 | static void free_ringdesc(struct netdev_private *np); | |
ad096463 | 335 | static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); |
7d12e780 | 336 | static irqreturn_t intr_handler(int irq, void *dev_instance); |
1da177e4 LT |
337 | static void netdev_error(struct net_device *dev, int intr_status); |
338 | static int netdev_rx(struct net_device *dev); | |
339 | static u32 __set_rx_mode(struct net_device *dev); | |
340 | static void set_rx_mode(struct net_device *dev); | |
341 | static struct net_device_stats *get_stats(struct net_device *dev); | |
342 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
7282d491 | 343 | static const struct ethtool_ops netdev_ethtool_ops; |
1da177e4 LT |
344 | static int netdev_close(struct net_device *dev); |
345 | ||
2a97e6b7 SH |
346 | static const struct net_device_ops netdev_ops = { |
347 | .ndo_open = netdev_open, | |
348 | .ndo_stop = netdev_close, | |
349 | .ndo_start_xmit = start_tx, | |
350 | .ndo_get_stats = get_stats, | |
351 | .ndo_set_multicast_list = set_rx_mode, | |
352 | .ndo_do_ioctl = netdev_ioctl, | |
353 | .ndo_tx_timeout = tx_timeout, | |
354 | .ndo_change_mtu = eth_change_mtu, | |
355 | .ndo_set_mac_address = eth_mac_addr, | |
356 | .ndo_validate_addr = eth_validate_addr, | |
357 | }; | |
1da177e4 LT |
358 | |
359 | static int __devinit w840_probe1 (struct pci_dev *pdev, | |
360 | const struct pci_device_id *ent) | |
361 | { | |
362 | struct net_device *dev; | |
363 | struct netdev_private *np; | |
364 | static int find_cnt; | |
365 | int chip_idx = ent->driver_data; | |
366 | int irq; | |
367 | int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0; | |
368 | void __iomem *ioaddr; | |
1da177e4 LT |
369 | |
370 | i = pci_enable_device(pdev); | |
371 | if (i) return i; | |
372 | ||
373 | pci_set_master(pdev); | |
374 | ||
375 | irq = pdev->irq; | |
376 | ||
284901a9 | 377 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { |
a1e37bc5 JP |
378 | pr_warning("Winbond-840: Device %s disabled due to DMA limitations\n", |
379 | pci_name(pdev)); | |
1da177e4 LT |
380 | return -EIO; |
381 | } | |
382 | dev = alloc_etherdev(sizeof(*np)); | |
383 | if (!dev) | |
384 | return -ENOMEM; | |
1da177e4 LT |
385 | SET_NETDEV_DEV(dev, &pdev->dev); |
386 | ||
387 | if (pci_request_regions(pdev, DRV_NAME)) | |
388 | goto err_out_netdev; | |
42eab567 GG |
389 | |
390 | ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size); | |
1da177e4 LT |
391 | if (!ioaddr) |
392 | goto err_out_free_res; | |
393 | ||
394 | for (i = 0; i < 3; i++) | |
c559a5bc | 395 | ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(eeprom_read(ioaddr, i)); |
1da177e4 LT |
396 | |
397 | /* Reset the chip to erase previous misconfiguration. | |
398 | No hold time required! */ | |
399 | iowrite32(0x00000001, ioaddr + PCIBusCfg); | |
400 | ||
401 | dev->base_addr = (unsigned long)ioaddr; | |
402 | dev->irq = irq; | |
403 | ||
404 | np = netdev_priv(dev); | |
405 | np->pci_dev = pdev; | |
406 | np->chip_id = chip_idx; | |
407 | np->drv_flags = pci_id_tbl[chip_idx].drv_flags; | |
408 | spin_lock_init(&np->lock); | |
409 | np->mii_if.dev = dev; | |
410 | np->mii_if.mdio_read = mdio_read; | |
411 | np->mii_if.mdio_write = mdio_write; | |
412 | np->base_addr = ioaddr; | |
f3b197ac | 413 | |
1da177e4 LT |
414 | pci_set_drvdata(pdev, dev); |
415 | ||
416 | if (dev->mem_start) | |
417 | option = dev->mem_start; | |
418 | ||
419 | /* The lower four bits are the media type. */ | |
420 | if (option > 0) { | |
421 | if (option & 0x200) | |
422 | np->mii_if.full_duplex = 1; | |
423 | if (option & 15) | |
a1e37bc5 JP |
424 | dev_info(&dev->dev, |
425 | "ignoring user supplied media type %d", | |
426 | option & 15); | |
1da177e4 LT |
427 | } |
428 | if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0) | |
429 | np->mii_if.full_duplex = 1; | |
430 | ||
431 | if (np->mii_if.full_duplex) | |
432 | np->mii_if.force_media = 1; | |
433 | ||
434 | /* The chip-specific entries in the device structure. */ | |
2a97e6b7 | 435 | dev->netdev_ops = &netdev_ops; |
1da177e4 | 436 | dev->ethtool_ops = &netdev_ethtool_ops; |
1da177e4 LT |
437 | dev->watchdog_timeo = TX_TIMEOUT; |
438 | ||
439 | i = register_netdev(dev); | |
440 | if (i) | |
441 | goto err_out_cleardev; | |
442 | ||
a1e37bc5 JP |
443 | dev_info(&dev->dev, "%s at %p, %pM, IRQ %d\n", |
444 | pci_id_tbl[chip_idx].name, ioaddr, dev->dev_addr, irq); | |
1da177e4 LT |
445 | |
446 | if (np->drv_flags & CanHaveMII) { | |
447 | int phy, phy_idx = 0; | |
448 | for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) { | |
449 | int mii_status = mdio_read(dev, phy, MII_BMSR); | |
450 | if (mii_status != 0xffff && mii_status != 0x0000) { | |
451 | np->phys[phy_idx++] = phy; | |
452 | np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE); | |
453 | np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+ | |
454 | mdio_read(dev, phy, MII_PHYSID2); | |
a1e37bc5 JP |
455 | dev_info(&dev->dev, |
456 | "MII PHY %08xh found at address %d, status 0x%04x advertising %04x\n", | |
457 | np->mii, phy, mii_status, | |
458 | np->mii_if.advertising); | |
1da177e4 LT |
459 | } |
460 | } | |
461 | np->mii_cnt = phy_idx; | |
462 | np->mii_if.phy_id = np->phys[0]; | |
463 | if (phy_idx == 0) { | |
a1e37bc5 JP |
464 | dev_warn(&dev->dev, |
465 | "MII PHY not found -- this device may not operate correctly\n"); | |
1da177e4 LT |
466 | } |
467 | } | |
468 | ||
469 | find_cnt++; | |
470 | return 0; | |
471 | ||
472 | err_out_cleardev: | |
473 | pci_set_drvdata(pdev, NULL); | |
474 | pci_iounmap(pdev, ioaddr); | |
475 | err_out_free_res: | |
476 | pci_release_regions(pdev); | |
477 | err_out_netdev: | |
478 | free_netdev (dev); | |
479 | return -ENODEV; | |
480 | } | |
481 | ||
f3b197ac | 482 | |
1da177e4 LT |
483 | /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are |
484 | often serial bit streams generated by the host processor. | |
485 | The example below is for the common 93c46 EEPROM, 64 16 bit words. */ | |
486 | ||
487 | /* Delay between EEPROM clock transitions. | |
488 | No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need | |
489 | a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that | |
490 | made udelay() unreliable. | |
491 | The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is | |
405bbe9f | 492 | deprecated. |
1da177e4 LT |
493 | */ |
494 | #define eeprom_delay(ee_addr) ioread32(ee_addr) | |
495 | ||
496 | enum EEPROM_Ctrl_Bits { | |
497 | EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805, | |
498 | EE_ChipSelect=0x801, EE_DataIn=0x08, | |
499 | }; | |
500 | ||
501 | /* The EEPROM commands include the alway-set leading bit. */ | |
502 | enum EEPROM_Cmds { | |
503 | EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6), | |
504 | }; | |
505 | ||
506 | static int eeprom_read(void __iomem *addr, int location) | |
507 | { | |
508 | int i; | |
509 | int retval = 0; | |
510 | void __iomem *ee_addr = addr + EECtrl; | |
511 | int read_cmd = location | EE_ReadCmd; | |
512 | iowrite32(EE_ChipSelect, ee_addr); | |
513 | ||
514 | /* Shift the read command bits out. */ | |
515 | for (i = 10; i >= 0; i--) { | |
516 | short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; | |
517 | iowrite32(dataval, ee_addr); | |
518 | eeprom_delay(ee_addr); | |
519 | iowrite32(dataval | EE_ShiftClk, ee_addr); | |
520 | eeprom_delay(ee_addr); | |
521 | } | |
522 | iowrite32(EE_ChipSelect, ee_addr); | |
523 | eeprom_delay(ee_addr); | |
524 | ||
525 | for (i = 16; i > 0; i--) { | |
526 | iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr); | |
527 | eeprom_delay(ee_addr); | |
528 | retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0); | |
529 | iowrite32(EE_ChipSelect, ee_addr); | |
530 | eeprom_delay(ee_addr); | |
531 | } | |
532 | ||
533 | /* Terminate the EEPROM access. */ | |
534 | iowrite32(0, ee_addr); | |
535 | return retval; | |
536 | } | |
537 | ||
538 | /* MII transceiver control section. | |
539 | Read and write the MII registers using software-generated serial | |
540 | MDIO protocol. See the MII specifications or DP83840A data sheet | |
541 | for details. | |
542 | ||
543 | The maximum data clock rate is 2.5 Mhz. The minimum timing is usually | |
544 | met by back-to-back 33Mhz PCI cycles. */ | |
545 | #define mdio_delay(mdio_addr) ioread32(mdio_addr) | |
546 | ||
547 | /* Set iff a MII transceiver on any interface requires mdio preamble. | |
548 | This only set with older transceivers, so the extra | |
549 | code size of a per-interface flag is not worthwhile. */ | |
550 | static char mii_preamble_required = 1; | |
551 | ||
552 | #define MDIO_WRITE0 (MDIO_EnbOutput) | |
553 | #define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput) | |
554 | ||
555 | /* Generate the preamble required for initial synchronization and | |
556 | a few older transceivers. */ | |
557 | static void mdio_sync(void __iomem *mdio_addr) | |
558 | { | |
559 | int bits = 32; | |
560 | ||
561 | /* Establish sync by sending at least 32 logic ones. */ | |
562 | while (--bits >= 0) { | |
563 | iowrite32(MDIO_WRITE1, mdio_addr); | |
564 | mdio_delay(mdio_addr); | |
565 | iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr); | |
566 | mdio_delay(mdio_addr); | |
567 | } | |
568 | } | |
569 | ||
570 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
571 | { | |
572 | struct netdev_private *np = netdev_priv(dev); | |
573 | void __iomem *mdio_addr = np->base_addr + MIICtrl; | |
574 | int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; | |
575 | int i, retval = 0; | |
576 | ||
577 | if (mii_preamble_required) | |
578 | mdio_sync(mdio_addr); | |
579 | ||
580 | /* Shift the read command bits out. */ | |
581 | for (i = 15; i >= 0; i--) { | |
582 | int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; | |
583 | ||
584 | iowrite32(dataval, mdio_addr); | |
585 | mdio_delay(mdio_addr); | |
586 | iowrite32(dataval | MDIO_ShiftClk, mdio_addr); | |
587 | mdio_delay(mdio_addr); | |
588 | } | |
589 | /* Read the two transition, 16 data, and wire-idle bits. */ | |
590 | for (i = 20; i > 0; i--) { | |
591 | iowrite32(MDIO_EnbIn, mdio_addr); | |
592 | mdio_delay(mdio_addr); | |
593 | retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0); | |
594 | iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); | |
595 | mdio_delay(mdio_addr); | |
596 | } | |
597 | return (retval>>1) & 0xffff; | |
598 | } | |
599 | ||
600 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | |
601 | { | |
602 | struct netdev_private *np = netdev_priv(dev); | |
603 | void __iomem *mdio_addr = np->base_addr + MIICtrl; | |
604 | int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value; | |
605 | int i; | |
606 | ||
607 | if (location == 4 && phy_id == np->phys[0]) | |
608 | np->mii_if.advertising = value; | |
609 | ||
610 | if (mii_preamble_required) | |
611 | mdio_sync(mdio_addr); | |
612 | ||
613 | /* Shift the command bits out. */ | |
614 | for (i = 31; i >= 0; i--) { | |
615 | int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; | |
616 | ||
617 | iowrite32(dataval, mdio_addr); | |
618 | mdio_delay(mdio_addr); | |
619 | iowrite32(dataval | MDIO_ShiftClk, mdio_addr); | |
620 | mdio_delay(mdio_addr); | |
621 | } | |
622 | /* Clear out extra bits. */ | |
623 | for (i = 2; i > 0; i--) { | |
624 | iowrite32(MDIO_EnbIn, mdio_addr); | |
625 | mdio_delay(mdio_addr); | |
626 | iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); | |
627 | mdio_delay(mdio_addr); | |
628 | } | |
629 | return; | |
630 | } | |
631 | ||
f3b197ac | 632 | |
1da177e4 LT |
633 | static int netdev_open(struct net_device *dev) |
634 | { | |
635 | struct netdev_private *np = netdev_priv(dev); | |
636 | void __iomem *ioaddr = np->base_addr; | |
637 | int i; | |
638 | ||
639 | iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */ | |
640 | ||
641 | netif_device_detach(dev); | |
a0607fd3 | 642 | i = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
643 | if (i) |
644 | goto out_err; | |
645 | ||
646 | if (debug > 1) | |
a1e37bc5 JP |
647 | printk(KERN_DEBUG "%s: w89c840_open() irq %d\n", |
648 | dev->name, dev->irq); | |
1da177e4 LT |
649 | |
650 | if((i=alloc_ringdesc(dev))) | |
651 | goto out_err; | |
652 | ||
653 | spin_lock_irq(&np->lock); | |
654 | netif_device_attach(dev); | |
655 | init_registers(dev); | |
656 | spin_unlock_irq(&np->lock); | |
657 | ||
658 | netif_start_queue(dev); | |
659 | if (debug > 2) | |
a1e37bc5 | 660 | printk(KERN_DEBUG "%s: Done netdev_open()\n", dev->name); |
1da177e4 LT |
661 | |
662 | /* Set the timer to check for link beat. */ | |
663 | init_timer(&np->timer); | |
664 | np->timer.expires = jiffies + 1*HZ; | |
665 | np->timer.data = (unsigned long)dev; | |
666 | np->timer.function = &netdev_timer; /* timer handler */ | |
667 | add_timer(&np->timer); | |
668 | return 0; | |
669 | out_err: | |
670 | netif_device_attach(dev); | |
671 | return i; | |
672 | } | |
673 | ||
674 | #define MII_DAVICOM_DM9101 0x0181b800 | |
675 | ||
676 | static int update_link(struct net_device *dev) | |
677 | { | |
678 | struct netdev_private *np = netdev_priv(dev); | |
679 | int duplex, fasteth, result, mii_reg; | |
680 | ||
681 | /* BSMR */ | |
682 | mii_reg = mdio_read(dev, np->phys[0], MII_BMSR); | |
683 | ||
684 | if (mii_reg == 0xffff) | |
685 | return np->csr6; | |
686 | /* reread: the link status bit is sticky */ | |
687 | mii_reg = mdio_read(dev, np->phys[0], MII_BMSR); | |
688 | if (!(mii_reg & 0x4)) { | |
689 | if (netif_carrier_ok(dev)) { | |
690 | if (debug) | |
a1e37bc5 JP |
691 | dev_info(&dev->dev, |
692 | "MII #%d reports no link. Disabling watchdog\n", | |
693 | np->phys[0]); | |
1da177e4 LT |
694 | netif_carrier_off(dev); |
695 | } | |
696 | return np->csr6; | |
697 | } | |
698 | if (!netif_carrier_ok(dev)) { | |
699 | if (debug) | |
a1e37bc5 JP |
700 | dev_info(&dev->dev, |
701 | "MII #%d link is back. Enabling watchdog\n", | |
702 | np->phys[0]); | |
1da177e4 LT |
703 | netif_carrier_on(dev); |
704 | } | |
f3b197ac | 705 | |
1da177e4 LT |
706 | if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) { |
707 | /* If the link partner doesn't support autonegotiation | |
708 | * the MII detects it's abilities with the "parallel detection". | |
709 | * Some MIIs update the LPA register to the result of the parallel | |
710 | * detection, some don't. | |
711 | * The Davicom PHY [at least 0181b800] doesn't. | |
712 | * Instead bit 9 and 13 of the BMCR are updated to the result | |
713 | * of the negotiation.. | |
714 | */ | |
715 | mii_reg = mdio_read(dev, np->phys[0], MII_BMCR); | |
716 | duplex = mii_reg & BMCR_FULLDPLX; | |
717 | fasteth = mii_reg & BMCR_SPEED100; | |
718 | } else { | |
719 | int negotiated; | |
720 | mii_reg = mdio_read(dev, np->phys[0], MII_LPA); | |
721 | negotiated = mii_reg & np->mii_if.advertising; | |
722 | ||
723 | duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL); | |
724 | fasteth = negotiated & 0x380; | |
725 | } | |
726 | duplex |= np->mii_if.force_media; | |
727 | /* remove fastether and fullduplex */ | |
728 | result = np->csr6 & ~0x20000200; | |
729 | if (duplex) | |
730 | result |= 0x200; | |
731 | if (fasteth) | |
732 | result |= 0x20000000; | |
733 | if (result != np->csr6 && debug) | |
a1e37bc5 JP |
734 | dev_info(&dev->dev, |
735 | "Setting %dMBit-%s-duplex based on MII#%d\n", | |
736 | fasteth ? 100 : 10, duplex ? "full" : "half", | |
737 | np->phys[0]); | |
1da177e4 LT |
738 | return result; |
739 | } | |
740 | ||
741 | #define RXTX_TIMEOUT 2000 | |
742 | static inline void update_csr6(struct net_device *dev, int new) | |
743 | { | |
744 | struct netdev_private *np = netdev_priv(dev); | |
745 | void __iomem *ioaddr = np->base_addr; | |
746 | int limit = RXTX_TIMEOUT; | |
747 | ||
748 | if (!netif_device_present(dev)) | |
749 | new = 0; | |
750 | if (new==np->csr6) | |
751 | return; | |
752 | /* stop both Tx and Rx processes */ | |
753 | iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig); | |
754 | /* wait until they have really stopped */ | |
755 | for (;;) { | |
756 | int csr5 = ioread32(ioaddr + IntrStatus); | |
757 | int t; | |
758 | ||
759 | t = (csr5 >> 17) & 0x07; | |
760 | if (t==0||t==1) { | |
761 | /* rx stopped */ | |
762 | t = (csr5 >> 20) & 0x07; | |
763 | if (t==0||t==1) | |
764 | break; | |
765 | } | |
766 | ||
767 | limit--; | |
768 | if(!limit) { | |
a1e37bc5 JP |
769 | dev_info(&dev->dev, |
770 | "couldn't stop rxtx, IntrStatus %xh\n", csr5); | |
1da177e4 LT |
771 | break; |
772 | } | |
773 | udelay(1); | |
774 | } | |
775 | np->csr6 = new; | |
776 | /* and restart them with the new configuration */ | |
777 | iowrite32(np->csr6, ioaddr + NetworkConfig); | |
778 | if (new & 0x200) | |
779 | np->mii_if.full_duplex = 1; | |
780 | } | |
781 | ||
782 | static void netdev_timer(unsigned long data) | |
783 | { | |
784 | struct net_device *dev = (struct net_device *)data; | |
785 | struct netdev_private *np = netdev_priv(dev); | |
786 | void __iomem *ioaddr = np->base_addr; | |
787 | ||
788 | if (debug > 2) | |
a1e37bc5 JP |
789 | printk(KERN_DEBUG "%s: Media selection timer tick, status %08x config %08x\n", |
790 | dev->name, ioread32(ioaddr + IntrStatus), | |
791 | ioread32(ioaddr + NetworkConfig)); | |
1da177e4 LT |
792 | spin_lock_irq(&np->lock); |
793 | update_csr6(dev, update_link(dev)); | |
794 | spin_unlock_irq(&np->lock); | |
795 | np->timer.expires = jiffies + 10*HZ; | |
796 | add_timer(&np->timer); | |
797 | } | |
798 | ||
799 | static void init_rxtx_rings(struct net_device *dev) | |
800 | { | |
801 | struct netdev_private *np = netdev_priv(dev); | |
802 | int i; | |
803 | ||
804 | np->rx_head_desc = &np->rx_ring[0]; | |
805 | np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE]; | |
806 | ||
807 | /* Initial all Rx descriptors. */ | |
808 | for (i = 0; i < RX_RING_SIZE; i++) { | |
809 | np->rx_ring[i].length = np->rx_buf_sz; | |
810 | np->rx_ring[i].status = 0; | |
811 | np->rx_skbuff[i] = NULL; | |
812 | } | |
813 | /* Mark the last entry as wrapping the ring. */ | |
814 | np->rx_ring[i-1].length |= DescEndRing; | |
815 | ||
816 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
817 | for (i = 0; i < RX_RING_SIZE; i++) { | |
818 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz); | |
819 | np->rx_skbuff[i] = skb; | |
820 | if (skb == NULL) | |
821 | break; | |
689be439 | 822 | np->rx_addr[i] = pci_map_single(np->pci_dev,skb->data, |
bb02aacc | 823 | np->rx_buf_sz,PCI_DMA_FROMDEVICE); |
1da177e4 LT |
824 | |
825 | np->rx_ring[i].buffer1 = np->rx_addr[i]; | |
42eab567 | 826 | np->rx_ring[i].status = DescOwned; |
1da177e4 LT |
827 | } |
828 | ||
829 | np->cur_rx = 0; | |
830 | np->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
831 | ||
832 | /* Initialize the Tx descriptors */ | |
833 | for (i = 0; i < TX_RING_SIZE; i++) { | |
834 | np->tx_skbuff[i] = NULL; | |
835 | np->tx_ring[i].status = 0; | |
836 | } | |
837 | np->tx_full = 0; | |
838 | np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0; | |
839 | ||
840 | iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr); | |
841 | iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE, | |
842 | np->base_addr + TxRingPtr); | |
843 | ||
844 | } | |
845 | ||
846 | static void free_rxtx_rings(struct netdev_private* np) | |
847 | { | |
848 | int i; | |
849 | /* Free all the skbuffs in the Rx queue. */ | |
850 | for (i = 0; i < RX_RING_SIZE; i++) { | |
851 | np->rx_ring[i].status = 0; | |
852 | if (np->rx_skbuff[i]) { | |
853 | pci_unmap_single(np->pci_dev, | |
854 | np->rx_addr[i], | |
855 | np->rx_skbuff[i]->len, | |
856 | PCI_DMA_FROMDEVICE); | |
857 | dev_kfree_skb(np->rx_skbuff[i]); | |
858 | } | |
859 | np->rx_skbuff[i] = NULL; | |
860 | } | |
861 | for (i = 0; i < TX_RING_SIZE; i++) { | |
862 | if (np->tx_skbuff[i]) { | |
863 | pci_unmap_single(np->pci_dev, | |
864 | np->tx_addr[i], | |
865 | np->tx_skbuff[i]->len, | |
866 | PCI_DMA_TODEVICE); | |
867 | dev_kfree_skb(np->tx_skbuff[i]); | |
868 | } | |
869 | np->tx_skbuff[i] = NULL; | |
870 | } | |
871 | } | |
872 | ||
873 | static void init_registers(struct net_device *dev) | |
874 | { | |
875 | struct netdev_private *np = netdev_priv(dev); | |
876 | void __iomem *ioaddr = np->base_addr; | |
877 | int i; | |
878 | ||
879 | for (i = 0; i < 6; i++) | |
880 | iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i); | |
881 | ||
882 | /* Initialize other registers. */ | |
883 | #ifdef __BIG_ENDIAN | |
884 | i = (1<<20); /* Big-endian descriptors */ | |
885 | #else | |
886 | i = 0; | |
887 | #endif | |
888 | i |= (0x04<<2); /* skip length 4 u32 */ | |
889 | i |= 0x02; /* give Rx priority */ | |
890 | ||
891 | /* Configure the PCI bus bursts and FIFO thresholds. | |
892 | 486: Set 8 longword cache alignment, 8 longword burst. | |
893 | 586: Set 16 longword cache alignment, no burst limit. | |
894 | Cache alignment bits 15:14 Burst length 13:8 | |
895 | 0000 <not allowed> 0000 align to cache 0800 8 longwords | |
896 | 4000 8 longwords 0100 1 longword 1000 16 longwords | |
897 | 8000 16 longwords 0200 2 longwords 2000 32 longwords | |
898 | C000 32 longwords 0400 4 longwords */ | |
899 | ||
900 | #if defined (__i386__) && !defined(MODULE) | |
901 | /* When not a module we can work around broken '486 PCI boards. */ | |
902 | if (boot_cpu_data.x86 <= 4) { | |
903 | i |= 0x4800; | |
a1e37bc5 JP |
904 | dev_info(&dev->dev, |
905 | "This is a 386/486 PCI system, setting cache alignment to 8 longwords\n"); | |
1da177e4 LT |
906 | } else { |
907 | i |= 0xE000; | |
908 | } | |
909 | #elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__) | |
910 | i |= 0xE000; | |
49345103 | 911 | #elif defined(CONFIG_SPARC) || defined (CONFIG_PARISC) |
1da177e4 LT |
912 | i |= 0x4800; |
913 | #else | |
914 | #warning Processor architecture undefined | |
915 | i |= 0x4800; | |
916 | #endif | |
917 | iowrite32(i, ioaddr + PCIBusCfg); | |
918 | ||
919 | np->csr6 = 0; | |
f3b197ac | 920 | /* 128 byte Tx threshold; |
1da177e4 LT |
921 | Transmit on; Receive on; */ |
922 | update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev)); | |
923 | ||
924 | /* Clear and Enable interrupts by setting the interrupt mask. */ | |
925 | iowrite32(0x1A0F5, ioaddr + IntrStatus); | |
926 | iowrite32(0x1A0F5, ioaddr + IntrEnable); | |
927 | ||
928 | iowrite32(0, ioaddr + RxStartDemand); | |
929 | } | |
930 | ||
931 | static void tx_timeout(struct net_device *dev) | |
932 | { | |
933 | struct netdev_private *np = netdev_priv(dev); | |
934 | void __iomem *ioaddr = np->base_addr; | |
935 | ||
a1e37bc5 JP |
936 | dev_warn(&dev->dev, "Transmit timed out, status %08x, resetting...\n", |
937 | ioread32(ioaddr + IntrStatus)); | |
1da177e4 LT |
938 | |
939 | { | |
940 | int i; | |
941 | printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring); | |
942 | for (i = 0; i < RX_RING_SIZE; i++) | |
a1e37bc5 JP |
943 | printk(KERN_CONT " %08x", (unsigned int)np->rx_ring[i].status); |
944 | printk(KERN_CONT "\n"); | |
945 | printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring); | |
1da177e4 | 946 | for (i = 0; i < TX_RING_SIZE; i++) |
a1e37bc5 JP |
947 | printk(KERN_CONT " %08x", np->tx_ring[i].status); |
948 | printk(KERN_CONT "\n"); | |
1da177e4 | 949 | } |
a1e37bc5 JP |
950 | printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d\n", |
951 | np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes); | |
952 | printk(KERN_DEBUG "Tx Descriptor addr %xh\n", ioread32(ioaddr+0x4C)); | |
1da177e4 LT |
953 | |
954 | disable_irq(dev->irq); | |
955 | spin_lock_irq(&np->lock); | |
956 | /* | |
957 | * Under high load dirty_tx and the internal tx descriptor pointer | |
958 | * come out of sync, thus perform a software reset and reinitialize | |
959 | * everything. | |
960 | */ | |
961 | ||
962 | iowrite32(1, np->base_addr+PCIBusCfg); | |
963 | udelay(1); | |
964 | ||
965 | free_rxtx_rings(np); | |
966 | init_rxtx_rings(dev); | |
967 | init_registers(dev); | |
968 | spin_unlock_irq(&np->lock); | |
969 | enable_irq(dev->irq); | |
970 | ||
971 | netif_wake_queue(dev); | |
1ae5dc34 | 972 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1da177e4 LT |
973 | np->stats.tx_errors++; |
974 | return; | |
975 | } | |
976 | ||
977 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
978 | static int alloc_ringdesc(struct net_device *dev) | |
979 | { | |
980 | struct netdev_private *np = netdev_priv(dev); | |
981 | ||
982 | np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
983 | ||
984 | np->rx_ring = pci_alloc_consistent(np->pci_dev, | |
985 | sizeof(struct w840_rx_desc)*RX_RING_SIZE + | |
986 | sizeof(struct w840_tx_desc)*TX_RING_SIZE, | |
987 | &np->ring_dma_addr); | |
988 | if(!np->rx_ring) | |
989 | return -ENOMEM; | |
990 | init_rxtx_rings(dev); | |
991 | return 0; | |
992 | } | |
993 | ||
994 | static void free_ringdesc(struct netdev_private *np) | |
995 | { | |
996 | pci_free_consistent(np->pci_dev, | |
997 | sizeof(struct w840_rx_desc)*RX_RING_SIZE + | |
998 | sizeof(struct w840_tx_desc)*TX_RING_SIZE, | |
999 | np->rx_ring, np->ring_dma_addr); | |
1000 | ||
1001 | } | |
1002 | ||
ad096463 | 1003 | static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
1004 | { |
1005 | struct netdev_private *np = netdev_priv(dev); | |
1006 | unsigned entry; | |
1007 | ||
1008 | /* Caution: the write order is important here, set the field | |
1009 | with the "ownership" bits last. */ | |
1010 | ||
1011 | /* Calculate the next Tx descriptor entry. */ | |
1012 | entry = np->cur_tx % TX_RING_SIZE; | |
1013 | ||
1014 | np->tx_addr[entry] = pci_map_single(np->pci_dev, | |
1015 | skb->data,skb->len, PCI_DMA_TODEVICE); | |
1016 | np->tx_skbuff[entry] = skb; | |
1017 | ||
1018 | np->tx_ring[entry].buffer1 = np->tx_addr[entry]; | |
1019 | if (skb->len < TX_BUFLIMIT) { | |
1020 | np->tx_ring[entry].length = DescWholePkt | skb->len; | |
1021 | } else { | |
1022 | int len = skb->len - TX_BUFLIMIT; | |
1023 | ||
1024 | np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT; | |
1025 | np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT; | |
1026 | } | |
1027 | if(entry == TX_RING_SIZE-1) | |
1028 | np->tx_ring[entry].length |= DescEndRing; | |
1029 | ||
1030 | /* Now acquire the irq spinlock. | |
59c51591 | 1031 | * The difficult race is the ordering between |
42eab567 | 1032 | * increasing np->cur_tx and setting DescOwned: |
1da177e4 LT |
1033 | * - if np->cur_tx is increased first the interrupt |
1034 | * handler could consider the packet as transmitted | |
42eab567 GG |
1035 | * since DescOwned is cleared. |
1036 | * - If DescOwned is set first the NIC could report the | |
1da177e4 LT |
1037 | * packet as sent, but the interrupt handler would ignore it |
1038 | * since the np->cur_tx was not yet increased. | |
1039 | */ | |
1040 | spin_lock_irq(&np->lock); | |
1041 | np->cur_tx++; | |
1042 | ||
1043 | wmb(); /* flush length, buffer1, buffer2 */ | |
42eab567 | 1044 | np->tx_ring[entry].status = DescOwned; |
1da177e4 LT |
1045 | wmb(); /* flush status and kick the hardware */ |
1046 | iowrite32(0, np->base_addr + TxStartDemand); | |
1047 | np->tx_q_bytes += skb->len; | |
1048 | /* Work around horrible bug in the chip by marking the queue as full | |
1049 | when we do not have FIFO room for a maximum sized packet. */ | |
1050 | if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN || | |
1051 | ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) { | |
1052 | netif_stop_queue(dev); | |
1053 | wmb(); | |
1054 | np->tx_full = 1; | |
1055 | } | |
1056 | spin_unlock_irq(&np->lock); | |
1057 | ||
1da177e4 | 1058 | if (debug > 4) { |
a1e37bc5 JP |
1059 | printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d\n", |
1060 | dev->name, np->cur_tx, entry); | |
1da177e4 | 1061 | } |
6ed10654 | 1062 | return NETDEV_TX_OK; |
1da177e4 LT |
1063 | } |
1064 | ||
1065 | static void netdev_tx_done(struct net_device *dev) | |
1066 | { | |
1067 | struct netdev_private *np = netdev_priv(dev); | |
1068 | for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { | |
1069 | int entry = np->dirty_tx % TX_RING_SIZE; | |
1070 | int tx_status = np->tx_ring[entry].status; | |
1071 | ||
1072 | if (tx_status < 0) | |
1073 | break; | |
1074 | if (tx_status & 0x8000) { /* There was an error, log it. */ | |
1075 | #ifndef final_version | |
1076 | if (debug > 1) | |
a1e37bc5 JP |
1077 | printk(KERN_DEBUG "%s: Transmit error, Tx status %08x\n", |
1078 | dev->name, tx_status); | |
1da177e4 LT |
1079 | #endif |
1080 | np->stats.tx_errors++; | |
1081 | if (tx_status & 0x0104) np->stats.tx_aborted_errors++; | |
1082 | if (tx_status & 0x0C80) np->stats.tx_carrier_errors++; | |
1083 | if (tx_status & 0x0200) np->stats.tx_window_errors++; | |
1084 | if (tx_status & 0x0002) np->stats.tx_fifo_errors++; | |
1085 | if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0) | |
1086 | np->stats.tx_heartbeat_errors++; | |
1087 | } else { | |
1088 | #ifndef final_version | |
1089 | if (debug > 3) | |
a1e37bc5 JP |
1090 | printk(KERN_DEBUG "%s: Transmit slot %d ok, Tx status %08x\n", |
1091 | dev->name, entry, tx_status); | |
1da177e4 LT |
1092 | #endif |
1093 | np->stats.tx_bytes += np->tx_skbuff[entry]->len; | |
1094 | np->stats.collisions += (tx_status >> 3) & 15; | |
1095 | np->stats.tx_packets++; | |
1096 | } | |
1097 | /* Free the original skb. */ | |
1098 | pci_unmap_single(np->pci_dev,np->tx_addr[entry], | |
1099 | np->tx_skbuff[entry]->len, | |
1100 | PCI_DMA_TODEVICE); | |
1101 | np->tx_q_bytes -= np->tx_skbuff[entry]->len; | |
1102 | dev_kfree_skb_irq(np->tx_skbuff[entry]); | |
1103 | np->tx_skbuff[entry] = NULL; | |
1104 | } | |
1105 | if (np->tx_full && | |
1106 | np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART && | |
1107 | np->tx_q_bytes < TX_BUG_FIFO_LIMIT) { | |
1108 | /* The ring is no longer full, clear tbusy. */ | |
1109 | np->tx_full = 0; | |
1110 | wmb(); | |
1111 | netif_wake_queue(dev); | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1116 | after the Tx thread. */ | |
7d12e780 | 1117 | static irqreturn_t intr_handler(int irq, void *dev_instance) |
1da177e4 LT |
1118 | { |
1119 | struct net_device *dev = (struct net_device *)dev_instance; | |
1120 | struct netdev_private *np = netdev_priv(dev); | |
1121 | void __iomem *ioaddr = np->base_addr; | |
1122 | int work_limit = max_interrupt_work; | |
1123 | int handled = 0; | |
1124 | ||
1125 | if (!netif_device_present(dev)) | |
1126 | return IRQ_NONE; | |
1127 | do { | |
1128 | u32 intr_status = ioread32(ioaddr + IntrStatus); | |
1129 | ||
1130 | /* Acknowledge all of the current interrupt sources ASAP. */ | |
1131 | iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus); | |
1132 | ||
1133 | if (debug > 4) | |
a1e37bc5 JP |
1134 | printk(KERN_DEBUG "%s: Interrupt, status %04x\n", |
1135 | dev->name, intr_status); | |
1da177e4 LT |
1136 | |
1137 | if ((intr_status & (NormalIntr|AbnormalIntr)) == 0) | |
1138 | break; | |
1139 | ||
1140 | handled = 1; | |
1141 | ||
42eab567 | 1142 | if (intr_status & (RxIntr | RxNoBuf)) |
1da177e4 LT |
1143 | netdev_rx(dev); |
1144 | if (intr_status & RxNoBuf) | |
1145 | iowrite32(0, ioaddr + RxStartDemand); | |
1146 | ||
42eab567 | 1147 | if (intr_status & (TxNoBuf | TxIntr) && |
1da177e4 LT |
1148 | np->cur_tx != np->dirty_tx) { |
1149 | spin_lock(&np->lock); | |
1150 | netdev_tx_done(dev); | |
1151 | spin_unlock(&np->lock); | |
1152 | } | |
1153 | ||
1154 | /* Abnormal error summary/uncommon events handlers. */ | |
1ddb9861 | 1155 | if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SystemError | |
42eab567 | 1156 | TimerInt | TxDied)) |
1da177e4 LT |
1157 | netdev_error(dev, intr_status); |
1158 | ||
1159 | if (--work_limit < 0) { | |
a1e37bc5 JP |
1160 | dev_warn(&dev->dev, |
1161 | "Too much work at interrupt, status=0x%04x\n", | |
1162 | intr_status); | |
1da177e4 LT |
1163 | /* Set the timer to re-enable the other interrupts after |
1164 | 10*82usec ticks. */ | |
1165 | spin_lock(&np->lock); | |
1166 | if (netif_device_present(dev)) { | |
1167 | iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable); | |
1168 | iowrite32(10, ioaddr + GPTimer); | |
1169 | } | |
1170 | spin_unlock(&np->lock); | |
1171 | break; | |
1172 | } | |
1173 | } while (1); | |
1174 | ||
1175 | if (debug > 3) | |
a1e37bc5 JP |
1176 | printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x\n", |
1177 | dev->name, ioread32(ioaddr + IntrStatus)); | |
1da177e4 LT |
1178 | return IRQ_RETVAL(handled); |
1179 | } | |
1180 | ||
1181 | /* This routine is logically part of the interrupt handler, but separated | |
1182 | for clarity and better register allocation. */ | |
1183 | static int netdev_rx(struct net_device *dev) | |
1184 | { | |
1185 | struct netdev_private *np = netdev_priv(dev); | |
1186 | int entry = np->cur_rx % RX_RING_SIZE; | |
1187 | int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx; | |
1188 | ||
1189 | if (debug > 4) { | |
a1e37bc5 JP |
1190 | printk(KERN_DEBUG " In netdev_rx(), entry %d status %04x\n", |
1191 | entry, np->rx_ring[entry].status); | |
1da177e4 LT |
1192 | } |
1193 | ||
1194 | /* If EOP is set on the next entry, it's a new packet. Send it up. */ | |
1195 | while (--work_limit >= 0) { | |
1196 | struct w840_rx_desc *desc = np->rx_head_desc; | |
1197 | s32 status = desc->status; | |
1198 | ||
1199 | if (debug > 4) | |
a1e37bc5 JP |
1200 | printk(KERN_DEBUG " netdev_rx() status was %08x\n", |
1201 | status); | |
1da177e4 LT |
1202 | if (status < 0) |
1203 | break; | |
1204 | if ((status & 0x38008300) != 0x0300) { | |
1205 | if ((status & 0x38000300) != 0x0300) { | |
1206 | /* Ingore earlier buffers. */ | |
1207 | if ((status & 0xffff) != 0x7fff) { | |
a1e37bc5 JP |
1208 | dev_warn(&dev->dev, |
1209 | "Oversized Ethernet frame spanned multiple buffers, entry %#x status %04x!\n", | |
1210 | np->cur_rx, status); | |
1da177e4 LT |
1211 | np->stats.rx_length_errors++; |
1212 | } | |
1213 | } else if (status & 0x8000) { | |
1214 | /* There was a fatal error. */ | |
1215 | if (debug > 2) | |
a1e37bc5 JP |
1216 | printk(KERN_DEBUG "%s: Receive error, Rx status %08x\n", |
1217 | dev->name, status); | |
1da177e4 LT |
1218 | np->stats.rx_errors++; /* end of a packet.*/ |
1219 | if (status & 0x0890) np->stats.rx_length_errors++; | |
1220 | if (status & 0x004C) np->stats.rx_frame_errors++; | |
1221 | if (status & 0x0002) np->stats.rx_crc_errors++; | |
1222 | } | |
1223 | } else { | |
1224 | struct sk_buff *skb; | |
1225 | /* Omit the four octet CRC from the length. */ | |
1226 | int pkt_len = ((status >> 16) & 0x7ff) - 4; | |
1227 | ||
1228 | #ifndef final_version | |
1229 | if (debug > 4) | |
a1e37bc5 JP |
1230 | printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d status %x\n", |
1231 | pkt_len, status); | |
1da177e4 LT |
1232 | #endif |
1233 | /* Check if the packet is long enough to accept without copying | |
1234 | to a minimally-sized skbuff. */ | |
8e95a202 JP |
1235 | if (pkt_len < rx_copybreak && |
1236 | (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { | |
1da177e4 LT |
1237 | skb_reserve(skb, 2); /* 16 byte align the IP header */ |
1238 | pci_dma_sync_single_for_cpu(np->pci_dev,np->rx_addr[entry], | |
1239 | np->rx_skbuff[entry]->len, | |
1240 | PCI_DMA_FROMDEVICE); | |
8c7b7faa | 1241 | skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len); |
1da177e4 LT |
1242 | skb_put(skb, pkt_len); |
1243 | pci_dma_sync_single_for_device(np->pci_dev,np->rx_addr[entry], | |
1244 | np->rx_skbuff[entry]->len, | |
1245 | PCI_DMA_FROMDEVICE); | |
1246 | } else { | |
1247 | pci_unmap_single(np->pci_dev,np->rx_addr[entry], | |
1248 | np->rx_skbuff[entry]->len, | |
1249 | PCI_DMA_FROMDEVICE); | |
1250 | skb_put(skb = np->rx_skbuff[entry], pkt_len); | |
1251 | np->rx_skbuff[entry] = NULL; | |
1252 | } | |
1253 | #ifndef final_version /* Remove after testing. */ | |
1254 | /* You will want this info for the initial debug. */ | |
e174961c | 1255 | if (debug > 5) |
a1e37bc5 | 1256 | printk(KERN_DEBUG " Rx data %pM %pM %02x%02x %pI4\n", |
e174961c | 1257 | &skb->data[0], &skb->data[6], |
0795af57 | 1258 | skb->data[12], skb->data[13], |
a1e37bc5 | 1259 | &skb->data[14]); |
1da177e4 LT |
1260 | #endif |
1261 | skb->protocol = eth_type_trans(skb, dev); | |
1262 | netif_rx(skb); | |
1da177e4 LT |
1263 | np->stats.rx_packets++; |
1264 | np->stats.rx_bytes += pkt_len; | |
1265 | } | |
1266 | entry = (++np->cur_rx) % RX_RING_SIZE; | |
1267 | np->rx_head_desc = &np->rx_ring[entry]; | |
1268 | } | |
1269 | ||
1270 | /* Refill the Rx ring buffers. */ | |
1271 | for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { | |
1272 | struct sk_buff *skb; | |
1273 | entry = np->dirty_rx % RX_RING_SIZE; | |
1274 | if (np->rx_skbuff[entry] == NULL) { | |
1275 | skb = dev_alloc_skb(np->rx_buf_sz); | |
1276 | np->rx_skbuff[entry] = skb; | |
1277 | if (skb == NULL) | |
1278 | break; /* Better luck next round. */ | |
1da177e4 | 1279 | np->rx_addr[entry] = pci_map_single(np->pci_dev, |
689be439 | 1280 | skb->data, |
bb02aacc | 1281 | np->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1282 | np->rx_ring[entry].buffer1 = np->rx_addr[entry]; |
1283 | } | |
1284 | wmb(); | |
42eab567 | 1285 | np->rx_ring[entry].status = DescOwned; |
1da177e4 LT |
1286 | } |
1287 | ||
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | static void netdev_error(struct net_device *dev, int intr_status) | |
1292 | { | |
1293 | struct netdev_private *np = netdev_priv(dev); | |
1294 | void __iomem *ioaddr = np->base_addr; | |
1295 | ||
1296 | if (debug > 2) | |
a1e37bc5 JP |
1297 | printk(KERN_DEBUG "%s: Abnormal event, %08x\n", |
1298 | dev->name, intr_status); | |
1da177e4 LT |
1299 | if (intr_status == 0xffffffff) |
1300 | return; | |
1301 | spin_lock(&np->lock); | |
1302 | if (intr_status & TxFIFOUnderflow) { | |
1303 | int new; | |
1304 | /* Bump up the Tx threshold */ | |
1305 | #if 0 | |
1306 | /* This causes lots of dropped packets, | |
1307 | * and under high load even tx_timeouts | |
1308 | */ | |
1309 | new = np->csr6 + 0x4000; | |
1310 | #else | |
1311 | new = (np->csr6 >> 14)&0x7f; | |
1312 | if (new < 64) | |
1313 | new *= 2; | |
1314 | else | |
1315 | new = 127; /* load full packet before starting */ | |
1316 | new = (np->csr6 & ~(0x7F << 14)) | (new<<14); | |
1317 | #endif | |
a1e37bc5 JP |
1318 | printk(KERN_DEBUG "%s: Tx underflow, new csr6 %08x\n", |
1319 | dev->name, new); | |
1da177e4 LT |
1320 | update_csr6(dev, new); |
1321 | } | |
42eab567 | 1322 | if (intr_status & RxDied) { /* Missed a Rx frame. */ |
1da177e4 LT |
1323 | np->stats.rx_errors++; |
1324 | } | |
1325 | if (intr_status & TimerInt) { | |
1326 | /* Re-enable other interrupts. */ | |
1327 | if (netif_device_present(dev)) | |
1328 | iowrite32(0x1A0F5, ioaddr + IntrEnable); | |
1329 | } | |
1330 | np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff; | |
1331 | iowrite32(0, ioaddr + RxStartDemand); | |
1332 | spin_unlock(&np->lock); | |
1333 | } | |
1334 | ||
1335 | static struct net_device_stats *get_stats(struct net_device *dev) | |
1336 | { | |
1337 | struct netdev_private *np = netdev_priv(dev); | |
1338 | void __iomem *ioaddr = np->base_addr; | |
1339 | ||
1340 | /* The chip only need report frame silently dropped. */ | |
1341 | spin_lock_irq(&np->lock); | |
1342 | if (netif_running(dev) && netif_device_present(dev)) | |
1343 | np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff; | |
1344 | spin_unlock_irq(&np->lock); | |
1345 | ||
1346 | return &np->stats; | |
1347 | } | |
1348 | ||
1349 | ||
1350 | static u32 __set_rx_mode(struct net_device *dev) | |
1351 | { | |
1352 | struct netdev_private *np = netdev_priv(dev); | |
1353 | void __iomem *ioaddr = np->base_addr; | |
1354 | u32 mc_filter[2]; /* Multicast hash filter */ | |
1355 | u32 rx_mode; | |
1356 | ||
1357 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1da177e4 | 1358 | memset(mc_filter, 0xff, sizeof(mc_filter)); |
42eab567 | 1359 | rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys |
1da177e4 | 1360 | | AcceptMyPhys; |
4cd24eaf | 1361 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
8e95a202 | 1362 | (dev->flags & IFF_ALLMULTI)) { |
1da177e4 LT |
1363 | /* Too many to match, or accept all multicasts. */ |
1364 | memset(mc_filter, 0xff, sizeof(mc_filter)); | |
42eab567 | 1365 | rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
1da177e4 | 1366 | } else { |
22bedad3 | 1367 | struct netdev_hw_addr *ha; |
4302b67e | 1368 | |
1da177e4 | 1369 | memset(mc_filter, 0, sizeof(mc_filter)); |
22bedad3 JP |
1370 | netdev_for_each_mc_addr(ha, dev) { |
1371 | int filbit; | |
1372 | ||
1373 | filbit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F; | |
1374 | filbit &= 0x3f; | |
1375 | mc_filter[filbit >> 5] |= 1 << (filbit & 31); | |
1da177e4 | 1376 | } |
42eab567 | 1377 | rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
1da177e4 LT |
1378 | } |
1379 | iowrite32(mc_filter[0], ioaddr + MulticastFilter0); | |
1380 | iowrite32(mc_filter[1], ioaddr + MulticastFilter1); | |
1381 | return rx_mode; | |
1382 | } | |
1383 | ||
1384 | static void set_rx_mode(struct net_device *dev) | |
1385 | { | |
1386 | struct netdev_private *np = netdev_priv(dev); | |
1387 | u32 rx_mode = __set_rx_mode(dev); | |
1388 | spin_lock_irq(&np->lock); | |
1389 | update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode); | |
1390 | spin_unlock_irq(&np->lock); | |
1391 | } | |
1392 | ||
1393 | static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info) | |
1394 | { | |
1395 | struct netdev_private *np = netdev_priv(dev); | |
1396 | ||
1397 | strcpy (info->driver, DRV_NAME); | |
1398 | strcpy (info->version, DRV_VERSION); | |
1399 | strcpy (info->bus_info, pci_name(np->pci_dev)); | |
1400 | } | |
1401 | ||
1402 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1403 | { | |
1404 | struct netdev_private *np = netdev_priv(dev); | |
1405 | int rc; | |
1406 | ||
1407 | spin_lock_irq(&np->lock); | |
1408 | rc = mii_ethtool_gset(&np->mii_if, cmd); | |
1409 | spin_unlock_irq(&np->lock); | |
1410 | ||
1411 | return rc; | |
1412 | } | |
1413 | ||
1414 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1415 | { | |
1416 | struct netdev_private *np = netdev_priv(dev); | |
1417 | int rc; | |
1418 | ||
1419 | spin_lock_irq(&np->lock); | |
1420 | rc = mii_ethtool_sset(&np->mii_if, cmd); | |
1421 | spin_unlock_irq(&np->lock); | |
1422 | ||
1423 | return rc; | |
1424 | } | |
1425 | ||
1426 | static int netdev_nway_reset(struct net_device *dev) | |
1427 | { | |
1428 | struct netdev_private *np = netdev_priv(dev); | |
1429 | return mii_nway_restart(&np->mii_if); | |
1430 | } | |
1431 | ||
1432 | static u32 netdev_get_link(struct net_device *dev) | |
1433 | { | |
1434 | struct netdev_private *np = netdev_priv(dev); | |
1435 | return mii_link_ok(&np->mii_if); | |
1436 | } | |
1437 | ||
1438 | static u32 netdev_get_msglevel(struct net_device *dev) | |
1439 | { | |
1440 | return debug; | |
1441 | } | |
1442 | ||
1443 | static void netdev_set_msglevel(struct net_device *dev, u32 value) | |
1444 | { | |
1445 | debug = value; | |
1446 | } | |
1447 | ||
7282d491 | 1448 | static const struct ethtool_ops netdev_ethtool_ops = { |
1da177e4 LT |
1449 | .get_drvinfo = netdev_get_drvinfo, |
1450 | .get_settings = netdev_get_settings, | |
1451 | .set_settings = netdev_set_settings, | |
1452 | .nway_reset = netdev_nway_reset, | |
1453 | .get_link = netdev_get_link, | |
1454 | .get_msglevel = netdev_get_msglevel, | |
1455 | .set_msglevel = netdev_set_msglevel, | |
1da177e4 LT |
1456 | }; |
1457 | ||
1458 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1459 | { | |
1460 | struct mii_ioctl_data *data = if_mii(rq); | |
1461 | struct netdev_private *np = netdev_priv(dev); | |
1462 | ||
1463 | switch(cmd) { | |
1464 | case SIOCGMIIPHY: /* Get address of MII PHY in use. */ | |
1465 | data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f; | |
1466 | /* Fall Through */ | |
1467 | ||
1468 | case SIOCGMIIREG: /* Read MII PHY register. */ | |
1469 | spin_lock_irq(&np->lock); | |
1470 | data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f); | |
1471 | spin_unlock_irq(&np->lock); | |
1472 | return 0; | |
1473 | ||
1474 | case SIOCSMIIREG: /* Write MII PHY register. */ | |
1da177e4 LT |
1475 | spin_lock_irq(&np->lock); |
1476 | mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); | |
1477 | spin_unlock_irq(&np->lock); | |
1478 | return 0; | |
1479 | default: | |
1480 | return -EOPNOTSUPP; | |
1481 | } | |
1482 | } | |
1483 | ||
1484 | static int netdev_close(struct net_device *dev) | |
1485 | { | |
1486 | struct netdev_private *np = netdev_priv(dev); | |
1487 | void __iomem *ioaddr = np->base_addr; | |
1488 | ||
1489 | netif_stop_queue(dev); | |
1490 | ||
1491 | if (debug > 1) { | |
a1e37bc5 JP |
1492 | printk(KERN_DEBUG "%s: Shutting down ethercard, status was %08x Config %08x\n", |
1493 | dev->name, ioread32(ioaddr + IntrStatus), | |
1494 | ioread32(ioaddr + NetworkConfig)); | |
1495 | printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d\n", | |
1496 | dev->name, | |
1497 | np->cur_tx, np->dirty_tx, | |
1498 | np->cur_rx, np->dirty_rx); | |
1da177e4 LT |
1499 | } |
1500 | ||
1501 | /* Stop the chip's Tx and Rx processes. */ | |
1502 | spin_lock_irq(&np->lock); | |
1503 | netif_device_detach(dev); | |
1504 | update_csr6(dev, 0); | |
1505 | iowrite32(0x0000, ioaddr + IntrEnable); | |
1506 | spin_unlock_irq(&np->lock); | |
1507 | ||
1508 | free_irq(dev->irq, dev); | |
1509 | wmb(); | |
1510 | netif_device_attach(dev); | |
1511 | ||
1512 | if (ioread32(ioaddr + NetworkConfig) != 0xffffffff) | |
1513 | np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff; | |
1514 | ||
1515 | #ifdef __i386__ | |
1516 | if (debug > 2) { | |
1517 | int i; | |
1518 | ||
a1e37bc5 | 1519 | printk(KERN_DEBUG" Tx ring at %08x:\n", (int)np->tx_ring); |
1da177e4 | 1520 | for (i = 0; i < TX_RING_SIZE; i++) |
a1e37bc5 JP |
1521 | printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n", |
1522 | i, np->tx_ring[i].length, | |
1523 | np->tx_ring[i].status, np->tx_ring[i].buffer1); | |
1524 | printk(KERN_DEBUG " Rx ring %08x:\n", (int)np->rx_ring); | |
1da177e4 | 1525 | for (i = 0; i < RX_RING_SIZE; i++) { |
a1e37bc5 JP |
1526 | printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n", |
1527 | i, np->rx_ring[i].length, | |
1528 | np->rx_ring[i].status, np->rx_ring[i].buffer1); | |
1da177e4 LT |
1529 | } |
1530 | } | |
1531 | #endif /* __i386__ debugging only */ | |
1532 | ||
1533 | del_timer_sync(&np->timer); | |
1534 | ||
1535 | free_rxtx_rings(np); | |
1536 | free_ringdesc(np); | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
1541 | static void __devexit w840_remove1 (struct pci_dev *pdev) | |
1542 | { | |
1543 | struct net_device *dev = pci_get_drvdata(pdev); | |
f3b197ac | 1544 | |
1da177e4 LT |
1545 | if (dev) { |
1546 | struct netdev_private *np = netdev_priv(dev); | |
1547 | unregister_netdev(dev); | |
1548 | pci_release_regions(pdev); | |
1549 | pci_iounmap(pdev, np->base_addr); | |
1550 | free_netdev(dev); | |
1551 | } | |
1552 | ||
1553 | pci_set_drvdata(pdev, NULL); | |
1554 | } | |
1555 | ||
1556 | #ifdef CONFIG_PM | |
1557 | ||
1558 | /* | |
1559 | * suspend/resume synchronization: | |
1560 | * - open, close, do_ioctl: | |
1561 | * rtnl_lock, & netif_device_detach after the rtnl_unlock. | |
1562 | * - get_stats: | |
1563 | * spin_lock_irq(np->lock), doesn't touch hw if not present | |
2a97e6b7 | 1564 | * - start_xmit: |
932ff279 | 1565 | * synchronize_irq + netif_tx_disable; |
1da177e4 | 1566 | * - tx_timeout: |
932ff279 | 1567 | * netif_device_detach + netif_tx_disable; |
1da177e4 | 1568 | * - set_multicast_list |
932ff279 | 1569 | * netif_device_detach + netif_tx_disable; |
1da177e4 LT |
1570 | * - interrupt handler |
1571 | * doesn't touch hw if not present, synchronize_irq waits for | |
1572 | * running instances of the interrupt handler. | |
1573 | * | |
1574 | * Disabling hw requires clearing csr6 & IntrEnable. | |
1575 | * update_csr6 & all function that write IntrEnable check netif_device_present | |
1576 | * before settings any bits. | |
1577 | * | |
1578 | * Detach must occur under spin_unlock_irq(), interrupts from a detached | |
1579 | * device would cause an irq storm. | |
1580 | */ | |
05adc3b7 | 1581 | static int w840_suspend (struct pci_dev *pdev, pm_message_t state) |
1da177e4 LT |
1582 | { |
1583 | struct net_device *dev = pci_get_drvdata (pdev); | |
1584 | struct netdev_private *np = netdev_priv(dev); | |
1585 | void __iomem *ioaddr = np->base_addr; | |
1586 | ||
1587 | rtnl_lock(); | |
1588 | if (netif_running (dev)) { | |
1589 | del_timer_sync(&np->timer); | |
1590 | ||
1591 | spin_lock_irq(&np->lock); | |
1592 | netif_device_detach(dev); | |
1593 | update_csr6(dev, 0); | |
1594 | iowrite32(0, ioaddr + IntrEnable); | |
1da177e4 LT |
1595 | spin_unlock_irq(&np->lock); |
1596 | ||
1da177e4 | 1597 | synchronize_irq(dev->irq); |
932ff279 | 1598 | netif_tx_disable(dev); |
6aa20a22 | 1599 | |
1da177e4 LT |
1600 | np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff; |
1601 | ||
1602 | /* no more hardware accesses behind this line. */ | |
1603 | ||
0ee904c3 | 1604 | BUG_ON(np->csr6 || ioread32(ioaddr + IntrEnable)); |
1da177e4 LT |
1605 | |
1606 | /* pci_power_off(pdev, -1); */ | |
1607 | ||
1608 | free_rxtx_rings(np); | |
1609 | } else { | |
1610 | netif_device_detach(dev); | |
1611 | } | |
1612 | rtnl_unlock(); | |
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | static int w840_resume (struct pci_dev *pdev) | |
1617 | { | |
1618 | struct net_device *dev = pci_get_drvdata (pdev); | |
1619 | struct netdev_private *np = netdev_priv(dev); | |
9f486ae1 | 1620 | int retval = 0; |
1da177e4 LT |
1621 | |
1622 | rtnl_lock(); | |
1623 | if (netif_device_present(dev)) | |
1624 | goto out; /* device not suspended */ | |
1625 | if (netif_running(dev)) { | |
9f486ae1 | 1626 | if ((retval = pci_enable_device(pdev))) { |
a1e37bc5 JP |
1627 | dev_err(&dev->dev, |
1628 | "pci_enable_device failed in resume\n"); | |
9f486ae1 VH |
1629 | goto out; |
1630 | } | |
1da177e4 LT |
1631 | spin_lock_irq(&np->lock); |
1632 | iowrite32(1, np->base_addr+PCIBusCfg); | |
1633 | ioread32(np->base_addr+PCIBusCfg); | |
1634 | udelay(1); | |
1635 | netif_device_attach(dev); | |
1636 | init_rxtx_rings(dev); | |
1637 | init_registers(dev); | |
1638 | spin_unlock_irq(&np->lock); | |
1639 | ||
1640 | netif_wake_queue(dev); | |
1641 | ||
1642 | mod_timer(&np->timer, jiffies + 1*HZ); | |
1643 | } else { | |
1644 | netif_device_attach(dev); | |
1645 | } | |
1646 | out: | |
1647 | rtnl_unlock(); | |
9f486ae1 | 1648 | return retval; |
1da177e4 LT |
1649 | } |
1650 | #endif | |
1651 | ||
1652 | static struct pci_driver w840_driver = { | |
1653 | .name = DRV_NAME, | |
1654 | .id_table = w840_pci_tbl, | |
1655 | .probe = w840_probe1, | |
1656 | .remove = __devexit_p(w840_remove1), | |
1657 | #ifdef CONFIG_PM | |
1658 | .suspend = w840_suspend, | |
1659 | .resume = w840_resume, | |
1660 | #endif | |
1661 | }; | |
1662 | ||
1663 | static int __init w840_init(void) | |
1664 | { | |
1665 | printk(version); | |
29917620 | 1666 | return pci_register_driver(&w840_driver); |
1da177e4 LT |
1667 | } |
1668 | ||
1669 | static void __exit w840_exit(void) | |
1670 | { | |
1671 | pci_unregister_driver(&w840_driver); | |
1672 | } | |
1673 | ||
1674 | module_init(w840_init); | |
1675 | module_exit(w840_exit); |