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1da177e4 LT |
1 | /* xircom_tulip_cb.c: A Xircom CBE-100 ethernet driver for Linux. */ |
2 | /* | |
3 | Written/copyright 1994-1999 by Donald Becker. | |
4 | ||
5 | This software may be used and distributed according to the terms | |
6 | of the GNU General Public License, incorporated herein by reference. | |
7 | ||
8 | The author may be reached as becker@scyld.com, or C/O | |
9 | Scyld Computing Corporation | |
10 | 410 Severn Ave., Suite 210 | |
11 | Annapolis MD 21403 | |
12 | ||
1da177e4 LT |
13 | */ |
14 | ||
15 | #define DRV_NAME "xircom_tulip_cb" | |
03a8c661 JG |
16 | #define DRV_VERSION "0.92" |
17 | #define DRV_RELDATE "June 27, 2006" | |
1da177e4 LT |
18 | |
19 | /* A few user-configurable values. */ | |
20 | ||
21 | #define xircom_debug debug | |
22 | #ifdef XIRCOM_DEBUG | |
23 | static int xircom_debug = XIRCOM_DEBUG; | |
24 | #else | |
25 | static int xircom_debug = 1; | |
26 | #endif | |
27 | ||
28 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ | |
29 | static int max_interrupt_work = 25; | |
30 | ||
31 | #define MAX_UNITS 4 | |
32 | /* Used to pass the full-duplex flag, etc. */ | |
33 | static int full_duplex[MAX_UNITS]; | |
34 | static int options[MAX_UNITS]; | |
35 | static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */ | |
36 | ||
37 | /* Keep the ring sizes a power of two for efficiency. | |
38 | Making the Tx ring too large decreases the effectiveness of channel | |
39 | bonding and packet priority. | |
40 | There are no ill effects from too-large receive rings. */ | |
41 | #define TX_RING_SIZE 16 | |
42 | #define RX_RING_SIZE 32 | |
43 | ||
44 | /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */ | |
45 | #ifdef __alpha__ | |
46 | static int rx_copybreak = 1518; | |
47 | #else | |
48 | static int rx_copybreak = 100; | |
49 | #endif | |
50 | ||
51 | /* | |
52 | Set the bus performance register. | |
53 | Typical: Set 16 longword cache alignment, no burst limit. | |
54 | Cache alignment bits 15:14 Burst length 13:8 | |
55 | 0000 No alignment 0x00000000 unlimited 0800 8 longwords | |
56 | 4000 8 longwords 0100 1 longword 1000 16 longwords | |
57 | 8000 16 longwords 0200 2 longwords 2000 32 longwords | |
58 | C000 32 longwords 0400 4 longwords | |
59 | Warning: many older 486 systems are broken and require setting 0x00A04800 | |
60 | 8 longword cache alignment, 8 longword burst. | |
61 | ToDo: Non-Intel setting could be better. | |
62 | */ | |
63 | ||
64 | #if defined(__alpha__) || defined(__ia64__) || defined(__x86_64__) | |
65 | static int csr0 = 0x01A00000 | 0xE000; | |
66 | #elif defined(__powerpc__) | |
67 | static int csr0 = 0x01B00000 | 0x8000; | |
68 | #elif defined(__sparc__) | |
69 | static int csr0 = 0x01B00080 | 0x8000; | |
70 | #elif defined(__i386__) | |
71 | static int csr0 = 0x01A00000 | 0x8000; | |
72 | #else | |
73 | #warning Processor architecture undefined! | |
74 | static int csr0 = 0x00A00000 | 0x4800; | |
75 | #endif | |
76 | ||
77 | /* Operational parameters that usually are not changed. */ | |
78 | /* Time in jiffies before concluding the transmitter is hung. */ | |
79 | #define TX_TIMEOUT (4 * HZ) | |
80 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
81 | #define PKT_SETUP_SZ 192 /* Size of the setup frame */ | |
82 | ||
83 | /* PCI registers */ | |
84 | #define PCI_POWERMGMT 0x40 | |
85 | ||
1da177e4 LT |
86 | #include <linux/module.h> |
87 | #include <linux/moduleparam.h> | |
88 | #include <linux/kernel.h> | |
89 | #include <linux/pci.h> | |
90 | #include <linux/netdevice.h> | |
91 | #include <linux/etherdevice.h> | |
92 | #include <linux/delay.h> | |
93 | #include <linux/init.h> | |
94 | #include <linux/mii.h> | |
95 | #include <linux/ethtool.h> | |
96 | #include <linux/crc32.h> | |
97 | ||
98 | #include <asm/io.h> | |
99 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
100 | #include <asm/uaccess.h> | |
101 | ||
102 | ||
103 | /* These identify the driver base version and may not be removed. */ | |
104 | static char version[] __devinitdata = | |
105 | KERN_INFO DRV_NAME ".c derived from tulip.c:v0.91 4/14/99 becker@scyld.com\n" | |
106 | KERN_INFO " unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE "\n"; | |
107 | ||
108 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
109 | MODULE_DESCRIPTION("Xircom CBE-100 ethernet driver"); | |
110 | MODULE_LICENSE("GPL v2"); | |
111 | MODULE_VERSION(DRV_VERSION); | |
112 | ||
113 | module_param(debug, int, 0); | |
114 | module_param(max_interrupt_work, int, 0); | |
115 | module_param(rx_copybreak, int, 0); | |
116 | module_param(csr0, int, 0); | |
117 | ||
118 | module_param_array(options, int, NULL, 0); | |
119 | module_param_array(full_duplex, int, NULL, 0); | |
120 | ||
121 | #define RUN_AT(x) (jiffies + (x)) | |
122 | ||
123 | /* | |
124 | Theory of Operation | |
125 | ||
126 | I. Board Compatibility | |
127 | ||
128 | This device driver was forked from the driver for the DECchip "Tulip", | |
129 | Digital's single-chip ethernet controllers for PCI. It supports Xircom's | |
130 | almost-Tulip-compatible CBE-100 CardBus adapters. | |
131 | ||
132 | II. Board-specific settings | |
133 | ||
134 | PCI bus devices are configured by the system at boot time, so no jumpers | |
135 | need to be set on the board. The system BIOS preferably should assign the | |
136 | PCI INTA signal to an otherwise unused system IRQ line. | |
137 | ||
138 | III. Driver operation | |
139 | ||
140 | IIIa. Ring buffers | |
141 | ||
142 | The Xircom can use either ring buffers or lists of Tx and Rx descriptors. | |
143 | This driver uses statically allocated rings of Rx and Tx descriptors, set at | |
144 | compile time by RX/TX_RING_SIZE. This version of the driver allocates skbuffs | |
145 | for the Rx ring buffers at open() time and passes the skb->data field to the | |
146 | Xircom as receive data buffers. When an incoming frame is less than | |
147 | RX_COPYBREAK bytes long, a fresh skbuff is allocated and the frame is | |
148 | copied to the new skbuff. When the incoming frame is larger, the skbuff is | |
149 | passed directly up the protocol stack and replaced by a newly allocated | |
150 | skbuff. | |
151 | ||
152 | The RX_COPYBREAK value is chosen to trade-off the memory wasted by | |
153 | using a full-sized skbuff for small frames vs. the copying costs of larger | |
154 | frames. For small frames the copying cost is negligible (esp. considering | |
155 | that we are pre-loading the cache with immediately useful header | |
156 | information). For large frames the copying cost is non-trivial, and the | |
157 | larger copy might flush the cache of useful data. A subtle aspect of this | |
158 | choice is that the Xircom only receives into longword aligned buffers, thus | |
159 | the IP header at offset 14 isn't longword aligned for further processing. | |
160 | Copied frames are put into the new skbuff at an offset of "+2", thus copying | |
161 | has the beneficial effect of aligning the IP header and preloading the | |
162 | cache. | |
163 | ||
164 | IIIC. Synchronization | |
165 | The driver runs as two independent, single-threaded flows of control. One | |
166 | is the send-packet routine, which enforces single-threaded use by the | |
167 | dev->tbusy flag. The other thread is the interrupt handler, which is single | |
168 | threaded by the hardware and other software. | |
169 | ||
170 | The send packet thread has partial control over the Tx ring and 'dev->tbusy' | |
171 | flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next | |
172 | queue slot is empty, it clears the tbusy flag when finished otherwise it sets | |
173 | the 'tp->tx_full' flag. | |
174 | ||
175 | The interrupt handler has exclusive control over the Rx ring and records stats | |
176 | from the Tx ring. (The Tx-done interrupt can't be selectively turned off, so | |
177 | we can't avoid the interrupt overhead by having the Tx routine reap the Tx | |
178 | stats.) After reaping the stats, it marks the queue entry as empty by setting | |
179 | the 'base' to zero. Iff the 'tp->tx_full' flag is set, it clears both the | |
180 | tx_full and tbusy flags. | |
181 | ||
182 | IV. Notes | |
183 | ||
184 | IVb. References | |
185 | ||
186 | http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html | |
187 | http://www.digital.com (search for current 21*4* datasheets and "21X4 SROM") | |
188 | http://www.national.com/pf/DP/DP83840A.html | |
189 | ||
190 | IVc. Errata | |
191 | ||
192 | */ | |
193 | ||
194 | /* A full-duplex map for media types. */ | |
195 | enum MediaIs { | |
196 | MediaIsFD = 1, MediaAlwaysFD=2, MediaIsMII=4, MediaIsFx=8, | |
197 | MediaIs100=16}; | |
198 | static const char media_cap[] = | |
199 | {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20 }; | |
200 | ||
201 | /* Offsets to the Command and Status Registers, "CSRs". All accesses | |
202 | must be longword instructions and quadword aligned. */ | |
203 | enum xircom_offsets { | |
204 | CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, | |
205 | CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58, | |
206 | CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x04, }; | |
207 | ||
208 | /* The bits in the CSR5 status registers, mostly interrupt sources. */ | |
209 | enum status_bits { | |
210 | LinkChange=0x08000000, | |
211 | NormalIntr=0x10000, NormalIntrMask=0x00014045, | |
212 | AbnormalIntr=0x8000, AbnormalIntrMask=0x0a00a5a2, | |
213 | ReservedIntrMask=0xe0001a18, | |
214 | EarlyRxIntr=0x4000, BusErrorIntr=0x2000, | |
215 | EarlyTxIntr=0x400, RxDied=0x100, RxNoBuf=0x80, RxIntr=0x40, | |
216 | TxFIFOUnderflow=0x20, TxNoBuf=0x04, TxDied=0x02, TxIntr=0x01, | |
217 | }; | |
218 | ||
219 | enum csr0_control_bits { | |
220 | EnableMWI=0x01000000, EnableMRL=0x00800000, | |
221 | EnableMRM=0x00200000, EqualBusPrio=0x02, | |
222 | SoftwareReset=0x01, | |
223 | }; | |
224 | ||
225 | enum csr6_control_bits { | |
226 | ReceiveAllBit=0x40000000, AllMultiBit=0x80, PromiscBit=0x40, | |
227 | HashFilterBit=0x01, FullDuplexBit=0x0200, | |
228 | TxThresh10=0x400000, TxStoreForw=0x200000, | |
229 | TxThreshMask=0xc000, TxThreshShift=14, | |
230 | EnableTx=0x2000, EnableRx=0x02, | |
231 | ReservedZeroMask=0x8d930134, ReservedOneMask=0x320c0000, | |
232 | EnableTxRx=(EnableTx | EnableRx), | |
233 | }; | |
234 | ||
235 | ||
236 | enum tbl_flag { | |
237 | HAS_MII=1, HAS_ACPI=2, | |
238 | }; | |
239 | static struct xircom_chip_table { | |
240 | char *chip_name; | |
241 | int valid_intrs; /* CSR7 interrupt enable settings */ | |
242 | int flags; | |
243 | } xircom_tbl[] = { | |
244 | { "Xircom Cardbus Adapter", | |
245 | LinkChange | NormalIntr | AbnormalIntr | BusErrorIntr | | |
246 | RxDied | RxNoBuf | RxIntr | TxFIFOUnderflow | TxNoBuf | TxDied | TxIntr, | |
247 | HAS_MII | HAS_ACPI, }, | |
248 | { NULL, }, | |
249 | }; | |
250 | /* This matches the table above. */ | |
251 | enum chips { | |
252 | X3201_3, | |
253 | }; | |
254 | ||
255 | ||
256 | /* The Xircom Rx and Tx buffer descriptors. */ | |
257 | struct xircom_rx_desc { | |
258 | s32 status; | |
259 | s32 length; | |
260 | u32 buffer1, buffer2; | |
261 | }; | |
262 | ||
263 | struct xircom_tx_desc { | |
264 | s32 status; | |
265 | s32 length; | |
266 | u32 buffer1, buffer2; /* We use only buffer 1. */ | |
267 | }; | |
268 | ||
269 | enum tx_desc0_status_bits { | |
270 | Tx0DescOwned=0x80000000, Tx0DescError=0x8000, Tx0NoCarrier=0x0800, | |
271 | Tx0LateColl=0x0200, Tx0ManyColl=0x0100, Tx0Underflow=0x02, | |
272 | }; | |
273 | enum tx_desc1_status_bits { | |
274 | Tx1ComplIntr=0x80000000, Tx1LastSeg=0x40000000, Tx1FirstSeg=0x20000000, | |
275 | Tx1SetupPkt=0x08000000, Tx1DisableCRC=0x04000000, Tx1RingWrap=0x02000000, | |
276 | Tx1ChainDesc=0x01000000, Tx1NoPad=0x800000, Tx1HashSetup=0x400000, | |
277 | Tx1WholePkt=(Tx1FirstSeg | Tx1LastSeg), | |
278 | }; | |
279 | enum rx_desc0_status_bits { | |
280 | Rx0DescOwned=0x80000000, Rx0DescError=0x8000, Rx0NoSpace=0x4000, | |
281 | Rx0Runt=0x0800, Rx0McastPkt=0x0400, Rx0FirstSeg=0x0200, Rx0LastSeg=0x0100, | |
282 | Rx0HugeFrame=0x80, Rx0CRCError=0x02, | |
283 | Rx0WholePkt=(Rx0FirstSeg | Rx0LastSeg), | |
284 | }; | |
285 | enum rx_desc1_status_bits { | |
286 | Rx1RingWrap=0x02000000, Rx1ChainDesc=0x01000000, | |
287 | }; | |
288 | ||
289 | struct xircom_private { | |
290 | struct xircom_rx_desc rx_ring[RX_RING_SIZE]; | |
291 | struct xircom_tx_desc tx_ring[TX_RING_SIZE]; | |
292 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ | |
293 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
03a8c661 | 294 | |
1da177e4 LT |
295 | /* The X3201-3 requires 4-byte aligned tx bufs */ |
296 | struct sk_buff* tx_aligned_skbuff[TX_RING_SIZE]; | |
03a8c661 | 297 | |
1da177e4 LT |
298 | /* The addresses of receive-in-place skbuffs. */ |
299 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; | |
300 | u16 setup_frame[PKT_SETUP_SZ / sizeof(u16)]; /* Pseudo-Tx frame to init address table. */ | |
301 | int chip_id; | |
302 | struct net_device_stats stats; | |
303 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ | |
304 | unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ | |
305 | unsigned int tx_full:1; /* The Tx queue is full. */ | |
306 | unsigned int speed100:1; | |
307 | unsigned int full_duplex:1; /* Full-duplex operation requested. */ | |
308 | unsigned int autoneg:1; | |
309 | unsigned int default_port:4; /* Last dev->if_port value. */ | |
310 | unsigned int open:1; | |
311 | unsigned int csr0; /* CSR0 setting. */ | |
312 | unsigned int csr6; /* Current CSR6 control settings. */ | |
313 | u16 to_advertise; /* NWay capabilities advertised. */ | |
314 | u16 advertising[4]; | |
315 | signed char phys[4], mii_cnt; /* MII device addresses. */ | |
316 | int saved_if_port; | |
317 | struct pci_dev *pdev; | |
318 | spinlock_t lock; | |
319 | }; | |
320 | ||
321 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
322 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value); | |
323 | static void xircom_up(struct net_device *dev); | |
324 | static void xircom_down(struct net_device *dev); | |
325 | static int xircom_open(struct net_device *dev); | |
326 | static void xircom_tx_timeout(struct net_device *dev); | |
327 | static void xircom_init_ring(struct net_device *dev); | |
328 | static int xircom_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
329 | static int xircom_rx(struct net_device *dev); | |
330 | static void xircom_media_change(struct net_device *dev); | |
331 | static irqreturn_t xircom_interrupt(int irq, void *dev_instance, struct pt_regs *regs); | |
332 | static int xircom_close(struct net_device *dev); | |
333 | static struct net_device_stats *xircom_get_stats(struct net_device *dev); | |
334 | static int xircom_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
335 | static void set_rx_mode(struct net_device *dev); | |
336 | static void check_duplex(struct net_device *dev); | |
7282d491 | 337 | static const struct ethtool_ops ops; |
1da177e4 LT |
338 | |
339 | ||
340 | /* The Xircom cards are picky about when certain bits in CSR6 can be | |
341 | manipulated. Keith Owens <kaos@ocs.com.au>. */ | |
342 | static void outl_CSR6(u32 newcsr6, long ioaddr) | |
343 | { | |
344 | const int strict_bits = | |
345 | TxThresh10 | TxStoreForw | TxThreshMask | EnableTxRx | FullDuplexBit; | |
346 | int csr5, csr5_22_20, csr5_19_17, currcsr6, attempts = 200; | |
347 | unsigned long flags; | |
348 | save_flags(flags); | |
349 | cli(); | |
350 | /* mask out the reserved bits that always read 0 on the Xircom cards */ | |
351 | newcsr6 &= ~ReservedZeroMask; | |
352 | /* or in the reserved bits that always read 1 */ | |
353 | newcsr6 |= ReservedOneMask; | |
354 | currcsr6 = inl(ioaddr + CSR6); | |
355 | if (((newcsr6 & strict_bits) == (currcsr6 & strict_bits)) || | |
356 | ((currcsr6 & ~EnableTxRx) == 0)) { | |
357 | outl(newcsr6, ioaddr + CSR6); /* safe */ | |
358 | restore_flags(flags); | |
359 | return; | |
360 | } | |
361 | /* make sure the transmitter and receiver are stopped first */ | |
362 | currcsr6 &= ~EnableTxRx; | |
363 | while (1) { | |
364 | csr5 = inl(ioaddr + CSR5); | |
365 | if (csr5 == 0xffffffff) | |
366 | break; /* cannot read csr5, card removed? */ | |
367 | csr5_22_20 = csr5 & 0x700000; | |
368 | csr5_19_17 = csr5 & 0x0e0000; | |
369 | if ((csr5_22_20 == 0 || csr5_22_20 == 0x600000) && | |
370 | (csr5_19_17 == 0 || csr5_19_17 == 0x80000 || csr5_19_17 == 0xc0000)) | |
371 | break; /* both are stopped or suspended */ | |
372 | if (!--attempts) { | |
373 | printk(KERN_INFO DRV_NAME ": outl_CSR6 too many attempts," | |
374 | "csr5=0x%08x\n", csr5); | |
375 | outl(newcsr6, ioaddr + CSR6); /* unsafe but do it anyway */ | |
376 | restore_flags(flags); | |
377 | return; | |
378 | } | |
379 | outl(currcsr6, ioaddr + CSR6); | |
380 | udelay(1); | |
381 | } | |
382 | /* now it is safe to change csr6 */ | |
383 | outl(newcsr6, ioaddr + CSR6); | |
384 | restore_flags(flags); | |
385 | } | |
386 | ||
387 | ||
388 | static void __devinit read_mac_address(struct net_device *dev) | |
389 | { | |
390 | long ioaddr = dev->base_addr; | |
391 | int i, j; | |
392 | unsigned char tuple, link, data_id, data_count; | |
393 | ||
394 | /* Xircom has its address stored in the CIS; | |
395 | * we access it through the boot rom interface for now | |
396 | * this might not work, as the CIS is not parsed but I | |
397 | * (danilo) use the offset I found on my card's CIS !!! | |
398 | * | |
399 | * Doug Ledford: I changed this routine around so that it | |
400 | * walks the CIS memory space, parsing the config items, and | |
401 | * finds the proper lan_node_id tuple and uses the data | |
402 | * stored there. | |
403 | */ | |
404 | outl(1 << 12, ioaddr + CSR9); /* enable boot rom access */ | |
405 | for (i = 0x100; i < 0x1f7; i += link+2) { | |
406 | outl(i, ioaddr + CSR10); | |
407 | tuple = inl(ioaddr + CSR9) & 0xff; | |
408 | outl(i + 1, ioaddr + CSR10); | |
409 | link = inl(ioaddr + CSR9) & 0xff; | |
410 | outl(i + 2, ioaddr + CSR10); | |
411 | data_id = inl(ioaddr + CSR9) & 0xff; | |
412 | outl(i + 3, ioaddr + CSR10); | |
413 | data_count = inl(ioaddr + CSR9) & 0xff; | |
414 | if ( (tuple == 0x22) && | |
415 | (data_id == 0x04) && (data_count == 0x06) ) { | |
416 | /* | |
417 | * This is it. We have the data we want. | |
418 | */ | |
419 | for (j = 0; j < 6; j++) { | |
420 | outl(i + j + 4, ioaddr + CSR10); | |
421 | dev->dev_addr[j] = inl(ioaddr + CSR9) & 0xff; | |
422 | } | |
423 | break; | |
424 | } else if (link == 0) { | |
425 | break; | |
426 | } | |
427 | } | |
428 | } | |
429 | ||
430 | ||
431 | /* | |
432 | * locate the MII interfaces and initialize them. | |
433 | * we disable full-duplex modes here, | |
434 | * because we don't know how to handle them. | |
435 | */ | |
436 | static void find_mii_transceivers(struct net_device *dev) | |
437 | { | |
438 | struct xircom_private *tp = netdev_priv(dev); | |
439 | int phy, phy_idx; | |
440 | ||
441 | if (media_cap[tp->default_port] & MediaIsMII) { | |
442 | u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 }; | |
443 | tp->to_advertise = media2advert[tp->default_port - 9]; | |
444 | } else | |
445 | tp->to_advertise = | |
446 | /*ADVERTISE_100BASE4 | ADVERTISE_100FULL |*/ ADVERTISE_100HALF | | |
447 | /*ADVERTISE_10FULL |*/ ADVERTISE_10HALF | ADVERTISE_CSMA; | |
448 | ||
449 | /* Find the connected MII xcvrs. | |
450 | Doing this in open() would allow detecting external xcvrs later, | |
451 | but takes much time. */ | |
452 | for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) { | |
453 | int mii_status = mdio_read(dev, phy, MII_BMSR); | |
454 | if ((mii_status & (BMSR_100BASE4 | BMSR_100HALF | BMSR_10HALF)) == BMSR_100BASE4 || | |
455 | ((mii_status & BMSR_100BASE4) == 0 && | |
456 | (mii_status & (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | BMSR_10HALF)) != 0)) { | |
457 | int mii_reg0 = mdio_read(dev, phy, MII_BMCR); | |
458 | int mii_advert = mdio_read(dev, phy, MII_ADVERTISE); | |
459 | int reg4 = ((mii_status >> 6) & tp->to_advertise) | ADVERTISE_CSMA; | |
460 | tp->phys[phy_idx] = phy; | |
461 | tp->advertising[phy_idx++] = reg4; | |
462 | printk(KERN_INFO "%s: MII transceiver #%d " | |
463 | "config %4.4x status %4.4x advertising %4.4x.\n", | |
464 | dev->name, phy, mii_reg0, mii_status, mii_advert); | |
465 | } | |
466 | } | |
467 | tp->mii_cnt = phy_idx; | |
468 | if (phy_idx == 0) { | |
469 | printk(KERN_INFO "%s: ***WARNING***: No MII transceiver found!\n", | |
470 | dev->name); | |
471 | tp->phys[0] = 0; | |
472 | } | |
473 | } | |
474 | ||
475 | ||
476 | /* | |
477 | * To quote Arjan van de Ven: | |
478 | * transceiver_voodoo() enables the external UTP plug thingy. | |
479 | * it's called voodoo as I stole this code and cannot cross-reference | |
480 | * it with the specification. | |
481 | * Actually it seems to go like this: | |
482 | * - GPIO2 enables the MII itself so we can talk to it. The MII gets reset | |
483 | * so any prior MII settings are lost. | |
484 | * - GPIO0 enables the TP port so the MII can talk to the network. | |
485 | * - a software reset will reset both GPIO pins. | |
486 | * I also moved the software reset here, because doing it in xircom_up() | |
487 | * required enabling the GPIO pins each time, which reset the MII each time. | |
488 | * Thus we couldn't control the MII -- which sucks because we don't know | |
489 | * how to handle full-duplex modes so we *must* disable them. | |
490 | */ | |
491 | static void transceiver_voodoo(struct net_device *dev) | |
492 | { | |
493 | struct xircom_private *tp = netdev_priv(dev); | |
494 | long ioaddr = dev->base_addr; | |
495 | ||
496 | /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ | |
497 | outl(SoftwareReset, ioaddr + CSR0); | |
498 | udelay(2); | |
499 | ||
500 | /* Deassert reset. */ | |
501 | outl(tp->csr0, ioaddr + CSR0); | |
502 | ||
503 | /* Reset the xcvr interface and turn on heartbeat. */ | |
504 | outl(0x0008, ioaddr + CSR15); | |
505 | udelay(5); /* The delays are Xircom-recommended to give the | |
506 | * chipset time to reset the actual hardware | |
507 | * on the PCMCIA card | |
508 | */ | |
509 | outl(0xa8050000, ioaddr + CSR15); | |
510 | udelay(5); | |
511 | outl(0xa00f0000, ioaddr + CSR15); | |
512 | udelay(5); | |
513 | ||
514 | outl_CSR6(0, ioaddr); | |
515 | //outl_CSR6(FullDuplexBit, ioaddr); | |
516 | } | |
517 | ||
518 | ||
519 | static int __devinit xircom_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |
520 | { | |
521 | struct net_device *dev; | |
522 | struct xircom_private *tp; | |
523 | static int board_idx = -1; | |
524 | int chip_idx = id->driver_data; | |
525 | long ioaddr; | |
526 | int i; | |
527 | u8 chip_rev; | |
528 | ||
529 | /* when built into the kernel, we only print version if device is found */ | |
530 | #ifndef MODULE | |
531 | static int printed_version; | |
532 | if (!printed_version++) | |
533 | printk(version); | |
534 | #endif | |
535 | ||
536 | //printk(KERN_INFO "xircom_init_one(%s)\n", pci_name(pdev)); | |
537 | ||
538 | board_idx++; | |
539 | ||
540 | if (pci_enable_device(pdev)) | |
541 | return -ENODEV; | |
542 | ||
543 | pci_set_master(pdev); | |
544 | ||
545 | ioaddr = pci_resource_start(pdev, 0); | |
546 | dev = alloc_etherdev(sizeof(*tp)); | |
547 | if (!dev) { | |
548 | printk (KERN_ERR DRV_NAME "%d: cannot alloc etherdev, aborting\n", board_idx); | |
549 | return -ENOMEM; | |
550 | } | |
551 | SET_MODULE_OWNER(dev); | |
552 | SET_NETDEV_DEV(dev, &pdev->dev); | |
553 | ||
554 | dev->base_addr = ioaddr; | |
555 | dev->irq = pdev->irq; | |
556 | ||
557 | if (pci_request_regions(pdev, dev->name)) { | |
558 | printk (KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", board_idx); | |
559 | goto err_out_free_netdev; | |
560 | } | |
561 | ||
562 | /* Bring the chip out of sleep mode. | |
563 | Caution: Snooze mode does not work with some boards! */ | |
564 | if (xircom_tbl[chip_idx].flags & HAS_ACPI) | |
565 | pci_write_config_dword(pdev, PCI_POWERMGMT, 0); | |
566 | ||
567 | /* Stop the chip's Tx and Rx processes. */ | |
568 | outl_CSR6(inl(ioaddr + CSR6) & ~EnableTxRx, ioaddr); | |
569 | /* Clear the missed-packet counter. */ | |
570 | (volatile int)inl(ioaddr + CSR8); | |
571 | ||
572 | tp = netdev_priv(dev); | |
573 | ||
574 | spin_lock_init(&tp->lock); | |
575 | tp->pdev = pdev; | |
576 | tp->chip_id = chip_idx; | |
577 | /* BugFixes: The 21143-TD hangs with PCI Write-and-Invalidate cycles. */ | |
578 | /* XXX: is this necessary for Xircom? */ | |
579 | tp->csr0 = csr0 & ~EnableMWI; | |
580 | ||
581 | pci_set_drvdata(pdev, dev); | |
582 | ||
583 | /* The lower four bits are the media type. */ | |
584 | if (board_idx >= 0 && board_idx < MAX_UNITS) { | |
585 | tp->default_port = options[board_idx] & 15; | |
586 | if ((options[board_idx] & 0x90) || full_duplex[board_idx] > 0) | |
587 | tp->full_duplex = 1; | |
588 | if (mtu[board_idx] > 0) | |
589 | dev->mtu = mtu[board_idx]; | |
590 | } | |
591 | if (dev->mem_start) | |
592 | tp->default_port = dev->mem_start; | |
593 | if (tp->default_port) { | |
594 | if (media_cap[tp->default_port] & MediaAlwaysFD) | |
595 | tp->full_duplex = 1; | |
596 | } | |
597 | if (tp->full_duplex) | |
598 | tp->autoneg = 0; | |
599 | else | |
600 | tp->autoneg = 1; | |
601 | tp->speed100 = 1; | |
602 | ||
603 | /* The Xircom-specific entries in the device structure. */ | |
604 | dev->open = &xircom_open; | |
605 | dev->hard_start_xmit = &xircom_start_xmit; | |
606 | dev->stop = &xircom_close; | |
607 | dev->get_stats = &xircom_get_stats; | |
608 | dev->do_ioctl = &xircom_ioctl; | |
609 | #ifdef HAVE_MULTICAST | |
610 | dev->set_multicast_list = &set_rx_mode; | |
611 | #endif | |
612 | dev->tx_timeout = xircom_tx_timeout; | |
613 | dev->watchdog_timeo = TX_TIMEOUT; | |
614 | SET_ETHTOOL_OPS(dev, &ops); | |
615 | ||
616 | transceiver_voodoo(dev); | |
617 | ||
618 | read_mac_address(dev); | |
619 | ||
620 | if (register_netdev(dev)) | |
621 | goto err_out_cleardev; | |
622 | ||
623 | pci_read_config_byte(pdev, PCI_REVISION_ID, &chip_rev); | |
624 | printk(KERN_INFO "%s: %s rev %d at %#3lx,", | |
625 | dev->name, xircom_tbl[chip_idx].chip_name, chip_rev, ioaddr); | |
626 | for (i = 0; i < 6; i++) | |
627 | printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]); | |
628 | printk(", IRQ %d.\n", dev->irq); | |
629 | ||
630 | if (xircom_tbl[chip_idx].flags & HAS_MII) { | |
631 | find_mii_transceivers(dev); | |
632 | check_duplex(dev); | |
633 | } | |
634 | ||
635 | return 0; | |
636 | ||
637 | err_out_cleardev: | |
638 | pci_set_drvdata(pdev, NULL); | |
639 | pci_release_regions(pdev); | |
640 | err_out_free_netdev: | |
641 | free_netdev(dev); | |
642 | return -ENODEV; | |
643 | } | |
644 | ||
645 | ||
646 | /* MII transceiver control section. | |
647 | Read and write the MII registers using software-generated serial | |
648 | MDIO protocol. See the MII specifications or DP83840A data sheet | |
649 | for details. */ | |
650 | ||
651 | /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually | |
652 | met by back-to-back PCI I/O cycles, but we insert a delay to avoid | |
653 | "overclocking" issues or future 66Mhz PCI. */ | |
654 | #define mdio_delay() inl(mdio_addr) | |
655 | ||
656 | /* Read and write the MII registers using software-generated serial | |
657 | MDIO protocol. It is just different enough from the EEPROM protocol | |
658 | to not share code. The maxium data clock rate is 2.5 Mhz. */ | |
659 | #define MDIO_SHIFT_CLK 0x10000 | |
660 | #define MDIO_DATA_WRITE0 0x00000 | |
661 | #define MDIO_DATA_WRITE1 0x20000 | |
662 | #define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */ | |
663 | #define MDIO_ENB_IN 0x40000 | |
664 | #define MDIO_DATA_READ 0x80000 | |
665 | ||
666 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
667 | { | |
668 | int i; | |
669 | int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; | |
670 | int retval = 0; | |
671 | long ioaddr = dev->base_addr; | |
672 | long mdio_addr = ioaddr + CSR9; | |
673 | ||
674 | /* Establish sync by sending at least 32 logic ones. */ | |
675 | for (i = 32; i >= 0; i--) { | |
676 | outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); | |
677 | mdio_delay(); | |
678 | outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); | |
679 | mdio_delay(); | |
680 | } | |
681 | /* Shift the read command bits out. */ | |
682 | for (i = 15; i >= 0; i--) { | |
683 | int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0; | |
684 | ||
685 | outl(MDIO_ENB | dataval, mdio_addr); | |
686 | mdio_delay(); | |
687 | outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr); | |
688 | mdio_delay(); | |
689 | } | |
690 | /* Read the two transition, 16 data, and wire-idle bits. */ | |
691 | for (i = 19; i > 0; i--) { | |
692 | outl(MDIO_ENB_IN, mdio_addr); | |
693 | mdio_delay(); | |
694 | retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0); | |
695 | outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); | |
696 | mdio_delay(); | |
697 | } | |
698 | return (retval>>1) & 0xffff; | |
699 | } | |
700 | ||
701 | ||
702 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | |
703 | { | |
704 | int i; | |
705 | int cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; | |
706 | long ioaddr = dev->base_addr; | |
707 | long mdio_addr = ioaddr + CSR9; | |
708 | ||
709 | /* Establish sync by sending 32 logic ones. */ | |
710 | for (i = 32; i >= 0; i--) { | |
711 | outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); | |
712 | mdio_delay(); | |
713 | outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); | |
714 | mdio_delay(); | |
715 | } | |
716 | /* Shift the command bits out. */ | |
717 | for (i = 31; i >= 0; i--) { | |
718 | int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0; | |
719 | outl(MDIO_ENB | dataval, mdio_addr); | |
720 | mdio_delay(); | |
721 | outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr); | |
722 | mdio_delay(); | |
723 | } | |
724 | /* Clear out extra bits. */ | |
725 | for (i = 2; i > 0; i--) { | |
726 | outl(MDIO_ENB_IN, mdio_addr); | |
727 | mdio_delay(); | |
728 | outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); | |
729 | mdio_delay(); | |
730 | } | |
731 | return; | |
732 | } | |
733 | ||
734 | ||
735 | static void | |
736 | xircom_up(struct net_device *dev) | |
737 | { | |
738 | struct xircom_private *tp = netdev_priv(dev); | |
739 | long ioaddr = dev->base_addr; | |
740 | int i; | |
741 | ||
742 | xircom_init_ring(dev); | |
743 | /* Clear the tx ring */ | |
744 | for (i = 0; i < TX_RING_SIZE; i++) { | |
745 | tp->tx_skbuff[i] = NULL; | |
746 | tp->tx_ring[i].status = 0; | |
747 | } | |
748 | ||
749 | if (xircom_debug > 1) | |
750 | printk(KERN_DEBUG "%s: xircom_up() irq %d.\n", dev->name, dev->irq); | |
751 | ||
752 | outl(virt_to_bus(tp->rx_ring), ioaddr + CSR3); | |
753 | outl(virt_to_bus(tp->tx_ring), ioaddr + CSR4); | |
754 | ||
755 | tp->saved_if_port = dev->if_port; | |
756 | if (dev->if_port == 0) | |
757 | dev->if_port = tp->default_port; | |
758 | ||
759 | tp->csr6 = TxThresh10 /*| FullDuplexBit*/; /* XXX: why 10 and not 100? */ | |
760 | ||
761 | set_rx_mode(dev); | |
762 | ||
763 | /* Start the chip's Tx to process setup frame. */ | |
764 | outl_CSR6(tp->csr6, ioaddr); | |
765 | outl_CSR6(tp->csr6 | EnableTx, ioaddr); | |
766 | ||
767 | /* Acknowledge all outstanding interrupts sources */ | |
768 | outl(xircom_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); | |
769 | /* Enable interrupts by setting the interrupt mask. */ | |
770 | outl(xircom_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7); | |
771 | /* Enable Rx */ | |
772 | outl_CSR6(tp->csr6 | EnableTxRx, ioaddr); | |
773 | /* Rx poll demand */ | |
774 | outl(0, ioaddr + CSR2); | |
775 | ||
776 | /* Tell the net layer we're ready */ | |
777 | netif_start_queue (dev); | |
778 | ||
779 | /* Check current media state */ | |
780 | xircom_media_change(dev); | |
781 | ||
782 | if (xircom_debug > 2) { | |
783 | printk(KERN_DEBUG "%s: Done xircom_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n", | |
784 | dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5), | |
785 | inl(ioaddr + CSR6)); | |
786 | } | |
787 | } | |
788 | ||
789 | ||
790 | static int | |
791 | xircom_open(struct net_device *dev) | |
792 | { | |
793 | struct xircom_private *tp = netdev_priv(dev); | |
794 | ||
1fb9df5d | 795 | if (request_irq(dev->irq, &xircom_interrupt, IRQF_SHARED, dev->name, dev)) |
1da177e4 LT |
796 | return -EAGAIN; |
797 | ||
798 | xircom_up(dev); | |
799 | tp->open = 1; | |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
804 | ||
805 | static void xircom_tx_timeout(struct net_device *dev) | |
806 | { | |
807 | struct xircom_private *tp = netdev_priv(dev); | |
808 | long ioaddr = dev->base_addr; | |
809 | ||
810 | if (media_cap[dev->if_port] & MediaIsMII) { | |
811 | /* Do nothing -- the media monitor should handle this. */ | |
812 | if (xircom_debug > 1) | |
813 | printk(KERN_WARNING "%s: Transmit timeout using MII device.\n", | |
814 | dev->name); | |
815 | } | |
816 | ||
817 | #if defined(way_too_many_messages) | |
818 | if (xircom_debug > 3) { | |
819 | int i; | |
820 | for (i = 0; i < RX_RING_SIZE; i++) { | |
821 | u8 *buf = (u8 *)(tp->rx_ring[i].buffer1); | |
822 | int j; | |
823 | printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x " | |
824 | "%2.2x %2.2x %2.2x.\n", | |
825 | i, (unsigned int)tp->rx_ring[i].status, | |
826 | (unsigned int)tp->rx_ring[i].length, | |
827 | (unsigned int)tp->rx_ring[i].buffer1, | |
828 | (unsigned int)tp->rx_ring[i].buffer2, | |
829 | buf[0], buf[1], buf[2]); | |
830 | for (j = 0; buf[j] != 0xee && j < 1600; j++) | |
831 | if (j < 100) printk(" %2.2x", buf[j]); | |
832 | printk(" j=%d.\n", j); | |
833 | } | |
834 | printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring); | |
835 | for (i = 0; i < RX_RING_SIZE; i++) | |
836 | printk(" %8.8x", (unsigned int)tp->rx_ring[i].status); | |
837 | printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring); | |
838 | for (i = 0; i < TX_RING_SIZE; i++) | |
839 | printk(" %8.8x", (unsigned int)tp->tx_ring[i].status); | |
840 | printk("\n"); | |
841 | } | |
842 | #endif | |
843 | ||
844 | /* Stop and restart the chip's Tx/Rx processes . */ | |
845 | outl_CSR6(tp->csr6 | EnableRx, ioaddr); | |
846 | outl_CSR6(tp->csr6 | EnableTxRx, ioaddr); | |
847 | /* Trigger an immediate transmit demand. */ | |
848 | outl(0, ioaddr + CSR1); | |
849 | ||
850 | dev->trans_start = jiffies; | |
851 | netif_wake_queue (dev); | |
852 | tp->stats.tx_errors++; | |
853 | } | |
854 | ||
855 | ||
856 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
857 | static void xircom_init_ring(struct net_device *dev) | |
858 | { | |
859 | struct xircom_private *tp = netdev_priv(dev); | |
860 | int i; | |
861 | ||
862 | tp->tx_full = 0; | |
863 | tp->cur_rx = tp->cur_tx = 0; | |
864 | tp->dirty_rx = tp->dirty_tx = 0; | |
865 | ||
866 | for (i = 0; i < RX_RING_SIZE; i++) { | |
867 | tp->rx_ring[i].status = 0; | |
868 | tp->rx_ring[i].length = PKT_BUF_SZ; | |
869 | tp->rx_ring[i].buffer2 = virt_to_bus(&tp->rx_ring[i+1]); | |
870 | tp->rx_skbuff[i] = NULL; | |
871 | } | |
872 | /* Mark the last entry as wrapping the ring. */ | |
873 | tp->rx_ring[i-1].length = PKT_BUF_SZ | Rx1RingWrap; | |
874 | tp->rx_ring[i-1].buffer2 = virt_to_bus(&tp->rx_ring[0]); | |
875 | ||
876 | for (i = 0; i < RX_RING_SIZE; i++) { | |
877 | /* Note the receive buffer must be longword aligned. | |
878 | dev_alloc_skb() provides 16 byte alignment. But do *not* | |
879 | use skb_reserve() to align the IP header! */ | |
880 | struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ); | |
881 | tp->rx_skbuff[i] = skb; | |
882 | if (skb == NULL) | |
883 | break; | |
884 | skb->dev = dev; /* Mark as being used by this device. */ | |
885 | tp->rx_ring[i].status = Rx0DescOwned; /* Owned by Xircom chip */ | |
689be439 | 886 | tp->rx_ring[i].buffer1 = virt_to_bus(skb->data); |
1da177e4 LT |
887 | } |
888 | tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
889 | ||
890 | /* The Tx buffer descriptor is filled in as needed, but we | |
891 | do need to clear the ownership bit. */ | |
892 | for (i = 0; i < TX_RING_SIZE; i++) { | |
893 | tp->tx_skbuff[i] = NULL; | |
894 | tp->tx_ring[i].status = 0; | |
895 | tp->tx_ring[i].buffer2 = virt_to_bus(&tp->tx_ring[i+1]); | |
1da177e4 LT |
896 | if (tp->chip_id == X3201_3) |
897 | tp->tx_aligned_skbuff[i] = dev_alloc_skb(PKT_BUF_SZ); | |
1da177e4 LT |
898 | } |
899 | tp->tx_ring[i-1].buffer2 = virt_to_bus(&tp->tx_ring[0]); | |
900 | } | |
901 | ||
902 | ||
903 | static int | |
904 | xircom_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
905 | { | |
906 | struct xircom_private *tp = netdev_priv(dev); | |
907 | int entry; | |
908 | u32 flag; | |
909 | ||
910 | /* Caution: the write order is important here, set the base address | |
911 | with the "ownership" bits last. */ | |
912 | ||
913 | /* Calculate the next Tx descriptor entry. */ | |
914 | entry = tp->cur_tx % TX_RING_SIZE; | |
915 | ||
916 | tp->tx_skbuff[entry] = skb; | |
1da177e4 LT |
917 | if (tp->chip_id == X3201_3) { |
918 | memcpy(tp->tx_aligned_skbuff[entry]->data,skb->data,skb->len); | |
919 | tp->tx_ring[entry].buffer1 = virt_to_bus(tp->tx_aligned_skbuff[entry]->data); | |
920 | } else | |
1da177e4 LT |
921 | tp->tx_ring[entry].buffer1 = virt_to_bus(skb->data); |
922 | ||
923 | if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */ | |
924 | flag = Tx1WholePkt; /* No interrupt */ | |
925 | } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) { | |
926 | flag = Tx1WholePkt | Tx1ComplIntr; /* Tx-done intr. */ | |
927 | } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) { | |
928 | flag = Tx1WholePkt; /* No Tx-done intr. */ | |
929 | } else { | |
930 | /* Leave room for set_rx_mode() to fill entries. */ | |
931 | flag = Tx1WholePkt | Tx1ComplIntr; /* Tx-done intr. */ | |
932 | tp->tx_full = 1; | |
933 | } | |
934 | if (entry == TX_RING_SIZE - 1) | |
935 | flag |= Tx1WholePkt | Tx1ComplIntr | Tx1RingWrap; | |
936 | ||
937 | tp->tx_ring[entry].length = skb->len | flag; | |
938 | tp->tx_ring[entry].status = Tx0DescOwned; /* Pass ownership to the chip. */ | |
939 | tp->cur_tx++; | |
940 | if (tp->tx_full) | |
941 | netif_stop_queue (dev); | |
942 | else | |
943 | netif_wake_queue (dev); | |
944 | ||
945 | /* Trigger an immediate transmit demand. */ | |
946 | outl(0, dev->base_addr + CSR1); | |
947 | ||
948 | dev->trans_start = jiffies; | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | ||
954 | static void xircom_media_change(struct net_device *dev) | |
955 | { | |
956 | struct xircom_private *tp = netdev_priv(dev); | |
957 | long ioaddr = dev->base_addr; | |
958 | u16 reg0, reg1, reg4, reg5; | |
959 | u32 csr6 = inl(ioaddr + CSR6), newcsr6; | |
960 | ||
961 | /* reset status first */ | |
962 | mdio_read(dev, tp->phys[0], MII_BMCR); | |
963 | mdio_read(dev, tp->phys[0], MII_BMSR); | |
964 | ||
965 | reg0 = mdio_read(dev, tp->phys[0], MII_BMCR); | |
966 | reg1 = mdio_read(dev, tp->phys[0], MII_BMSR); | |
967 | ||
968 | if (reg1 & BMSR_LSTATUS) { | |
969 | /* link is up */ | |
970 | if (reg0 & BMCR_ANENABLE) { | |
971 | /* autonegotiation is enabled */ | |
972 | reg4 = mdio_read(dev, tp->phys[0], MII_ADVERTISE); | |
973 | reg5 = mdio_read(dev, tp->phys[0], MII_LPA); | |
974 | if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) { | |
975 | tp->speed100 = 1; | |
976 | tp->full_duplex = 1; | |
977 | } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) { | |
978 | tp->speed100 = 1; | |
979 | tp->full_duplex = 0; | |
980 | } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) { | |
981 | tp->speed100 = 0; | |
982 | tp->full_duplex = 1; | |
983 | } else { | |
984 | tp->speed100 = 0; | |
985 | tp->full_duplex = 0; | |
986 | } | |
987 | } else { | |
988 | /* autonegotiation is disabled */ | |
989 | if (reg0 & BMCR_SPEED100) | |
990 | tp->speed100 = 1; | |
991 | else | |
992 | tp->speed100 = 0; | |
993 | if (reg0 & BMCR_FULLDPLX) | |
994 | tp->full_duplex = 1; | |
995 | else | |
996 | tp->full_duplex = 0; | |
997 | } | |
998 | printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n", | |
999 | dev->name, | |
1000 | tp->speed100 ? "100" : "10", | |
1001 | tp->full_duplex ? "full" : "half"); | |
1002 | netif_carrier_on(dev); | |
1003 | newcsr6 = csr6 & ~FullDuplexBit; | |
1004 | if (tp->full_duplex) | |
1005 | newcsr6 |= FullDuplexBit; | |
1006 | if (newcsr6 != csr6) | |
1007 | outl_CSR6(newcsr6, ioaddr + CSR6); | |
1008 | } else { | |
1009 | printk(KERN_DEBUG "%s: Link is down\n", dev->name); | |
1010 | netif_carrier_off(dev); | |
1011 | } | |
1012 | } | |
1013 | ||
1014 | ||
1015 | static void check_duplex(struct net_device *dev) | |
1016 | { | |
1017 | struct xircom_private *tp = netdev_priv(dev); | |
1018 | u16 reg0; | |
1019 | ||
1020 | mdio_write(dev, tp->phys[0], MII_BMCR, BMCR_RESET); | |
1021 | udelay(500); | |
1022 | while (mdio_read(dev, tp->phys[0], MII_BMCR) & BMCR_RESET); | |
1023 | ||
1024 | reg0 = mdio_read(dev, tp->phys[0], MII_BMCR); | |
1025 | mdio_write(dev, tp->phys[0], MII_ADVERTISE, tp->advertising[0]); | |
1026 | ||
1027 | if (tp->autoneg) { | |
1028 | reg0 &= ~(BMCR_SPEED100 | BMCR_FULLDPLX); | |
1029 | reg0 |= BMCR_ANENABLE | BMCR_ANRESTART; | |
1030 | } else { | |
1031 | reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART); | |
1032 | if (tp->speed100) | |
1033 | reg0 |= BMCR_SPEED100; | |
1034 | if (tp->full_duplex) | |
1035 | reg0 |= BMCR_FULLDPLX; | |
1036 | printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n", | |
1037 | dev->name, | |
1038 | tp->speed100 ? "100" : "10", | |
1039 | tp->full_duplex ? "full" : "half"); | |
1040 | } | |
1041 | mdio_write(dev, tp->phys[0], MII_BMCR, reg0); | |
1042 | } | |
1043 | ||
1044 | ||
1045 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1046 | after the Tx thread. */ | |
1047 | static irqreturn_t xircom_interrupt(int irq, void *dev_instance, struct pt_regs *regs) | |
1048 | { | |
1049 | struct net_device *dev = dev_instance; | |
1050 | struct xircom_private *tp = netdev_priv(dev); | |
1051 | long ioaddr = dev->base_addr; | |
1052 | int csr5, work_budget = max_interrupt_work; | |
1053 | int handled = 0; | |
1054 | ||
1055 | spin_lock (&tp->lock); | |
1056 | ||
1057 | do { | |
1058 | csr5 = inl(ioaddr + CSR5); | |
1059 | /* Acknowledge all of the current interrupt sources ASAP. */ | |
1060 | outl(csr5 & 0x0001ffff, ioaddr + CSR5); | |
1061 | ||
1062 | if (xircom_debug > 4) | |
1063 | printk(KERN_DEBUG "%s: interrupt csr5=%#8.8x new csr5=%#8.8x.\n", | |
1064 | dev->name, csr5, inl(dev->base_addr + CSR5)); | |
1065 | ||
1066 | if (csr5 == 0xffffffff) | |
1067 | break; /* all bits set, assume PCMCIA card removed */ | |
1068 | ||
1069 | if ((csr5 & (NormalIntr|AbnormalIntr)) == 0) | |
1070 | break; | |
1071 | ||
1072 | handled = 1; | |
1073 | ||
1074 | if (csr5 & (RxIntr | RxNoBuf)) | |
1075 | work_budget -= xircom_rx(dev); | |
1076 | ||
1077 | if (csr5 & (TxNoBuf | TxDied | TxIntr)) { | |
1078 | unsigned int dirty_tx; | |
1079 | ||
1080 | for (dirty_tx = tp->dirty_tx; tp->cur_tx - dirty_tx > 0; | |
1081 | dirty_tx++) { | |
1082 | int entry = dirty_tx % TX_RING_SIZE; | |
1083 | int status = tp->tx_ring[entry].status; | |
1084 | ||
1085 | if (status < 0) | |
1086 | break; /* It still hasn't been Txed */ | |
1087 | /* Check for Rx filter setup frames. */ | |
1088 | if (tp->tx_skbuff[entry] == NULL) | |
1089 | continue; | |
1090 | ||
1091 | if (status & Tx0DescError) { | |
1092 | /* There was an major error, log it. */ | |
1093 | #ifndef final_version | |
1094 | if (xircom_debug > 1) | |
1095 | printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n", | |
1096 | dev->name, status); | |
1097 | #endif | |
1098 | tp->stats.tx_errors++; | |
1099 | if (status & Tx0ManyColl) { | |
1100 | tp->stats.tx_aborted_errors++; | |
1101 | } | |
1102 | if (status & Tx0NoCarrier) tp->stats.tx_carrier_errors++; | |
1103 | if (status & Tx0LateColl) tp->stats.tx_window_errors++; | |
1104 | if (status & Tx0Underflow) tp->stats.tx_fifo_errors++; | |
1105 | } else { | |
1106 | tp->stats.tx_bytes += tp->tx_ring[entry].length & 0x7ff; | |
1107 | tp->stats.collisions += (status >> 3) & 15; | |
1108 | tp->stats.tx_packets++; | |
1109 | } | |
1110 | ||
1111 | /* Free the original skb. */ | |
1112 | dev_kfree_skb_irq(tp->tx_skbuff[entry]); | |
1113 | tp->tx_skbuff[entry] = NULL; | |
1114 | } | |
1115 | ||
1116 | #ifndef final_version | |
1117 | if (tp->cur_tx - dirty_tx > TX_RING_SIZE) { | |
1118 | printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n", | |
1119 | dev->name, dirty_tx, tp->cur_tx, tp->tx_full); | |
1120 | dirty_tx += TX_RING_SIZE; | |
1121 | } | |
1122 | #endif | |
1123 | ||
1124 | if (tp->tx_full && | |
1125 | tp->cur_tx - dirty_tx < TX_RING_SIZE - 2) | |
1126 | /* The ring is no longer full */ | |
1127 | tp->tx_full = 0; | |
1128 | ||
1129 | if (tp->tx_full) | |
1130 | netif_stop_queue (dev); | |
1131 | else | |
1132 | netif_wake_queue (dev); | |
1133 | ||
1134 | tp->dirty_tx = dirty_tx; | |
1135 | if (csr5 & TxDied) { | |
1136 | if (xircom_debug > 2) | |
1137 | printk(KERN_WARNING "%s: The transmitter stopped." | |
1138 | " CSR5 is %x, CSR6 %x, new CSR6 %x.\n", | |
1139 | dev->name, csr5, inl(ioaddr + CSR6), tp->csr6); | |
1140 | outl_CSR6(tp->csr6 | EnableRx, ioaddr); | |
1141 | outl_CSR6(tp->csr6 | EnableTxRx, ioaddr); | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | /* Log errors. */ | |
1146 | if (csr5 & AbnormalIntr) { /* Abnormal error summary bit. */ | |
1147 | if (csr5 & LinkChange) | |
1148 | xircom_media_change(dev); | |
1149 | if (csr5 & TxFIFOUnderflow) { | |
1150 | if ((tp->csr6 & TxThreshMask) != TxThreshMask) | |
1151 | tp->csr6 += (1 << TxThreshShift); /* Bump up the Tx threshold */ | |
1152 | else | |
1153 | tp->csr6 |= TxStoreForw; /* Store-n-forward. */ | |
1154 | /* Restart the transmit process. */ | |
1155 | outl_CSR6(tp->csr6 | EnableRx, ioaddr); | |
1156 | outl_CSR6(tp->csr6 | EnableTxRx, ioaddr); | |
1157 | } | |
1158 | if (csr5 & RxDied) { /* Missed a Rx frame. */ | |
1159 | tp->stats.rx_errors++; | |
1160 | tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff; | |
1161 | outl_CSR6(tp->csr6 | EnableTxRx, ioaddr); | |
1162 | } | |
1163 | /* Clear all error sources, included undocumented ones! */ | |
1164 | outl(0x0800f7ba, ioaddr + CSR5); | |
1165 | } | |
1166 | if (--work_budget < 0) { | |
1167 | if (xircom_debug > 1) | |
1168 | printk(KERN_WARNING "%s: Too much work during an interrupt, " | |
1169 | "csr5=0x%8.8x.\n", dev->name, csr5); | |
1170 | /* Acknowledge all interrupt sources. */ | |
1171 | outl(0x8001ffff, ioaddr + CSR5); | |
1172 | break; | |
1173 | } | |
1174 | } while (1); | |
1175 | ||
1176 | if (xircom_debug > 3) | |
1177 | printk(KERN_DEBUG "%s: exiting interrupt, csr5=%#4.4x.\n", | |
1178 | dev->name, inl(ioaddr + CSR5)); | |
1179 | ||
1180 | spin_unlock (&tp->lock); | |
1181 | return IRQ_RETVAL(handled); | |
1182 | } | |
1183 | ||
1184 | ||
1185 | static int | |
1186 | xircom_rx(struct net_device *dev) | |
1187 | { | |
1188 | struct xircom_private *tp = netdev_priv(dev); | |
1189 | int entry = tp->cur_rx % RX_RING_SIZE; | |
1190 | int rx_work_limit = tp->dirty_rx + RX_RING_SIZE - tp->cur_rx; | |
1191 | int work_done = 0; | |
1192 | ||
1193 | if (xircom_debug > 4) | |
1194 | printk(KERN_DEBUG " In xircom_rx(), entry %d %8.8x.\n", entry, | |
1195 | tp->rx_ring[entry].status); | |
1196 | /* If we own the next entry, it's a new packet. Send it up. */ | |
1197 | while (tp->rx_ring[entry].status >= 0) { | |
1198 | s32 status = tp->rx_ring[entry].status; | |
1199 | ||
1200 | if (xircom_debug > 5) | |
1201 | printk(KERN_DEBUG " In xircom_rx(), entry %d %8.8x.\n", entry, | |
1202 | tp->rx_ring[entry].status); | |
1203 | if (--rx_work_limit < 0) | |
1204 | break; | |
1205 | if ((status & 0x38008300) != 0x0300) { | |
1206 | if ((status & 0x38000300) != 0x0300) { | |
1207 | /* Ignore earlier buffers. */ | |
1208 | if ((status & 0xffff) != 0x7fff) { | |
1209 | if (xircom_debug > 1) | |
1210 | printk(KERN_WARNING "%s: Oversized Ethernet frame " | |
1211 | "spanned multiple buffers, status %8.8x!\n", | |
1212 | dev->name, status); | |
1213 | tp->stats.rx_length_errors++; | |
1214 | } | |
1215 | } else if (status & Rx0DescError) { | |
1216 | /* There was a fatal error. */ | |
1217 | if (xircom_debug > 2) | |
1218 | printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n", | |
1219 | dev->name, status); | |
1220 | tp->stats.rx_errors++; /* end of a packet.*/ | |
1221 | if (status & (Rx0Runt | Rx0HugeFrame)) tp->stats.rx_length_errors++; | |
1222 | if (status & Rx0CRCError) tp->stats.rx_crc_errors++; | |
1223 | } | |
1224 | } else { | |
1225 | /* Omit the four octet CRC from the length. */ | |
1226 | short pkt_len = ((status >> 16) & 0x7ff) - 4; | |
1227 | struct sk_buff *skb; | |
1228 | ||
1229 | #ifndef final_version | |
1230 | if (pkt_len > 1518) { | |
1231 | printk(KERN_WARNING "%s: Bogus packet size of %d (%#x).\n", | |
1232 | dev->name, pkt_len, pkt_len); | |
1233 | pkt_len = 1518; | |
1234 | tp->stats.rx_length_errors++; | |
1235 | } | |
1236 | #endif | |
1237 | /* Check if the packet is long enough to accept without copying | |
1238 | to a minimally-sized skbuff. */ | |
1239 | if (pkt_len < rx_copybreak | |
1240 | && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { | |
1241 | skb->dev = dev; | |
1242 | skb_reserve(skb, 2); /* 16 byte align the IP header */ | |
1243 | #if ! defined(__alpha__) | |
1244 | eth_copy_and_sum(skb, bus_to_virt(tp->rx_ring[entry].buffer1), | |
1245 | pkt_len, 0); | |
1246 | skb_put(skb, pkt_len); | |
1247 | #else | |
1248 | memcpy(skb_put(skb, pkt_len), | |
1249 | bus_to_virt(tp->rx_ring[entry].buffer1), pkt_len); | |
1250 | #endif | |
1251 | work_done++; | |
1252 | } else { /* Pass up the skb already on the Rx ring. */ | |
1253 | skb_put(skb = tp->rx_skbuff[entry], pkt_len); | |
1254 | tp->rx_skbuff[entry] = NULL; | |
1255 | } | |
1256 | skb->protocol = eth_type_trans(skb, dev); | |
1257 | netif_rx(skb); | |
1258 | dev->last_rx = jiffies; | |
1259 | tp->stats.rx_packets++; | |
1260 | tp->stats.rx_bytes += pkt_len; | |
1261 | } | |
1262 | entry = (++tp->cur_rx) % RX_RING_SIZE; | |
1263 | } | |
1264 | ||
1265 | /* Refill the Rx ring buffers. */ | |
1266 | for (; tp->cur_rx - tp->dirty_rx > 0; tp->dirty_rx++) { | |
1267 | entry = tp->dirty_rx % RX_RING_SIZE; | |
1268 | if (tp->rx_skbuff[entry] == NULL) { | |
1269 | struct sk_buff *skb; | |
1270 | skb = tp->rx_skbuff[entry] = dev_alloc_skb(PKT_BUF_SZ); | |
1271 | if (skb == NULL) | |
1272 | break; | |
1273 | skb->dev = dev; /* Mark as being used by this device. */ | |
689be439 | 1274 | tp->rx_ring[entry].buffer1 = virt_to_bus(skb->data); |
1da177e4 LT |
1275 | work_done++; |
1276 | } | |
1277 | tp->rx_ring[entry].status = Rx0DescOwned; | |
1278 | } | |
1279 | ||
1280 | return work_done; | |
1281 | } | |
1282 | ||
1283 | ||
1284 | static void | |
1285 | xircom_down(struct net_device *dev) | |
1286 | { | |
1287 | long ioaddr = dev->base_addr; | |
1288 | struct xircom_private *tp = netdev_priv(dev); | |
1289 | ||
1290 | /* Disable interrupts by clearing the interrupt mask. */ | |
1291 | outl(0, ioaddr + CSR7); | |
1292 | /* Stop the chip's Tx and Rx processes. */ | |
1293 | outl_CSR6(inl(ioaddr + CSR6) & ~EnableTxRx, ioaddr); | |
1294 | ||
1295 | if (inl(ioaddr + CSR6) != 0xffffffff) | |
1296 | tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff; | |
1297 | ||
1298 | dev->if_port = tp->saved_if_port; | |
1299 | } | |
1300 | ||
1301 | ||
1302 | static int | |
1303 | xircom_close(struct net_device *dev) | |
1304 | { | |
1305 | long ioaddr = dev->base_addr; | |
1306 | struct xircom_private *tp = netdev_priv(dev); | |
1307 | int i; | |
1308 | ||
1309 | if (xircom_debug > 1) | |
1310 | printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n", | |
1311 | dev->name, inl(ioaddr + CSR5)); | |
1312 | ||
1313 | netif_stop_queue(dev); | |
1314 | ||
1315 | if (netif_device_present(dev)) | |
1316 | xircom_down(dev); | |
1317 | ||
1318 | free_irq(dev->irq, dev); | |
1319 | ||
1320 | /* Free all the skbuffs in the Rx queue. */ | |
1321 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1322 | struct sk_buff *skb = tp->rx_skbuff[i]; | |
1323 | tp->rx_skbuff[i] = NULL; | |
1324 | tp->rx_ring[i].status = 0; /* Not owned by Xircom chip. */ | |
1325 | tp->rx_ring[i].length = 0; | |
1326 | tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */ | |
1327 | if (skb) { | |
1328 | dev_kfree_skb(skb); | |
1329 | } | |
1330 | } | |
1331 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1332 | if (tp->tx_skbuff[i]) | |
1333 | dev_kfree_skb(tp->tx_skbuff[i]); | |
1334 | tp->tx_skbuff[i] = NULL; | |
1335 | } | |
1336 | ||
1337 | tp->open = 0; | |
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | ||
1342 | static struct net_device_stats *xircom_get_stats(struct net_device *dev) | |
1343 | { | |
1344 | struct xircom_private *tp = netdev_priv(dev); | |
1345 | long ioaddr = dev->base_addr; | |
1346 | ||
1347 | if (netif_device_present(dev)) | |
1348 | tp->stats.rx_missed_errors += inl(ioaddr + CSR8) & 0xffff; | |
1349 | ||
1350 | return &tp->stats; | |
1351 | } | |
1352 | ||
1353 | static int xircom_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1354 | { | |
1355 | struct xircom_private *tp = netdev_priv(dev); | |
1356 | ecmd->supported = | |
1357 | SUPPORTED_10baseT_Half | | |
1358 | SUPPORTED_10baseT_Full | | |
1359 | SUPPORTED_100baseT_Half | | |
1360 | SUPPORTED_100baseT_Full | | |
1361 | SUPPORTED_Autoneg | | |
1362 | SUPPORTED_MII; | |
1363 | ||
1364 | ecmd->advertising = ADVERTISED_MII; | |
1365 | if (tp->advertising[0] & ADVERTISE_10HALF) | |
1366 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
1367 | if (tp->advertising[0] & ADVERTISE_10FULL) | |
1368 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
1369 | if (tp->advertising[0] & ADVERTISE_100HALF) | |
1370 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
1371 | if (tp->advertising[0] & ADVERTISE_100FULL) | |
1372 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
1373 | if (tp->autoneg) { | |
1374 | ecmd->advertising |= ADVERTISED_Autoneg; | |
1375 | ecmd->autoneg = AUTONEG_ENABLE; | |
1376 | } else | |
1377 | ecmd->autoneg = AUTONEG_DISABLE; | |
1378 | ||
1379 | ecmd->port = PORT_MII; | |
1380 | ecmd->transceiver = XCVR_INTERNAL; | |
1381 | ecmd->phy_address = tp->phys[0]; | |
1382 | ecmd->speed = tp->speed100 ? SPEED_100 : SPEED_10; | |
1383 | ecmd->duplex = tp->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; | |
1384 | ecmd->maxtxpkt = TX_RING_SIZE / 2; | |
1385 | ecmd->maxrxpkt = 0; | |
1386 | return 0; | |
1387 | } | |
1388 | ||
1389 | static int xircom_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1390 | { | |
1391 | struct xircom_private *tp = netdev_priv(dev); | |
1392 | u16 autoneg, speed100, full_duplex; | |
1393 | ||
1394 | autoneg = (ecmd->autoneg == AUTONEG_ENABLE); | |
1395 | speed100 = (ecmd->speed == SPEED_100); | |
1396 | full_duplex = (ecmd->duplex == DUPLEX_FULL); | |
1397 | ||
1398 | tp->autoneg = autoneg; | |
1399 | if (speed100 != tp->speed100 || | |
1400 | full_duplex != tp->full_duplex) { | |
1401 | tp->speed100 = speed100; | |
1402 | tp->full_duplex = full_duplex; | |
1403 | /* change advertising bits */ | |
1404 | tp->advertising[0] &= ~(ADVERTISE_10HALF | | |
1405 | ADVERTISE_10FULL | | |
1406 | ADVERTISE_100HALF | | |
1407 | ADVERTISE_100FULL | | |
1408 | ADVERTISE_100BASE4); | |
1409 | if (speed100) { | |
1410 | if (full_duplex) | |
1411 | tp->advertising[0] |= ADVERTISE_100FULL; | |
1412 | else | |
1413 | tp->advertising[0] |= ADVERTISE_100HALF; | |
1414 | } else { | |
1415 | if (full_duplex) | |
1416 | tp->advertising[0] |= ADVERTISE_10FULL; | |
1417 | else | |
1418 | tp->advertising[0] |= ADVERTISE_10HALF; | |
1419 | } | |
1420 | } | |
1421 | check_duplex(dev); | |
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | static void xircom_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1426 | { | |
1427 | struct xircom_private *tp = netdev_priv(dev); | |
1428 | strcpy(info->driver, DRV_NAME); | |
1429 | strcpy(info->version, DRV_VERSION); | |
1430 | strcpy(info->bus_info, pci_name(tp->pdev)); | |
1431 | } | |
1432 | ||
7282d491 | 1433 | static const struct ethtool_ops ops = { |
1da177e4 LT |
1434 | .get_settings = xircom_get_settings, |
1435 | .set_settings = xircom_set_settings, | |
1436 | .get_drvinfo = xircom_get_drvinfo, | |
1437 | }; | |
1438 | ||
1439 | /* Provide ioctl() calls to examine the MII xcvr state. */ | |
1440 | static int xircom_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1441 | { | |
1442 | struct xircom_private *tp = netdev_priv(dev); | |
1443 | u16 *data = (u16 *)&rq->ifr_ifru; | |
1444 | int phy = tp->phys[0] & 0x1f; | |
1445 | unsigned long flags; | |
1446 | ||
1447 | switch(cmd) { | |
1448 | /* Legacy mii-diag interface */ | |
1449 | case SIOCGMIIPHY: /* Get address of MII PHY in use. */ | |
1450 | if (tp->mii_cnt) | |
1451 | data[0] = phy; | |
1452 | else | |
1453 | return -ENODEV; | |
1454 | return 0; | |
1455 | case SIOCGMIIREG: /* Read MII PHY register. */ | |
1456 | save_flags(flags); | |
1457 | cli(); | |
1458 | data[3] = mdio_read(dev, data[0] & 0x1f, data[1] & 0x1f); | |
1459 | restore_flags(flags); | |
1460 | return 0; | |
1461 | case SIOCSMIIREG: /* Write MII PHY register. */ | |
1462 | if (!capable(CAP_NET_ADMIN)) | |
1463 | return -EPERM; | |
1464 | save_flags(flags); | |
1465 | cli(); | |
1466 | if (data[0] == tp->phys[0]) { | |
1467 | u16 value = data[2]; | |
1468 | switch (data[1]) { | |
1469 | case 0: | |
1470 | if (value & (BMCR_RESET | BMCR_ANENABLE)) | |
1471 | /* Autonegotiation. */ | |
1472 | tp->autoneg = 1; | |
1473 | else { | |
1474 | tp->full_duplex = (value & BMCR_FULLDPLX) ? 1 : 0; | |
1475 | tp->autoneg = 0; | |
1476 | } | |
1477 | break; | |
1478 | case 4: | |
1479 | tp->advertising[0] = value; | |
1480 | break; | |
1481 | } | |
1482 | check_duplex(dev); | |
1483 | } | |
1484 | mdio_write(dev, data[0] & 0x1f, data[1] & 0x1f, data[2]); | |
1485 | restore_flags(flags); | |
1486 | return 0; | |
1487 | default: | |
1488 | return -EOPNOTSUPP; | |
1489 | } | |
1490 | ||
1491 | return -EOPNOTSUPP; | |
1492 | } | |
1493 | ||
1494 | /* Set or clear the multicast filter for this adaptor. | |
1495 | Note that we only use exclusion around actually queueing the | |
1496 | new frame, not around filling tp->setup_frame. This is non-deterministic | |
1497 | when re-entered but still correct. */ | |
1498 | static void set_rx_mode(struct net_device *dev) | |
1499 | { | |
1500 | struct xircom_private *tp = netdev_priv(dev); | |
1501 | struct dev_mc_list *mclist; | |
1502 | long ioaddr = dev->base_addr; | |
1503 | int csr6 = inl(ioaddr + CSR6); | |
1504 | u16 *eaddrs, *setup_frm; | |
1505 | u32 tx_flags; | |
1506 | int i; | |
1507 | ||
1508 | tp->csr6 &= ~(AllMultiBit | PromiscBit | HashFilterBit); | |
1509 | csr6 &= ~(AllMultiBit | PromiscBit | HashFilterBit); | |
1510 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1511 | tp->csr6 |= PromiscBit; | |
1512 | csr6 |= PromiscBit; | |
1513 | goto out; | |
1514 | } | |
1515 | ||
1516 | if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) { | |
1517 | /* Too many to filter well -- accept all multicasts. */ | |
1518 | tp->csr6 |= AllMultiBit; | |
1519 | csr6 |= AllMultiBit; | |
1520 | goto out; | |
1521 | } | |
1522 | ||
1523 | tx_flags = Tx1WholePkt | Tx1SetupPkt | PKT_SETUP_SZ; | |
1524 | ||
1525 | /* Note that only the low-address shortword of setup_frame is valid! */ | |
1526 | setup_frm = tp->setup_frame; | |
1527 | mclist = dev->mc_list; | |
1528 | ||
1529 | /* Fill the first entry with our physical address. */ | |
1530 | eaddrs = (u16 *)dev->dev_addr; | |
1531 | *setup_frm = cpu_to_le16(eaddrs[0]); setup_frm += 2; | |
1532 | *setup_frm = cpu_to_le16(eaddrs[1]); setup_frm += 2; | |
1533 | *setup_frm = cpu_to_le16(eaddrs[2]); setup_frm += 2; | |
1534 | ||
1535 | if (dev->mc_count > 14) { /* Must use a multicast hash table. */ | |
1536 | u32 *hash_table = (u32 *)(tp->setup_frame + 4 * 12); | |
1537 | u32 hash, hash2; | |
1538 | ||
1539 | tx_flags |= Tx1HashSetup; | |
1540 | tp->csr6 |= HashFilterBit; | |
1541 | csr6 |= HashFilterBit; | |
1542 | ||
1543 | /* Fill the unused 3 entries with the broadcast address. | |
1544 | At least one entry *must* contain the broadcast address!!!*/ | |
1545 | for (i = 0; i < 3; i++) { | |
1546 | *setup_frm = 0xffff; setup_frm += 2; | |
1547 | *setup_frm = 0xffff; setup_frm += 2; | |
1548 | *setup_frm = 0xffff; setup_frm += 2; | |
1549 | } | |
1550 | ||
1551 | /* Truly brain-damaged hash filter layout */ | |
1552 | /* XXX: not sure if I should take the last or the first 9 bits */ | |
1553 | for (i = 0; i < dev->mc_count; i++, mclist = mclist->next) { | |
1554 | u32 *hptr; | |
1555 | hash = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x1ff; | |
1556 | if (hash < 384) { | |
1557 | hash2 = hash + ((hash >> 4) << 4) + | |
1558 | ((hash >> 5) << 5); | |
1559 | } else { | |
1560 | hash -= 384; | |
1561 | hash2 = 64 + hash + (hash >> 4) * 80; | |
1562 | } | |
1563 | hptr = &hash_table[hash2 & ~0x1f]; | |
1564 | *hptr |= cpu_to_le32(1 << (hash2 & 0x1f)); | |
1565 | } | |
1566 | } else { | |
1567 | /* We have <= 14 mcast addresses so we can use Xircom's | |
1568 | wonderful 16-address perfect filter. */ | |
1569 | for (i = 0; i < dev->mc_count; i++, mclist = mclist->next) { | |
1570 | eaddrs = (u16 *)mclist->dmi_addr; | |
1571 | *setup_frm = cpu_to_le16(eaddrs[0]); setup_frm += 2; | |
1572 | *setup_frm = cpu_to_le16(eaddrs[1]); setup_frm += 2; | |
1573 | *setup_frm = cpu_to_le16(eaddrs[2]); setup_frm += 2; | |
1574 | } | |
1575 | /* Fill the unused entries with the broadcast address. | |
1576 | At least one entry *must* contain the broadcast address!!!*/ | |
1577 | for (; i < 15; i++) { | |
1578 | *setup_frm = 0xffff; setup_frm += 2; | |
1579 | *setup_frm = 0xffff; setup_frm += 2; | |
1580 | *setup_frm = 0xffff; setup_frm += 2; | |
1581 | } | |
1582 | } | |
1583 | ||
1584 | /* Now add this frame to the Tx list. */ | |
1585 | if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) { | |
1586 | /* Same setup recently queued, we need not add it. */ | |
1587 | /* XXX: Huh? All it means is that the Tx list is full...*/ | |
1588 | } else { | |
1589 | unsigned long flags; | |
1590 | unsigned int entry; | |
1591 | int dummy = -1; | |
1592 | ||
1593 | save_flags(flags); cli(); | |
1594 | entry = tp->cur_tx++ % TX_RING_SIZE; | |
1595 | ||
1596 | if (entry != 0) { | |
1597 | /* Avoid a chip errata by prefixing a dummy entry. */ | |
1598 | tp->tx_skbuff[entry] = NULL; | |
1599 | tp->tx_ring[entry].length = | |
1600 | (entry == TX_RING_SIZE - 1) ? Tx1RingWrap : 0; | |
1601 | tp->tx_ring[entry].buffer1 = 0; | |
1602 | /* race with chip, set Tx0DescOwned later */ | |
1603 | dummy = entry; | |
1604 | entry = tp->cur_tx++ % TX_RING_SIZE; | |
1605 | } | |
1606 | ||
1607 | tp->tx_skbuff[entry] = NULL; | |
1608 | /* Put the setup frame on the Tx list. */ | |
1609 | if (entry == TX_RING_SIZE - 1) | |
1610 | tx_flags |= Tx1RingWrap; /* Wrap ring. */ | |
1611 | tp->tx_ring[entry].length = tx_flags; | |
1612 | tp->tx_ring[entry].buffer1 = virt_to_bus(tp->setup_frame); | |
1613 | tp->tx_ring[entry].status = Tx0DescOwned; | |
1614 | if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2) { | |
1615 | tp->tx_full = 1; | |
1616 | netif_stop_queue (dev); | |
1617 | } | |
1618 | if (dummy >= 0) | |
1619 | tp->tx_ring[dummy].status = Tx0DescOwned; | |
1620 | restore_flags(flags); | |
1621 | /* Trigger an immediate transmit demand. */ | |
1622 | outl(0, ioaddr + CSR1); | |
1623 | } | |
1624 | ||
1625 | out: | |
1626 | outl_CSR6(csr6, ioaddr); | |
1627 | } | |
1628 | ||
1629 | ||
1630 | static struct pci_device_id xircom_pci_table[] = { | |
1631 | { 0x115D, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, X3201_3 }, | |
1632 | {0}, | |
1633 | }; | |
1634 | MODULE_DEVICE_TABLE(pci, xircom_pci_table); | |
1635 | ||
1636 | ||
1637 | #ifdef CONFIG_PM | |
05adc3b7 | 1638 | static int xircom_suspend(struct pci_dev *pdev, pm_message_t state) |
1da177e4 LT |
1639 | { |
1640 | struct net_device *dev = pci_get_drvdata(pdev); | |
1641 | struct xircom_private *tp = netdev_priv(dev); | |
1642 | printk(KERN_INFO "xircom_suspend(%s)\n", dev->name); | |
1643 | if (tp->open) | |
1644 | xircom_down(dev); | |
1645 | ||
1646 | pci_save_state(pdev); | |
1647 | pci_disable_device(pdev); | |
1648 | pci_set_power_state(pdev, 3); | |
1649 | ||
1650 | return 0; | |
1651 | } | |
1652 | ||
1653 | ||
1654 | static int xircom_resume(struct pci_dev *pdev) | |
1655 | { | |
1656 | struct net_device *dev = pci_get_drvdata(pdev); | |
1657 | struct xircom_private *tp = netdev_priv(dev); | |
1658 | printk(KERN_INFO "xircom_resume(%s)\n", dev->name); | |
1659 | ||
1660 | pci_set_power_state(pdev,0); | |
1661 | pci_enable_device(pdev); | |
1662 | pci_restore_state(pdev); | |
1663 | ||
1664 | /* Bring the chip out of sleep mode. | |
1665 | Caution: Snooze mode does not work with some boards! */ | |
1666 | if (xircom_tbl[tp->chip_id].flags & HAS_ACPI) | |
1667 | pci_write_config_dword(tp->pdev, PCI_POWERMGMT, 0); | |
1668 | ||
1669 | transceiver_voodoo(dev); | |
1670 | if (xircom_tbl[tp->chip_id].flags & HAS_MII) | |
1671 | check_duplex(dev); | |
1672 | ||
1673 | if (tp->open) | |
1674 | xircom_up(dev); | |
1675 | return 0; | |
1676 | } | |
1677 | #endif /* CONFIG_PM */ | |
1678 | ||
1679 | ||
1680 | static void __devexit xircom_remove_one(struct pci_dev *pdev) | |
1681 | { | |
1682 | struct net_device *dev = pci_get_drvdata(pdev); | |
1683 | ||
1684 | printk(KERN_INFO "xircom_remove_one(%s)\n", dev->name); | |
1685 | unregister_netdev(dev); | |
1686 | pci_release_regions(pdev); | |
1687 | free_netdev(dev); | |
1688 | pci_set_drvdata(pdev, NULL); | |
1689 | } | |
1690 | ||
1691 | ||
1692 | static struct pci_driver xircom_driver = { | |
1693 | .name = DRV_NAME, | |
1694 | .id_table = xircom_pci_table, | |
1695 | .probe = xircom_init_one, | |
1696 | .remove = __devexit_p(xircom_remove_one), | |
1697 | #ifdef CONFIG_PM | |
1698 | .suspend = xircom_suspend, | |
1699 | .resume = xircom_resume | |
1700 | #endif /* CONFIG_PM */ | |
1701 | }; | |
1702 | ||
1703 | ||
1704 | static int __init xircom_init(void) | |
1705 | { | |
1706 | /* when a module, this is printed whether or not devices are found in probe */ | |
1707 | #ifdef MODULE | |
1708 | printk(version); | |
1709 | #endif | |
29917620 | 1710 | return pci_register_driver(&xircom_driver); |
1da177e4 LT |
1711 | } |
1712 | ||
1713 | ||
1714 | static void __exit xircom_exit(void) | |
1715 | { | |
1716 | pci_unregister_driver(&xircom_driver); | |
1717 | } | |
1718 | ||
1719 | module_init(xircom_init) | |
1720 | module_exit(xircom_exit) | |
1721 | ||
1722 | /* | |
1723 | * Local variables: | |
1724 | * c-indent-level: 4 | |
1725 | * c-basic-offset: 4 | |
1726 | * tab-width: 4 | |
1727 | * End: | |
1728 | */ |