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Commit | Line | Data |
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2e55cc72 DB |
1 | /* |
2 | * ASIX AX8817X based USB 2.0 Ethernet Devices | |
933a27d3 | 3 | * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> |
2e55cc72 | 4 | * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> |
933a27d3 | 5 | * Copyright (C) 2006 James Painter <jamie.painter@iname.com> |
2e55cc72 DB |
6 | * Copyright (c) 2002-2003 TiVo Inc. |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | // #define DEBUG // error path messages, extra info | |
24 | // #define VERBOSE // more; success messages | |
25 | ||
2e55cc72 DB |
26 | #include <linux/module.h> |
27 | #include <linux/kmod.h> | |
2e55cc72 DB |
28 | #include <linux/init.h> |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/ethtool.h> | |
32 | #include <linux/workqueue.h> | |
33 | #include <linux/mii.h> | |
34 | #include <linux/usb.h> | |
35 | #include <linux/crc32.h> | |
3692e94f | 36 | #include <linux/usb/usbnet.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
9dae3100 | 38 | #include <linux/if_vlan.h> |
2e55cc72 | 39 | |
f87ce5b2 | 40 | #define DRIVER_VERSION "22-Dec-2011" |
83e1b918 | 41 | #define DRIVER_NAME "asix" |
933a27d3 | 42 | |
2e55cc72 DB |
43 | /* ASIX AX8817X based USB 2.0 Ethernet Devices */ |
44 | ||
45 | #define AX_CMD_SET_SW_MII 0x06 | |
46 | #define AX_CMD_READ_MII_REG 0x07 | |
47 | #define AX_CMD_WRITE_MII_REG 0x08 | |
48 | #define AX_CMD_SET_HW_MII 0x0a | |
49 | #define AX_CMD_READ_EEPROM 0x0b | |
50 | #define AX_CMD_WRITE_EEPROM 0x0c | |
51 | #define AX_CMD_WRITE_ENABLE 0x0d | |
52 | #define AX_CMD_WRITE_DISABLE 0x0e | |
933a27d3 | 53 | #define AX_CMD_READ_RX_CTL 0x0f |
2e55cc72 DB |
54 | #define AX_CMD_WRITE_RX_CTL 0x10 |
55 | #define AX_CMD_READ_IPG012 0x11 | |
56 | #define AX_CMD_WRITE_IPG0 0x12 | |
57 | #define AX_CMD_WRITE_IPG1 0x13 | |
933a27d3 | 58 | #define AX_CMD_READ_NODE_ID 0x13 |
7f29a3ba | 59 | #define AX_CMD_WRITE_NODE_ID 0x14 |
2e55cc72 DB |
60 | #define AX_CMD_WRITE_IPG2 0x14 |
61 | #define AX_CMD_WRITE_MULTI_FILTER 0x16 | |
933a27d3 | 62 | #define AX88172_CMD_READ_NODE_ID 0x17 |
2e55cc72 DB |
63 | #define AX_CMD_READ_PHY_ID 0x19 |
64 | #define AX_CMD_READ_MEDIUM_STATUS 0x1a | |
65 | #define AX_CMD_WRITE_MEDIUM_MODE 0x1b | |
66 | #define AX_CMD_READ_MONITOR_MODE 0x1c | |
67 | #define AX_CMD_WRITE_MONITOR_MODE 0x1d | |
933a27d3 | 68 | #define AX_CMD_READ_GPIOS 0x1e |
2e55cc72 DB |
69 | #define AX_CMD_WRITE_GPIOS 0x1f |
70 | #define AX_CMD_SW_RESET 0x20 | |
71 | #define AX_CMD_SW_PHY_STATUS 0x21 | |
72 | #define AX_CMD_SW_PHY_SELECT 0x22 | |
2e55cc72 DB |
73 | |
74 | #define AX_MONITOR_MODE 0x01 | |
75 | #define AX_MONITOR_LINK 0x02 | |
76 | #define AX_MONITOR_MAGIC 0x04 | |
77 | #define AX_MONITOR_HSFS 0x10 | |
78 | ||
79 | /* AX88172 Medium Status Register values */ | |
933a27d3 DH |
80 | #define AX88172_MEDIUM_FD 0x02 |
81 | #define AX88172_MEDIUM_TX 0x04 | |
82 | #define AX88172_MEDIUM_FC 0x10 | |
83 | #define AX88172_MEDIUM_DEFAULT \ | |
84 | ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC ) | |
2e55cc72 DB |
85 | |
86 | #define AX_MCAST_FILTER_SIZE 8 | |
87 | #define AX_MAX_MCAST 64 | |
88 | ||
2e55cc72 DB |
89 | #define AX_SWRESET_CLEAR 0x00 |
90 | #define AX_SWRESET_RR 0x01 | |
91 | #define AX_SWRESET_RT 0x02 | |
92 | #define AX_SWRESET_PRTE 0x04 | |
93 | #define AX_SWRESET_PRL 0x08 | |
94 | #define AX_SWRESET_BZ 0x10 | |
95 | #define AX_SWRESET_IPRL 0x20 | |
96 | #define AX_SWRESET_IPPD 0x40 | |
97 | ||
98 | #define AX88772_IPG0_DEFAULT 0x15 | |
99 | #define AX88772_IPG1_DEFAULT 0x0c | |
100 | #define AX88772_IPG2_DEFAULT 0x12 | |
101 | ||
933a27d3 DH |
102 | /* AX88772 & AX88178 Medium Mode Register */ |
103 | #define AX_MEDIUM_PF 0x0080 | |
104 | #define AX_MEDIUM_JFE 0x0040 | |
105 | #define AX_MEDIUM_TFC 0x0020 | |
106 | #define AX_MEDIUM_RFC 0x0010 | |
107 | #define AX_MEDIUM_ENCK 0x0008 | |
108 | #define AX_MEDIUM_AC 0x0004 | |
109 | #define AX_MEDIUM_FD 0x0002 | |
110 | #define AX_MEDIUM_GM 0x0001 | |
111 | #define AX_MEDIUM_SM 0x1000 | |
112 | #define AX_MEDIUM_SBP 0x0800 | |
113 | #define AX_MEDIUM_PS 0x0200 | |
114 | #define AX_MEDIUM_RE 0x0100 | |
115 | ||
116 | #define AX88178_MEDIUM_DEFAULT \ | |
117 | (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ | |
118 | AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ | |
83e1b918 | 119 | AX_MEDIUM_RE) |
2e55cc72 | 120 | |
933a27d3 DH |
121 | #define AX88772_MEDIUM_DEFAULT \ |
122 | (AX_MEDIUM_FD | AX_MEDIUM_RFC | \ | |
123 | AX_MEDIUM_TFC | AX_MEDIUM_PS | \ | |
83e1b918 | 124 | AX_MEDIUM_AC | AX_MEDIUM_RE) |
933a27d3 DH |
125 | |
126 | /* AX88772 & AX88178 RX_CTL values */ | |
83e1b918 GG |
127 | #define AX_RX_CTL_SO 0x0080 |
128 | #define AX_RX_CTL_AP 0x0020 | |
129 | #define AX_RX_CTL_AM 0x0010 | |
130 | #define AX_RX_CTL_AB 0x0008 | |
131 | #define AX_RX_CTL_SEP 0x0004 | |
132 | #define AX_RX_CTL_AMALL 0x0002 | |
133 | #define AX_RX_CTL_PRO 0x0001 | |
134 | #define AX_RX_CTL_MFB_2048 0x0000 | |
135 | #define AX_RX_CTL_MFB_4096 0x0100 | |
136 | #define AX_RX_CTL_MFB_8192 0x0200 | |
137 | #define AX_RX_CTL_MFB_16384 0x0300 | |
138 | ||
139 | #define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO | AX_RX_CTL_AB) | |
933a27d3 DH |
140 | |
141 | /* GPIO 0 .. 2 toggles */ | |
142 | #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ | |
143 | #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ | |
144 | #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ | |
145 | #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ | |
146 | #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ | |
147 | #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ | |
148 | #define AX_GPIO_RESERVED 0x40 /* Reserved */ | |
149 | #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ | |
150 | ||
151 | #define AX_EEPROM_MAGIC 0xdeadbeef | |
152 | #define AX88172_EEPROM_LEN 0x40 | |
153 | #define AX88772_EEPROM_LEN 0xff | |
154 | ||
155 | #define PHY_MODE_MARVELL 0x0000 | |
156 | #define MII_MARVELL_LED_CTRL 0x0018 | |
157 | #define MII_MARVELL_STATUS 0x001b | |
158 | #define MII_MARVELL_CTRL 0x0014 | |
159 | ||
160 | #define MARVELL_LED_MANUAL 0x0019 | |
161 | ||
162 | #define MARVELL_STATUS_HWCFG 0x0004 | |
163 | ||
164 | #define MARVELL_CTRL_TXDELAY 0x0002 | |
165 | #define MARVELL_CTRL_RXDELAY 0x0080 | |
2e55cc72 | 166 | |
3486140e | 167 | #define PHY_MODE_RTL8211CL 0x000C |
610d885d | 168 | |
2e55cc72 | 169 | /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ |
48b1be6a | 170 | struct asix_data { |
2e55cc72 | 171 | u8 multi_filter[AX_MCAST_FILTER_SIZE]; |
7f29a3ba | 172 | u8 mac_addr[ETH_ALEN]; |
933a27d3 DH |
173 | u8 phymode; |
174 | u8 ledmode; | |
175 | u8 eeprom_len; | |
2e55cc72 DB |
176 | }; |
177 | ||
178 | struct ax88172_int_data { | |
51bf2976 | 179 | __le16 res1; |
2e55cc72 | 180 | u8 link; |
51bf2976 | 181 | __le16 res2; |
2e55cc72 | 182 | u8 status; |
51bf2976 | 183 | __le16 res3; |
ba2d3587 | 184 | } __packed; |
2e55cc72 | 185 | |
48b1be6a | 186 | static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
187 | u16 size, void *data) |
188 | { | |
51bf2976 AV |
189 | void *buf; |
190 | int err = -ENOMEM; | |
191 | ||
60b86755 JP |
192 | netdev_dbg(dev->net, "asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
193 | cmd, value, index, size); | |
51bf2976 AV |
194 | |
195 | buf = kmalloc(size, GFP_KERNEL); | |
196 | if (!buf) | |
197 | goto out; | |
198 | ||
199 | err = usb_control_msg( | |
2e55cc72 DB |
200 | dev->udev, |
201 | usb_rcvctrlpipe(dev->udev, 0), | |
202 | cmd, | |
203 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
204 | value, | |
205 | index, | |
51bf2976 | 206 | buf, |
2e55cc72 DB |
207 | size, |
208 | USB_CTRL_GET_TIMEOUT); | |
94d43363 | 209 | if (err == size) |
51bf2976 | 210 | memcpy(data, buf, size); |
94d43363 RD |
211 | else if (err >= 0) |
212 | err = -EINVAL; | |
51bf2976 AV |
213 | kfree(buf); |
214 | ||
215 | out: | |
216 | return err; | |
2e55cc72 DB |
217 | } |
218 | ||
48b1be6a | 219 | static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
220 | u16 size, void *data) |
221 | { | |
51bf2976 AV |
222 | void *buf = NULL; |
223 | int err = -ENOMEM; | |
224 | ||
60b86755 JP |
225 | netdev_dbg(dev->net, "asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
226 | cmd, value, index, size); | |
51bf2976 AV |
227 | |
228 | if (data) { | |
99bf2366 | 229 | buf = kmemdup(data, size, GFP_KERNEL); |
51bf2976 AV |
230 | if (!buf) |
231 | goto out; | |
51bf2976 AV |
232 | } |
233 | ||
234 | err = usb_control_msg( | |
2e55cc72 DB |
235 | dev->udev, |
236 | usb_sndctrlpipe(dev->udev, 0), | |
237 | cmd, | |
238 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
239 | value, | |
240 | index, | |
51bf2976 | 241 | buf, |
2e55cc72 DB |
242 | size, |
243 | USB_CTRL_SET_TIMEOUT); | |
51bf2976 AV |
244 | kfree(buf); |
245 | ||
246 | out: | |
247 | return err; | |
2e55cc72 DB |
248 | } |
249 | ||
7d12e780 | 250 | static void asix_async_cmd_callback(struct urb *urb) |
2e55cc72 DB |
251 | { |
252 | struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context; | |
c94cb314 | 253 | int status = urb->status; |
2e55cc72 | 254 | |
c94cb314 | 255 | if (status < 0) |
48b1be6a | 256 | printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d", |
c94cb314 | 257 | status); |
2e55cc72 DB |
258 | |
259 | kfree(req); | |
260 | usb_free_urb(urb); | |
261 | } | |
262 | ||
933a27d3 DH |
263 | static void |
264 | asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index, | |
265 | u16 size, void *data) | |
266 | { | |
267 | struct usb_ctrlrequest *req; | |
268 | int status; | |
269 | struct urb *urb; | |
270 | ||
60b86755 JP |
271 | netdev_dbg(dev->net, "asix_write_cmd_async() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", |
272 | cmd, value, index, size); | |
83e1b918 GG |
273 | |
274 | urb = usb_alloc_urb(0, GFP_ATOMIC); | |
275 | if (!urb) { | |
60b86755 | 276 | netdev_err(dev->net, "Error allocating URB in write_cmd_async!\n"); |
933a27d3 DH |
277 | return; |
278 | } | |
279 | ||
83e1b918 GG |
280 | req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC); |
281 | if (!req) { | |
60b86755 | 282 | netdev_err(dev->net, "Failed to allocate memory for control request\n"); |
933a27d3 DH |
283 | usb_free_urb(urb); |
284 | return; | |
285 | } | |
286 | ||
287 | req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE; | |
288 | req->bRequest = cmd; | |
9aa742ef ON |
289 | req->wValue = cpu_to_le16(value); |
290 | req->wIndex = cpu_to_le16(index); | |
291 | req->wLength = cpu_to_le16(size); | |
933a27d3 DH |
292 | |
293 | usb_fill_control_urb(urb, dev->udev, | |
294 | usb_sndctrlpipe(dev->udev, 0), | |
295 | (void *)req, data, size, | |
296 | asix_async_cmd_callback, req); | |
297 | ||
83e1b918 GG |
298 | status = usb_submit_urb(urb, GFP_ATOMIC); |
299 | if (status < 0) { | |
60b86755 JP |
300 | netdev_err(dev->net, "Error submitting the control message: status=%d\n", |
301 | status); | |
933a27d3 DH |
302 | kfree(req); |
303 | usb_free_urb(urb); | |
304 | } | |
305 | } | |
306 | ||
307 | static int asix_rx_fixup(struct usbnet *dev, struct sk_buff *skb) | |
308 | { | |
a9e0aca4 | 309 | int offset = 0; |
933a27d3 | 310 | |
a9e0aca4 ED |
311 | while (offset + sizeof(u32) < skb->len) { |
312 | struct sk_buff *ax_skb; | |
313 | u16 size; | |
314 | u32 header = get_unaligned_le32(skb->data + offset); | |
933a27d3 | 315 | |
a9e0aca4 | 316 | offset += sizeof(u32); |
bc466e67 | 317 | |
933a27d3 | 318 | /* get the packet length */ |
a9e0aca4 ED |
319 | size = (u16) (header & 0x7ff); |
320 | if (size != ((~header >> 16) & 0x07ff)) { | |
321 | netdev_err(dev->net, "asix_rx_fixup() Bad Header Length\n"); | |
322 | return 0; | |
3f78d1f2 NJ |
323 | } |
324 | ||
9dae3100 | 325 | if ((size > dev->net->mtu + ETH_HLEN + VLAN_HLEN) || |
a9e0aca4 | 326 | (size + offset > skb->len)) { |
60b86755 JP |
327 | netdev_err(dev->net, "asix_rx_fixup() Bad RX Length %d\n", |
328 | size); | |
933a27d3 DH |
329 | return 0; |
330 | } | |
a9e0aca4 ED |
331 | ax_skb = netdev_alloc_skb_ip_align(dev->net, size); |
332 | if (!ax_skb) | |
933a27d3 | 333 | return 0; |
933a27d3 | 334 | |
a9e0aca4 ED |
335 | skb_put(ax_skb, size); |
336 | memcpy(ax_skb->data, skb->data + offset, size); | |
337 | usbnet_skb_return(dev, ax_skb); | |
933a27d3 | 338 | |
a9e0aca4 | 339 | offset += (size + 1) & 0xfffe; |
933a27d3 DH |
340 | } |
341 | ||
a9e0aca4 | 342 | if (skb->len != offset) { |
60b86755 JP |
343 | netdev_err(dev->net, "asix_rx_fixup() Bad SKB Length %d\n", |
344 | skb->len); | |
933a27d3 DH |
345 | return 0; |
346 | } | |
347 | return 1; | |
348 | } | |
349 | ||
350 | static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb, | |
351 | gfp_t flags) | |
352 | { | |
353 | int padlen; | |
354 | int headroom = skb_headroom(skb); | |
355 | int tailroom = skb_tailroom(skb); | |
356 | u32 packet_len; | |
357 | u32 padbytes = 0xffff0000; | |
358 | ||
2a580949 | 359 | padlen = ((skb->len + 4) & (dev->maxpacket - 1)) ? 0 : 4; |
933a27d3 | 360 | |
8e95a202 JP |
361 | if ((!skb_cloned(skb)) && |
362 | ((headroom + tailroom) >= (4 + padlen))) { | |
933a27d3 DH |
363 | if ((headroom < 4) || (tailroom < padlen)) { |
364 | skb->data = memmove(skb->head + 4, skb->data, skb->len); | |
27a884dc | 365 | skb_set_tail_pointer(skb, skb->len); |
933a27d3 DH |
366 | } |
367 | } else { | |
368 | struct sk_buff *skb2; | |
369 | skb2 = skb_copy_expand(skb, 4, padlen, flags); | |
370 | dev_kfree_skb_any(skb); | |
371 | skb = skb2; | |
372 | if (!skb) | |
373 | return NULL; | |
374 | } | |
375 | ||
376 | skb_push(skb, 4); | |
377 | packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4); | |
57e4f041 | 378 | cpu_to_le32s(&packet_len); |
27d7ff46 | 379 | skb_copy_to_linear_data(skb, &packet_len, sizeof(packet_len)); |
933a27d3 | 380 | |
2a580949 | 381 | if (padlen) { |
57e4f041 | 382 | cpu_to_le32s(&padbytes); |
27a884dc | 383 | memcpy(skb_tail_pointer(skb), &padbytes, sizeof(padbytes)); |
933a27d3 DH |
384 | skb_put(skb, sizeof(padbytes)); |
385 | } | |
386 | return skb; | |
387 | } | |
388 | ||
389 | static void asix_status(struct usbnet *dev, struct urb *urb) | |
390 | { | |
391 | struct ax88172_int_data *event; | |
392 | int link; | |
393 | ||
394 | if (urb->actual_length < 8) | |
395 | return; | |
396 | ||
397 | event = urb->transfer_buffer; | |
398 | link = event->link & 0x01; | |
399 | if (netif_carrier_ok(dev->net) != link) { | |
400 | if (link) { | |
401 | netif_carrier_on(dev->net); | |
402 | usbnet_defer_kevent (dev, EVENT_LINK_RESET ); | |
403 | } else | |
404 | netif_carrier_off(dev->net); | |
60b86755 | 405 | netdev_dbg(dev->net, "Link Status is: %d\n", link); |
933a27d3 DH |
406 | } |
407 | } | |
408 | ||
48b1be6a DH |
409 | static inline int asix_set_sw_mii(struct usbnet *dev) |
410 | { | |
411 | int ret; | |
412 | ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL); | |
413 | if (ret < 0) | |
60b86755 | 414 | netdev_err(dev->net, "Failed to enable software MII access\n"); |
48b1be6a DH |
415 | return ret; |
416 | } | |
417 | ||
418 | static inline int asix_set_hw_mii(struct usbnet *dev) | |
419 | { | |
420 | int ret; | |
421 | ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL); | |
422 | if (ret < 0) | |
60b86755 | 423 | netdev_err(dev->net, "Failed to enable hardware MII access\n"); |
48b1be6a DH |
424 | return ret; |
425 | } | |
426 | ||
933a27d3 | 427 | static inline int asix_get_phy_addr(struct usbnet *dev) |
48b1be6a | 428 | { |
51bf2976 AV |
429 | u8 buf[2]; |
430 | int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf); | |
48b1be6a | 431 | |
60b86755 | 432 | netdev_dbg(dev->net, "asix_get_phy_addr()\n"); |
933a27d3 | 433 | |
51bf2976 | 434 | if (ret < 0) { |
60b86755 | 435 | netdev_err(dev->net, "Error reading PHYID register: %02x\n", ret); |
51bf2976 | 436 | goto out; |
48b1be6a | 437 | } |
60b86755 JP |
438 | netdev_dbg(dev->net, "asix_get_phy_addr() returning 0x%04x\n", |
439 | *((__le16 *)buf)); | |
51bf2976 AV |
440 | ret = buf[1]; |
441 | ||
442 | out: | |
48b1be6a DH |
443 | return ret; |
444 | } | |
445 | ||
446 | static int asix_sw_reset(struct usbnet *dev, u8 flags) | |
447 | { | |
448 | int ret; | |
449 | ||
450 | ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL); | |
451 | if (ret < 0) | |
60b86755 | 452 | netdev_err(dev->net, "Failed to send software reset: %02x\n", ret); |
933a27d3 DH |
453 | |
454 | return ret; | |
455 | } | |
48b1be6a | 456 | |
933a27d3 DH |
457 | static u16 asix_read_rx_ctl(struct usbnet *dev) |
458 | { | |
51bf2976 AV |
459 | __le16 v; |
460 | int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v); | |
933a27d3 | 461 | |
51bf2976 | 462 | if (ret < 0) { |
60b86755 | 463 | netdev_err(dev->net, "Error reading RX_CTL register: %02x\n", ret); |
51bf2976 | 464 | goto out; |
933a27d3 | 465 | } |
51bf2976 AV |
466 | ret = le16_to_cpu(v); |
467 | out: | |
48b1be6a DH |
468 | return ret; |
469 | } | |
470 | ||
471 | static int asix_write_rx_ctl(struct usbnet *dev, u16 mode) | |
472 | { | |
473 | int ret; | |
474 | ||
60b86755 | 475 | netdev_dbg(dev->net, "asix_write_rx_ctl() - mode = 0x%04x\n", mode); |
48b1be6a DH |
476 | ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL); |
477 | if (ret < 0) | |
60b86755 JP |
478 | netdev_err(dev->net, "Failed to write RX_CTL mode to 0x%04x: %02x\n", |
479 | mode, ret); | |
48b1be6a DH |
480 | |
481 | return ret; | |
482 | } | |
483 | ||
933a27d3 | 484 | static u16 asix_read_medium_status(struct usbnet *dev) |
2e55cc72 | 485 | { |
51bf2976 AV |
486 | __le16 v; |
487 | int ret = asix_read_cmd(dev, AX_CMD_READ_MEDIUM_STATUS, 0, 0, 2, &v); | |
2e55cc72 | 488 | |
51bf2976 | 489 | if (ret < 0) { |
60b86755 JP |
490 | netdev_err(dev->net, "Error reading Medium Status register: %02x\n", |
491 | ret); | |
83e1b918 | 492 | return ret; /* TODO: callers not checking for error ret */ |
2e55cc72 | 493 | } |
83e1b918 GG |
494 | |
495 | return le16_to_cpu(v); | |
496 | ||
2e55cc72 DB |
497 | } |
498 | ||
933a27d3 | 499 | static int asix_write_medium_mode(struct usbnet *dev, u16 mode) |
2e55cc72 | 500 | { |
933a27d3 | 501 | int ret; |
2e55cc72 | 502 | |
60b86755 | 503 | netdev_dbg(dev->net, "asix_write_medium_mode() - mode = 0x%04x\n", mode); |
933a27d3 DH |
504 | ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL); |
505 | if (ret < 0) | |
60b86755 JP |
506 | netdev_err(dev->net, "Failed to write Medium Mode mode to 0x%04x: %02x\n", |
507 | mode, ret); | |
2e55cc72 | 508 | |
933a27d3 DH |
509 | return ret; |
510 | } | |
2e55cc72 | 511 | |
933a27d3 DH |
512 | static int asix_write_gpio(struct usbnet *dev, u16 value, int sleep) |
513 | { | |
514 | int ret; | |
2e55cc72 | 515 | |
60b86755 | 516 | netdev_dbg(dev->net, "asix_write_gpio() - value = 0x%04x\n", value); |
933a27d3 DH |
517 | ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL); |
518 | if (ret < 0) | |
60b86755 JP |
519 | netdev_err(dev->net, "Failed to write GPIO value 0x%04x: %02x\n", |
520 | value, ret); | |
2e55cc72 | 521 | |
933a27d3 DH |
522 | if (sleep) |
523 | msleep(sleep); | |
524 | ||
525 | return ret; | |
2e55cc72 DB |
526 | } |
527 | ||
933a27d3 DH |
528 | /* |
529 | * AX88772 & AX88178 have a 16-bit RX_CTL value | |
530 | */ | |
48b1be6a | 531 | static void asix_set_multicast(struct net_device *net) |
2e55cc72 DB |
532 | { |
533 | struct usbnet *dev = netdev_priv(net); | |
48b1be6a | 534 | struct asix_data *data = (struct asix_data *)&dev->data; |
933a27d3 | 535 | u16 rx_ctl = AX_DEFAULT_RX_CTL; |
2e55cc72 DB |
536 | |
537 | if (net->flags & IFF_PROMISC) { | |
933a27d3 | 538 | rx_ctl |= AX_RX_CTL_PRO; |
8e95a202 | 539 | } else if (net->flags & IFF_ALLMULTI || |
4cd24eaf | 540 | netdev_mc_count(net) > AX_MAX_MCAST) { |
933a27d3 | 541 | rx_ctl |= AX_RX_CTL_AMALL; |
4cd24eaf | 542 | } else if (netdev_mc_empty(net)) { |
2e55cc72 DB |
543 | /* just broadcast and directed */ |
544 | } else { | |
545 | /* We use the 20 byte dev->data | |
546 | * for our 8 byte filter buffer | |
547 | * to avoid allocating memory that | |
548 | * is tricky to free later */ | |
22bedad3 | 549 | struct netdev_hw_addr *ha; |
2e55cc72 | 550 | u32 crc_bits; |
2e55cc72 DB |
551 | |
552 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
553 | ||
554 | /* Build the multicast hash filter. */ | |
22bedad3 JP |
555 | netdev_for_each_mc_addr(ha, net) { |
556 | crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
2e55cc72 DB |
557 | data->multi_filter[crc_bits >> 3] |= |
558 | 1 << (crc_bits & 7); | |
2e55cc72 DB |
559 | } |
560 | ||
48b1be6a | 561 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, |
2e55cc72 DB |
562 | AX_MCAST_FILTER_SIZE, data->multi_filter); |
563 | ||
933a27d3 | 564 | rx_ctl |= AX_RX_CTL_AM; |
2e55cc72 DB |
565 | } |
566 | ||
48b1be6a | 567 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); |
2e55cc72 DB |
568 | } |
569 | ||
48b1be6a | 570 | static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc) |
2e55cc72 DB |
571 | { |
572 | struct usbnet *dev = netdev_priv(netdev); | |
51bf2976 | 573 | __le16 res; |
2e55cc72 | 574 | |
a9fc6338 | 575 | mutex_lock(&dev->phy_mutex); |
48b1be6a DH |
576 | asix_set_sw_mii(dev); |
577 | asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, | |
51bf2976 | 578 | (__u16)loc, 2, &res); |
48b1be6a | 579 | asix_set_hw_mii(dev); |
a9fc6338 | 580 | mutex_unlock(&dev->phy_mutex); |
2e55cc72 | 581 | |
60b86755 JP |
582 | netdev_dbg(dev->net, "asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", |
583 | phy_id, loc, le16_to_cpu(res)); | |
2e55cc72 | 584 | |
51bf2976 | 585 | return le16_to_cpu(res); |
2e55cc72 DB |
586 | } |
587 | ||
588 | static void | |
48b1be6a | 589 | asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val) |
2e55cc72 DB |
590 | { |
591 | struct usbnet *dev = netdev_priv(netdev); | |
51bf2976 | 592 | __le16 res = cpu_to_le16(val); |
2e55cc72 | 593 | |
60b86755 JP |
594 | netdev_dbg(dev->net, "asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n", |
595 | phy_id, loc, val); | |
a9fc6338 | 596 | mutex_lock(&dev->phy_mutex); |
48b1be6a | 597 | asix_set_sw_mii(dev); |
51bf2976 | 598 | asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res); |
48b1be6a | 599 | asix_set_hw_mii(dev); |
a9fc6338 | 600 | mutex_unlock(&dev->phy_mutex); |
2e55cc72 DB |
601 | } |
602 | ||
933a27d3 DH |
603 | /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ |
604 | static u32 asix_get_phyid(struct usbnet *dev) | |
2e55cc72 | 605 | { |
933a27d3 DH |
606 | int phy_reg; |
607 | u32 phy_id; | |
a77929a2 | 608 | int i; |
2e55cc72 | 609 | |
a77929a2 GG |
610 | /* Poll for the rare case the FW or phy isn't ready yet. */ |
611 | for (i = 0; i < 100; i++) { | |
612 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); | |
613 | if (phy_reg != 0 && phy_reg != 0xFFFF) | |
614 | break; | |
615 | mdelay(1); | |
616 | } | |
617 | ||
618 | if (phy_reg <= 0 || phy_reg == 0xFFFF) | |
933a27d3 | 619 | return 0; |
2e55cc72 | 620 | |
933a27d3 | 621 | phy_id = (phy_reg & 0xffff) << 16; |
2e55cc72 | 622 | |
933a27d3 DH |
623 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); |
624 | if (phy_reg < 0) | |
625 | return 0; | |
626 | ||
627 | phy_id |= (phy_reg & 0xffff); | |
628 | ||
629 | return phy_id; | |
2e55cc72 DB |
630 | } |
631 | ||
632 | static void | |
48b1be6a | 633 | asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
634 | { |
635 | struct usbnet *dev = netdev_priv(net); | |
636 | u8 opt; | |
637 | ||
48b1be6a | 638 | if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) { |
2e55cc72 DB |
639 | wolinfo->supported = 0; |
640 | wolinfo->wolopts = 0; | |
641 | return; | |
642 | } | |
643 | wolinfo->supported = WAKE_PHY | WAKE_MAGIC; | |
644 | wolinfo->wolopts = 0; | |
f87ce5b2 | 645 | if (opt & AX_MONITOR_LINK) |
646 | wolinfo->wolopts |= WAKE_PHY; | |
647 | if (opt & AX_MONITOR_MAGIC) | |
648 | wolinfo->wolopts |= WAKE_MAGIC; | |
2e55cc72 DB |
649 | } |
650 | ||
651 | static int | |
48b1be6a | 652 | asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
653 | { |
654 | struct usbnet *dev = netdev_priv(net); | |
655 | u8 opt = 0; | |
2e55cc72 DB |
656 | |
657 | if (wolinfo->wolopts & WAKE_PHY) | |
658 | opt |= AX_MONITOR_LINK; | |
659 | if (wolinfo->wolopts & WAKE_MAGIC) | |
660 | opt |= AX_MONITOR_MAGIC; | |
2e55cc72 | 661 | |
48b1be6a | 662 | if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE, |
51bf2976 | 663 | opt, 0, 0, NULL) < 0) |
2e55cc72 DB |
664 | return -EINVAL; |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
48b1be6a | 669 | static int asix_get_eeprom_len(struct net_device *net) |
2e55cc72 | 670 | { |
933a27d3 DH |
671 | struct usbnet *dev = netdev_priv(net); |
672 | struct asix_data *data = (struct asix_data *)&dev->data; | |
673 | ||
674 | return data->eeprom_len; | |
2e55cc72 DB |
675 | } |
676 | ||
48b1be6a | 677 | static int asix_get_eeprom(struct net_device *net, |
2e55cc72 DB |
678 | struct ethtool_eeprom *eeprom, u8 *data) |
679 | { | |
680 | struct usbnet *dev = netdev_priv(net); | |
51bf2976 | 681 | __le16 *ebuf = (__le16 *)data; |
2e55cc72 DB |
682 | int i; |
683 | ||
684 | /* Crude hack to ensure that we don't overwrite memory | |
685 | * if an odd length is supplied | |
686 | */ | |
687 | if (eeprom->len % 2) | |
688 | return -EINVAL; | |
689 | ||
690 | eeprom->magic = AX_EEPROM_MAGIC; | |
691 | ||
692 | /* ax8817x returns 2 bytes from eeprom on read */ | |
693 | for (i=0; i < eeprom->len / 2; i++) { | |
48b1be6a | 694 | if (asix_read_cmd(dev, AX_CMD_READ_EEPROM, |
2e55cc72 DB |
695 | eeprom->offset + i, 0, 2, &ebuf[i]) < 0) |
696 | return -EINVAL; | |
697 | } | |
698 | return 0; | |
699 | } | |
700 | ||
48b1be6a | 701 | static void asix_get_drvinfo (struct net_device *net, |
2e55cc72 DB |
702 | struct ethtool_drvinfo *info) |
703 | { | |
933a27d3 DH |
704 | struct usbnet *dev = netdev_priv(net); |
705 | struct asix_data *data = (struct asix_data *)&dev->data; | |
706 | ||
2e55cc72 DB |
707 | /* Inherit standard device info */ |
708 | usbnet_get_drvinfo(net, info); | |
83e1b918 | 709 | strncpy (info->driver, DRIVER_NAME, sizeof info->driver); |
933a27d3 DH |
710 | strncpy (info->version, DRIVER_VERSION, sizeof info->version); |
711 | info->eedump_len = data->eeprom_len; | |
2e55cc72 DB |
712 | } |
713 | ||
933a27d3 DH |
714 | static u32 asix_get_link(struct net_device *net) |
715 | { | |
716 | struct usbnet *dev = netdev_priv(net); | |
717 | ||
718 | return mii_link_ok(&dev->mii); | |
719 | } | |
720 | ||
721 | static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) | |
722 | { | |
723 | struct usbnet *dev = netdev_priv(net); | |
724 | ||
725 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
726 | } | |
727 | ||
7f29a3ba JK |
728 | static int asix_set_mac_address(struct net_device *net, void *p) |
729 | { | |
730 | struct usbnet *dev = netdev_priv(net); | |
731 | struct asix_data *data = (struct asix_data *)&dev->data; | |
732 | struct sockaddr *addr = p; | |
733 | ||
734 | if (netif_running(net)) | |
735 | return -EBUSY; | |
736 | if (!is_valid_ether_addr(addr->sa_data)) | |
737 | return -EADDRNOTAVAIL; | |
738 | ||
739 | memcpy(net->dev_addr, addr->sa_data, ETH_ALEN); | |
740 | ||
741 | /* We use the 20 byte dev->data | |
742 | * for our 6 byte mac buffer | |
743 | * to avoid allocating memory that | |
744 | * is tricky to free later */ | |
745 | memcpy(data->mac_addr, addr->sa_data, ETH_ALEN); | |
746 | asix_write_cmd_async(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, | |
747 | data->mac_addr); | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
933a27d3 DH |
752 | /* We need to override some ethtool_ops so we require our |
753 | own structure so we don't interfere with other usbnet | |
754 | devices that may be connected at the same time. */ | |
0fc0b732 | 755 | static const struct ethtool_ops ax88172_ethtool_ops = { |
933a27d3 DH |
756 | .get_drvinfo = asix_get_drvinfo, |
757 | .get_link = asix_get_link, | |
933a27d3 | 758 | .get_msglevel = usbnet_get_msglevel, |
2e55cc72 | 759 | .set_msglevel = usbnet_set_msglevel, |
48b1be6a DH |
760 | .get_wol = asix_get_wol, |
761 | .set_wol = asix_set_wol, | |
762 | .get_eeprom_len = asix_get_eeprom_len, | |
763 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
764 | .get_settings = usbnet_get_settings, |
765 | .set_settings = usbnet_set_settings, | |
766 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
767 | }; |
768 | ||
933a27d3 | 769 | static void ax88172_set_multicast(struct net_device *net) |
2e55cc72 DB |
770 | { |
771 | struct usbnet *dev = netdev_priv(net); | |
933a27d3 DH |
772 | struct asix_data *data = (struct asix_data *)&dev->data; |
773 | u8 rx_ctl = 0x8c; | |
2e55cc72 | 774 | |
933a27d3 DH |
775 | if (net->flags & IFF_PROMISC) { |
776 | rx_ctl |= 0x01; | |
8e95a202 | 777 | } else if (net->flags & IFF_ALLMULTI || |
4cd24eaf | 778 | netdev_mc_count(net) > AX_MAX_MCAST) { |
933a27d3 | 779 | rx_ctl |= 0x02; |
4cd24eaf | 780 | } else if (netdev_mc_empty(net)) { |
933a27d3 DH |
781 | /* just broadcast and directed */ |
782 | } else { | |
783 | /* We use the 20 byte dev->data | |
784 | * for our 8 byte filter buffer | |
785 | * to avoid allocating memory that | |
786 | * is tricky to free later */ | |
22bedad3 | 787 | struct netdev_hw_addr *ha; |
933a27d3 | 788 | u32 crc_bits; |
933a27d3 DH |
789 | |
790 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
791 | ||
792 | /* Build the multicast hash filter. */ | |
22bedad3 JP |
793 | netdev_for_each_mc_addr(ha, net) { |
794 | crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
933a27d3 DH |
795 | data->multi_filter[crc_bits >> 3] |= |
796 | 1 << (crc_bits & 7); | |
933a27d3 DH |
797 | } |
798 | ||
799 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, | |
800 | AX_MCAST_FILTER_SIZE, data->multi_filter); | |
801 | ||
802 | rx_ctl |= 0x10; | |
803 | } | |
804 | ||
805 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); | |
806 | } | |
807 | ||
808 | static int ax88172_link_reset(struct usbnet *dev) | |
809 | { | |
810 | u8 mode; | |
8ae6daca | 811 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
933a27d3 DH |
812 | |
813 | mii_check_media(&dev->mii, 1, 1); | |
814 | mii_ethtool_gset(&dev->mii, &ecmd); | |
815 | mode = AX88172_MEDIUM_DEFAULT; | |
816 | ||
817 | if (ecmd.duplex != DUPLEX_FULL) | |
818 | mode |= ~AX88172_MEDIUM_FD; | |
819 | ||
8ae6daca DD |
820 | netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", |
821 | ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); | |
933a27d3 DH |
822 | |
823 | asix_write_medium_mode(dev, mode); | |
824 | ||
825 | return 0; | |
2e55cc72 DB |
826 | } |
827 | ||
1703338c SH |
828 | static const struct net_device_ops ax88172_netdev_ops = { |
829 | .ndo_open = usbnet_open, | |
830 | .ndo_stop = usbnet_stop, | |
831 | .ndo_start_xmit = usbnet_start_xmit, | |
832 | .ndo_tx_timeout = usbnet_tx_timeout, | |
833 | .ndo_change_mtu = usbnet_change_mtu, | |
834 | .ndo_set_mac_address = eth_mac_addr, | |
835 | .ndo_validate_addr = eth_validate_addr, | |
836 | .ndo_do_ioctl = asix_ioctl, | |
afc4b13d | 837 | .ndo_set_rx_mode = ax88172_set_multicast, |
1703338c SH |
838 | }; |
839 | ||
48b1be6a | 840 | static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) |
2e55cc72 DB |
841 | { |
842 | int ret = 0; | |
51bf2976 | 843 | u8 buf[ETH_ALEN]; |
2e55cc72 DB |
844 | int i; |
845 | unsigned long gpio_bits = dev->driver_info->data; | |
933a27d3 DH |
846 | struct asix_data *data = (struct asix_data *)&dev->data; |
847 | ||
848 | data->eeprom_len = AX88172_EEPROM_LEN; | |
2e55cc72 DB |
849 | |
850 | usbnet_get_endpoints(dev,intf); | |
851 | ||
2e55cc72 DB |
852 | /* Toggle the GPIOs in a manufacturer/model specific way */ |
853 | for (i = 2; i >= 0; i--) { | |
83e1b918 GG |
854 | ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, |
855 | (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL); | |
856 | if (ret < 0) | |
51bf2976 | 857 | goto out; |
2e55cc72 DB |
858 | msleep(5); |
859 | } | |
860 | ||
83e1b918 GG |
861 | ret = asix_write_rx_ctl(dev, 0x80); |
862 | if (ret < 0) | |
51bf2976 | 863 | goto out; |
2e55cc72 DB |
864 | |
865 | /* Get the MAC address */ | |
83e1b918 GG |
866 | ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); |
867 | if (ret < 0) { | |
2e55cc72 | 868 | dbg("read AX_CMD_READ_NODE_ID failed: %d", ret); |
51bf2976 | 869 | goto out; |
2e55cc72 DB |
870 | } |
871 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
872 | ||
2e55cc72 DB |
873 | /* Initialize MII structure */ |
874 | dev->mii.dev = dev->net; | |
48b1be6a DH |
875 | dev->mii.mdio_read = asix_mdio_read; |
876 | dev->mii.mdio_write = asix_mdio_write; | |
2e55cc72 DB |
877 | dev->mii.phy_id_mask = 0x3f; |
878 | dev->mii.reg_num_mask = 0x1f; | |
933a27d3 | 879 | dev->mii.phy_id = asix_get_phy_addr(dev); |
2e55cc72 | 880 | |
1703338c | 881 | dev->net->netdev_ops = &ax88172_netdev_ops; |
48b1be6a | 882 | dev->net->ethtool_ops = &ax88172_ethtool_ops; |
2e55cc72 | 883 | |
933a27d3 DH |
884 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
885 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
886 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); |
887 | mii_nway_restart(&dev->mii); | |
888 | ||
889 | return 0; | |
51bf2976 AV |
890 | |
891 | out: | |
2e55cc72 DB |
892 | return ret; |
893 | } | |
894 | ||
0fc0b732 | 895 | static const struct ethtool_ops ax88772_ethtool_ops = { |
48b1be6a | 896 | .get_drvinfo = asix_get_drvinfo, |
933a27d3 | 897 | .get_link = asix_get_link, |
2e55cc72 DB |
898 | .get_msglevel = usbnet_get_msglevel, |
899 | .set_msglevel = usbnet_set_msglevel, | |
48b1be6a DH |
900 | .get_wol = asix_get_wol, |
901 | .set_wol = asix_set_wol, | |
902 | .get_eeprom_len = asix_get_eeprom_len, | |
903 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
904 | .get_settings = usbnet_get_settings, |
905 | .set_settings = usbnet_set_settings, | |
906 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
907 | }; |
908 | ||
933a27d3 DH |
909 | static int ax88772_link_reset(struct usbnet *dev) |
910 | { | |
911 | u16 mode; | |
8ae6daca | 912 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
933a27d3 DH |
913 | |
914 | mii_check_media(&dev->mii, 1, 1); | |
915 | mii_ethtool_gset(&dev->mii, &ecmd); | |
916 | mode = AX88772_MEDIUM_DEFAULT; | |
917 | ||
8ae6daca | 918 | if (ethtool_cmd_speed(&ecmd) != SPEED_100) |
933a27d3 DH |
919 | mode &= ~AX_MEDIUM_PS; |
920 | ||
921 | if (ecmd.duplex != DUPLEX_FULL) | |
922 | mode &= ~AX_MEDIUM_FD; | |
923 | ||
8ae6daca DD |
924 | netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", |
925 | ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); | |
933a27d3 DH |
926 | |
927 | asix_write_medium_mode(dev, mode); | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
4ad1438f | 932 | static int ax88772_reset(struct usbnet *dev) |
2e55cc72 | 933 | { |
8ef66bdc | 934 | struct asix_data *data = (struct asix_data *)&dev->data; |
d0ffff8f | 935 | int ret, embd_phy; |
933a27d3 | 936 | u16 rx_ctl; |
2e55cc72 | 937 | |
83e1b918 GG |
938 | ret = asix_write_gpio(dev, |
939 | AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5); | |
940 | if (ret < 0) | |
51bf2976 | 941 | goto out; |
2e55cc72 | 942 | |
d0ffff8f | 943 | embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); |
4ad1438f | 944 | |
83e1b918 GG |
945 | ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); |
946 | if (ret < 0) { | |
2e55cc72 | 947 | dbg("Select PHY #1 failed: %d", ret); |
51bf2976 | 948 | goto out; |
2e55cc72 DB |
949 | } |
950 | ||
83e1b918 GG |
951 | ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL); |
952 | if (ret < 0) | |
51bf2976 | 953 | goto out; |
2e55cc72 DB |
954 | |
955 | msleep(150); | |
83e1b918 GG |
956 | |
957 | ret = asix_sw_reset(dev, AX_SWRESET_CLEAR); | |
958 | if (ret < 0) | |
51bf2976 | 959 | goto out; |
2e55cc72 DB |
960 | |
961 | msleep(150); | |
4ad1438f | 962 | |
d0ffff8f | 963 | if (embd_phy) { |
83e1b918 GG |
964 | ret = asix_sw_reset(dev, AX_SWRESET_IPRL); |
965 | if (ret < 0) | |
51bf2976 | 966 | goto out; |
83e1b918 GG |
967 | } else { |
968 | ret = asix_sw_reset(dev, AX_SWRESET_PRTE); | |
969 | if (ret < 0) | |
51bf2976 | 970 | goto out; |
d0ffff8f | 971 | } |
2e55cc72 DB |
972 | |
973 | msleep(150); | |
933a27d3 DH |
974 | rx_ctl = asix_read_rx_ctl(dev); |
975 | dbg("RX_CTL is 0x%04x after software reset", rx_ctl); | |
83e1b918 GG |
976 | ret = asix_write_rx_ctl(dev, 0x0000); |
977 | if (ret < 0) | |
51bf2976 | 978 | goto out; |
2e55cc72 | 979 | |
933a27d3 DH |
980 | rx_ctl = asix_read_rx_ctl(dev); |
981 | dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl); | |
982 | ||
83e1b918 GG |
983 | ret = asix_sw_reset(dev, AX_SWRESET_PRL); |
984 | if (ret < 0) | |
51bf2976 | 985 | goto out; |
2e55cc72 | 986 | |
2e55cc72 | 987 | msleep(150); |
48b1be6a | 988 | |
83e1b918 GG |
989 | ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL); |
990 | if (ret < 0) | |
51bf2976 | 991 | goto out; |
2e55cc72 | 992 | |
48b1be6a | 993 | msleep(150); |
2e55cc72 | 994 | |
933a27d3 DH |
995 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
996 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
997 | ADVERTISE_ALL | ADVERTISE_CSMA); |
998 | mii_nway_restart(&dev->mii); | |
999 | ||
83e1b918 GG |
1000 | ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT); |
1001 | if (ret < 0) | |
51bf2976 | 1002 | goto out; |
2e55cc72 | 1003 | |
83e1b918 | 1004 | ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, |
2e55cc72 | 1005 | AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, |
83e1b918 GG |
1006 | AX88772_IPG2_DEFAULT, 0, NULL); |
1007 | if (ret < 0) { | |
2e55cc72 | 1008 | dbg("Write IPG,IPG1,IPG2 failed: %d", ret); |
51bf2976 | 1009 | goto out; |
2e55cc72 | 1010 | } |
2e55cc72 | 1011 | |
8ef66bdc JK |
1012 | /* Rewrite MAC address */ |
1013 | memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); | |
1014 | ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, | |
1015 | data->mac_addr); | |
1016 | if (ret < 0) | |
1017 | goto out; | |
1018 | ||
2e55cc72 | 1019 | /* Set RX_CTL to default values with 2k buffer, and enable cactus */ |
83e1b918 GG |
1020 | ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL); |
1021 | if (ret < 0) | |
51bf2976 | 1022 | goto out; |
2e55cc72 | 1023 | |
933a27d3 DH |
1024 | rx_ctl = asix_read_rx_ctl(dev); |
1025 | dbg("RX_CTL is 0x%04x after all initializations", rx_ctl); | |
1026 | ||
1027 | rx_ctl = asix_read_medium_status(dev); | |
1028 | dbg("Medium Status is 0x%04x after all initializations", rx_ctl); | |
1029 | ||
4ad1438f GG |
1030 | return 0; |
1031 | ||
1032 | out: | |
1033 | return ret; | |
1034 | ||
1035 | } | |
1036 | ||
1037 | static const struct net_device_ops ax88772_netdev_ops = { | |
1038 | .ndo_open = usbnet_open, | |
1039 | .ndo_stop = usbnet_stop, | |
1040 | .ndo_start_xmit = usbnet_start_xmit, | |
1041 | .ndo_tx_timeout = usbnet_tx_timeout, | |
1042 | .ndo_change_mtu = usbnet_change_mtu, | |
1043 | .ndo_set_mac_address = asix_set_mac_address, | |
1044 | .ndo_validate_addr = eth_validate_addr, | |
1045 | .ndo_do_ioctl = asix_ioctl, | |
1046 | .ndo_set_rx_mode = asix_set_multicast, | |
1047 | }; | |
1048 | ||
1049 | static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) | |
1050 | { | |
d3665188 | 1051 | int ret, embd_phy; |
4ad1438f GG |
1052 | struct asix_data *data = (struct asix_data *)&dev->data; |
1053 | u8 buf[ETH_ALEN]; | |
1054 | u32 phyid; | |
1055 | ||
1056 | data->eeprom_len = AX88772_EEPROM_LEN; | |
1057 | ||
1058 | usbnet_get_endpoints(dev,intf); | |
1059 | ||
1060 | /* Get the MAC address */ | |
83e1b918 GG |
1061 | ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); |
1062 | if (ret < 0) { | |
4ad1438f | 1063 | dbg("Failed to read MAC address: %d", ret); |
83e1b918 | 1064 | return ret; |
4ad1438f GG |
1065 | } |
1066 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
1067 | ||
1068 | /* Initialize MII structure */ | |
1069 | dev->mii.dev = dev->net; | |
1070 | dev->mii.mdio_read = asix_mdio_read; | |
1071 | dev->mii.mdio_write = asix_mdio_write; | |
1072 | dev->mii.phy_id_mask = 0x1f; | |
1073 | dev->mii.reg_num_mask = 0x1f; | |
1074 | dev->mii.phy_id = asix_get_phy_addr(dev); | |
1075 | ||
4ad1438f GG |
1076 | dev->net->netdev_ops = &ax88772_netdev_ops; |
1077 | dev->net->ethtool_ops = &ax88772_ethtool_ops; | |
1078 | ||
d3665188 GG |
1079 | embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); |
1080 | ||
1081 | /* Reset the PHY to normal operation mode */ | |
1082 | ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); | |
1083 | if (ret < 0) { | |
1084 | dbg("Select PHY #1 failed: %d", ret); | |
1085 | return ret; | |
1086 | } | |
1087 | ||
1088 | ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL); | |
83e1b918 GG |
1089 | if (ret < 0) |
1090 | return ret; | |
4ad1438f | 1091 | |
d3665188 GG |
1092 | msleep(150); |
1093 | ||
1094 | ret = asix_sw_reset(dev, AX_SWRESET_CLEAR); | |
1095 | if (ret < 0) | |
1096 | return ret; | |
1097 | ||
1098 | msleep(150); | |
1099 | ||
1100 | ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE); | |
1101 | ||
1102 | /* Read PHYID register *AFTER* the PHY was reset properly */ | |
1103 | phyid = asix_get_phyid(dev); | |
1104 | dbg("PHYID=0x%08x", phyid); | |
1105 | ||
2e55cc72 DB |
1106 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ |
1107 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1108 | /* hard_mtu is still the default - the device does not support | |
1109 | jumbo eth frames */ | |
1110 | dev->rx_urb_size = 2048; | |
1111 | } | |
83e1b918 | 1112 | |
2e55cc72 | 1113 | return 0; |
2e55cc72 DB |
1114 | } |
1115 | ||
bc689c97 | 1116 | static const struct ethtool_ops ax88178_ethtool_ops = { |
933a27d3 DH |
1117 | .get_drvinfo = asix_get_drvinfo, |
1118 | .get_link = asix_get_link, | |
933a27d3 DH |
1119 | .get_msglevel = usbnet_get_msglevel, |
1120 | .set_msglevel = usbnet_set_msglevel, | |
1121 | .get_wol = asix_get_wol, | |
1122 | .set_wol = asix_set_wol, | |
1123 | .get_eeprom_len = asix_get_eeprom_len, | |
1124 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
1125 | .get_settings = usbnet_get_settings, |
1126 | .set_settings = usbnet_set_settings, | |
1127 | .nway_reset = usbnet_nway_reset, | |
933a27d3 DH |
1128 | }; |
1129 | ||
1130 | static int marvell_phy_init(struct usbnet *dev) | |
2e55cc72 | 1131 | { |
933a27d3 DH |
1132 | struct asix_data *data = (struct asix_data *)&dev->data; |
1133 | u16 reg; | |
2e55cc72 | 1134 | |
60b86755 | 1135 | netdev_dbg(dev->net, "marvell_phy_init()\n"); |
2e55cc72 | 1136 | |
933a27d3 | 1137 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); |
60b86755 | 1138 | netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); |
2e55cc72 | 1139 | |
933a27d3 DH |
1140 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, |
1141 | MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); | |
2e55cc72 | 1142 | |
933a27d3 DH |
1143 | if (data->ledmode) { |
1144 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, | |
1145 | MII_MARVELL_LED_CTRL); | |
60b86755 | 1146 | netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); |
2e55cc72 | 1147 | |
933a27d3 DH |
1148 | reg &= 0xf8ff; |
1149 | reg |= (1 + 0x0100); | |
1150 | asix_mdio_write(dev->net, dev->mii.phy_id, | |
1151 | MII_MARVELL_LED_CTRL, reg); | |
2e55cc72 | 1152 | |
933a27d3 DH |
1153 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, |
1154 | MII_MARVELL_LED_CTRL); | |
60b86755 | 1155 | netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); |
933a27d3 DH |
1156 | reg &= 0xfc0f; |
1157 | } | |
2e55cc72 | 1158 | |
933a27d3 DH |
1159 | return 0; |
1160 | } | |
1161 | ||
610d885d GG |
1162 | static int rtl8211cl_phy_init(struct usbnet *dev) |
1163 | { | |
1164 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1165 | ||
1166 | netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); | |
1167 | ||
1168 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); | |
1169 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); | |
1170 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, | |
1171 | asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); | |
1172 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); | |
1173 | ||
1174 | if (data->ledmode == 12) { | |
1175 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); | |
1176 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); | |
1177 | asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); | |
1178 | } | |
1179 | ||
1180 | return 0; | |
1181 | } | |
1182 | ||
933a27d3 DH |
1183 | static int marvell_led_status(struct usbnet *dev, u16 speed) |
1184 | { | |
1185 | u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); | |
1186 | ||
60b86755 | 1187 | netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); |
933a27d3 DH |
1188 | |
1189 | /* Clear out the center LED bits - 0x03F0 */ | |
1190 | reg &= 0xfc0f; | |
1191 | ||
1192 | switch (speed) { | |
1193 | case SPEED_1000: | |
1194 | reg |= 0x03e0; | |
1195 | break; | |
1196 | case SPEED_100: | |
1197 | reg |= 0x03b0; | |
1198 | break; | |
1199 | default: | |
1200 | reg |= 0x02f0; | |
2e55cc72 DB |
1201 | } |
1202 | ||
60b86755 | 1203 | netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); |
933a27d3 DH |
1204 | asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
610d885d GG |
1209 | static int ax88178_reset(struct usbnet *dev) |
1210 | { | |
1211 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1212 | int ret; | |
1213 | __le16 eeprom; | |
1214 | u8 status; | |
1215 | int gpio0 = 0; | |
b2d3ad29 | 1216 | u32 phyid; |
610d885d GG |
1217 | |
1218 | asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status); | |
1219 | dbg("GPIO Status: 0x%04x", status); | |
1220 | ||
1221 | asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL); | |
1222 | asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom); | |
1223 | asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL); | |
1224 | ||
1225 | dbg("EEPROM index 0x17 is 0x%04x", eeprom); | |
1226 | ||
1227 | if (eeprom == cpu_to_le16(0xffff)) { | |
1228 | data->phymode = PHY_MODE_MARVELL; | |
1229 | data->ledmode = 0; | |
1230 | gpio0 = 1; | |
1231 | } else { | |
b2d3ad29 | 1232 | data->phymode = le16_to_cpu(eeprom) & 0x7F; |
610d885d GG |
1233 | data->ledmode = le16_to_cpu(eeprom) >> 8; |
1234 | gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; | |
1235 | } | |
1236 | dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode); | |
1237 | ||
b2d3ad29 | 1238 | /* Power up external GigaPHY through AX88178 GPIO pin */ |
610d885d GG |
1239 | asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40); |
1240 | if ((le16_to_cpu(eeprom) >> 8) != 1) { | |
1241 | asix_write_gpio(dev, 0x003c, 30); | |
1242 | asix_write_gpio(dev, 0x001c, 300); | |
1243 | asix_write_gpio(dev, 0x003c, 30); | |
1244 | } else { | |
1245 | dbg("gpio phymode == 1 path"); | |
1246 | asix_write_gpio(dev, AX_GPIO_GPO1EN, 30); | |
1247 | asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30); | |
1248 | } | |
1249 | ||
b2d3ad29 GG |
1250 | /* Read PHYID register *AFTER* powering up PHY */ |
1251 | phyid = asix_get_phyid(dev); | |
1252 | dbg("PHYID=0x%08x", phyid); | |
1253 | ||
1254 | /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ | |
1255 | asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL); | |
1256 | ||
610d885d GG |
1257 | asix_sw_reset(dev, 0); |
1258 | msleep(150); | |
1259 | ||
1260 | asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); | |
1261 | msleep(150); | |
1262 | ||
1263 | asix_write_rx_ctl(dev, 0); | |
1264 | ||
1265 | if (data->phymode == PHY_MODE_MARVELL) { | |
1266 | marvell_phy_init(dev); | |
1267 | msleep(60); | |
1268 | } else if (data->phymode == PHY_MODE_RTL8211CL) | |
1269 | rtl8211cl_phy_init(dev); | |
1270 | ||
1271 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, | |
1272 | BMCR_RESET | BMCR_ANENABLE); | |
1273 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
1274 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
1275 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, | |
1276 | ADVERTISE_1000FULL); | |
1277 | ||
1278 | mii_nway_restart(&dev->mii); | |
1279 | ||
83e1b918 GG |
1280 | ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT); |
1281 | if (ret < 0) | |
1282 | return ret; | |
610d885d | 1283 | |
71bc5d94 JK |
1284 | /* Rewrite MAC address */ |
1285 | memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); | |
1286 | ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, | |
1287 | data->mac_addr); | |
1288 | if (ret < 0) | |
1289 | return ret; | |
1290 | ||
83e1b918 GG |
1291 | ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL); |
1292 | if (ret < 0) | |
1293 | return ret; | |
610d885d GG |
1294 | |
1295 | return 0; | |
610d885d GG |
1296 | } |
1297 | ||
933a27d3 DH |
1298 | static int ax88178_link_reset(struct usbnet *dev) |
1299 | { | |
1300 | u16 mode; | |
8ae6daca | 1301 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
933a27d3 | 1302 | struct asix_data *data = (struct asix_data *)&dev->data; |
8ae6daca | 1303 | u32 speed; |
933a27d3 | 1304 | |
60b86755 | 1305 | netdev_dbg(dev->net, "ax88178_link_reset()\n"); |
933a27d3 DH |
1306 | |
1307 | mii_check_media(&dev->mii, 1, 1); | |
1308 | mii_ethtool_gset(&dev->mii, &ecmd); | |
1309 | mode = AX88178_MEDIUM_DEFAULT; | |
8ae6daca | 1310 | speed = ethtool_cmd_speed(&ecmd); |
933a27d3 | 1311 | |
8ae6daca | 1312 | if (speed == SPEED_1000) |
a7f75c0c | 1313 | mode |= AX_MEDIUM_GM; |
8ae6daca | 1314 | else if (speed == SPEED_100) |
933a27d3 DH |
1315 | mode |= AX_MEDIUM_PS; |
1316 | else | |
1317 | mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); | |
1318 | ||
a7f75c0c PK |
1319 | mode |= AX_MEDIUM_ENCK; |
1320 | ||
933a27d3 DH |
1321 | if (ecmd.duplex == DUPLEX_FULL) |
1322 | mode |= AX_MEDIUM_FD; | |
1323 | else | |
1324 | mode &= ~AX_MEDIUM_FD; | |
1325 | ||
8ae6daca DD |
1326 | netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", |
1327 | speed, ecmd.duplex, mode); | |
933a27d3 DH |
1328 | |
1329 | asix_write_medium_mode(dev, mode); | |
1330 | ||
1331 | if (data->phymode == PHY_MODE_MARVELL && data->ledmode) | |
8ae6daca | 1332 | marvell_led_status(dev, speed); |
933a27d3 DH |
1333 | |
1334 | return 0; | |
1335 | } | |
1336 | ||
1337 | static void ax88178_set_mfb(struct usbnet *dev) | |
1338 | { | |
1339 | u16 mfb = AX_RX_CTL_MFB_16384; | |
1340 | u16 rxctl; | |
1341 | u16 medium; | |
1342 | int old_rx_urb_size = dev->rx_urb_size; | |
1343 | ||
1344 | if (dev->hard_mtu < 2048) { | |
1345 | dev->rx_urb_size = 2048; | |
1346 | mfb = AX_RX_CTL_MFB_2048; | |
1347 | } else if (dev->hard_mtu < 4096) { | |
1348 | dev->rx_urb_size = 4096; | |
1349 | mfb = AX_RX_CTL_MFB_4096; | |
1350 | } else if (dev->hard_mtu < 8192) { | |
1351 | dev->rx_urb_size = 8192; | |
1352 | mfb = AX_RX_CTL_MFB_8192; | |
1353 | } else if (dev->hard_mtu < 16384) { | |
1354 | dev->rx_urb_size = 16384; | |
1355 | mfb = AX_RX_CTL_MFB_16384; | |
2e55cc72 | 1356 | } |
933a27d3 DH |
1357 | |
1358 | rxctl = asix_read_rx_ctl(dev); | |
1359 | asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb); | |
1360 | ||
1361 | medium = asix_read_medium_status(dev); | |
1362 | if (dev->net->mtu > 1500) | |
1363 | medium |= AX_MEDIUM_JFE; | |
1364 | else | |
1365 | medium &= ~AX_MEDIUM_JFE; | |
1366 | asix_write_medium_mode(dev, medium); | |
1367 | ||
1368 | if (dev->rx_urb_size > old_rx_urb_size) | |
1369 | usbnet_unlink_rx_urbs(dev); | |
2e55cc72 DB |
1370 | } |
1371 | ||
933a27d3 | 1372 | static int ax88178_change_mtu(struct net_device *net, int new_mtu) |
2e55cc72 | 1373 | { |
933a27d3 DH |
1374 | struct usbnet *dev = netdev_priv(net); |
1375 | int ll_mtu = new_mtu + net->hard_header_len + 4; | |
2e55cc72 | 1376 | |
60b86755 | 1377 | netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); |
2e55cc72 | 1378 | |
933a27d3 DH |
1379 | if (new_mtu <= 0 || ll_mtu > 16384) |
1380 | return -EINVAL; | |
1381 | ||
1382 | if ((ll_mtu % dev->maxpacket) == 0) | |
1383 | return -EDOM; | |
1384 | ||
1385 | net->mtu = new_mtu; | |
1386 | dev->hard_mtu = net->mtu + net->hard_header_len; | |
1387 | ax88178_set_mfb(dev); | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | ||
1703338c SH |
1392 | static const struct net_device_ops ax88178_netdev_ops = { |
1393 | .ndo_open = usbnet_open, | |
1394 | .ndo_stop = usbnet_stop, | |
1395 | .ndo_start_xmit = usbnet_start_xmit, | |
1396 | .ndo_tx_timeout = usbnet_tx_timeout, | |
7f29a3ba | 1397 | .ndo_set_mac_address = asix_set_mac_address, |
1703338c | 1398 | .ndo_validate_addr = eth_validate_addr, |
afc4b13d | 1399 | .ndo_set_rx_mode = asix_set_multicast, |
1703338c SH |
1400 | .ndo_do_ioctl = asix_ioctl, |
1401 | .ndo_change_mtu = ax88178_change_mtu, | |
1402 | }; | |
1403 | ||
933a27d3 DH |
1404 | static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) |
1405 | { | |
933a27d3 | 1406 | int ret; |
51bf2976 | 1407 | u8 buf[ETH_ALEN]; |
79de9efd GG |
1408 | struct asix_data *data = (struct asix_data *)&dev->data; |
1409 | ||
1410 | data->eeprom_len = AX88772_EEPROM_LEN; | |
933a27d3 DH |
1411 | |
1412 | usbnet_get_endpoints(dev,intf); | |
1413 | ||
933a27d3 | 1414 | /* Get the MAC address */ |
83e1b918 GG |
1415 | ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); |
1416 | if (ret < 0) { | |
933a27d3 | 1417 | dbg("Failed to read MAC address: %d", ret); |
83e1b918 | 1418 | return ret; |
2e55cc72 | 1419 | } |
933a27d3 | 1420 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); |
2e55cc72 | 1421 | |
933a27d3 DH |
1422 | /* Initialize MII structure */ |
1423 | dev->mii.dev = dev->net; | |
1424 | dev->mii.mdio_read = asix_mdio_read; | |
1425 | dev->mii.mdio_write = asix_mdio_write; | |
1426 | dev->mii.phy_id_mask = 0x1f; | |
1427 | dev->mii.reg_num_mask = 0xff; | |
1428 | dev->mii.supports_gmii = 1; | |
933a27d3 | 1429 | dev->mii.phy_id = asix_get_phy_addr(dev); |
1703338c SH |
1430 | |
1431 | dev->net->netdev_ops = &ax88178_netdev_ops; | |
933a27d3 | 1432 | dev->net->ethtool_ops = &ax88178_ethtool_ops; |
2e55cc72 | 1433 | |
b2d3ad29 GG |
1434 | /* Blink LEDS so users know driver saw dongle */ |
1435 | asix_sw_reset(dev, 0); | |
1436 | msleep(150); | |
2e55cc72 | 1437 | |
b2d3ad29 GG |
1438 | asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); |
1439 | msleep(150); | |
933a27d3 DH |
1440 | |
1441 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ | |
1442 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1443 | /* hard_mtu is still the default - the device does not support | |
1444 | jumbo eth frames */ | |
1445 | dev->rx_urb_size = 2048; | |
1446 | } | |
933a27d3 | 1447 | |
83e1b918 | 1448 | return 0; |
2e55cc72 DB |
1449 | } |
1450 | ||
1451 | static const struct driver_info ax8817x_info = { | |
1452 | .description = "ASIX AX8817x USB 2.0 Ethernet", | |
48b1be6a DH |
1453 | .bind = ax88172_bind, |
1454 | .status = asix_status, | |
2e55cc72 DB |
1455 | .link_reset = ax88172_link_reset, |
1456 | .reset = ax88172_link_reset, | |
37e8273c | 1457 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1458 | .data = 0x00130103, |
1459 | }; | |
1460 | ||
1461 | static const struct driver_info dlink_dub_e100_info = { | |
1462 | .description = "DLink DUB-E100 USB Ethernet", | |
48b1be6a DH |
1463 | .bind = ax88172_bind, |
1464 | .status = asix_status, | |
2e55cc72 DB |
1465 | .link_reset = ax88172_link_reset, |
1466 | .reset = ax88172_link_reset, | |
37e8273c | 1467 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1468 | .data = 0x009f9d9f, |
1469 | }; | |
1470 | ||
1471 | static const struct driver_info netgear_fa120_info = { | |
1472 | .description = "Netgear FA-120 USB Ethernet", | |
48b1be6a DH |
1473 | .bind = ax88172_bind, |
1474 | .status = asix_status, | |
2e55cc72 DB |
1475 | .link_reset = ax88172_link_reset, |
1476 | .reset = ax88172_link_reset, | |
37e8273c | 1477 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1478 | .data = 0x00130103, |
1479 | }; | |
1480 | ||
1481 | static const struct driver_info hawking_uf200_info = { | |
1482 | .description = "Hawking UF200 USB Ethernet", | |
48b1be6a DH |
1483 | .bind = ax88172_bind, |
1484 | .status = asix_status, | |
2e55cc72 DB |
1485 | .link_reset = ax88172_link_reset, |
1486 | .reset = ax88172_link_reset, | |
37e8273c | 1487 | .flags = FLAG_ETHER | FLAG_LINK_INTR, |
2e55cc72 DB |
1488 | .data = 0x001f1d1f, |
1489 | }; | |
1490 | ||
1491 | static const struct driver_info ax88772_info = { | |
1492 | .description = "ASIX AX88772 USB 2.0 Ethernet", | |
1493 | .bind = ax88772_bind, | |
48b1be6a | 1494 | .status = asix_status, |
2e55cc72 | 1495 | .link_reset = ax88772_link_reset, |
4ad1438f | 1496 | .reset = ax88772_reset, |
a9e0aca4 | 1497 | .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET, |
933a27d3 DH |
1498 | .rx_fixup = asix_rx_fixup, |
1499 | .tx_fixup = asix_tx_fixup, | |
1500 | }; | |
1501 | ||
1502 | static const struct driver_info ax88178_info = { | |
1503 | .description = "ASIX AX88178 USB 2.0 Ethernet", | |
1504 | .bind = ax88178_bind, | |
1505 | .status = asix_status, | |
1506 | .link_reset = ax88178_link_reset, | |
610d885d | 1507 | .reset = ax88178_reset, |
37e8273c | 1508 | .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR, |
933a27d3 DH |
1509 | .rx_fixup = asix_rx_fixup, |
1510 | .tx_fixup = asix_tx_fixup, | |
2e55cc72 DB |
1511 | }; |
1512 | ||
1513 | static const struct usb_device_id products [] = { | |
1514 | { | |
1515 | // Linksys USB200M | |
1516 | USB_DEVICE (0x077b, 0x2226), | |
1517 | .driver_info = (unsigned long) &ax8817x_info, | |
1518 | }, { | |
1519 | // Netgear FA120 | |
1520 | USB_DEVICE (0x0846, 0x1040), | |
1521 | .driver_info = (unsigned long) &netgear_fa120_info, | |
1522 | }, { | |
1523 | // DLink DUB-E100 | |
1524 | USB_DEVICE (0x2001, 0x1a00), | |
1525 | .driver_info = (unsigned long) &dlink_dub_e100_info, | |
1526 | }, { | |
1527 | // Intellinet, ST Lab USB Ethernet | |
1528 | USB_DEVICE (0x0b95, 0x1720), | |
1529 | .driver_info = (unsigned long) &ax8817x_info, | |
1530 | }, { | |
1531 | // Hawking UF200, TrendNet TU2-ET100 | |
1532 | USB_DEVICE (0x07b8, 0x420a), | |
1533 | .driver_info = (unsigned long) &hawking_uf200_info, | |
1534 | }, { | |
39c4b38c DH |
1535 | // Billionton Systems, USB2AR |
1536 | USB_DEVICE (0x08dd, 0x90ff), | |
1537 | .driver_info = (unsigned long) &ax8817x_info, | |
2e55cc72 DB |
1538 | }, { |
1539 | // ATEN UC210T | |
1540 | USB_DEVICE (0x0557, 0x2009), | |
1541 | .driver_info = (unsigned long) &ax8817x_info, | |
1542 | }, { | |
1543 | // Buffalo LUA-U2-KTX | |
1544 | USB_DEVICE (0x0411, 0x003d), | |
1545 | .driver_info = (unsigned long) &ax8817x_info, | |
ac7b77f1 MD |
1546 | }, { |
1547 | // Buffalo LUA-U2-GT 10/100/1000 | |
1548 | USB_DEVICE (0x0411, 0x006e), | |
1549 | .driver_info = (unsigned long) &ax88178_info, | |
2e55cc72 DB |
1550 | }, { |
1551 | // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" | |
1552 | USB_DEVICE (0x6189, 0x182d), | |
1553 | .driver_info = (unsigned long) &ax8817x_info, | |
4e503919 JN |
1554 | }, { |
1555 | // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" | |
1556 | USB_DEVICE (0x0df6, 0x0056), | |
1557 | .driver_info = (unsigned long) &ax88178_info, | |
2e55cc72 DB |
1558 | }, { |
1559 | // corega FEther USB2-TX | |
1560 | USB_DEVICE (0x07aa, 0x0017), | |
1561 | .driver_info = (unsigned long) &ax8817x_info, | |
1562 | }, { | |
1563 | // Surecom EP-1427X-2 | |
1564 | USB_DEVICE (0x1189, 0x0893), | |
1565 | .driver_info = (unsigned long) &ax8817x_info, | |
1566 | }, { | |
1567 | // goodway corp usb gwusb2e | |
1568 | USB_DEVICE (0x1631, 0x6200), | |
1569 | .driver_info = (unsigned long) &ax8817x_info, | |
39c4b38c DH |
1570 | }, { |
1571 | // JVC MP-PRX1 Port Replicator | |
1572 | USB_DEVICE (0x04f1, 0x3008), | |
1573 | .driver_info = (unsigned long) &ax8817x_info, | |
30885909 MV |
1574 | }, { |
1575 | // ASIX AX88772B 10/100 | |
1576 | USB_DEVICE (0x0b95, 0x772b), | |
1577 | .driver_info = (unsigned long) &ax88772_info, | |
2e55cc72 DB |
1578 | }, { |
1579 | // ASIX AX88772 10/100 | |
39c4b38c DH |
1580 | USB_DEVICE (0x0b95, 0x7720), |
1581 | .driver_info = (unsigned long) &ax88772_info, | |
7327413c EW |
1582 | }, { |
1583 | // ASIX AX88178 10/100/1000 | |
1584 | USB_DEVICE (0x0b95, 0x1780), | |
933a27d3 | 1585 | .driver_info = (unsigned long) &ax88178_info, |
f4680d3d AE |
1586 | }, { |
1587 | // Logitec LAN-GTJ/U2A | |
1588 | USB_DEVICE (0x0789, 0x0160), | |
1589 | .driver_info = (unsigned long) &ax88178_info, | |
5e0f76c6 DH |
1590 | }, { |
1591 | // Linksys USB200M Rev 2 | |
1592 | USB_DEVICE (0x13b1, 0x0018), | |
1593 | .driver_info = (unsigned long) &ax88772_info, | |
5732ce84 DH |
1594 | }, { |
1595 | // 0Q0 cable ethernet | |
1596 | USB_DEVICE (0x1557, 0x7720), | |
1597 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1598 | }, { |
1599 | // DLink DUB-E100 H/W Ver B1 | |
1600 | USB_DEVICE (0x07d1, 0x3c05), | |
1601 | .driver_info = (unsigned long) &ax88772_info, | |
b923e7fc DH |
1602 | }, { |
1603 | // DLink DUB-E100 H/W Ver B1 Alternate | |
1604 | USB_DEVICE (0x2001, 0x3c05), | |
1605 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1606 | }, { |
1607 | // Linksys USB1000 | |
1608 | USB_DEVICE (0x1737, 0x0039), | |
1609 | .driver_info = (unsigned long) &ax88178_info, | |
b29cf31d YH |
1610 | }, { |
1611 | // IO-DATA ETG-US2 | |
1612 | USB_DEVICE (0x04bb, 0x0930), | |
1613 | .driver_info = (unsigned long) &ax88178_info, | |
2ed22bc2 DH |
1614 | }, { |
1615 | // Belkin F5D5055 | |
1616 | USB_DEVICE(0x050d, 0x5055), | |
1617 | .driver_info = (unsigned long) &ax88178_info, | |
3d60efb5 AN |
1618 | }, { |
1619 | // Apple USB Ethernet Adapter | |
1620 | USB_DEVICE(0x05ac, 0x1402), | |
1621 | .driver_info = (unsigned long) &ax88772_info, | |
ccf95402 JC |
1622 | }, { |
1623 | // Cables-to-Go USB Ethernet Adapter | |
1624 | USB_DEVICE(0x0b95, 0x772a), | |
1625 | .driver_info = (unsigned long) &ax88772_info, | |
fef7cc08 GKH |
1626 | }, { |
1627 | // ABOCOM for pci | |
1628 | USB_DEVICE(0x14ea, 0xab11), | |
1629 | .driver_info = (unsigned long) &ax88178_info, | |
1630 | }, { | |
1631 | // ASIX 88772a | |
1632 | USB_DEVICE(0x0db0, 0xa877), | |
1633 | .driver_info = (unsigned long) &ax88772_info, | |
e8303a3b AJ |
1634 | }, { |
1635 | // Asus USB Ethernet Adapter | |
1636 | USB_DEVICE (0x0b95, 0x7e2b), | |
1637 | .driver_info = (unsigned long) &ax88772_info, | |
2e55cc72 DB |
1638 | }, |
1639 | { }, // END | |
1640 | }; | |
1641 | MODULE_DEVICE_TABLE(usb, products); | |
1642 | ||
1643 | static struct usb_driver asix_driver = { | |
83e1b918 | 1644 | .name = DRIVER_NAME, |
2e55cc72 DB |
1645 | .id_table = products, |
1646 | .probe = usbnet_probe, | |
1647 | .suspend = usbnet_suspend, | |
1648 | .resume = usbnet_resume, | |
1649 | .disconnect = usbnet_disconnect, | |
a11a6544 | 1650 | .supports_autosuspend = 1, |
e1f12eb6 | 1651 | .disable_hub_initiated_lpm = 1, |
2e55cc72 DB |
1652 | }; |
1653 | ||
d632eb1b | 1654 | module_usb_driver(asix_driver); |
2e55cc72 DB |
1655 | |
1656 | MODULE_AUTHOR("David Hollis"); | |
4ad1438f | 1657 | MODULE_VERSION(DRIVER_VERSION); |
2e55cc72 DB |
1658 | MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); |
1659 | MODULE_LICENSE("GPL"); | |
1660 |