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Commit | Line | Data |
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2e55cc72 DB |
1 | /* |
2 | * ASIX AX8817X based USB 2.0 Ethernet Devices | |
933a27d3 | 3 | * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> |
2e55cc72 | 4 | * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> |
933a27d3 | 5 | * Copyright (C) 2006 James Painter <jamie.painter@iname.com> |
2e55cc72 DB |
6 | * Copyright (c) 2002-2003 TiVo Inc. |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | // #define DEBUG // error path messages, extra info | |
24 | // #define VERBOSE // more; success messages | |
25 | ||
2e55cc72 DB |
26 | #include <linux/module.h> |
27 | #include <linux/kmod.h> | |
2e55cc72 DB |
28 | #include <linux/init.h> |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/ethtool.h> | |
32 | #include <linux/workqueue.h> | |
33 | #include <linux/mii.h> | |
34 | #include <linux/usb.h> | |
35 | #include <linux/crc32.h> | |
3692e94f | 36 | #include <linux/usb/usbnet.h> |
2e55cc72 | 37 | |
933a27d3 DH |
38 | #define DRIVER_VERSION "14-Jun-2006" |
39 | static const char driver_name [] = "asix"; | |
40 | ||
2e55cc72 DB |
41 | /* ASIX AX8817X based USB 2.0 Ethernet Devices */ |
42 | ||
43 | #define AX_CMD_SET_SW_MII 0x06 | |
44 | #define AX_CMD_READ_MII_REG 0x07 | |
45 | #define AX_CMD_WRITE_MII_REG 0x08 | |
46 | #define AX_CMD_SET_HW_MII 0x0a | |
47 | #define AX_CMD_READ_EEPROM 0x0b | |
48 | #define AX_CMD_WRITE_EEPROM 0x0c | |
49 | #define AX_CMD_WRITE_ENABLE 0x0d | |
50 | #define AX_CMD_WRITE_DISABLE 0x0e | |
933a27d3 | 51 | #define AX_CMD_READ_RX_CTL 0x0f |
2e55cc72 DB |
52 | #define AX_CMD_WRITE_RX_CTL 0x10 |
53 | #define AX_CMD_READ_IPG012 0x11 | |
54 | #define AX_CMD_WRITE_IPG0 0x12 | |
55 | #define AX_CMD_WRITE_IPG1 0x13 | |
933a27d3 | 56 | #define AX_CMD_READ_NODE_ID 0x13 |
2e55cc72 DB |
57 | #define AX_CMD_WRITE_IPG2 0x14 |
58 | #define AX_CMD_WRITE_MULTI_FILTER 0x16 | |
933a27d3 | 59 | #define AX88172_CMD_READ_NODE_ID 0x17 |
2e55cc72 DB |
60 | #define AX_CMD_READ_PHY_ID 0x19 |
61 | #define AX_CMD_READ_MEDIUM_STATUS 0x1a | |
62 | #define AX_CMD_WRITE_MEDIUM_MODE 0x1b | |
63 | #define AX_CMD_READ_MONITOR_MODE 0x1c | |
64 | #define AX_CMD_WRITE_MONITOR_MODE 0x1d | |
933a27d3 | 65 | #define AX_CMD_READ_GPIOS 0x1e |
2e55cc72 DB |
66 | #define AX_CMD_WRITE_GPIOS 0x1f |
67 | #define AX_CMD_SW_RESET 0x20 | |
68 | #define AX_CMD_SW_PHY_STATUS 0x21 | |
69 | #define AX_CMD_SW_PHY_SELECT 0x22 | |
2e55cc72 DB |
70 | |
71 | #define AX_MONITOR_MODE 0x01 | |
72 | #define AX_MONITOR_LINK 0x02 | |
73 | #define AX_MONITOR_MAGIC 0x04 | |
74 | #define AX_MONITOR_HSFS 0x10 | |
75 | ||
76 | /* AX88172 Medium Status Register values */ | |
933a27d3 DH |
77 | #define AX88172_MEDIUM_FD 0x02 |
78 | #define AX88172_MEDIUM_TX 0x04 | |
79 | #define AX88172_MEDIUM_FC 0x10 | |
80 | #define AX88172_MEDIUM_DEFAULT \ | |
81 | ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC ) | |
2e55cc72 DB |
82 | |
83 | #define AX_MCAST_FILTER_SIZE 8 | |
84 | #define AX_MAX_MCAST 64 | |
85 | ||
2e55cc72 DB |
86 | #define AX_SWRESET_CLEAR 0x00 |
87 | #define AX_SWRESET_RR 0x01 | |
88 | #define AX_SWRESET_RT 0x02 | |
89 | #define AX_SWRESET_PRTE 0x04 | |
90 | #define AX_SWRESET_PRL 0x08 | |
91 | #define AX_SWRESET_BZ 0x10 | |
92 | #define AX_SWRESET_IPRL 0x20 | |
93 | #define AX_SWRESET_IPPD 0x40 | |
94 | ||
95 | #define AX88772_IPG0_DEFAULT 0x15 | |
96 | #define AX88772_IPG1_DEFAULT 0x0c | |
97 | #define AX88772_IPG2_DEFAULT 0x12 | |
98 | ||
933a27d3 DH |
99 | /* AX88772 & AX88178 Medium Mode Register */ |
100 | #define AX_MEDIUM_PF 0x0080 | |
101 | #define AX_MEDIUM_JFE 0x0040 | |
102 | #define AX_MEDIUM_TFC 0x0020 | |
103 | #define AX_MEDIUM_RFC 0x0010 | |
104 | #define AX_MEDIUM_ENCK 0x0008 | |
105 | #define AX_MEDIUM_AC 0x0004 | |
106 | #define AX_MEDIUM_FD 0x0002 | |
107 | #define AX_MEDIUM_GM 0x0001 | |
108 | #define AX_MEDIUM_SM 0x1000 | |
109 | #define AX_MEDIUM_SBP 0x0800 | |
110 | #define AX_MEDIUM_PS 0x0200 | |
111 | #define AX_MEDIUM_RE 0x0100 | |
112 | ||
113 | #define AX88178_MEDIUM_DEFAULT \ | |
114 | (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ | |
115 | AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ | |
116 | AX_MEDIUM_RE ) | |
2e55cc72 | 117 | |
933a27d3 DH |
118 | #define AX88772_MEDIUM_DEFAULT \ |
119 | (AX_MEDIUM_FD | AX_MEDIUM_RFC | \ | |
120 | AX_MEDIUM_TFC | AX_MEDIUM_PS | \ | |
121 | AX_MEDIUM_AC | AX_MEDIUM_RE ) | |
122 | ||
123 | /* AX88772 & AX88178 RX_CTL values */ | |
124 | #define AX_RX_CTL_SO 0x0080 | |
125 | #define AX_RX_CTL_AP 0x0020 | |
126 | #define AX_RX_CTL_AM 0x0010 | |
127 | #define AX_RX_CTL_AB 0x0008 | |
128 | #define AX_RX_CTL_SEP 0x0004 | |
129 | #define AX_RX_CTL_AMALL 0x0002 | |
130 | #define AX_RX_CTL_PRO 0x0001 | |
131 | #define AX_RX_CTL_MFB_2048 0x0000 | |
132 | #define AX_RX_CTL_MFB_4096 0x0100 | |
133 | #define AX_RX_CTL_MFB_8192 0x0200 | |
134 | #define AX_RX_CTL_MFB_16384 0x0300 | |
135 | ||
136 | #define AX_DEFAULT_RX_CTL \ | |
137 | (AX_RX_CTL_SO | AX_RX_CTL_AB ) | |
138 | ||
139 | /* GPIO 0 .. 2 toggles */ | |
140 | #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ | |
141 | #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ | |
142 | #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ | |
143 | #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ | |
144 | #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ | |
145 | #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ | |
146 | #define AX_GPIO_RESERVED 0x40 /* Reserved */ | |
147 | #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ | |
148 | ||
149 | #define AX_EEPROM_MAGIC 0xdeadbeef | |
150 | #define AX88172_EEPROM_LEN 0x40 | |
151 | #define AX88772_EEPROM_LEN 0xff | |
152 | ||
153 | #define PHY_MODE_MARVELL 0x0000 | |
154 | #define MII_MARVELL_LED_CTRL 0x0018 | |
155 | #define MII_MARVELL_STATUS 0x001b | |
156 | #define MII_MARVELL_CTRL 0x0014 | |
157 | ||
158 | #define MARVELL_LED_MANUAL 0x0019 | |
159 | ||
160 | #define MARVELL_STATUS_HWCFG 0x0004 | |
161 | ||
162 | #define MARVELL_CTRL_TXDELAY 0x0002 | |
163 | #define MARVELL_CTRL_RXDELAY 0x0080 | |
2e55cc72 DB |
164 | |
165 | /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ | |
48b1be6a | 166 | struct asix_data { |
2e55cc72 | 167 | u8 multi_filter[AX_MCAST_FILTER_SIZE]; |
933a27d3 DH |
168 | u8 phymode; |
169 | u8 ledmode; | |
170 | u8 eeprom_len; | |
2e55cc72 DB |
171 | }; |
172 | ||
173 | struct ax88172_int_data { | |
51bf2976 | 174 | __le16 res1; |
2e55cc72 | 175 | u8 link; |
51bf2976 | 176 | __le16 res2; |
2e55cc72 | 177 | u8 status; |
51bf2976 | 178 | __le16 res3; |
2e55cc72 DB |
179 | } __attribute__ ((packed)); |
180 | ||
48b1be6a | 181 | static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
182 | u16 size, void *data) |
183 | { | |
51bf2976 AV |
184 | void *buf; |
185 | int err = -ENOMEM; | |
186 | ||
933a27d3 DH |
187 | devdbg(dev,"asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d", |
188 | cmd, value, index, size); | |
51bf2976 AV |
189 | |
190 | buf = kmalloc(size, GFP_KERNEL); | |
191 | if (!buf) | |
192 | goto out; | |
193 | ||
194 | err = usb_control_msg( | |
2e55cc72 DB |
195 | dev->udev, |
196 | usb_rcvctrlpipe(dev->udev, 0), | |
197 | cmd, | |
198 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
199 | value, | |
200 | index, | |
51bf2976 | 201 | buf, |
2e55cc72 DB |
202 | size, |
203 | USB_CTRL_GET_TIMEOUT); | |
94d43363 | 204 | if (err == size) |
51bf2976 | 205 | memcpy(data, buf, size); |
94d43363 RD |
206 | else if (err >= 0) |
207 | err = -EINVAL; | |
51bf2976 AV |
208 | kfree(buf); |
209 | ||
210 | out: | |
211 | return err; | |
2e55cc72 DB |
212 | } |
213 | ||
48b1be6a | 214 | static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
215 | u16 size, void *data) |
216 | { | |
51bf2976 AV |
217 | void *buf = NULL; |
218 | int err = -ENOMEM; | |
219 | ||
933a27d3 DH |
220 | devdbg(dev,"asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d", |
221 | cmd, value, index, size); | |
51bf2976 AV |
222 | |
223 | if (data) { | |
224 | buf = kmalloc(size, GFP_KERNEL); | |
225 | if (!buf) | |
226 | goto out; | |
227 | memcpy(buf, data, size); | |
228 | } | |
229 | ||
230 | err = usb_control_msg( | |
2e55cc72 DB |
231 | dev->udev, |
232 | usb_sndctrlpipe(dev->udev, 0), | |
233 | cmd, | |
234 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
235 | value, | |
236 | index, | |
51bf2976 | 237 | buf, |
2e55cc72 DB |
238 | size, |
239 | USB_CTRL_SET_TIMEOUT); | |
51bf2976 AV |
240 | kfree(buf); |
241 | ||
242 | out: | |
243 | return err; | |
2e55cc72 DB |
244 | } |
245 | ||
7d12e780 | 246 | static void asix_async_cmd_callback(struct urb *urb) |
2e55cc72 DB |
247 | { |
248 | struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context; | |
249 | ||
250 | if (urb->status < 0) | |
48b1be6a | 251 | printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d", |
2e55cc72 DB |
252 | urb->status); |
253 | ||
254 | kfree(req); | |
255 | usb_free_urb(urb); | |
256 | } | |
257 | ||
933a27d3 DH |
258 | static void |
259 | asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index, | |
260 | u16 size, void *data) | |
261 | { | |
262 | struct usb_ctrlrequest *req; | |
263 | int status; | |
264 | struct urb *urb; | |
265 | ||
266 | devdbg(dev,"asix_write_cmd_async() cmd=0x%02x value=0x%04x index=0x%04x size=%d", | |
267 | cmd, value, index, size); | |
268 | if ((urb = usb_alloc_urb(0, GFP_ATOMIC)) == NULL) { | |
269 | deverr(dev, "Error allocating URB in write_cmd_async!"); | |
270 | return; | |
271 | } | |
272 | ||
273 | if ((req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC)) == NULL) { | |
274 | deverr(dev, "Failed to allocate memory for control request"); | |
275 | usb_free_urb(urb); | |
276 | return; | |
277 | } | |
278 | ||
279 | req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE; | |
280 | req->bRequest = cmd; | |
9aa742ef ON |
281 | req->wValue = cpu_to_le16(value); |
282 | req->wIndex = cpu_to_le16(index); | |
283 | req->wLength = cpu_to_le16(size); | |
933a27d3 DH |
284 | |
285 | usb_fill_control_urb(urb, dev->udev, | |
286 | usb_sndctrlpipe(dev->udev, 0), | |
287 | (void *)req, data, size, | |
288 | asix_async_cmd_callback, req); | |
289 | ||
290 | if((status = usb_submit_urb(urb, GFP_ATOMIC)) < 0) { | |
291 | deverr(dev, "Error submitting the control message: status=%d", | |
292 | status); | |
293 | kfree(req); | |
294 | usb_free_urb(urb); | |
295 | } | |
296 | } | |
297 | ||
298 | static int asix_rx_fixup(struct usbnet *dev, struct sk_buff *skb) | |
299 | { | |
300 | u8 *head; | |
301 | u32 header; | |
302 | char *packet; | |
303 | struct sk_buff *ax_skb; | |
304 | u16 size; | |
305 | ||
306 | head = (u8 *) skb->data; | |
307 | memcpy(&header, head, sizeof(header)); | |
308 | le32_to_cpus(&header); | |
309 | packet = head + sizeof(header); | |
310 | ||
311 | skb_pull(skb, 4); | |
312 | ||
313 | while (skb->len > 0) { | |
314 | if ((short)(header & 0x0000ffff) != | |
315 | ~((short)((header & 0xffff0000) >> 16))) { | |
316 | deverr(dev,"asix_rx_fixup() Bad Header Length"); | |
317 | } | |
318 | /* get the packet length */ | |
319 | size = (u16) (header & 0x0000ffff); | |
320 | ||
321 | if ((skb->len) - ((size + 1) & 0xfffe) == 0) | |
322 | return 2; | |
323 | if (size > ETH_FRAME_LEN) { | |
324 | deverr(dev,"asix_rx_fixup() Bad RX Length %d", size); | |
325 | return 0; | |
326 | } | |
327 | ax_skb = skb_clone(skb, GFP_ATOMIC); | |
328 | if (ax_skb) { | |
329 | ax_skb->len = size; | |
330 | ax_skb->data = packet; | |
27a884dc | 331 | skb_set_tail_pointer(ax_skb, size); |
933a27d3 DH |
332 | usbnet_skb_return(dev, ax_skb); |
333 | } else { | |
334 | return 0; | |
335 | } | |
336 | ||
337 | skb_pull(skb, (size + 1) & 0xfffe); | |
338 | ||
339 | if (skb->len == 0) | |
340 | break; | |
341 | ||
342 | head = (u8 *) skb->data; | |
343 | memcpy(&header, head, sizeof(header)); | |
344 | le32_to_cpus(&header); | |
345 | packet = head + sizeof(header); | |
346 | skb_pull(skb, 4); | |
347 | } | |
348 | ||
349 | if (skb->len < 0) { | |
350 | deverr(dev,"asix_rx_fixup() Bad SKB Length %d", skb->len); | |
351 | return 0; | |
352 | } | |
353 | return 1; | |
354 | } | |
355 | ||
356 | static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb, | |
357 | gfp_t flags) | |
358 | { | |
359 | int padlen; | |
360 | int headroom = skb_headroom(skb); | |
361 | int tailroom = skb_tailroom(skb); | |
362 | u32 packet_len; | |
363 | u32 padbytes = 0xffff0000; | |
364 | ||
365 | padlen = ((skb->len + 4) % 512) ? 0 : 4; | |
366 | ||
367 | if ((!skb_cloned(skb)) | |
368 | && ((headroom + tailroom) >= (4 + padlen))) { | |
369 | if ((headroom < 4) || (tailroom < padlen)) { | |
370 | skb->data = memmove(skb->head + 4, skb->data, skb->len); | |
27a884dc | 371 | skb_set_tail_pointer(skb, skb->len); |
933a27d3 DH |
372 | } |
373 | } else { | |
374 | struct sk_buff *skb2; | |
375 | skb2 = skb_copy_expand(skb, 4, padlen, flags); | |
376 | dev_kfree_skb_any(skb); | |
377 | skb = skb2; | |
378 | if (!skb) | |
379 | return NULL; | |
380 | } | |
381 | ||
382 | skb_push(skb, 4); | |
383 | packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4); | |
57e4f041 | 384 | cpu_to_le32s(&packet_len); |
27d7ff46 | 385 | skb_copy_to_linear_data(skb, &packet_len, sizeof(packet_len)); |
933a27d3 DH |
386 | |
387 | if ((skb->len % 512) == 0) { | |
57e4f041 | 388 | cpu_to_le32s(&padbytes); |
27a884dc | 389 | memcpy(skb_tail_pointer(skb), &padbytes, sizeof(padbytes)); |
933a27d3 DH |
390 | skb_put(skb, sizeof(padbytes)); |
391 | } | |
392 | return skb; | |
393 | } | |
394 | ||
395 | static void asix_status(struct usbnet *dev, struct urb *urb) | |
396 | { | |
397 | struct ax88172_int_data *event; | |
398 | int link; | |
399 | ||
400 | if (urb->actual_length < 8) | |
401 | return; | |
402 | ||
403 | event = urb->transfer_buffer; | |
404 | link = event->link & 0x01; | |
405 | if (netif_carrier_ok(dev->net) != link) { | |
406 | if (link) { | |
407 | netif_carrier_on(dev->net); | |
408 | usbnet_defer_kevent (dev, EVENT_LINK_RESET ); | |
409 | } else | |
410 | netif_carrier_off(dev->net); | |
411 | devdbg(dev, "Link Status is: %d", link); | |
412 | } | |
413 | } | |
414 | ||
48b1be6a DH |
415 | static inline int asix_set_sw_mii(struct usbnet *dev) |
416 | { | |
417 | int ret; | |
418 | ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL); | |
419 | if (ret < 0) | |
933a27d3 | 420 | deverr(dev, "Failed to enable software MII access"); |
48b1be6a DH |
421 | return ret; |
422 | } | |
423 | ||
424 | static inline int asix_set_hw_mii(struct usbnet *dev) | |
425 | { | |
426 | int ret; | |
427 | ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL); | |
428 | if (ret < 0) | |
933a27d3 | 429 | deverr(dev, "Failed to enable hardware MII access"); |
48b1be6a DH |
430 | return ret; |
431 | } | |
432 | ||
933a27d3 | 433 | static inline int asix_get_phy_addr(struct usbnet *dev) |
48b1be6a | 434 | { |
51bf2976 AV |
435 | u8 buf[2]; |
436 | int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf); | |
48b1be6a | 437 | |
933a27d3 DH |
438 | devdbg(dev, "asix_get_phy_addr()"); |
439 | ||
51bf2976 | 440 | if (ret < 0) { |
933a27d3 | 441 | deverr(dev, "Error reading PHYID register: %02x", ret); |
51bf2976 | 442 | goto out; |
48b1be6a | 443 | } |
51bf2976 AV |
444 | devdbg(dev, "asix_get_phy_addr() returning 0x%04x", *((__le16 *)buf)); |
445 | ret = buf[1]; | |
446 | ||
447 | out: | |
48b1be6a DH |
448 | return ret; |
449 | } | |
450 | ||
451 | static int asix_sw_reset(struct usbnet *dev, u8 flags) | |
452 | { | |
453 | int ret; | |
454 | ||
455 | ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL); | |
456 | if (ret < 0) | |
933a27d3 DH |
457 | deverr(dev,"Failed to send software reset: %02x", ret); |
458 | ||
459 | return ret; | |
460 | } | |
48b1be6a | 461 | |
933a27d3 DH |
462 | static u16 asix_read_rx_ctl(struct usbnet *dev) |
463 | { | |
51bf2976 AV |
464 | __le16 v; |
465 | int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v); | |
933a27d3 | 466 | |
51bf2976 | 467 | if (ret < 0) { |
933a27d3 | 468 | deverr(dev, "Error reading RX_CTL register: %02x", ret); |
51bf2976 | 469 | goto out; |
933a27d3 | 470 | } |
51bf2976 AV |
471 | ret = le16_to_cpu(v); |
472 | out: | |
48b1be6a DH |
473 | return ret; |
474 | } | |
475 | ||
476 | static int asix_write_rx_ctl(struct usbnet *dev, u16 mode) | |
477 | { | |
478 | int ret; | |
479 | ||
933a27d3 | 480 | devdbg(dev,"asix_write_rx_ctl() - mode = 0x%04x", mode); |
48b1be6a DH |
481 | ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL); |
482 | if (ret < 0) | |
933a27d3 DH |
483 | deverr(dev, "Failed to write RX_CTL mode to 0x%04x: %02x", |
484 | mode, ret); | |
48b1be6a DH |
485 | |
486 | return ret; | |
487 | } | |
488 | ||
933a27d3 | 489 | static u16 asix_read_medium_status(struct usbnet *dev) |
2e55cc72 | 490 | { |
51bf2976 AV |
491 | __le16 v; |
492 | int ret = asix_read_cmd(dev, AX_CMD_READ_MEDIUM_STATUS, 0, 0, 2, &v); | |
2e55cc72 | 493 | |
51bf2976 | 494 | if (ret < 0) { |
933a27d3 | 495 | deverr(dev, "Error reading Medium Status register: %02x", ret); |
51bf2976 | 496 | goto out; |
2e55cc72 | 497 | } |
51bf2976 AV |
498 | ret = le16_to_cpu(v); |
499 | out: | |
933a27d3 | 500 | return ret; |
2e55cc72 DB |
501 | } |
502 | ||
933a27d3 | 503 | static int asix_write_medium_mode(struct usbnet *dev, u16 mode) |
2e55cc72 | 504 | { |
933a27d3 | 505 | int ret; |
2e55cc72 | 506 | |
933a27d3 DH |
507 | devdbg(dev,"asix_write_medium_mode() - mode = 0x%04x", mode); |
508 | ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL); | |
509 | if (ret < 0) | |
510 | deverr(dev, "Failed to write Medium Mode mode to 0x%04x: %02x", | |
511 | mode, ret); | |
2e55cc72 | 512 | |
933a27d3 DH |
513 | return ret; |
514 | } | |
2e55cc72 | 515 | |
933a27d3 DH |
516 | static int asix_write_gpio(struct usbnet *dev, u16 value, int sleep) |
517 | { | |
518 | int ret; | |
2e55cc72 | 519 | |
933a27d3 DH |
520 | devdbg(dev,"asix_write_gpio() - value = 0x%04x", value); |
521 | ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL); | |
522 | if (ret < 0) | |
523 | deverr(dev, "Failed to write GPIO value 0x%04x: %02x", | |
524 | value, ret); | |
2e55cc72 | 525 | |
933a27d3 DH |
526 | if (sleep) |
527 | msleep(sleep); | |
528 | ||
529 | return ret; | |
2e55cc72 DB |
530 | } |
531 | ||
933a27d3 DH |
532 | /* |
533 | * AX88772 & AX88178 have a 16-bit RX_CTL value | |
534 | */ | |
48b1be6a | 535 | static void asix_set_multicast(struct net_device *net) |
2e55cc72 DB |
536 | { |
537 | struct usbnet *dev = netdev_priv(net); | |
48b1be6a | 538 | struct asix_data *data = (struct asix_data *)&dev->data; |
933a27d3 | 539 | u16 rx_ctl = AX_DEFAULT_RX_CTL; |
2e55cc72 DB |
540 | |
541 | if (net->flags & IFF_PROMISC) { | |
933a27d3 | 542 | rx_ctl |= AX_RX_CTL_PRO; |
2e55cc72 DB |
543 | } else if (net->flags & IFF_ALLMULTI |
544 | || net->mc_count > AX_MAX_MCAST) { | |
933a27d3 | 545 | rx_ctl |= AX_RX_CTL_AMALL; |
2e55cc72 DB |
546 | } else if (net->mc_count == 0) { |
547 | /* just broadcast and directed */ | |
548 | } else { | |
549 | /* We use the 20 byte dev->data | |
550 | * for our 8 byte filter buffer | |
551 | * to avoid allocating memory that | |
552 | * is tricky to free later */ | |
553 | struct dev_mc_list *mc_list = net->mc_list; | |
554 | u32 crc_bits; | |
555 | int i; | |
556 | ||
557 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
558 | ||
559 | /* Build the multicast hash filter. */ | |
560 | for (i = 0; i < net->mc_count; i++) { | |
561 | crc_bits = | |
562 | ether_crc(ETH_ALEN, | |
563 | mc_list->dmi_addr) >> 26; | |
564 | data->multi_filter[crc_bits >> 3] |= | |
565 | 1 << (crc_bits & 7); | |
566 | mc_list = mc_list->next; | |
567 | } | |
568 | ||
48b1be6a | 569 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, |
2e55cc72 DB |
570 | AX_MCAST_FILTER_SIZE, data->multi_filter); |
571 | ||
933a27d3 | 572 | rx_ctl |= AX_RX_CTL_AM; |
2e55cc72 DB |
573 | } |
574 | ||
48b1be6a | 575 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); |
2e55cc72 DB |
576 | } |
577 | ||
48b1be6a | 578 | static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc) |
2e55cc72 DB |
579 | { |
580 | struct usbnet *dev = netdev_priv(netdev); | |
51bf2976 | 581 | __le16 res; |
2e55cc72 | 582 | |
a9fc6338 | 583 | mutex_lock(&dev->phy_mutex); |
48b1be6a DH |
584 | asix_set_sw_mii(dev); |
585 | asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, | |
51bf2976 | 586 | (__u16)loc, 2, &res); |
48b1be6a | 587 | asix_set_hw_mii(dev); |
a9fc6338 | 588 | mutex_unlock(&dev->phy_mutex); |
2e55cc72 | 589 | |
51bf2976 | 590 | devdbg(dev, "asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x", phy_id, loc, le16_to_cpu(res)); |
2e55cc72 | 591 | |
51bf2976 | 592 | return le16_to_cpu(res); |
2e55cc72 DB |
593 | } |
594 | ||
595 | static void | |
48b1be6a | 596 | asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val) |
2e55cc72 DB |
597 | { |
598 | struct usbnet *dev = netdev_priv(netdev); | |
51bf2976 | 599 | __le16 res = cpu_to_le16(val); |
2e55cc72 | 600 | |
933a27d3 | 601 | devdbg(dev, "asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x", phy_id, loc, val); |
a9fc6338 | 602 | mutex_lock(&dev->phy_mutex); |
48b1be6a | 603 | asix_set_sw_mii(dev); |
51bf2976 | 604 | asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res); |
48b1be6a | 605 | asix_set_hw_mii(dev); |
a9fc6338 | 606 | mutex_unlock(&dev->phy_mutex); |
2e55cc72 DB |
607 | } |
608 | ||
933a27d3 DH |
609 | /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ |
610 | static u32 asix_get_phyid(struct usbnet *dev) | |
2e55cc72 | 611 | { |
933a27d3 DH |
612 | int phy_reg; |
613 | u32 phy_id; | |
2e55cc72 | 614 | |
933a27d3 DH |
615 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); |
616 | if (phy_reg < 0) | |
617 | return 0; | |
2e55cc72 | 618 | |
933a27d3 | 619 | phy_id = (phy_reg & 0xffff) << 16; |
2e55cc72 | 620 | |
933a27d3 DH |
621 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); |
622 | if (phy_reg < 0) | |
623 | return 0; | |
624 | ||
625 | phy_id |= (phy_reg & 0xffff); | |
626 | ||
627 | return phy_id; | |
2e55cc72 DB |
628 | } |
629 | ||
630 | static void | |
48b1be6a | 631 | asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
632 | { |
633 | struct usbnet *dev = netdev_priv(net); | |
634 | u8 opt; | |
635 | ||
48b1be6a | 636 | if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) { |
2e55cc72 DB |
637 | wolinfo->supported = 0; |
638 | wolinfo->wolopts = 0; | |
639 | return; | |
640 | } | |
641 | wolinfo->supported = WAKE_PHY | WAKE_MAGIC; | |
642 | wolinfo->wolopts = 0; | |
643 | if (opt & AX_MONITOR_MODE) { | |
644 | if (opt & AX_MONITOR_LINK) | |
645 | wolinfo->wolopts |= WAKE_PHY; | |
646 | if (opt & AX_MONITOR_MAGIC) | |
647 | wolinfo->wolopts |= WAKE_MAGIC; | |
648 | } | |
649 | } | |
650 | ||
651 | static int | |
48b1be6a | 652 | asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
653 | { |
654 | struct usbnet *dev = netdev_priv(net); | |
655 | u8 opt = 0; | |
2e55cc72 DB |
656 | |
657 | if (wolinfo->wolopts & WAKE_PHY) | |
658 | opt |= AX_MONITOR_LINK; | |
659 | if (wolinfo->wolopts & WAKE_MAGIC) | |
660 | opt |= AX_MONITOR_MAGIC; | |
661 | if (opt != 0) | |
662 | opt |= AX_MONITOR_MODE; | |
663 | ||
48b1be6a | 664 | if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE, |
51bf2976 | 665 | opt, 0, 0, NULL) < 0) |
2e55cc72 DB |
666 | return -EINVAL; |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
48b1be6a | 671 | static int asix_get_eeprom_len(struct net_device *net) |
2e55cc72 | 672 | { |
933a27d3 DH |
673 | struct usbnet *dev = netdev_priv(net); |
674 | struct asix_data *data = (struct asix_data *)&dev->data; | |
675 | ||
676 | return data->eeprom_len; | |
2e55cc72 DB |
677 | } |
678 | ||
48b1be6a | 679 | static int asix_get_eeprom(struct net_device *net, |
2e55cc72 DB |
680 | struct ethtool_eeprom *eeprom, u8 *data) |
681 | { | |
682 | struct usbnet *dev = netdev_priv(net); | |
51bf2976 | 683 | __le16 *ebuf = (__le16 *)data; |
2e55cc72 DB |
684 | int i; |
685 | ||
686 | /* Crude hack to ensure that we don't overwrite memory | |
687 | * if an odd length is supplied | |
688 | */ | |
689 | if (eeprom->len % 2) | |
690 | return -EINVAL; | |
691 | ||
692 | eeprom->magic = AX_EEPROM_MAGIC; | |
693 | ||
694 | /* ax8817x returns 2 bytes from eeprom on read */ | |
695 | for (i=0; i < eeprom->len / 2; i++) { | |
48b1be6a | 696 | if (asix_read_cmd(dev, AX_CMD_READ_EEPROM, |
2e55cc72 DB |
697 | eeprom->offset + i, 0, 2, &ebuf[i]) < 0) |
698 | return -EINVAL; | |
699 | } | |
700 | return 0; | |
701 | } | |
702 | ||
48b1be6a | 703 | static void asix_get_drvinfo (struct net_device *net, |
2e55cc72 DB |
704 | struct ethtool_drvinfo *info) |
705 | { | |
933a27d3 DH |
706 | struct usbnet *dev = netdev_priv(net); |
707 | struct asix_data *data = (struct asix_data *)&dev->data; | |
708 | ||
2e55cc72 DB |
709 | /* Inherit standard device info */ |
710 | usbnet_get_drvinfo(net, info); | |
933a27d3 DH |
711 | strncpy (info->driver, driver_name, sizeof info->driver); |
712 | strncpy (info->version, DRIVER_VERSION, sizeof info->version); | |
713 | info->eedump_len = data->eeprom_len; | |
2e55cc72 DB |
714 | } |
715 | ||
933a27d3 DH |
716 | static u32 asix_get_link(struct net_device *net) |
717 | { | |
718 | struct usbnet *dev = netdev_priv(net); | |
719 | ||
720 | return mii_link_ok(&dev->mii); | |
721 | } | |
722 | ||
723 | static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) | |
724 | { | |
725 | struct usbnet *dev = netdev_priv(net); | |
726 | ||
727 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
728 | } | |
729 | ||
730 | /* We need to override some ethtool_ops so we require our | |
731 | own structure so we don't interfere with other usbnet | |
732 | devices that may be connected at the same time. */ | |
733 | static struct ethtool_ops ax88172_ethtool_ops = { | |
734 | .get_drvinfo = asix_get_drvinfo, | |
735 | .get_link = asix_get_link, | |
933a27d3 | 736 | .get_msglevel = usbnet_get_msglevel, |
2e55cc72 | 737 | .set_msglevel = usbnet_set_msglevel, |
48b1be6a DH |
738 | .get_wol = asix_get_wol, |
739 | .set_wol = asix_set_wol, | |
740 | .get_eeprom_len = asix_get_eeprom_len, | |
741 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
742 | .get_settings = usbnet_get_settings, |
743 | .set_settings = usbnet_set_settings, | |
744 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
745 | }; |
746 | ||
933a27d3 | 747 | static void ax88172_set_multicast(struct net_device *net) |
2e55cc72 DB |
748 | { |
749 | struct usbnet *dev = netdev_priv(net); | |
933a27d3 DH |
750 | struct asix_data *data = (struct asix_data *)&dev->data; |
751 | u8 rx_ctl = 0x8c; | |
2e55cc72 | 752 | |
933a27d3 DH |
753 | if (net->flags & IFF_PROMISC) { |
754 | rx_ctl |= 0x01; | |
755 | } else if (net->flags & IFF_ALLMULTI | |
756 | || net->mc_count > AX_MAX_MCAST) { | |
757 | rx_ctl |= 0x02; | |
758 | } else if (net->mc_count == 0) { | |
759 | /* just broadcast and directed */ | |
760 | } else { | |
761 | /* We use the 20 byte dev->data | |
762 | * for our 8 byte filter buffer | |
763 | * to avoid allocating memory that | |
764 | * is tricky to free later */ | |
765 | struct dev_mc_list *mc_list = net->mc_list; | |
766 | u32 crc_bits; | |
767 | int i; | |
768 | ||
769 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
770 | ||
771 | /* Build the multicast hash filter. */ | |
772 | for (i = 0; i < net->mc_count; i++) { | |
773 | crc_bits = | |
774 | ether_crc(ETH_ALEN, | |
775 | mc_list->dmi_addr) >> 26; | |
776 | data->multi_filter[crc_bits >> 3] |= | |
777 | 1 << (crc_bits & 7); | |
778 | mc_list = mc_list->next; | |
779 | } | |
780 | ||
781 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, | |
782 | AX_MCAST_FILTER_SIZE, data->multi_filter); | |
783 | ||
784 | rx_ctl |= 0x10; | |
785 | } | |
786 | ||
787 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); | |
788 | } | |
789 | ||
790 | static int ax88172_link_reset(struct usbnet *dev) | |
791 | { | |
792 | u8 mode; | |
793 | struct ethtool_cmd ecmd; | |
794 | ||
795 | mii_check_media(&dev->mii, 1, 1); | |
796 | mii_ethtool_gset(&dev->mii, &ecmd); | |
797 | mode = AX88172_MEDIUM_DEFAULT; | |
798 | ||
799 | if (ecmd.duplex != DUPLEX_FULL) | |
800 | mode |= ~AX88172_MEDIUM_FD; | |
801 | ||
802 | devdbg(dev, "ax88172_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode); | |
803 | ||
804 | asix_write_medium_mode(dev, mode); | |
805 | ||
806 | return 0; | |
2e55cc72 DB |
807 | } |
808 | ||
48b1be6a | 809 | static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) |
2e55cc72 DB |
810 | { |
811 | int ret = 0; | |
51bf2976 | 812 | u8 buf[ETH_ALEN]; |
2e55cc72 DB |
813 | int i; |
814 | unsigned long gpio_bits = dev->driver_info->data; | |
933a27d3 DH |
815 | struct asix_data *data = (struct asix_data *)&dev->data; |
816 | ||
817 | data->eeprom_len = AX88172_EEPROM_LEN; | |
2e55cc72 DB |
818 | |
819 | usbnet_get_endpoints(dev,intf); | |
820 | ||
2e55cc72 DB |
821 | /* Toggle the GPIOs in a manufacturer/model specific way */ |
822 | for (i = 2; i >= 0; i--) { | |
48b1be6a | 823 | if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, |
2e55cc72 | 824 | (gpio_bits >> (i * 8)) & 0xff, 0, 0, |
51bf2976 AV |
825 | NULL)) < 0) |
826 | goto out; | |
2e55cc72 DB |
827 | msleep(5); |
828 | } | |
829 | ||
933a27d3 | 830 | if ((ret = asix_write_rx_ctl(dev, 0x80)) < 0) |
51bf2976 | 831 | goto out; |
2e55cc72 DB |
832 | |
833 | /* Get the MAC address */ | |
933a27d3 | 834 | if ((ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, |
51bf2976 | 835 | 0, 0, ETH_ALEN, buf)) < 0) { |
2e55cc72 | 836 | dbg("read AX_CMD_READ_NODE_ID failed: %d", ret); |
51bf2976 | 837 | goto out; |
2e55cc72 DB |
838 | } |
839 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
840 | ||
2e55cc72 DB |
841 | /* Initialize MII structure */ |
842 | dev->mii.dev = dev->net; | |
48b1be6a DH |
843 | dev->mii.mdio_read = asix_mdio_read; |
844 | dev->mii.mdio_write = asix_mdio_write; | |
2e55cc72 DB |
845 | dev->mii.phy_id_mask = 0x3f; |
846 | dev->mii.reg_num_mask = 0x1f; | |
933a27d3 | 847 | dev->mii.phy_id = asix_get_phy_addr(dev); |
48b1be6a | 848 | dev->net->do_ioctl = asix_ioctl; |
2e55cc72 | 849 | |
933a27d3 | 850 | dev->net->set_multicast_list = ax88172_set_multicast; |
48b1be6a | 851 | dev->net->ethtool_ops = &ax88172_ethtool_ops; |
2e55cc72 | 852 | |
933a27d3 DH |
853 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
854 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
855 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); |
856 | mii_nway_restart(&dev->mii); | |
857 | ||
858 | return 0; | |
51bf2976 AV |
859 | |
860 | out: | |
2e55cc72 DB |
861 | return ret; |
862 | } | |
863 | ||
864 | static struct ethtool_ops ax88772_ethtool_ops = { | |
48b1be6a | 865 | .get_drvinfo = asix_get_drvinfo, |
933a27d3 | 866 | .get_link = asix_get_link, |
2e55cc72 DB |
867 | .get_msglevel = usbnet_get_msglevel, |
868 | .set_msglevel = usbnet_set_msglevel, | |
48b1be6a DH |
869 | .get_wol = asix_get_wol, |
870 | .set_wol = asix_set_wol, | |
871 | .get_eeprom_len = asix_get_eeprom_len, | |
872 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
873 | .get_settings = usbnet_get_settings, |
874 | .set_settings = usbnet_set_settings, | |
875 | .nway_reset = usbnet_nway_reset, | |
2e55cc72 DB |
876 | }; |
877 | ||
933a27d3 DH |
878 | static int ax88772_link_reset(struct usbnet *dev) |
879 | { | |
880 | u16 mode; | |
881 | struct ethtool_cmd ecmd; | |
882 | ||
883 | mii_check_media(&dev->mii, 1, 1); | |
884 | mii_ethtool_gset(&dev->mii, &ecmd); | |
885 | mode = AX88772_MEDIUM_DEFAULT; | |
886 | ||
887 | if (ecmd.speed != SPEED_100) | |
888 | mode &= ~AX_MEDIUM_PS; | |
889 | ||
890 | if (ecmd.duplex != DUPLEX_FULL) | |
891 | mode &= ~AX_MEDIUM_FD; | |
892 | ||
893 | devdbg(dev, "ax88772_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode); | |
894 | ||
895 | asix_write_medium_mode(dev, mode); | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
2e55cc72 DB |
900 | static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) |
901 | { | |
d0ffff8f | 902 | int ret, embd_phy; |
933a27d3 DH |
903 | u16 rx_ctl; |
904 | struct asix_data *data = (struct asix_data *)&dev->data; | |
51bf2976 | 905 | u8 buf[ETH_ALEN]; |
933a27d3 DH |
906 | u32 phyid; |
907 | ||
908 | data->eeprom_len = AX88772_EEPROM_LEN; | |
2e55cc72 DB |
909 | |
910 | usbnet_get_endpoints(dev,intf); | |
911 | ||
933a27d3 DH |
912 | if ((ret = asix_write_gpio(dev, |
913 | AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5)) < 0) | |
51bf2976 | 914 | goto out; |
2e55cc72 | 915 | |
d0ffff8f AS |
916 | /* 0x10 is the phy id of the embedded 10/100 ethernet phy */ |
917 | embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); | |
48b1be6a | 918 | if ((ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, |
51bf2976 | 919 | embd_phy, 0, 0, NULL)) < 0) { |
2e55cc72 | 920 | dbg("Select PHY #1 failed: %d", ret); |
51bf2976 | 921 | goto out; |
2e55cc72 DB |
922 | } |
923 | ||
d0ffff8f | 924 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL)) < 0) |
51bf2976 | 925 | goto out; |
2e55cc72 DB |
926 | |
927 | msleep(150); | |
48b1be6a | 928 | if ((ret = asix_sw_reset(dev, AX_SWRESET_CLEAR)) < 0) |
51bf2976 | 929 | goto out; |
2e55cc72 DB |
930 | |
931 | msleep(150); | |
d0ffff8f AS |
932 | if (embd_phy) { |
933 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL)) < 0) | |
51bf2976 | 934 | goto out; |
d0ffff8f AS |
935 | } |
936 | else { | |
937 | if ((ret = asix_sw_reset(dev, AX_SWRESET_PRTE)) < 0) | |
51bf2976 | 938 | goto out; |
d0ffff8f | 939 | } |
2e55cc72 DB |
940 | |
941 | msleep(150); | |
933a27d3 DH |
942 | rx_ctl = asix_read_rx_ctl(dev); |
943 | dbg("RX_CTL is 0x%04x after software reset", rx_ctl); | |
944 | if ((ret = asix_write_rx_ctl(dev, 0x0000)) < 0) | |
51bf2976 | 945 | goto out; |
2e55cc72 | 946 | |
933a27d3 DH |
947 | rx_ctl = asix_read_rx_ctl(dev); |
948 | dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl); | |
949 | ||
2e55cc72 | 950 | /* Get the MAC address */ |
933a27d3 | 951 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, |
2e55cc72 DB |
952 | 0, 0, ETH_ALEN, buf)) < 0) { |
953 | dbg("Failed to read MAC address: %d", ret); | |
51bf2976 | 954 | goto out; |
2e55cc72 DB |
955 | } |
956 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
957 | ||
2e55cc72 DB |
958 | /* Initialize MII structure */ |
959 | dev->mii.dev = dev->net; | |
48b1be6a DH |
960 | dev->mii.mdio_read = asix_mdio_read; |
961 | dev->mii.mdio_write = asix_mdio_write; | |
933a27d3 DH |
962 | dev->mii.phy_id_mask = 0x1f; |
963 | dev->mii.reg_num_mask = 0x1f; | |
48b1be6a | 964 | dev->net->do_ioctl = asix_ioctl; |
933a27d3 DH |
965 | dev->mii.phy_id = asix_get_phy_addr(dev); |
966 | ||
967 | phyid = asix_get_phyid(dev); | |
968 | dbg("PHYID=0x%08x", phyid); | |
2e55cc72 | 969 | |
48b1be6a | 970 | if ((ret = asix_sw_reset(dev, AX_SWRESET_PRL)) < 0) |
51bf2976 | 971 | goto out; |
2e55cc72 | 972 | |
2e55cc72 | 973 | msleep(150); |
48b1be6a DH |
974 | |
975 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0) | |
51bf2976 | 976 | goto out; |
2e55cc72 | 977 | |
48b1be6a | 978 | msleep(150); |
2e55cc72 | 979 | |
48b1be6a | 980 | dev->net->set_multicast_list = asix_set_multicast; |
2e55cc72 DB |
981 | dev->net->ethtool_ops = &ax88772_ethtool_ops; |
982 | ||
933a27d3 DH |
983 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
984 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
985 | ADVERTISE_ALL | ADVERTISE_CSMA); |
986 | mii_nway_restart(&dev->mii); | |
987 | ||
933a27d3 | 988 | if ((ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT)) < 0) |
51bf2976 | 989 | goto out; |
2e55cc72 | 990 | |
48b1be6a | 991 | if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, |
2e55cc72 | 992 | AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, |
51bf2976 | 993 | AX88772_IPG2_DEFAULT, 0, NULL)) < 0) { |
2e55cc72 | 994 | dbg("Write IPG,IPG1,IPG2 failed: %d", ret); |
51bf2976 | 995 | goto out; |
2e55cc72 | 996 | } |
2e55cc72 DB |
997 | |
998 | /* Set RX_CTL to default values with 2k buffer, and enable cactus */ | |
933a27d3 | 999 | if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0) |
51bf2976 | 1000 | goto out; |
2e55cc72 | 1001 | |
933a27d3 DH |
1002 | rx_ctl = asix_read_rx_ctl(dev); |
1003 | dbg("RX_CTL is 0x%04x after all initializations", rx_ctl); | |
1004 | ||
1005 | rx_ctl = asix_read_medium_status(dev); | |
1006 | dbg("Medium Status is 0x%04x after all initializations", rx_ctl); | |
1007 | ||
2e55cc72 DB |
1008 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ |
1009 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1010 | /* hard_mtu is still the default - the device does not support | |
1011 | jumbo eth frames */ | |
1012 | dev->rx_urb_size = 2048; | |
1013 | } | |
2e55cc72 DB |
1014 | return 0; |
1015 | ||
51bf2976 | 1016 | out: |
2e55cc72 DB |
1017 | return ret; |
1018 | } | |
1019 | ||
933a27d3 DH |
1020 | static struct ethtool_ops ax88178_ethtool_ops = { |
1021 | .get_drvinfo = asix_get_drvinfo, | |
1022 | .get_link = asix_get_link, | |
933a27d3 DH |
1023 | .get_msglevel = usbnet_get_msglevel, |
1024 | .set_msglevel = usbnet_set_msglevel, | |
1025 | .get_wol = asix_get_wol, | |
1026 | .set_wol = asix_set_wol, | |
1027 | .get_eeprom_len = asix_get_eeprom_len, | |
1028 | .get_eeprom = asix_get_eeprom, | |
c41286fd AB |
1029 | .get_settings = usbnet_get_settings, |
1030 | .set_settings = usbnet_set_settings, | |
1031 | .nway_reset = usbnet_nway_reset, | |
933a27d3 DH |
1032 | }; |
1033 | ||
1034 | static int marvell_phy_init(struct usbnet *dev) | |
2e55cc72 | 1035 | { |
933a27d3 DH |
1036 | struct asix_data *data = (struct asix_data *)&dev->data; |
1037 | u16 reg; | |
2e55cc72 | 1038 | |
933a27d3 | 1039 | devdbg(dev,"marvell_phy_init()"); |
2e55cc72 | 1040 | |
933a27d3 DH |
1041 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); |
1042 | devdbg(dev,"MII_MARVELL_STATUS = 0x%04x", reg); | |
2e55cc72 | 1043 | |
933a27d3 DH |
1044 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, |
1045 | MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); | |
2e55cc72 | 1046 | |
933a27d3 DH |
1047 | if (data->ledmode) { |
1048 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, | |
1049 | MII_MARVELL_LED_CTRL); | |
1050 | devdbg(dev,"MII_MARVELL_LED_CTRL (1) = 0x%04x", reg); | |
2e55cc72 | 1051 | |
933a27d3 DH |
1052 | reg &= 0xf8ff; |
1053 | reg |= (1 + 0x0100); | |
1054 | asix_mdio_write(dev->net, dev->mii.phy_id, | |
1055 | MII_MARVELL_LED_CTRL, reg); | |
2e55cc72 | 1056 | |
933a27d3 DH |
1057 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, |
1058 | MII_MARVELL_LED_CTRL); | |
1059 | devdbg(dev,"MII_MARVELL_LED_CTRL (2) = 0x%04x", reg); | |
1060 | reg &= 0xfc0f; | |
1061 | } | |
2e55cc72 | 1062 | |
933a27d3 DH |
1063 | return 0; |
1064 | } | |
1065 | ||
1066 | static int marvell_led_status(struct usbnet *dev, u16 speed) | |
1067 | { | |
1068 | u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); | |
1069 | ||
1070 | devdbg(dev, "marvell_led_status() read 0x%04x", reg); | |
1071 | ||
1072 | /* Clear out the center LED bits - 0x03F0 */ | |
1073 | reg &= 0xfc0f; | |
1074 | ||
1075 | switch (speed) { | |
1076 | case SPEED_1000: | |
1077 | reg |= 0x03e0; | |
1078 | break; | |
1079 | case SPEED_100: | |
1080 | reg |= 0x03b0; | |
1081 | break; | |
1082 | default: | |
1083 | reg |= 0x02f0; | |
2e55cc72 DB |
1084 | } |
1085 | ||
933a27d3 DH |
1086 | devdbg(dev, "marvell_led_status() writing 0x%04x", reg); |
1087 | asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | static int ax88178_link_reset(struct usbnet *dev) | |
1093 | { | |
1094 | u16 mode; | |
1095 | struct ethtool_cmd ecmd; | |
1096 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1097 | ||
1098 | devdbg(dev,"ax88178_link_reset()"); | |
1099 | ||
1100 | mii_check_media(&dev->mii, 1, 1); | |
1101 | mii_ethtool_gset(&dev->mii, &ecmd); | |
1102 | mode = AX88178_MEDIUM_DEFAULT; | |
1103 | ||
1104 | if (ecmd.speed == SPEED_1000) | |
1105 | mode |= AX_MEDIUM_GM | AX_MEDIUM_ENCK; | |
1106 | else if (ecmd.speed == SPEED_100) | |
1107 | mode |= AX_MEDIUM_PS; | |
1108 | else | |
1109 | mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); | |
1110 | ||
1111 | if (ecmd.duplex == DUPLEX_FULL) | |
1112 | mode |= AX_MEDIUM_FD; | |
1113 | else | |
1114 | mode &= ~AX_MEDIUM_FD; | |
1115 | ||
1116 | devdbg(dev, "ax88178_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode); | |
1117 | ||
1118 | asix_write_medium_mode(dev, mode); | |
1119 | ||
1120 | if (data->phymode == PHY_MODE_MARVELL && data->ledmode) | |
1121 | marvell_led_status(dev, ecmd.speed); | |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | static void ax88178_set_mfb(struct usbnet *dev) | |
1127 | { | |
1128 | u16 mfb = AX_RX_CTL_MFB_16384; | |
1129 | u16 rxctl; | |
1130 | u16 medium; | |
1131 | int old_rx_urb_size = dev->rx_urb_size; | |
1132 | ||
1133 | if (dev->hard_mtu < 2048) { | |
1134 | dev->rx_urb_size = 2048; | |
1135 | mfb = AX_RX_CTL_MFB_2048; | |
1136 | } else if (dev->hard_mtu < 4096) { | |
1137 | dev->rx_urb_size = 4096; | |
1138 | mfb = AX_RX_CTL_MFB_4096; | |
1139 | } else if (dev->hard_mtu < 8192) { | |
1140 | dev->rx_urb_size = 8192; | |
1141 | mfb = AX_RX_CTL_MFB_8192; | |
1142 | } else if (dev->hard_mtu < 16384) { | |
1143 | dev->rx_urb_size = 16384; | |
1144 | mfb = AX_RX_CTL_MFB_16384; | |
2e55cc72 | 1145 | } |
933a27d3 DH |
1146 | |
1147 | rxctl = asix_read_rx_ctl(dev); | |
1148 | asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb); | |
1149 | ||
1150 | medium = asix_read_medium_status(dev); | |
1151 | if (dev->net->mtu > 1500) | |
1152 | medium |= AX_MEDIUM_JFE; | |
1153 | else | |
1154 | medium &= ~AX_MEDIUM_JFE; | |
1155 | asix_write_medium_mode(dev, medium); | |
1156 | ||
1157 | if (dev->rx_urb_size > old_rx_urb_size) | |
1158 | usbnet_unlink_rx_urbs(dev); | |
2e55cc72 DB |
1159 | } |
1160 | ||
933a27d3 | 1161 | static int ax88178_change_mtu(struct net_device *net, int new_mtu) |
2e55cc72 | 1162 | { |
933a27d3 DH |
1163 | struct usbnet *dev = netdev_priv(net); |
1164 | int ll_mtu = new_mtu + net->hard_header_len + 4; | |
2e55cc72 | 1165 | |
933a27d3 | 1166 | devdbg(dev, "ax88178_change_mtu() new_mtu=%d", new_mtu); |
2e55cc72 | 1167 | |
933a27d3 DH |
1168 | if (new_mtu <= 0 || ll_mtu > 16384) |
1169 | return -EINVAL; | |
1170 | ||
1171 | if ((ll_mtu % dev->maxpacket) == 0) | |
1172 | return -EDOM; | |
1173 | ||
1174 | net->mtu = new_mtu; | |
1175 | dev->hard_mtu = net->mtu + net->hard_header_len; | |
1176 | ax88178_set_mfb(dev); | |
1177 | ||
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) | |
1182 | { | |
1183 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1184 | int ret; | |
51bf2976 AV |
1185 | u8 buf[ETH_ALEN]; |
1186 | __le16 eeprom; | |
1187 | u8 status; | |
933a27d3 DH |
1188 | int gpio0 = 0; |
1189 | u32 phyid; | |
1190 | ||
1191 | usbnet_get_endpoints(dev,intf); | |
1192 | ||
51bf2976 AV |
1193 | asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status); |
1194 | dbg("GPIO Status: 0x%04x", status); | |
933a27d3 DH |
1195 | |
1196 | asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL); | |
1197 | asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom); | |
1198 | asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL); | |
1199 | ||
1200 | dbg("EEPROM index 0x17 is 0x%04x", eeprom); | |
1201 | ||
51bf2976 | 1202 | if (eeprom == cpu_to_le16(0xffff)) { |
933a27d3 DH |
1203 | data->phymode = PHY_MODE_MARVELL; |
1204 | data->ledmode = 0; | |
1205 | gpio0 = 1; | |
2e55cc72 | 1206 | } else { |
51bf2976 AV |
1207 | data->phymode = le16_to_cpu(eeprom) & 7; |
1208 | data->ledmode = le16_to_cpu(eeprom) >> 8; | |
1209 | gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; | |
2e55cc72 | 1210 | } |
933a27d3 | 1211 | dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode); |
2e55cc72 | 1212 | |
933a27d3 | 1213 | asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40); |
51bf2976 | 1214 | if ((le16_to_cpu(eeprom) >> 8) != 1) { |
933a27d3 DH |
1215 | asix_write_gpio(dev, 0x003c, 30); |
1216 | asix_write_gpio(dev, 0x001c, 300); | |
1217 | asix_write_gpio(dev, 0x003c, 30); | |
1218 | } else { | |
1219 | dbg("gpio phymode == 1 path"); | |
1220 | asix_write_gpio(dev, AX_GPIO_GPO1EN, 30); | |
1221 | asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30); | |
1222 | } | |
2e55cc72 | 1223 | |
933a27d3 DH |
1224 | asix_sw_reset(dev, 0); |
1225 | msleep(150); | |
1226 | ||
1227 | asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); | |
1228 | msleep(150); | |
1229 | ||
1230 | asix_write_rx_ctl(dev, 0); | |
1231 | ||
1232 | /* Get the MAC address */ | |
933a27d3 DH |
1233 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, |
1234 | 0, 0, ETH_ALEN, buf)) < 0) { | |
1235 | dbg("Failed to read MAC address: %d", ret); | |
51bf2976 | 1236 | goto out; |
2e55cc72 | 1237 | } |
933a27d3 | 1238 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); |
2e55cc72 | 1239 | |
933a27d3 DH |
1240 | /* Initialize MII structure */ |
1241 | dev->mii.dev = dev->net; | |
1242 | dev->mii.mdio_read = asix_mdio_read; | |
1243 | dev->mii.mdio_write = asix_mdio_write; | |
1244 | dev->mii.phy_id_mask = 0x1f; | |
1245 | dev->mii.reg_num_mask = 0xff; | |
1246 | dev->mii.supports_gmii = 1; | |
1247 | dev->net->do_ioctl = asix_ioctl; | |
1248 | dev->mii.phy_id = asix_get_phy_addr(dev); | |
1249 | dev->net->set_multicast_list = asix_set_multicast; | |
1250 | dev->net->ethtool_ops = &ax88178_ethtool_ops; | |
1251 | dev->net->change_mtu = &ax88178_change_mtu; | |
2e55cc72 | 1252 | |
933a27d3 DH |
1253 | phyid = asix_get_phyid(dev); |
1254 | dbg("PHYID=0x%08x", phyid); | |
2e55cc72 | 1255 | |
933a27d3 DH |
1256 | if (data->phymode == PHY_MODE_MARVELL) { |
1257 | marvell_phy_init(dev); | |
1258 | msleep(60); | |
1259 | } | |
1260 | ||
1261 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, | |
1262 | BMCR_RESET | BMCR_ANENABLE); | |
1263 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
1264 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
1265 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, | |
1266 | ADVERTISE_1000FULL); | |
1267 | ||
1268 | mii_nway_restart(&dev->mii); | |
1269 | ||
1270 | if ((ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT)) < 0) | |
51bf2976 | 1271 | goto out; |
933a27d3 DH |
1272 | |
1273 | if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0) | |
51bf2976 | 1274 | goto out; |
933a27d3 DH |
1275 | |
1276 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ | |
1277 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1278 | /* hard_mtu is still the default - the device does not support | |
1279 | jumbo eth frames */ | |
1280 | dev->rx_urb_size = 2048; | |
1281 | } | |
2e55cc72 | 1282 | return 0; |
933a27d3 | 1283 | |
51bf2976 | 1284 | out: |
933a27d3 | 1285 | return ret; |
2e55cc72 DB |
1286 | } |
1287 | ||
1288 | static const struct driver_info ax8817x_info = { | |
1289 | .description = "ASIX AX8817x USB 2.0 Ethernet", | |
48b1be6a DH |
1290 | .bind = ax88172_bind, |
1291 | .status = asix_status, | |
2e55cc72 DB |
1292 | .link_reset = ax88172_link_reset, |
1293 | .reset = ax88172_link_reset, | |
1294 | .flags = FLAG_ETHER, | |
1295 | .data = 0x00130103, | |
1296 | }; | |
1297 | ||
1298 | static const struct driver_info dlink_dub_e100_info = { | |
1299 | .description = "DLink DUB-E100 USB Ethernet", | |
48b1be6a DH |
1300 | .bind = ax88172_bind, |
1301 | .status = asix_status, | |
2e55cc72 DB |
1302 | .link_reset = ax88172_link_reset, |
1303 | .reset = ax88172_link_reset, | |
1304 | .flags = FLAG_ETHER, | |
1305 | .data = 0x009f9d9f, | |
1306 | }; | |
1307 | ||
1308 | static const struct driver_info netgear_fa120_info = { | |
1309 | .description = "Netgear FA-120 USB Ethernet", | |
48b1be6a DH |
1310 | .bind = ax88172_bind, |
1311 | .status = asix_status, | |
2e55cc72 DB |
1312 | .link_reset = ax88172_link_reset, |
1313 | .reset = ax88172_link_reset, | |
1314 | .flags = FLAG_ETHER, | |
1315 | .data = 0x00130103, | |
1316 | }; | |
1317 | ||
1318 | static const struct driver_info hawking_uf200_info = { | |
1319 | .description = "Hawking UF200 USB Ethernet", | |
48b1be6a DH |
1320 | .bind = ax88172_bind, |
1321 | .status = asix_status, | |
2e55cc72 DB |
1322 | .link_reset = ax88172_link_reset, |
1323 | .reset = ax88172_link_reset, | |
1324 | .flags = FLAG_ETHER, | |
1325 | .data = 0x001f1d1f, | |
1326 | }; | |
1327 | ||
1328 | static const struct driver_info ax88772_info = { | |
1329 | .description = "ASIX AX88772 USB 2.0 Ethernet", | |
1330 | .bind = ax88772_bind, | |
48b1be6a | 1331 | .status = asix_status, |
2e55cc72 DB |
1332 | .link_reset = ax88772_link_reset, |
1333 | .reset = ax88772_link_reset, | |
1334 | .flags = FLAG_ETHER | FLAG_FRAMING_AX, | |
933a27d3 DH |
1335 | .rx_fixup = asix_rx_fixup, |
1336 | .tx_fixup = asix_tx_fixup, | |
1337 | }; | |
1338 | ||
1339 | static const struct driver_info ax88178_info = { | |
1340 | .description = "ASIX AX88178 USB 2.0 Ethernet", | |
1341 | .bind = ax88178_bind, | |
1342 | .status = asix_status, | |
1343 | .link_reset = ax88178_link_reset, | |
1344 | .reset = ax88178_link_reset, | |
1345 | .flags = FLAG_ETHER | FLAG_FRAMING_AX, | |
1346 | .rx_fixup = asix_rx_fixup, | |
1347 | .tx_fixup = asix_tx_fixup, | |
2e55cc72 DB |
1348 | }; |
1349 | ||
1350 | static const struct usb_device_id products [] = { | |
1351 | { | |
1352 | // Linksys USB200M | |
1353 | USB_DEVICE (0x077b, 0x2226), | |
1354 | .driver_info = (unsigned long) &ax8817x_info, | |
1355 | }, { | |
1356 | // Netgear FA120 | |
1357 | USB_DEVICE (0x0846, 0x1040), | |
1358 | .driver_info = (unsigned long) &netgear_fa120_info, | |
1359 | }, { | |
1360 | // DLink DUB-E100 | |
1361 | USB_DEVICE (0x2001, 0x1a00), | |
1362 | .driver_info = (unsigned long) &dlink_dub_e100_info, | |
1363 | }, { | |
1364 | // Intellinet, ST Lab USB Ethernet | |
1365 | USB_DEVICE (0x0b95, 0x1720), | |
1366 | .driver_info = (unsigned long) &ax8817x_info, | |
1367 | }, { | |
1368 | // Hawking UF200, TrendNet TU2-ET100 | |
1369 | USB_DEVICE (0x07b8, 0x420a), | |
1370 | .driver_info = (unsigned long) &hawking_uf200_info, | |
1371 | }, { | |
39c4b38c DH |
1372 | // Billionton Systems, USB2AR |
1373 | USB_DEVICE (0x08dd, 0x90ff), | |
1374 | .driver_info = (unsigned long) &ax8817x_info, | |
2e55cc72 DB |
1375 | }, { |
1376 | // ATEN UC210T | |
1377 | USB_DEVICE (0x0557, 0x2009), | |
1378 | .driver_info = (unsigned long) &ax8817x_info, | |
1379 | }, { | |
1380 | // Buffalo LUA-U2-KTX | |
1381 | USB_DEVICE (0x0411, 0x003d), | |
1382 | .driver_info = (unsigned long) &ax8817x_info, | |
ac7b77f1 MD |
1383 | }, { |
1384 | // Buffalo LUA-U2-GT 10/100/1000 | |
1385 | USB_DEVICE (0x0411, 0x006e), | |
1386 | .driver_info = (unsigned long) &ax88178_info, | |
2e55cc72 DB |
1387 | }, { |
1388 | // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" | |
1389 | USB_DEVICE (0x6189, 0x182d), | |
1390 | .driver_info = (unsigned long) &ax8817x_info, | |
1391 | }, { | |
1392 | // corega FEther USB2-TX | |
1393 | USB_DEVICE (0x07aa, 0x0017), | |
1394 | .driver_info = (unsigned long) &ax8817x_info, | |
1395 | }, { | |
1396 | // Surecom EP-1427X-2 | |
1397 | USB_DEVICE (0x1189, 0x0893), | |
1398 | .driver_info = (unsigned long) &ax8817x_info, | |
1399 | }, { | |
1400 | // goodway corp usb gwusb2e | |
1401 | USB_DEVICE (0x1631, 0x6200), | |
1402 | .driver_info = (unsigned long) &ax8817x_info, | |
39c4b38c DH |
1403 | }, { |
1404 | // JVC MP-PRX1 Port Replicator | |
1405 | USB_DEVICE (0x04f1, 0x3008), | |
1406 | .driver_info = (unsigned long) &ax8817x_info, | |
2e55cc72 DB |
1407 | }, { |
1408 | // ASIX AX88772 10/100 | |
39c4b38c DH |
1409 | USB_DEVICE (0x0b95, 0x7720), |
1410 | .driver_info = (unsigned long) &ax88772_info, | |
7327413c EW |
1411 | }, { |
1412 | // ASIX AX88178 10/100/1000 | |
1413 | USB_DEVICE (0x0b95, 0x1780), | |
933a27d3 | 1414 | .driver_info = (unsigned long) &ax88178_info, |
5e0f76c6 DH |
1415 | }, { |
1416 | // Linksys USB200M Rev 2 | |
1417 | USB_DEVICE (0x13b1, 0x0018), | |
1418 | .driver_info = (unsigned long) &ax88772_info, | |
5732ce84 DH |
1419 | }, { |
1420 | // 0Q0 cable ethernet | |
1421 | USB_DEVICE (0x1557, 0x7720), | |
1422 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1423 | }, { |
1424 | // DLink DUB-E100 H/W Ver B1 | |
1425 | USB_DEVICE (0x07d1, 0x3c05), | |
1426 | .driver_info = (unsigned long) &ax88772_info, | |
b923e7fc DH |
1427 | }, { |
1428 | // DLink DUB-E100 H/W Ver B1 Alternate | |
1429 | USB_DEVICE (0x2001, 0x3c05), | |
1430 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1431 | }, { |
1432 | // Linksys USB1000 | |
1433 | USB_DEVICE (0x1737, 0x0039), | |
1434 | .driver_info = (unsigned long) &ax88178_info, | |
b29cf31d YH |
1435 | }, { |
1436 | // IO-DATA ETG-US2 | |
1437 | USB_DEVICE (0x04bb, 0x0930), | |
1438 | .driver_info = (unsigned long) &ax88178_info, | |
2ed22bc2 DH |
1439 | }, { |
1440 | // Belkin F5D5055 | |
1441 | USB_DEVICE(0x050d, 0x5055), | |
1442 | .driver_info = (unsigned long) &ax88178_info, | |
2e55cc72 DB |
1443 | }, |
1444 | { }, // END | |
1445 | }; | |
1446 | MODULE_DEVICE_TABLE(usb, products); | |
1447 | ||
1448 | static struct usb_driver asix_driver = { | |
2e55cc72 DB |
1449 | .name = "asix", |
1450 | .id_table = products, | |
1451 | .probe = usbnet_probe, | |
1452 | .suspend = usbnet_suspend, | |
1453 | .resume = usbnet_resume, | |
1454 | .disconnect = usbnet_disconnect, | |
a11a6544 | 1455 | .supports_autosuspend = 1, |
2e55cc72 DB |
1456 | }; |
1457 | ||
1458 | static int __init asix_init(void) | |
1459 | { | |
1460 | return usb_register(&asix_driver); | |
1461 | } | |
1462 | module_init(asix_init); | |
1463 | ||
1464 | static void __exit asix_exit(void) | |
1465 | { | |
1466 | usb_deregister(&asix_driver); | |
1467 | } | |
1468 | module_exit(asix_exit); | |
1469 | ||
1470 | MODULE_AUTHOR("David Hollis"); | |
1471 | MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); | |
1472 | MODULE_LICENSE("GPL"); | |
1473 |