[mirror_ubuntu-artful-kernel.git] / drivers / net / usb / asix.h

/*
 * ASIX AX8817X based USB 2.0 Ethernet Devices
 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
 * Copyright (c) 2002-2003 TiVo Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _ASIX_H
#define _ASIX_H

// #define	DEBUG			// error path messages, extra info
// #define	VERBOSE			// more; success messages

#include <linux/module.h>
#include <linux/kmod.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/workqueue.h>
#include <linux/mii.h>
#include <linux/usb.h>
#include <linux/crc32.h>
#include <linux/usb/usbnet.h>
#include <linux/slab.h>
#include <linux/if_vlan.h>

#define DRIVER_VERSION "22-Dec-2011"
#define DRIVER_NAME "asix"

/* ASIX AX8817X based USB 2.0 Ethernet Devices */

#define AX_CMD_SET_SW_MII		0x06
#define AX_CMD_READ_MII_REG		0x07
#define AX_CMD_WRITE_MII_REG		0x08
#define AX_CMD_STATMNGSTS_REG		0x09
#define AX_CMD_SET_HW_MII		0x0a
#define AX_CMD_READ_EEPROM		0x0b
#define AX_CMD_WRITE_EEPROM		0x0c
#define AX_CMD_WRITE_ENABLE		0x0d
#define AX_CMD_WRITE_DISABLE		0x0e
#define AX_CMD_READ_RX_CTL		0x0f
#define AX_CMD_WRITE_RX_CTL		0x10
#define AX_CMD_READ_IPG012		0x11
#define AX_CMD_WRITE_IPG0		0x12
#define AX_CMD_WRITE_IPG1		0x13
#define AX_CMD_READ_NODE_ID		0x13
#define AX_CMD_WRITE_NODE_ID		0x14
#define AX_CMD_WRITE_IPG2		0x14
#define AX_CMD_WRITE_MULTI_FILTER	0x16
#define AX88172_CMD_READ_NODE_ID	0x17
#define AX_CMD_READ_PHY_ID		0x19
#define AX_CMD_READ_MEDIUM_STATUS	0x1a
#define AX_CMD_WRITE_MEDIUM_MODE	0x1b
#define AX_CMD_READ_MONITOR_MODE	0x1c
#define AX_CMD_WRITE_MONITOR_MODE	0x1d
#define AX_CMD_READ_GPIOS		0x1e
#define AX_CMD_WRITE_GPIOS		0x1f
#define AX_CMD_SW_RESET			0x20
#define AX_CMD_SW_PHY_STATUS		0x21
#define AX_CMD_SW_PHY_SELECT		0x22
#define AX_QCTCTRL			0x2A

#define AX_CHIPCODE_MASK		0x70
#define AX_AX88772_CHIPCODE		0x00
#define AX_AX88772A_CHIPCODE		0x10
#define AX_AX88772B_CHIPCODE		0x20
#define AX_HOST_EN			0x01

#define AX_PHYSEL_PSEL			0x01
#define AX_PHYSEL_SSMII			0
#define AX_PHYSEL_SSEN			0x10

#define AX_PHY_SELECT_MASK		(BIT(3) | BIT(2))
#define AX_PHY_SELECT_INTERNAL		0
#define AX_PHY_SELECT_EXTERNAL		BIT(2)

#define AX_MONITOR_MODE			0x01
#define AX_MONITOR_LINK			0x02
#define AX_MONITOR_MAGIC		0x04
#define AX_MONITOR_HSFS			0x10

/* AX88172 Medium Status Register values */
#define AX88172_MEDIUM_FD		0x02
#define AX88172_MEDIUM_TX		0x04
#define AX88172_MEDIUM_FC		0x10
#define AX88172_MEDIUM_DEFAULT \
		( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )

#define AX_MCAST_FILTER_SIZE		8
#define AX_MAX_MCAST			64

#define AX_SWRESET_CLEAR		0x00
#define AX_SWRESET_RR			0x01
#define AX_SWRESET_RT			0x02
#define AX_SWRESET_PRTE			0x04
#define AX_SWRESET_PRL			0x08
#define AX_SWRESET_BZ			0x10
#define AX_SWRESET_IPRL			0x20
#define AX_SWRESET_IPPD			0x40

#define AX88772_IPG0_DEFAULT		0x15
#define AX88772_IPG1_DEFAULT		0x0c
#define AX88772_IPG2_DEFAULT		0x12

/* AX88772 & AX88178 Medium Mode Register */
#define AX_MEDIUM_PF		0x0080
#define AX_MEDIUM_JFE		0x0040
#define AX_MEDIUM_TFC		0x0020
#define AX_MEDIUM_RFC		0x0010
#define AX_MEDIUM_ENCK		0x0008
#define AX_MEDIUM_AC		0x0004
#define AX_MEDIUM_FD		0x0002
#define AX_MEDIUM_GM		0x0001
#define AX_MEDIUM_SM		0x1000
#define AX_MEDIUM_SBP		0x0800
#define AX_MEDIUM_PS		0x0200
#define AX_MEDIUM_RE		0x0100

#define AX88178_MEDIUM_DEFAULT	\
	(AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
	 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
	 AX_MEDIUM_RE)

#define AX88772_MEDIUM_DEFAULT	\
	(AX_MEDIUM_FD | AX_MEDIUM_RFC | \
	 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
	 AX_MEDIUM_AC | AX_MEDIUM_RE)

/* AX88772 & AX88178 RX_CTL values */
#define AX_RX_CTL_SO		0x0080
#define AX_RX_CTL_AP		0x0020
#define AX_RX_CTL_AM		0x0010
#define AX_RX_CTL_AB		0x0008
#define AX_RX_CTL_SEP		0x0004
#define AX_RX_CTL_AMALL		0x0002
#define AX_RX_CTL_PRO		0x0001
#define AX_RX_CTL_MFB_2048	0x0000
#define AX_RX_CTL_MFB_4096	0x0100
#define AX_RX_CTL_MFB_8192	0x0200
#define AX_RX_CTL_MFB_16384	0x0300

#define AX_DEFAULT_RX_CTL	(AX_RX_CTL_SO | AX_RX_CTL_AB)

/* GPIO 0 .. 2 toggles */
#define AX_GPIO_GPO0EN		0x01	/* GPIO0 Output enable */
#define AX_GPIO_GPO_0		0x02	/* GPIO0 Output value */
#define AX_GPIO_GPO1EN		0x04	/* GPIO1 Output enable */
#define AX_GPIO_GPO_1		0x08	/* GPIO1 Output value */
#define AX_GPIO_GPO2EN		0x10	/* GPIO2 Output enable */
#define AX_GPIO_GPO_2		0x20	/* GPIO2 Output value */
#define AX_GPIO_RESERVED	0x40	/* Reserved */
#define AX_GPIO_RSE		0x80	/* Reload serial EEPROM */

#define AX_EEPROM_MAGIC		0xdeadbeef
#define AX_EEPROM_LEN		0x200

/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
struct asix_data {
	u8 multi_filter[AX_MCAST_FILTER_SIZE];
	u8 mac_addr[ETH_ALEN];
	u8 phymode;
	u8 ledmode;
	u8 res;
};

struct asix_rx_fixup_info {
	struct sk_buff *ax_skb;
	u32 header;
	u16 remaining;
	bool split_head;
};

struct asix_common_private {
	void (*resume)(struct usbnet *dev);
	void (*suspend)(struct usbnet *dev);
	u16 presvd_phy_advertise;
	u16 presvd_phy_bmcr;
	struct asix_rx_fixup_info rx_fixup_info;
};

extern const struct driver_info ax88172a_info;

/* ASIX specific flags */
#define FLAG_EEPROM_MAC		(1UL << 0)  /* init device MAC from eeprom */

int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
		  u16 size, void *data, int in_pm);

int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
		   u16 size, void *data, int in_pm);

void asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
			  u16 index, u16 size, void *data);

int asix_rx_fixup_internal(struct usbnet *dev, struct sk_buff *skb,
			   struct asix_rx_fixup_info *rx);
int asix_rx_fixup_common(struct usbnet *dev, struct sk_buff *skb);
void asix_rx_fixup_common_free(struct asix_common_private *dp);

struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
			      gfp_t flags);

int asix_set_sw_mii(struct usbnet *dev, int in_pm);
int asix_set_hw_mii(struct usbnet *dev, int in_pm);

int asix_read_phy_addr(struct usbnet *dev, int internal);
int asix_get_phy_addr(struct usbnet *dev);

int asix_sw_reset(struct usbnet *dev, u8 flags, int in_pm);

u16 asix_read_rx_ctl(struct usbnet *dev, int in_pm);
int asix_write_rx_ctl(struct usbnet *dev, u16 mode, int in_pm);

u16 asix_read_medium_status(struct usbnet *dev, int in_pm);
int asix_write_medium_mode(struct usbnet *dev, u16 mode, int in_pm);

int asix_write_gpio(struct usbnet *dev, u16 value, int sleep, int in_pm);

void asix_set_multicast(struct net_device *net);

int asix_mdio_read(struct net_device *netdev, int phy_id, int loc);
void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val);

int asix_mdio_read_nopm(struct net_device *netdev, int phy_id, int loc);
void asix_mdio_write_nopm(struct net_device *netdev, int phy_id, int loc,
			  int val);

void asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
int asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);

int asix_get_eeprom_len(struct net_device *net);
int asix_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
		    u8 *data);
int asix_set_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
		    u8 *data);

void asix_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info);

int asix_set_mac_address(struct net_device *net, void *p);

#endif /* _ASIX_H */
Commit	Line	Data
2e55cc72 DB	1	/*
2e55cc72 DB	2	* ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3	3	* Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72	4	* Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3	5	* Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72 DB	6	* Copyright (c) 2002-2003 TiVo Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
9cb00073	19	* along with this program; if not, see <http://www.gnu.org/licenses/>.
2e55cc72 DB	20	*/
2e55cc72 DB	21
607740bc CR	22	#ifndef _ASIX_H
	23	#define _ASIX_H
	24
2e55cc72 DB	25	// #define DEBUG // error path messages, extra info
	26	// #define VERBOSE // more; success messages
	27
2e55cc72 DB	28	#include <linux/module.h>
2e55cc72 DB	29	#include <linux/kmod.h>
2e55cc72 DB	30	#include <linux/netdevice.h>
	31	#include <linux/etherdevice.h>
	32	#include <linux/ethtool.h>
	33	#include <linux/workqueue.h>
	34	#include <linux/mii.h>
	35	#include <linux/usb.h>
	36	#include <linux/crc32.h>
3692e94f	37	#include <linux/usb/usbnet.h>
5a0e3ad6	38	#include <linux/slab.h>
9dae3100	39	#include <linux/if_vlan.h>
2e55cc72	40
f87ce5b2	41	#define DRIVER_VERSION "22-Dec-2011"
83e1b918	42	#define DRIVER_NAME "asix"
933a27d3	43
2e55cc72 DB	44	/* ASIX AX8817X based USB 2.0 Ethernet Devices */
	45
	46	#define AX_CMD_SET_SW_MII 0x06
	47	#define AX_CMD_READ_MII_REG 0x07
	48	#define AX_CMD_WRITE_MII_REG 0x08
d9fe64e5	49	#define AX_CMD_STATMNGSTS_REG 0x09
2e55cc72 DB	50	#define AX_CMD_SET_HW_MII 0x0a
	51	#define AX_CMD_READ_EEPROM 0x0b
	52	#define AX_CMD_WRITE_EEPROM 0x0c
	53	#define AX_CMD_WRITE_ENABLE 0x0d
	54	#define AX_CMD_WRITE_DISABLE 0x0e
933a27d3	55	#define AX_CMD_READ_RX_CTL 0x0f
2e55cc72 DB	56	#define AX_CMD_WRITE_RX_CTL 0x10
	57	#define AX_CMD_READ_IPG012 0x11
	58	#define AX_CMD_WRITE_IPG0 0x12
	59	#define AX_CMD_WRITE_IPG1 0x13
933a27d3	60	#define AX_CMD_READ_NODE_ID 0x13
7f29a3ba	61	#define AX_CMD_WRITE_NODE_ID 0x14
2e55cc72 DB	62	#define AX_CMD_WRITE_IPG2 0x14
2e55cc72 DB	63	#define AX_CMD_WRITE_MULTI_FILTER 0x16
933a27d3	64	#define AX88172_CMD_READ_NODE_ID 0x17
2e55cc72 DB	65	#define AX_CMD_READ_PHY_ID 0x19
	66	#define AX_CMD_READ_MEDIUM_STATUS 0x1a
	67	#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
	68	#define AX_CMD_READ_MONITOR_MODE 0x1c
	69	#define AX_CMD_WRITE_MONITOR_MODE 0x1d
933a27d3	70	#define AX_CMD_READ_GPIOS 0x1e
2e55cc72 DB	71	#define AX_CMD_WRITE_GPIOS 0x1f
	72	#define AX_CMD_SW_RESET 0x20
	73	#define AX_CMD_SW_PHY_STATUS 0x21
	74	#define AX_CMD_SW_PHY_SELECT 0x22
d9fe64e5 RF	75	#define AX_QCTCTRL 0x2A
	76
	77	#define AX_CHIPCODE_MASK 0x70
	78	#define AX_AX88772_CHIPCODE 0x00
	79	#define AX_AX88772A_CHIPCODE 0x10
	80	#define AX_AX88772B_CHIPCODE 0x20
	81	#define AX_HOST_EN 0x01
	82
	83	#define AX_PHYSEL_PSEL 0x01
	84	#define AX_PHYSEL_SSMII 0
	85	#define AX_PHYSEL_SSEN 0x10
2e55cc72	86
16626b0c CR	87	#define AX_PHY_SELECT_MASK (BIT(3) \| BIT(2))
	88	#define AX_PHY_SELECT_INTERNAL 0
	89	#define AX_PHY_SELECT_EXTERNAL BIT(2)
	90
2e55cc72 DB	91	#define AX_MONITOR_MODE 0x01
	92	#define AX_MONITOR_LINK 0x02
	93	#define AX_MONITOR_MAGIC 0x04
	94	#define AX_MONITOR_HSFS 0x10
	95
	96	/* AX88172 Medium Status Register values */
933a27d3 DH	97	#define AX88172_MEDIUM_FD 0x02
	98	#define AX88172_MEDIUM_TX 0x04
	99	#define AX88172_MEDIUM_FC 0x10
	100	#define AX88172_MEDIUM_DEFAULT \
	101	( AX88172_MEDIUM_FD \| AX88172_MEDIUM_TX \| AX88172_MEDIUM_FC )
2e55cc72 DB	102
	103	#define AX_MCAST_FILTER_SIZE 8
	104	#define AX_MAX_MCAST 64
	105
2e55cc72 DB	106	#define AX_SWRESET_CLEAR 0x00
	107	#define AX_SWRESET_RR 0x01
	108	#define AX_SWRESET_RT 0x02
	109	#define AX_SWRESET_PRTE 0x04
	110	#define AX_SWRESET_PRL 0x08
	111	#define AX_SWRESET_BZ 0x10
	112	#define AX_SWRESET_IPRL 0x20
	113	#define AX_SWRESET_IPPD 0x40
	114
	115	#define AX88772_IPG0_DEFAULT 0x15
	116	#define AX88772_IPG1_DEFAULT 0x0c
	117	#define AX88772_IPG2_DEFAULT 0x12
	118
933a27d3 DH	119	/* AX88772 & AX88178 Medium Mode Register */
	120	#define AX_MEDIUM_PF 0x0080
	121	#define AX_MEDIUM_JFE 0x0040
	122	#define AX_MEDIUM_TFC 0x0020
	123	#define AX_MEDIUM_RFC 0x0010
	124	#define AX_MEDIUM_ENCK 0x0008
	125	#define AX_MEDIUM_AC 0x0004
	126	#define AX_MEDIUM_FD 0x0002
	127	#define AX_MEDIUM_GM 0x0001
	128	#define AX_MEDIUM_SM 0x1000
	129	#define AX_MEDIUM_SBP 0x0800
	130	#define AX_MEDIUM_PS 0x0200
	131	#define AX_MEDIUM_RE 0x0100
	132
	133	#define AX88178_MEDIUM_DEFAULT \
	134	(AX_MEDIUM_PS \| AX_MEDIUM_FD \| AX_MEDIUM_AC \| \
	135	AX_MEDIUM_RFC \| AX_MEDIUM_TFC \| AX_MEDIUM_JFE \| \
83e1b918	136	AX_MEDIUM_RE)
2e55cc72	137
933a27d3 DH	138	#define AX88772_MEDIUM_DEFAULT \
	139	(AX_MEDIUM_FD \| AX_MEDIUM_RFC \| \
	140	AX_MEDIUM_TFC \| AX_MEDIUM_PS \| \
83e1b918	141	AX_MEDIUM_AC \| AX_MEDIUM_RE)
933a27d3 DH	142
933a27d3 DH	143	/* AX88772 & AX88178 RX_CTL values */
83e1b918 GG	144	#define AX_RX_CTL_SO 0x0080
	145	#define AX_RX_CTL_AP 0x0020
	146	#define AX_RX_CTL_AM 0x0010
	147	#define AX_RX_CTL_AB 0x0008
	148	#define AX_RX_CTL_SEP 0x0004
	149	#define AX_RX_CTL_AMALL 0x0002
	150	#define AX_RX_CTL_PRO 0x0001
	151	#define AX_RX_CTL_MFB_2048 0x0000
	152	#define AX_RX_CTL_MFB_4096 0x0100
	153	#define AX_RX_CTL_MFB_8192 0x0200
	154	#define AX_RX_CTL_MFB_16384 0x0300
	155
	156	#define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO \| AX_RX_CTL_AB)
933a27d3 DH	157
	158	/* GPIO 0 .. 2 toggles */
	159	#define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */
	160	#define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */
	161	#define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */
	162	#define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */
	163	#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
	164	#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
	165	#define AX_GPIO_RESERVED 0x40 /* Reserved */
	166	#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
	167
	168	#define AX_EEPROM_MAGIC 0xdeadbeef
ceb02c91	169	#define AX_EEPROM_LEN 0x200
933a27d3	170
2e55cc72	171	/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
48b1be6a	172	struct asix_data {
2e55cc72	173	u8 multi_filter[AX_MCAST_FILTER_SIZE];
7f29a3ba	174	u8 mac_addr[ETH_ALEN];
933a27d3 DH	175	u8 phymode;
933a27d3 DH	176	u8 ledmode;
ceb02c91	177	u8 res;
2e55cc72 DB	178	};
2e55cc72 DB	179
8b5b6f54 LS	180	struct asix_rx_fixup_info {
	181	struct sk_buff *ax_skb;
	182	u32 header;
7b0378f5	183	u16 remaining;
8b5b6f54 LS	184	bool split_head;
	185	};
	186
	187	struct asix_common_private {
d9fe64e5 RF	188	void (resume)(struct usbnet dev);
	189	void (suspend)(struct usbnet dev);
	190	u16 presvd_phy_advertise;
	191	u16 presvd_phy_bmcr;
8b5b6f54 LS	192	struct asix_rx_fixup_info rx_fixup_info;
	193	};
	194
55d10a11 MB	195	extern const struct driver_info ax88172a_info;
55d10a11 MB	196
5620df65 LS	197	/* ASIX specific flags */
	198	#define FLAG_EEPROM_MAC (1UL << 0) /* init device MAC from eeprom */
	199
607740bc	200	int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
d9fe64e5	201	u16 size, void *data, int in_pm);
933a27d3	202
607740bc	203	int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
d9fe64e5	204	u16 size, void *data, int in_pm);
933a27d3	205
607740bc CR	206	void asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
607740bc CR	207	u16 index, u16 size, void *data);
933a27d3	208
8b5b6f54 LS	209	int asix_rx_fixup_internal(struct usbnet dev, struct sk_buff skb,
	210	struct asix_rx_fixup_info *rx);
	211	int asix_rx_fixup_common(struct usbnet dev, struct sk_buff skb);
d0c8f338	212	void asix_rx_fixup_common_free(struct asix_common_private *dp);
933a27d3	213
607740bc CR	214	struct sk_buff asix_tx_fixup(struct usbnet dev, struct sk_buff *skb,
607740bc CR	215	gfp_t flags);
933a27d3	216
d9fe64e5 RF	217	int asix_set_sw_mii(struct usbnet *dev, int in_pm);
d9fe64e5 RF	218	int asix_set_hw_mii(struct usbnet *dev, int in_pm);
933a27d3	219
16626b0c	220	int asix_read_phy_addr(struct usbnet *dev, int internal);
607740bc	221	int asix_get_phy_addr(struct usbnet *dev);
933a27d3	222
d9fe64e5	223	int asix_sw_reset(struct usbnet *dev, u8 flags, int in_pm);
933a27d3	224
d9fe64e5 RF	225	u16 asix_read_rx_ctl(struct usbnet *dev, int in_pm);
d9fe64e5 RF	226	int asix_write_rx_ctl(struct usbnet *dev, u16 mode, int in_pm);
933a27d3	227
d9fe64e5 RF	228	u16 asix_read_medium_status(struct usbnet *dev, int in_pm);
d9fe64e5 RF	229	int asix_write_medium_mode(struct usbnet *dev, u16 mode, int in_pm);
2e55cc72	230
d9fe64e5	231	int asix_write_gpio(struct usbnet *dev, u16 value, int sleep, int in_pm);
933a27d3	232
607740bc	233	void asix_set_multicast(struct net_device *net);
933a27d3	234
607740bc CR	235	int asix_mdio_read(struct net_device *netdev, int phy_id, int loc);
607740bc CR	236	void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val);
933a27d3	237
d9fe64e5 RF	238	int asix_mdio_read_nopm(struct net_device *netdev, int phy_id, int loc);
	239	void asix_mdio_write_nopm(struct net_device *netdev, int phy_id, int loc,
	240	int val);
	241
607740bc CR	242	void asix_get_wol(struct net_device net, struct ethtool_wolinfo wolinfo);
607740bc CR	243	int asix_set_wol(struct net_device net, struct ethtool_wolinfo wolinfo);
933a27d3	244
607740bc CR	245	int asix_get_eeprom_len(struct net_device *net);
	246	int asix_get_eeprom(struct net_device net, struct ethtool_eeprom eeprom,
	247	u8 *data);
cb7b24cd CR	248	int asix_set_eeprom(struct net_device net, struct ethtool_eeprom eeprom,
cb7b24cd CR	249	u8 *data);
2e55cc72	250
607740bc	251	void asix_get_drvinfo(struct net_device net, struct ethtool_drvinfo info);
2e55cc72	252
607740bc	253	int asix_set_mac_address(struct net_device net, void p);
2e55cc72	254
607740bc	255	#endif /* _ASIX_H */