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Merge tag 'linux-kselftest-4.13-rc6-fixes' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-artful-kernel.git] / drivers / net / usb / asix_devices.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
9cb00073 19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
2e55cc72
DB		 20 */
21
607740bc 22#include "asix.h"
933a27d3
DH		 23
24#define PHY_MODE_MARVELL 0x0000
25#define MII_MARVELL_LED_CTRL 0x0018
26#define MII_MARVELL_STATUS 0x001b
27#define MII_MARVELL_CTRL 0x0014
28
29#define MARVELL_LED_MANUAL 0x0019
30
31#define MARVELL_STATUS_HWCFG 0x0004
32
33#define MARVELL_CTRL_TXDELAY 0x0002
34#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72 35
3486140e 36#define PHY_MODE_RTL8211CL 0x000C
610d885d 37
4c1442aa
RF		 38#define AX88772A_PHY14H 0x14
39#define AX88772A_PHY14H_DEFAULT 0x442C
40
41#define AX88772A_PHY15H 0x15
42#define AX88772A_PHY15H_DEFAULT 0x03C8
43
44#define AX88772A_PHY16H 0x16
45#define AX88772A_PHY16H_DEFAULT 0x4044
46
2e55cc72 47struct ax88172_int_data {
51bf2976 48 __le16 res1;
2e55cc72 49 u8 link;
51bf2976 50 __le16 res2;
2e55cc72 51 u8 status;
51bf2976 52 __le16 res3;
ba2d3587 53} __packed;
2e55cc72 54
933a27d3
DH		 55static void asix_status(struct usbnet *dev, struct urb *urb)
56{
57 struct ax88172_int_data *event;
58 int link;
59
60 if (urb->actual_length < 8)
61 return;
62
63 event = urb->transfer_buffer;
64 link = event->link & 0x01;
65 if (netif_carrier_ok(dev->net) != link) {
eae65919 66 usbnet_link_change(dev, link, 1);
60b86755 67 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH		 68 }
69}
70
452b5ecd
JCPV		 71static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
72{
73 if (is_valid_ether_addr(addr)) {
74 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
75 } else {
76 netdev_info(dev->net, "invalid hw address, using random\n");
77 eth_hw_addr_random(dev->net);
78 }
79}
80
933a27d3
DH		 81/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
82static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 83{
933a27d3
DH		 84 int phy_reg;
85 u32 phy_id;
a77929a2 86 int i;
2e55cc72 87
a77929a2
GG		 88 /* Poll for the rare case the FW or phy isn't ready yet. */
89 for (i = 0; i < 100; i++) {
90 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
8a46f665
RF		 91 if (phy_reg < 0)
92 return 0;
a77929a2
GG		 93 if (phy_reg != 0 && phy_reg != 0xFFFF)
94 break;
95 mdelay(1);
96 }
97
98 if (phy_reg <= 0 || phy_reg == 0xFFFF)
933a27d3 99 return 0;
2e55cc72 100
933a27d3 101 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 102
933a27d3
DH		 103 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
104 if (phy_reg < 0)
105 return 0;
106
107 phy_id |= (phy_reg & 0xffff);
108
109 return phy_id;
2e55cc72
DB		 110}
111
933a27d3
DH		 112static u32 asix_get_link(struct net_device *net)
113{
114 struct usbnet *dev = netdev_priv(net);
115
116 return mii_link_ok(&dev->mii);
117}
118
119static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
120{
121 struct usbnet *dev = netdev_priv(net);
122
123 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
124}
125
126/* We need to override some ethtool_ops so we require our
127 own structure so we don't interfere with other usbnet
128 devices that may be connected at the same time. */
0fc0b732 129static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH		 130 .get_drvinfo = asix_get_drvinfo,
131 .get_link = asix_get_link,
933a27d3 132 .get_msglevel = usbnet_get_msglevel,
2e55cc72 133 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 134 .get_wol = asix_get_wol,
135 .set_wol = asix_set_wol,
136 .get_eeprom_len = asix_get_eeprom_len,
137 .get_eeprom = asix_get_eeprom,
cb7b24cd 138 .set_eeprom = asix_set_eeprom,
c41286fd 139 .nway_reset = usbnet_nway_reset,
fd4f0a75
PR		 140 .get_link_ksettings = usbnet_get_link_ksettings,
141 .set_link_ksettings = usbnet_set_link_ksettings,
2e55cc72
DB		 142};
143
933a27d3 144static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 145{
146 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 147 struct asix_data *data = (struct asix_data *)&dev->data;
148 u8 rx_ctl = 0x8c;
2e55cc72 149
933a27d3
DH		 150 if (net->flags & IFF_PROMISC) {
151 rx_ctl |= 0x01;
8e95a202 152 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 153 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 154 rx_ctl |= 0x02;
4cd24eaf 155 } else if (netdev_mc_empty(net)) {
933a27d3
DH		 156 /* just broadcast and directed */
157 } else {
158 /* We use the 20 byte dev->data
159 * for our 8 byte filter buffer
160 * to avoid allocating memory that
161 * is tricky to free later */
22bedad3 162 struct netdev_hw_addr *ha;
933a27d3 163 u32 crc_bits;
933a27d3
DH		 164
165 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
166
167 /* Build the multicast hash filter. */
22bedad3
JP		 168 netdev_for_each_mc_addr(ha, net) {
169 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
933a27d3
DH		 170 data->multi_filter[crc_bits >> 3] |=
171 1 << (crc_bits & 7);
933a27d3
DH		 172 }
173
174 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
175 AX_MCAST_FILTER_SIZE, data->multi_filter);
176
177 rx_ctl |= 0x10;
178 }
179
180 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
181}
182
183static int ax88172_link_reset(struct usbnet *dev)
184{
185 u8 mode;
8ae6daca 186 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 187
188 mii_check_media(&dev->mii, 1, 1);
189 mii_ethtool_gset(&dev->mii, &ecmd);
190 mode = AX88172_MEDIUM_DEFAULT;
191
192 if (ecmd.duplex != DUPLEX_FULL)
193 mode |= ~AX88172_MEDIUM_FD;
194
8ae6daca
DD		 195 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
196 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3 197
d9fe64e5 198 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 199
200 return 0;
2e55cc72
DB		 201}
202
1703338c
SH		 203static const struct net_device_ops ax88172_netdev_ops = {
204 .ndo_open = usbnet_open,
205 .ndo_stop = usbnet_stop,
206 .ndo_start_xmit = usbnet_start_xmit,
207 .ndo_tx_timeout = usbnet_tx_timeout,
208 .ndo_change_mtu = usbnet_change_mtu,
c8b5d129 209 .ndo_get_stats64 = usbnet_get_stats64,
1703338c
SH		 210 .ndo_set_mac_address = eth_mac_addr,
211 .ndo_validate_addr = eth_validate_addr,
212 .ndo_do_ioctl = asix_ioctl,
afc4b13d 213 .ndo_set_rx_mode = ax88172_set_multicast,
1703338c
SH		 214};
215
a243c2ef
RF		 216static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
217{
218 unsigned int timeout = 5000;
219
220 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
221
222 /* give phy_id a chance to process reset */
223 udelay(500);
224
225 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
226 while (timeout--) {
227 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
228 & BMCR_RESET)
229 udelay(100);
230 else
231 return;
232 }
233
234 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
235 dev->mii.phy_id);
236}
237
48b1be6a 238static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 239{
240 int ret = 0;
51bf2976 241 u8 buf[ETH_ALEN];
2e55cc72
DB		 242 int i;
243 unsigned long gpio_bits = dev->driver_info->data;
244
245 usbnet_get_endpoints(dev,intf);
246
2e55cc72
DB		 247 /* Toggle the GPIOs in a manufacturer/model specific way */
248 for (i = 2; i >= 0; i--) {
83e1b918 249 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
d9fe64e5 250 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
83e1b918 251 if (ret < 0)
51bf2976 252 goto out;
2e55cc72
DB		 253 msleep(5);
254 }
255
d9fe64e5 256 ret = asix_write_rx_ctl(dev, 0x80, 0);
83e1b918 257 if (ret < 0)
51bf2976 258 goto out;
2e55cc72
DB		 259
260 /* Get the MAC address */
d9fe64e5
RF		 261 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
262 0, 0, ETH_ALEN, buf, 0);
83e1b918 263 if (ret < 0) {
49ae25b0
GKH		 264 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
265 ret);
51bf2976 266 goto out;
2e55cc72 267 }
452b5ecd
JCPV		 268
269 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 270
2e55cc72
DB		 271 /* Initialize MII structure */
272 dev->mii.dev = dev->net;
48b1be6a
DH		 273 dev->mii.mdio_read = asix_mdio_read;
274 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 275 dev->mii.phy_id_mask = 0x3f;
276 dev->mii.reg_num_mask = 0x1f;
933a27d3 277 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 278
1703338c 279 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 280 dev->net->ethtool_ops = &ax88172_ethtool_ops;
95162d65
ED		 281 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
282 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
2e55cc72 283
a243c2ef 284 asix_phy_reset(dev, BMCR_RESET);
933a27d3 285 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 286 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
287 mii_nway_restart(&dev->mii);
288
289 return 0;
51bf2976
AV		 290
291out:
2e55cc72
DB		 292 return ret;
293}
294
0fc0b732 295static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 296 .get_drvinfo = asix_get_drvinfo,
933a27d3 297 .get_link = asix_get_link,
2e55cc72
DB		 298 .get_msglevel = usbnet_get_msglevel,
299 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 300 .get_wol = asix_get_wol,
301 .set_wol = asix_set_wol,
302 .get_eeprom_len = asix_get_eeprom_len,
303 .get_eeprom = asix_get_eeprom,
cb7b24cd 304 .set_eeprom = asix_set_eeprom,
c41286fd 305 .nway_reset = usbnet_nway_reset,
fd4f0a75
PR		 306 .get_link_ksettings = usbnet_get_link_ksettings,
307 .set_link_ksettings = usbnet_set_link_ksettings,
2e55cc72
DB		 308};
309
933a27d3
DH		 310static int ax88772_link_reset(struct usbnet *dev)
311{
312 u16 mode;
8ae6daca 313 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 314
315 mii_check_media(&dev->mii, 1, 1);
316 mii_ethtool_gset(&dev->mii, &ecmd);
317 mode = AX88772_MEDIUM_DEFAULT;
318
8ae6daca 319 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
933a27d3
DH		 320 mode &= ~AX_MEDIUM_PS;
321
322 if (ecmd.duplex != DUPLEX_FULL)
323 mode &= ~AX_MEDIUM_FD;
324
8ae6daca
DD		 325 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
326 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3 327
d9fe64e5 328 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 329
330 return 0;
331}
332
4ad1438f 333static int ax88772_reset(struct usbnet *dev)
d9fe64e5
RF		 334{
335 struct asix_data *data = (struct asix_data *)&dev->data;
336 int ret;
337
338 /* Rewrite MAC address */
339 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
340 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
341 ETH_ALEN, data->mac_addr, 0);
342 if (ret < 0)
343 goto out;
344
345 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
346 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
347 if (ret < 0)
348 goto out;
349
4f3de46f 350 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
d9fe64e5
RF		 351 if (ret < 0)
352 goto out;
353
354 return 0;
355
356out:
357 return ret;
358}
359
360static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
2e55cc72 361{
8ef66bdc 362 struct asix_data *data = (struct asix_data *)&dev->data;
d0ffff8f 363 int ret, embd_phy;
933a27d3 364 u16 rx_ctl;
2e55cc72 365
d9fe64e5
RF		 366 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
367 AX_GPIO_GPO2EN, 5, in_pm);
83e1b918 368 if (ret < 0)
51bf2976 369 goto out;
2e55cc72 370
d9fe64e5 371 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
4ad1438f 372
d9fe64e5
RF		 373 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy,
374 0, 0, NULL, in_pm);
83e1b918 375 if (ret < 0) {
49ae25b0 376 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
51bf2976 377 goto out;
2e55cc72
DB		 378 }
379
d9fe64e5
RF		 380 if (embd_phy) {
381 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
382 if (ret < 0)
383 goto out;
2e55cc72 384
d9fe64e5 385 usleep_range(10000, 11000);
83e1b918 386
d9fe64e5
RF		 387 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
388 if (ret < 0)
389 goto out;
2e55cc72 390
d9fe64e5 391 msleep(60);
4ad1438f 392
d9fe64e5
RF		 393 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
394 in_pm);
83e1b918 395 if (ret < 0)
51bf2976 396 goto out;
83e1b918 397 } else {
d9fe64e5
RF		 398 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
399 in_pm);
83e1b918 400 if (ret < 0)
51bf2976 401 goto out;
d0ffff8f 402 }
2e55cc72
DB		 403
404 msleep(150);
d9fe64e5
RF		 405
406 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
407 MII_PHYSID1))){
408 ret = -EIO;
409 goto out;
410 }
411
412 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
413 if (ret < 0)
414 goto out;
415
416 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
83e1b918 417 if (ret < 0)
51bf2976 418 goto out;
2e55cc72 419
d9fe64e5
RF		 420 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
421 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
422 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
423 if (ret < 0) {
424 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
425 goto out;
426 }
933a27d3 427
d9fe64e5
RF		 428 /* Rewrite MAC address */
429 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
430 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
431 ETH_ALEN, data->mac_addr, in_pm);
83e1b918 432 if (ret < 0)
51bf2976 433 goto out;
2e55cc72 434
d9fe64e5
RF		 435 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
436 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
437 if (ret < 0)
438 goto out;
439
440 rx_ctl = asix_read_rx_ctl(dev, in_pm);
441 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
442 rx_ctl);
443
444 rx_ctl = asix_read_medium_status(dev, in_pm);
445 netdev_dbg(dev->net,
446 "Medium Status is 0x%04x after all initializations\n",
447 rx_ctl);
448
449 return 0;
450
451out:
452 return ret;
453}
454
455static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
456{
457 struct asix_data *data = (struct asix_data *)&dev->data;
458 int ret, embd_phy;
4c1442aa 459 u16 rx_ctl, phy14h, phy15h, phy16h;
d9fe64e5 460 u8 chipcode = 0;
48b1be6a 461
d9fe64e5 462 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
83e1b918 463 if (ret < 0)
51bf2976 464 goto out;
2e55cc72 465
d9fe64e5 466 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
2e55cc72 467
d9fe64e5
RF		 468 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy |
469 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
470 if (ret < 0) {
471 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
472 goto out;
473 }
474 usleep_range(10000, 11000);
2e55cc72 475
d9fe64e5 476 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
83e1b918 477 if (ret < 0)
51bf2976 478 goto out;
2e55cc72 479
d9fe64e5
RF		 480 usleep_range(10000, 11000);
481
482 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
483 if (ret < 0)
484 goto out;
485
486 msleep(160);
487
488 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
489 if (ret < 0)
490 goto out;
491
492 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
493 if (ret < 0)
494 goto out;
495
496 msleep(200);
497
498 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
499 MII_PHYSID1))) {
500 ret = -1;
501 goto out;
502 }
503
504 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0,
505 0, 1, &chipcode, in_pm);
506 if (ret < 0)
507 goto out;
508
509 if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) {
510 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
511 0, NULL, in_pm);
512 if (ret < 0) {
513 netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
514 ret);
515 goto out;
516 }
4c1442aa
RF		 517 } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) {
518 /* Check if the PHY registers have default settings */
519 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
520 AX88772A_PHY14H);
521 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
522 AX88772A_PHY15H);
523 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
524 AX88772A_PHY16H);
525
526 netdev_dbg(dev->net,
527 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
528 phy14h, phy15h, phy16h);
529
530 /* Restore PHY registers default setting if not */
531 if (phy14h != AX88772A_PHY14H_DEFAULT)
532 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
533 AX88772A_PHY14H,
534 AX88772A_PHY14H_DEFAULT);
535 if (phy15h != AX88772A_PHY15H_DEFAULT)
536 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
537 AX88772A_PHY15H,
538 AX88772A_PHY15H_DEFAULT);
539 if (phy16h != AX88772A_PHY16H_DEFAULT)
540 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
541 AX88772A_PHY16H,
542 AX88772A_PHY16H_DEFAULT);
d9fe64e5
RF		 543 }
544
83e1b918 545 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 546 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
d9fe64e5 547 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
83e1b918 548 if (ret < 0) {
49ae25b0 549 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
51bf2976 550 goto out;
2e55cc72 551 }
2e55cc72 552
8ef66bdc
JK		 553 /* Rewrite MAC address */
554 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
555 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
d9fe64e5
RF		 556 data->mac_addr, in_pm);
557 if (ret < 0)
558 goto out;
559
560 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
561 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
8ef66bdc
JK		 562 if (ret < 0)
563 goto out;
564
d9fe64e5
RF		 565 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
566 if (ret < 0)
567 return ret;
568
2e55cc72 569 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
d9fe64e5 570 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
83e1b918 571 if (ret < 0)
51bf2976 572 goto out;
2e55cc72 573
d9fe64e5 574 rx_ctl = asix_read_rx_ctl(dev, in_pm);
49ae25b0
GKH		 575 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
576 rx_ctl);
933a27d3 577
d9fe64e5 578 rx_ctl = asix_read_medium_status(dev, in_pm);
49ae25b0
GKH		 579 netdev_dbg(dev->net,
580 "Medium Status is 0x%04x after all initializations\n",
581 rx_ctl);
933a27d3 582
4ad1438f
GG		 583 return 0;
584
585out:
586 return ret;
4ad1438f
GG		 587}
588
589static const struct net_device_ops ax88772_netdev_ops = {
590 .ndo_open = usbnet_open,
591 .ndo_stop = usbnet_stop,
592 .ndo_start_xmit = usbnet_start_xmit,
593 .ndo_tx_timeout = usbnet_tx_timeout,
594 .ndo_change_mtu = usbnet_change_mtu,
c8b5d129 595 .ndo_get_stats64 = usbnet_get_stats64,
4ad1438f
GG		 596 .ndo_set_mac_address = asix_set_mac_address,
597 .ndo_validate_addr = eth_validate_addr,
598 .ndo_do_ioctl = asix_ioctl,
599 .ndo_set_rx_mode = asix_set_multicast,
600};
601
d9fe64e5
RF		 602static void ax88772_suspend(struct usbnet *dev)
603{
604 struct asix_common_private *priv = dev->driver_priv;
4c1442aa
RF		 605 u16 medium;
606
607 /* Stop MAC operation */
fadf3a28 608 medium = asix_read_medium_status(dev, 1);
4c1442aa 609 medium &= ~AX_MEDIUM_RE;
fadf3a28 610 asix_write_medium_mode(dev, medium, 1);
4c1442aa
RF		 611
612 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
fadf3a28 613 asix_read_medium_status(dev, 1));
d9fe64e5
RF		 614
615 /* Preserve BMCR for restoring */
616 priv->presvd_phy_bmcr =
617 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);
618
619 /* Preserve ANAR for restoring */
620 priv->presvd_phy_advertise =
621 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);
622}
623
624static int asix_suspend(struct usb_interface *intf, pm_message_t message)
625{
626 struct usbnet *dev = usb_get_intfdata(intf);
627 struct asix_common_private *priv = dev->driver_priv;
628
629 if (priv->suspend)
630 priv->suspend(dev);
631
632 return usbnet_suspend(intf, message);
633}
634
635static void ax88772_restore_phy(struct usbnet *dev)
636{
637 struct asix_common_private *priv = dev->driver_priv;
638
639 if (priv->presvd_phy_advertise) {
640 /* Restore Advertisement control reg */
641 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,
642 priv->presvd_phy_advertise);
643
644 /* Restore BMCR */
645 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,
646 priv->presvd_phy_bmcr);
647
4c1442aa 648 mii_nway_restart(&dev->mii);
d9fe64e5
RF		 649 priv->presvd_phy_advertise = 0;
650 priv->presvd_phy_bmcr = 0;
651 }
652}
653
654static void ax88772_resume(struct usbnet *dev)
655{
656 int i;
657
658 for (i = 0; i < 3; i++)
659 if (!ax88772_hw_reset(dev, 1))
660 break;
661 ax88772_restore_phy(dev);
662}
663
664static void ax88772a_resume(struct usbnet *dev)
665{
666 int i;
667
668 for (i = 0; i < 3; i++) {
669 if (!ax88772a_hw_reset(dev, 1))
670 break;
671 }
672
673 ax88772_restore_phy(dev);
674}
675
676static int asix_resume(struct usb_interface *intf)
677{
678 struct usbnet *dev = usb_get_intfdata(intf);
679 struct asix_common_private *priv = dev->driver_priv;
680
681 if (priv->resume)
682 priv->resume(dev);
683
684 return usbnet_resume(intf);
685}
686
4ad1438f
GG		 687static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
688{
d9fe64e5
RF		 689 int ret, i;
690 u8 buf[ETH_ALEN], chipcode = 0;
4ad1438f 691 u32 phyid;
d9fe64e5 692 struct asix_common_private *priv;
4ad1438f 693
4ad1438f
GG		 694 usbnet_get_endpoints(dev,intf);
695
696 /* Get the MAC address */
5620df65
LS		 697 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
698 for (i = 0; i < (ETH_ALEN >> 1); i++) {
699 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x04 + i,
d9fe64e5 700 0, 2, buf + i * 2, 0);
5620df65
LS		 701 if (ret < 0)
702 break;
703 }
704 } else {
705 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
d9fe64e5 706 0, 0, ETH_ALEN, buf, 0);
5620df65
LS		 707 }
708
83e1b918 709 if (ret < 0) {
49ae25b0 710 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 711 return ret;
4ad1438f 712 }
452b5ecd
JCPV		 713
714 asix_set_netdev_dev_addr(dev, buf);
4ad1438f
GG		 715
716 /* Initialize MII structure */
717 dev->mii.dev = dev->net;
718 dev->mii.mdio_read = asix_mdio_read;
719 dev->mii.mdio_write = asix_mdio_write;
720 dev->mii.phy_id_mask = 0x1f;
721 dev->mii.reg_num_mask = 0x1f;
722 dev->mii.phy_id = asix_get_phy_addr(dev);
723
4ad1438f
GG		 724 dev->net->netdev_ops = &ax88772_netdev_ops;
725 dev->net->ethtool_ops = &ax88772_ethtool_ops;
95162d65
ED		 726 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
727 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
4ad1438f 728
d9fe64e5
RF		 729 asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0);
730 chipcode &= AX_CHIPCODE_MASK;
d3665188 731
d9fe64e5
RF		 732 (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) :
733 ax88772a_hw_reset(dev, 0);
d3665188
GG		 734
735 /* Read PHYID register *AFTER* the PHY was reset properly */
736 phyid = asix_get_phyid(dev);
49ae25b0 737 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
d3665188 738
2e55cc72
DB		 739 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
740 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
741 /* hard_mtu is still the default - the device does not support
742 jumbo eth frames */
743 dev->rx_urb_size = 2048;
744 }
83e1b918 745
8b5b6f54
LS		 746 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
747 if (!dev->driver_priv)
748 return -ENOMEM;
749
d9fe64e5
RF		 750 priv = dev->driver_priv;
751
752 priv->presvd_phy_bmcr = 0;
753 priv->presvd_phy_advertise = 0;
754 if (chipcode == AX_AX88772_CHIPCODE) {
755 priv->resume = ax88772_resume;
756 priv->suspend = ax88772_suspend;
757 } else {
758 priv->resume = ax88772a_resume;
759 priv->suspend = ax88772_suspend;
760 }
761
2e55cc72 762 return 0;
2e55cc72
DB		 763}
764
ad327910 765static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
8b5b6f54 766{
d0c8f338 767 asix_rx_fixup_common_free(dev->driver_priv);
91ecee68 768 kfree(dev->driver_priv);
8b5b6f54
LS		 769}
770
bc689c97 771static const struct ethtool_ops ax88178_ethtool_ops = {
933a27d3
DH		 772 .get_drvinfo = asix_get_drvinfo,
773 .get_link = asix_get_link,
933a27d3
DH		 774 .get_msglevel = usbnet_get_msglevel,
775 .set_msglevel = usbnet_set_msglevel,
776 .get_wol = asix_get_wol,
777 .set_wol = asix_set_wol,
778 .get_eeprom_len = asix_get_eeprom_len,
779 .get_eeprom = asix_get_eeprom,
cb7b24cd 780 .set_eeprom = asix_set_eeprom,
c41286fd 781 .nway_reset = usbnet_nway_reset,
fd4f0a75
PR		 782 .get_link_ksettings = usbnet_get_link_ksettings,
783 .set_link_ksettings = usbnet_set_link_ksettings,
933a27d3
DH		 784};
785
786static int marvell_phy_init(struct usbnet *dev)
2e55cc72 787{
933a27d3
DH		 788 struct asix_data *data = (struct asix_data *)&dev->data;
789 u16 reg;
2e55cc72 790
60b86755 791 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 792
933a27d3 793 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 794 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 795
933a27d3
DH		 796 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
797 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 798
933a27d3
DH		 799 if (data->ledmode) {
800 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
801 MII_MARVELL_LED_CTRL);
60b86755 802 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 803
933a27d3
DH		 804 reg &= 0xf8ff;
805 reg |= (1 + 0x0100);
806 asix_mdio_write(dev->net, dev->mii.phy_id,
807 MII_MARVELL_LED_CTRL, reg);
2e55cc72 808
933a27d3
DH		 809 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
810 MII_MARVELL_LED_CTRL);
60b86755 811 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH		 812 reg &= 0xfc0f;
813 }
2e55cc72 814
933a27d3
DH		 815 return 0;
816}
817
610d885d
GG		 818static int rtl8211cl_phy_init(struct usbnet *dev)
819{
820 struct asix_data *data = (struct asix_data *)&dev->data;
821
822 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
823
824 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
825 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
826 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
827 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
828 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
829
830 if (data->ledmode == 12) {
831 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
832 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
833 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
834 }
835
836 return 0;
837}
838
933a27d3
DH		 839static int marvell_led_status(struct usbnet *dev, u16 speed)
840{
841 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
842
60b86755 843 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH		 844
845 /* Clear out the center LED bits - 0x03F0 */
846 reg &= 0xfc0f;
847
848 switch (speed) {
849 case SPEED_1000:
850 reg |= 0x03e0;
851 break;
852 case SPEED_100:
853 reg |= 0x03b0;
854 break;
855 default:
856 reg |= 0x02f0;
2e55cc72
DB		 857 }
858
60b86755 859 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH		 860 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
861
862 return 0;
863}
864
610d885d
GG		 865static int ax88178_reset(struct usbnet *dev)
866{
867 struct asix_data *data = (struct asix_data *)&dev->data;
868 int ret;
869 __le16 eeprom;
870 u8 status;
871 int gpio0 = 0;
b2d3ad29 872 u32 phyid;
610d885d 873
d9fe64e5 874 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
49ae25b0 875 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
610d885d 876
d9fe64e5
RF		 877 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
878 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
879 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
610d885d 880
49ae25b0 881 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
610d885d
GG		 882
883 if (eeprom == cpu_to_le16(0xffff)) {
884 data->phymode = PHY_MODE_MARVELL;
885 data->ledmode = 0;
886 gpio0 = 1;
887 } else {
b2d3ad29 888 data->phymode = le16_to_cpu(eeprom) & 0x7F;
610d885d
GG		 889 data->ledmode = le16_to_cpu(eeprom) >> 8;
890 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
891 }
49ae25b0 892 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
610d885d 893
b2d3ad29 894 /* Power up external GigaPHY through AX88178 GPIO pin */
d9fe64e5
RF		 895 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
896 AX_GPIO_GPO1EN, 40, 0);
610d885d 897 if ((le16_to_cpu(eeprom) >> 8) != 1) {
d9fe64e5
RF		 898 asix_write_gpio(dev, 0x003c, 30, 0);
899 asix_write_gpio(dev, 0x001c, 300, 0);
900 asix_write_gpio(dev, 0x003c, 30, 0);
610d885d 901 } else {
49ae25b0 902 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
d9fe64e5
RF		 903 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
904 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
610d885d
GG		 905 }
906
b2d3ad29
GG		 907 /* Read PHYID register *AFTER* powering up PHY */
908 phyid = asix_get_phyid(dev);
49ae25b0 909 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
b2d3ad29
GG		 910
911 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
d9fe64e5 912 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
b2d3ad29 913
d9fe64e5 914 asix_sw_reset(dev, 0, 0);
610d885d
GG		 915 msleep(150);
916
d9fe64e5 917 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
610d885d
GG		 918 msleep(150);
919
d9fe64e5 920 asix_write_rx_ctl(dev, 0, 0);
610d885d
GG		 921
922 if (data->phymode == PHY_MODE_MARVELL) {
923 marvell_phy_init(dev);
924 msleep(60);
925 } else if (data->phymode == PHY_MODE_RTL8211CL)
926 rtl8211cl_phy_init(dev);
927
a243c2ef 928 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
610d885d
GG		 929 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
930 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
931 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
932 ADVERTISE_1000FULL);
933
535baf85 934 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
610d885d
GG		 935 mii_nway_restart(&dev->mii);
936
71bc5d94
JK		 937 /* Rewrite MAC address */
938 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
939 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
d9fe64e5 940 data->mac_addr, 0);
71bc5d94
JK		 941 if (ret < 0)
942 return ret;
943
d9fe64e5 944 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
83e1b918
GG		 945 if (ret < 0)
946 return ret;
610d885d
GG		 947
948 return 0;
610d885d
GG		 949}
950
933a27d3
DH		 951static int ax88178_link_reset(struct usbnet *dev)
952{
953 u16 mode;
8ae6daca 954 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3 955 struct asix_data *data = (struct asix_data *)&dev->data;
8ae6daca 956 u32 speed;
933a27d3 957
60b86755 958 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH		 959
960 mii_check_media(&dev->mii, 1, 1);
961 mii_ethtool_gset(&dev->mii, &ecmd);
962 mode = AX88178_MEDIUM_DEFAULT;
8ae6daca 963 speed = ethtool_cmd_speed(&ecmd);
933a27d3 964
8ae6daca 965 if (speed == SPEED_1000)
a7f75c0c 966 mode |= AX_MEDIUM_GM;
8ae6daca 967 else if (speed == SPEED_100)
933a27d3
DH		 968 mode |= AX_MEDIUM_PS;
969 else
970 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
971
a7f75c0c
PK		 972 mode |= AX_MEDIUM_ENCK;
973
933a27d3
DH		 974 if (ecmd.duplex == DUPLEX_FULL)
975 mode |= AX_MEDIUM_FD;
976 else
977 mode &= ~AX_MEDIUM_FD;
978
8ae6daca
DD		 979 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
980 speed, ecmd.duplex, mode);
933a27d3 981
d9fe64e5 982 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 983
984 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
8ae6daca 985 marvell_led_status(dev, speed);
933a27d3
DH		 986
987 return 0;
988}
989
990static void ax88178_set_mfb(struct usbnet *dev)
991{
992 u16 mfb = AX_RX_CTL_MFB_16384;
993 u16 rxctl;
994 u16 medium;
995 int old_rx_urb_size = dev->rx_urb_size;
996
997 if (dev->hard_mtu < 2048) {
998 dev->rx_urb_size = 2048;
999 mfb = AX_RX_CTL_MFB_2048;
1000 } else if (dev->hard_mtu < 4096) {
1001 dev->rx_urb_size = 4096;
1002 mfb = AX_RX_CTL_MFB_4096;
1003 } else if (dev->hard_mtu < 8192) {
1004 dev->rx_urb_size = 8192;
1005 mfb = AX_RX_CTL_MFB_8192;
1006 } else if (dev->hard_mtu < 16384) {
1007 dev->rx_urb_size = 16384;
1008 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 1009 }
933a27d3 1010
d9fe64e5
RF		 1011 rxctl = asix_read_rx_ctl(dev, 0);
1012 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
933a27d3 1013
d9fe64e5 1014 medium = asix_read_medium_status(dev, 0);
933a27d3
DH		 1015 if (dev->net->mtu > 1500)
1016 medium |= AX_MEDIUM_JFE;
1017 else
1018 medium &= ~AX_MEDIUM_JFE;
d9fe64e5 1019 asix_write_medium_mode(dev, medium, 0);
933a27d3
DH		 1020
1021 if (dev->rx_urb_size > old_rx_urb_size)
1022 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 1023}
1024
933a27d3 1025static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 1026{
933a27d3
DH		 1027 struct usbnet *dev = netdev_priv(net);
1028 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 1029
60b86755 1030 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 1031
933a27d3
DH		 1032 if ((ll_mtu % dev->maxpacket) == 0)
1033 return -EDOM;
1034
1035 net->mtu = new_mtu;
1036 dev->hard_mtu = net->mtu + net->hard_header_len;
1037 ax88178_set_mfb(dev);
1038
a88c32ae
ML		 1039 /* max qlen depend on hard_mtu and rx_urb_size */
1040 usbnet_update_max_qlen(dev);
1041
933a27d3
DH		 1042 return 0;
1043}
1044
1703338c
SH		 1045static const struct net_device_ops ax88178_netdev_ops = {
1046 .ndo_open = usbnet_open,
1047 .ndo_stop = usbnet_stop,
1048 .ndo_start_xmit = usbnet_start_xmit,
1049 .ndo_tx_timeout = usbnet_tx_timeout,
c8b5d129 1050 .ndo_get_stats64 = usbnet_get_stats64,
7f29a3ba 1051 .ndo_set_mac_address = asix_set_mac_address,
1703338c 1052 .ndo_validate_addr = eth_validate_addr,
afc4b13d 1053 .ndo_set_rx_mode = asix_set_multicast,
1703338c
SH		 1054 .ndo_do_ioctl = asix_ioctl,
1055 .ndo_change_mtu = ax88178_change_mtu,
1056};
1057
933a27d3
DH		 1058static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1059{
933a27d3 1060 int ret;
51bf2976 1061 u8 buf[ETH_ALEN];
933a27d3
DH		 1062
1063 usbnet_get_endpoints(dev,intf);
1064
933a27d3 1065 /* Get the MAC address */
d9fe64e5 1066 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
83e1b918 1067 if (ret < 0) {
49ae25b0 1068 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 1069 return ret;
2e55cc72 1070 }
452b5ecd
JCPV		 1071
1072 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 1073
933a27d3
DH		 1074 /* Initialize MII structure */
1075 dev->mii.dev = dev->net;
1076 dev->mii.mdio_read = asix_mdio_read;
1077 dev->mii.mdio_write = asix_mdio_write;
1078 dev->mii.phy_id_mask = 0x1f;
1079 dev->mii.reg_num_mask = 0xff;
1080 dev->mii.supports_gmii = 1;
933a27d3 1081 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH		 1082
1083 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 1084 dev->net->ethtool_ops = &ax88178_ethtool_ops;
f77f0aee 1085 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4);
2e55cc72 1086
b2d3ad29 1087 /* Blink LEDS so users know driver saw dongle */
d9fe64e5 1088 asix_sw_reset(dev, 0, 0);
b2d3ad29 1089 msleep(150);
2e55cc72 1090
d9fe64e5 1091 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
b2d3ad29 1092 msleep(150);
933a27d3
DH		 1093
1094 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1095 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1096 /* hard_mtu is still the default - the device does not support
1097 jumbo eth frames */
1098 dev->rx_urb_size = 2048;
1099 }
933a27d3 1100
8b5b6f54
LS		 1101 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1102 if (!dev->driver_priv)
1103 return -ENOMEM;
1104
83e1b918 1105 return 0;
2e55cc72
DB		 1106}
1107
1108static const struct driver_info ax8817x_info = {
1109 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 1110 .bind = ax88172_bind,
1111 .status = asix_status,
2e55cc72
DB		 1112 .link_reset = ax88172_link_reset,
1113 .reset = ax88172_link_reset,
37e8273c 1114 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1115 .data = 0x00130103,
1116};
1117
1118static const struct driver_info dlink_dub_e100_info = {
1119 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 1120 .bind = ax88172_bind,
1121 .status = asix_status,
2e55cc72
DB		 1122 .link_reset = ax88172_link_reset,
1123 .reset = ax88172_link_reset,
37e8273c 1124 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1125 .data = 0x009f9d9f,
1126};
1127
1128static const struct driver_info netgear_fa120_info = {
1129 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 1130 .bind = ax88172_bind,
1131 .status = asix_status,
2e55cc72
DB		 1132 .link_reset = ax88172_link_reset,
1133 .reset = ax88172_link_reset,
37e8273c 1134 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1135 .data = 0x00130103,
1136};
1137
1138static const struct driver_info hawking_uf200_info = {
1139 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 1140 .bind = ax88172_bind,
1141 .status = asix_status,
2e55cc72
DB		 1142 .link_reset = ax88172_link_reset,
1143 .reset = ax88172_link_reset,
37e8273c 1144 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1145 .data = 0x001f1d1f,
1146};
1147
1148static const struct driver_info ax88772_info = {
1149 .description = "ASIX AX88772 USB 2.0 Ethernet",
1150 .bind = ax88772_bind,
8b5b6f54 1151 .unbind = ax88772_unbind,
48b1be6a 1152 .status = asix_status,
2e55cc72 1153 .link_reset = ax88772_link_reset,
d9fe64e5 1154 .reset = ax88772_reset,
a9e0aca4 1155 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
8b5b6f54 1156 .rx_fixup = asix_rx_fixup_common,
933a27d3
DH		 1157 .tx_fixup = asix_tx_fixup,
1158};
1159
5620df65
LS		 1160static const struct driver_info ax88772b_info = {
1161 .description = "ASIX AX88772B USB 2.0 Ethernet",
1162 .bind = ax88772_bind,
8b5b6f54 1163 .unbind = ax88772_unbind,
5620df65
LS		 1164 .status = asix_status,
1165 .link_reset = ax88772_link_reset,
1166 .reset = ax88772_reset,
1167 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1168 FLAG_MULTI_PACKET,
8b5b6f54 1169 .rx_fixup = asix_rx_fixup_common,
5620df65
LS		 1170 .tx_fixup = asix_tx_fixup,
1171 .data = FLAG_EEPROM_MAC,
1172};
1173
933a27d3
DH		 1174static const struct driver_info ax88178_info = {
1175 .description = "ASIX AX88178 USB 2.0 Ethernet",
1176 .bind = ax88178_bind,
8b5b6f54 1177 .unbind = ax88772_unbind,
933a27d3
DH		 1178 .status = asix_status,
1179 .link_reset = ax88178_link_reset,
610d885d 1180 .reset = ax88178_reset,
d43ff4cd
EG		 1181 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1182 FLAG_MULTI_PACKET,
8b5b6f54 1183 .rx_fixup = asix_rx_fixup_common,
933a27d3 1184 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 1185};
1186
45af3fb4
GT		 1187/*
1188 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1189 * no-name packaging.
1190 * USB device strings are:
1191 * 1: Manufacturer: USBLINK
1192 * 2: Product: HG20F9 USB2.0
1193 * 3: Serial: 000003
1194 * Appears to be compatible with Asix 88772B.
1195 */
1196static const struct driver_info hg20f9_info = {
1197 .description = "HG20F9 USB 2.0 Ethernet",
1198 .bind = ax88772_bind,
1199 .unbind = ax88772_unbind,
1200 .status = asix_status,
1201 .link_reset = ax88772_link_reset,
1202 .reset = ax88772_reset,
1203 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1204 FLAG_MULTI_PACKET,
1205 .rx_fixup = asix_rx_fixup_common,
1206 .tx_fixup = asix_tx_fixup,
1207 .data = FLAG_EEPROM_MAC,
1208};
1209
2e55cc72
DB		 1210static const struct usb_device_id products [] = {
1211{
1212 // Linksys USB200M
1213 USB_DEVICE (0x077b, 0x2226),
1214 .driver_info = (unsigned long) &ax8817x_info,
1215}, {
1216 // Netgear FA120
1217 USB_DEVICE (0x0846, 0x1040),
1218 .driver_info = (unsigned long) &netgear_fa120_info,
1219}, {
1220 // DLink DUB-E100
1221 USB_DEVICE (0x2001, 0x1a00),
1222 .driver_info = (unsigned long) &dlink_dub_e100_info,
1223}, {
1224 // Intellinet, ST Lab USB Ethernet
1225 USB_DEVICE (0x0b95, 0x1720),
1226 .driver_info = (unsigned long) &ax8817x_info,
1227}, {
1228 // Hawking UF200, TrendNet TU2-ET100
1229 USB_DEVICE (0x07b8, 0x420a),
1230 .driver_info = (unsigned long) &hawking_uf200_info,
1231}, {
39c4b38c
DH		 1232 // Billionton Systems, USB2AR
1233 USB_DEVICE (0x08dd, 0x90ff),
1234 .driver_info = (unsigned long) &ax8817x_info,
80083a3c
CSC		 1235}, {
1236 // Billionton Systems, GUSB2AM-1G-B
1237 USB_DEVICE(0x08dd, 0x0114),
1238 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1239}, {
1240 // ATEN UC210T
1241 USB_DEVICE (0x0557, 0x2009),
1242 .driver_info = (unsigned long) &ax8817x_info,
1243}, {
1244 // Buffalo LUA-U2-KTX
1245 USB_DEVICE (0x0411, 0x003d),
1246 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD		 1247}, {
1248 // Buffalo LUA-U2-GT 10/100/1000
1249 USB_DEVICE (0x0411, 0x006e),
1250 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1251}, {
1252 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1253 USB_DEVICE (0x6189, 0x182d),
1254 .driver_info = (unsigned long) &ax8817x_info,
4e503919
JN		 1255}, {
1256 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1257 USB_DEVICE (0x0df6, 0x0056),
1258 .driver_info = (unsigned long) &ax88178_info,
7488c3e3
LC		 1259}, {
1260 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1261 USB_DEVICE (0x0df6, 0x061c),
1262 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1263}, {
1264 // corega FEther USB2-TX
1265 USB_DEVICE (0x07aa, 0x0017),
1266 .driver_info = (unsigned long) &ax8817x_info,
1267}, {
1268 // Surecom EP-1427X-2
1269 USB_DEVICE (0x1189, 0x0893),
1270 .driver_info = (unsigned long) &ax8817x_info,
1271}, {
1272 // goodway corp usb gwusb2e
1273 USB_DEVICE (0x1631, 0x6200),
1274 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH		 1275}, {
1276 // JVC MP-PRX1 Port Replicator
1277 USB_DEVICE (0x04f1, 0x3008),
1278 .driver_info = (unsigned long) &ax8817x_info,
66dc81ec
QP		 1279}, {
1280 // Lenovo U2L100P 10/100
1281 USB_DEVICE (0x17ef, 0x7203),
d9fe64e5 1282 .driver_info = (unsigned long)&ax88772b_info,
30885909
MV		 1283}, {
1284 // ASIX AX88772B 10/100
1285 USB_DEVICE (0x0b95, 0x772b),
5620df65 1286 .driver_info = (unsigned long) &ax88772b_info,
2e55cc72
DB		 1287}, {
1288 // ASIX AX88772 10/100
39c4b38c
DH		 1289 USB_DEVICE (0x0b95, 0x7720),
1290 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 1291}, {
1292 // ASIX AX88178 10/100/1000
1293 USB_DEVICE (0x0b95, 0x1780),
933a27d3 1294 .driver_info = (unsigned long) &ax88178_info,
f4680d3d
AE		 1295}, {
1296 // Logitec LAN-GTJ/U2A
1297 USB_DEVICE (0x0789, 0x0160),
1298 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 1299}, {
1300 // Linksys USB200M Rev 2
1301 USB_DEVICE (0x13b1, 0x0018),
1302 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 1303}, {
1304 // 0Q0 cable ethernet
1305 USB_DEVICE (0x1557, 0x7720),
1306 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1307}, {
1308 // DLink DUB-E100 H/W Ver B1
1309 USB_DEVICE (0x07d1, 0x3c05),
1310 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 1311}, {
1312 // DLink DUB-E100 H/W Ver B1 Alternate
1313 USB_DEVICE (0x2001, 0x3c05),
1314 .driver_info = (unsigned long) &ax88772_info,
ed3770a9
S		 1315}, {
1316 // DLink DUB-E100 H/W Ver C1
1317 USB_DEVICE (0x2001, 0x1a02),
1318 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1319}, {
1320 // Linksys USB1000
1321 USB_DEVICE (0x1737, 0x0039),
1322 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH		 1323}, {
1324 // IO-DATA ETG-US2
1325 USB_DEVICE (0x04bb, 0x0930),
1326 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH		 1327}, {
1328 // Belkin F5D5055
1329 USB_DEVICE(0x050d, 0x5055),
1330 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN		 1331}, {
1332 // Apple USB Ethernet Adapter
1333 USB_DEVICE(0x05ac, 0x1402),
1334 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC		 1335}, {
1336 // Cables-to-Go USB Ethernet Adapter
1337 USB_DEVICE(0x0b95, 0x772a),
1338 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH		 1339}, {
1340 // ABOCOM for pci
1341 USB_DEVICE(0x14ea, 0xab11),
1342 .driver_info = (unsigned long) &ax88178_info,
1343}, {
1344 // ASIX 88772a
1345 USB_DEVICE(0x0db0, 0xa877),
1346 .driver_info = (unsigned long) &ax88772_info,
e8303a3b
AJ		 1347}, {
1348 // Asus USB Ethernet Adapter
1349 USB_DEVICE (0x0b95, 0x7e2b),
d9fe64e5 1350 .driver_info = (unsigned long)&ax88772b_info,
16626b0c
CR		 1351}, {
1352 /* ASIX 88172a demo board */
1353 USB_DEVICE(0x0b95, 0x172a),
1354 .driver_info = (unsigned long) &ax88172a_info,
45af3fb4
GT		 1355}, {
1356 /*
1357 * USBLINK HG20F9 "USB 2.0 LAN"
1358 * Appears to have gazumped Linksys's manufacturer ID but
1359 * doesn't (yet) conflict with any known Linksys product.
1360 */
1361 USB_DEVICE(0x066b, 0x20f9),
1362 .driver_info = (unsigned long) &hg20f9_info,
2e55cc72
DB		 1363},
1364 { }, // END
1365};
1366MODULE_DEVICE_TABLE(usb, products);
1367
1368static struct usb_driver asix_driver = {
83e1b918 1369 .name = DRIVER_NAME,
2e55cc72
DB		 1370 .id_table = products,
1371 .probe = usbnet_probe,
d9fe64e5
RF		 1372 .suspend = asix_suspend,
1373 .resume = asix_resume,
63dfb0da 1374 .reset_resume = asix_resume,
2e55cc72 1375 .disconnect = usbnet_disconnect,
a11a6544 1376 .supports_autosuspend = 1,
e1f12eb6 1377 .disable_hub_initiated_lpm = 1,
2e55cc72
DB		 1378};
1379
d632eb1b 1380module_usb_driver(asix_driver);
2e55cc72
DB		 1381
1382MODULE_AUTHOR("David Hollis");
4ad1438f 1383MODULE_VERSION(DRIVER_VERSION);
2e55cc72
DB		 1384MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1385MODULE_LICENSE("GPL");
1386
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