]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - drivers/net/usb/asix_devices.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'sh-pfc-for-v5.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-focal-kernel.git] / drivers / net / usb / asix_devices.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
9cb00073 19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
2e55cc72
DB		 20 */
21
607740bc 22#include "asix.h"
933a27d3
DH		 23
24#define PHY_MODE_MARVELL 0x0000
25#define MII_MARVELL_LED_CTRL 0x0018
26#define MII_MARVELL_STATUS 0x001b
27#define MII_MARVELL_CTRL 0x0014
28
29#define MARVELL_LED_MANUAL 0x0019
30
31#define MARVELL_STATUS_HWCFG 0x0004
32
33#define MARVELL_CTRL_TXDELAY 0x0002
34#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72 35
3486140e 36#define PHY_MODE_RTL8211CL 0x000C
610d885d 37
4c1442aa
RF		 38#define AX88772A_PHY14H 0x14
39#define AX88772A_PHY14H_DEFAULT 0x442C
40
41#define AX88772A_PHY15H 0x15
42#define AX88772A_PHY15H_DEFAULT 0x03C8
43
44#define AX88772A_PHY16H 0x16
45#define AX88772A_PHY16H_DEFAULT 0x4044
46
2e55cc72 47struct ax88172_int_data {
51bf2976 48 __le16 res1;
2e55cc72 49 u8 link;
51bf2976 50 __le16 res2;
2e55cc72 51 u8 status;
51bf2976 52 __le16 res3;
ba2d3587 53} __packed;
2e55cc72 54
933a27d3
DH		 55static void asix_status(struct usbnet *dev, struct urb *urb)
56{
57 struct ax88172_int_data *event;
58 int link;
59
60 if (urb->actual_length < 8)
61 return;
62
63 event = urb->transfer_buffer;
64 link = event->link & 0x01;
65 if (netif_carrier_ok(dev->net) != link) {
eae65919 66 usbnet_link_change(dev, link, 1);
60b86755 67 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH		 68 }
69}
70
452b5ecd
JCPV		 71static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
72{
73 if (is_valid_ether_addr(addr)) {
74 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
75 } else {
76 netdev_info(dev->net, "invalid hw address, using random\n");
77 eth_hw_addr_random(dev->net);
78 }
79}
80
933a27d3
DH		 81/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
82static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 83{
933a27d3
DH		 84 int phy_reg;
85 u32 phy_id;
a77929a2 86 int i;
2e55cc72 87
a77929a2
GG		 88 /* Poll for the rare case the FW or phy isn't ready yet. */
89 for (i = 0; i < 100; i++) {
90 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
8a46f665
RF		 91 if (phy_reg < 0)
92 return 0;
a77929a2
GG		 93 if (phy_reg != 0 && phy_reg != 0xFFFF)
94 break;
95 mdelay(1);
96 }
97
98 if (phy_reg <= 0 || phy_reg == 0xFFFF)
933a27d3 99 return 0;
2e55cc72 100
933a27d3 101 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 102
933a27d3
DH		 103 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
104 if (phy_reg < 0)
105 return 0;
106
107 phy_id |= (phy_reg & 0xffff);
108
109 return phy_id;
2e55cc72
DB		 110}
111
933a27d3
DH		 112static u32 asix_get_link(struct net_device *net)
113{
114 struct usbnet *dev = netdev_priv(net);
115
116 return mii_link_ok(&dev->mii);
117}
118
119static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
120{
121 struct usbnet *dev = netdev_priv(net);
122
123 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
124}
125
126/* We need to override some ethtool_ops so we require our
127 own structure so we don't interfere with other usbnet
128 devices that may be connected at the same time. */
0fc0b732 129static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH		 130 .get_drvinfo = asix_get_drvinfo,
131 .get_link = asix_get_link,
933a27d3 132 .get_msglevel = usbnet_get_msglevel,
2e55cc72 133 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 134 .get_wol = asix_get_wol,
135 .set_wol = asix_set_wol,
136 .get_eeprom_len = asix_get_eeprom_len,
137 .get_eeprom = asix_get_eeprom,
cb7b24cd 138 .set_eeprom = asix_set_eeprom,
c41286fd 139 .nway_reset = usbnet_nway_reset,
fd4f0a75
PR		 140 .get_link_ksettings = usbnet_get_link_ksettings,
141 .set_link_ksettings = usbnet_set_link_ksettings,
2e55cc72
DB		 142};
143
933a27d3 144static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 145{
146 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 147 struct asix_data *data = (struct asix_data *)&dev->data;
148 u8 rx_ctl = 0x8c;
2e55cc72 149
933a27d3
DH		 150 if (net->flags & IFF_PROMISC) {
151 rx_ctl |= 0x01;
8e95a202 152 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 153 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 154 rx_ctl |= 0x02;
4cd24eaf 155 } else if (netdev_mc_empty(net)) {
933a27d3
DH		 156 /* just broadcast and directed */
157 } else {
158 /* We use the 20 byte dev->data
159 * for our 8 byte filter buffer
160 * to avoid allocating memory that
161 * is tricky to free later */
22bedad3 162 struct netdev_hw_addr *ha;
933a27d3 163 u32 crc_bits;
933a27d3
DH		 164
165 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
166
167 /* Build the multicast hash filter. */
22bedad3
JP		 168 netdev_for_each_mc_addr(ha, net) {
169 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
933a27d3
DH		 170 data->multi_filter[crc_bits >> 3] |=
171 1 << (crc_bits & 7);
933a27d3
DH		 172 }
173
174 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
175 AX_MCAST_FILTER_SIZE, data->multi_filter);
176
177 rx_ctl |= 0x10;
178 }
179
180 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
181}
182
183static int ax88172_link_reset(struct usbnet *dev)
184{
185 u8 mode;
8ae6daca 186 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 187
188 mii_check_media(&dev->mii, 1, 1);
189 mii_ethtool_gset(&dev->mii, &ecmd);
190 mode = AX88172_MEDIUM_DEFAULT;
191
192 if (ecmd.duplex != DUPLEX_FULL)
193 mode |= ~AX88172_MEDIUM_FD;
194
8ae6daca
DD		 195 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
196 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3 197
d9fe64e5 198 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 199
200 return 0;
2e55cc72
DB		 201}
202
1703338c
SH		 203static const struct net_device_ops ax88172_netdev_ops = {
204 .ndo_open = usbnet_open,
205 .ndo_stop = usbnet_stop,
206 .ndo_start_xmit = usbnet_start_xmit,
207 .ndo_tx_timeout = usbnet_tx_timeout,
208 .ndo_change_mtu = usbnet_change_mtu,
c8b5d129 209 .ndo_get_stats64 = usbnet_get_stats64,
1703338c
SH		 210 .ndo_set_mac_address = eth_mac_addr,
211 .ndo_validate_addr = eth_validate_addr,
212 .ndo_do_ioctl = asix_ioctl,
afc4b13d 213 .ndo_set_rx_mode = ax88172_set_multicast,
1703338c
SH		 214};
215
a243c2ef
RF		 216static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
217{
218 unsigned int timeout = 5000;
219
220 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
221
222 /* give phy_id a chance to process reset */
223 udelay(500);
224
225 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
226 while (timeout--) {
227 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
228 & BMCR_RESET)
229 udelay(100);
230 else
231 return;
232 }
233
234 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
235 dev->mii.phy_id);
236}
237
48b1be6a 238static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 239{
240 int ret = 0;
51bf2976 241 u8 buf[ETH_ALEN];
2e55cc72
DB		 242 int i;
243 unsigned long gpio_bits = dev->driver_info->data;
244
245 usbnet_get_endpoints(dev,intf);
246
2e55cc72
DB		 247 /* Toggle the GPIOs in a manufacturer/model specific way */
248 for (i = 2; i >= 0; i--) {
83e1b918 249 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
d9fe64e5 250 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
83e1b918 251 if (ret < 0)
51bf2976 252 goto out;
2e55cc72
DB		 253 msleep(5);
254 }
255
d9fe64e5 256 ret = asix_write_rx_ctl(dev, 0x80, 0);
83e1b918 257 if (ret < 0)
51bf2976 258 goto out;
2e55cc72
DB		 259
260 /* Get the MAC address */
d9fe64e5
RF		 261 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
262 0, 0, ETH_ALEN, buf, 0);
83e1b918 263 if (ret < 0) {
49ae25b0
GKH		 264 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
265 ret);
51bf2976 266 goto out;
2e55cc72 267 }
452b5ecd
JCPV		 268
269 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 270
2e55cc72
DB		 271 /* Initialize MII structure */
272 dev->mii.dev = dev->net;
48b1be6a
DH		 273 dev->mii.mdio_read = asix_mdio_read;
274 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 275 dev->mii.phy_id_mask = 0x3f;
276 dev->mii.reg_num_mask = 0x1f;
933a27d3 277 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 278
1703338c 279 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 280 dev->net->ethtool_ops = &ax88172_ethtool_ops;
95162d65
ED		 281 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
282 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
2e55cc72 283
a243c2ef 284 asix_phy_reset(dev, BMCR_RESET);
933a27d3 285 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 286 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
287 mii_nway_restart(&dev->mii);
288
289 return 0;
51bf2976
AV		 290
291out:
2e55cc72
DB		 292 return ret;
293}
294
0fc0b732 295static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 296 .get_drvinfo = asix_get_drvinfo,
933a27d3 297 .get_link = asix_get_link,
2e55cc72
DB		 298 .get_msglevel = usbnet_get_msglevel,
299 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 300 .get_wol = asix_get_wol,
301 .set_wol = asix_set_wol,
302 .get_eeprom_len = asix_get_eeprom_len,
303 .get_eeprom = asix_get_eeprom,
cb7b24cd 304 .set_eeprom = asix_set_eeprom,
c41286fd 305 .nway_reset = usbnet_nway_reset,
fd4f0a75
PR		 306 .get_link_ksettings = usbnet_get_link_ksettings,
307 .set_link_ksettings = usbnet_set_link_ksettings,
2e55cc72
DB		 308};
309
933a27d3
DH		 310static int ax88772_link_reset(struct usbnet *dev)
311{
312 u16 mode;
8ae6daca 313 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 314
315 mii_check_media(&dev->mii, 1, 1);
316 mii_ethtool_gset(&dev->mii, &ecmd);
317 mode = AX88772_MEDIUM_DEFAULT;
318
8ae6daca 319 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
933a27d3
DH		 320 mode &= ~AX_MEDIUM_PS;
321
322 if (ecmd.duplex != DUPLEX_FULL)
323 mode &= ~AX_MEDIUM_FD;
324
8ae6daca
DD		 325 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
326 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3 327
d9fe64e5 328 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 329
330 return 0;
331}
332
4ad1438f 333static int ax88772_reset(struct usbnet *dev)
d9fe64e5
RF		 334{
335 struct asix_data *data = (struct asix_data *)&dev->data;
336 int ret;
337
338 /* Rewrite MAC address */
339 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
340 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
341 ETH_ALEN, data->mac_addr, 0);
342 if (ret < 0)
343 goto out;
344
345 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
346 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
347 if (ret < 0)
348 goto out;
349
4f3de46f 350 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
d9fe64e5
RF		 351 if (ret < 0)
352 goto out;
353
354 return 0;
355
356out:
357 return ret;
358}
359
360static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
2e55cc72 361{
8ef66bdc 362 struct asix_data *data = (struct asix_data *)&dev->data;
d0ffff8f 363 int ret, embd_phy;
933a27d3 364 u16 rx_ctl;
2e55cc72 365
d9fe64e5
RF		 366 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
367 AX_GPIO_GPO2EN, 5, in_pm);
83e1b918 368 if (ret < 0)
51bf2976 369 goto out;
2e55cc72 370
d9fe64e5 371 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
4ad1438f 372
d9fe64e5
RF		 373 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy,
374 0, 0, NULL, in_pm);
83e1b918 375 if (ret < 0) {
49ae25b0 376 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
51bf2976 377 goto out;
2e55cc72
DB		 378 }
379
d9fe64e5
RF		 380 if (embd_phy) {
381 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
382 if (ret < 0)
383 goto out;
2e55cc72 384
d9fe64e5 385 usleep_range(10000, 11000);
83e1b918 386
d9fe64e5
RF		 387 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
388 if (ret < 0)
389 goto out;
2e55cc72 390
d9fe64e5 391 msleep(60);
4ad1438f 392
d9fe64e5
RF		 393 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
394 in_pm);
83e1b918 395 if (ret < 0)
51bf2976 396 goto out;
83e1b918 397 } else {
d9fe64e5
RF		 398 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
399 in_pm);
83e1b918 400 if (ret < 0)
51bf2976 401 goto out;
d0ffff8f 402 }
2e55cc72
DB		 403
404 msleep(150);
d9fe64e5
RF		 405
406 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
407 MII_PHYSID1))){
408 ret = -EIO;
409 goto out;
410 }
411
412 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
413 if (ret < 0)
414 goto out;
415
416 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
83e1b918 417 if (ret < 0)
51bf2976 418 goto out;
2e55cc72 419
d9fe64e5
RF		 420 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
421 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
422 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
423 if (ret < 0) {
424 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
425 goto out;
426 }
933a27d3 427
d9fe64e5
RF		 428 /* Rewrite MAC address */
429 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
430 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
431 ETH_ALEN, data->mac_addr, in_pm);
83e1b918 432 if (ret < 0)
51bf2976 433 goto out;
2e55cc72 434
d9fe64e5
RF		 435 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
436 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
437 if (ret < 0)
438 goto out;
439
440 rx_ctl = asix_read_rx_ctl(dev, in_pm);
441 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
442 rx_ctl);
443
444 rx_ctl = asix_read_medium_status(dev, in_pm);
445 netdev_dbg(dev->net,
446 "Medium Status is 0x%04x after all initializations\n",
447 rx_ctl);
448
449 return 0;
450
451out:
452 return ret;
453}
454
455static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
456{
457 struct asix_data *data = (struct asix_data *)&dev->data;
458 int ret, embd_phy;
4c1442aa 459 u16 rx_ctl, phy14h, phy15h, phy16h;
d9fe64e5 460 u8 chipcode = 0;
48b1be6a 461
d9fe64e5 462 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
83e1b918 463 if (ret < 0)
51bf2976 464 goto out;
2e55cc72 465
d9fe64e5 466 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
2e55cc72 467
d9fe64e5
RF		 468 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy |
469 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
470 if (ret < 0) {
471 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
472 goto out;
473 }
474 usleep_range(10000, 11000);
2e55cc72 475
d9fe64e5 476 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
83e1b918 477 if (ret < 0)
51bf2976 478 goto out;
2e55cc72 479
d9fe64e5
RF		 480 usleep_range(10000, 11000);
481
482 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
483 if (ret < 0)
484 goto out;
485
486 msleep(160);
487
488 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
489 if (ret < 0)
490 goto out;
491
492 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
493 if (ret < 0)
494 goto out;
495
496 msleep(200);
497
498 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
499 MII_PHYSID1))) {
500 ret = -1;
501 goto out;
502 }
503
504 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0,
505 0, 1, &chipcode, in_pm);
506 if (ret < 0)
507 goto out;
508
509 if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) {
510 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
511 0, NULL, in_pm);
512 if (ret < 0) {
513 netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
514 ret);
515 goto out;
516 }
4c1442aa
RF		 517 } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) {
518 /* Check if the PHY registers have default settings */
519 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
520 AX88772A_PHY14H);
521 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
522 AX88772A_PHY15H);
523 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
524 AX88772A_PHY16H);
525
526 netdev_dbg(dev->net,
527 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
528 phy14h, phy15h, phy16h);
529
530 /* Restore PHY registers default setting if not */
531 if (phy14h != AX88772A_PHY14H_DEFAULT)
532 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
533 AX88772A_PHY14H,
534 AX88772A_PHY14H_DEFAULT);
535 if (phy15h != AX88772A_PHY15H_DEFAULT)
536 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
537 AX88772A_PHY15H,
538 AX88772A_PHY15H_DEFAULT);
539 if (phy16h != AX88772A_PHY16H_DEFAULT)
540 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
541 AX88772A_PHY16H,
542 AX88772A_PHY16H_DEFAULT);
d9fe64e5
RF		 543 }
544
83e1b918 545 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 546 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
d9fe64e5 547 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
83e1b918 548 if (ret < 0) {
49ae25b0 549 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
51bf2976 550 goto out;
2e55cc72 551 }
2e55cc72 552
8ef66bdc
JK		 553 /* Rewrite MAC address */
554 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
555 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
d9fe64e5
RF		 556 data->mac_addr, in_pm);
557 if (ret < 0)
558 goto out;
559
560 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
561 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
8ef66bdc
JK		 562 if (ret < 0)
563 goto out;
564
d9fe64e5
RF		 565 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
566 if (ret < 0)
567 return ret;
568
2e55cc72 569 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
d9fe64e5 570 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
83e1b918 571 if (ret < 0)
51bf2976 572 goto out;
2e55cc72 573
d9fe64e5 574 rx_ctl = asix_read_rx_ctl(dev, in_pm);
49ae25b0
GKH		 575 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
576 rx_ctl);
933a27d3 577
d9fe64e5 578 rx_ctl = asix_read_medium_status(dev, in_pm);
49ae25b0
GKH		 579 netdev_dbg(dev->net,
580 "Medium Status is 0x%04x after all initializations\n",
581 rx_ctl);
933a27d3 582
4ad1438f
GG		 583 return 0;
584
585out:
586 return ret;
4ad1438f
GG		 587}
588
589static const struct net_device_ops ax88772_netdev_ops = {
590 .ndo_open = usbnet_open,
591 .ndo_stop = usbnet_stop,
592 .ndo_start_xmit = usbnet_start_xmit,
593 .ndo_tx_timeout = usbnet_tx_timeout,
594 .ndo_change_mtu = usbnet_change_mtu,
c8b5d129 595 .ndo_get_stats64 = usbnet_get_stats64,
4ad1438f
GG		 596 .ndo_set_mac_address = asix_set_mac_address,
597 .ndo_validate_addr = eth_validate_addr,
598 .ndo_do_ioctl = asix_ioctl,
599 .ndo_set_rx_mode = asix_set_multicast,
600};
601
d9fe64e5
RF		 602static void ax88772_suspend(struct usbnet *dev)
603{
604 struct asix_common_private *priv = dev->driver_priv;
4c1442aa
RF		 605 u16 medium;
606
607 /* Stop MAC operation */
fadf3a28 608 medium = asix_read_medium_status(dev, 1);
4c1442aa 609 medium &= ~AX_MEDIUM_RE;
fadf3a28 610 asix_write_medium_mode(dev, medium, 1);
4c1442aa
RF		 611
612 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
fadf3a28 613 asix_read_medium_status(dev, 1));
d9fe64e5
RF		 614
615 /* Preserve BMCR for restoring */
616 priv->presvd_phy_bmcr =
617 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);
618
619 /* Preserve ANAR for restoring */
620 priv->presvd_phy_advertise =
621 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);
622}
623
624static int asix_suspend(struct usb_interface *intf, pm_message_t message)
625{
626 struct usbnet *dev = usb_get_intfdata(intf);
627 struct asix_common_private *priv = dev->driver_priv;
628
8f562462 629 if (priv && priv->suspend)
d9fe64e5
RF		 630 priv->suspend(dev);
631
632 return usbnet_suspend(intf, message);
633}
634
635static void ax88772_restore_phy(struct usbnet *dev)
636{
637 struct asix_common_private *priv = dev->driver_priv;
638
639 if (priv->presvd_phy_advertise) {
640 /* Restore Advertisement control reg */
641 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,
642 priv->presvd_phy_advertise);
643
644 /* Restore BMCR */
5c968f48
AC		 645 if (priv->presvd_phy_bmcr & BMCR_ANENABLE)
646 priv->presvd_phy_bmcr |= BMCR_ANRESTART;
647
d9fe64e5
RF		 648 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,
649 priv->presvd_phy_bmcr);
650
651 priv->presvd_phy_advertise = 0;
652 priv->presvd_phy_bmcr = 0;
653 }
654}
655
656static void ax88772_resume(struct usbnet *dev)
657{
658 int i;
659
660 for (i = 0; i < 3; i++)
661 if (!ax88772_hw_reset(dev, 1))
662 break;
663 ax88772_restore_phy(dev);
664}
665
666static void ax88772a_resume(struct usbnet *dev)
667{
668 int i;
669
670 for (i = 0; i < 3; i++) {
671 if (!ax88772a_hw_reset(dev, 1))
672 break;
673 }
674
675 ax88772_restore_phy(dev);
676}
677
678static int asix_resume(struct usb_interface *intf)
679{
680 struct usbnet *dev = usb_get_intfdata(intf);
681 struct asix_common_private *priv = dev->driver_priv;
682
8f562462 683 if (priv && priv->resume)
d9fe64e5
RF		 684 priv->resume(dev);
685
686 return usbnet_resume(intf);
687}
688
4ad1438f
GG		 689static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
690{
d9fe64e5
RF		 691 int ret, i;
692 u8 buf[ETH_ALEN], chipcode = 0;
4ad1438f 693 u32 phyid;
d9fe64e5 694 struct asix_common_private *priv;
4ad1438f 695
03fc5d4f 696 usbnet_get_endpoints(dev, intf);
4ad1438f 697
03fc5d4f
MZ		 698 /* Maybe the boot loader passed the MAC address via device tree */
699 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) {
700 netif_dbg(dev, ifup, dev->net,
701 "MAC address read from device tree");
5620df65 702 } else {
03fc5d4f
MZ		 703 /* Try getting the MAC address from EEPROM */
704 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
705 for (i = 0; i < (ETH_ALEN >> 1); i++) {
706 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM,
707 0x04 + i, 0, 2, buf + i * 2,
708 0);
709 if (ret < 0)
710 break;
711 }
712 } else {
713 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
714 0, 0, ETH_ALEN, buf, 0);
715 }
5620df65 716
03fc5d4f
MZ		 717 if (ret < 0) {
718 netdev_dbg(dev->net, "Failed to read MAC address: %d\n",
719 ret);
720 return ret;
721 }
4ad1438f 722 }
452b5ecd
JCPV		 723
724 asix_set_netdev_dev_addr(dev, buf);
4ad1438f
GG		 725
726 /* Initialize MII structure */
727 dev->mii.dev = dev->net;
728 dev->mii.mdio_read = asix_mdio_read;
729 dev->mii.mdio_write = asix_mdio_write;
730 dev->mii.phy_id_mask = 0x1f;
731 dev->mii.reg_num_mask = 0x1f;
732 dev->mii.phy_id = asix_get_phy_addr(dev);
733
4ad1438f
GG		 734 dev->net->netdev_ops = &ax88772_netdev_ops;
735 dev->net->ethtool_ops = &ax88772_ethtool_ops;
95162d65
ED		 736 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
737 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
4ad1438f 738
d9fe64e5
RF		 739 asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0);
740 chipcode &= AX_CHIPCODE_MASK;
d3665188 741
6eea3527
ZR		 742 ret = (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) :
743 ax88772a_hw_reset(dev, 0);
744
745 if (ret < 0) {
746 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret);
747 return ret;
748 }
d3665188
GG		 749
750 /* Read PHYID register *AFTER* the PHY was reset properly */
751 phyid = asix_get_phyid(dev);
49ae25b0 752 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
d3665188 753
2e55cc72
DB		 754 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
755 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
756 /* hard_mtu is still the default - the device does not support
757 jumbo eth frames */
758 dev->rx_urb_size = 2048;
759 }
83e1b918 760
8b5b6f54
LS		 761 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
762 if (!dev->driver_priv)
763 return -ENOMEM;
764
d9fe64e5
RF		 765 priv = dev->driver_priv;
766
767 priv->presvd_phy_bmcr = 0;
768 priv->presvd_phy_advertise = 0;
769 if (chipcode == AX_AX88772_CHIPCODE) {
770 priv->resume = ax88772_resume;
771 priv->suspend = ax88772_suspend;
772 } else {
773 priv->resume = ax88772a_resume;
774 priv->suspend = ax88772_suspend;
775 }
776
2e55cc72 777 return 0;
2e55cc72
DB		 778}
779
ad327910 780static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
8b5b6f54 781{
d0c8f338 782 asix_rx_fixup_common_free(dev->driver_priv);
91ecee68 783 kfree(dev->driver_priv);
8b5b6f54
LS		 784}
785
bc689c97 786static const struct ethtool_ops ax88178_ethtool_ops = {
933a27d3
DH		 787 .get_drvinfo = asix_get_drvinfo,
788 .get_link = asix_get_link,
933a27d3
DH		 789 .get_msglevel = usbnet_get_msglevel,
790 .set_msglevel = usbnet_set_msglevel,
791 .get_wol = asix_get_wol,
792 .set_wol = asix_set_wol,
793 .get_eeprom_len = asix_get_eeprom_len,
794 .get_eeprom = asix_get_eeprom,
cb7b24cd 795 .set_eeprom = asix_set_eeprom,
c41286fd 796 .nway_reset = usbnet_nway_reset,
fd4f0a75
PR		 797 .get_link_ksettings = usbnet_get_link_ksettings,
798 .set_link_ksettings = usbnet_set_link_ksettings,
933a27d3
DH		 799};
800
801static int marvell_phy_init(struct usbnet *dev)
2e55cc72 802{
933a27d3
DH		 803 struct asix_data *data = (struct asix_data *)&dev->data;
804 u16 reg;
2e55cc72 805
60b86755 806 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 807
933a27d3 808 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 809 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 810
933a27d3
DH		 811 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
812 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 813
933a27d3
DH		 814 if (data->ledmode) {
815 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
816 MII_MARVELL_LED_CTRL);
60b86755 817 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 818
933a27d3
DH		 819 reg &= 0xf8ff;
820 reg |= (1 + 0x0100);
821 asix_mdio_write(dev->net, dev->mii.phy_id,
822 MII_MARVELL_LED_CTRL, reg);
2e55cc72 823
933a27d3
DH		 824 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
825 MII_MARVELL_LED_CTRL);
60b86755 826 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH		 827 reg &= 0xfc0f;
828 }
2e55cc72 829
933a27d3
DH		 830 return 0;
831}
832
610d885d
GG		 833static int rtl8211cl_phy_init(struct usbnet *dev)
834{
835 struct asix_data *data = (struct asix_data *)&dev->data;
836
837 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
838
839 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
840 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
841 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
842 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
843 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
844
845 if (data->ledmode == 12) {
846 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
847 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
848 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
849 }
850
851 return 0;
852}
853
933a27d3
DH		 854static int marvell_led_status(struct usbnet *dev, u16 speed)
855{
856 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
857
60b86755 858 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH		 859
860 /* Clear out the center LED bits - 0x03F0 */
861 reg &= 0xfc0f;
862
863 switch (speed) {
864 case SPEED_1000:
865 reg |= 0x03e0;
866 break;
867 case SPEED_100:
868 reg |= 0x03b0;
869 break;
870 default:
871 reg |= 0x02f0;
2e55cc72
DB		 872 }
873
60b86755 874 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH		 875 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
876
877 return 0;
878}
879
610d885d
GG		 880static int ax88178_reset(struct usbnet *dev)
881{
882 struct asix_data *data = (struct asix_data *)&dev->data;
883 int ret;
884 __le16 eeprom;
885 u8 status;
886 int gpio0 = 0;
b2d3ad29 887 u32 phyid;
610d885d 888
d9fe64e5 889 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
49ae25b0 890 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
610d885d 891
d9fe64e5
RF		 892 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
893 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
894 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
610d885d 895
49ae25b0 896 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
610d885d
GG		 897
898 if (eeprom == cpu_to_le16(0xffff)) {
899 data->phymode = PHY_MODE_MARVELL;
900 data->ledmode = 0;
901 gpio0 = 1;
902 } else {
b2d3ad29 903 data->phymode = le16_to_cpu(eeprom) & 0x7F;
610d885d
GG		 904 data->ledmode = le16_to_cpu(eeprom) >> 8;
905 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
906 }
49ae25b0 907 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
610d885d 908
b2d3ad29 909 /* Power up external GigaPHY through AX88178 GPIO pin */
d9fe64e5
RF		 910 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
911 AX_GPIO_GPO1EN, 40, 0);
610d885d 912 if ((le16_to_cpu(eeprom) >> 8) != 1) {
d9fe64e5
RF		 913 asix_write_gpio(dev, 0x003c, 30, 0);
914 asix_write_gpio(dev, 0x001c, 300, 0);
915 asix_write_gpio(dev, 0x003c, 30, 0);
610d885d 916 } else {
49ae25b0 917 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
d9fe64e5
RF		 918 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
919 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
610d885d
GG		 920 }
921
b2d3ad29
GG		 922 /* Read PHYID register *AFTER* powering up PHY */
923 phyid = asix_get_phyid(dev);
49ae25b0 924 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
b2d3ad29
GG		 925
926 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
d9fe64e5 927 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
b2d3ad29 928
d9fe64e5 929 asix_sw_reset(dev, 0, 0);
610d885d
GG		 930 msleep(150);
931
d9fe64e5 932 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
610d885d
GG		 933 msleep(150);
934
d9fe64e5 935 asix_write_rx_ctl(dev, 0, 0);
610d885d
GG		 936
937 if (data->phymode == PHY_MODE_MARVELL) {
938 marvell_phy_init(dev);
939 msleep(60);
940 } else if (data->phymode == PHY_MODE_RTL8211CL)
941 rtl8211cl_phy_init(dev);
942
a243c2ef 943 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
610d885d
GG		 944 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
945 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
946 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
947 ADVERTISE_1000FULL);
948
535baf85 949 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
610d885d
GG		 950 mii_nway_restart(&dev->mii);
951
71bc5d94
JK		 952 /* Rewrite MAC address */
953 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
954 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
d9fe64e5 955 data->mac_addr, 0);
71bc5d94
JK		 956 if (ret < 0)
957 return ret;
958
d9fe64e5 959 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
83e1b918
GG		 960 if (ret < 0)
961 return ret;
610d885d
GG		 962
963 return 0;
610d885d
GG		 964}
965
933a27d3
DH		 966static int ax88178_link_reset(struct usbnet *dev)
967{
968 u16 mode;
8ae6daca 969 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3 970 struct asix_data *data = (struct asix_data *)&dev->data;
8ae6daca 971 u32 speed;
933a27d3 972
60b86755 973 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH		 974
975 mii_check_media(&dev->mii, 1, 1);
976 mii_ethtool_gset(&dev->mii, &ecmd);
977 mode = AX88178_MEDIUM_DEFAULT;
8ae6daca 978 speed = ethtool_cmd_speed(&ecmd);
933a27d3 979
8ae6daca 980 if (speed == SPEED_1000)
a7f75c0c 981 mode |= AX_MEDIUM_GM;
8ae6daca 982 else if (speed == SPEED_100)
933a27d3
DH		 983 mode |= AX_MEDIUM_PS;
984 else
985 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
986
a7f75c0c
PK		 987 mode |= AX_MEDIUM_ENCK;
988
933a27d3
DH		 989 if (ecmd.duplex == DUPLEX_FULL)
990 mode |= AX_MEDIUM_FD;
991 else
992 mode &= ~AX_MEDIUM_FD;
993
8ae6daca
DD		 994 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
995 speed, ecmd.duplex, mode);
933a27d3 996
d9fe64e5 997 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 998
999 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
8ae6daca 1000 marvell_led_status(dev, speed);
933a27d3
DH		 1001
1002 return 0;
1003}
1004
1005static void ax88178_set_mfb(struct usbnet *dev)
1006{
1007 u16 mfb = AX_RX_CTL_MFB_16384;
1008 u16 rxctl;
1009 u16 medium;
1010 int old_rx_urb_size = dev->rx_urb_size;
1011
1012 if (dev->hard_mtu < 2048) {
1013 dev->rx_urb_size = 2048;
1014 mfb = AX_RX_CTL_MFB_2048;
1015 } else if (dev->hard_mtu < 4096) {
1016 dev->rx_urb_size = 4096;
1017 mfb = AX_RX_CTL_MFB_4096;
1018 } else if (dev->hard_mtu < 8192) {
1019 dev->rx_urb_size = 8192;
1020 mfb = AX_RX_CTL_MFB_8192;
1021 } else if (dev->hard_mtu < 16384) {
1022 dev->rx_urb_size = 16384;
1023 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 1024 }
933a27d3 1025
d9fe64e5
RF		 1026 rxctl = asix_read_rx_ctl(dev, 0);
1027 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
933a27d3 1028
d9fe64e5 1029 medium = asix_read_medium_status(dev, 0);
933a27d3
DH		 1030 if (dev->net->mtu > 1500)
1031 medium |= AX_MEDIUM_JFE;
1032 else
1033 medium &= ~AX_MEDIUM_JFE;
d9fe64e5 1034 asix_write_medium_mode(dev, medium, 0);
933a27d3
DH		 1035
1036 if (dev->rx_urb_size > old_rx_urb_size)
1037 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 1038}
1039
933a27d3 1040static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 1041{
933a27d3
DH		 1042 struct usbnet *dev = netdev_priv(net);
1043 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 1044
60b86755 1045 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 1046
933a27d3
DH		 1047 if ((ll_mtu % dev->maxpacket) == 0)
1048 return -EDOM;
1049
1050 net->mtu = new_mtu;
1051 dev->hard_mtu = net->mtu + net->hard_header_len;
1052 ax88178_set_mfb(dev);
1053
a88c32ae
ML		 1054 /* max qlen depend on hard_mtu and rx_urb_size */
1055 usbnet_update_max_qlen(dev);
1056
933a27d3
DH		 1057 return 0;
1058}
1059
1703338c
SH		 1060static const struct net_device_ops ax88178_netdev_ops = {
1061 .ndo_open = usbnet_open,
1062 .ndo_stop = usbnet_stop,
1063 .ndo_start_xmit = usbnet_start_xmit,
1064 .ndo_tx_timeout = usbnet_tx_timeout,
c8b5d129 1065 .ndo_get_stats64 = usbnet_get_stats64,
7f29a3ba 1066 .ndo_set_mac_address = asix_set_mac_address,
1703338c 1067 .ndo_validate_addr = eth_validate_addr,
afc4b13d 1068 .ndo_set_rx_mode = asix_set_multicast,
1703338c
SH		 1069 .ndo_do_ioctl = asix_ioctl,
1070 .ndo_change_mtu = ax88178_change_mtu,
1071};
1072
933a27d3
DH		 1073static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1074{
933a27d3 1075 int ret;
51bf2976 1076 u8 buf[ETH_ALEN];
933a27d3
DH		 1077
1078 usbnet_get_endpoints(dev,intf);
1079
933a27d3 1080 /* Get the MAC address */
d9fe64e5 1081 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
83e1b918 1082 if (ret < 0) {
49ae25b0 1083 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 1084 return ret;
2e55cc72 1085 }
452b5ecd
JCPV		 1086
1087 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 1088
933a27d3
DH		 1089 /* Initialize MII structure */
1090 dev->mii.dev = dev->net;
1091 dev->mii.mdio_read = asix_mdio_read;
1092 dev->mii.mdio_write = asix_mdio_write;
1093 dev->mii.phy_id_mask = 0x1f;
1094 dev->mii.reg_num_mask = 0xff;
1095 dev->mii.supports_gmii = 1;
933a27d3 1096 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH		 1097
1098 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 1099 dev->net->ethtool_ops = &ax88178_ethtool_ops;
f77f0aee 1100 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4);
2e55cc72 1101
b2d3ad29 1102 /* Blink LEDS so users know driver saw dongle */
d9fe64e5 1103 asix_sw_reset(dev, 0, 0);
b2d3ad29 1104 msleep(150);
2e55cc72 1105
d9fe64e5 1106 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
b2d3ad29 1107 msleep(150);
933a27d3
DH		 1108
1109 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1110 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1111 /* hard_mtu is still the default - the device does not support
1112 jumbo eth frames */
1113 dev->rx_urb_size = 2048;
1114 }
933a27d3 1115
8b5b6f54
LS		 1116 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1117 if (!dev->driver_priv)
1118 return -ENOMEM;
1119
83e1b918 1120 return 0;
2e55cc72
DB		 1121}
1122
1123static const struct driver_info ax8817x_info = {
1124 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 1125 .bind = ax88172_bind,
1126 .status = asix_status,
2e55cc72
DB		 1127 .link_reset = ax88172_link_reset,
1128 .reset = ax88172_link_reset,
37e8273c 1129 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1130 .data = 0x00130103,
1131};
1132
1133static const struct driver_info dlink_dub_e100_info = {
1134 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 1135 .bind = ax88172_bind,
1136 .status = asix_status,
2e55cc72
DB		 1137 .link_reset = ax88172_link_reset,
1138 .reset = ax88172_link_reset,
37e8273c 1139 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1140 .data = 0x009f9d9f,
1141};
1142
1143static const struct driver_info netgear_fa120_info = {
1144 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 1145 .bind = ax88172_bind,
1146 .status = asix_status,
2e55cc72
DB		 1147 .link_reset = ax88172_link_reset,
1148 .reset = ax88172_link_reset,
37e8273c 1149 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1150 .data = 0x00130103,
1151};
1152
1153static const struct driver_info hawking_uf200_info = {
1154 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 1155 .bind = ax88172_bind,
1156 .status = asix_status,
2e55cc72
DB		 1157 .link_reset = ax88172_link_reset,
1158 .reset = ax88172_link_reset,
37e8273c 1159 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1160 .data = 0x001f1d1f,
1161};
1162
1163static const struct driver_info ax88772_info = {
1164 .description = "ASIX AX88772 USB 2.0 Ethernet",
1165 .bind = ax88772_bind,
8b5b6f54 1166 .unbind = ax88772_unbind,
48b1be6a 1167 .status = asix_status,
2e55cc72 1168 .link_reset = ax88772_link_reset,
d9fe64e5 1169 .reset = ax88772_reset,
a9e0aca4 1170 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
8b5b6f54 1171 .rx_fixup = asix_rx_fixup_common,
933a27d3
DH		 1172 .tx_fixup = asix_tx_fixup,
1173};
1174
5620df65
LS		 1175static const struct driver_info ax88772b_info = {
1176 .description = "ASIX AX88772B USB 2.0 Ethernet",
1177 .bind = ax88772_bind,
8b5b6f54 1178 .unbind = ax88772_unbind,
5620df65
LS		 1179 .status = asix_status,
1180 .link_reset = ax88772_link_reset,
1181 .reset = ax88772_reset,
1182 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1183 FLAG_MULTI_PACKET,
8b5b6f54 1184 .rx_fixup = asix_rx_fixup_common,
5620df65
LS		 1185 .tx_fixup = asix_tx_fixup,
1186 .data = FLAG_EEPROM_MAC,
1187};
1188
933a27d3
DH		 1189static const struct driver_info ax88178_info = {
1190 .description = "ASIX AX88178 USB 2.0 Ethernet",
1191 .bind = ax88178_bind,
8b5b6f54 1192 .unbind = ax88772_unbind,
933a27d3
DH		 1193 .status = asix_status,
1194 .link_reset = ax88178_link_reset,
610d885d 1195 .reset = ax88178_reset,
d43ff4cd
EG		 1196 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1197 FLAG_MULTI_PACKET,
8b5b6f54 1198 .rx_fixup = asix_rx_fixup_common,
933a27d3 1199 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 1200};
1201
45af3fb4
GT		 1202/*
1203 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1204 * no-name packaging.
1205 * USB device strings are:
1206 * 1: Manufacturer: USBLINK
1207 * 2: Product: HG20F9 USB2.0
1208 * 3: Serial: 000003
1209 * Appears to be compatible with Asix 88772B.
1210 */
1211static const struct driver_info hg20f9_info = {
1212 .description = "HG20F9 USB 2.0 Ethernet",
1213 .bind = ax88772_bind,
1214 .unbind = ax88772_unbind,
1215 .status = asix_status,
1216 .link_reset = ax88772_link_reset,
1217 .reset = ax88772_reset,
1218 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1219 FLAG_MULTI_PACKET,
1220 .rx_fixup = asix_rx_fixup_common,
1221 .tx_fixup = asix_tx_fixup,
1222 .data = FLAG_EEPROM_MAC,
1223};
1224
2e55cc72
DB		 1225static const struct usb_device_id products [] = {
1226{
1227 // Linksys USB200M
1228 USB_DEVICE (0x077b, 0x2226),
1229 .driver_info = (unsigned long) &ax8817x_info,
1230}, {
1231 // Netgear FA120
1232 USB_DEVICE (0x0846, 0x1040),
1233 .driver_info = (unsigned long) &netgear_fa120_info,
1234}, {
1235 // DLink DUB-E100
1236 USB_DEVICE (0x2001, 0x1a00),
1237 .driver_info = (unsigned long) &dlink_dub_e100_info,
1238}, {
1239 // Intellinet, ST Lab USB Ethernet
1240 USB_DEVICE (0x0b95, 0x1720),
1241 .driver_info = (unsigned long) &ax8817x_info,
1242}, {
1243 // Hawking UF200, TrendNet TU2-ET100
1244 USB_DEVICE (0x07b8, 0x420a),
1245 .driver_info = (unsigned long) &hawking_uf200_info,
1246}, {
39c4b38c
DH		 1247 // Billionton Systems, USB2AR
1248 USB_DEVICE (0x08dd, 0x90ff),
1249 .driver_info = (unsigned long) &ax8817x_info,
80083a3c
CSC		 1250}, {
1251 // Billionton Systems, GUSB2AM-1G-B
1252 USB_DEVICE(0x08dd, 0x0114),
1253 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1254}, {
1255 // ATEN UC210T
1256 USB_DEVICE (0x0557, 0x2009),
1257 .driver_info = (unsigned long) &ax8817x_info,
1258}, {
1259 // Buffalo LUA-U2-KTX
1260 USB_DEVICE (0x0411, 0x003d),
1261 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD		 1262}, {
1263 // Buffalo LUA-U2-GT 10/100/1000
1264 USB_DEVICE (0x0411, 0x006e),
1265 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1266}, {
1267 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1268 USB_DEVICE (0x6189, 0x182d),
1269 .driver_info = (unsigned long) &ax8817x_info,
4e503919
JN		 1270}, {
1271 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1272 USB_DEVICE (0x0df6, 0x0056),
1273 .driver_info = (unsigned long) &ax88178_info,
7488c3e3
LC		 1274}, {
1275 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1276 USB_DEVICE (0x0df6, 0x061c),
1277 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1278}, {
1279 // corega FEther USB2-TX
1280 USB_DEVICE (0x07aa, 0x0017),
1281 .driver_info = (unsigned long) &ax8817x_info,
1282}, {
1283 // Surecom EP-1427X-2
1284 USB_DEVICE (0x1189, 0x0893),
1285 .driver_info = (unsigned long) &ax8817x_info,
1286}, {
1287 // goodway corp usb gwusb2e
1288 USB_DEVICE (0x1631, 0x6200),
1289 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH		 1290}, {
1291 // JVC MP-PRX1 Port Replicator
1292 USB_DEVICE (0x04f1, 0x3008),
1293 .driver_info = (unsigned long) &ax8817x_info,
66dc81ec
QP		 1294}, {
1295 // Lenovo U2L100P 10/100
1296 USB_DEVICE (0x17ef, 0x7203),
d9fe64e5 1297 .driver_info = (unsigned long)&ax88772b_info,
30885909
MV		 1298}, {
1299 // ASIX AX88772B 10/100
1300 USB_DEVICE (0x0b95, 0x772b),
5620df65 1301 .driver_info = (unsigned long) &ax88772b_info,
2e55cc72
DB		 1302}, {
1303 // ASIX AX88772 10/100
39c4b38c
DH		 1304 USB_DEVICE (0x0b95, 0x7720),
1305 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 1306}, {
1307 // ASIX AX88178 10/100/1000
1308 USB_DEVICE (0x0b95, 0x1780),
933a27d3 1309 .driver_info = (unsigned long) &ax88178_info,
f4680d3d
AE		 1310}, {
1311 // Logitec LAN-GTJ/U2A
1312 USB_DEVICE (0x0789, 0x0160),
1313 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 1314}, {
1315 // Linksys USB200M Rev 2
1316 USB_DEVICE (0x13b1, 0x0018),
1317 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 1318}, {
1319 // 0Q0 cable ethernet
1320 USB_DEVICE (0x1557, 0x7720),
1321 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1322}, {
1323 // DLink DUB-E100 H/W Ver B1
1324 USB_DEVICE (0x07d1, 0x3c05),
1325 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 1326}, {
1327 // DLink DUB-E100 H/W Ver B1 Alternate
1328 USB_DEVICE (0x2001, 0x3c05),
1329 .driver_info = (unsigned long) &ax88772_info,
ed3770a9
S		 1330}, {
1331 // DLink DUB-E100 H/W Ver C1
1332 USB_DEVICE (0x2001, 0x1a02),
1333 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1334}, {
1335 // Linksys USB1000
1336 USB_DEVICE (0x1737, 0x0039),
1337 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH		 1338}, {
1339 // IO-DATA ETG-US2
1340 USB_DEVICE (0x04bb, 0x0930),
1341 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH		 1342}, {
1343 // Belkin F5D5055
1344 USB_DEVICE(0x050d, 0x5055),
1345 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN		 1346}, {
1347 // Apple USB Ethernet Adapter
1348 USB_DEVICE(0x05ac, 0x1402),
1349 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC		 1350}, {
1351 // Cables-to-Go USB Ethernet Adapter
1352 USB_DEVICE(0x0b95, 0x772a),
1353 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH		 1354}, {
1355 // ABOCOM for pci
1356 USB_DEVICE(0x14ea, 0xab11),
1357 .driver_info = (unsigned long) &ax88178_info,
1358}, {
1359 // ASIX 88772a
1360 USB_DEVICE(0x0db0, 0xa877),
1361 .driver_info = (unsigned long) &ax88772_info,
e8303a3b
AJ		 1362}, {
1363 // Asus USB Ethernet Adapter
1364 USB_DEVICE (0x0b95, 0x7e2b),
d9fe64e5 1365 .driver_info = (unsigned long)&ax88772b_info,
16626b0c
CR		 1366}, {
1367 /* ASIX 88172a demo board */
1368 USB_DEVICE(0x0b95, 0x172a),
1369 .driver_info = (unsigned long) &ax88172a_info,
45af3fb4
GT		 1370}, {
1371 /*
1372 * USBLINK HG20F9 "USB 2.0 LAN"
1373 * Appears to have gazumped Linksys's manufacturer ID but
1374 * doesn't (yet) conflict with any known Linksys product.
1375 */
1376 USB_DEVICE(0x066b, 0x20f9),
1377 .driver_info = (unsigned long) &hg20f9_info,
2e55cc72
DB		 1378},
1379 { }, // END
1380};
1381MODULE_DEVICE_TABLE(usb, products);
1382
1383static struct usb_driver asix_driver = {
83e1b918 1384 .name = DRIVER_NAME,
2e55cc72
DB		 1385 .id_table = products,
1386 .probe = usbnet_probe,
d9fe64e5
RF		 1387 .suspend = asix_suspend,
1388 .resume = asix_resume,
63dfb0da 1389 .reset_resume = asix_resume,
2e55cc72 1390 .disconnect = usbnet_disconnect,
a11a6544 1391 .supports_autosuspend = 1,
e1f12eb6 1392 .disable_hub_initiated_lpm = 1,
2e55cc72
DB		 1393};
1394
d632eb1b 1395module_usb_driver(asix_driver);
2e55cc72
DB		 1396
1397MODULE_AUTHOR("David Hollis");
4ad1438f 1398MODULE_VERSION(DRIVER_VERSION);
2e55cc72
DB		 1399MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1400MODULE_LICENSE("GPL");
1401
Ubuntu Focal Linux kernel mirror