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net: asix: Fix AX88772x resume failures
[mirror_ubuntu-zesty-kernel.git] / drivers / net / usb / asix_devices.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
9cb00073 19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
2e55cc72
DB		 20 */
21
607740bc 22#include "asix.h"
933a27d3
DH		 23
24#define PHY_MODE_MARVELL 0x0000
25#define MII_MARVELL_LED_CTRL 0x0018
26#define MII_MARVELL_STATUS 0x001b
27#define MII_MARVELL_CTRL 0x0014
28
29#define MARVELL_LED_MANUAL 0x0019
30
31#define MARVELL_STATUS_HWCFG 0x0004
32
33#define MARVELL_CTRL_TXDELAY 0x0002
34#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72 35
3486140e 36#define PHY_MODE_RTL8211CL 0x000C
610d885d 37
4c1442aa
RF		 38#define AX88772A_PHY14H 0x14
39#define AX88772A_PHY14H_DEFAULT 0x442C
40
41#define AX88772A_PHY15H 0x15
42#define AX88772A_PHY15H_DEFAULT 0x03C8
43
44#define AX88772A_PHY16H 0x16
45#define AX88772A_PHY16H_DEFAULT 0x4044
46
2e55cc72 47struct ax88172_int_data {
51bf2976 48 __le16 res1;
2e55cc72 49 u8 link;
51bf2976 50 __le16 res2;
2e55cc72 51 u8 status;
51bf2976 52 __le16 res3;
ba2d3587 53} __packed;
2e55cc72 54
933a27d3
DH		 55static void asix_status(struct usbnet *dev, struct urb *urb)
56{
57 struct ax88172_int_data *event;
58 int link;
59
60 if (urb->actual_length < 8)
61 return;
62
63 event = urb->transfer_buffer;
64 link = event->link & 0x01;
65 if (netif_carrier_ok(dev->net) != link) {
eae65919 66 usbnet_link_change(dev, link, 1);
60b86755 67 netdev_dbg(dev->net, "Link Status is: %d\n", link);
933a27d3
DH		 68 }
69}
70
452b5ecd
JCPV		 71static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
72{
73 if (is_valid_ether_addr(addr)) {
74 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
75 } else {
76 netdev_info(dev->net, "invalid hw address, using random\n");
77 eth_hw_addr_random(dev->net);
78 }
79}
80
933a27d3
DH		 81/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
82static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 83{
933a27d3
DH		 84 int phy_reg;
85 u32 phy_id;
a77929a2 86 int i;
2e55cc72 87
a77929a2
GG		 88 /* Poll for the rare case the FW or phy isn't ready yet. */
89 for (i = 0; i < 100; i++) {
90 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
8a46f665
RF		 91 if (phy_reg < 0)
92 return 0;
a77929a2
GG		 93 if (phy_reg != 0 && phy_reg != 0xFFFF)
94 break;
95 mdelay(1);
96 }
97
98 if (phy_reg <= 0 || phy_reg == 0xFFFF)
933a27d3 99 return 0;
2e55cc72 100
933a27d3 101 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 102
933a27d3
DH		 103 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
104 if (phy_reg < 0)
105 return 0;
106
107 phy_id |= (phy_reg & 0xffff);
108
109 return phy_id;
2e55cc72
DB		 110}
111
933a27d3
DH		 112static u32 asix_get_link(struct net_device *net)
113{
114 struct usbnet *dev = netdev_priv(net);
115
116 return mii_link_ok(&dev->mii);
117}
118
119static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
120{
121 struct usbnet *dev = netdev_priv(net);
122
123 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
124}
125
126/* We need to override some ethtool_ops so we require our
127 own structure so we don't interfere with other usbnet
128 devices that may be connected at the same time. */
0fc0b732 129static const struct ethtool_ops ax88172_ethtool_ops = {
933a27d3
DH		 130 .get_drvinfo = asix_get_drvinfo,
131 .get_link = asix_get_link,
933a27d3 132 .get_msglevel = usbnet_get_msglevel,
2e55cc72 133 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 134 .get_wol = asix_get_wol,
135 .set_wol = asix_set_wol,
136 .get_eeprom_len = asix_get_eeprom_len,
137 .get_eeprom = asix_get_eeprom,
cb7b24cd 138 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 139 .get_settings = usbnet_get_settings,
140 .set_settings = usbnet_set_settings,
141 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 142};
143
933a27d3 144static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 145{
146 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 147 struct asix_data *data = (struct asix_data *)&dev->data;
148 u8 rx_ctl = 0x8c;
2e55cc72 149
933a27d3
DH		 150 if (net->flags & IFF_PROMISC) {
151 rx_ctl |= 0x01;
8e95a202 152 } else if (net->flags & IFF_ALLMULTI ||
4cd24eaf 153 netdev_mc_count(net) > AX_MAX_MCAST) {
933a27d3 154 rx_ctl |= 0x02;
4cd24eaf 155 } else if (netdev_mc_empty(net)) {
933a27d3
DH		 156 /* just broadcast and directed */
157 } else {
158 /* We use the 20 byte dev->data
159 * for our 8 byte filter buffer
160 * to avoid allocating memory that
161 * is tricky to free later */
22bedad3 162 struct netdev_hw_addr *ha;
933a27d3 163 u32 crc_bits;
933a27d3
DH		 164
165 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
166
167 /* Build the multicast hash filter. */
22bedad3
JP		 168 netdev_for_each_mc_addr(ha, net) {
169 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
933a27d3
DH		 170 data->multi_filter[crc_bits >> 3] |=
171 1 << (crc_bits & 7);
933a27d3
DH		 172 }
173
174 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
175 AX_MCAST_FILTER_SIZE, data->multi_filter);
176
177 rx_ctl |= 0x10;
178 }
179
180 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
181}
182
183static int ax88172_link_reset(struct usbnet *dev)
184{
185 u8 mode;
8ae6daca 186 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 187
188 mii_check_media(&dev->mii, 1, 1);
189 mii_ethtool_gset(&dev->mii, &ecmd);
190 mode = AX88172_MEDIUM_DEFAULT;
191
192 if (ecmd.duplex != DUPLEX_FULL)
193 mode |= ~AX88172_MEDIUM_FD;
194
8ae6daca
DD		 195 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
196 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3 197
d9fe64e5 198 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 199
200 return 0;
2e55cc72
DB		 201}
202
1703338c
SH		 203static const struct net_device_ops ax88172_netdev_ops = {
204 .ndo_open = usbnet_open,
205 .ndo_stop = usbnet_stop,
206 .ndo_start_xmit = usbnet_start_xmit,
207 .ndo_tx_timeout = usbnet_tx_timeout,
208 .ndo_change_mtu = usbnet_change_mtu,
209 .ndo_set_mac_address = eth_mac_addr,
210 .ndo_validate_addr = eth_validate_addr,
211 .ndo_do_ioctl = asix_ioctl,
afc4b13d 212 .ndo_set_rx_mode = ax88172_set_multicast,
1703338c
SH		 213};
214
48b1be6a 215static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 216{
217 int ret = 0;
51bf2976 218 u8 buf[ETH_ALEN];
2e55cc72
DB		 219 int i;
220 unsigned long gpio_bits = dev->driver_info->data;
221
222 usbnet_get_endpoints(dev,intf);
223
2e55cc72
DB		 224 /* Toggle the GPIOs in a manufacturer/model specific way */
225 for (i = 2; i >= 0; i--) {
83e1b918 226 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
d9fe64e5 227 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
83e1b918 228 if (ret < 0)
51bf2976 229 goto out;
2e55cc72
DB		 230 msleep(5);
231 }
232
d9fe64e5 233 ret = asix_write_rx_ctl(dev, 0x80, 0);
83e1b918 234 if (ret < 0)
51bf2976 235 goto out;
2e55cc72
DB		 236
237 /* Get the MAC address */
d9fe64e5
RF		 238 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
239 0, 0, ETH_ALEN, buf, 0);
83e1b918 240 if (ret < 0) {
49ae25b0
GKH		 241 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
242 ret);
51bf2976 243 goto out;
2e55cc72 244 }
452b5ecd
JCPV		 245
246 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 247
2e55cc72
DB		 248 /* Initialize MII structure */
249 dev->mii.dev = dev->net;
48b1be6a
DH		 250 dev->mii.mdio_read = asix_mdio_read;
251 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 252 dev->mii.phy_id_mask = 0x3f;
253 dev->mii.reg_num_mask = 0x1f;
933a27d3 254 dev->mii.phy_id = asix_get_phy_addr(dev);
2e55cc72 255
1703338c 256 dev->net->netdev_ops = &ax88172_netdev_ops;
48b1be6a 257 dev->net->ethtool_ops = &ax88172_ethtool_ops;
95162d65
ED		 258 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
259 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
2e55cc72 260
933a27d3
DH		 261 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
262 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 263 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
264 mii_nway_restart(&dev->mii);
265
266 return 0;
51bf2976
AV		 267
268out:
2e55cc72
DB		 269 return ret;
270}
271
0fc0b732 272static const struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 273 .get_drvinfo = asix_get_drvinfo,
933a27d3 274 .get_link = asix_get_link,
2e55cc72
DB		 275 .get_msglevel = usbnet_get_msglevel,
276 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 277 .get_wol = asix_get_wol,
278 .set_wol = asix_set_wol,
279 .get_eeprom_len = asix_get_eeprom_len,
280 .get_eeprom = asix_get_eeprom,
cb7b24cd 281 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 282 .get_settings = usbnet_get_settings,
283 .set_settings = usbnet_set_settings,
284 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 285};
286
933a27d3
DH		 287static int ax88772_link_reset(struct usbnet *dev)
288{
289 u16 mode;
8ae6daca 290 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3
DH		 291
292 mii_check_media(&dev->mii, 1, 1);
293 mii_ethtool_gset(&dev->mii, &ecmd);
294 mode = AX88772_MEDIUM_DEFAULT;
295
8ae6daca 296 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
933a27d3
DH		 297 mode &= ~AX_MEDIUM_PS;
298
299 if (ecmd.duplex != DUPLEX_FULL)
300 mode &= ~AX_MEDIUM_FD;
301
8ae6daca
DD		 302 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
303 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
933a27d3 304
d9fe64e5 305 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 306
307 return 0;
308}
309
4ad1438f 310static int ax88772_reset(struct usbnet *dev)
d9fe64e5
RF		 311{
312 struct asix_data *data = (struct asix_data *)&dev->data;
313 int ret;
314
315 /* Rewrite MAC address */
316 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
317 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
318 ETH_ALEN, data->mac_addr, 0);
319 if (ret < 0)
320 goto out;
321
322 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
323 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
324 if (ret < 0)
325 goto out;
326
327 asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
328 if (ret < 0)
329 goto out;
330
331 return 0;
332
333out:
334 return ret;
335}
336
337static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
2e55cc72 338{
8ef66bdc 339 struct asix_data *data = (struct asix_data *)&dev->data;
d0ffff8f 340 int ret, embd_phy;
933a27d3 341 u16 rx_ctl;
2e55cc72 342
d9fe64e5
RF		 343 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
344 AX_GPIO_GPO2EN, 5, in_pm);
83e1b918 345 if (ret < 0)
51bf2976 346 goto out;
2e55cc72 347
d9fe64e5 348 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
4ad1438f 349
d9fe64e5
RF		 350 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy,
351 0, 0, NULL, in_pm);
83e1b918 352 if (ret < 0) {
49ae25b0 353 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
51bf2976 354 goto out;
2e55cc72
DB		 355 }
356
d9fe64e5
RF		 357 if (embd_phy) {
358 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
359 if (ret < 0)
360 goto out;
2e55cc72 361
d9fe64e5 362 usleep_range(10000, 11000);
83e1b918 363
d9fe64e5
RF		 364 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
365 if (ret < 0)
366 goto out;
2e55cc72 367
d9fe64e5 368 msleep(60);
4ad1438f 369
d9fe64e5
RF		 370 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
371 in_pm);
83e1b918 372 if (ret < 0)
51bf2976 373 goto out;
83e1b918 374 } else {
d9fe64e5
RF		 375 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
376 in_pm);
83e1b918 377 if (ret < 0)
51bf2976 378 goto out;
d0ffff8f 379 }
2e55cc72
DB		 380
381 msleep(150);
d9fe64e5
RF		 382
383 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
384 MII_PHYSID1))){
385 ret = -EIO;
386 goto out;
387 }
388
389 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
390 if (ret < 0)
391 goto out;
392
393 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
83e1b918 394 if (ret < 0)
51bf2976 395 goto out;
2e55cc72 396
d9fe64e5
RF		 397 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
398 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
399 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
400 if (ret < 0) {
401 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
402 goto out;
403 }
933a27d3 404
d9fe64e5
RF		 405 /* Rewrite MAC address */
406 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
407 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
408 ETH_ALEN, data->mac_addr, in_pm);
83e1b918 409 if (ret < 0)
51bf2976 410 goto out;
2e55cc72 411
d9fe64e5
RF		 412 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
413 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
414 if (ret < 0)
415 goto out;
416
417 rx_ctl = asix_read_rx_ctl(dev, in_pm);
418 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
419 rx_ctl);
420
421 rx_ctl = asix_read_medium_status(dev, in_pm);
422 netdev_dbg(dev->net,
423 "Medium Status is 0x%04x after all initializations\n",
424 rx_ctl);
425
426 return 0;
427
428out:
429 return ret;
430}
431
432static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
433{
434 struct asix_data *data = (struct asix_data *)&dev->data;
435 int ret, embd_phy;
4c1442aa 436 u16 rx_ctl, phy14h, phy15h, phy16h;
d9fe64e5 437 u8 chipcode = 0;
48b1be6a 438
d9fe64e5 439 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
83e1b918 440 if (ret < 0)
51bf2976 441 goto out;
2e55cc72 442
d9fe64e5 443 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
2e55cc72 444
d9fe64e5
RF		 445 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy |
446 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
447 if (ret < 0) {
448 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
449 goto out;
450 }
451 usleep_range(10000, 11000);
2e55cc72 452
d9fe64e5 453 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
83e1b918 454 if (ret < 0)
51bf2976 455 goto out;
2e55cc72 456
d9fe64e5
RF		 457 usleep_range(10000, 11000);
458
459 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
460 if (ret < 0)
461 goto out;
462
463 msleep(160);
464
465 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
466 if (ret < 0)
467 goto out;
468
469 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
470 if (ret < 0)
471 goto out;
472
473 msleep(200);
474
475 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
476 MII_PHYSID1))) {
477 ret = -1;
478 goto out;
479 }
480
481 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0,
482 0, 1, &chipcode, in_pm);
483 if (ret < 0)
484 goto out;
485
486 if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) {
487 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
488 0, NULL, in_pm);
489 if (ret < 0) {
490 netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
491 ret);
492 goto out;
493 }
4c1442aa
RF		 494 } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) {
495 /* Check if the PHY registers have default settings */
496 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
497 AX88772A_PHY14H);
498 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
499 AX88772A_PHY15H);
500 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
501 AX88772A_PHY16H);
502
503 netdev_dbg(dev->net,
504 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
505 phy14h, phy15h, phy16h);
506
507 /* Restore PHY registers default setting if not */
508 if (phy14h != AX88772A_PHY14H_DEFAULT)
509 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
510 AX88772A_PHY14H,
511 AX88772A_PHY14H_DEFAULT);
512 if (phy15h != AX88772A_PHY15H_DEFAULT)
513 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
514 AX88772A_PHY15H,
515 AX88772A_PHY15H_DEFAULT);
516 if (phy16h != AX88772A_PHY16H_DEFAULT)
517 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
518 AX88772A_PHY16H,
519 AX88772A_PHY16H_DEFAULT);
d9fe64e5
RF		 520 }
521
83e1b918 522 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72 523 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
d9fe64e5 524 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
83e1b918 525 if (ret < 0) {
49ae25b0 526 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
51bf2976 527 goto out;
2e55cc72 528 }
2e55cc72 529
8ef66bdc
JK		 530 /* Rewrite MAC address */
531 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
532 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
d9fe64e5
RF		 533 data->mac_addr, in_pm);
534 if (ret < 0)
535 goto out;
536
537 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
538 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
8ef66bdc
JK		 539 if (ret < 0)
540 goto out;
541
d9fe64e5
RF		 542 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
543 if (ret < 0)
544 return ret;
545
2e55cc72 546 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
d9fe64e5 547 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
83e1b918 548 if (ret < 0)
51bf2976 549 goto out;
2e55cc72 550
d9fe64e5 551 rx_ctl = asix_read_rx_ctl(dev, in_pm);
49ae25b0
GKH		 552 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
553 rx_ctl);
933a27d3 554
d9fe64e5 555 rx_ctl = asix_read_medium_status(dev, in_pm);
49ae25b0
GKH		 556 netdev_dbg(dev->net,
557 "Medium Status is 0x%04x after all initializations\n",
558 rx_ctl);
933a27d3 559
4ad1438f
GG		 560 return 0;
561
562out:
563 return ret;
4ad1438f
GG		 564}
565
566static const struct net_device_ops ax88772_netdev_ops = {
567 .ndo_open = usbnet_open,
568 .ndo_stop = usbnet_stop,
569 .ndo_start_xmit = usbnet_start_xmit,
570 .ndo_tx_timeout = usbnet_tx_timeout,
571 .ndo_change_mtu = usbnet_change_mtu,
572 .ndo_set_mac_address = asix_set_mac_address,
573 .ndo_validate_addr = eth_validate_addr,
574 .ndo_do_ioctl = asix_ioctl,
575 .ndo_set_rx_mode = asix_set_multicast,
576};
577
d9fe64e5
RF		 578static void ax88772_suspend(struct usbnet *dev)
579{
580 struct asix_common_private *priv = dev->driver_priv;
4c1442aa
RF		 581 u16 medium;
582
583 /* Stop MAC operation */
584 medium = asix_read_medium_status(dev, 0);
585 medium &= ~AX_MEDIUM_RE;
586 asix_write_medium_mode(dev, medium, 0);
587
588 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
589 asix_read_medium_status(dev, 0));
d9fe64e5
RF		 590
591 /* Preserve BMCR for restoring */
592 priv->presvd_phy_bmcr =
593 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);
594
595 /* Preserve ANAR for restoring */
596 priv->presvd_phy_advertise =
597 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);
598}
599
600static int asix_suspend(struct usb_interface *intf, pm_message_t message)
601{
602 struct usbnet *dev = usb_get_intfdata(intf);
603 struct asix_common_private *priv = dev->driver_priv;
604
605 if (priv->suspend)
606 priv->suspend(dev);
607
608 return usbnet_suspend(intf, message);
609}
610
611static void ax88772_restore_phy(struct usbnet *dev)
612{
613 struct asix_common_private *priv = dev->driver_priv;
614
615 if (priv->presvd_phy_advertise) {
616 /* Restore Advertisement control reg */
617 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,
618 priv->presvd_phy_advertise);
619
620 /* Restore BMCR */
621 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,
622 priv->presvd_phy_bmcr);
623
4c1442aa 624 mii_nway_restart(&dev->mii);
d9fe64e5
RF		 625 priv->presvd_phy_advertise = 0;
626 priv->presvd_phy_bmcr = 0;
627 }
628}
629
630static void ax88772_resume(struct usbnet *dev)
631{
632 int i;
633
634 for (i = 0; i < 3; i++)
635 if (!ax88772_hw_reset(dev, 1))
636 break;
637 ax88772_restore_phy(dev);
638}
639
640static void ax88772a_resume(struct usbnet *dev)
641{
642 int i;
643
644 for (i = 0; i < 3; i++) {
645 if (!ax88772a_hw_reset(dev, 1))
646 break;
647 }
648
649 ax88772_restore_phy(dev);
650}
651
652static int asix_resume(struct usb_interface *intf)
653{
654 struct usbnet *dev = usb_get_intfdata(intf);
655 struct asix_common_private *priv = dev->driver_priv;
656
657 if (priv->resume)
658 priv->resume(dev);
659
660 return usbnet_resume(intf);
661}
662
4ad1438f
GG		 663static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
664{
d9fe64e5
RF		 665 int ret, i;
666 u8 buf[ETH_ALEN], chipcode = 0;
4ad1438f 667 u32 phyid;
d9fe64e5 668 struct asix_common_private *priv;
4ad1438f 669
4ad1438f
GG		 670 usbnet_get_endpoints(dev,intf);
671
672 /* Get the MAC address */
5620df65
LS		 673 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
674 for (i = 0; i < (ETH_ALEN >> 1); i++) {
675 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x04 + i,
d9fe64e5 676 0, 2, buf + i * 2, 0);
5620df65
LS		 677 if (ret < 0)
678 break;
679 }
680 } else {
681 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
d9fe64e5 682 0, 0, ETH_ALEN, buf, 0);
5620df65
LS		 683 }
684
83e1b918 685 if (ret < 0) {
49ae25b0 686 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 687 return ret;
4ad1438f 688 }
452b5ecd
JCPV		 689
690 asix_set_netdev_dev_addr(dev, buf);
4ad1438f
GG		 691
692 /* Initialize MII structure */
693 dev->mii.dev = dev->net;
694 dev->mii.mdio_read = asix_mdio_read;
695 dev->mii.mdio_write = asix_mdio_write;
696 dev->mii.phy_id_mask = 0x1f;
697 dev->mii.reg_num_mask = 0x1f;
698 dev->mii.phy_id = asix_get_phy_addr(dev);
699
4ad1438f
GG		 700 dev->net->netdev_ops = &ax88772_netdev_ops;
701 dev->net->ethtool_ops = &ax88772_ethtool_ops;
95162d65
ED		 702 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
703 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
4ad1438f 704
d9fe64e5
RF		 705 asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0);
706 chipcode &= AX_CHIPCODE_MASK;
d3665188 707
d9fe64e5
RF		 708 (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) :
709 ax88772a_hw_reset(dev, 0);
d3665188
GG		 710
711 /* Read PHYID register *AFTER* the PHY was reset properly */
712 phyid = asix_get_phyid(dev);
49ae25b0 713 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
d3665188 714
2e55cc72
DB		 715 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
716 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
717 /* hard_mtu is still the default - the device does not support
718 jumbo eth frames */
719 dev->rx_urb_size = 2048;
720 }
83e1b918 721
8b5b6f54
LS		 722 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
723 if (!dev->driver_priv)
724 return -ENOMEM;
725
d9fe64e5
RF		 726 priv = dev->driver_priv;
727
728 priv->presvd_phy_bmcr = 0;
729 priv->presvd_phy_advertise = 0;
730 if (chipcode == AX_AX88772_CHIPCODE) {
731 priv->resume = ax88772_resume;
732 priv->suspend = ax88772_suspend;
733 } else {
734 priv->resume = ax88772a_resume;
735 priv->suspend = ax88772_suspend;
736 }
737
2e55cc72 738 return 0;
2e55cc72
DB		 739}
740
ad327910 741static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
8b5b6f54 742{
91ecee68 743 kfree(dev->driver_priv);
8b5b6f54
LS		 744}
745
bc689c97 746static const struct ethtool_ops ax88178_ethtool_ops = {
933a27d3
DH		 747 .get_drvinfo = asix_get_drvinfo,
748 .get_link = asix_get_link,
933a27d3
DH		 749 .get_msglevel = usbnet_get_msglevel,
750 .set_msglevel = usbnet_set_msglevel,
751 .get_wol = asix_get_wol,
752 .set_wol = asix_set_wol,
753 .get_eeprom_len = asix_get_eeprom_len,
754 .get_eeprom = asix_get_eeprom,
cb7b24cd 755 .set_eeprom = asix_set_eeprom,
c41286fd
AB		 756 .get_settings = usbnet_get_settings,
757 .set_settings = usbnet_set_settings,
758 .nway_reset = usbnet_nway_reset,
933a27d3
DH		 759};
760
761static int marvell_phy_init(struct usbnet *dev)
2e55cc72 762{
933a27d3
DH		 763 struct asix_data *data = (struct asix_data *)&dev->data;
764 u16 reg;
2e55cc72 765
60b86755 766 netdev_dbg(dev->net, "marvell_phy_init()\n");
2e55cc72 767
933a27d3 768 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
60b86755 769 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
2e55cc72 770
933a27d3
DH		 771 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
772 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 773
933a27d3
DH		 774 if (data->ledmode) {
775 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
776 MII_MARVELL_LED_CTRL);
60b86755 777 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
2e55cc72 778
933a27d3
DH		 779 reg &= 0xf8ff;
780 reg |= (1 + 0x0100);
781 asix_mdio_write(dev->net, dev->mii.phy_id,
782 MII_MARVELL_LED_CTRL, reg);
2e55cc72 783
933a27d3
DH		 784 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
785 MII_MARVELL_LED_CTRL);
60b86755 786 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
933a27d3
DH		 787 reg &= 0xfc0f;
788 }
2e55cc72 789
933a27d3
DH		 790 return 0;
791}
792
610d885d
GG		 793static int rtl8211cl_phy_init(struct usbnet *dev)
794{
795 struct asix_data *data = (struct asix_data *)&dev->data;
796
797 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
798
799 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
800 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
801 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
802 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
803 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
804
805 if (data->ledmode == 12) {
806 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
807 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
808 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
809 }
810
811 return 0;
812}
813
933a27d3
DH		 814static int marvell_led_status(struct usbnet *dev, u16 speed)
815{
816 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
817
60b86755 818 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
933a27d3
DH		 819
820 /* Clear out the center LED bits - 0x03F0 */
821 reg &= 0xfc0f;
822
823 switch (speed) {
824 case SPEED_1000:
825 reg |= 0x03e0;
826 break;
827 case SPEED_100:
828 reg |= 0x03b0;
829 break;
830 default:
831 reg |= 0x02f0;
2e55cc72
DB		 832 }
833
60b86755 834 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
933a27d3
DH		 835 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
836
837 return 0;
838}
839
610d885d
GG		 840static int ax88178_reset(struct usbnet *dev)
841{
842 struct asix_data *data = (struct asix_data *)&dev->data;
843 int ret;
844 __le16 eeprom;
845 u8 status;
846 int gpio0 = 0;
b2d3ad29 847 u32 phyid;
610d885d 848
d9fe64e5 849 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
49ae25b0 850 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
610d885d 851
d9fe64e5
RF		 852 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
853 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
854 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
610d885d 855
49ae25b0 856 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
610d885d
GG		 857
858 if (eeprom == cpu_to_le16(0xffff)) {
859 data->phymode = PHY_MODE_MARVELL;
860 data->ledmode = 0;
861 gpio0 = 1;
862 } else {
b2d3ad29 863 data->phymode = le16_to_cpu(eeprom) & 0x7F;
610d885d
GG		 864 data->ledmode = le16_to_cpu(eeprom) >> 8;
865 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
866 }
49ae25b0 867 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
610d885d 868
b2d3ad29 869 /* Power up external GigaPHY through AX88178 GPIO pin */
d9fe64e5
RF		 870 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
871 AX_GPIO_GPO1EN, 40, 0);
610d885d 872 if ((le16_to_cpu(eeprom) >> 8) != 1) {
d9fe64e5
RF		 873 asix_write_gpio(dev, 0x003c, 30, 0);
874 asix_write_gpio(dev, 0x001c, 300, 0);
875 asix_write_gpio(dev, 0x003c, 30, 0);
610d885d 876 } else {
49ae25b0 877 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
d9fe64e5
RF		 878 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
879 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
610d885d
GG		 880 }
881
b2d3ad29
GG		 882 /* Read PHYID register *AFTER* powering up PHY */
883 phyid = asix_get_phyid(dev);
49ae25b0 884 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
b2d3ad29
GG		 885
886 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
d9fe64e5 887 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
b2d3ad29 888
d9fe64e5 889 asix_sw_reset(dev, 0, 0);
610d885d
GG		 890 msleep(150);
891
d9fe64e5 892 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
610d885d
GG		 893 msleep(150);
894
d9fe64e5 895 asix_write_rx_ctl(dev, 0, 0);
610d885d
GG		 896
897 if (data->phymode == PHY_MODE_MARVELL) {
898 marvell_phy_init(dev);
899 msleep(60);
900 } else if (data->phymode == PHY_MODE_RTL8211CL)
901 rtl8211cl_phy_init(dev);
902
903 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
904 BMCR_RESET | BMCR_ANENABLE);
905 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
906 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
907 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
908 ADVERTISE_1000FULL);
909
910 mii_nway_restart(&dev->mii);
911
d9fe64e5 912 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
83e1b918
GG		 913 if (ret < 0)
914 return ret;
610d885d 915
71bc5d94
JK		 916 /* Rewrite MAC address */
917 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
918 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
d9fe64e5 919 data->mac_addr, 0);
71bc5d94
JK		 920 if (ret < 0)
921 return ret;
922
d9fe64e5 923 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
83e1b918
GG		 924 if (ret < 0)
925 return ret;
610d885d
GG		 926
927 return 0;
610d885d
GG		 928}
929
933a27d3
DH		 930static int ax88178_link_reset(struct usbnet *dev)
931{
932 u16 mode;
8ae6daca 933 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
933a27d3 934 struct asix_data *data = (struct asix_data *)&dev->data;
8ae6daca 935 u32 speed;
933a27d3 936
60b86755 937 netdev_dbg(dev->net, "ax88178_link_reset()\n");
933a27d3
DH		 938
939 mii_check_media(&dev->mii, 1, 1);
940 mii_ethtool_gset(&dev->mii, &ecmd);
941 mode = AX88178_MEDIUM_DEFAULT;
8ae6daca 942 speed = ethtool_cmd_speed(&ecmd);
933a27d3 943
8ae6daca 944 if (speed == SPEED_1000)
a7f75c0c 945 mode |= AX_MEDIUM_GM;
8ae6daca 946 else if (speed == SPEED_100)
933a27d3
DH		 947 mode |= AX_MEDIUM_PS;
948 else
949 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
950
a7f75c0c
PK		 951 mode |= AX_MEDIUM_ENCK;
952
933a27d3
DH		 953 if (ecmd.duplex == DUPLEX_FULL)
954 mode |= AX_MEDIUM_FD;
955 else
956 mode &= ~AX_MEDIUM_FD;
957
8ae6daca
DD		 958 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
959 speed, ecmd.duplex, mode);
933a27d3 960
d9fe64e5 961 asix_write_medium_mode(dev, mode, 0);
933a27d3
DH		 962
963 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
8ae6daca 964 marvell_led_status(dev, speed);
933a27d3
DH		 965
966 return 0;
967}
968
969static void ax88178_set_mfb(struct usbnet *dev)
970{
971 u16 mfb = AX_RX_CTL_MFB_16384;
972 u16 rxctl;
973 u16 medium;
974 int old_rx_urb_size = dev->rx_urb_size;
975
976 if (dev->hard_mtu < 2048) {
977 dev->rx_urb_size = 2048;
978 mfb = AX_RX_CTL_MFB_2048;
979 } else if (dev->hard_mtu < 4096) {
980 dev->rx_urb_size = 4096;
981 mfb = AX_RX_CTL_MFB_4096;
982 } else if (dev->hard_mtu < 8192) {
983 dev->rx_urb_size = 8192;
984 mfb = AX_RX_CTL_MFB_8192;
985 } else if (dev->hard_mtu < 16384) {
986 dev->rx_urb_size = 16384;
987 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 988 }
933a27d3 989
d9fe64e5
RF		 990 rxctl = asix_read_rx_ctl(dev, 0);
991 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
933a27d3 992
d9fe64e5 993 medium = asix_read_medium_status(dev, 0);
933a27d3
DH		 994 if (dev->net->mtu > 1500)
995 medium |= AX_MEDIUM_JFE;
996 else
997 medium &= ~AX_MEDIUM_JFE;
d9fe64e5 998 asix_write_medium_mode(dev, medium, 0);
933a27d3
DH		 999
1000 if (dev->rx_urb_size > old_rx_urb_size)
1001 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 1002}
1003
933a27d3 1004static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 1005{
933a27d3
DH		 1006 struct usbnet *dev = netdev_priv(net);
1007 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 1008
60b86755 1009 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
2e55cc72 1010
933a27d3
DH		 1011 if (new_mtu <= 0 || ll_mtu > 16384)
1012 return -EINVAL;
1013
1014 if ((ll_mtu % dev->maxpacket) == 0)
1015 return -EDOM;
1016
1017 net->mtu = new_mtu;
1018 dev->hard_mtu = net->mtu + net->hard_header_len;
1019 ax88178_set_mfb(dev);
1020
a88c32ae
ML		 1021 /* max qlen depend on hard_mtu and rx_urb_size */
1022 usbnet_update_max_qlen(dev);
1023
933a27d3
DH		 1024 return 0;
1025}
1026
1703338c
SH		 1027static const struct net_device_ops ax88178_netdev_ops = {
1028 .ndo_open = usbnet_open,
1029 .ndo_stop = usbnet_stop,
1030 .ndo_start_xmit = usbnet_start_xmit,
1031 .ndo_tx_timeout = usbnet_tx_timeout,
7f29a3ba 1032 .ndo_set_mac_address = asix_set_mac_address,
1703338c 1033 .ndo_validate_addr = eth_validate_addr,
afc4b13d 1034 .ndo_set_rx_mode = asix_set_multicast,
1703338c
SH		 1035 .ndo_do_ioctl = asix_ioctl,
1036 .ndo_change_mtu = ax88178_change_mtu,
1037};
1038
933a27d3
DH		 1039static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1040{
933a27d3 1041 int ret;
51bf2976 1042 u8 buf[ETH_ALEN];
933a27d3
DH		 1043
1044 usbnet_get_endpoints(dev,intf);
1045
933a27d3 1046 /* Get the MAC address */
d9fe64e5 1047 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
83e1b918 1048 if (ret < 0) {
49ae25b0 1049 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
83e1b918 1050 return ret;
2e55cc72 1051 }
452b5ecd
JCPV		 1052
1053 asix_set_netdev_dev_addr(dev, buf);
2e55cc72 1054
933a27d3
DH		 1055 /* Initialize MII structure */
1056 dev->mii.dev = dev->net;
1057 dev->mii.mdio_read = asix_mdio_read;
1058 dev->mii.mdio_write = asix_mdio_write;
1059 dev->mii.phy_id_mask = 0x1f;
1060 dev->mii.reg_num_mask = 0xff;
1061 dev->mii.supports_gmii = 1;
933a27d3 1062 dev->mii.phy_id = asix_get_phy_addr(dev);
1703338c
SH		 1063
1064 dev->net->netdev_ops = &ax88178_netdev_ops;
933a27d3 1065 dev->net->ethtool_ops = &ax88178_ethtool_ops;
2e55cc72 1066
b2d3ad29 1067 /* Blink LEDS so users know driver saw dongle */
d9fe64e5 1068 asix_sw_reset(dev, 0, 0);
b2d3ad29 1069 msleep(150);
2e55cc72 1070
d9fe64e5 1071 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
b2d3ad29 1072 msleep(150);
933a27d3
DH		 1073
1074 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1075 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1076 /* hard_mtu is still the default - the device does not support
1077 jumbo eth frames */
1078 dev->rx_urb_size = 2048;
1079 }
933a27d3 1080
8b5b6f54
LS		 1081 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1082 if (!dev->driver_priv)
1083 return -ENOMEM;
1084
83e1b918 1085 return 0;
2e55cc72
DB		 1086}
1087
1088static const struct driver_info ax8817x_info = {
1089 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 1090 .bind = ax88172_bind,
1091 .status = asix_status,
2e55cc72
DB		 1092 .link_reset = ax88172_link_reset,
1093 .reset = ax88172_link_reset,
37e8273c 1094 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1095 .data = 0x00130103,
1096};
1097
1098static const struct driver_info dlink_dub_e100_info = {
1099 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 1100 .bind = ax88172_bind,
1101 .status = asix_status,
2e55cc72
DB		 1102 .link_reset = ax88172_link_reset,
1103 .reset = ax88172_link_reset,
37e8273c 1104 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1105 .data = 0x009f9d9f,
1106};
1107
1108static const struct driver_info netgear_fa120_info = {
1109 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 1110 .bind = ax88172_bind,
1111 .status = asix_status,
2e55cc72
DB		 1112 .link_reset = ax88172_link_reset,
1113 .reset = ax88172_link_reset,
37e8273c 1114 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1115 .data = 0x00130103,
1116};
1117
1118static const struct driver_info hawking_uf200_info = {
1119 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 1120 .bind = ax88172_bind,
1121 .status = asix_status,
2e55cc72
DB		 1122 .link_reset = ax88172_link_reset,
1123 .reset = ax88172_link_reset,
37e8273c 1124 .flags = FLAG_ETHER | FLAG_LINK_INTR,
2e55cc72
DB		 1125 .data = 0x001f1d1f,
1126};
1127
1128static const struct driver_info ax88772_info = {
1129 .description = "ASIX AX88772 USB 2.0 Ethernet",
1130 .bind = ax88772_bind,
8b5b6f54 1131 .unbind = ax88772_unbind,
48b1be6a 1132 .status = asix_status,
2e55cc72 1133 .link_reset = ax88772_link_reset,
d9fe64e5 1134 .reset = ax88772_reset,
a9e0aca4 1135 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
8b5b6f54 1136 .rx_fixup = asix_rx_fixup_common,
933a27d3
DH		 1137 .tx_fixup = asix_tx_fixup,
1138};
1139
5620df65
LS		 1140static const struct driver_info ax88772b_info = {
1141 .description = "ASIX AX88772B USB 2.0 Ethernet",
1142 .bind = ax88772_bind,
8b5b6f54 1143 .unbind = ax88772_unbind,
5620df65
LS		 1144 .status = asix_status,
1145 .link_reset = ax88772_link_reset,
1146 .reset = ax88772_reset,
1147 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1148 FLAG_MULTI_PACKET,
8b5b6f54 1149 .rx_fixup = asix_rx_fixup_common,
5620df65
LS		 1150 .tx_fixup = asix_tx_fixup,
1151 .data = FLAG_EEPROM_MAC,
1152};
1153
933a27d3
DH		 1154static const struct driver_info ax88178_info = {
1155 .description = "ASIX AX88178 USB 2.0 Ethernet",
1156 .bind = ax88178_bind,
8b5b6f54 1157 .unbind = ax88772_unbind,
933a27d3
DH		 1158 .status = asix_status,
1159 .link_reset = ax88178_link_reset,
610d885d 1160 .reset = ax88178_reset,
d43ff4cd
EG		 1161 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1162 FLAG_MULTI_PACKET,
8b5b6f54 1163 .rx_fixup = asix_rx_fixup_common,
933a27d3 1164 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 1165};
1166
45af3fb4
GT		 1167/*
1168 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1169 * no-name packaging.
1170 * USB device strings are:
1171 * 1: Manufacturer: USBLINK
1172 * 2: Product: HG20F9 USB2.0
1173 * 3: Serial: 000003
1174 * Appears to be compatible with Asix 88772B.
1175 */
1176static const struct driver_info hg20f9_info = {
1177 .description = "HG20F9 USB 2.0 Ethernet",
1178 .bind = ax88772_bind,
1179 .unbind = ax88772_unbind,
1180 .status = asix_status,
1181 .link_reset = ax88772_link_reset,
1182 .reset = ax88772_reset,
1183 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1184 FLAG_MULTI_PACKET,
1185 .rx_fixup = asix_rx_fixup_common,
1186 .tx_fixup = asix_tx_fixup,
1187 .data = FLAG_EEPROM_MAC,
1188};
1189
2e55cc72
DB		 1190static const struct usb_device_id products [] = {
1191{
1192 // Linksys USB200M
1193 USB_DEVICE (0x077b, 0x2226),
1194 .driver_info = (unsigned long) &ax8817x_info,
1195}, {
1196 // Netgear FA120
1197 USB_DEVICE (0x0846, 0x1040),
1198 .driver_info = (unsigned long) &netgear_fa120_info,
1199}, {
1200 // DLink DUB-E100
1201 USB_DEVICE (0x2001, 0x1a00),
1202 .driver_info = (unsigned long) &dlink_dub_e100_info,
1203}, {
1204 // Intellinet, ST Lab USB Ethernet
1205 USB_DEVICE (0x0b95, 0x1720),
1206 .driver_info = (unsigned long) &ax8817x_info,
1207}, {
1208 // Hawking UF200, TrendNet TU2-ET100
1209 USB_DEVICE (0x07b8, 0x420a),
1210 .driver_info = (unsigned long) &hawking_uf200_info,
1211}, {
39c4b38c
DH		 1212 // Billionton Systems, USB2AR
1213 USB_DEVICE (0x08dd, 0x90ff),
1214 .driver_info = (unsigned long) &ax8817x_info,
80083a3c
CSC		 1215}, {
1216 // Billionton Systems, GUSB2AM-1G-B
1217 USB_DEVICE(0x08dd, 0x0114),
1218 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1219}, {
1220 // ATEN UC210T
1221 USB_DEVICE (0x0557, 0x2009),
1222 .driver_info = (unsigned long) &ax8817x_info,
1223}, {
1224 // Buffalo LUA-U2-KTX
1225 USB_DEVICE (0x0411, 0x003d),
1226 .driver_info = (unsigned long) &ax8817x_info,
ac7b77f1
MD		 1227}, {
1228 // Buffalo LUA-U2-GT 10/100/1000
1229 USB_DEVICE (0x0411, 0x006e),
1230 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1231}, {
1232 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1233 USB_DEVICE (0x6189, 0x182d),
1234 .driver_info = (unsigned long) &ax8817x_info,
4e503919
JN		 1235}, {
1236 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1237 USB_DEVICE (0x0df6, 0x0056),
1238 .driver_info = (unsigned long) &ax88178_info,
7488c3e3
LC		 1239}, {
1240 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1241 USB_DEVICE (0x0df6, 0x061c),
1242 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1243}, {
1244 // corega FEther USB2-TX
1245 USB_DEVICE (0x07aa, 0x0017),
1246 .driver_info = (unsigned long) &ax8817x_info,
1247}, {
1248 // Surecom EP-1427X-2
1249 USB_DEVICE (0x1189, 0x0893),
1250 .driver_info = (unsigned long) &ax8817x_info,
1251}, {
1252 // goodway corp usb gwusb2e
1253 USB_DEVICE (0x1631, 0x6200),
1254 .driver_info = (unsigned long) &ax8817x_info,
39c4b38c
DH		 1255}, {
1256 // JVC MP-PRX1 Port Replicator
1257 USB_DEVICE (0x04f1, 0x3008),
1258 .driver_info = (unsigned long) &ax8817x_info,
66dc81ec
QP		 1259}, {
1260 // Lenovo U2L100P 10/100
1261 USB_DEVICE (0x17ef, 0x7203),
d9fe64e5 1262 .driver_info = (unsigned long)&ax88772b_info,
30885909
MV		 1263}, {
1264 // ASIX AX88772B 10/100
1265 USB_DEVICE (0x0b95, 0x772b),
5620df65 1266 .driver_info = (unsigned long) &ax88772b_info,
2e55cc72
DB		 1267}, {
1268 // ASIX AX88772 10/100
39c4b38c
DH		 1269 USB_DEVICE (0x0b95, 0x7720),
1270 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 1271}, {
1272 // ASIX AX88178 10/100/1000
1273 USB_DEVICE (0x0b95, 0x1780),
933a27d3 1274 .driver_info = (unsigned long) &ax88178_info,
f4680d3d
AE		 1275}, {
1276 // Logitec LAN-GTJ/U2A
1277 USB_DEVICE (0x0789, 0x0160),
1278 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 1279}, {
1280 // Linksys USB200M Rev 2
1281 USB_DEVICE (0x13b1, 0x0018),
1282 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 1283}, {
1284 // 0Q0 cable ethernet
1285 USB_DEVICE (0x1557, 0x7720),
1286 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1287}, {
1288 // DLink DUB-E100 H/W Ver B1
1289 USB_DEVICE (0x07d1, 0x3c05),
1290 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 1291}, {
1292 // DLink DUB-E100 H/W Ver B1 Alternate
1293 USB_DEVICE (0x2001, 0x3c05),
1294 .driver_info = (unsigned long) &ax88772_info,
ed3770a9
S		 1295}, {
1296 // DLink DUB-E100 H/W Ver C1
1297 USB_DEVICE (0x2001, 0x1a02),
1298 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1299}, {
1300 // Linksys USB1000
1301 USB_DEVICE (0x1737, 0x0039),
1302 .driver_info = (unsigned long) &ax88178_info,
b29cf31d
YH		 1303}, {
1304 // IO-DATA ETG-US2
1305 USB_DEVICE (0x04bb, 0x0930),
1306 .driver_info = (unsigned long) &ax88178_info,
2ed22bc2
DH		 1307}, {
1308 // Belkin F5D5055
1309 USB_DEVICE(0x050d, 0x5055),
1310 .driver_info = (unsigned long) &ax88178_info,
3d60efb5
AN		 1311}, {
1312 // Apple USB Ethernet Adapter
1313 USB_DEVICE(0x05ac, 0x1402),
1314 .driver_info = (unsigned long) &ax88772_info,
ccf95402
JC		 1315}, {
1316 // Cables-to-Go USB Ethernet Adapter
1317 USB_DEVICE(0x0b95, 0x772a),
1318 .driver_info = (unsigned long) &ax88772_info,
fef7cc08
GKH		 1319}, {
1320 // ABOCOM for pci
1321 USB_DEVICE(0x14ea, 0xab11),
1322 .driver_info = (unsigned long) &ax88178_info,
1323}, {
1324 // ASIX 88772a
1325 USB_DEVICE(0x0db0, 0xa877),
1326 .driver_info = (unsigned long) &ax88772_info,
e8303a3b
AJ		 1327}, {
1328 // Asus USB Ethernet Adapter
1329 USB_DEVICE (0x0b95, 0x7e2b),
d9fe64e5 1330 .driver_info = (unsigned long)&ax88772b_info,
16626b0c
CR		 1331}, {
1332 /* ASIX 88172a demo board */
1333 USB_DEVICE(0x0b95, 0x172a),
1334 .driver_info = (unsigned long) &ax88172a_info,
45af3fb4
GT		 1335}, {
1336 /*
1337 * USBLINK HG20F9 "USB 2.0 LAN"
1338 * Appears to have gazumped Linksys's manufacturer ID but
1339 * doesn't (yet) conflict with any known Linksys product.
1340 */
1341 USB_DEVICE(0x066b, 0x20f9),
1342 .driver_info = (unsigned long) &hg20f9_info,
2e55cc72
DB		 1343},
1344 { }, // END
1345};
1346MODULE_DEVICE_TABLE(usb, products);
1347
1348static struct usb_driver asix_driver = {
83e1b918 1349 .name = DRIVER_NAME,
2e55cc72
DB		 1350 .id_table = products,
1351 .probe = usbnet_probe,
d9fe64e5
RF		 1352 .suspend = asix_suspend,
1353 .resume = asix_resume,
2e55cc72 1354 .disconnect = usbnet_disconnect,
a11a6544 1355 .supports_autosuspend = 1,
e1f12eb6 1356 .disable_hub_initiated_lpm = 1,
2e55cc72
DB		 1357};
1358
d632eb1b 1359module_usb_driver(asix_driver);
2e55cc72
DB		 1360
1361MODULE_AUTHOR("David Hollis");
4ad1438f 1362MODULE_VERSION(DRIVER_VERSION);
2e55cc72
DB		 1363MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1364MODULE_LICENSE("GPL");
1365
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