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ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
d9a28c5b 27#include <linux/usb/cdc.h>
5ee3c60c 28#include <linux/suspend.h>
34ee32c9 29#include <linux/acpi.h>
ac718b69 30
d0942473 31/* Information for net-next */
32#define NETNEXT_VERSION "08"
33
34/* Information for net */
b20cb60e 35#define NET_VERSION "9"
d0942473 36
37#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
ac718b69 38#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 39#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 40#define MODULENAME "r8152"
41
42#define R8152_PHY_ID 32
43
44#define PLA_IDR 0xc000
45#define PLA_RCR 0xc010
46#define PLA_RMS 0xc016
47#define PLA_RXFIFO_CTRL0 0xc0a0
48#define PLA_RXFIFO_CTRL1 0xc0a4
49#define PLA_RXFIFO_CTRL2 0xc0a8
65bab84c 50#define PLA_DMY_REG0 0xc0b0
ac718b69 51#define PLA_FMC 0xc0b4
52#define PLA_CFG_WOL 0xc0b6
43779f8d 53#define PLA_TEREDO_CFG 0xc0bc
ac718b69 54#define PLA_MAR 0xcd00
43779f8d 55#define PLA_BACKUP 0xd000
ac718b69 56#define PAL_BDC_CR 0xd1a0
43779f8d 57#define PLA_TEREDO_TIMER 0xd2cc
58#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 59#define PLA_LEDSEL 0xdd90
60#define PLA_LED_FEATURE 0xdd92
61#define PLA_PHYAR 0xde00
43779f8d 62#define PLA_BOOT_CTRL 0xe004
ac718b69 63#define PLA_GPHY_INTR_IMR 0xe022
64#define PLA_EEE_CR 0xe040
65#define PLA_EEEP_CR 0xe080
66#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 67#define PLA_MAC_PWR_CTRL2 0xe0ca
68#define PLA_MAC_PWR_CTRL3 0xe0cc
69#define PLA_MAC_PWR_CTRL4 0xe0ce
70#define PLA_WDT6_CTRL 0xe428
ac718b69 71#define PLA_TCR0 0xe610
72#define PLA_TCR1 0xe612
69b4b7a4 73#define PLA_MTPS 0xe615
ac718b69 74#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 75#define PLA_RSTTALLY 0xe800
ac718b69 76#define PLA_CR 0xe813
77#define PLA_CRWECR 0xe81c
21ff2e89 78#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
79#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 80#define PLA_CONFIG5 0xe822
81#define PLA_PHY_PWR 0xe84c
82#define PLA_OOB_CTRL 0xe84f
83#define PLA_CPCR 0xe854
84#define PLA_MISC_0 0xe858
85#define PLA_MISC_1 0xe85a
86#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 87#define PLA_TALLYCNT 0xe890
ac718b69 88#define PLA_SFF_STS_7 0xe8de
89#define PLA_PHYSTATUS 0xe908
90#define PLA_BP_BA 0xfc26
91#define PLA_BP_0 0xfc28
92#define PLA_BP_1 0xfc2a
93#define PLA_BP_2 0xfc2c
94#define PLA_BP_3 0xfc2e
95#define PLA_BP_4 0xfc30
96#define PLA_BP_5 0xfc32
97#define PLA_BP_6 0xfc34
98#define PLA_BP_7 0xfc36
43779f8d 99#define PLA_BP_EN 0xfc38
ac718b69 100
65bab84c 101#define USB_USB2PHY 0xb41e
102#define USB_SSPHYLINK2 0xb428
43779f8d 103#define USB_U2P3_CTRL 0xb460
65bab84c 104#define USB_CSR_DUMMY1 0xb464
105#define USB_CSR_DUMMY2 0xb466
ac718b69 106#define USB_DEV_STAT 0xb808
65bab84c 107#define USB_CONNECT_TIMER 0xcbf8
108#define USB_BURST_SIZE 0xcfc0
ac718b69 109#define USB_USB_CTRL 0xd406
110#define USB_PHY_CTRL 0xd408
111#define USB_TX_AGG 0xd40a
112#define USB_RX_BUF_TH 0xd40c
113#define USB_USB_TIMER 0xd428
464ec10a 114#define USB_RX_EARLY_TIMEOUT 0xd42c
115#define USB_RX_EARLY_SIZE 0xd42e
ac718b69 116#define USB_PM_CTRL_STATUS 0xd432
117#define USB_TX_DMA 0xd434
43779f8d 118#define USB_TOLERANCE 0xd490
119#define USB_LPM_CTRL 0xd41a
93fe9b18 120#define USB_BMU_RESET 0xd4b0
ac718b69 121#define USB_UPS_CTRL 0xd800
43779f8d 122#define USB_MISC_0 0xd81a
123#define USB_POWER_CUT 0xd80a
124#define USB_AFE_CTRL2 0xd824
125#define USB_WDT11_CTRL 0xe43c
ac718b69 126#define USB_BP_BA 0xfc26
127#define USB_BP_0 0xfc28
128#define USB_BP_1 0xfc2a
129#define USB_BP_2 0xfc2c
130#define USB_BP_3 0xfc2e
131#define USB_BP_4 0xfc30
132#define USB_BP_5 0xfc32
133#define USB_BP_6 0xfc34
134#define USB_BP_7 0xfc36
43779f8d 135#define USB_BP_EN 0xfc38
ac718b69 136
137/* OCP Registers */
138#define OCP_ALDPS_CONFIG 0x2010
139#define OCP_EEE_CONFIG1 0x2080
140#define OCP_EEE_CONFIG2 0x2092
141#define OCP_EEE_CONFIG3 0x2094
ac244d3e 142#define OCP_BASE_MII 0xa400
ac718b69 143#define OCP_EEE_AR 0xa41a
144#define OCP_EEE_DATA 0xa41c
43779f8d 145#define OCP_PHY_STATUS 0xa420
146#define OCP_POWER_CFG 0xa430
147#define OCP_EEE_CFG 0xa432
148#define OCP_SRAM_ADDR 0xa436
149#define OCP_SRAM_DATA 0xa438
150#define OCP_DOWN_SPEED 0xa442
df35d283 151#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 152#define OCP_EEE_ADV 0xa5d0
df35d283 153#define OCP_EEE_LPABLE 0xa5d2
2dd49e0f 154#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
43779f8d 155#define OCP_ADC_CFG 0xbc06
156
157/* SRAM Register */
158#define SRAM_LPF_CFG 0x8012
159#define SRAM_10M_AMP1 0x8080
160#define SRAM_10M_AMP2 0x8082
161#define SRAM_IMPEDANCE 0x8084
ac718b69 162
163/* PLA_RCR */
164#define RCR_AAP 0x00000001
165#define RCR_APM 0x00000002
166#define RCR_AM 0x00000004
167#define RCR_AB 0x00000008
168#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
169
170/* PLA_RXFIFO_CTRL0 */
171#define RXFIFO_THR1_NORMAL 0x00080002
172#define RXFIFO_THR1_OOB 0x01800003
173
174/* PLA_RXFIFO_CTRL1 */
175#define RXFIFO_THR2_FULL 0x00000060
176#define RXFIFO_THR2_HIGH 0x00000038
177#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 178#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 179
180/* PLA_RXFIFO_CTRL2 */
181#define RXFIFO_THR3_FULL 0x00000078
182#define RXFIFO_THR3_HIGH 0x00000048
183#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 184#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 185
186/* PLA_TXFIFO_CTRL */
187#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 188#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 189
65bab84c 190/* PLA_DMY_REG0 */
191#define ECM_ALDPS 0x0002
192
ac718b69 193/* PLA_FMC */
194#define FMC_FCR_MCU_EN 0x0001
195
196/* PLA_EEEP_CR */
197#define EEEP_CR_EEEP_TX 0x0002
198
43779f8d 199/* PLA_WDT6_CTRL */
200#define WDT6_SET_MODE 0x0010
201
ac718b69 202/* PLA_TCR0 */
203#define TCR0_TX_EMPTY 0x0800
204#define TCR0_AUTO_FIFO 0x0080
205
206/* PLA_TCR1 */
207#define VERSION_MASK 0x7cf0
208
69b4b7a4 209/* PLA_MTPS */
210#define MTPS_JUMBO (12 * 1024 / 64)
211#define MTPS_DEFAULT (6 * 1024 / 64)
212
4f1d4d54 213/* PLA_RSTTALLY */
214#define TALLY_RESET 0x0001
215
ac718b69 216/* PLA_CR */
217#define CR_RST 0x10
218#define CR_RE 0x08
219#define CR_TE 0x04
220
221/* PLA_CRWECR */
222#define CRWECR_NORAML 0x00
223#define CRWECR_CONFIG 0xc0
224
225/* PLA_OOB_CTRL */
226#define NOW_IS_OOB 0x80
227#define TXFIFO_EMPTY 0x20
228#define RXFIFO_EMPTY 0x10
229#define LINK_LIST_READY 0x02
230#define DIS_MCU_CLROOB 0x01
231#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
232
233/* PLA_MISC_1 */
234#define RXDY_GATED_EN 0x0008
235
236/* PLA_SFF_STS_7 */
237#define RE_INIT_LL 0x8000
238#define MCU_BORW_EN 0x4000
239
240/* PLA_CPCR */
241#define CPCR_RX_VLAN 0x0040
242
243/* PLA_CFG_WOL */
244#define MAGIC_EN 0x0001
245
43779f8d 246/* PLA_TEREDO_CFG */
247#define TEREDO_SEL 0x8000
248#define TEREDO_WAKE_MASK 0x7f00
249#define TEREDO_RS_EVENT_MASK 0x00fe
250#define OOB_TEREDO_EN 0x0001
251
ac718b69 252/* PAL_BDC_CR */
253#define ALDPS_PROXY_MODE 0x0001
254
21ff2e89 255/* PLA_CONFIG34 */
256#define LINK_ON_WAKE_EN 0x0010
257#define LINK_OFF_WAKE_EN 0x0008
258
ac718b69 259/* PLA_CONFIG5 */
21ff2e89 260#define BWF_EN 0x0040
261#define MWF_EN 0x0020
262#define UWF_EN 0x0010
ac718b69 263#define LAN_WAKE_EN 0x0002
264
265/* PLA_LED_FEATURE */
266#define LED_MODE_MASK 0x0700
267
268/* PLA_PHY_PWR */
269#define TX_10M_IDLE_EN 0x0080
270#define PFM_PWM_SWITCH 0x0040
271
272/* PLA_MAC_PWR_CTRL */
273#define D3_CLK_GATED_EN 0x00004000
274#define MCU_CLK_RATIO 0x07010f07
275#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 276#define ALDPS_SPDWN_RATIO 0x0f87
277
278/* PLA_MAC_PWR_CTRL2 */
279#define EEE_SPDWN_RATIO 0x8007
280
281/* PLA_MAC_PWR_CTRL3 */
282#define PKT_AVAIL_SPDWN_EN 0x0100
283#define SUSPEND_SPDWN_EN 0x0004
284#define U1U2_SPDWN_EN 0x0002
285#define L1_SPDWN_EN 0x0001
286
287/* PLA_MAC_PWR_CTRL4 */
288#define PWRSAVE_SPDWN_EN 0x1000
289#define RXDV_SPDWN_EN 0x0800
290#define TX10MIDLE_EN 0x0100
291#define TP100_SPDWN_EN 0x0020
292#define TP500_SPDWN_EN 0x0010
293#define TP1000_SPDWN_EN 0x0008
294#define EEE_SPDWN_EN 0x0001
ac718b69 295
296/* PLA_GPHY_INTR_IMR */
297#define GPHY_STS_MSK 0x0001
298#define SPEED_DOWN_MSK 0x0002
299#define SPDWN_RXDV_MSK 0x0004
300#define SPDWN_LINKCHG_MSK 0x0008
301
302/* PLA_PHYAR */
303#define PHYAR_FLAG 0x80000000
304
305/* PLA_EEE_CR */
306#define EEE_RX_EN 0x0001
307#define EEE_TX_EN 0x0002
308
43779f8d 309/* PLA_BOOT_CTRL */
310#define AUTOLOAD_DONE 0x0002
311
65bab84c 312/* USB_USB2PHY */
313#define USB2PHY_SUSPEND 0x0001
314#define USB2PHY_L1 0x0002
315
316/* USB_SSPHYLINK2 */
317#define pwd_dn_scale_mask 0x3ffe
318#define pwd_dn_scale(x) ((x) << 1)
319
320/* USB_CSR_DUMMY1 */
321#define DYNAMIC_BURST 0x0001
322
323/* USB_CSR_DUMMY2 */
324#define EP4_FULL_FC 0x0001
325
ac718b69 326/* USB_DEV_STAT */
327#define STAT_SPEED_MASK 0x0006
328#define STAT_SPEED_HIGH 0x0000
a3cc465d 329#define STAT_SPEED_FULL 0x0002
ac718b69 330
331/* USB_TX_AGG */
332#define TX_AGG_MAX_THRESHOLD 0x03
333
334/* USB_RX_BUF_TH */
43779f8d 335#define RX_THR_SUPPER 0x0c350180
8e1f51bd 336#define RX_THR_HIGH 0x7a120180
43779f8d 337#define RX_THR_SLOW 0xffff0180
ac718b69 338
339/* USB_TX_DMA */
340#define TEST_MODE_DISABLE 0x00000001
341#define TX_SIZE_ADJUST1 0x00000100
342
93fe9b18 343/* USB_BMU_RESET */
344#define BMU_RESET_EP_IN 0x01
345#define BMU_RESET_EP_OUT 0x02
346
ac718b69 347/* USB_UPS_CTRL */
348#define POWER_CUT 0x0100
349
350/* USB_PM_CTRL_STATUS */
8e1f51bd 351#define RESUME_INDICATE 0x0001
ac718b69 352
353/* USB_USB_CTRL */
354#define RX_AGG_DISABLE 0x0010
e90fba8d 355#define RX_ZERO_EN 0x0080
ac718b69 356
43779f8d 357/* USB_U2P3_CTRL */
358#define U2P3_ENABLE 0x0001
359
360/* USB_POWER_CUT */
361#define PWR_EN 0x0001
362#define PHASE2_EN 0x0008
363
364/* USB_MISC_0 */
365#define PCUT_STATUS 0x0001
366
464ec10a 367/* USB_RX_EARLY_TIMEOUT */
368#define COALESCE_SUPER 85000U
369#define COALESCE_HIGH 250000U
370#define COALESCE_SLOW 524280U
43779f8d 371
372/* USB_WDT11_CTRL */
373#define TIMER11_EN 0x0001
374
375/* USB_LPM_CTRL */
65bab84c 376/* bit 4 ~ 5: fifo empty boundary */
377#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
378/* bit 2 ~ 3: LMP timer */
43779f8d 379#define LPM_TIMER_MASK 0x0c
380#define LPM_TIMER_500MS 0x04 /* 500 ms */
381#define LPM_TIMER_500US 0x0c /* 500 us */
65bab84c 382#define ROK_EXIT_LPM 0x02
43779f8d 383
384/* USB_AFE_CTRL2 */
385#define SEN_VAL_MASK 0xf800
386#define SEN_VAL_NORMAL 0xa000
387#define SEL_RXIDLE 0x0100
388
ac718b69 389/* OCP_ALDPS_CONFIG */
390#define ENPWRSAVE 0x8000
391#define ENPDNPS 0x0200
392#define LINKENA 0x0100
393#define DIS_SDSAVE 0x0010
394
43779f8d 395/* OCP_PHY_STATUS */
396#define PHY_STAT_MASK 0x0007
397#define PHY_STAT_LAN_ON 3
398#define PHY_STAT_PWRDN 5
399
400/* OCP_POWER_CFG */
401#define EEE_CLKDIV_EN 0x8000
402#define EN_ALDPS 0x0004
403#define EN_10M_PLLOFF 0x0001
404
ac718b69 405/* OCP_EEE_CONFIG1 */
406#define RG_TXLPI_MSK_HFDUP 0x8000
407#define RG_MATCLR_EN 0x4000
408#define EEE_10_CAP 0x2000
409#define EEE_NWAY_EN 0x1000
410#define TX_QUIET_EN 0x0200
411#define RX_QUIET_EN 0x0100
d24f6134 412#define sd_rise_time_mask 0x0070
4c4a6b1b 413#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 414#define RG_RXLPI_MSK_HFDUP 0x0008
415#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
416
417/* OCP_EEE_CONFIG2 */
418#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
419#define RG_DACQUIET_EN 0x0400
420#define RG_LDVQUIET_EN 0x0200
421#define RG_CKRSEL 0x0020
422#define RG_EEEPRG_EN 0x0010
423
424/* OCP_EEE_CONFIG3 */
d24f6134 425#define fast_snr_mask 0xff80
4c4a6b1b 426#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 427#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
428#define MSK_PH 0x0006 /* bit 0 ~ 3 */
429
430/* OCP_EEE_AR */
431/* bit[15:14] function */
432#define FUN_ADDR 0x0000
433#define FUN_DATA 0x4000
434/* bit[4:0] device addr */
ac718b69 435
43779f8d 436/* OCP_EEE_CFG */
437#define CTAP_SHORT_EN 0x0040
438#define EEE10_EN 0x0010
439
440/* OCP_DOWN_SPEED */
441#define EN_10M_BGOFF 0x0080
442
2dd49e0f 443/* OCP_PHY_STATE */
444#define TXDIS_STATE 0x01
445#define ABD_STATE 0x02
446
43779f8d 447/* OCP_ADC_CFG */
448#define CKADSEL_L 0x0100
449#define ADC_EN 0x0080
450#define EN_EMI_L 0x0040
451
452/* SRAM_LPF_CFG */
453#define LPF_AUTO_TUNE 0x8000
454
455/* SRAM_10M_AMP1 */
456#define GDAC_IB_UPALL 0x0008
457
458/* SRAM_10M_AMP2 */
459#define AMP_DN 0x0200
460
461/* SRAM_IMPEDANCE */
462#define RX_DRIVING_MASK 0x6000
463
34ee32c9
ML
464/* MAC PASSTHRU */
465#define AD_MASK 0xfee0
466#define EFUSE 0xcfdb
467#define PASS_THRU_MASK 0x1
468
ac718b69 469enum rtl_register_content {
43779f8d 470 _1000bps = 0x10,
ac718b69 471 _100bps = 0x08,
472 _10bps = 0x04,
473 LINK_STATUS = 0x02,
474 FULL_DUP = 0x01,
475};
476
1764bcd9 477#define RTL8152_MAX_TX 4
ebc2ec48 478#define RTL8152_MAX_RX 10
40a82917 479#define INTBUFSIZE 2
8e1f51bd 480#define CRC_SIZE 4
481#define TX_ALIGN 4
482#define RX_ALIGN 8
40a82917 483
484#define INTR_LINK 0x0004
ebc2ec48 485
ac718b69 486#define RTL8152_REQT_READ 0xc0
487#define RTL8152_REQT_WRITE 0x40
488#define RTL8152_REQ_GET_REGS 0x05
489#define RTL8152_REQ_SET_REGS 0x05
490
491#define BYTE_EN_DWORD 0xff
492#define BYTE_EN_WORD 0x33
493#define BYTE_EN_BYTE 0x11
494#define BYTE_EN_SIX_BYTES 0x3f
495#define BYTE_EN_START_MASK 0x0f
496#define BYTE_EN_END_MASK 0xf0
497
69b4b7a4 498#define RTL8153_MAX_PACKET 9216 /* 9K */
499#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 500#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 501#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 502#define RTL8152_TX_TIMEOUT (5 * HZ)
d823ab68 503#define RTL8152_NAPI_WEIGHT 64
b20cb60e 504#define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + CRC_SIZE + \
505 sizeof(struct rx_desc) + RX_ALIGN)
ac718b69 506
507/* rtl8152 flags */
508enum rtl8152_flags {
509 RTL8152_UNPLUG = 0,
ac718b69 510 RTL8152_SET_RX_MODE,
40a82917 511 WORK_ENABLE,
512 RTL8152_LINK_CHG,
9a4be1bd 513 SELECTIVE_SUSPEND,
aa66a5f1 514 PHY_RESET,
d823ab68 515 SCHEDULE_NAPI,
ac718b69 516};
517
518/* Define these values to match your device */
519#define VENDOR_ID_REALTEK 0x0bda
43779f8d 520#define VENDOR_ID_SAMSUNG 0x04e8
347eec34 521#define VENDOR_ID_LENOVO 0x17ef
d065c3c1 522#define VENDOR_ID_NVIDIA 0x0955
ac718b69 523
524#define MCU_TYPE_PLA 0x0100
525#define MCU_TYPE_USB 0x0000
526
4f1d4d54 527struct tally_counter {
528 __le64 tx_packets;
529 __le64 rx_packets;
530 __le64 tx_errors;
531 __le32 rx_errors;
532 __le16 rx_missed;
533 __le16 align_errors;
534 __le32 tx_one_collision;
535 __le32 tx_multi_collision;
536 __le64 rx_unicast;
537 __le64 rx_broadcast;
538 __le32 rx_multicast;
539 __le16 tx_aborted;
f37119c5 540 __le16 tx_underrun;
4f1d4d54 541};
542
ac718b69 543struct rx_desc {
500b6d7e 544 __le32 opts1;
ac718b69 545#define RX_LEN_MASK 0x7fff
565cab0a 546
500b6d7e 547 __le32 opts2;
f5aaaa6d 548#define RD_UDP_CS BIT(23)
549#define RD_TCP_CS BIT(22)
550#define RD_IPV6_CS BIT(20)
551#define RD_IPV4_CS BIT(19)
565cab0a 552
500b6d7e 553 __le32 opts3;
f5aaaa6d 554#define IPF BIT(23) /* IP checksum fail */
555#define UDPF BIT(22) /* UDP checksum fail */
556#define TCPF BIT(21) /* TCP checksum fail */
557#define RX_VLAN_TAG BIT(16)
565cab0a 558
500b6d7e 559 __le32 opts4;
560 __le32 opts5;
561 __le32 opts6;
ac718b69 562};
563
564struct tx_desc {
500b6d7e 565 __le32 opts1;
f5aaaa6d 566#define TX_FS BIT(31) /* First segment of a packet */
567#define TX_LS BIT(30) /* Final segment of a packet */
568#define GTSENDV4 BIT(28)
569#define GTSENDV6 BIT(27)
60c89071 570#define GTTCPHO_SHIFT 18
6128d1bb 571#define GTTCPHO_MAX 0x7fU
60c89071 572#define TX_LEN_MAX 0x3ffffU
5bd23881 573
500b6d7e 574 __le32 opts2;
f5aaaa6d 575#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
576#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
577#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
578#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
60c89071 579#define MSS_SHIFT 17
580#define MSS_MAX 0x7ffU
581#define TCPHO_SHIFT 17
6128d1bb 582#define TCPHO_MAX 0x7ffU
f5aaaa6d 583#define TX_VLAN_TAG BIT(16)
ac718b69 584};
585
dff4e8ad 586struct r8152;
587
ebc2ec48 588struct rx_agg {
589 struct list_head list;
590 struct urb *urb;
dff4e8ad 591 struct r8152 *context;
ebc2ec48 592 void *buffer;
593 void *head;
594};
595
596struct tx_agg {
597 struct list_head list;
598 struct urb *urb;
dff4e8ad 599 struct r8152 *context;
ebc2ec48 600 void *buffer;
601 void *head;
602 u32 skb_num;
603 u32 skb_len;
604};
605
ac718b69 606struct r8152 {
607 unsigned long flags;
608 struct usb_device *udev;
d823ab68 609 struct napi_struct napi;
40a82917 610 struct usb_interface *intf;
ac718b69 611 struct net_device *netdev;
40a82917 612 struct urb *intr_urb;
ebc2ec48 613 struct tx_agg tx_info[RTL8152_MAX_TX];
614 struct rx_agg rx_info[RTL8152_MAX_RX];
615 struct list_head rx_done, tx_free;
d823ab68 616 struct sk_buff_head tx_queue, rx_queue;
ebc2ec48 617 spinlock_t rx_lock, tx_lock;
a028a9e0 618 struct delayed_work schedule, hw_phy_work;
ac718b69 619 struct mii_if_info mii;
b5403273 620 struct mutex control; /* use for hw setting */
5ee3c60c 621#ifdef CONFIG_PM_SLEEP
622 struct notifier_block pm_notifier;
623#endif
c81229c9 624
625 struct rtl_ops {
626 void (*init)(struct r8152 *);
627 int (*enable)(struct r8152 *);
628 void (*disable)(struct r8152 *);
7e9da481 629 void (*up)(struct r8152 *);
c81229c9 630 void (*down)(struct r8152 *);
631 void (*unload)(struct r8152 *);
df35d283 632 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
633 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
2dd49e0f 634 bool (*in_nway)(struct r8152 *);
a028a9e0 635 void (*hw_phy_cfg)(struct r8152 *);
2609af19 636 void (*autosuspend_en)(struct r8152 *tp, bool enable);
c81229c9 637 } rtl_ops;
638
40a82917 639 int intr_interval;
21ff2e89 640 u32 saved_wolopts;
ac718b69 641 u32 msg_enable;
dd1b119c 642 u32 tx_qlen;
464ec10a 643 u32 coalesce;
ac718b69 644 u16 ocp_base;
aa7e26b6 645 u16 speed;
40a82917 646 u8 *intr_buff;
ac718b69 647 u8 version;
aa7e26b6 648 u8 duplex;
649 u8 autoneg;
ac718b69 650};
651
652enum rtl_version {
653 RTL_VER_UNKNOWN = 0,
654 RTL_VER_01,
43779f8d 655 RTL_VER_02,
656 RTL_VER_03,
657 RTL_VER_04,
658 RTL_VER_05,
fb02eb4a 659 RTL_VER_06,
43779f8d 660 RTL_VER_MAX
ac718b69 661};
662
60c89071 663enum tx_csum_stat {
664 TX_CSUM_SUCCESS = 0,
665 TX_CSUM_TSO,
666 TX_CSUM_NONE
667};
668
ac718b69 669/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
670 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
671 */
672static const int multicast_filter_limit = 32;
52aec126 673static unsigned int agg_buf_sz = 16384;
ac718b69 674
52aec126 675#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 676 VLAN_ETH_HLEN - VLAN_HLEN)
677
ac718b69 678static
679int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
680{
31787f53 681 int ret;
682 void *tmp;
683
684 tmp = kmalloc(size, GFP_KERNEL);
685 if (!tmp)
686 return -ENOMEM;
687
688 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 689 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
690 value, index, tmp, size, 500);
31787f53 691
692 memcpy(data, tmp, size);
693 kfree(tmp);
694
695 return ret;
ac718b69 696}
697
698static
699int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
700{
31787f53 701 int ret;
702 void *tmp;
703
c4438f03 704 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 705 if (!tmp)
706 return -ENOMEM;
707
31787f53 708 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 709 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
710 value, index, tmp, size, 500);
31787f53 711
712 kfree(tmp);
db8515ef 713
31787f53 714 return ret;
ac718b69 715}
716
717static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 718 void *data, u16 type)
ac718b69 719{
45f4a19f 720 u16 limit = 64;
721 int ret = 0;
ac718b69 722
723 if (test_bit(RTL8152_UNPLUG, &tp->flags))
724 return -ENODEV;
725
726 /* both size and indix must be 4 bytes align */
727 if ((size & 3) || !size || (index & 3) || !data)
728 return -EPERM;
729
730 if ((u32)index + (u32)size > 0xffff)
731 return -EPERM;
732
733 while (size) {
734 if (size > limit) {
735 ret = get_registers(tp, index, type, limit, data);
736 if (ret < 0)
737 break;
738
739 index += limit;
740 data += limit;
741 size -= limit;
742 } else {
743 ret = get_registers(tp, index, type, size, data);
744 if (ret < 0)
745 break;
746
747 index += size;
748 data += size;
749 size = 0;
750 break;
751 }
752 }
753
67610496 754 if (ret == -ENODEV)
755 set_bit(RTL8152_UNPLUG, &tp->flags);
756
ac718b69 757 return ret;
758}
759
760static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 761 u16 size, void *data, u16 type)
ac718b69 762{
45f4a19f 763 int ret;
764 u16 byteen_start, byteen_end, byen;
765 u16 limit = 512;
ac718b69 766
767 if (test_bit(RTL8152_UNPLUG, &tp->flags))
768 return -ENODEV;
769
770 /* both size and indix must be 4 bytes align */
771 if ((size & 3) || !size || (index & 3) || !data)
772 return -EPERM;
773
774 if ((u32)index + (u32)size > 0xffff)
775 return -EPERM;
776
777 byteen_start = byteen & BYTE_EN_START_MASK;
778 byteen_end = byteen & BYTE_EN_END_MASK;
779
780 byen = byteen_start | (byteen_start << 4);
781 ret = set_registers(tp, index, type | byen, 4, data);
782 if (ret < 0)
783 goto error1;
784
785 index += 4;
786 data += 4;
787 size -= 4;
788
789 if (size) {
790 size -= 4;
791
792 while (size) {
793 if (size > limit) {
794 ret = set_registers(tp, index,
b209af99 795 type | BYTE_EN_DWORD,
796 limit, data);
ac718b69 797 if (ret < 0)
798 goto error1;
799
800 index += limit;
801 data += limit;
802 size -= limit;
803 } else {
804 ret = set_registers(tp, index,
b209af99 805 type | BYTE_EN_DWORD,
806 size, data);
ac718b69 807 if (ret < 0)
808 goto error1;
809
810 index += size;
811 data += size;
812 size = 0;
813 break;
814 }
815 }
816
817 byen = byteen_end | (byteen_end >> 4);
818 ret = set_registers(tp, index, type | byen, 4, data);
819 if (ret < 0)
820 goto error1;
821 }
822
823error1:
67610496 824 if (ret == -ENODEV)
825 set_bit(RTL8152_UNPLUG, &tp->flags);
826
ac718b69 827 return ret;
828}
829
830static inline
831int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
832{
833 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
834}
835
836static inline
837int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
838{
839 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
840}
841
842static inline
843int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
844{
845 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
846}
847
848static inline
849int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
850{
851 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
852}
853
854static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
855{
c8826de8 856 __le32 data;
ac718b69 857
c8826de8 858 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 859
860 return __le32_to_cpu(data);
861}
862
863static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
864{
c8826de8 865 __le32 tmp = __cpu_to_le32(data);
866
867 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 868}
869
870static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
871{
872 u32 data;
c8826de8 873 __le32 tmp;
ac718b69 874 u8 shift = index & 2;
875
876 index &= ~3;
877
c8826de8 878 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 879
c8826de8 880 data = __le32_to_cpu(tmp);
ac718b69 881 data >>= (shift * 8);
882 data &= 0xffff;
883
884 return (u16)data;
885}
886
887static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
888{
c8826de8 889 u32 mask = 0xffff;
890 __le32 tmp;
ac718b69 891 u16 byen = BYTE_EN_WORD;
892 u8 shift = index & 2;
893
894 data &= mask;
895
896 if (index & 2) {
897 byen <<= shift;
898 mask <<= (shift * 8);
899 data <<= (shift * 8);
900 index &= ~3;
901 }
902
c8826de8 903 tmp = __cpu_to_le32(data);
ac718b69 904
c8826de8 905 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 906}
907
908static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
909{
910 u32 data;
c8826de8 911 __le32 tmp;
ac718b69 912 u8 shift = index & 3;
913
914 index &= ~3;
915
c8826de8 916 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 917
c8826de8 918 data = __le32_to_cpu(tmp);
ac718b69 919 data >>= (shift * 8);
920 data &= 0xff;
921
922 return (u8)data;
923}
924
925static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
926{
c8826de8 927 u32 mask = 0xff;
928 __le32 tmp;
ac718b69 929 u16 byen = BYTE_EN_BYTE;
930 u8 shift = index & 3;
931
932 data &= mask;
933
934 if (index & 3) {
935 byen <<= shift;
936 mask <<= (shift * 8);
937 data <<= (shift * 8);
938 index &= ~3;
939 }
940
c8826de8 941 tmp = __cpu_to_le32(data);
ac718b69 942
c8826de8 943 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 944}
945
ac244d3e 946static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 947{
948 u16 ocp_base, ocp_index;
949
950 ocp_base = addr & 0xf000;
951 if (ocp_base != tp->ocp_base) {
952 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
953 tp->ocp_base = ocp_base;
954 }
955
956 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 957 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 958}
959
ac244d3e 960static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 961{
ac244d3e 962 u16 ocp_base, ocp_index;
ac718b69 963
ac244d3e 964 ocp_base = addr & 0xf000;
965 if (ocp_base != tp->ocp_base) {
966 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
967 tp->ocp_base = ocp_base;
ac718b69 968 }
ac244d3e 969
970 ocp_index = (addr & 0x0fff) | 0xb000;
971 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 972}
973
ac244d3e 974static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 975{
ac244d3e 976 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
977}
ac718b69 978
ac244d3e 979static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
980{
981 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 982}
983
43779f8d 984static void sram_write(struct r8152 *tp, u16 addr, u16 data)
985{
986 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
987 ocp_reg_write(tp, OCP_SRAM_DATA, data);
988}
989
ac718b69 990static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
991{
992 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 993 int ret;
ac718b69 994
6871438c 995 if (test_bit(RTL8152_UNPLUG, &tp->flags))
996 return -ENODEV;
997
ac718b69 998 if (phy_id != R8152_PHY_ID)
999 return -EINVAL;
1000
9a4be1bd 1001 ret = r8152_mdio_read(tp, reg);
1002
9a4be1bd 1003 return ret;
ac718b69 1004}
1005
1006static
1007void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1008{
1009 struct r8152 *tp = netdev_priv(netdev);
1010
6871438c 1011 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1012 return;
1013
ac718b69 1014 if (phy_id != R8152_PHY_ID)
1015 return;
1016
1017 r8152_mdio_write(tp, reg, val);
1018}
1019
b209af99 1020static int
1021r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 1022
8ba789ab 1023static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1024{
1025 struct r8152 *tp = netdev_priv(netdev);
1026 struct sockaddr *addr = p;
ea6a7112 1027 int ret = -EADDRNOTAVAIL;
8ba789ab 1028
1029 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 1030 goto out1;
1031
1032 ret = usb_autopm_get_interface(tp->intf);
1033 if (ret < 0)
1034 goto out1;
8ba789ab 1035
b5403273 1036 mutex_lock(&tp->control);
1037
8ba789ab 1038 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1039
1040 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1041 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1042 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1043
b5403273 1044 mutex_unlock(&tp->control);
1045
ea6a7112 1046 usb_autopm_put_interface(tp->intf);
1047out1:
1048 return ret;
8ba789ab 1049}
1050
34ee32c9
ML
1051/* Devices containing RTL8153-AD can support a persistent
1052 * host system provided MAC address.
1053 * Examples of this are Dell TB15 and Dell WD15 docks
1054 */
1055static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1056{
1057 acpi_status status;
1058 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1059 union acpi_object *obj;
1060 int ret = -EINVAL;
1061 u32 ocp_data;
1062 unsigned char buf[6];
1063
1064 /* test for -AD variant of RTL8153 */
1065 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1066 if ((ocp_data & AD_MASK) != 0x1000)
1067 return -ENODEV;
1068
1069 /* test for MAC address pass-through bit */
1070 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1071 if ((ocp_data & PASS_THRU_MASK) != 1)
1072 return -ENODEV;
1073
1074 /* returns _AUXMAC_#AABBCCDDEEFF# */
1075 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1076 obj = (union acpi_object *)buffer.pointer;
1077 if (!ACPI_SUCCESS(status))
1078 return -ENODEV;
1079 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1080 netif_warn(tp, probe, tp->netdev,
53700f0c 1081 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
34ee32c9
ML
1082 obj->type, obj->string.length);
1083 goto amacout;
1084 }
1085 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1086 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1087 netif_warn(tp, probe, tp->netdev,
1088 "Invalid header when reading pass-thru MAC addr\n");
1089 goto amacout;
1090 }
1091 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1092 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1093 netif_warn(tp, probe, tp->netdev,
53700f0c 1094 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1095 ret, buf);
34ee32c9
ML
1096 ret = -EINVAL;
1097 goto amacout;
1098 }
1099 memcpy(sa->sa_data, buf, 6);
1100 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1101 netif_info(tp, probe, tp->netdev,
1102 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1103
1104amacout:
1105 kfree(obj);
1106 return ret;
1107}
1108
179bb6d7 1109static int set_ethernet_addr(struct r8152 *tp)
ac718b69 1110{
1111 struct net_device *dev = tp->netdev;
179bb6d7 1112 struct sockaddr sa;
8a91c824 1113 int ret;
ac718b69 1114
53700f0c 1115 if (tp->version == RTL_VER_01) {
179bb6d7 1116 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
53700f0c 1117 } else {
34ee32c9
ML
1118 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1119 * or system doesn't provide valid _SB.AMAC this will be
1120 * be expected to non-zero
1121 */
1122 ret = vendor_mac_passthru_addr_read(tp, &sa);
1123 if (ret < 0)
1124 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1125 }
8a91c824 1126
1127 if (ret < 0) {
179bb6d7 1128 netif_err(tp, probe, dev, "Get ether addr fail\n");
1129 } else if (!is_valid_ether_addr(sa.sa_data)) {
1130 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1131 sa.sa_data);
1132 eth_hw_addr_random(dev);
1133 ether_addr_copy(sa.sa_data, dev->dev_addr);
1134 ret = rtl8152_set_mac_address(dev, &sa);
1135 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1136 sa.sa_data);
8a91c824 1137 } else {
179bb6d7 1138 if (tp->version == RTL_VER_01)
1139 ether_addr_copy(dev->dev_addr, sa.sa_data);
1140 else
1141 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1142 }
179bb6d7 1143
1144 return ret;
ac718b69 1145}
1146
ac718b69 1147static void read_bulk_callback(struct urb *urb)
1148{
ac718b69 1149 struct net_device *netdev;
ac718b69 1150 int status = urb->status;
ebc2ec48 1151 struct rx_agg *agg;
1152 struct r8152 *tp;
ac718b69 1153
ebc2ec48 1154 agg = urb->context;
1155 if (!agg)
1156 return;
1157
1158 tp = agg->context;
ac718b69 1159 if (!tp)
1160 return;
ebc2ec48 1161
ac718b69 1162 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1163 return;
ebc2ec48 1164
1165 if (!test_bit(WORK_ENABLE, &tp->flags))
1166 return;
1167
ac718b69 1168 netdev = tp->netdev;
7559fb2f 1169
1170 /* When link down, the driver would cancel all bulks. */
1171 /* This avoid the re-submitting bulk */
ebc2ec48 1172 if (!netif_carrier_ok(netdev))
ac718b69 1173 return;
1174
9a4be1bd 1175 usb_mark_last_busy(tp->udev);
1176
ac718b69 1177 switch (status) {
1178 case 0:
ebc2ec48 1179 if (urb->actual_length < ETH_ZLEN)
1180 break;
1181
2685d410 1182 spin_lock(&tp->rx_lock);
ebc2ec48 1183 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1184 spin_unlock(&tp->rx_lock);
d823ab68 1185 napi_schedule(&tp->napi);
ebc2ec48 1186 return;
ac718b69 1187 case -ESHUTDOWN:
1188 set_bit(RTL8152_UNPLUG, &tp->flags);
1189 netif_device_detach(tp->netdev);
ebc2ec48 1190 return;
ac718b69 1191 case -ENOENT:
1192 return; /* the urb is in unlink state */
1193 case -ETIME:
4a8deae2
HW
1194 if (net_ratelimit())
1195 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1196 break;
ac718b69 1197 default:
4a8deae2
HW
1198 if (net_ratelimit())
1199 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1200 break;
ac718b69 1201 }
1202
a0fccd48 1203 r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1204}
1205
ebc2ec48 1206static void write_bulk_callback(struct urb *urb)
ac718b69 1207{
ebc2ec48 1208 struct net_device_stats *stats;
d104eafa 1209 struct net_device *netdev;
ebc2ec48 1210 struct tx_agg *agg;
ac718b69 1211 struct r8152 *tp;
ebc2ec48 1212 int status = urb->status;
ac718b69 1213
ebc2ec48 1214 agg = urb->context;
1215 if (!agg)
ac718b69 1216 return;
1217
ebc2ec48 1218 tp = agg->context;
1219 if (!tp)
1220 return;
1221
d104eafa 1222 netdev = tp->netdev;
05e0f1aa 1223 stats = &netdev->stats;
ebc2ec48 1224 if (status) {
4a8deae2 1225 if (net_ratelimit())
d104eafa 1226 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1227 stats->tx_errors += agg->skb_num;
ac718b69 1228 } else {
ebc2ec48 1229 stats->tx_packets += agg->skb_num;
1230 stats->tx_bytes += agg->skb_len;
ac718b69 1231 }
1232
2685d410 1233 spin_lock(&tp->tx_lock);
ebc2ec48 1234 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1235 spin_unlock(&tp->tx_lock);
ebc2ec48 1236
9a4be1bd 1237 usb_autopm_put_interface_async(tp->intf);
1238
d104eafa 1239 if (!netif_carrier_ok(netdev))
ebc2ec48 1240 return;
1241
1242 if (!test_bit(WORK_ENABLE, &tp->flags))
1243 return;
1244
1245 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1246 return;
1247
1248 if (!skb_queue_empty(&tp->tx_queue))
d823ab68 1249 napi_schedule(&tp->napi);
ac718b69 1250}
1251
40a82917 1252static void intr_callback(struct urb *urb)
1253{
1254 struct r8152 *tp;
500b6d7e 1255 __le16 *d;
40a82917 1256 int status = urb->status;
1257 int res;
1258
1259 tp = urb->context;
1260 if (!tp)
1261 return;
1262
1263 if (!test_bit(WORK_ENABLE, &tp->flags))
1264 return;
1265
1266 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1267 return;
1268
1269 switch (status) {
1270 case 0: /* success */
1271 break;
1272 case -ECONNRESET: /* unlink */
1273 case -ESHUTDOWN:
1274 netif_device_detach(tp->netdev);
1275 case -ENOENT:
d59c876d 1276 case -EPROTO:
1277 netif_info(tp, intr, tp->netdev,
1278 "Stop submitting intr, status %d\n", status);
40a82917 1279 return;
1280 case -EOVERFLOW:
1281 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1282 goto resubmit;
1283 /* -EPIPE: should clear the halt */
1284 default:
1285 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1286 goto resubmit;
1287 }
1288
1289 d = urb->transfer_buffer;
1290 if (INTR_LINK & __le16_to_cpu(d[0])) {
51d979fa 1291 if (!netif_carrier_ok(tp->netdev)) {
40a82917 1292 set_bit(RTL8152_LINK_CHG, &tp->flags);
1293 schedule_delayed_work(&tp->schedule, 0);
1294 }
1295 } else {
51d979fa 1296 if (netif_carrier_ok(tp->netdev)) {
40a82917 1297 set_bit(RTL8152_LINK_CHG, &tp->flags);
1298 schedule_delayed_work(&tp->schedule, 0);
1299 }
1300 }
1301
1302resubmit:
1303 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1304 if (res == -ENODEV) {
1305 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1306 netif_device_detach(tp->netdev);
67610496 1307 } else if (res) {
40a82917 1308 netif_err(tp, intr, tp->netdev,
4a8deae2 1309 "can't resubmit intr, status %d\n", res);
67610496 1310 }
40a82917 1311}
1312
ebc2ec48 1313static inline void *rx_agg_align(void *data)
1314{
8e1f51bd 1315 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1316}
1317
1318static inline void *tx_agg_align(void *data)
1319{
8e1f51bd 1320 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1321}
1322
1323static void free_all_mem(struct r8152 *tp)
1324{
1325 int i;
1326
1327 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1328 usb_free_urb(tp->rx_info[i].urb);
1329 tp->rx_info[i].urb = NULL;
ebc2ec48 1330
9629e3c0 1331 kfree(tp->rx_info[i].buffer);
1332 tp->rx_info[i].buffer = NULL;
1333 tp->rx_info[i].head = NULL;
ebc2ec48 1334 }
1335
1336 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1337 usb_free_urb(tp->tx_info[i].urb);
1338 tp->tx_info[i].urb = NULL;
ebc2ec48 1339
9629e3c0 1340 kfree(tp->tx_info[i].buffer);
1341 tp->tx_info[i].buffer = NULL;
1342 tp->tx_info[i].head = NULL;
ebc2ec48 1343 }
40a82917 1344
9629e3c0 1345 usb_free_urb(tp->intr_urb);
1346 tp->intr_urb = NULL;
40a82917 1347
9629e3c0 1348 kfree(tp->intr_buff);
1349 tp->intr_buff = NULL;
ebc2ec48 1350}
1351
1352static int alloc_all_mem(struct r8152 *tp)
1353{
1354 struct net_device *netdev = tp->netdev;
40a82917 1355 struct usb_interface *intf = tp->intf;
1356 struct usb_host_interface *alt = intf->cur_altsetting;
1357 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1358 struct urb *urb;
1359 int node, i;
1360 u8 *buf;
1361
1362 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1363
1364 spin_lock_init(&tp->rx_lock);
1365 spin_lock_init(&tp->tx_lock);
ebc2ec48 1366 INIT_LIST_HEAD(&tp->tx_free);
98d068ab 1367 INIT_LIST_HEAD(&tp->rx_done);
ebc2ec48 1368 skb_queue_head_init(&tp->tx_queue);
d823ab68 1369 skb_queue_head_init(&tp->rx_queue);
ebc2ec48 1370
1371 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1372 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1373 if (!buf)
1374 goto err1;
1375
1376 if (buf != rx_agg_align(buf)) {
1377 kfree(buf);
52aec126 1378 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1379 node);
ebc2ec48 1380 if (!buf)
1381 goto err1;
1382 }
1383
1384 urb = usb_alloc_urb(0, GFP_KERNEL);
1385 if (!urb) {
1386 kfree(buf);
1387 goto err1;
1388 }
1389
1390 INIT_LIST_HEAD(&tp->rx_info[i].list);
1391 tp->rx_info[i].context = tp;
1392 tp->rx_info[i].urb = urb;
1393 tp->rx_info[i].buffer = buf;
1394 tp->rx_info[i].head = rx_agg_align(buf);
1395 }
1396
1397 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1398 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1399 if (!buf)
1400 goto err1;
1401
1402 if (buf != tx_agg_align(buf)) {
1403 kfree(buf);
52aec126 1404 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1405 node);
ebc2ec48 1406 if (!buf)
1407 goto err1;
1408 }
1409
1410 urb = usb_alloc_urb(0, GFP_KERNEL);
1411 if (!urb) {
1412 kfree(buf);
1413 goto err1;
1414 }
1415
1416 INIT_LIST_HEAD(&tp->tx_info[i].list);
1417 tp->tx_info[i].context = tp;
1418 tp->tx_info[i].urb = urb;
1419 tp->tx_info[i].buffer = buf;
1420 tp->tx_info[i].head = tx_agg_align(buf);
1421
1422 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1423 }
1424
40a82917 1425 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1426 if (!tp->intr_urb)
1427 goto err1;
1428
1429 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1430 if (!tp->intr_buff)
1431 goto err1;
1432
1433 tp->intr_interval = (int)ep_intr->desc.bInterval;
1434 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1435 tp->intr_buff, INTBUFSIZE, intr_callback,
1436 tp, tp->intr_interval);
40a82917 1437
ebc2ec48 1438 return 0;
1439
1440err1:
1441 free_all_mem(tp);
1442 return -ENOMEM;
1443}
1444
0de98f6c 1445static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1446{
1447 struct tx_agg *agg = NULL;
1448 unsigned long flags;
1449
21949ab7 1450 if (list_empty(&tp->tx_free))
1451 return NULL;
1452
0de98f6c 1453 spin_lock_irqsave(&tp->tx_lock, flags);
1454 if (!list_empty(&tp->tx_free)) {
1455 struct list_head *cursor;
1456
1457 cursor = tp->tx_free.next;
1458 list_del_init(cursor);
1459 agg = list_entry(cursor, struct tx_agg, list);
1460 }
1461 spin_unlock_irqrestore(&tp->tx_lock, flags);
1462
1463 return agg;
1464}
1465
b209af99 1466/* r8152_csum_workaround()
6128d1bb 1467 * The hw limites the value the transport offset. When the offset is out of the
1468 * range, calculate the checksum by sw.
1469 */
1470static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1471 struct sk_buff_head *list)
1472{
1473 if (skb_shinfo(skb)->gso_size) {
1474 netdev_features_t features = tp->netdev->features;
1475 struct sk_buff_head seg_list;
1476 struct sk_buff *segs, *nskb;
1477
a91d45f1 1478 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1479 segs = skb_gso_segment(skb, features);
1480 if (IS_ERR(segs) || !segs)
1481 goto drop;
1482
1483 __skb_queue_head_init(&seg_list);
1484
1485 do {
1486 nskb = segs;
1487 segs = segs->next;
1488 nskb->next = NULL;
1489 __skb_queue_tail(&seg_list, nskb);
1490 } while (segs);
1491
1492 skb_queue_splice(&seg_list, list);
1493 dev_kfree_skb(skb);
1494 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1495 if (skb_checksum_help(skb) < 0)
1496 goto drop;
1497
1498 __skb_queue_head(list, skb);
1499 } else {
1500 struct net_device_stats *stats;
1501
1502drop:
1503 stats = &tp->netdev->stats;
1504 stats->tx_dropped++;
1505 dev_kfree_skb(skb);
1506 }
1507}
1508
b209af99 1509/* msdn_giant_send_check()
6128d1bb 1510 * According to the document of microsoft, the TCP Pseudo Header excludes the
1511 * packet length for IPv6 TCP large packets.
1512 */
1513static int msdn_giant_send_check(struct sk_buff *skb)
1514{
1515 const struct ipv6hdr *ipv6h;
1516 struct tcphdr *th;
fcb308d5 1517 int ret;
1518
1519 ret = skb_cow_head(skb, 0);
1520 if (ret)
1521 return ret;
6128d1bb 1522
1523 ipv6h = ipv6_hdr(skb);
1524 th = tcp_hdr(skb);
1525
1526 th->check = 0;
1527 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1528
fcb308d5 1529 return ret;
6128d1bb 1530}
1531
c5554298 1532static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1533{
df8a39de 1534 if (skb_vlan_tag_present(skb)) {
c5554298 1535 u32 opts2;
1536
df8a39de 1537 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
c5554298 1538 desc->opts2 |= cpu_to_le32(opts2);
1539 }
1540}
1541
1542static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1543{
1544 u32 opts2 = le32_to_cpu(desc->opts2);
1545
1546 if (opts2 & RX_VLAN_TAG)
1547 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1548 swab16(opts2 & 0xffff));
1549}
1550
60c89071 1551static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1552 struct sk_buff *skb, u32 len, u32 transport_offset)
1553{
1554 u32 mss = skb_shinfo(skb)->gso_size;
1555 u32 opts1, opts2 = 0;
1556 int ret = TX_CSUM_SUCCESS;
1557
1558 WARN_ON_ONCE(len > TX_LEN_MAX);
1559
1560 opts1 = len | TX_FS | TX_LS;
1561
1562 if (mss) {
6128d1bb 1563 if (transport_offset > GTTCPHO_MAX) {
1564 netif_warn(tp, tx_err, tp->netdev,
1565 "Invalid transport offset 0x%x for TSO\n",
1566 transport_offset);
1567 ret = TX_CSUM_TSO;
1568 goto unavailable;
1569 }
1570
6e74d174 1571 switch (vlan_get_protocol(skb)) {
60c89071 1572 case htons(ETH_P_IP):
1573 opts1 |= GTSENDV4;
1574 break;
1575
6128d1bb 1576 case htons(ETH_P_IPV6):
fcb308d5 1577 if (msdn_giant_send_check(skb)) {
1578 ret = TX_CSUM_TSO;
1579 goto unavailable;
1580 }
6128d1bb 1581 opts1 |= GTSENDV6;
6128d1bb 1582 break;
1583
60c89071 1584 default:
1585 WARN_ON_ONCE(1);
1586 break;
1587 }
1588
1589 opts1 |= transport_offset << GTTCPHO_SHIFT;
1590 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1591 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1592 u8 ip_protocol;
5bd23881 1593
6128d1bb 1594 if (transport_offset > TCPHO_MAX) {
1595 netif_warn(tp, tx_err, tp->netdev,
1596 "Invalid transport offset 0x%x\n",
1597 transport_offset);
1598 ret = TX_CSUM_NONE;
1599 goto unavailable;
1600 }
1601
6e74d174 1602 switch (vlan_get_protocol(skb)) {
5bd23881 1603 case htons(ETH_P_IP):
1604 opts2 |= IPV4_CS;
1605 ip_protocol = ip_hdr(skb)->protocol;
1606 break;
1607
1608 case htons(ETH_P_IPV6):
1609 opts2 |= IPV6_CS;
1610 ip_protocol = ipv6_hdr(skb)->nexthdr;
1611 break;
1612
1613 default:
1614 ip_protocol = IPPROTO_RAW;
1615 break;
1616 }
1617
60c89071 1618 if (ip_protocol == IPPROTO_TCP)
5bd23881 1619 opts2 |= TCP_CS;
60c89071 1620 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1621 opts2 |= UDP_CS;
60c89071 1622 else
5bd23881 1623 WARN_ON_ONCE(1);
5bd23881 1624
60c89071 1625 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1626 }
60c89071 1627
1628 desc->opts2 = cpu_to_le32(opts2);
1629 desc->opts1 = cpu_to_le32(opts1);
1630
6128d1bb 1631unavailable:
60c89071 1632 return ret;
5bd23881 1633}
1634
b1379d9a 1635static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1636{
d84130a1 1637 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1638 int remain, ret;
b1379d9a 1639 u8 *tx_data;
1640
d84130a1 1641 __skb_queue_head_init(&skb_head);
0c3121fc 1642 spin_lock(&tx_queue->lock);
d84130a1 1643 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1644 spin_unlock(&tx_queue->lock);
d84130a1 1645
b1379d9a 1646 tx_data = agg->head;
b209af99 1647 agg->skb_num = 0;
1648 agg->skb_len = 0;
52aec126 1649 remain = agg_buf_sz;
b1379d9a 1650
7937f9e5 1651 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1652 struct tx_desc *tx_desc;
1653 struct sk_buff *skb;
1654 unsigned int len;
60c89071 1655 u32 offset;
b1379d9a 1656
d84130a1 1657 skb = __skb_dequeue(&skb_head);
b1379d9a 1658 if (!skb)
1659 break;
1660
60c89071 1661 len = skb->len + sizeof(*tx_desc);
1662
1663 if (len > remain) {
d84130a1 1664 __skb_queue_head(&skb_head, skb);
b1379d9a 1665 break;
1666 }
1667
7937f9e5 1668 tx_data = tx_agg_align(tx_data);
b1379d9a 1669 tx_desc = (struct tx_desc *)tx_data;
60c89071 1670
1671 offset = (u32)skb_transport_offset(skb);
1672
6128d1bb 1673 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1674 r8152_csum_workaround(tp, skb, &skb_head);
1675 continue;
1676 }
60c89071 1677
c5554298 1678 rtl_tx_vlan_tag(tx_desc, skb);
1679
b1379d9a 1680 tx_data += sizeof(*tx_desc);
1681
60c89071 1682 len = skb->len;
1683 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1684 struct net_device_stats *stats = &tp->netdev->stats;
1685
1686 stats->tx_dropped++;
1687 dev_kfree_skb_any(skb);
1688 tx_data -= sizeof(*tx_desc);
1689 continue;
1690 }
1691
1692 tx_data += len;
b1379d9a 1693 agg->skb_len += len;
60c89071 1694 agg->skb_num++;
1695
b1379d9a 1696 dev_kfree_skb_any(skb);
1697
52aec126 1698 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1699 }
1700
d84130a1 1701 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1702 spin_lock(&tx_queue->lock);
d84130a1 1703 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1704 spin_unlock(&tx_queue->lock);
d84130a1 1705 }
1706
0c3121fc 1707 netif_tx_lock(tp->netdev);
dd1b119c 1708
1709 if (netif_queue_stopped(tp->netdev) &&
1710 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1711 netif_wake_queue(tp->netdev);
1712
0c3121fc 1713 netif_tx_unlock(tp->netdev);
9a4be1bd 1714
0c3121fc 1715 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1716 if (ret < 0)
1717 goto out_tx_fill;
dd1b119c 1718
b1379d9a 1719 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1720 agg->head, (int)(tx_data - (u8 *)agg->head),
1721 (usb_complete_t)write_bulk_callback, agg);
1722
0c3121fc 1723 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1724 if (ret < 0)
0c3121fc 1725 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1726
1727out_tx_fill:
1728 return ret;
b1379d9a 1729}
1730
565cab0a 1731static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1732{
1733 u8 checksum = CHECKSUM_NONE;
1734 u32 opts2, opts3;
1735
19c0f40d 1736 if (!(tp->netdev->features & NETIF_F_RXCSUM))
565cab0a 1737 goto return_result;
1738
1739 opts2 = le32_to_cpu(rx_desc->opts2);
1740 opts3 = le32_to_cpu(rx_desc->opts3);
1741
1742 if (opts2 & RD_IPV4_CS) {
1743 if (opts3 & IPF)
1744 checksum = CHECKSUM_NONE;
1745 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1746 checksum = CHECKSUM_NONE;
1747 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1748 checksum = CHECKSUM_NONE;
1749 else
1750 checksum = CHECKSUM_UNNECESSARY;
b9a321b4 1751 } else if (opts2 & RD_IPV6_CS) {
6128d1bb 1752 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1753 checksum = CHECKSUM_UNNECESSARY;
1754 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1755 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1756 }
1757
1758return_result:
1759 return checksum;
1760}
1761
d823ab68 1762static int rx_bottom(struct r8152 *tp, int budget)
ebc2ec48 1763{
a5a4f468 1764 unsigned long flags;
d84130a1 1765 struct list_head *cursor, *next, rx_queue;
e1a2ca92 1766 int ret = 0, work_done = 0;
ce594e98 1767 struct napi_struct *napi = &tp->napi;
d823ab68 1768
1769 if (!skb_queue_empty(&tp->rx_queue)) {
1770 while (work_done < budget) {
1771 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1772 struct net_device *netdev = tp->netdev;
1773 struct net_device_stats *stats = &netdev->stats;
1774 unsigned int pkt_len;
1775
1776 if (!skb)
1777 break;
1778
1779 pkt_len = skb->len;
ce594e98 1780 napi_gro_receive(napi, skb);
d823ab68 1781 work_done++;
1782 stats->rx_packets++;
1783 stats->rx_bytes += pkt_len;
1784 }
1785 }
ebc2ec48 1786
d84130a1 1787 if (list_empty(&tp->rx_done))
d823ab68 1788 goto out1;
d84130a1 1789
1790 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1791 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1792 list_splice_init(&tp->rx_done, &rx_queue);
1793 spin_unlock_irqrestore(&tp->rx_lock, flags);
1794
1795 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1796 struct rx_desc *rx_desc;
1797 struct rx_agg *agg;
43a4478d 1798 int len_used = 0;
1799 struct urb *urb;
1800 u8 *rx_data;
43a4478d 1801
ebc2ec48 1802 list_del_init(cursor);
ebc2ec48 1803
1804 agg = list_entry(cursor, struct rx_agg, list);
1805 urb = agg->urb;
0de98f6c 1806 if (urb->actual_length < ETH_ZLEN)
1807 goto submit;
ebc2ec48 1808
ebc2ec48 1809 rx_desc = agg->head;
1810 rx_data = agg->head;
7937f9e5 1811 len_used += sizeof(struct rx_desc);
ebc2ec48 1812
7937f9e5 1813 while (urb->actual_length > len_used) {
43a4478d 1814 struct net_device *netdev = tp->netdev;
05e0f1aa 1815 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1816 unsigned int pkt_len;
43a4478d 1817 struct sk_buff *skb;
1818
7937f9e5 1819 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1820 if (pkt_len < ETH_ZLEN)
1821 break;
1822
7937f9e5 1823 len_used += pkt_len;
1824 if (urb->actual_length < len_used)
1825 break;
1826
8e1f51bd 1827 pkt_len -= CRC_SIZE;
ebc2ec48 1828 rx_data += sizeof(struct rx_desc);
1829
ce594e98 1830 skb = napi_alloc_skb(napi, pkt_len);
ebc2ec48 1831 if (!skb) {
1832 stats->rx_dropped++;
5e2f7485 1833 goto find_next_rx;
ebc2ec48 1834 }
565cab0a 1835
1836 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1837 memcpy(skb->data, rx_data, pkt_len);
1838 skb_put(skb, pkt_len);
1839 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1840 rtl_rx_vlan_tag(rx_desc, skb);
d823ab68 1841 if (work_done < budget) {
ce594e98 1842 napi_gro_receive(napi, skb);
d823ab68 1843 work_done++;
1844 stats->rx_packets++;
1845 stats->rx_bytes += pkt_len;
1846 } else {
1847 __skb_queue_tail(&tp->rx_queue, skb);
1848 }
ebc2ec48 1849
5e2f7485 1850find_next_rx:
8e1f51bd 1851 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1852 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1853 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1854 len_used += sizeof(struct rx_desc);
ebc2ec48 1855 }
1856
0de98f6c 1857submit:
e1a2ca92 1858 if (!ret) {
1859 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1860 } else {
1861 urb->actual_length = 0;
1862 list_add_tail(&agg->list, next);
1863 }
1864 }
1865
1866 if (!list_empty(&rx_queue)) {
1867 spin_lock_irqsave(&tp->rx_lock, flags);
1868 list_splice_tail(&rx_queue, &tp->rx_done);
1869 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1870 }
d823ab68 1871
1872out1:
1873 return work_done;
ebc2ec48 1874}
1875
1876static void tx_bottom(struct r8152 *tp)
1877{
ebc2ec48 1878 int res;
1879
b1379d9a 1880 do {
1881 struct tx_agg *agg;
ebc2ec48 1882
b1379d9a 1883 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1884 break;
1885
b1379d9a 1886 agg = r8152_get_tx_agg(tp);
1887 if (!agg)
ebc2ec48 1888 break;
ebc2ec48 1889
b1379d9a 1890 res = r8152_tx_agg_fill(tp, agg);
1891 if (res) {
05e0f1aa 1892 struct net_device *netdev = tp->netdev;
ebc2ec48 1893
b1379d9a 1894 if (res == -ENODEV) {
67610496 1895 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1896 netif_device_detach(netdev);
1897 } else {
05e0f1aa 1898 struct net_device_stats *stats = &netdev->stats;
1899 unsigned long flags;
1900
b1379d9a 1901 netif_warn(tp, tx_err, netdev,
1902 "failed tx_urb %d\n", res);
1903 stats->tx_dropped += agg->skb_num;
db8515ef 1904
b1379d9a 1905 spin_lock_irqsave(&tp->tx_lock, flags);
1906 list_add_tail(&agg->list, &tp->tx_free);
1907 spin_unlock_irqrestore(&tp->tx_lock, flags);
1908 }
ebc2ec48 1909 }
b1379d9a 1910 } while (res == 0);
ebc2ec48 1911}
1912
d823ab68 1913static void bottom_half(struct r8152 *tp)
ac718b69 1914{
ebc2ec48 1915 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1916 return;
1917
1918 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1919 return;
ebc2ec48 1920
7559fb2f 1921 /* When link down, the driver would cancel all bulks. */
1922 /* This avoid the re-submitting bulk */
ebc2ec48 1923 if (!netif_carrier_ok(tp->netdev))
ac718b69 1924 return;
ebc2ec48 1925
d823ab68 1926 clear_bit(SCHEDULE_NAPI, &tp->flags);
9451a11c 1927
0c3121fc 1928 tx_bottom(tp);
ebc2ec48 1929}
1930
d823ab68 1931static int r8152_poll(struct napi_struct *napi, int budget)
1932{
1933 struct r8152 *tp = container_of(napi, struct r8152, napi);
1934 int work_done;
1935
1936 work_done = rx_bottom(tp, budget);
1937 bottom_half(tp);
1938
1939 if (work_done < budget) {
1940 napi_complete(napi);
1941 if (!list_empty(&tp->rx_done))
1942 napi_schedule(napi);
248b213a 1943 else if (!skb_queue_empty(&tp->tx_queue) &&
1944 !list_empty(&tp->tx_free))
1945 napi_schedule(napi);
d823ab68 1946 }
1947
1948 return work_done;
1949}
1950
ebc2ec48 1951static
1952int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1953{
a0fccd48 1954 int ret;
1955
ef827a5b 1956 /* The rx would be stopped, so skip submitting */
1957 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1958 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1959 return 0;
1960
ebc2ec48 1961 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1962 agg->head, agg_buf_sz,
b209af99 1963 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1964
a0fccd48 1965 ret = usb_submit_urb(agg->urb, mem_flags);
1966 if (ret == -ENODEV) {
1967 set_bit(RTL8152_UNPLUG, &tp->flags);
1968 netif_device_detach(tp->netdev);
1969 } else if (ret) {
1970 struct urb *urb = agg->urb;
1971 unsigned long flags;
1972
1973 urb->actual_length = 0;
1974 spin_lock_irqsave(&tp->rx_lock, flags);
1975 list_add_tail(&agg->list, &tp->rx_done);
1976 spin_unlock_irqrestore(&tp->rx_lock, flags);
d823ab68 1977
1978 netif_err(tp, rx_err, tp->netdev,
1979 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1980
1981 napi_schedule(&tp->napi);
a0fccd48 1982 }
1983
1984 return ret;
ac718b69 1985}
1986
00a5e360 1987static void rtl_drop_queued_tx(struct r8152 *tp)
1988{
1989 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1990 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1991 struct sk_buff *skb;
1992
d84130a1 1993 if (skb_queue_empty(tx_queue))
1994 return;
1995
1996 __skb_queue_head_init(&skb_head);
2685d410 1997 spin_lock_bh(&tx_queue->lock);
d84130a1 1998 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1999 spin_unlock_bh(&tx_queue->lock);
d84130a1 2000
2001 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 2002 dev_kfree_skb(skb);
2003 stats->tx_dropped++;
2004 }
2005}
2006
ac718b69 2007static void rtl8152_tx_timeout(struct net_device *netdev)
2008{
2009 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 2010
4a8deae2 2011 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
37608f3e 2012
2013 usb_queue_reset_device(tp->intf);
ac718b69 2014}
2015
2016static void rtl8152_set_rx_mode(struct net_device *netdev)
2017{
2018 struct r8152 *tp = netdev_priv(netdev);
2019
51d979fa 2020 if (netif_carrier_ok(netdev)) {
ac718b69 2021 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 2022 schedule_delayed_work(&tp->schedule, 0);
2023 }
ac718b69 2024}
2025
2026static void _rtl8152_set_rx_mode(struct net_device *netdev)
2027{
2028 struct r8152 *tp = netdev_priv(netdev);
31787f53 2029 u32 mc_filter[2]; /* Multicast hash filter */
2030 __le32 tmp[2];
ac718b69 2031 u32 ocp_data;
2032
ac718b69 2033 netif_stop_queue(netdev);
2034 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2035 ocp_data &= ~RCR_ACPT_ALL;
2036 ocp_data |= RCR_AB | RCR_APM;
2037
2038 if (netdev->flags & IFF_PROMISC) {
2039 /* Unconditionally log net taps. */
2040 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2041 ocp_data |= RCR_AM | RCR_AAP;
b209af99 2042 mc_filter[1] = 0xffffffff;
2043 mc_filter[0] = 0xffffffff;
ac718b69 2044 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2045 (netdev->flags & IFF_ALLMULTI)) {
2046 /* Too many to filter perfectly -- accept all multicasts. */
2047 ocp_data |= RCR_AM;
b209af99 2048 mc_filter[1] = 0xffffffff;
2049 mc_filter[0] = 0xffffffff;
ac718b69 2050 } else {
2051 struct netdev_hw_addr *ha;
2052
b209af99 2053 mc_filter[1] = 0;
2054 mc_filter[0] = 0;
ac718b69 2055 netdev_for_each_mc_addr(ha, netdev) {
2056 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 2057
ac718b69 2058 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2059 ocp_data |= RCR_AM;
2060 }
2061 }
2062
31787f53 2063 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2064 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 2065
31787f53 2066 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 2067 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2068 netif_wake_queue(netdev);
ac718b69 2069}
2070
a5e31255 2071static netdev_features_t
2072rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2073 netdev_features_t features)
2074{
2075 u32 mss = skb_shinfo(skb)->gso_size;
2076 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2077 int offset = skb_transport_offset(skb);
2078
2079 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
a188222b 2080 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
a5e31255 2081 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2082 features &= ~NETIF_F_GSO_MASK;
2083
2084 return features;
2085}
2086
ac718b69 2087static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 2088 struct net_device *netdev)
ac718b69 2089{
2090 struct r8152 *tp = netdev_priv(netdev);
ac718b69 2091
ebc2ec48 2092 skb_tx_timestamp(skb);
ac718b69 2093
61598788 2094 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 2095
0c3121fc 2096 if (!list_empty(&tp->tx_free)) {
2097 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
d823ab68 2098 set_bit(SCHEDULE_NAPI, &tp->flags);
0c3121fc 2099 schedule_delayed_work(&tp->schedule, 0);
2100 } else {
2101 usb_mark_last_busy(tp->udev);
d823ab68 2102 napi_schedule(&tp->napi);
0c3121fc 2103 }
b209af99 2104 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 2105 netif_stop_queue(netdev);
b209af99 2106 }
dd1b119c 2107
ac718b69 2108 return NETDEV_TX_OK;
2109}
2110
2111static void r8152b_reset_packet_filter(struct r8152 *tp)
2112{
2113 u32 ocp_data;
2114
2115 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2116 ocp_data &= ~FMC_FCR_MCU_EN;
2117 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2118 ocp_data |= FMC_FCR_MCU_EN;
2119 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2120}
2121
2122static void rtl8152_nic_reset(struct r8152 *tp)
2123{
2124 int i;
2125
2126 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2127
2128 for (i = 0; i < 1000; i++) {
2129 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2130 break;
b209af99 2131 usleep_range(100, 400);
ac718b69 2132 }
2133}
2134
dd1b119c 2135static void set_tx_qlen(struct r8152 *tp)
2136{
2137 struct net_device *netdev = tp->netdev;
2138
52aec126 2139 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2140 sizeof(struct tx_desc));
dd1b119c 2141}
2142
ac718b69 2143static inline u8 rtl8152_get_speed(struct r8152 *tp)
2144{
2145 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2146}
2147
507605a8 2148static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 2149{
ebc2ec48 2150 u32 ocp_data;
ac718b69 2151 u8 speed;
2152
2153 speed = rtl8152_get_speed(tp);
ebc2ec48 2154 if (speed & _10bps) {
ac718b69 2155 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2156 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 2157 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2158 } else {
2159 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2160 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 2161 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2162 }
507605a8 2163}
2164
00a5e360 2165static void rxdy_gated_en(struct r8152 *tp, bool enable)
2166{
2167 u32 ocp_data;
2168
2169 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2170 if (enable)
2171 ocp_data |= RXDY_GATED_EN;
2172 else
2173 ocp_data &= ~RXDY_GATED_EN;
2174 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2175}
2176
445f7f4d 2177static int rtl_start_rx(struct r8152 *tp)
2178{
2179 int i, ret = 0;
2180
2181 INIT_LIST_HEAD(&tp->rx_done);
2182 for (i = 0; i < RTL8152_MAX_RX; i++) {
2183 INIT_LIST_HEAD(&tp->rx_info[i].list);
2184 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2185 if (ret)
2186 break;
2187 }
2188
7bcf4f60 2189 if (ret && ++i < RTL8152_MAX_RX) {
2190 struct list_head rx_queue;
2191 unsigned long flags;
2192
2193 INIT_LIST_HEAD(&rx_queue);
2194
2195 do {
2196 struct rx_agg *agg = &tp->rx_info[i++];
2197 struct urb *urb = agg->urb;
2198
2199 urb->actual_length = 0;
2200 list_add_tail(&agg->list, &rx_queue);
2201 } while (i < RTL8152_MAX_RX);
2202
2203 spin_lock_irqsave(&tp->rx_lock, flags);
2204 list_splice_tail(&rx_queue, &tp->rx_done);
2205 spin_unlock_irqrestore(&tp->rx_lock, flags);
2206 }
2207
445f7f4d 2208 return ret;
2209}
2210
2211static int rtl_stop_rx(struct r8152 *tp)
2212{
2213 int i;
2214
2215 for (i = 0; i < RTL8152_MAX_RX; i++)
2216 usb_kill_urb(tp->rx_info[i].urb);
2217
d823ab68 2218 while (!skb_queue_empty(&tp->rx_queue))
2219 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2220
445f7f4d 2221 return 0;
2222}
2223
507605a8 2224static int rtl_enable(struct r8152 *tp)
2225{
2226 u32 ocp_data;
ac718b69 2227
2228 r8152b_reset_packet_filter(tp);
2229
2230 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2231 ocp_data |= CR_RE | CR_TE;
2232 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2233
00a5e360 2234 rxdy_gated_en(tp, false);
ac718b69 2235
aa2e0926 2236 return 0;
ac718b69 2237}
2238
507605a8 2239static int rtl8152_enable(struct r8152 *tp)
2240{
6871438c 2241 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2242 return -ENODEV;
2243
507605a8 2244 set_tx_qlen(tp);
2245 rtl_set_eee_plus(tp);
2246
2247 return rtl_enable(tp);
2248}
2249
464ec10a 2250static void r8153_set_rx_early_timeout(struct r8152 *tp)
43779f8d 2251{
464ec10a 2252 u32 ocp_data = tp->coalesce / 8;
43779f8d 2253
464ec10a 2254 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2255}
2256
2257static void r8153_set_rx_early_size(struct r8152 *tp)
2258{
b20cb60e 2259 u32 ocp_data = (agg_buf_sz - rx_reserved_size(tp->netdev->mtu)) / 4;
464ec10a 2260
2261 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
43779f8d 2262}
2263
2264static int rtl8153_enable(struct r8152 *tp)
2265{
6871438c 2266 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2267 return -ENODEV;
2268
b214396f 2269 usb_disable_lpm(tp->udev);
43779f8d 2270 set_tx_qlen(tp);
2271 rtl_set_eee_plus(tp);
464ec10a 2272 r8153_set_rx_early_timeout(tp);
2273 r8153_set_rx_early_size(tp);
43779f8d 2274
2275 return rtl_enable(tp);
2276}
2277
d70b1137 2278static void rtl_disable(struct r8152 *tp)
ac718b69 2279{
ebc2ec48 2280 u32 ocp_data;
2281 int i;
ac718b69 2282
6871438c 2283 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2284 rtl_drop_queued_tx(tp);
2285 return;
2286 }
2287
ac718b69 2288 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2289 ocp_data &= ~RCR_ACPT_ALL;
2290 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2291
00a5e360 2292 rtl_drop_queued_tx(tp);
ebc2ec48 2293
2294 for (i = 0; i < RTL8152_MAX_TX; i++)
2295 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2296
00a5e360 2297 rxdy_gated_en(tp, true);
ac718b69 2298
2299 for (i = 0; i < 1000; i++) {
2300 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2301 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2302 break;
8ddfa077 2303 usleep_range(1000, 2000);
ac718b69 2304 }
2305
2306 for (i = 0; i < 1000; i++) {
2307 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2308 break;
8ddfa077 2309 usleep_range(1000, 2000);
ac718b69 2310 }
2311
445f7f4d 2312 rtl_stop_rx(tp);
ac718b69 2313
2314 rtl8152_nic_reset(tp);
2315}
2316
00a5e360 2317static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2318{
2319 u32 ocp_data;
2320
2321 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2322 if (enable)
2323 ocp_data |= POWER_CUT;
2324 else
2325 ocp_data &= ~POWER_CUT;
2326 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2327
2328 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2329 ocp_data &= ~RESUME_INDICATE;
2330 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2331}
2332
c5554298 2333static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2334{
2335 u32 ocp_data;
2336
2337 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2338 if (enable)
2339 ocp_data |= CPCR_RX_VLAN;
2340 else
2341 ocp_data &= ~CPCR_RX_VLAN;
2342 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2343}
2344
2345static int rtl8152_set_features(struct net_device *dev,
2346 netdev_features_t features)
2347{
2348 netdev_features_t changed = features ^ dev->features;
2349 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2350 int ret;
2351
2352 ret = usb_autopm_get_interface(tp->intf);
2353 if (ret < 0)
2354 goto out;
c5554298 2355
b5403273 2356 mutex_lock(&tp->control);
2357
c5554298 2358 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2359 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2360 rtl_rx_vlan_en(tp, true);
2361 else
2362 rtl_rx_vlan_en(tp, false);
2363 }
2364
b5403273 2365 mutex_unlock(&tp->control);
2366
405f8a0e 2367 usb_autopm_put_interface(tp->intf);
2368
2369out:
2370 return ret;
c5554298 2371}
2372
21ff2e89 2373#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2374
2375static u32 __rtl_get_wol(struct r8152 *tp)
2376{
2377 u32 ocp_data;
2378 u32 wolopts = 0;
2379
21ff2e89 2380 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2381 if (ocp_data & LINK_ON_WAKE_EN)
2382 wolopts |= WAKE_PHY;
2383
2384 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2385 if (ocp_data & UWF_EN)
2386 wolopts |= WAKE_UCAST;
2387 if (ocp_data & BWF_EN)
2388 wolopts |= WAKE_BCAST;
2389 if (ocp_data & MWF_EN)
2390 wolopts |= WAKE_MCAST;
2391
2392 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2393 if (ocp_data & MAGIC_EN)
2394 wolopts |= WAKE_MAGIC;
2395
2396 return wolopts;
2397}
2398
2399static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2400{
2401 u32 ocp_data;
2402
2403 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2404
2405 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2406 ocp_data &= ~LINK_ON_WAKE_EN;
2407 if (wolopts & WAKE_PHY)
2408 ocp_data |= LINK_ON_WAKE_EN;
2409 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2410
2411 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
92f7d07d 2412 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
21ff2e89 2413 if (wolopts & WAKE_UCAST)
2414 ocp_data |= UWF_EN;
2415 if (wolopts & WAKE_BCAST)
2416 ocp_data |= BWF_EN;
2417 if (wolopts & WAKE_MCAST)
2418 ocp_data |= MWF_EN;
21ff2e89 2419 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2420
2421 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2422
2423 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2424 ocp_data &= ~MAGIC_EN;
2425 if (wolopts & WAKE_MAGIC)
2426 ocp_data |= MAGIC_EN;
2427 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2428
2429 if (wolopts & WAKE_ANY)
2430 device_set_wakeup_enable(&tp->udev->dev, true);
2431 else
2432 device_set_wakeup_enable(&tp->udev->dev, false);
2433}
2434
b214396f 2435static void r8153_u1u2en(struct r8152 *tp, bool enable)
2436{
2437 u8 u1u2[8];
2438
2439 if (enable)
2440 memset(u1u2, 0xff, sizeof(u1u2));
2441 else
2442 memset(u1u2, 0x00, sizeof(u1u2));
2443
2444 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2445}
2446
2447static void r8153_u2p3en(struct r8152 *tp, bool enable)
2448{
2449 u32 ocp_data;
2450
2451 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2452 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
2453 ocp_data |= U2P3_ENABLE;
2454 else
2455 ocp_data &= ~U2P3_ENABLE;
2456 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2457}
2458
2459static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2460{
2461 u32 ocp_data;
2462
2463 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2464 if (enable)
2465 ocp_data |= PWR_EN | PHASE2_EN;
2466 else
2467 ocp_data &= ~(PWR_EN | PHASE2_EN);
2468 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2469
2470 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2471 ocp_data &= ~PCUT_STATUS;
2472 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2473}
2474
7daed8dc 2475static bool rtl_can_wakeup(struct r8152 *tp)
2476{
2477 struct usb_device *udev = tp->udev;
2478
2479 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2480}
2481
9a4be1bd 2482static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2483{
2484 if (enable) {
2485 u32 ocp_data;
2486
2487 __rtl_set_wol(tp, WAKE_ANY);
2488
2489 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2490
2491 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2492 ocp_data |= LINK_OFF_WAKE_EN;
2493 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2494
2495 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2496 } else {
f95ae8a0 2497 u32 ocp_data;
2498
9a4be1bd 2499 __rtl_set_wol(tp, tp->saved_wolopts);
f95ae8a0 2500
2501 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2502
2503 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2504 ocp_data &= ~LINK_OFF_WAKE_EN;
2505 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2506
2507 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2609af19 2508 }
2509}
f95ae8a0 2510
2609af19 2511static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2512{
2513 rtl_runtime_suspend_enable(tp, enable);
2514
2515 if (enable) {
2516 r8153_u1u2en(tp, false);
2517 r8153_u2p3en(tp, false);
2518 } else {
b214396f 2519 r8153_u2p3en(tp, true);
2520 r8153_u1u2en(tp, true);
9a4be1bd 2521 }
2522}
2523
4349968a 2524static void r8153_teredo_off(struct r8152 *tp)
2525{
2526 u32 ocp_data;
2527
2528 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2529 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2530 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2531
2532 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2533 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2534 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2535}
2536
93fe9b18 2537static void rtl_reset_bmu(struct r8152 *tp)
2538{
2539 u32 ocp_data;
2540
2541 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2542 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2543 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2544 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2545 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2546}
2547
cda9fb01 2548static void r8152_aldps_en(struct r8152 *tp, bool enable)
4349968a 2549{
cda9fb01 2550 if (enable) {
2551 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2552 LINKENA | DIS_SDSAVE);
2553 } else {
2554 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2555 DIS_SDSAVE);
2556 msleep(20);
2557 }
4349968a 2558}
2559
e6449539 2560static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2561{
2562 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2563 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2564 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2565}
2566
2567static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2568{
2569 u16 data;
2570
2571 r8152_mmd_indirect(tp, dev, reg);
2572 data = ocp_reg_read(tp, OCP_EEE_DATA);
2573 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2574
2575 return data;
2576}
2577
2578static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2579{
2580 r8152_mmd_indirect(tp, dev, reg);
2581 ocp_reg_write(tp, OCP_EEE_DATA, data);
2582 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2583}
2584
2585static void r8152_eee_en(struct r8152 *tp, bool enable)
2586{
2587 u16 config1, config2, config3;
2588 u32 ocp_data;
2589
2590 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2591 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2592 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2593 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2594
2595 if (enable) {
2596 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2597 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2598 config1 |= sd_rise_time(1);
2599 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2600 config3 |= fast_snr(42);
2601 } else {
2602 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2603 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2604 RX_QUIET_EN);
2605 config1 |= sd_rise_time(7);
2606 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2607 config3 |= fast_snr(511);
2608 }
2609
2610 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2611 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2612 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2613 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2614}
2615
2616static void r8152b_enable_eee(struct r8152 *tp)
2617{
2618 r8152_eee_en(tp, true);
2619 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
2620}
2621
2622static void r8152b_enable_fc(struct r8152 *tp)
2623{
2624 u16 anar;
2625
2626 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2627 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2628 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2629}
2630
d70b1137 2631static void rtl8152_disable(struct r8152 *tp)
2632{
cda9fb01 2633 r8152_aldps_en(tp, false);
d70b1137 2634 rtl_disable(tp);
cda9fb01 2635 r8152_aldps_en(tp, true);
d70b1137 2636}
2637
4349968a 2638static void r8152b_hw_phy_cfg(struct r8152 *tp)
2639{
ef39df8e 2640 r8152b_enable_eee(tp);
2641 r8152_aldps_en(tp, true);
2642 r8152b_enable_fc(tp);
f0cbe0ac 2643
aa66a5f1 2644 set_bit(PHY_RESET, &tp->flags);
4349968a 2645}
2646
ac718b69 2647static void r8152b_exit_oob(struct r8152 *tp)
2648{
db8515ef 2649 u32 ocp_data;
2650 int i;
ac718b69 2651
2652 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2653 ocp_data &= ~RCR_ACPT_ALL;
2654 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2655
00a5e360 2656 rxdy_gated_en(tp, true);
da9bd117 2657 r8153_teredo_off(tp);
ac718b69 2658 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2659 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2660
2661 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2662 ocp_data &= ~NOW_IS_OOB;
2663 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2664
2665 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2666 ocp_data &= ~MCU_BORW_EN;
2667 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2668
2669 for (i = 0; i < 1000; i++) {
2670 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2671 if (ocp_data & LINK_LIST_READY)
2672 break;
8ddfa077 2673 usleep_range(1000, 2000);
ac718b69 2674 }
2675
2676 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2677 ocp_data |= RE_INIT_LL;
2678 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2679
2680 for (i = 0; i < 1000; i++) {
2681 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2682 if (ocp_data & LINK_LIST_READY)
2683 break;
8ddfa077 2684 usleep_range(1000, 2000);
ac718b69 2685 }
2686
2687 rtl8152_nic_reset(tp);
2688
2689 /* rx share fifo credit full threshold */
2690 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2691
a3cc465d 2692 if (tp->udev->speed == USB_SPEED_FULL ||
2693 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2694 /* rx share fifo credit near full threshold */
2695 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2696 RXFIFO_THR2_FULL);
2697 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2698 RXFIFO_THR3_FULL);
2699 } else {
2700 /* rx share fifo credit near full threshold */
2701 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2702 RXFIFO_THR2_HIGH);
2703 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2704 RXFIFO_THR3_HIGH);
2705 }
2706
2707 /* TX share fifo free credit full threshold */
2708 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2709
2710 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2711 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2712 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2713 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2714
c5554298 2715 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2716
2717 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2718
2719 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2720 ocp_data |= TCR0_AUTO_FIFO;
2721 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2722}
2723
2724static void r8152b_enter_oob(struct r8152 *tp)
2725{
45f4a19f 2726 u32 ocp_data;
2727 int i;
ac718b69 2728
2729 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2730 ocp_data &= ~NOW_IS_OOB;
2731 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2732
2733 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2734 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2735 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2736
d70b1137 2737 rtl_disable(tp);
ac718b69 2738
2739 for (i = 0; i < 1000; i++) {
2740 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2741 if (ocp_data & LINK_LIST_READY)
2742 break;
8ddfa077 2743 usleep_range(1000, 2000);
ac718b69 2744 }
2745
2746 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2747 ocp_data |= RE_INIT_LL;
2748 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2749
2750 for (i = 0; i < 1000; i++) {
2751 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2752 if (ocp_data & LINK_LIST_READY)
2753 break;
8ddfa077 2754 usleep_range(1000, 2000);
ac718b69 2755 }
2756
2757 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2758
c5554298 2759 rtl_rx_vlan_en(tp, true);
ac718b69 2760
2761 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2762 ocp_data |= ALDPS_PROXY_MODE;
2763 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2764
2765 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2766 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2767 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2768
00a5e360 2769 rxdy_gated_en(tp, false);
ac718b69 2770
2771 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2772 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2773 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2774}
2775
e6449539 2776static void r8153_aldps_en(struct r8152 *tp, bool enable)
2777{
2778 u16 data;
2779
2780 data = ocp_reg_read(tp, OCP_POWER_CFG);
2781 if (enable) {
2782 data |= EN_ALDPS;
2783 ocp_reg_write(tp, OCP_POWER_CFG, data);
2784 } else {
2785 data &= ~EN_ALDPS;
2786 ocp_reg_write(tp, OCP_POWER_CFG, data);
2787 msleep(20);
2788 }
2789}
2790
2791static void r8153_eee_en(struct r8152 *tp, bool enable)
2792{
2793 u32 ocp_data;
2794 u16 config;
2795
2796 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2797 config = ocp_reg_read(tp, OCP_EEE_CFG);
2798
2799 if (enable) {
2800 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2801 config |= EEE10_EN;
2802 } else {
2803 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2804 config &= ~EEE10_EN;
2805 }
2806
2807 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2808 ocp_reg_write(tp, OCP_EEE_CFG, config);
2809}
2810
43779f8d 2811static void r8153_hw_phy_cfg(struct r8152 *tp)
2812{
2813 u32 ocp_data;
2814 u16 data;
2815
d768c61b 2816 /* disable ALDPS before updating the PHY parameters */
2817 r8153_aldps_en(tp, false);
fb02eb4a 2818
d768c61b 2819 /* disable EEE before updating the PHY parameters */
2820 r8153_eee_en(tp, false);
2821 ocp_reg_write(tp, OCP_EEE_ADV, 0);
43779f8d 2822
2823 if (tp->version == RTL_VER_03) {
2824 data = ocp_reg_read(tp, OCP_EEE_CFG);
2825 data &= ~CTAP_SHORT_EN;
2826 ocp_reg_write(tp, OCP_EEE_CFG, data);
2827 }
2828
2829 data = ocp_reg_read(tp, OCP_POWER_CFG);
2830 data |= EEE_CLKDIV_EN;
2831 ocp_reg_write(tp, OCP_POWER_CFG, data);
2832
2833 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2834 data |= EN_10M_BGOFF;
2835 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2836 data = ocp_reg_read(tp, OCP_POWER_CFG);
2837 data |= EN_10M_PLLOFF;
2838 ocp_reg_write(tp, OCP_POWER_CFG, data);
b4d99def 2839 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
43779f8d 2840
2841 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2842 ocp_data |= PFM_PWM_SWITCH;
2843 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2844
b4d99def 2845 /* Enable LPF corner auto tune */
2846 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
43779f8d 2847
b4d99def 2848 /* Adjust 10M Amplitude */
2849 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2850 sram_write(tp, SRAM_10M_AMP2, 0x0208);
aa66a5f1 2851
af0287ec 2852 r8153_eee_en(tp, true);
2853 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
2854
ef39df8e 2855 r8153_aldps_en(tp, true);
2856 r8152b_enable_fc(tp);
2857
aa66a5f1 2858 set_bit(PHY_RESET, &tp->flags);
43779f8d 2859}
2860
43779f8d 2861static void r8153_first_init(struct r8152 *tp)
2862{
2863 u32 ocp_data;
2864 int i;
2865
00a5e360 2866 rxdy_gated_en(tp, true);
43779f8d 2867 r8153_teredo_off(tp);
2868
2869 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2870 ocp_data &= ~RCR_ACPT_ALL;
2871 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2872
43779f8d 2873 rtl8152_nic_reset(tp);
93fe9b18 2874 rtl_reset_bmu(tp);
43779f8d 2875
2876 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2877 ocp_data &= ~NOW_IS_OOB;
2878 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2879
2880 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2881 ocp_data &= ~MCU_BORW_EN;
2882 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2883
2884 for (i = 0; i < 1000; i++) {
2885 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2886 if (ocp_data & LINK_LIST_READY)
2887 break;
8ddfa077 2888 usleep_range(1000, 2000);
43779f8d 2889 }
2890
2891 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2892 ocp_data |= RE_INIT_LL;
2893 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2894
2895 for (i = 0; i < 1000; i++) {
2896 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2897 if (ocp_data & LINK_LIST_READY)
2898 break;
8ddfa077 2899 usleep_range(1000, 2000);
43779f8d 2900 }
2901
c5554298 2902 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2903
210c4f70 2904 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE;
2905 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
69b4b7a4 2906 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2907
2908 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2909 ocp_data |= TCR0_AUTO_FIFO;
2910 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2911
2912 rtl8152_nic_reset(tp);
2913
2914 /* rx share fifo credit full threshold */
2915 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2916 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2917 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2918 /* TX share fifo free credit full threshold */
2919 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2920
9629e3c0 2921 /* rx aggregation */
43779f8d 2922 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
e90fba8d 2923 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
43779f8d 2924 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2925}
2926
2927static void r8153_enter_oob(struct r8152 *tp)
2928{
2929 u32 ocp_data;
2930 int i;
2931
2932 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2933 ocp_data &= ~NOW_IS_OOB;
2934 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2935
d70b1137 2936 rtl_disable(tp);
93fe9b18 2937 rtl_reset_bmu(tp);
43779f8d 2938
2939 for (i = 0; i < 1000; i++) {
2940 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2941 if (ocp_data & LINK_LIST_READY)
2942 break;
8ddfa077 2943 usleep_range(1000, 2000);
43779f8d 2944 }
2945
2946 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2947 ocp_data |= RE_INIT_LL;
2948 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2949
2950 for (i = 0; i < 1000; i++) {
2951 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2952 if (ocp_data & LINK_LIST_READY)
2953 break;
8ddfa077 2954 usleep_range(1000, 2000);
43779f8d 2955 }
2956
210c4f70 2957 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE;
2958 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
43779f8d 2959
43779f8d 2960 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2961 ocp_data &= ~TEREDO_WAKE_MASK;
2962 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2963
c5554298 2964 rtl_rx_vlan_en(tp, true);
43779f8d 2965
2966 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2967 ocp_data |= ALDPS_PROXY_MODE;
2968 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2969
2970 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2971 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2972 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2973
00a5e360 2974 rxdy_gated_en(tp, false);
43779f8d 2975
2976 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2977 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2978 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2979}
2980
d70b1137 2981static void rtl8153_disable(struct r8152 *tp)
2982{
cda9fb01 2983 r8153_aldps_en(tp, false);
d70b1137 2984 rtl_disable(tp);
93fe9b18 2985 rtl_reset_bmu(tp);
cda9fb01 2986 r8153_aldps_en(tp, true);
b214396f 2987 usb_enable_lpm(tp->udev);
d70b1137 2988}
2989
ac718b69 2990static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2991{
43779f8d 2992 u16 bmcr, anar, gbcr;
ac718b69 2993 int ret = 0;
2994
ac718b69 2995 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2996 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2997 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2998 if (tp->mii.supports_gmii) {
2999 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3000 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3001 } else {
3002 gbcr = 0;
3003 }
ac718b69 3004
3005 if (autoneg == AUTONEG_DISABLE) {
3006 if (speed == SPEED_10) {
3007 bmcr = 0;
3008 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3009 } else if (speed == SPEED_100) {
3010 bmcr = BMCR_SPEED100;
3011 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 3012 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3013 bmcr = BMCR_SPEED1000;
3014 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 3015 } else {
3016 ret = -EINVAL;
3017 goto out;
3018 }
3019
3020 if (duplex == DUPLEX_FULL)
3021 bmcr |= BMCR_FULLDPLX;
3022 } else {
3023 if (speed == SPEED_10) {
3024 if (duplex == DUPLEX_FULL)
3025 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3026 else
3027 anar |= ADVERTISE_10HALF;
3028 } else if (speed == SPEED_100) {
3029 if (duplex == DUPLEX_FULL) {
3030 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3031 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3032 } else {
3033 anar |= ADVERTISE_10HALF;
3034 anar |= ADVERTISE_100HALF;
3035 }
43779f8d 3036 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3037 if (duplex == DUPLEX_FULL) {
3038 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3039 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3040 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3041 } else {
3042 anar |= ADVERTISE_10HALF;
3043 anar |= ADVERTISE_100HALF;
3044 gbcr |= ADVERTISE_1000HALF;
3045 }
ac718b69 3046 } else {
3047 ret = -EINVAL;
3048 goto out;
3049 }
3050
3051 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3052 }
3053
fae56178 3054 if (test_and_clear_bit(PHY_RESET, &tp->flags))
aa66a5f1 3055 bmcr |= BMCR_RESET;
3056
43779f8d 3057 if (tp->mii.supports_gmii)
3058 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3059
ac718b69 3060 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3061 r8152_mdio_write(tp, MII_BMCR, bmcr);
3062
fae56178 3063 if (bmcr & BMCR_RESET) {
aa66a5f1 3064 int i;
3065
aa66a5f1 3066 for (i = 0; i < 50; i++) {
3067 msleep(20);
3068 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3069 break;
3070 }
3071 }
3072
ac718b69 3073out:
ac718b69 3074 return ret;
3075}
3076
d70b1137 3077static void rtl8152_up(struct r8152 *tp)
3078{
3079 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3080 return;
3081
cda9fb01 3082 r8152_aldps_en(tp, false);
d70b1137 3083 r8152b_exit_oob(tp);
cda9fb01 3084 r8152_aldps_en(tp, true);
d70b1137 3085}
3086
ac718b69 3087static void rtl8152_down(struct r8152 *tp)
3088{
6871438c 3089 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3090 rtl_drop_queued_tx(tp);
3091 return;
3092 }
3093
00a5e360 3094 r8152_power_cut_en(tp, false);
cda9fb01 3095 r8152_aldps_en(tp, false);
ac718b69 3096 r8152b_enter_oob(tp);
cda9fb01 3097 r8152_aldps_en(tp, true);
ac718b69 3098}
3099
d70b1137 3100static void rtl8153_up(struct r8152 *tp)
3101{
3102 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3103 return;
3104
b214396f 3105 r8153_u1u2en(tp, false);
cda9fb01 3106 r8153_aldps_en(tp, false);
d70b1137 3107 r8153_first_init(tp);
cda9fb01 3108 r8153_aldps_en(tp, true);
b214396f 3109 r8153_u2p3en(tp, true);
3110 r8153_u1u2en(tp, true);
3111 usb_enable_lpm(tp->udev);
d70b1137 3112}
3113
43779f8d 3114static void rtl8153_down(struct r8152 *tp)
3115{
6871438c 3116 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3117 rtl_drop_queued_tx(tp);
3118 return;
3119 }
3120
b9702723 3121 r8153_u1u2en(tp, false);
b214396f 3122 r8153_u2p3en(tp, false);
b9702723 3123 r8153_power_cut_en(tp, false);
cda9fb01 3124 r8153_aldps_en(tp, false);
43779f8d 3125 r8153_enter_oob(tp);
cda9fb01 3126 r8153_aldps_en(tp, true);
43779f8d 3127}
3128
2dd49e0f 3129static bool rtl8152_in_nway(struct r8152 *tp)
3130{
3131 u16 nway_state;
3132
3133 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3134 tp->ocp_base = 0x2000;
3135 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3136 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3137
3138 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3139 if (nway_state & 0xc000)
3140 return false;
3141 else
3142 return true;
3143}
3144
3145static bool rtl8153_in_nway(struct r8152 *tp)
3146{
3147 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3148
3149 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3150 return false;
3151 else
3152 return true;
3153}
3154
ac718b69 3155static void set_carrier(struct r8152 *tp)
3156{
3157 struct net_device *netdev = tp->netdev;
ce594e98 3158 struct napi_struct *napi = &tp->napi;
ac718b69 3159 u8 speed;
3160
3161 speed = rtl8152_get_speed(tp);
3162
3163 if (speed & LINK_STATUS) {
51d979fa 3164 if (!netif_carrier_ok(netdev)) {
c81229c9 3165 tp->rtl_ops.enable(tp);
ac718b69 3166 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
de9bf29d 3167 netif_stop_queue(netdev);
ce594e98 3168 napi_disable(napi);
ac718b69 3169 netif_carrier_on(netdev);
aa2e0926 3170 rtl_start_rx(tp);
41cec84c 3171 napi_enable(&tp->napi);
de9bf29d 3172 netif_wake_queue(netdev);
3173 netif_info(tp, link, netdev, "carrier on\n");
ac718b69 3174 }
3175 } else {
51d979fa 3176 if (netif_carrier_ok(netdev)) {
ac718b69 3177 netif_carrier_off(netdev);
ce594e98 3178 napi_disable(napi);
c81229c9 3179 tp->rtl_ops.disable(tp);
ce594e98 3180 napi_enable(napi);
de9bf29d 3181 netif_info(tp, link, netdev, "carrier off\n");
ac718b69 3182 }
3183 }
ac718b69 3184}
3185
3186static void rtl_work_func_t(struct work_struct *work)
3187{
3188 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3189
a1f83fee 3190 /* If the device is unplugged or !netif_running(), the workqueue
3191 * doesn't need to wake the device, and could return directly.
3192 */
3193 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3194 return;
3195
9a4be1bd 3196 if (usb_autopm_get_interface(tp->intf) < 0)
3197 return;
3198
ac718b69 3199 if (!test_bit(WORK_ENABLE, &tp->flags))
3200 goto out1;
3201
b5403273 3202 if (!mutex_trylock(&tp->control)) {
3203 schedule_delayed_work(&tp->schedule, 0);
3204 goto out1;
3205 }
3206
216a8349 3207 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
40a82917 3208 set_carrier(tp);
ac718b69 3209
216a8349 3210 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
ac718b69 3211 _rtl8152_set_rx_mode(tp->netdev);
3212
d823ab68 3213 /* don't schedule napi before linking */
216a8349 3214 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3215 netif_carrier_ok(tp->netdev))
d823ab68 3216 napi_schedule(&tp->napi);
aa66a5f1 3217
b5403273 3218 mutex_unlock(&tp->control);
3219
ac718b69 3220out1:
9a4be1bd 3221 usb_autopm_put_interface(tp->intf);
ac718b69 3222}
3223
a028a9e0 3224static void rtl_hw_phy_work_func_t(struct work_struct *work)
3225{
3226 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3227
3228 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3229 return;
3230
3231 if (usb_autopm_get_interface(tp->intf) < 0)
3232 return;
3233
3234 mutex_lock(&tp->control);
3235
3236 tp->rtl_ops.hw_phy_cfg(tp);
3237
aa7e26b6 3238 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
9d21c0d8 3239
a028a9e0 3240 mutex_unlock(&tp->control);
3241
3242 usb_autopm_put_interface(tp->intf);
3243}
3244
5ee3c60c 3245#ifdef CONFIG_PM_SLEEP
3246static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3247 void *data)
3248{
3249 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3250
3251 switch (action) {
3252 case PM_HIBERNATION_PREPARE:
3253 case PM_SUSPEND_PREPARE:
3254 usb_autopm_get_interface(tp->intf);
3255 break;
3256
3257 case PM_POST_HIBERNATION:
3258 case PM_POST_SUSPEND:
3259 usb_autopm_put_interface(tp->intf);
3260 break;
3261
3262 case PM_POST_RESTORE:
3263 case PM_RESTORE_PREPARE:
3264 default:
3265 break;
3266 }
3267
3268 return NOTIFY_DONE;
3269}
3270#endif
3271
ac718b69 3272static int rtl8152_open(struct net_device *netdev)
3273{
3274 struct r8152 *tp = netdev_priv(netdev);
3275 int res = 0;
3276
7e9da481 3277 res = alloc_all_mem(tp);
3278 if (res)
3279 goto out;
3280
9a4be1bd 3281 res = usb_autopm_get_interface(tp->intf);
ca0a7531
GR
3282 if (res < 0)
3283 goto out_free;
9a4be1bd 3284
b5403273 3285 mutex_lock(&tp->control);
3286
7e9da481 3287 tp->rtl_ops.up(tp);
3288
3d55f44f 3289 netif_carrier_off(netdev);
3290 netif_start_queue(netdev);
3291 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 3292
40a82917 3293 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3294 if (res) {
3295 if (res == -ENODEV)
3296 netif_device_detach(tp->netdev);
4a8deae2
HW
3297 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3298 res);
ca0a7531 3299 goto out_unlock;
ac718b69 3300 }
ca0a7531 3301 napi_enable(&tp->napi);
ac718b69 3302
b5403273 3303 mutex_unlock(&tp->control);
3304
9a4be1bd 3305 usb_autopm_put_interface(tp->intf);
5ee3c60c 3306#ifdef CONFIG_PM_SLEEP
3307 tp->pm_notifier.notifier_call = rtl_notifier;
3308 register_pm_notifier(&tp->pm_notifier);
3309#endif
ca0a7531 3310 return 0;
ac718b69 3311
ca0a7531
GR
3312out_unlock:
3313 mutex_unlock(&tp->control);
3314 usb_autopm_put_interface(tp->intf);
3315out_free:
3316 free_all_mem(tp);
7e9da481 3317out:
ac718b69 3318 return res;
3319}
3320
3321static int rtl8152_close(struct net_device *netdev)
3322{
3323 struct r8152 *tp = netdev_priv(netdev);
3324 int res = 0;
3325
5ee3c60c 3326#ifdef CONFIG_PM_SLEEP
3327 unregister_pm_notifier(&tp->pm_notifier);
3328#endif
d823ab68 3329 napi_disable(&tp->napi);
ac718b69 3330 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 3331 usb_kill_urb(tp->intr_urb);
ac718b69 3332 cancel_delayed_work_sync(&tp->schedule);
3333 netif_stop_queue(netdev);
9a4be1bd 3334
3335 res = usb_autopm_get_interface(tp->intf);
53543db5 3336 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
9a4be1bd 3337 rtl_drop_queued_tx(tp);
d823ab68 3338 rtl_stop_rx(tp);
9a4be1bd 3339 } else {
b5403273 3340 mutex_lock(&tp->control);
3341
9a4be1bd 3342 tp->rtl_ops.down(tp);
b5403273 3343
3344 mutex_unlock(&tp->control);
3345
9a4be1bd 3346 usb_autopm_put_interface(tp->intf);
3347 }
ac718b69 3348
7e9da481 3349 free_all_mem(tp);
3350
ac718b69 3351 return res;
3352}
3353
4f1d4d54 3354static void rtl_tally_reset(struct r8152 *tp)
3355{
3356 u32 ocp_data;
3357
3358 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3359 ocp_data |= TALLY_RESET;
3360 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3361}
3362
ac718b69 3363static void r8152b_init(struct r8152 *tp)
3364{
ebc2ec48 3365 u32 ocp_data;
2dd436da 3366 u16 data;
ac718b69 3367
6871438c 3368 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3369 return;
3370
2dd436da 3371 data = r8152_mdio_read(tp, MII_BMCR);
3372 if (data & BMCR_PDOWN) {
3373 data &= ~BMCR_PDOWN;
3374 r8152_mdio_write(tp, MII_BMCR, data);
3375 }
3376
cda9fb01 3377 r8152_aldps_en(tp, false);
d70b1137 3378
ac718b69 3379 if (tp->version == RTL_VER_01) {
3380 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3381 ocp_data &= ~LED_MODE_MASK;
3382 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3383 }
3384
00a5e360 3385 r8152_power_cut_en(tp, false);
ac718b69 3386
ac718b69 3387 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3388 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3389 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3390 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3391 ocp_data &= ~MCU_CLK_RATIO_MASK;
3392 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3393 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3394 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3395 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3396 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3397
4f1d4d54 3398 rtl_tally_reset(tp);
ac718b69 3399
ebc2ec48 3400 /* enable rx aggregation */
ac718b69 3401 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
e90fba8d 3402 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
ac718b69 3403 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3404}
3405
43779f8d 3406static void r8153_init(struct r8152 *tp)
3407{
3408 u32 ocp_data;
2dd436da 3409 u16 data;
43779f8d 3410 int i;
3411
6871438c 3412 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3413 return;
3414
b9702723 3415 r8153_u1u2en(tp, false);
43779f8d 3416
3417 for (i = 0; i < 500; i++) {
3418 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3419 AUTOLOAD_DONE)
3420 break;
3421 msleep(20);
3422 }
3423
3424 for (i = 0; i < 500; i++) {
3425 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3426 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3427 break;
3428 msleep(20);
3429 }
3430
2dd436da 3431 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
3432 tp->version == RTL_VER_05)
3433 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
3434
3435 data = r8152_mdio_read(tp, MII_BMCR);
3436 if (data & BMCR_PDOWN) {
3437 data &= ~BMCR_PDOWN;
3438 r8152_mdio_write(tp, MII_BMCR, data);
3439 }
3440
3441 for (i = 0; i < 500; i++) {
3442 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3443 if (ocp_data == PHY_STAT_LAN_ON)
3444 break;
3445 msleep(20);
3446 }
3447
b214396f 3448 usb_disable_lpm(tp->udev);
b9702723 3449 r8153_u2p3en(tp, false);
43779f8d 3450
65bab84c 3451 if (tp->version == RTL_VER_04) {
3452 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3453 ocp_data &= ~pwd_dn_scale_mask;
3454 ocp_data |= pwd_dn_scale(96);
3455 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3456
3457 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3458 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3459 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3460 } else if (tp->version == RTL_VER_05) {
3461 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3462 ocp_data &= ~ECM_ALDPS;
3463 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3464
fb02eb4a 3465 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3466 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3467 ocp_data &= ~DYNAMIC_BURST;
3468 else
3469 ocp_data |= DYNAMIC_BURST;
3470 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3471 } else if (tp->version == RTL_VER_06) {
65bab84c 3472 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3473 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3474 ocp_data &= ~DYNAMIC_BURST;
3475 else
3476 ocp_data |= DYNAMIC_BURST;
3477 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3478 }
3479
3480 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3481 ocp_data |= EP4_FULL_FC;
3482 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3483
43779f8d 3484 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3485 ocp_data &= ~TIMER11_EN;
3486 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3487
43779f8d 3488 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3489 ocp_data &= ~LED_MODE_MASK;
3490 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3491
65bab84c 3492 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
2b84af94 3493 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
43779f8d 3494 ocp_data |= LPM_TIMER_500MS;
34203e25 3495 else
3496 ocp_data |= LPM_TIMER_500US;
43779f8d 3497 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3498
3499 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3500 ocp_data &= ~SEN_VAL_MASK;
3501 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3502 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3503
65bab84c 3504 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3505
b9702723 3506 r8153_power_cut_en(tp, false);
3507 r8153_u1u2en(tp, true);
43779f8d 3508
4e384ac1 3509 /* MAC clock speed down */
3510 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3512 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3513 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
43779f8d 3514
4f1d4d54 3515 rtl_tally_reset(tp);
b214396f 3516 r8153_u2p3en(tp, true);
43779f8d 3517}
3518
e501139a 3519static int rtl8152_pre_reset(struct usb_interface *intf)
3520{
3521 struct r8152 *tp = usb_get_intfdata(intf);
3522 struct net_device *netdev;
3523
3524 if (!tp)
3525 return 0;
3526
3527 netdev = tp->netdev;
3528 if (!netif_running(netdev))
3529 return 0;
3530
de9bf29d 3531 netif_stop_queue(netdev);
e501139a 3532 napi_disable(&tp->napi);
3533 clear_bit(WORK_ENABLE, &tp->flags);
3534 usb_kill_urb(tp->intr_urb);
3535 cancel_delayed_work_sync(&tp->schedule);
3536 if (netif_carrier_ok(netdev)) {
e501139a 3537 mutex_lock(&tp->control);
3538 tp->rtl_ops.disable(tp);
3539 mutex_unlock(&tp->control);
3540 }
3541
3542 return 0;
3543}
3544
3545static int rtl8152_post_reset(struct usb_interface *intf)
3546{
3547 struct r8152 *tp = usb_get_intfdata(intf);
3548 struct net_device *netdev;
3549
3550 if (!tp)
3551 return 0;
3552
3553 netdev = tp->netdev;
3554 if (!netif_running(netdev))
3555 return 0;
3556
3557 set_bit(WORK_ENABLE, &tp->flags);
3558 if (netif_carrier_ok(netdev)) {
3559 mutex_lock(&tp->control);
3560 tp->rtl_ops.enable(tp);
2c561b2b 3561 rtl_start_rx(tp);
e501139a 3562 rtl8152_set_rx_mode(netdev);
3563 mutex_unlock(&tp->control);
e501139a 3564 }
3565
3566 napi_enable(&tp->napi);
de9bf29d 3567 netif_wake_queue(netdev);
2c561b2b 3568 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
e501139a 3569
7489bdad 3570 if (!list_empty(&tp->rx_done))
3571 napi_schedule(&tp->napi);
e501139a 3572
3573 return 0;
43779f8d 3574}
3575
2dd49e0f 3576static bool delay_autosuspend(struct r8152 *tp)
3577{
3578 bool sw_linking = !!netif_carrier_ok(tp->netdev);
3579 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
3580
3581 /* This means a linking change occurs and the driver doesn't detect it,
3582 * yet. If the driver has disabled tx/rx and hw is linking on, the
3583 * device wouldn't wake up by receiving any packet.
3584 */
3585 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
3586 return true;
3587
3588 /* If the linking down is occurred by nway, the device may miss the
3589 * linking change event. And it wouldn't wake when linking on.
3590 */
3591 if (!sw_linking && tp->rtl_ops.in_nway(tp))
3592 return true;
6a0b76c0 3593 else if (!skb_queue_empty(&tp->tx_queue))
3594 return true;
2dd49e0f 3595 else
3596 return false;
3597}
3598
a9c54ad2 3599static int rtl8152_runtime_suspend(struct r8152 *tp)
ac718b69 3600{
6cc69f2a 3601 struct net_device *netdev = tp->netdev;
3602 int ret = 0;
ac718b69 3603
26afec39 3604 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3605 smp_mb__after_atomic();
3606
8fb28061 3607 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
75dc692e 3608 u32 rcr = 0;
3609
8fb28061 3610 if (delay_autosuspend(tp)) {
26afec39 3611 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3612 smp_mb__after_atomic();
6cc69f2a 3613 ret = -EBUSY;
3614 goto out1;
3615 }
3616
75dc692e 3617 if (netif_carrier_ok(netdev)) {
3618 u32 ocp_data;
3619
3620 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3621 ocp_data = rcr & ~RCR_ACPT_ALL;
3622 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3623 rxdy_gated_en(tp, true);
3624 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
3625 PLA_OOB_CTRL);
3626 if (!(ocp_data & RXFIFO_EMPTY)) {
3627 rxdy_gated_en(tp, false);
3628 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
26afec39 3629 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3630 smp_mb__after_atomic();
75dc692e 3631 ret = -EBUSY;
3632 goto out1;
3633 }
3634 }
3635
8fb28061 3636 clear_bit(WORK_ENABLE, &tp->flags);
3637 usb_kill_urb(tp->intr_urb);
75dc692e 3638
8fb28061 3639 tp->rtl_ops.autosuspend_en(tp, true);
75dc692e 3640
3641 if (netif_carrier_ok(netdev)) {
ce594e98 3642 struct napi_struct *napi = &tp->napi;
3643
3644 napi_disable(napi);
75dc692e 3645 rtl_stop_rx(tp);
3646 rxdy_gated_en(tp, false);
3647 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
ce594e98 3648 napi_enable(napi);
75dc692e 3649 }
6cc69f2a 3650 }
ac718b69 3651
8fb28061 3652out1:
3653 return ret;
3654}
3655
3656static int rtl8152_system_suspend(struct r8152 *tp)
3657{
3658 struct net_device *netdev = tp->netdev;
3659 int ret = 0;
3660
3661 netif_device_detach(netdev);
3662
e3bd1a81 3663 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ce594e98 3664 struct napi_struct *napi = &tp->napi;
3665
ac718b69 3666 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3667 usb_kill_urb(tp->intr_urb);
ce594e98 3668 napi_disable(napi);
8fb28061 3669 cancel_delayed_work_sync(&tp->schedule);
3670 tp->rtl_ops.down(tp);
ce594e98 3671 napi_enable(napi);
ac718b69 3672 }
8fb28061 3673
3674 return ret;
3675}
3676
3677static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3678{
3679 struct r8152 *tp = usb_get_intfdata(intf);
3680 int ret;
3681
3682 mutex_lock(&tp->control);
3683
3684 if (PMSG_IS_AUTO(message))
a9c54ad2 3685 ret = rtl8152_runtime_suspend(tp);
8fb28061 3686 else
3687 ret = rtl8152_system_suspend(tp);
3688
b5403273 3689 mutex_unlock(&tp->control);
3690
6cc69f2a 3691 return ret;
ac718b69 3692}
3693
3694static int rtl8152_resume(struct usb_interface *intf)
3695{
3696 struct r8152 *tp = usb_get_intfdata(intf);
ce594e98 3697 struct net_device *netdev = tp->netdev;
ac718b69 3698
b5403273 3699 mutex_lock(&tp->control);
3700
9a4be1bd 3701 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3702 tp->rtl_ops.init(tp);
a028a9e0 3703 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
ce594e98 3704 netif_device_attach(netdev);
9a4be1bd 3705 }
3706
ce594e98 3707 if (netif_running(netdev) && netdev->flags & IFF_UP) {
9a4be1bd 3708 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
ce594e98 3709 struct napi_struct *napi = &tp->napi;
3710
2609af19 3711 tp->rtl_ops.autosuspend_en(tp, false);
ce594e98 3712 napi_disable(napi);
445f7f4d 3713 set_bit(WORK_ENABLE, &tp->flags);
ce594e98 3714 if (netif_carrier_ok(netdev))
445f7f4d 3715 rtl_start_rx(tp);
ce594e98 3716 napi_enable(napi);
26afec39 3717 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3718 smp_mb__after_atomic();
7489bdad 3719 if (!list_empty(&tp->rx_done))
3720 napi_schedule(&tp->napi);
9a4be1bd 3721 } else {
3722 tp->rtl_ops.up(tp);
ce594e98 3723 netif_carrier_off(netdev);
445f7f4d 3724 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3725 }
40a82917 3726 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3727 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
ce594e98 3728 if (netdev->flags & IFF_UP)
2609af19 3729 tp->rtl_ops.autosuspend_en(tp, false);
923e1ee3 3730 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3731 }
3732
b5403273 3733 mutex_unlock(&tp->control);
3734
ac718b69 3735 return 0;
3736}
3737
7ec2541a 3738static int rtl8152_reset_resume(struct usb_interface *intf)
3739{
3740 struct r8152 *tp = usb_get_intfdata(intf);
3741
3742 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3743 return rtl8152_resume(intf);
3744}
3745
21ff2e89 3746static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3747{
3748 struct r8152 *tp = netdev_priv(dev);
3749
9a4be1bd 3750 if (usb_autopm_get_interface(tp->intf) < 0)
3751 return;
3752
7daed8dc 3753 if (!rtl_can_wakeup(tp)) {
3754 wol->supported = 0;
3755 wol->wolopts = 0;
3756 } else {
3757 mutex_lock(&tp->control);
3758 wol->supported = WAKE_ANY;
3759 wol->wolopts = __rtl_get_wol(tp);
3760 mutex_unlock(&tp->control);
3761 }
b5403273 3762
9a4be1bd 3763 usb_autopm_put_interface(tp->intf);
21ff2e89 3764}
3765
3766static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3767{
3768 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3769 int ret;
3770
7daed8dc 3771 if (!rtl_can_wakeup(tp))
3772 return -EOPNOTSUPP;
3773
9a4be1bd 3774 ret = usb_autopm_get_interface(tp->intf);
3775 if (ret < 0)
3776 goto out_set_wol;
21ff2e89 3777
b5403273 3778 mutex_lock(&tp->control);
3779
21ff2e89 3780 __rtl_set_wol(tp, wol->wolopts);
3781 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3782
b5403273 3783 mutex_unlock(&tp->control);
3784
9a4be1bd 3785 usb_autopm_put_interface(tp->intf);
3786
3787out_set_wol:
3788 return ret;
21ff2e89 3789}
3790
a5ec27c1 3791static u32 rtl8152_get_msglevel(struct net_device *dev)
3792{
3793 struct r8152 *tp = netdev_priv(dev);
3794
3795 return tp->msg_enable;
3796}
3797
3798static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3799{
3800 struct r8152 *tp = netdev_priv(dev);
3801
3802 tp->msg_enable = value;
3803}
3804
ac718b69 3805static void rtl8152_get_drvinfo(struct net_device *netdev,
3806 struct ethtool_drvinfo *info)
3807{
3808 struct r8152 *tp = netdev_priv(netdev);
3809
b0b46c77 3810 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3811 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3812 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3813}
3814
3815static
06144dcf
PR
3816int rtl8152_get_link_ksettings(struct net_device *netdev,
3817 struct ethtool_link_ksettings *cmd)
ac718b69 3818{
3819 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3820 int ret;
ac718b69 3821
3822 if (!tp->mii.mdio_read)
3823 return -EOPNOTSUPP;
3824
8d4a4d72 3825 ret = usb_autopm_get_interface(tp->intf);
3826 if (ret < 0)
3827 goto out;
3828
b5403273 3829 mutex_lock(&tp->control);
3830
06144dcf 3831 ret = mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8d4a4d72 3832
b5403273 3833 mutex_unlock(&tp->control);
3834
8d4a4d72 3835 usb_autopm_put_interface(tp->intf);
3836
3837out:
3838 return ret;
ac718b69 3839}
3840
06144dcf
PR
3841static int rtl8152_set_link_ksettings(struct net_device *dev,
3842 const struct ethtool_link_ksettings *cmd)
ac718b69 3843{
3844 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3845 int ret;
3846
3847 ret = usb_autopm_get_interface(tp->intf);
3848 if (ret < 0)
3849 goto out;
ac718b69 3850
b5403273 3851 mutex_lock(&tp->control);
3852
06144dcf
PR
3853 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
3854 cmd->base.duplex);
aa7e26b6 3855 if (!ret) {
06144dcf
PR
3856 tp->autoneg = cmd->base.autoneg;
3857 tp->speed = cmd->base.speed;
3858 tp->duplex = cmd->base.duplex;
aa7e26b6 3859 }
9a4be1bd 3860
b5403273 3861 mutex_unlock(&tp->control);
3862
9a4be1bd 3863 usb_autopm_put_interface(tp->intf);
3864
3865out:
3866 return ret;
ac718b69 3867}
3868
4f1d4d54 3869static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3870 "tx_packets",
3871 "rx_packets",
3872 "tx_errors",
3873 "rx_errors",
3874 "rx_missed",
3875 "align_errors",
3876 "tx_single_collisions",
3877 "tx_multi_collisions",
3878 "rx_unicast",
3879 "rx_broadcast",
3880 "rx_multicast",
3881 "tx_aborted",
3882 "tx_underrun",
3883};
3884
3885static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3886{
3887 switch (sset) {
3888 case ETH_SS_STATS:
3889 return ARRAY_SIZE(rtl8152_gstrings);
3890 default:
3891 return -EOPNOTSUPP;
3892 }
3893}
3894
3895static void rtl8152_get_ethtool_stats(struct net_device *dev,
3896 struct ethtool_stats *stats, u64 *data)
3897{
3898 struct r8152 *tp = netdev_priv(dev);
3899 struct tally_counter tally;
3900
0b030244 3901 if (usb_autopm_get_interface(tp->intf) < 0)
3902 return;
3903
4f1d4d54 3904 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3905
0b030244 3906 usb_autopm_put_interface(tp->intf);
3907
4f1d4d54 3908 data[0] = le64_to_cpu(tally.tx_packets);
3909 data[1] = le64_to_cpu(tally.rx_packets);
3910 data[2] = le64_to_cpu(tally.tx_errors);
3911 data[3] = le32_to_cpu(tally.rx_errors);
3912 data[4] = le16_to_cpu(tally.rx_missed);
3913 data[5] = le16_to_cpu(tally.align_errors);
3914 data[6] = le32_to_cpu(tally.tx_one_collision);
3915 data[7] = le32_to_cpu(tally.tx_multi_collision);
3916 data[8] = le64_to_cpu(tally.rx_unicast);
3917 data[9] = le64_to_cpu(tally.rx_broadcast);
3918 data[10] = le32_to_cpu(tally.rx_multicast);
3919 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 3920 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 3921}
3922
3923static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3924{
3925 switch (stringset) {
3926 case ETH_SS_STATS:
3927 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3928 break;
3929 }
3930}
3931
df35d283 3932static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3933{
3934 u32 ocp_data, lp, adv, supported = 0;
3935 u16 val;
3936
3937 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3938 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3939
3940 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3941 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3942
3943 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3944 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3945
3946 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3947 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3948
3949 eee->eee_enabled = !!ocp_data;
3950 eee->eee_active = !!(supported & adv & lp);
3951 eee->supported = supported;
3952 eee->advertised = adv;
3953 eee->lp_advertised = lp;
3954
3955 return 0;
3956}
3957
3958static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3959{
3960 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3961
3962 r8152_eee_en(tp, eee->eee_enabled);
3963
3964 if (!eee->eee_enabled)
3965 val = 0;
3966
3967 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3968
3969 return 0;
3970}
3971
3972static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3973{
3974 u32 ocp_data, lp, adv, supported = 0;
3975 u16 val;
3976
3977 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3978 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3979
3980 val = ocp_reg_read(tp, OCP_EEE_ADV);
3981 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3982
3983 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3984 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3985
3986 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3987 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3988
3989 eee->eee_enabled = !!ocp_data;
3990 eee->eee_active = !!(supported & adv & lp);
3991 eee->supported = supported;
3992 eee->advertised = adv;
3993 eee->lp_advertised = lp;
3994
3995 return 0;
3996}
3997
3998static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3999{
4000 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4001
4002 r8153_eee_en(tp, eee->eee_enabled);
4003
4004 if (!eee->eee_enabled)
4005 val = 0;
4006
4007 ocp_reg_write(tp, OCP_EEE_ADV, val);
4008
4009 return 0;
4010}
4011
4012static int
4013rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4014{
4015 struct r8152 *tp = netdev_priv(net);
4016 int ret;
4017
4018 ret = usb_autopm_get_interface(tp->intf);
4019 if (ret < 0)
4020 goto out;
4021
b5403273 4022 mutex_lock(&tp->control);
4023
df35d283 4024 ret = tp->rtl_ops.eee_get(tp, edata);
4025
b5403273 4026 mutex_unlock(&tp->control);
4027
df35d283 4028 usb_autopm_put_interface(tp->intf);
4029
4030out:
4031 return ret;
4032}
4033
4034static int
4035rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4036{
4037 struct r8152 *tp = netdev_priv(net);
4038 int ret;
4039
4040 ret = usb_autopm_get_interface(tp->intf);
4041 if (ret < 0)
4042 goto out;
4043
b5403273 4044 mutex_lock(&tp->control);
4045
df35d283 4046 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 4047 if (!ret)
4048 ret = mii_nway_restart(&tp->mii);
df35d283 4049
b5403273 4050 mutex_unlock(&tp->control);
4051
df35d283 4052 usb_autopm_put_interface(tp->intf);
4053
4054out:
4055 return ret;
4056}
4057
8884f507 4058static int rtl8152_nway_reset(struct net_device *dev)
4059{
4060 struct r8152 *tp = netdev_priv(dev);
4061 int ret;
4062
4063 ret = usb_autopm_get_interface(tp->intf);
4064 if (ret < 0)
4065 goto out;
4066
4067 mutex_lock(&tp->control);
4068
4069 ret = mii_nway_restart(&tp->mii);
4070
4071 mutex_unlock(&tp->control);
4072
4073 usb_autopm_put_interface(tp->intf);
4074
4075out:
4076 return ret;
4077}
4078
efb3dd88 4079static int rtl8152_get_coalesce(struct net_device *netdev,
4080 struct ethtool_coalesce *coalesce)
4081{
4082 struct r8152 *tp = netdev_priv(netdev);
4083
4084 switch (tp->version) {
4085 case RTL_VER_01:
4086 case RTL_VER_02:
4087 return -EOPNOTSUPP;
4088 default:
4089 break;
4090 }
4091
4092 coalesce->rx_coalesce_usecs = tp->coalesce;
4093
4094 return 0;
4095}
4096
4097static int rtl8152_set_coalesce(struct net_device *netdev,
4098 struct ethtool_coalesce *coalesce)
4099{
4100 struct r8152 *tp = netdev_priv(netdev);
4101 int ret;
4102
4103 switch (tp->version) {
4104 case RTL_VER_01:
4105 case RTL_VER_02:
4106 return -EOPNOTSUPP;
4107 default:
4108 break;
4109 }
4110
4111 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4112 return -EINVAL;
4113
4114 ret = usb_autopm_get_interface(tp->intf);
4115 if (ret < 0)
4116 return ret;
4117
4118 mutex_lock(&tp->control);
4119
4120 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4121 tp->coalesce = coalesce->rx_coalesce_usecs;
4122
4123 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4124 r8153_set_rx_early_timeout(tp);
4125 }
4126
4127 mutex_unlock(&tp->control);
4128
4129 usb_autopm_put_interface(tp->intf);
4130
4131 return ret;
4132}
4133
407a471d 4134static const struct ethtool_ops ops = {
ac718b69 4135 .get_drvinfo = rtl8152_get_drvinfo,
ac718b69 4136 .get_link = ethtool_op_get_link,
8884f507 4137 .nway_reset = rtl8152_nway_reset,
a5ec27c1 4138 .get_msglevel = rtl8152_get_msglevel,
4139 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 4140 .get_wol = rtl8152_get_wol,
4141 .set_wol = rtl8152_set_wol,
4f1d4d54 4142 .get_strings = rtl8152_get_strings,
4143 .get_sset_count = rtl8152_get_sset_count,
4144 .get_ethtool_stats = rtl8152_get_ethtool_stats,
efb3dd88 4145 .get_coalesce = rtl8152_get_coalesce,
4146 .set_coalesce = rtl8152_set_coalesce,
df35d283 4147 .get_eee = rtl_ethtool_get_eee,
4148 .set_eee = rtl_ethtool_set_eee,
06144dcf
PR
4149 .get_link_ksettings = rtl8152_get_link_ksettings,
4150 .set_link_ksettings = rtl8152_set_link_ksettings,
ac718b69 4151};
4152
4153static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4154{
4155 struct r8152 *tp = netdev_priv(netdev);
4156 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 4157 int res;
4158
6871438c 4159 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4160 return -ENODEV;
4161
9a4be1bd 4162 res = usb_autopm_get_interface(tp->intf);
4163 if (res < 0)
4164 goto out;
ac718b69 4165
4166 switch (cmd) {
4167 case SIOCGMIIPHY:
4168 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4169 break;
4170
4171 case SIOCGMIIREG:
b5403273 4172 mutex_lock(&tp->control);
ac718b69 4173 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 4174 mutex_unlock(&tp->control);
ac718b69 4175 break;
4176
4177 case SIOCSMIIREG:
4178 if (!capable(CAP_NET_ADMIN)) {
4179 res = -EPERM;
4180 break;
4181 }
b5403273 4182 mutex_lock(&tp->control);
ac718b69 4183 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 4184 mutex_unlock(&tp->control);
ac718b69 4185 break;
4186
4187 default:
4188 res = -EOPNOTSUPP;
4189 }
4190
9a4be1bd 4191 usb_autopm_put_interface(tp->intf);
4192
4193out:
ac718b69 4194 return res;
4195}
4196
69b4b7a4 4197static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4198{
4199 struct r8152 *tp = netdev_priv(dev);
396e2e23 4200 int ret;
69b4b7a4 4201
4202 switch (tp->version) {
4203 case RTL_VER_01:
4204 case RTL_VER_02:
a52ad514
JW
4205 dev->mtu = new_mtu;
4206 return 0;
69b4b7a4 4207 default:
4208 break;
4209 }
4210
396e2e23 4211 ret = usb_autopm_get_interface(tp->intf);
4212 if (ret < 0)
4213 return ret;
4214
4215 mutex_lock(&tp->control);
4216
69b4b7a4 4217 dev->mtu = new_mtu;
4218
210c4f70 4219 if (netif_running(dev)) {
4220 u32 rms = new_mtu + VLAN_ETH_HLEN + CRC_SIZE;
4221
4222 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4223
4224 if (netif_carrier_ok(dev))
4225 r8153_set_rx_early_size(tp);
4226 }
396e2e23 4227
4228 mutex_unlock(&tp->control);
4229
4230 usb_autopm_put_interface(tp->intf);
4231
4232 return ret;
69b4b7a4 4233}
4234
ac718b69 4235static const struct net_device_ops rtl8152_netdev_ops = {
4236 .ndo_open = rtl8152_open,
4237 .ndo_stop = rtl8152_close,
4238 .ndo_do_ioctl = rtl8152_ioctl,
4239 .ndo_start_xmit = rtl8152_start_xmit,
4240 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 4241 .ndo_set_features = rtl8152_set_features,
ac718b69 4242 .ndo_set_rx_mode = rtl8152_set_rx_mode,
4243 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 4244 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 4245 .ndo_validate_addr = eth_validate_addr,
a5e31255 4246 .ndo_features_check = rtl8152_features_check,
ac718b69 4247};
4248
e3fe0b1a 4249static void rtl8152_unload(struct r8152 *tp)
4250{
6871438c 4251 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4252 return;
4253
00a5e360 4254 if (tp->version != RTL_VER_01)
4255 r8152_power_cut_en(tp, true);
e3fe0b1a 4256}
4257
43779f8d 4258static void rtl8153_unload(struct r8152 *tp)
4259{
6871438c 4260 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4261 return;
4262
49be1723 4263 r8153_power_cut_en(tp, false);
43779f8d 4264}
4265
55b65475 4266static int rtl_ops_init(struct r8152 *tp)
c81229c9 4267{
4268 struct rtl_ops *ops = &tp->rtl_ops;
55b65475 4269 int ret = 0;
4270
4271 switch (tp->version) {
4272 case RTL_VER_01:
4273 case RTL_VER_02:
4274 ops->init = r8152b_init;
4275 ops->enable = rtl8152_enable;
4276 ops->disable = rtl8152_disable;
4277 ops->up = rtl8152_up;
4278 ops->down = rtl8152_down;
4279 ops->unload = rtl8152_unload;
4280 ops->eee_get = r8152_get_eee;
4281 ops->eee_set = r8152_set_eee;
2dd49e0f 4282 ops->in_nway = rtl8152_in_nway;
a028a9e0 4283 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
2609af19 4284 ops->autosuspend_en = rtl_runtime_suspend_enable;
43779f8d 4285 break;
4286
55b65475 4287 case RTL_VER_03:
4288 case RTL_VER_04:
4289 case RTL_VER_05:
fb02eb4a 4290 case RTL_VER_06:
55b65475 4291 ops->init = r8153_init;
4292 ops->enable = rtl8153_enable;
4293 ops->disable = rtl8153_disable;
4294 ops->up = rtl8153_up;
4295 ops->down = rtl8153_down;
4296 ops->unload = rtl8153_unload;
4297 ops->eee_get = r8153_get_eee;
4298 ops->eee_set = r8153_set_eee;
2dd49e0f 4299 ops->in_nway = rtl8153_in_nway;
a028a9e0 4300 ops->hw_phy_cfg = r8153_hw_phy_cfg;
2609af19 4301 ops->autosuspend_en = rtl8153_runtime_enable;
c81229c9 4302 break;
4303
4304 default:
55b65475 4305 ret = -ENODEV;
4306 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
c81229c9 4307 break;
4308 }
4309
4310 return ret;
4311}
4312
33928eed 4313static u8 rtl_get_version(struct usb_interface *intf)
4314{
4315 struct usb_device *udev = interface_to_usbdev(intf);
4316 u32 ocp_data = 0;
4317 __le32 *tmp;
4318 u8 version;
4319 int ret;
4320
4321 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
4322 if (!tmp)
4323 return 0;
4324
4325 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
4326 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
4327 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
4328 if (ret > 0)
4329 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
4330
4331 kfree(tmp);
4332
4333 switch (ocp_data) {
4334 case 0x4c00:
4335 version = RTL_VER_01;
4336 break;
4337 case 0x4c10:
4338 version = RTL_VER_02;
4339 break;
4340 case 0x5c00:
4341 version = RTL_VER_03;
4342 break;
4343 case 0x5c10:
4344 version = RTL_VER_04;
4345 break;
4346 case 0x5c20:
4347 version = RTL_VER_05;
4348 break;
4349 case 0x5c30:
4350 version = RTL_VER_06;
4351 break;
4352 default:
4353 version = RTL_VER_UNKNOWN;
4354 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
4355 break;
4356 }
4357
4358 return version;
4359}
4360
ac718b69 4361static int rtl8152_probe(struct usb_interface *intf,
4362 const struct usb_device_id *id)
4363{
4364 struct usb_device *udev = interface_to_usbdev(intf);
33928eed 4365 u8 version = rtl_get_version(intf);
ac718b69 4366 struct r8152 *tp;
4367 struct net_device *netdev;
ebc2ec48 4368 int ret;
ac718b69 4369
33928eed 4370 if (version == RTL_VER_UNKNOWN)
4371 return -ENODEV;
4372
10c32717 4373 if (udev->actconfig->desc.bConfigurationValue != 1) {
4374 usb_driver_set_configuration(udev, 1);
4375 return -ENODEV;
4376 }
4377
4378 usb_reset_device(udev);
ac718b69 4379 netdev = alloc_etherdev(sizeof(struct r8152));
4380 if (!netdev) {
4a8deae2 4381 dev_err(&intf->dev, "Out of memory\n");
ac718b69 4382 return -ENOMEM;
4383 }
4384
ebc2ec48 4385 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 4386 tp = netdev_priv(netdev);
4387 tp->msg_enable = 0x7FFF;
4388
e3ad412a 4389 tp->udev = udev;
4390 tp->netdev = netdev;
4391 tp->intf = intf;
33928eed 4392 tp->version = version;
4393
4394 switch (version) {
4395 case RTL_VER_01:
4396 case RTL_VER_02:
4397 tp->mii.supports_gmii = 0;
4398 break;
4399 default:
4400 tp->mii.supports_gmii = 1;
4401 break;
4402 }
e3ad412a 4403
55b65475 4404 ret = rtl_ops_init(tp);
31ca1dec 4405 if (ret)
4406 goto out;
c81229c9 4407
b5403273 4408 mutex_init(&tp->control);
ac718b69 4409 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
a028a9e0 4410 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
ac718b69 4411
ac718b69 4412 netdev->netdev_ops = &rtl8152_netdev_ops;
4413 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 4414
60c89071 4415 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4416 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 4417 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4418 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 4419 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4420 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 4421 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
ccc39faf 4422 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
c5554298 4423 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4424 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4425 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 4426
19c0f40d 4427 if (tp->version == RTL_VER_01) {
4428 netdev->features &= ~NETIF_F_RXCSUM;
4429 netdev->hw_features &= ~NETIF_F_RXCSUM;
4430 }
4431
7ad24ea4 4432 netdev->ethtool_ops = &ops;
60c89071 4433 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 4434
f77f0aee
JW
4435 /* MTU range: 68 - 1500 or 9194 */
4436 netdev->min_mtu = ETH_MIN_MTU;
4437 switch (tp->version) {
4438 case RTL_VER_01:
4439 case RTL_VER_02:
4440 netdev->max_mtu = ETH_DATA_LEN;
4441 break;
4442 default:
4443 netdev->max_mtu = RTL8153_MAX_MTU;
4444 break;
4445 }
4446
ac718b69 4447 tp->mii.dev = netdev;
4448 tp->mii.mdio_read = read_mii_word;
4449 tp->mii.mdio_write = write_mii_word;
4450 tp->mii.phy_id_mask = 0x3f;
4451 tp->mii.reg_num_mask = 0x1f;
4452 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 4453
464ec10a 4454 switch (udev->speed) {
4455 case USB_SPEED_SUPER:
2b84af94 4456 case USB_SPEED_SUPER_PLUS:
464ec10a 4457 tp->coalesce = COALESCE_SUPER;
4458 break;
4459 case USB_SPEED_HIGH:
4460 tp->coalesce = COALESCE_HIGH;
4461 break;
4462 default:
4463 tp->coalesce = COALESCE_SLOW;
4464 break;
4465 }
4466
aa7e26b6 4467 tp->autoneg = AUTONEG_ENABLE;
4468 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
4469 tp->duplex = DUPLEX_FULL;
4470
9a4be1bd 4471 intf->needs_remote_wakeup = 1;
4472
c81229c9 4473 tp->rtl_ops.init(tp);
a028a9e0 4474 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
ac718b69 4475 set_ethernet_addr(tp);
4476
ac718b69 4477 usb_set_intfdata(intf, tp);
d823ab68 4478 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
ac718b69 4479
ebc2ec48 4480 ret = register_netdev(netdev);
4481 if (ret != 0) {
4a8deae2 4482 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 4483 goto out1;
ac718b69 4484 }
4485
7daed8dc 4486 if (!rtl_can_wakeup(tp))
4487 __rtl_set_wol(tp, 0);
4488
21ff2e89 4489 tp->saved_wolopts = __rtl_get_wol(tp);
4490 if (tp->saved_wolopts)
4491 device_set_wakeup_enable(&udev->dev, true);
4492 else
4493 device_set_wakeup_enable(&udev->dev, false);
4494
4a8deae2 4495 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 4496
4497 return 0;
4498
ac718b69 4499out1:
d823ab68 4500 netif_napi_del(&tp->napi);
ebc2ec48 4501 usb_set_intfdata(intf, NULL);
ac718b69 4502out:
4503 free_netdev(netdev);
ebc2ec48 4504 return ret;
ac718b69 4505}
4506
ac718b69 4507static void rtl8152_disconnect(struct usb_interface *intf)
4508{
4509 struct r8152 *tp = usb_get_intfdata(intf);
4510
4511 usb_set_intfdata(intf, NULL);
4512 if (tp) {
f561de33 4513 struct usb_device *udev = tp->udev;
4514
4515 if (udev->state == USB_STATE_NOTATTACHED)
4516 set_bit(RTL8152_UNPLUG, &tp->flags);
4517
d823ab68 4518 netif_napi_del(&tp->napi);
ac718b69 4519 unregister_netdev(tp->netdev);
a028a9e0 4520 cancel_delayed_work_sync(&tp->hw_phy_work);
c81229c9 4521 tp->rtl_ops.unload(tp);
ac718b69 4522 free_netdev(tp->netdev);
4523 }
4524}
4525
d9a28c5b 4526#define REALTEK_USB_DEVICE(vend, prod) \
4527 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4528 USB_DEVICE_ID_MATCH_INT_CLASS, \
4529 .idVendor = (vend), \
4530 .idProduct = (prod), \
4531 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4532}, \
4533{ \
4534 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4535 USB_DEVICE_ID_MATCH_DEVICE, \
4536 .idVendor = (vend), \
4537 .idProduct = (prod), \
4538 .bInterfaceClass = USB_CLASS_COMM, \
4539 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4540 .bInterfaceProtocol = USB_CDC_PROTO_NONE
4541
ac718b69 4542/* table of devices that work with this driver */
4543static struct usb_device_id rtl8152_table[] = {
d9a28c5b 4544 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4545 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4546 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
1006da19 4547 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
d248cafc 4548 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
4549 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
4550 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
4551 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
4552 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
d065c3c1 4553 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
ac718b69 4554 {}
4555};
4556
4557MODULE_DEVICE_TABLE(usb, rtl8152_table);
4558
4559static struct usb_driver rtl8152_driver = {
4560 .name = MODULENAME,
ebc2ec48 4561 .id_table = rtl8152_table,
ac718b69 4562 .probe = rtl8152_probe,
4563 .disconnect = rtl8152_disconnect,
ac718b69 4564 .suspend = rtl8152_suspend,
ebc2ec48 4565 .resume = rtl8152_resume,
7ec2541a 4566 .reset_resume = rtl8152_reset_resume,
e501139a 4567 .pre_reset = rtl8152_pre_reset,
4568 .post_reset = rtl8152_post_reset,
9a4be1bd 4569 .supports_autosuspend = 1,
a634782f 4570 .disable_hub_initiated_lpm = 1,
ac718b69 4571};
4572
b4236daa 4573module_usb_driver(rtl8152_driver);
ac718b69 4574
4575MODULE_AUTHOR(DRIVER_AUTHOR);
4576MODULE_DESCRIPTION(DRIVER_DESC);
4577MODULE_LICENSE("GPL");
c961e877 4578MODULE_VERSION(DRIVER_VERSION);